diff options
Diffstat (limited to 'arch')
117 files changed, 3454 insertions, 1441 deletions
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 41408c2b460..ed6c5dfa584 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -63,7 +63,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { r0 = 2; r2 = (unsigned int)images->ft_addr; } else { diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ebb19272708..504abca0b71 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -636,7 +636,6 @@ config ARCH_BCMSTB select DM select GPIO_EXTRA_HEADER select OF_CONTROL - select OF_PRIOR_STAGE imply CMD_DM help This enables support for Broadcom ARM-based set-top box @@ -1028,6 +1027,7 @@ config ARCH_SUNXI select DM select DM_ETH select DM_GPIO + select DM_I2C if I2C select DM_KEYBOARD select DM_MMC if MMC select DM_SCSI if SCSI diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 07033acb5c1..67764ccf66a 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) +#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff; rndoff = (usec % 10) ? 1 : 0; @@ -110,5 +110,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - return CONFIG_STV0991_HZ; + return CONFIG_SYS_HZ; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 41f3e95019b..9820d3290e7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -54,7 +54,8 @@ int ls_gic_rd_tables_init(void *blob) lpi_base.start = addr; lpi_base.end = addr + size - 1; - ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false); + ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, + 0, NULL, 0); if (ret) { debug("%s: failed to add reserved memory\n", __func__); return ret; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8a382d1539..b549f3c8b89 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -638,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-libretech-all-h5-cc.dtb \ sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-nanopi-r1s-h5.dtb \ sun50i-h5-orangepi-zero-plus.dtb \ sun50i-h5-orangepi-pc2.dtb \ sun50i-h5-orangepi-prime.dtb \ @@ -821,7 +822,9 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb + imx6ul-pico-pi.dtb \ + imx6ul-kontron-n631x-s.dtb \ + imx6ull-kontron-n641x-s.dtb dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ @@ -876,6 +879,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ + imx8mm-kontron-n801x-s.dtb \ + imx8mm-kontron-n801x-s-lvds.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ @@ -1143,6 +1148,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb +dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb + dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb targets += $(dtb-y) diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi index 92218243904..44b6268ae32 100644 --- a/arch/arm/dts/am33xx-clocks.dtsi +++ b/arch/arm/dts/am33xx-clocks.dtsi @@ -167,7 +167,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -207,7 +207,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -223,7 +223,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { @@ -247,7 +247,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { @@ -264,7 +264,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; dpll_per_m2_ck: dpll_per_m2_ck@4ac { diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi index d0c0dfa4ec4..b1127b5b91f 100644 --- a/arch/arm/dts/am43xx-clocks.dtsi +++ b/arch/arm/dts/am43xx-clocks.dtsi @@ -199,7 +199,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -245,7 +245,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck { @@ -263,7 +263,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck { @@ -281,7 +281,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck { @@ -300,7 +300,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; dpll_per_m2_ck: dpll_per_m2_ck { @@ -583,7 +583,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck { diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 2615b8c748c..fec34609cf8 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -335,14 +335,14 @@ /* * The 128 MiB address range [0xe8000000-0xf0000000] is * dedicated for PCIe and can be assigned to 8 windows - * with size a power of two. Use one 64 KiB window for + * with size a power of two. Use one 1 MiB window for * IO at the end and the remaining seven windows * (totaling 127 MiB) for MEM. */ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */ - 0x81000000 0 0xefff0000 - 0 0xefff0000 0 0x10000>; /* Port 0 IO*/ + 0x81000000 0 0xeff00000 + 0 0xeff00000 0 0x100000>; /* Port 0 IO*/ }; }; }; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 510fb84d5a9..9e714c33e90 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -243,6 +243,9 @@ &cp1_mdio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_smi_pins>; + cp1_ge_phy0: ethernet-phy@3 { reg = <1>; }; @@ -292,33 +295,24 @@ /* * MPP Bus: * [0-5] TDM - * [6,7] CP1_UART 0 - * [8] CP1 10G SFP LOS - * [9] CP1 10G PHY RESET - * [10] CP1 10G SFP TX Disable - * [11] CP1 10G SFP Mode - * [12] SPI1 CS1n - * [13] SPI1 MISO (TDM and SPI ROM shared) - * [14] SPI1 CS0n - * [15] SPI1 MOSI (TDM and SPI ROM shared) - * [16] SPI1 CLK (TDM and SPI ROM shared) - * [24] CP1 2.5G SFP TX Disable - * [26] CP0 10G SFP TX Fault - * [27] CP0 10G SFP Mode - * [28] CP0 10G SFP LOS - * [29] CP0 10G SFP TX Disable - * [30] USB Over current indication - * [31] 10G Port 0 phy reset + * [27-28] SMI + * [29-30] CP1 MSS I2C + * [6-26, 31] GPIO * [32-62] = 0xff: Keep default CP1_shared_pins: */ /* 0 1 2 3 4 5 6 7 8 9 */ - pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 - 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff - 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 - 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 + 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + cp1_smi_pins: cp1-smi-pins { + marvell,pins = < 27 28 >; + marvell,function = <8>; + }; }; &ap_spi0 { diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi index bc4b3483a6b..869adb9dada 100644 --- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi +++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi @@ -7,7 +7,7 @@ soc { u-boot,dm-pre-reloc; - aips@50000000 { + bus@50000000 { u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/imx53-usbarmory.dts b/arch/arm/dts/imx53-usbarmory.dts index f34993a490e..433b62e7367 100644 --- a/arch/arm/dts/imx53-usbarmory.dts +++ b/arch/arm/dts/imx53-usbarmory.dts @@ -91,6 +91,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; + broken-cd; status = "okay"; }; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index ed341cfd9d0..8536f59f59e 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -222,7 +222,7 @@ clock-names = "core_clk", "mem_iface_clk"; }; - aips@50000000 { /* AIPS1 */ + bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -654,7 +654,7 @@ }; }; - aips@60000000 { /* AIPS2 */ + bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6-apalis-u-boot.dtsi b/arch/arm/dts/imx6-apalis-u-boot.dtsi new file mode 100644 index 00000000000..95e7e022b9a --- /dev/null +++ b/arch/arm/dts/imx6-apalis-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Foundries.IO + */ + +#include "imx6qdl-u-boot.dtsi" + +&wdog1 { + status = "okay"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi index f0607eb41df..ae5aad6b9ef 100644 --- a/arch/arm/dts/imx6dl.dtsi +++ b/arch/arm/dts/imx6dl.dtsi @@ -84,7 +84,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc"; }; @@ -100,7 +100,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi index aa660b5aeb6..ced4dacc735 100644 --- a/arch/arm/dts/imx6q-display5-u-boot.dtsi +++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi @@ -23,7 +23,7 @@ soc { u-boot,dm-pre-reloc; - aips-bus@2100000 { + bus@2100000 { u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi index 71543a4a684..c37484dce35 100644 --- a/arch/arm/dts/imx6q.dtsi +++ b/arch/arm/dts/imx6q.dtsi @@ -162,7 +162,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2000000 { /* AIPS1 */ + bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { #address-cells = <1>; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 904b2283063..77ac103c2d9 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -137,7 +137,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { @@ -550,6 +551,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -720,6 +723,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index ffed4fb550b..98c81e9c9b5 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -146,7 +146,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator@3 { @@ -620,6 +621,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -815,6 +818,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 diff --git a/arch/arm/dts/imx6qdl-gw552x.dtsi b/arch/arm/dts/imx6qdl-gw552x.dtsi index f6742e51315..b853399aec6 100644 --- a/arch/arm/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/dts/imx6qdl-gw552x.dtsi @@ -121,6 +121,15 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_usb_h1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &gpmi { @@ -390,9 +399,13 @@ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; }; + status = "okay"; +}; &usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -507,6 +520,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index 5da19756e03..1e95267c974 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -221,7 +221,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index b5ed2d83c17..286c7a9924c 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -176,7 +176,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { @@ -593,6 +594,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; status = "okay"; }; @@ -753,6 +756,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi index 2537288627d..8fd8fdb5147 100644 --- a/arch/arm/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -120,7 +120,8 @@ regulator-name = "usb_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -380,6 +381,8 @@ &usbh1 { vbus-supply = <®_usb_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -560,6 +563,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi index 1279cc2338b..f74af6c423e 100644 --- a/arch/arm/dts/imx6qdl-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-u-boot.dtsi @@ -13,14 +13,14 @@ u-boot,dm-spl; u-boot,dm-pre-reloc; - aips-bus@2000000 { + bus@2000000 { u-boot,dm-spl; spba-bus@2000000 { u-boot,dm-spl; }; }; - aips-bus@2100000 { + bus@2100000 { u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index e4daf150881..1cdb498c720 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -283,7 +283,7 @@ status = "disabled"; }; - aips-bus@2000000 { /* AIPS1 */ + bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -913,7 +913,7 @@ }; }; - aips-bus@2100000 { /* AIPS2 */ + bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi index 5f51f8e5c1f..93b89dc1f53 100644 --- a/arch/arm/dts/imx6qp.dtsi +++ b/arch/arm/dts/imx6qp.dtsi @@ -18,7 +18,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2100000 { + bus@2100000 { pre1: pre@21c8000 { compatible = "fsl,imx6qp-pre"; reg = <0x021c8000 0x1000>; diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi index cc9572ea286..37e341c6c35 100644 --- a/arch/arm/dts/imx6sl.dtsi +++ b/arch/arm/dts/imx6sl.dtsi @@ -130,7 +130,7 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; - aips1: aips-bus@02000000 { + aips1: bus@02000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -751,7 +751,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: bus@02100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi index 349c47a03a2..ebc6d9d2c98 100644 --- a/arch/arm/dts/imx6sll.dtsi +++ b/arch/arm/dts/imx6sll.dtsi @@ -176,7 +176,7 @@ arm,data-latency = <4 2 3>; }; - aips1: aips-bus@02000000 { + aips1: bus@02000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -682,7 +682,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: bus@02100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi index 531a52c1e98..8d2d396ad13 100644 --- a/arch/arm/dts/imx6sx.dtsi +++ b/arch/arm/dts/imx6sx.dtsi @@ -235,7 +235,7 @@ status = "disabled"; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -830,7 +830,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -1188,7 +1188,7 @@ }; }; - aips3: aips-bus@2200000 { + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi new file mode 100644 index 00000000000..d3f013c58cf --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ul-kontron-n631x-s.dts b/arch/arm/dts/imx6ul-kontron-n631x-s.dts new file mode 100644 index 00000000000..407d2b1dab9 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n631x-s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +/dts-v1/; + +#include "imx6ul-kontron-n631x-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" + +/ { + model = "Kontron N631X S"; + compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som", + "fsl,imx6ul"; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi b/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi new file mode 100644 index 00000000000..9a1179814b7 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +#include "imx6ul.dtsi" +#include "imx6ul-kontron-n6x1x-som-common.dtsi" + +/ { + model = "Kontron N631X SOM"; + compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul"; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi new file mode 100644 index 00000000000..39cc6d05d3f --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#if defined(CONFIG_FIT) + +/ { + binman: binman { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "SPL"; + }; + + uboot: blob-ext@2 { + offset = <0x11000>; + filename = "u-boot.img"; + }; + }; +}; + +#endif /* CONFIG_FIT */ + +/* + * To make the PHYs work, we need to set the reset pin once. Afterwards + * in Linux we can't assign the shared reset GPIO to the PHYs, as this + * would cause Linux to reset both PHYs every time one of them gets + * reinitialized. + * + * Also we disable the second ethernet as it currently doesn't work with + * the devicetree setup in U-Boot. + */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec2 { + status = "disabled"; + /delete-property/ phy-handle; + /delete-node/ mdio; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts new file mode 100644 index 00000000000..84d8a717ab5 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6ul-kontron-n6x1x-som.dtsi" + +/ { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "debug-led1"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "debug-led2"; + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "debug-led3"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm8 0 5000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_adc: regulator-vref-adc { + compatible = "regulator-fixed"; + regulator-name = "vref-adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + num-channels = <3>; + vref-supply = <®_vref_adc>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32e61w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <8192>; + address-width = <16>; + }; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + rs485-rts-active-low; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 + >; + }; + + pinctrl_enet2_mdio: enet2mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 + /* + * mux unused RTS to make sure it doesn't cause + * any interrupts when it is undefined + */ + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi new file mode 100644 index 00000000000..4682a79f5b2 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "debug-led1"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "debug-led2"; + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "debug-led3"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm8 0 5000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_adc: regulator-vref-adc { + compatible = "regulator-fixed"; + regulator-name = "vref-adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + num-channels = <3>; + vref-supply = <®_vref_adc>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32e61w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <8192>; + address-width = <16>; + }; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + rs485-rts-active-low; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 + >; + }; + + pinctrl_enet2_mdio: enet2mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 + /* + * mux unused RTS to make sure it doesn't cause + * any interrupts when it is undefined + */ + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi new file mode 100644 index 00000000000..e9ec6b78919 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@80000000 { + reg = <0x80000000 0x10000000>; + device_type = "memory"; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec2 { + phy-mode = "rmii"; + status = "disabled"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_out>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + >; + }; + + pinctrl_enet1_mdio: enet1mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_reset_out: rstoutgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 5644b0f34d5..ad9cb37db77 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -206,7 +206,7 @@ status = "disabled"; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -763,7 +763,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi b/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi new file mode 100644 index 00000000000..d3f013c58cf --- /dev/null +++ b/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ull-kontron-n641x-s.dts b/arch/arm/dts/imx6ull-kontron-n641x-s.dts new file mode 100644 index 00000000000..01aeea40853 --- /dev/null +++ b/arch/arm/dts/imx6ull-kontron-n641x-s.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ull-kontron-n641x-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" + +/ { + model = "Kontron N641X S"; + compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som", + "fsl,imx6ull"; +}; diff --git a/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi b/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi new file mode 100644 index 00000000000..8a64aa9a275 --- /dev/null +++ b/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ull.dtsi" +#include "imx6ul-kontron-n6x1x-som-common.dtsi" + +/ { + model = "Kontron N641X SOM"; + compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull"; +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 22e4a307fa5..f224e20bda9 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -44,7 +44,7 @@ / { soc { - aips3: aips-bus@2200000 { + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index 967023fde19..483824fc06e 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -340,7 +340,7 @@ <0x31006000 0x2000>; }; - aips1: aips-bus@30000000 { + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -647,7 +647,7 @@ }; }; - aips2: aips-bus@30400000 { + aips2: bus@30400000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -739,7 +739,7 @@ }; }; - aips3: aips-bus@30800000 { + aips3: bus@30800000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi new file mode 100644 index 00000000000..12065935e49 --- /dev/null +++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + binman: binman { + multiple-images; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_uart3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart3 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl2.bin"; + }; + }; + + fip { + description = "Trusted Firmware FIP"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x40310000>; + + fip_blob: blob-ext{ + filename = "fip.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf", "fip"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts b/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts new file mode 100644 index 00000000000..4d0ef469975 --- /dev/null +++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-cl-iot-gate.dts" diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi index 3226a244a97..00927c15744 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi @@ -217,18 +217,6 @@ }; }; - fip { - description = "Trusted Firmware FIP"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x40310000>; - - fip_blob: blob-ext{ - filename = "fip.bin"; - }; - }; - fdt { description = "NAME"; type = "flat_dt"; @@ -246,7 +234,7 @@ conf { description = "NAME"; firmware = "uboot"; - loadables = "atf", "fip"; + loadables = "atf"; fdt = "fdt"; }; }; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts b/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts new file mode 100644 index 00000000000..dd1addea708 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm-kontron-n801x-s.dts" + +/ { + model = "Kontron i.MX8MM N801X S LVDS"; + compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */ + power-supply = <®_vdd_24v>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + status = "okay"; + }; + + reg_panel_pwr: regpanel-pwr { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_pwr"; + regulator-always-on; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_rst: regpanel-rst { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_rst"; + regulator-always-on; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_stby: regpanel-stby { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_stby"; + regulator-always-on; + gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_hinv: regpanel-hinv { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_hinv"; + regulator-always-on; + gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_vinv: regpanel-vinv { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_vinv"; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_24v: regulator-24v { + compatible = "regulator-fixed"; + regulator-name = "reg-vdd-24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + gt911@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio3>; + interrupts = <22 8>; + reset-gpios = <&gpio3 23 0>; + irq-gpios = <&gpio3 22 0>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */ + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */ + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi new file mode 100644 index 00000000000..5e368a61bc9 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm-u-boot.dtsi" + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + binman: binman { + multiple-images; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&fec1 { + phy-mode = "rgmii-rxid"; +}; + +&i2c1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&i2c2 { + status = "okay"; + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + /* Disable Pullup for SD_VSEL */ + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41 + >; +}; + +&pinctrl_uart3 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pca9450 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&ecspi1 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart3 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "spl.bin"; + }; + + uboot: blob-ext@2 { + offset = <0x57c00>; + filename = "u-boot.itb"; + }; + }; + + u-boot-update { + filename = "firmware-update.itb"; + + fit { + description = "Configuration for firmware update file"; + + images { + flash-bin { + description = "U-Boot flash image"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compress = "none"; + load = <0>; /* unused */ + + blob { + filename = "flash.bin"; + }; + + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s.dts b/arch/arm/dts/imx8mm-kontron-n801x-s.dts new file mode 100644 index 00000000000..c796d144e22 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-s.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n801x-som.dtsi" +#include <dt-bindings/net/mscc-phy-vsc8531.h> + +/ { + model = "Kontron i.MX8MM N801X S"; + compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + aliases { + ethernet1 = &usbnet; + }; + + /* fixed crystal dedicated to mcp2515 */ + osc_can: clock-osc-can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "osc-can"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led1 { + label = "led1"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "led3"; + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + }; + + led4 { + label = "led4"; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + }; + + led5 { + label = "led5"; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + }; + + led6 { + label = "led6"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible = "regulator-fixed"; + regulator-name = "rst-usb-eth2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth2>; + gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_vdd_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&osc_can>; + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rgmii-rxid"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.0570"; + reg = <0>; + reset-assert-us = <100>; + reset-deassert-us = <100>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>; + vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>; + vsc8531,led-0-combine-disable; + }; + }; +}; + +&gpio4 { + dsi_mux_sel: dsi_mux_sel { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "dsi-mux-sel"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_sel>; + }; + + dsi_mux_oe { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-high; + line-name = "dsi-mux-oe"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_oe>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_dsi_sel: dsiselgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + >; + }; + + pinctrl_dsi_oe: dsioegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi new file mode 100644 index 00000000000..c3418d263eb --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "Kontron i.MX8MM N801X SoM"; + compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg = <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi index 1a15d6a2add..76702438515 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi @@ -3,59 +3,7 @@ * Copyright 2021 Gateworks Corporation */ -#include "imx8mm-u-boot.dtsi" - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&i2c2 { - u-boot,dm-spl; -}; - -&pinctrl_i2c2 { - u-boot,dm-spl; -}; +#include "imx8mm-venice-u-boot.dtsi" &fec1 { phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; @@ -63,6 +11,10 @@ phy-reset-post-delay = <1>; }; +&pinctrl_fec1 { + u-boot,dm-spl; +}; + &{/soc@0/bus@30800000/i2c@30a20000/pmic@69} { u-boot,dm-spl; }; @@ -70,3 +22,7 @@ &{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} { u-boot,dm-spl; }; + +&pinctrl_pmic { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index cc850e7dce3..f182a816b57 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -282,65 +282,83 @@ reg = <0x69>; regulators { + /* vdd_0p95: DRAM/GPU/VPU */ buck1 { - regulator-name = "vdd_0p95"; - regulator-min-microvolt = <805000>; + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-max-microamp = <2500000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_soc */ buck2 { - regulator-name = "vdd_soc"; - regulator-min-microvolt = <805000>; + regulator-name = "buck2"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; - regulator-max-microamp = <1000000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_arm */ buck3_reg: buck3 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <805000>; + regulator-name = "buck3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-max-microamp = <2200000>; - regulator-boot-on; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; + regulator-always-on; }; + /* vdd_1p8 */ buck4 { - regulator-name = "vdd_1p8"; + regulator-name = "buck4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-max-microamp = <500000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; + regulator-always-on; }; + /* nvcc_snvs_1p8 */ ldo1 { - regulator-name = "nvcc_snvs_1p8"; + regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-max-microamp = <300000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_snvs_0p8 */ ldo2 { - regulator-name = "vdd_snvs_0p8"; + regulator-name = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_0p9 */ ldo3 { - regulator-name = "vdd_0p95"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; + regulator-name = "ldo3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_1p8 */ ldo4 { - regulator-name = "vdd_1p8"; + regulator-name = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; + regulator-always-on; }; }; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index a5adf27649d..a801ee1deb9 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -3,67 +3,7 @@ * Copyright 2020 Gateworks Corporation */ -#include "imx8mm-u-boot.dtsi" - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&usdhc2 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&i2c2 { - u-boot,dm-spl; -}; - -&pinctrl_i2c2 { - u-boot,dm-spl; -}; +#include "imx8mm-venice-u-boot.dtsi" &fec1 { phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; @@ -71,6 +11,10 @@ phy-reset-post-delay = <1>; }; +&pinctrl_fec1 { + u-boot,dm-spl; +}; + &{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index 124e1e4e704..d5cdbb7f994 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -1041,15 +1041,3 @@ >; }; }; - -&cpu_alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; -}; - -&cpu_crit0 { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index 361ddaa78fe..d0e5d6c5b63 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -3,59 +3,7 @@ * Copyright 2021 Gateworks Corporation */ -#include "imx8mm-u-boot.dtsi" - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&i2c2 { - u-boot,dm-spl; -}; - -&pinctrl_i2c2 { - u-boot,dm-spl; -}; +#include "imx8mm-venice-u-boot.dtsi" &fec1 { phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 29488216442..07e436be95e 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -913,15 +913,3 @@ >; }; }; - -&cpu_alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; -}; - -&cpu_crit0 { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; -}; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index fb0756d6e19..ac2a4b69d3c 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -160,7 +160,7 @@ &fec1 { fsl,magic-packet; phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_ethphy>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec1>; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index d61346da303..afb3995482e 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -79,7 +79,9 @@ }; }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000"; @@ -146,4 +148,19 @@ }; }; }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + }; + + uboot: blob-ext@2 { + filename = "u-boot.itb"; + offset = <0x58000>; + }; + }; }; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi new file mode 100644 index 00000000000..64dddce6488 --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Chao Zeng <chao.zeng@siemens.com> + * + * U-Boot bits of the IOT2050 Advanced PG2 variants + * (downgrade of usb0 to USB 2.0 mode) + */ + +&serdes0 { + status = "disabled"; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ + /delete-property/ phys; + /delete-property/ phy-names; +}; + +&usb0 { + maximum-speed = "high-speed"; + /delete-property/ snps,dis-u1-entry-quirk; + /delete-property/ snps,dis-u2-entry-quirk; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi index c25bce7339b..e7e0ca41597 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi @@ -44,8 +44,10 @@ phy-names = "usb3-phy"; }; -&usb0_phy { +&usb0 { maximum-speed = "super-speed"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; }; + +#include "k3-am65-iot2050-common-pg2-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index 88c36fcf438..286e25f3794 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -35,7 +35,7 @@ &cbass_main { u-boot,dm-spl; - main-navss { + main_navss: bus@30800000 { u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index aaa8ae2235d..ef706486dc6 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -967,7 +967,7 @@ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; clock-names = "clk_sfc", "hclk_sfc"; pinctrl-names = "default"; - pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; power-domains = <&power PX30_PD_MMC_NAND>; status = "disabled"; }; @@ -1953,7 +1953,7 @@ <1 RK_PA1 3 &pcfg_pull_none>; }; - sfc_cs: sfc-cs { + sfc_cs0: sfc-cs0 { rockchip,pins = <1 RK_PA4 3 &pcfg_pull_none>; }; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 741e8dd9352..bffaa3edf33 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -18,8 +18,18 @@ }; }; +/* U-Boot clk driver for px30 cannot set GPU_CLK */ &cru { u-boot,dm-pre-reloc; + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <17000000>; }; &dmc { @@ -70,7 +80,7 @@ u-boot,dm-pre-reloc; }; -&spi_flash { +&{/sfc@ff3a0000/flash@0} { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts index 6f91f5040b0..4e3dceecbec 100644 --- a/arch/arm/dts/rk3326-odroid-go2.dts +++ b/arch/arm/dts/rk3326-odroid-go2.dts @@ -618,18 +618,18 @@ }; &sfc { + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; status = "okay"; - spi_flash: xt25f128b@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <108000000>; spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; + spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d8a125b0735..038cd73c031 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -671,6 +671,14 @@ status = "disabled"; }; + pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; + status = "disabled"; + }; + rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index ba9b3cd03ce..78facde2b5b 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -313,6 +313,7 @@ clocks = <&rcc 1 CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -325,6 +326,7 @@ clocks = <&rcc 1 CLK_I2C2>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -337,6 +339,7 @@ clocks = <&rcc 1 CLK_I2C3>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -349,6 +352,7 @@ clocks = <&rcc 1 CLK_I2C4>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index ed6857512f7..dbfebf07f28 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -124,6 +124,7 @@ <32>; resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; clocks = <&rcc I2C1_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -136,6 +137,7 @@ <34>; resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; clocks = <&rcc I2C2_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -148,6 +150,7 @@ <73>; resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; clocks = <&rcc I2C3_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -395,6 +398,7 @@ <96>; resets = <&rcc STM32H7_APB4_RESET(I2C4)>; clocks = <&rcc I2C4_CK>; + i2c-analog-filter; status = "disabled"; }; diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts new file mode 100644 index 00000000000..55bcdf8d1a0 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn> + * + * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: + * Copyright (C) 2017 Antony Antony <antony@phenome.org> + * Copyright (C) 2016 ARM Ltd. + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "FriendlyARM NanoPi R1S H5"; + compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; + + aliases { + ethernet0 = &emac; + ethernet1 = &rtl8189etv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + r-gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "microchip,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index 5f69d0fd6e6..5ba13dc62bc 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -34,7 +34,7 @@ compatible = "simple-bus"; ranges; - aips0: aips-bus@40000000 { + aips0: bus@40000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -158,7 +158,7 @@ }; }; - aips1: aips-bus@40080000 { + aips1: bus@40080000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 5d775902bbe..79e3b8c7d9f 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -78,6 +78,18 @@ #define CM_CLKSEL_DPLL_N_SHIFT 0 #define CM_CLKSEL_DPLL_N_MASK 0x7F +/* CM_SSC_DELTAM_DPLL */ +#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0 +#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0) +#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18 +#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18) + +/* CM_SSC_MODFREQ_DPLL */ +#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0 +#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0) +#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7 +#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8) + struct dpll_params { u32 m; u32 n; diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index ea2f113f98d..df392a27149 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -11,7 +11,7 @@ #include <asm/arch/sys_proto.h> -/* CONFIG_REG_0 */ +/* CFG REG_0 */ #define CFG_REG_0_OFFSET 0xC #define CFG_REG_ROM_READ_SHIFT 1 #define CFG_REG_ROM_READ_MASK (1 << 1) @@ -22,18 +22,18 @@ #define CFG_REG_ROM_READ_START (1 << 1) #define CFG_REG_ROM_READ_END (0 << 1) -/* CONFIG_REG_2 */ +/* CFG REG_2 */ #define CFG_REG_2_OFFSET 0x14 #define CFG_REG_REFCLK_PERIOD_SHIFT 0 #define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) #define CFG_REG_REFCLK_PERIOD 0x2EF -/* CONFIG_REG_8 */ +/* CFG REG_8 */ #define CFG_REG_8_OFFSET 0x2C #define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA #define CFG_IODELAY_LOCK_KEY 0x0000AAAB -/* CONFIG_REG_3/4 */ +/* CFG REG_3/4 */ #define CFG_REG_3_OFFSET 0x18 #define CFG_REG_4_OFFSET 0x1C #define CFG_REG_DLY_CNT_SHIFT 16 diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 6c59033f03a..399f19ad21e 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -14,7 +14,7 @@ #define APLL_HZ (816 * MHz) #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (1000 * MHz) -#define PPLL_HZ (100 * MHz) +#define PPLL_HZ (200 * MHz) /* RK3568 pll id */ enum rk3568_pll_id { diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index cd27472ad7e..f1d5667c32b 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,7 +36,7 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_STV0991_HZ 1000 -#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) #endif diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h deleted file mode 100644 index cac5c5faf05..00000000000 --- a/arch/arm/include/asm/arch-sunxi/ccu.h +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Amarula Solutions. - * Author: Jagan Teki <jagan@amarulasolutions.com> - */ - -#ifndef _ASM_ARCH_CCU_H -#define _ASM_ARCH_CCU_H - -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -#endif - -/** - * enum ccu_flags - ccu clock/reset flags - * - * @CCU_CLK_F_IS_VALID: is given clock gate is valid? - * @CCU_RST_F_IS_VALID: is given reset control is valid? - */ -enum ccu_flags { - CCU_CLK_F_IS_VALID = BIT(0), - CCU_RST_F_IS_VALID = BIT(1), -}; - -/** - * struct ccu_clk_gate - ccu clock gate - * @off: gate offset - * @bit: gate bit - * @flags: ccu clock gate flags - */ -struct ccu_clk_gate { - u16 off; - u32 bit; - enum ccu_flags flags; -}; - -#define GATE(_off, _bit) { \ - .off = _off, \ - .bit = _bit, \ - .flags = CCU_CLK_F_IS_VALID, \ -} - -/** - * struct ccu_reset - ccu reset - * @off: reset offset - * @bit: reset bit - * @flags: ccu reset control flags - */ -struct ccu_reset { - u16 off; - u32 bit; - enum ccu_flags flags; -}; - -#define RESET(_off, _bit) { \ - .off = _off, \ - .bit = _bit, \ - .flags = CCU_RST_F_IS_VALID, \ -} - -/** - * struct ccu_desc - clock control unit descriptor - * - * @gates: clock gates - * @resets: reset unit - */ -struct ccu_desc { - const struct ccu_clk_gate *gates; - const struct ccu_reset *resets; -}; - -/** - * struct ccu_priv - sunxi clock control unit - * - * @base: base address - * @desc: ccu descriptor - */ -struct ccu_priv { - void *base; - const struct ccu_desc *desc; -}; - -/** - * sunxi_clk_probe - common sunxi clock probe - * @dev: clock device - */ -int sunxi_clk_probe(struct udevice *dev); - -extern struct clk_ops sunxi_clk_ops; - -/** - * sunxi_reset_bind() - reset binding - * - * @dev: reset device - * @count: reset count - * @return 0 success, or error value - */ -int sunxi_reset_bind(struct udevice *dev, ulong count); - -#endif /* _ASM_ARCH_CCU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 2969a530ae1..f3ab1aea0ef 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -93,20 +93,10 @@ struct sunxi_gpio_reg { #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) /* GPIO bank sizes */ -#define SUNXI_GPIO_A_NR 32 -#define SUNXI_GPIO_B_NR 32 -#define SUNXI_GPIO_C_NR 32 -#define SUNXI_GPIO_D_NR 32 -#define SUNXI_GPIO_E_NR 32 -#define SUNXI_GPIO_F_NR 32 -#define SUNXI_GPIO_G_NR 32 -#define SUNXI_GPIO_H_NR 32 -#define SUNXI_GPIO_I_NR 32 -#define SUNXI_GPIO_L_NR 32 -#define SUNXI_GPIO_M_NR 32 +#define SUNXI_GPIOS_PER_BANK 32 #define SUNXI_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + 0) + ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) enum sunxi_gpio_number { SUNXI_GPIO_A_START = 0, @@ -148,8 +138,6 @@ enum sunxi_gpio_number { #define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 -#define SUN6I_GPA_SDC2 5 -#define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2 #define SUN4I_GPB_PWM 2 @@ -173,12 +161,10 @@ enum sunxi_gpio_number { #define SUN6I_GPC_SDC3 4 #define SUN50I_GPC_SPI0 4 -#define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3 #define SUNXI_GPD_PWM 2 -#define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 #define SUN50I_GPE_TWI2 3 @@ -242,9 +228,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); -int sunxi_name_to_gpio_bank(const char *name); int sunxi_name_to_gpio(const char *name); -#define name_to_gpio(name) sunxi_name_to_gpio(name) #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO int axp_gpio_init(void); diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 24d0db8ced8..cd4d0ee3c95 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -30,4 +30,14 @@ void pin_mux_nand(void); /* overridable NAND pinmux setup */ void pin_mux_mmc(void); /* overridable mmc pinmux setup */ void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ +/* + * Helpers for various standard DT update mechanisms. + */ + +#if defined(CONFIG_ARM64) +void ft_mac_address_setup(void *fdt); +void ft_carveout_setup(void *fdt, const char *const *nodes, + unsigned int count); +#endif + #endif diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 1de70933550..9330a32fe98 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) #ifdef CONFIG_IMX8M -#define PAD_CTL_DSE0 (0x0 << 0) -#define PAD_CTL_DSE1 (0x1 << 0) -#define PAD_CTL_DSE2 (0x2 << 0) -#define PAD_CTL_DSE3 (0x3 << 0) -#define PAD_CTL_DSE4 (0x4 << 0) -#define PAD_CTL_DSE5 (0x5 << 0) -#define PAD_CTL_DSE6 (0x6 << 0) -#define PAD_CTL_DSE7 (0x7 << 0) - #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) @@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_DSE1 (0x0 << 1) +#define PAD_CTL_DSE2 (0x2 << 1) +#define PAD_CTL_DSE4 (0x1 << 1) +#define PAD_CTL_DSE6 (0x3 << 1) #define PAD_CTL_PE (0x1 << 8) #else +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) #define PAD_CTL_LVTTL (0x1 << 8) #endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index dd6a69315ac..a59a5e6c0ea 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -199,7 +199,7 @@ static void boot_prep_linux(bootm_headers_t *images) { char *commandline = env_get("bootargs"); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { @@ -356,7 +356,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) bootstage_mark(BOOTSTAGE_ID_RUN_OS); announce_and_cleanup(fake); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) r2 = (unsigned long)images->ft_addr; else r2 = gd->bd->bi_boot_params; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index dd4f027f36d..9aa1d84336b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -48,7 +48,7 @@ config USE_IMXIMG_PLUGIN config IMX_HAB bool "Support i.MX HAB features" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP select FSL_CAAM if HAS_CAAM imply CMD_DEKBLOB if HAS_CAAM help diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 63e28c635e3..bfff79f88c5 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -114,8 +114,7 @@ endif DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) else ifeq ($(CONFIG_ARCH_IMX8M), y) IMAGE_TYPE := imx8mimage -IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh -DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi) +DEPFILE_EXISTS := 0 else IMAGE_TYPE := imximage DEPFILE_EXISTS := 0 @@ -150,16 +149,18 @@ endif ifdef CONFIG_ARM64 ifeq ($(CONFIG_ARCH_IMX8M), y) -SPL: + +SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) flash.bin: MKIMAGEOUTPUT = flash.log +spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cpp_cfg) + spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE -ifeq ($(DEPFILE_EXISTS),0) - $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1 -endif flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE $(call if_changed,mkimage) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index cc39e6bf569..55317abba23 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -591,7 +591,7 @@ static ulong get_image_ivt_offset(ulong img_addr) return (image_get_image_size((image_header_t *)img_addr) + 0x1000 - 1) & ~(0x1000 - 1); #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) case IMAGE_FORMAT_FIT: return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1); #endif diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index ccaf106be5d..41088a2dcdc 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -75,6 +75,13 @@ config TARGET_IMX8MM_VENICE select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_KONTRON_MX8MM + bool "Kontron Electronics N80xx" + select BINMAN + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" select BINMAN @@ -138,6 +145,13 @@ config TARGET_IMX8MM_CL_IOT_GATE select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + +config TARGET_IMX8MM_CL_IOT_GATE_OPTEE + bool "CompuLab iot-gate-imx8 with optee support" + select BINMAN + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 endchoice source "board/beacon/imx8mm/Kconfig" @@ -150,6 +164,7 @@ source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" source "board/gateworks/venice/Kconfig" source "board/google/imx8mq_phanbell/Kconfig" +source "board/kontron/sl-mx8mm/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index f2ddc834d4b..863508776dd 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -298,16 +298,26 @@ phys_size_t get_effective_memsize(void) ulong board_get_usable_ram_top(ulong total_size) { + ulong top_addr = PHYS_SDRAM + gd->ram_size; + /* * Some IPs have their accessible address space restricted by * the interconnect. Let's make sure U-Boot only ever uses the * space below the 4G address boundary (which is 3GiB big), * even when the effective available memory is bigger. */ - if (PHYS_SDRAM + gd->ram_size > 0x80000000) - return 0x80000000; + if (top_addr > 0x80000000) + top_addr = 0x80000000; + + /* + * rom_pointer[0] stores the TEE memory start address. + * rom_pointer[1] stores the size TEE uses. + * We need to reserve the memory region for TEE. + */ + if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0]) + top_addr = rom_pointer[0]; - return PHYS_SDRAM + gd->ram_size; + return top_addr; } static u32 get_cpu_variant_type(u32 type) diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh deleted file mode 100755 index 2a17968794c..00000000000 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ /dev/null @@ -1,143 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0+ -# -# script to generate FIT image source for i.MX8MQ boards with -# ARM Trusted Firmware and multiple device trees (given on the command line) -# -# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] - -[ -z "$BL31" ] && BL31="bl31.bin" -[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000" -[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000" -[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000" - -if [ ! -f $BL31 ]; then - echo "ERROR: BL31 file $BL31 NOT found" >&2 - exit 0 -else - echo "$BL31 size: " >&2 - stat -c %s $BL31 >&2 -fi - -BL32="tee.bin" - -if [ ! -f $BL32 ]; then - BL32=/dev/null -else - echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2 - echo "$BL32 size: " >&2 - stat -c %s $BL32 >&2 -fi - -BL33="u-boot-nodtb.bin" - -if [ ! -f $BL33 ]; then - echo "ERROR: $BL33 file NOT found" >&2 - exit 0 -else - echo "u-boot-nodtb.bin size: " >&2 - stat -c %s u-boot-nodtb.bin >&2 -fi - -for dtname in $* -do - echo "$dtname size: " >&2 - stat -c %s $dtname >&2 -done - - -cat << __HEADER_EOF -/dts-v1/; - -/ { - description = "Configuration to load ATF before U-Boot"; - - images { - uboot@1 { - description = "U-Boot (64-bit)"; - os = "u-boot"; - data = /incbin/("$BL33"); - type = "standalone"; - arch = "arm64"; - compression = "none"; - load = <$BL33_LOAD_ADDR>; - }; -__HEADER_EOF - -cnt=1 -for dtname in $* -do - cat << __FDT_IMAGE_EOF - fdt@$cnt { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname"); - type = "flat_dt"; - compression = "none"; - }; -__FDT_IMAGE_EOF -cnt=$((cnt+1)) -done - -cat << __HEADER_EOF - atf@1 { - description = "ARM Trusted Firmware"; - os = "arm-trusted-firmware"; - data = /incbin/("$BL31"); - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <$ATF_LOAD_ADDR>; - entry = <$ATF_LOAD_ADDR>; - }; -__HEADER_EOF - -if [ -f $BL32 ]; then -cat << __HEADER_EOF - tee@1 { - description = "TEE firmware"; - data = /incbin/("$BL32"); - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <$TEE_LOAD_ADDR>; - entry = <$TEE_LOAD_ADDR>; - }; -__HEADER_EOF -fi - -cat << __CONF_HEADER_EOF - }; - configurations { - default = "config@1"; - -__CONF_HEADER_EOF - -cnt=1 -for dtname in $* -do -if [ -f $BL32 ]; then -cat << __CONF_SECTION_EOF - config@$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "uboot@1"; - loadables = "atf@1", "tee@1"; - fdt = "fdt@$cnt"; - }; -__CONF_SECTION_EOF -else -cat << __CONF_SECTION1_EOF - config@$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "uboot@1"; - loadables = "atf@1"; - fdt = "fdt@$cnt"; - }; -__CONF_SECTION1_EOF -fi -cnt=$((cnt+1)) -done - -cat << __ITS_EOF - }; -}; -__ITS_EOF diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index ee73006ae81..b4c8511cb87 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -230,6 +230,15 @@ config TARGET_GW_VENTANA imply CMD_SATA imply CMD_SPL +config TARGET_KONTRON_MX6UL + bool "Kontron Electronics SL/BL i.MX6UL/ULL (N63xx/N64xx)" + depends on MX6UL + select BINMAN + select DM + select DM_THERMAL + select SUPPORT_SPL + imply CMD_DM + config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" select BOARD_LATE_INIT @@ -668,6 +677,7 @@ source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" +source "board/kontron/sl-mx6ul/Kconfig" source "board/kosagi/novena/Kconfig" source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 320f24dd296..7f097d68503 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -93,14 +93,31 @@ int board_postclk_init(void) static void disable_wdog(u32 wdog_base) { - writel(UNLOCK_WORD0, (wdog_base + 0x04)); - writel(UNLOCK_WORD1, (wdog_base + 0x04)); - writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ - writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ - writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ - - writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ - writel(REFRESH_WORD1, (wdog_base + 0x04)); + u32 val_cs = readl(wdog_base + 0x00); + + if (!(val_cs & 0x80)) + return; + + dmb(); + __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ + __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); + dmb(); + + if (!(val_cs & 800)) { + dmb(); + __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); + __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x800)); + } + dmb(); + __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */ + __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */ + __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */ + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x400)); } void init_wdog(void) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index c2845241d9d..427b7f78599 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -334,6 +334,20 @@ void board_spl_fit_post_load(const void *fit) } #endif +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + int align_len = ARCH_DMA_MINALIGN - 1; + + /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address + * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust + * the bl_len to align with SD/MMC. + */ + if (bl_len < 512) + bl_len = 512; + + return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len - + align_len) & ~align_len); +} #endif #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) @@ -345,3 +359,36 @@ int dram_init_banksize(void) return 0; } #endif + +/* + * read the address where the IVT header must sit + * from IVT image header, loaded from SPL into + * an malloced buffer and copy the IVT header + * to this address + */ +void *spl_load_simple_fit_fix_load(const void *fit) +{ + struct ivt *ivt; + unsigned long new; + unsigned long offset; + unsigned long size; + u8 *tmp = (u8 *)fit; + + offset = ALIGN(fdt_totalsize(fit), 0x1000); + size = ALIGN(fdt_totalsize(fit), 4); + size = board_spl_fit_size_align(size); + tmp += offset; + ivt = (struct ivt *)tmp; + if (ivt->hdr.magic != IVT_HEADER_MAGIC) { + debug("no IVT header found\n"); + return (void *)fit; + } + debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size); + debug("%s: ivt self: %x\n", __func__, ivt->self); + new = ivt->self; + new -= offset; + debug("%s: new %lx\n", __func__, new); + memcpy((void *)new, fit, size); + + return (void *)new; +} diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 9002e26d75f..cf6b1b9b634 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -63,13 +63,6 @@ #endif /* CONFIG_CMD_NET */ /* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* * IDE Support on SATA ports */ #ifdef CONFIG_IDE diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 087643725e8..d23cc0c760f 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -11,6 +11,7 @@ config ARMADA_32BIT select SPL_DM if SPL select SPL_DM_SEQ_ALIAS if SPL select SPL_OF_CONTROL if SPL + select SPL_SKIP_LOWLEVEL_INIT if SPL select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL select TRANSLATION_OFFSET @@ -126,7 +127,9 @@ config TARGET_TURRIS_OMNIA select DM_I2C select I2C_MUX select I2C_MUX_PCA954x + select SPL_DRIVERS_MISC select SPL_I2C_MUX + select SPL_SYS_MALLOC_SIMPLE select SYS_I2C_MVTWSI select ATSHA204A diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index adef3331a7c..55c3f9ca390 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -21,35 +21,12 @@ __weak void board_pex_config(void) int hws_pex_config(const struct serdes_map *serdes_map, u8 count) { - u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg, - temp_reg, addr, dev_id, ctrl_mode; enum serdes_type serdes_type; - u32 idx; + u32 idx, tmp; DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n"); - for (idx = 0; idx < count; idx++) { - serdes_type = serdes_map[idx].serdes_type; - /* configuration for PEX only */ - if ((serdes_type != PEX0) && (serdes_type != PEX1) && - (serdes_type != PEX2) && (serdes_type != PEX3)) - continue; - - if ((serdes_type != PEX0) && - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { - /* for PEX by4 - relevant for the first port only */ - continue; - } - - pex_idx = serdes_type - PEX0; - tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); - tmp &= ~(0xf << 20); - tmp |= (0x4 << 20); - reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); - } - - tmp = reg_read(SOC_CTRL_REG); + tmp = reg_read(SOC_CONTROL_REG1); tmp &= ~0x03; for (idx = 0; idx < count; idx++) { @@ -79,277 +56,9 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) } } - reg_write(SOC_CTRL_REG, tmp); - - /* Support gen1/gen2 */ - DEBUG_INIT_FULL_S("Support gen1/gen2\n"); + reg_write(SOC_CONTROL_REG1, tmp); board_pex_config(); - next_busno = 0; - mdelay(150); - - for (idx = 0; idx < count; idx++) { - serdes_type = serdes_map[idx].serdes_type; - DEBUG_INIT_FULL_S(" serdes_type=0x"); - DEBUG_INIT_FULL_D(serdes_type, 8); - DEBUG_INIT_FULL_S("\n"); - DEBUG_INIT_FULL_S(" idx=0x"); - DEBUG_INIT_FULL_D(idx, 8); - DEBUG_INIT_FULL_S("\n"); - - /* Configuration for PEX only */ - if ((serdes_type != PEX0) && (serdes_type != PEX1) && - (serdes_type != PEX2) && (serdes_type != PEX3)) - continue; - - if ((serdes_type != PEX0) && - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { - /* for PEX by4 - relevant for the first port only */ - continue; - } - - pex_idx = serdes_type - PEX0; - tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx)); - - first_busno = next_busno; - if ((tmp & 0x7f) != 0x7e) { - DEBUG_INIT_S("PCIe, Idx "); - DEBUG_INIT_D(pex_idx, 1); - DEBUG_INIT_S(": detected no link\n"); - continue; - } - - next_busno++; - temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS - (pex_idx, PEX_LINK_CAPABILITY_REG))); - temp_pex_reg &= 0xf; - if (temp_pex_reg != 0x2) - continue; - - temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CTRL_STAT_REG)) & - 0xf0000) >> 16; - - /* Check if the link established is GEN1 */ - DEBUG_INIT_FULL_S - ("Checking if the link established is gen1\n"); - if (temp_reg != 0x1) - continue; - - pex_local_bus_num_set(pex_idx, first_busno); - pex_local_dev_num_set(pex_idx, 1); - DEBUG_INIT_FULL_S("PCIe, Idx "); - DEBUG_INIT_FULL_D(pex_idx, 1); - - DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n"); - /* link is Gen1, check the EP capability */ - addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff; - DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4); - if (addr == 0xff) { - DEBUG_INIT_FULL_C - ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.", - pex_idx, 1); - continue; - } - - while ((pex_config_read(pex_idx, first_busno, 0, 0, addr) - & 0xff) != 0x10) { - addr = (pex_config_read(pex_idx, first_busno, 0, - 0, addr) & 0xff00) >> 8; - } - - /* Check for Gen2 and above */ - if ((pex_config_read(pex_idx, first_busno, 0, 0, - addr + 0xc) & 0xf) < 0x2) { - DEBUG_INIT_S("PCIe, Idx "); - DEBUG_INIT_D(pex_idx, 1); - DEBUG_INIT_S(": remains Gen1\n"); - continue; - } - - tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx)); - DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); - tmp &= ~(BIT(0) | BIT(1)); - tmp |= BIT(1); - tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */ - reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); - DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); - - tmp = reg_read(PEX_CTRL_REG(pex_idx)); - DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp); - tmp |= BIT(10); - reg_write(PEX_CTRL_REG(pex_idx), tmp); - DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp); - - /* - * We need to wait 10ms before reading the PEX_DBG_STATUS_REG - * in order not to read the status of the former state - */ - mdelay(10); - - DEBUG_INIT_S("PCIe, Idx "); - DEBUG_INIT_D(pex_idx, 1); - DEBUG_INIT_S - (": Link upgraded to Gen2 based on client capabilities\n"); - } - - /* Update pex DEVICE ID */ - ctrl_mode = sys_env_model_get(); - - for (idx = 0; idx < count; idx++) { - serdes_type = serdes_map[idx].serdes_type; - /* configuration for PEX only */ - if ((serdes_type != PEX0) && (serdes_type != PEX1) && - (serdes_type != PEX2) && (serdes_type != PEX3)) - continue; - - if ((serdes_type != PEX0) && - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { - /* for PEX by4 - relevant for the first port only */ - continue; - } - - pex_idx = serdes_type - PEX0; - dev_id = reg_read(PEX_CFG_DIRECT_ACCESS - (pex_idx, PEX_DEVICE_AND_VENDOR_ID)); - dev_id &= 0xffff; - dev_id |= ((ctrl_mode << 16) & 0xffff0000); - reg_write(PEX_CFG_DIRECT_ACCESS - (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id); - } - DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4); - return MV_OK; } - -int pex_local_bus_num_set(u32 pex_if, u32 bus_num) -{ - u32 pex_status; - - DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n"); - - if (bus_num >= MAX_PEX_BUSSES) { - DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n", - bus_num, 4); - return MV_BAD_PARAM; - } - - pex_status = reg_read(PEX_STATUS_REG(pex_if)); - pex_status &= ~PXSR_PEX_BUS_NUM_MASK; - pex_status |= - (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; - reg_write(PEX_STATUS_REG(pex_if), pex_status); - - return MV_OK; -} - -int pex_local_dev_num_set(u32 pex_if, u32 dev_num) -{ - u32 pex_status; - - DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n"); - - pex_status = reg_read(PEX_STATUS_REG(pex_if)); - pex_status &= ~PXSR_PEX_DEV_NUM_MASK; - pex_status |= - (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; - reg_write(PEX_STATUS_REG(pex_if), pex_status); - - return MV_OK; -} - -/* - * pex_config_read - Read from configuration space - * - * DESCRIPTION: - * This function performs a 32 bit read from PEX configuration space. - * It supports both type 0 and type 1 of Configuration Transactions - * (local and over bridge). In order to read from local bus segment, use - * bus number retrieved from pex_local_bus_num_get(). Other bus numbers - * will result configuration transaction of type 1 (over bridge). - * - * INPUT: - * pex_if - PEX interface number. - * bus - PEX segment bus number. - * dev - PEX device number. - * func - Function number. - * reg_offs - Register offset. - * - * OUTPUT: - * None. - * - * RETURN: - * 32bit register data, 0xffffffff on error - */ -u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off) -{ - u32 pex_data = 0; - u32 local_dev, local_bus; - u32 pex_status; - - pex_status = reg_read(PEX_STATUS_REG(pex_if)); - local_dev = - ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS); - local_bus = - ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS); - - /* - * In PCI Express we have only one device number - * and this number is the first number we encounter - * else that the local_dev - * spec pex define return on config read/write on any device - */ - if (bus == local_bus) { - if (local_dev == 0) { - /* - * if local dev is 0 then the first number we encounter - * after 0 is 1 - */ - if ((dev != 1) && (dev != local_dev)) - return MV_ERROR; - } else { - /* - * if local dev is not 0 then the first number we - * encounter is 0 - */ - if ((dev != 0) && (dev != local_dev)) - return MV_ERROR; - } - } - - /* Creating PEX address to be passed */ - pex_data = (bus << PXCAR_BUS_NUM_OFFS); - pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS); - pex_data |= (func << PXCAR_FUNC_NUM_OFFS); - /* Legacy register space */ - pex_data |= (reg_off & PXCAR_REG_NUM_MASK); - /* Extended register space */ - pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >> - PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); - pex_data |= PXCAR_CONFIG_EN; - - /* Write the address to the PEX configuration address register */ - reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data); - - /* - * In order to let the PEX controller absorbed the address - * of the read transaction we perform a validity check that - * the address was written - */ - if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if))) - return MV_ERROR; - - /* Cleaning Master Abort */ - reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND), - PXSAC_MABORT); - /* Read the Data returned in the PEX Data register */ - pex_data = reg_read(PEX_CFG_DATA_REG(pex_if)); - - DEBUG_INIT_FULL_C(" --> ", pex_data, 4); - - return pex_data; -} diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index 3f30b6bf972..64193d52888 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -6,35 +6,13 @@ #ifndef _CTRL_PEX_H #define _CTRL_PEX_H +#include <pci.h> #include "high_speed_env_spec.h" -/* Sample at Reset */ -#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4)) +/* Direct access to PEX0 Root Port's PCIe Capability structure */ +#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) -/* PCI Express Control and Status Registers */ -#define MAX_PEX_BUSSES 256 - -#define MISC_REGS_OFFSET 0x18200 -#define MV_MISC_REGS_BASE MISC_REGS_OFFSET -#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) - -#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \ - (0x40000 + ((if) - 1) * 0x4000) : \ - 0x80000) -#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if)) -#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60) -#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90) -#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00) -#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04) -#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64) -#define PEX_LINK_CAPABILITY_REG 0x6c -#define PEX_LINK_CTRL_STAT_REG 0x70 -#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) - -/* PEX_CAPABILITIES_REG fields */ +/* SOC_CONTROL_REG1 fields */ #define PCIE0_ENABLE_OFFS 0 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) #define PCIE1_ENABLE_OFFS 1 @@ -44,45 +22,7 @@ #define PCIE3_ENABLE_OFFS 3 #define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS) -/* Controller revision info */ -#define PEX_DEVICE_AND_VENDOR_ID 0x000 -#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg)) - -/* PCI Express Configuration Address Register */ -#define PXCAR_REG_NUM_OFFS 2 -#define PXCAR_REG_NUM_MAX 0x3f -#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \ - PXCAR_REG_NUM_OFFS) -#define PXCAR_FUNC_NUM_OFFS 8 -#define PXCAR_FUNC_NUM_MAX 0x7 -#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \ - PXCAR_FUNC_NUM_OFFS) -#define PXCAR_DEVICE_NUM_OFFS 11 -#define PXCAR_DEVICE_NUM_MAX 0x1f -#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \ - PXCAR_DEVICE_NUM_OFFS) -#define PXCAR_BUS_NUM_OFFS 16 -#define PXCAR_BUS_NUM_MAX 0xff -#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \ - PXCAR_BUS_NUM_OFFS) -#define PXCAR_EXT_REG_NUM_OFFS 24 -#define PXCAR_EXT_REG_NUM_MAX 0xf - -#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8) -#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc) - -#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS) - -#define PXCAR_CONFIG_EN BIT(31) -#define PEX_STATUS_AND_COMMAND 0x004 -#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */ - int hws_pex_config(const struct serdes_map *serdes_map, u8 count); -int pex_local_bus_num_set(u32 pex_if, u32 bus_num); -int pex_local_dev_num_set(u32 pex_if, u32 dev_num); -u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off); - void board_pex_config(void); #endif diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index bb7d24b4b7b..d2bc3ab25c3 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1712,7 +1712,7 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, (serdes_mode == PEX_END_POINT_X1); pex_idx = serdes_type - PEX0; - if ((is_pex_by1 == 1) || (serdes_type == PEX0)) { + if (serdes_type == PEX0) { /* For PEX by 4, init only the PEX 0 */ reg_data = reg_read(SOC_CONTROL_REG1); if (is_pex_by1 == 1) @@ -1721,32 +1721,20 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, reg_data &= ~0x4000; reg_write(SOC_CONTROL_REG1, reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x6c)); - reg_data &= ~0x3f0; - if (is_pex_by1 == 1) - reg_data |= 0x10; - else - reg_data |= 0x40; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), - reg_data); - - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x6c)); - reg_data &= ~0xf; - reg_data |= 0x2; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), - reg_data); - - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x70)); - reg_data &= ~0x40; - reg_data |= 0x40; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70), - reg_data); + /* + * Set Maximum Link Width to X1 or X4 in Root + * Port's PCIe Link Capability register. + * This register is read-only but if is not set + * correctly then access to PCI config space of + * endpoint card behind this Root Port does not + * work. + */ + reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET + + PCI_EXP_LNKCAP); + reg_data &= ~PCI_EXP_LNKCAP_MLW; + reg_data |= (is_pex_by1 ? 1 : 4) << 4; + reg_write(PEX0_RP_PCIE_CFG_OFFSET + + PCI_EXP_LNKCAP, reg_data); } CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ)); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1d4a4fdd0c5..2c18cf02d1a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -88,17 +88,6 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE feature. endif -config SUN6I_P2WI - bool "Allwinner sun6i internal P2WI controller" - help - If you say yes to this option, support will be included for the - P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi - SOCs. - The P2WI looks like an SMBus controller (which supports only byte - accesses), except that it only supports one slave device. - This interface is used to connect to specific PMIC devices (like the - AXP221). - config SUN6I_PRCM bool help @@ -106,19 +95,13 @@ config SUN6I_PRCM in A31 SoC. config AXP_PMIC_BUS - bool "Sunxi AXP PMIC bus access helpers" + bool + select DM_PMIC if DM_I2C + select PMIC_AXP if DM_I2C help Select this PMIC bus access helpers for Sunxi platform PRCM or other AXP family PMIC devices. -config SUN8I_RSB - bool "Allwinner sunXi Reduced Serial Bus Driver" - help - Say y here to enable support for Allwinner's Reduced Serial Bus - (RSB) support. This controller is responsible for communicating - with various RSB based devices, such as AXP223, AXP8XX PMICs, - and AC100/AC200 ICs. - config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 @@ -182,7 +165,6 @@ endif config MACH_SUNXI_H3_H5 bool - select DM_I2C select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_DRAM_DW @@ -232,10 +214,11 @@ config MACH_SUN6I select ARCH_SUPPORT_PSCI select DRAM_SUN6I select PHY_SUN4I_USB - select SUN6I_P2WI + select SPL_I2C select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SYS_I2C_SUN6I_P2WI select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN7I @@ -260,8 +243,10 @@ config MACH_SUN8I_A23 select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A23 select PHY_SUN4I_USB + select SPL_I2C select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SYS_I2C_SUN8I_RSB select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT imply CONS_INDEX_5 if !DM_SERIAL @@ -273,8 +258,10 @@ config MACH_SUN8I_A33 select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A33 select PHY_SUN4I_USB + select SPL_I2C select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SYS_I2C_SUN8I_RSB select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT imply CONS_INDEX_5 if !DM_SERIAL @@ -283,10 +270,12 @@ config MACH_SUN8I_A83T select CPU_V7A select DRAM_SUN8I_A83T select PHY_SUN4I_USB + select SPL_I2C select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE select MMC_SUNXI_HAS_MODE_SWITCH select SUPPORT_SPL + select SYS_I2C_SUN8I_RSB config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" @@ -327,16 +316,15 @@ config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7A select DRAM_SUN9I + select SPL_I2C select SUN6I_PRCM select SUNXI_GEN_SUN6I - select SUN8I_RSB select SUPPORT_SPL config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 select SPI - select DM_I2C select DM_SPI if SPI select DM_SPI_FLASH select PHY_SUN4I_USB @@ -377,7 +365,6 @@ endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool - select SUN8I_RSB select SUN6I_PRCM default y if MACH_SUN8I_A23 default y if MACH_SUN8I_A33 @@ -677,24 +664,11 @@ config MMC3_CD_PIN ---help--- See MMC0_CD_PIN help text. -config MMC1_PINS - string "Pins for mmc1" - default "" +config MMC1_PINS_PH + bool "Pins for mmc1 are on Port H" + depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 ---help--- - Set the pins used for mmc1, when applicable. This takes a string in the - format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. - -config MMC2_PINS - string "Pins for mmc2" - default "" - ---help--- - See MMC1_PINS help text. - -config MMC3_PINS - string "Pins for mmc3" - default "" - ---help--- - See MMC1_PINS help text. + Select this option for boards where mmc1 uses the Port H pinmux. config MMC_SUNXI_SLOT_EXTRA int "mmc extra slot number" @@ -807,6 +781,7 @@ endif config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" + depends on AXP_PMIC_BUS ---help--- Say Y here to enable support for the gpio pins of the axp PMIC ICs. @@ -932,27 +907,17 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI - select CMD_I2C + select DM_I2C_GPIO ---help--- Say y here if the LCD panel needs to be configured via i2c. This will add a bitbang i2c controller using gpios to talk to the LCD. -config VIDEO_LCD_PANEL_I2C_SDA - string "LCD panel i2c interface SDA pin" +config VIDEO_LCD_PANEL_I2C_NAME + string "LCD panel i2c interface node name" depends on VIDEO_LCD_PANEL_I2C - default "PG12" + default "i2c@0" ---help--- - Set the SDA pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_LCD_PANEL_I2C_SCL - string "LCD panel i2c interface SCL pin" - depends on VIDEO_LCD_PANEL_I2C - default "PG10" - ---help--- - Set the SCL pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - + Set the device tree node name for the LCD i2c interface. # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 3f081d92f37..5d3fd70f749 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -11,10 +11,8 @@ obj-y += clock.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-y += pinmux.o -obj-$(CONFIG_SUN6I_P2WI) += p2wi.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o -obj-$(CONFIG_SUN8I_RSB) += rsb.o obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index d9b04f75fc4..b4ba2a72c42 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -21,7 +21,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> #include <asm/arch/spl.h> #include <asm/arch/sys_proto.h> #include <asm/arch/timer.h> @@ -339,7 +338,7 @@ void board_init_f(ulong dummy) spl_init(); preloader_console_init(); -#ifdef CONFIG_SPL_I2C +#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) /* Needed early by sunxi_board_init if PMU is enabled */ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index f591affebf7..de7e8752988 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -10,7 +10,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> #include <asm/arch/prcm.h> #include <asm/arch/gtbus.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 57ee018eaa2..471609764d2 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -12,7 +12,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-sunxi/p2wi.c b/arch/arm/mach-sunxi/p2wi.c deleted file mode 100644 index 7c5c12254ea..00000000000 --- a/arch/arm/mach-sunxi/p2wi.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Sunxi A31 Power Management Unit - * - * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> - * http://linux-sunxi.org - * - * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work - * - * (C) Copyright 2006-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#include <common.h> -#include <errno.h> -#include <time.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/p2wi.h> -#include <asm/arch/prcm.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> - -void p2wi_init(void) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - - /* Enable p2wi and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); - - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); - - /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ - writel(P2WI_CTRL_RESET, &p2wi->ctrl); - sdelay(0x100); - writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), - &p2wi->cc); -} - -int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - unsigned long tmo = timer_get_us() + 1000000; - - writel(P2WI_PM_DEV_ADDR(slave_addr) | - P2WI_PM_CTRL_ADDR(ctrl_reg) | - P2WI_PM_INIT_DATA(init_data) | - P2WI_PM_INIT_SEND, - &p2wi->pm); - - while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { - if (timer_get_us() > tmo) - return -ETIME; - } - - return 0; -} - -static int p2wi_await_trans(void) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - unsigned long tmo = timer_get_us() + 1000000; - int ret; - u8 reg; - - while (1) { - reg = readl(&p2wi->status); - if (reg & P2WI_STAT_TRANS_ERR) { - ret = -EIO; - break; - } - if (reg & P2WI_STAT_TRANS_DONE) { - ret = 0; - break; - } - if (timer_get_us() > tmo) { - ret = -ETIME; - break; - } - } - writel(reg, &p2wi->status); /* Clear status bits */ - return ret; -} - -int p2wi_read(const u8 addr, u8 *data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - int ret; - - writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); - writel(P2WI_DATA_NUM_BYTES(1) | - P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); - writel(P2WI_STAT_TRANS_DONE, &p2wi->status); - writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); - - ret = p2wi_await_trans(); - - *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; - return ret; -} - -int p2wi_write(const u8 addr, u8 data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - - writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); - writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); - writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); - writel(P2WI_STAT_TRANS_DONE, &p2wi->status); - writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); - - return p2wi_await_trans(); -} diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 0394ce85644..c0908406370 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -8,10 +8,13 @@ * axp223 uses the rsb bus, these functions abstract this. */ +#include <axp_pmic.h> #include <common.h> +#include <dm.h> #include <asm/arch/p2wi.h> #include <asm/arch/rsb.h> #include <i2c.h> +#include <power/pmic.h> #include <asm/arch/pmic_bus.h> #define AXP152_I2C_ADDR 0x30 @@ -21,80 +24,80 @@ #define AXP305_I2C_ADDR 0x36 #define AXP221_CHIP_ADDR 0x68 -#define AXP221_CTRL_ADDR 0x3e -#define AXP221_INIT_DATA 0x3e -/* AXP818 device and runtime addresses are same as AXP223 */ -#define AXP223_DEVICE_ADDR 0x3a3 -#define AXP223_RUNTIME_ADDR 0x2d +#if CONFIG_IS_ENABLED(PMIC_AXP) +static struct udevice *pmic; +#else +static int pmic_i2c_address(void) +{ + if (IS_ENABLED(CONFIG_AXP152_POWER)) + return AXP152_I2C_ADDR; + if (IS_ENABLED(CONFIG_AXP305_POWER)) + return AXP305_I2C_ADDR; + + /* Other AXP2xx and AXP8xx variants */ + return AXP209_I2C_ADDR; +} +#endif int pmic_bus_init(void) { /* This cannot be 0 because it is used in SPL before BSS is ready */ static int needs_init = 1; - __maybe_unused int ret; + int ret = 0; if (!needs_init) return 0; -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - p2wi_init(); - ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, - AXP221_INIT_DATA); -# elif defined CONFIG_MACH_SUN8I_R40 - /* Nothing. R40 uses the AXP221s in I2C mode */ - ret = 0; -# else - ret = rsb_init(); - if (ret) - return ret; - - ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); -# endif - if (ret) - return ret; +#if CONFIG_IS_ENABLED(PMIC_AXP) + ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic), + &pmic); +#else + if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) { + p2wi_init(); + ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, + AXP_PMIC_MODE_REG, + AXP_PMIC_MODE_P2WI); + } else if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) { + ret = rsb_init(); + if (ret) + return ret; + + ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, + AXP_PMIC_PRI_RUNTIME_ADDR); + } #endif - needs_init = 0; - return 0; + needs_init = ret; + + return ret; } int pmic_bus_read(u8 reg, u8 *data) { -#ifdef CONFIG_AXP152_POWER - return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP209_POWER - return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP305_POWER - return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - return p2wi_read(reg, data); -# elif defined CONFIG_MACH_SUN8I_R40 - return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -# else - return rsb_read(AXP223_RUNTIME_ADDR, reg, data); -# endif +#if CONFIG_IS_ENABLED(PMIC_AXP) + return pmic_read(pmic, reg, data, 1); +#else + if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) + return p2wi_read(reg, data); + if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) + return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); + + return i2c_read(pmic_i2c_address(), reg, 1, data, 1); #endif } int pmic_bus_write(u8 reg, u8 data) { -#ifdef CONFIG_AXP152_POWER - return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP209_POWER - return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP305_POWER - return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - return p2wi_write(reg, data); -# elif defined CONFIG_MACH_SUN8I_R40 - return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -# else - return rsb_write(AXP223_RUNTIME_ADDR, reg, data); -# endif +#if CONFIG_IS_ENABLED(PMIC_AXP) + return pmic_write(pmic, reg, &data, 1); +#else + if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) + return p2wi_write(reg, data); + if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) + return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); + + return i2c_write(pmic_i2c_address(), reg, 1, &data, 1); #endif } diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c deleted file mode 100644 index 01bb09b7478..00000000000 --- a/arch/arm/mach-sunxi/rsb.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * - * Based on allwinner u-boot sources rsb code which is: - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * lixiang <lixiang@allwinnertech.com> - */ - -#include <common.h> -#include <errno.h> -#include <time.h> -#include <asm/arch/cpu.h> -#include <asm/arch/gpio.h> -#include <asm/arch/prcm.h> -#include <asm/arch/rsb.h> - -static int rsb_set_device_mode(void); - -static void rsb_cfg_io(void) -{ -#ifdef CONFIG_MACH_SUN8I - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPL(0), 1); - sunxi_gpio_set_pull(SUNXI_GPL(1), 1); - sunxi_gpio_set_drv(SUNXI_GPL(0), 2); - sunxi_gpio_set_drv(SUNXI_GPL(1), 2); -#elif defined CONFIG_MACH_SUN9I - sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPN(0), 1); - sunxi_gpio_set_pull(SUNXI_GPN(1), 1); - sunxi_gpio_set_drv(SUNXI_GPN(0), 2); - sunxi_gpio_set_drv(SUNXI_GPN(1), 2); -#else -#error unsupported MACH_SUNXI -#endif -} - -static void rsb_set_clk(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - u32 div = 0; - u32 cd_odly = 0; - - /* Source is Hosc24M, set RSB clk to 3Mhz */ - div = 24000000 / 3000000 / 2 - 1; - cd_odly = div >> 1; - if (!cd_odly) - cd_odly = 1; - - writel((cd_odly << 8) | div, &rsb->ccr); -} - -int rsb_init(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - /* Enable RSB and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); - - /* Setup external pins */ - rsb_cfg_io(); - - writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); - rsb_set_clk(); - - return rsb_set_device_mode(); -} - -static int rsb_await_trans(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - unsigned long tmo = timer_get_us() + 1000000; - u32 stat; - int ret; - - while (1) { - stat = readl(&rsb->stat); - if (stat & RSB_STAT_LBSY_INT) { - ret = -EBUSY; - break; - } - if (stat & RSB_STAT_TERR_INT) { - ret = -EIO; - break; - } - if (stat & RSB_STAT_TOVER_INT) { - ret = 0; - break; - } - if (timer_get_us() > tmo) { - ret = -ETIME; - break; - } - } - writel(stat, &rsb->stat); /* Clear status bits */ - - return ret; -} - -static int rsb_set_device_mode(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - unsigned long tmo = timer_get_us() + 1000000; - - writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA, - &rsb->dmcr); - - while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { - if (timer_get_us() > tmo) - return -ETIME; - } - - return rsb_await_trans(); -} - -static int rsb_do_trans(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); - return rsb_await_trans(); -} - -int rsb_set_device_address(u16 device_addr, u16 runtime_addr) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | - RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); - writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); - - return rsb_do_trans(); -} - -int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); - writel(reg_addr, &rsb->addr); - writel(data, &rsb->data); - writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); - - return rsb_do_trans(); -} - -int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - int ret; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); - writel(reg_addr, &rsb->addr); - writel(RSB_CMD_BYTE_READ, &rsb->cmd); - - ret = rsb_do_trans(); - if (ret) - return ret; - - *data = readl(&rsb->data) & 0xff; - - return 0; -} diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index 602b20e6b7e..c11494722bc 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -4,6 +4,9 @@ */ #include <common.h> +#include <fdtdec.h> +#include <stdlib.h> +#include <asm/arch-tegra/cboot.h> #include <asm/arch-tegra/gpu.h> /* @@ -31,3 +34,147 @@ int ft_system_setup(void *blob, struct bd_info *bd) return 0; } + +#if defined(CONFIG_ARM64) +void ft_mac_address_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) { + printf("ethernet alias points to absent node %s\n", path); + return; + } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } +} + +static int ft_copy_carveout(void *dst, const void *src, const char *node) +{ + const char *names = "memory-region-names"; + struct fdt_memory carveout; + unsigned int index = 0; + int err, offset, len; + const void *prop; + + while (true) { + const char **compatibles = NULL; + unsigned int num_compatibles; + unsigned long flags; + char *copy = NULL; + const char *name; + + err = fdtdec_get_carveout(src, node, "memory-region", index, + &carveout, &name, &compatibles, + &num_compatibles, &flags); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", + node, err); + else + break; + + return err; + } + + if (name) { + const char *ptr = strchr(name, '@'); + + if (ptr) { + copy = strndup(name, ptr - name); + name = copy; + } + } else { + name = "carveout"; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", index, + &carveout, name, compatibles, + num_compatibles, flags); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, + err); + return err; + } + + if (copy) + free(copy); + + index++; + } + + offset = fdt_path_offset(src, node); + if (offset < 0) { + debug("failed to find source offset for %s: %s\n", node, + fdt_strerror(err)); + return err; + } + + prop = fdt_getprop(src, offset, names, &len); + if (prop) { + offset = fdt_path_offset(dst, node); + if (offset < 0) { + debug("failed to find destination offset for %s: %s\n", + node, fdt_strerror(err)); + return err; + } + + err = fdt_setprop(dst, offset, "memory-region-names", prop, + len); + if (err < 0) { + debug("failed to copy \"%s\" property: %s\n", names, + fdt_strerror(err)); + return err; + } + } + + return 0; +} + +void ft_carveout_setup(void *fdt, const char * const *nodes, unsigned int count) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + unsigned int i; + int err; + + for (i = 0; i < count; i++) { + printf("copying carveout for %s...\n", nodes[i]); + + err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to copy carveout for %s: %d\n", + nodes[i], err); + + continue; + } + } +} +#endif diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 3a6da6e29ff..12ea32488e6 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -75,7 +75,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) static void boot_prep_linux(bootm_headers_t *images) { - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { debug("using: FDT\n"); if (image_setup_linux(images)) { printf("FDT creation failed! hanging..."); diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index bdb23b57658..cd85d1b6c31 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -20,6 +20,7 @@ config SOC_AR934X select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select USB_EHCI_IS_TDI if USB_EHCI_HCD help This supports QCA/Atheros ar934x family SOCs. diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 1c7f7856999..71ebfb4225b 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -69,7 +69,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) debug("## Transferring control to Linux (at address %08lx) ...\n", (ulong)theKernel); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { @@ -110,7 +110,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) #endif } cleanup_before_linux(); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) theKernel(0, machid, (unsigned long)images->ft_addr); else theKernel(0, machid, bd->bi_boot_params); diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 8e49b6d7364..8d90c5e6b8a 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -17,9 +17,6 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ -#ifdef CONFIG_OF_PRIOR_STAGE -phys_addr_t prior_stage_fdt_address __section(".data"); -#endif #ifndef CONFIG_XIP u32 hart_lottery __section(".data") = 0; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 308b0a97a58..76850ec9be2 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -142,11 +142,6 @@ call_harts_early_init: bnez tp, secondary_hart_loop #endif -#ifdef CONFIG_OF_PRIOR_STAGE - la t0, prior_stage_fdt_address - SREG s1, 0(t0) -#endif - jal board_init_f_init_reserve SREG s1, GD_FIRMWARE_FDT_ADDR(gp) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index d26cfdb78a9..5757ef65ea4 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -48,7 +48,7 @@ }; }; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD @fdt-SEQ { description = "NAME"; type = "flat_dt"; @@ -60,7 +60,7 @@ configurations { default = "conf-1"; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD @conf-SEQ { #else conf-1 { @@ -68,7 +68,7 @@ description = "NAME"; firmware = "opensbi"; loadables = "uboot"; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD fdt = "fdt-SEQ"; #endif }; diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index acf5a96449c..3540773c4fe 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -44,15 +44,15 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) * read/writes. We define __arch_*[bl] here, and leave __arch_*w * to the architecture specific code. */ -#define __arch_getb(a) (*(unsigned char *)(a)) -#define __arch_getw(a) (*(unsigned short *)(a)) -#define __arch_getl(a) (*(unsigned int *)(a)) -#define __arch_getq(a) (*(unsigned long long *)(a)) - -#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) -#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) -#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) -#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) +#define __arch_getq(a) (*(volatile unsigned long long *)(a)) + +#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) +#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v)) #define __raw_writeb(v, a) __arch_putb(v, a) #define __raw_writew(v, a) __arch_putw(v, a) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index ff1bdf71318..2e1e286c8ef 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -64,7 +64,7 @@ static void announce_and_cleanup(int fake) static void boot_prep_linux(bootm_headers_t *images) { - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { @@ -96,7 +96,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) announce_and_cleanup(fake); if (!fake) { - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_SMP ret = smp_call_function(images->ep, (ulong)images->ft_addr, 0, 0); diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 61cf8935269..36c16e9be2a 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) pmp_mem.start = addr; pmp_mem.end = addr + size - 1; err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, - &phandle, false); + NULL, 0, &phandle, 0); if (err < 0 && err != -FDT_ERR_EXISTS) { log_err("failed to add reserved memory: %d\n", err); return err; diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index b4ff717e784..a2bc5a7ee60 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2002-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y += interrupts.o sections.o +obj-y += fdt_fixup.o interrupts.o sections.o obj-$(CONFIG_PCI) += pci_io.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o diff --git a/arch/sandbox/lib/fdt_fixup.c b/arch/sandbox/lib/fdt_fixup.c new file mode 100644 index 00000000000..a646f2059c2 --- /dev/null +++ b/arch/sandbox/lib/fdt_fixup.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY LOGC_ARCH + +#include <common.h> +#include <fdt_support.h> +#include <log.h> + +#if defined(__riscv) +int arch_fixup_fdt(void *blob) +{ + int ret; + + ret = fdt_find_or_add_subnode(blob, 0, "chosen");; + if (ret < 0) + goto err; + ret = fdt_setprop_u32(blob, ret, "boot-hartid", 1); + if (ret < 0) + goto err; + return 0; +err: + log_err("Setting /chosen/boot-hartid failed: %s\n", fdt_strerror(ret)); + return ret; +} +#endif diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 7a8242562db..589f2aed2bc 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -37,7 +37,7 @@ KBUILD_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64) LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined -s OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \ - -j .rel -j .rela -j .reloc + -j .rel -j .rela -j .reloc --strip-all # Compiler flags to be added when building UEFI applications CFLAGS_EFI := -fpic -fshort-wchar @@ -65,7 +65,7 @@ CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI) ifeq ($(CONFIG_EFI_APP),y) PLATFORM_CPPFLAGS += $(CFLAGS_EFI) -LDFLAGS_FINAL += -znocombreloc -shared -s +LDFLAGS_FINAL += -znocombreloc -shared LDSCRIPT := $(LDSCRIPT_EFI) else diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 9a73b768e9b..3a9f7d72868 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -280,15 +280,24 @@ void setup_efi_info(struct efi_info *efi_info) } efi_info->efi_memdesc_size = map->desc_size; efi_info->efi_memdesc_version = map->version; - efi_info->efi_memmap = (u32)(map->desc); + efi_info->efi_memmap = (ulong)(map->desc); efi_info->efi_memmap_size = size - sizeof(struct efi_entry_memmap); #ifdef CONFIG_EFI_STUB_64BIT efi_info->efi_systab_hi = table->sys_table >> 32; - efi_info->efi_memmap_hi = (u64)(u32)(map->desc) >> 32; + efi_info->efi_memmap_hi = (u64)(ulong)map->desc >> 32; signature = EFI64_LOADER_SIGNATURE; #else signature = EFI32_LOADER_SIGNATURE; #endif memcpy(&efi_info->efi_loader_signature, signature, 4); } + +void efi_show_bdinfo(void) +{ + struct efi_entry_systable *table = NULL; + int size, ret; + + ret = efi_info_get(EFIET_SYS_TABLE, (void **)&table, &size); + bdinfo_print_num_l("efi_table", (ulong)table); +} diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h new file mode 100644 index 00000000000..dfd858b78ba --- /dev/null +++ b/arch/x86/include/asm/efi.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright Google LLC + */ + +#ifndef _ASM_EFI_H_ +#define _ASM_EFI_H_ + +struct efi_info; +struct screen_info; + +/** + * setup_video() - Set up the screen info in the x86 setup + * + * This is needed so Linux can use the display (when U-Boot is an EFI payload) + * + * @efi_info: Pointer to place to put the screen info in the x86 setup base + */ +void setup_video(struct screen_info *screen_info); + +/** + * setup_efi_info() - Set up the EFI info needed by Linux to boot + * + * This writes a suitable signature, table pointers, memory-map pointer, etc. + * These are needed for Linux to boot from U-Boot (when U-Boot is an EFI + * payload). + * + * @efi_info: Pointer to place to put the EFI info in the x86 setup base + */ +void setup_efi_info(struct efi_info *efi_info); + +/** + * efi_show_bdinfo() - Show information about EFI for the 'bdinfo' command + * + * This looks up the EFI table pointer and shows related info + */ +void efi_show_bdinfo(void); + +#endif diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 6679767d16b..fa6e7f76e05 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -72,7 +72,4 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, */ void zimage_dump(struct boot_params *base_ptr); -void setup_video(struct screen_info *screen_info); -void setup_efi_info(struct efi_info *efi_info); - #endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 65d9b3bd6a3..18757b29aa9 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -3,6 +3,7 @@ # (C) Copyright 2002-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +obj-y += bdinfo.o ifndef CONFIG_X86_64 ifndef CONFIG_TPL_BUILD obj-y += bios.o diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c new file mode 100644 index 00000000000..0cb79b01bd3 --- /dev/null +++ b/arch/x86/lib/bdinfo.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * x86-specific information for the 'bd' command + * + * Copyright 2021 Google LLC + */ + +#include <common.h> +#include <efi.h> +#include <init.h> +#include <asm/efi.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +void arch_print_bdinfo(void) +{ + bdinfo_print_num_l("prev table", gd->arch.table); + + if (IS_ENABLED(CONFIG_EFI_STUB)) + efi_show_bdinfo(); +} diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 9938c80a42b..7ce02226ef9 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -29,6 +29,7 @@ #include <asm/byteorder.h> #include <asm/bootm.h> #include <asm/bootparam.h> +#include <asm/efi.h> #include <asm/global_data.h> #ifdef CONFIG_SYS_COREBOOT #include <asm/arch/timestamp.h> |