diff options
Diffstat (limited to 'arch')
121 files changed, 3628 insertions, 2822 deletions
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 5169fc627fa..08f9e7dceac 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -8,6 +8,7 @@ #include <asm/global_data.h> #include <linux/bitops.h> #include <linux/compiler.h> +#include <linux/errno.h> #include <linux/kernel.h> #include <linux/log2.h> #include <asm/arcregs.h> @@ -819,3 +820,8 @@ void sync_n_cleanup_cache_all(void) __ic_entire_invalidate(); } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index da6f1174934..cf08fe63f1e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1128,7 +1128,6 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL - select GICV2 select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL @@ -1150,6 +1149,7 @@ config ARCH_SOCFPGA select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ TARGET_SOCFPGA_SOC64 + select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 5b87a3af91b..71b8ad0f71d 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -5,6 +5,7 @@ */ #include <cpu_func.h> #include <asm/cache.h> +#include <linux/errno.h> #include <linux/types.h> #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) @@ -88,3 +89,8 @@ void enable_caches(void) dcache_enable(); #endif } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index d11420d2fdd..371dc92cd46 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -6,6 +6,7 @@ */ #include <cpu_func.h> #include <asm/cache.h> +#include <linux/errno.h> #include <linux/types.h> #include <asm/armv7.h> #include <asm/utils.h> @@ -209,3 +210,8 @@ __weak void v7_outer_cache_flush_all(void) {} __weak void v7_outer_cache_inval_all(void) {} __weak void v7_outer_cache_flush_range(u32 start, u32 end) {} __weak void v7_outer_cache_inval_range(u32 start, u32 end) {} + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/arm/cpu/armv7/exception_level.c b/arch/arm/cpu/armv7/exception_level.c index 7baade61b07..a55c158ce51 100644 --- a/arch/arm/cpu/armv7/exception_level.c +++ b/arch/arm/cpu/armv7/exception_level.c @@ -11,9 +11,9 @@ #include <bootm.h> #include <cpu_func.h> #include <log.h> +#include <setjmp.h> #include <asm/armv7.h> #include <asm/secure.h> -#include <asm/setjmp.h> /** * entry_non_secure() - entry point when switching to non-secure mode @@ -24,7 +24,7 @@ * * @non_secure_jmp: jump buffer for restoring stack and registers */ -static void entry_non_secure(struct jmp_buf_data *non_secure_jmp) +static void entry_non_secure(jmp_buf non_secure_jmp) { dcache_enable(); debug("Reached non-secure mode\n"); @@ -42,10 +42,10 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp) void switch_to_non_secure_mode(void) { static bool is_nonsec; - struct jmp_buf_data non_secure_jmp; + jmp_buf non_secure_jmp; if (armv7_boot_nonsec() && !is_nonsec) { - if (setjmp(&non_secure_jmp)) + if (setjmp(non_secure_jmp)) return; dcache_disable(); /* flush cache before switch to HYP */ armv7_init_nonsec(); diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index a6c844b7e3d..72b7b7d082c 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -26,8 +26,8 @@ WEAK(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ -#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr sp, =CONFIG_SPL_STACK +#if CONFIG_IS_ENABLED(HAVE_INIT_STACK) + ldr sp, =CONFIG_VAL(STACK) #else ldr sp, =SYS_INIT_SP_ADDR #endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b63481b43ca..959251957de 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -279,8 +279,8 @@ ENTRY(cpu_init_cp15) orr r2, r4, r2 @ r2 has combined CPU variant + revision /* Early stack for ERRATA that needs into call C code */ -#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr r0, =(CONFIG_SPL_STACK) +#if CONFIG_IS_ENABLED(HAVE_INIT_STACK) + ldr r0, =CONFIG_VAL(STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) #endif diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index b6d08b7aad7..8e7db734055 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -11,6 +11,7 @@ #include <asm/cache.h> #include <asm/io.h> #include <linux/bitops.h> +#include <linux/errno.h> /* Cache maintenance operation registers */ @@ -370,3 +371,8 @@ void enable_caches(void) dcache_enable(); #endif } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 5d6953ffedd..12ae9bd0603 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -14,6 +14,7 @@ #include <asm/global_data.h> #include <asm/system.h> #include <asm/armv8/mmu.h> +#include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -421,7 +422,7 @@ static int count_ranges(void) return count; } -#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK) #define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) enum walker_state { @@ -568,6 +569,20 @@ static void pretty_print_table_attrs(u64 pte) static void pretty_print_block_attrs(u64 pte) { u64 attrs = pte & PMD_ATTRINDX_MASK; + u64 perm_attrs = pte & PMD_ATTRMASK; + char mem_attrs[16] = { 0 }; + int cnt = 0; + + if (perm_attrs & PTE_BLOCK_PXN) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN "); + if (perm_attrs & PTE_BLOCK_UXN) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN "); + if (perm_attrs & PTE_BLOCK_RO) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO"); + if (!mem_attrs[0]) + snprintf(mem_attrs, sizeof(mem_attrs), "RWX "); + + printf(" | %-10s", mem_attrs); switch (attrs) { case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): @@ -613,6 +628,7 @@ static void print_pte(u64 pte, int level) { if (PTE_IS_TABLE(pte, level)) { printf(" %-5s", "Table"); + printf(" %-12s", "|"); pretty_print_table_attrs(pte); } else { pretty_print_pte_type(pte); @@ -642,9 +658,9 @@ static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int lev printf("%*s", indent * 2, ""); if (PTE_IS_TABLE(start_attrs, level)) - printf("[%#011llx]%14s", _addr, ""); + printf("[%#016llx]%19s", _addr, ""); else - printf("[%#011llx - %#011llx]", _addr, end); + printf("[%#016llx - %#016llx]", _addr, end); printf("%*s | ", (3 - level) * 2, ""); print_pte(start_attrs, level); @@ -952,61 +968,93 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(real_start, real_start + real_size); } -/* - * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits. - * The procecess is break-before-make. The target region will be marked as - * invalid during the process of changing. - */ -void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs) { int level; u64 r, size, start; - start = addr; - size = siz; /* * Loop through the address range until we find a page granule that fits - * our alignment constraints, then set it to "invalid". + * our alignment constraints and set the new permissions */ + start = addr; + size = siz; while (size > 0) { for (level = 1; level < 4; level++) { - /* Set PTE to fault */ - r = set_one_region(start, size, PTE_TYPE_FAULT, true, - level); + /* Set PTE to new attributes */ + r = set_one_region(start, size, attrs, true, level); if (r) { - /* PTE successfully invalidated */ + /* PTE successfully updated */ size -= r; start += r; break; } } } - flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); +} + +/* + * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits. + * The procecess is break-before-make. The target region will be marked as + * invalid during the process of changing. + */ +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +{ + int level; + u64 r, size, start; + start = addr; + size = siz; /* * Loop through the address range until we find a page granule that fits - * our alignment constraints, then set it to the new cache attributes + * our alignment constraints, then set it to "invalid". */ - start = addr; - size = siz; while (size > 0) { for (level = 1; level < 4; level++) { - /* Set PTE to new attributes */ - r = set_one_region(start, size, attrs, true, level); + /* Set PTE to fault */ + r = set_one_region(start, size, PTE_TYPE_FAULT, true, + level); if (r) { - /* PTE successfully updated */ + /* PTE successfully invalidated */ size -= r; start += r; break; } } } + flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); + + mmu_change_region_attr_nobreak(addr, siz, attrs); +} + +int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_TYPE_VALID; + + switch (perm) { + case MMU_ATTR_RO: + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO; + break; + case MMU_ATTR_RX: + attrs |= PTE_BLOCK_RO; + break; + case MMU_ATTR_RW: + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN; + break; + default: + log_err("Unknown attribute %d\n", perm); + return -EINVAL; + } + + mmu_change_region_attr_nobreak(addr, size, attrs); + + return 0; } #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ @@ -1112,3 +1160,8 @@ void __weak enable_caches(void) icache_enable(); dcache_enable(); } + +void arch_dump_mem_attrs(void) +{ + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); +} diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c index 85c78f55789..746737861e7 100644 --- a/arch/arm/cpu/armv8/exception_level.c +++ b/arch/arm/cpu/armv8/exception_level.c @@ -11,8 +11,8 @@ #include <bootm.h> #include <cpu_func.h> #include <log.h> +#include <setjmp.h> #include <asm/cache.h> -#include <asm/setjmp.h> /** * entry_non_secure() - entry point when switching to non-secure mode @@ -23,7 +23,7 @@ * * @non_secure_jmp: jump buffer for restoring stack and registers */ -static void entry_non_secure(struct jmp_buf_data *non_secure_jmp) +static void entry_non_secure(jmp_buf non_secure_jmp) { dcache_enable(); debug("Reached non-secure mode\n"); @@ -42,11 +42,11 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp) */ void switch_to_non_secure_mode(void) { - struct jmp_buf_data non_secure_jmp; + jmp_buf non_secure_jmp; /* On AArch64 we need to make sure we call our payload in < EL3 */ if (current_el() == 3) { - if (setjmp(&non_secure_jmp)) + if (setjmp(non_secure_jmp)) return; dcache_disable(); /* flush cache before switch to EL2 */ diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 259b49ff364..492353c93df 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -5,23 +5,28 @@ #include <spl.h> +char __data_start[0] __section(".__data_start"); char __data_save_start[0] __section(".__data_save_start"); char __data_save_end[0] __section(".__data_save_end"); u32 cold_reboot_flag = 1; +u32 __weak reset_flag(void) +{ + return 1; +} + void spl_save_restore_data(void) { u32 data_size = __data_save_end - __data_save_start; + cold_reboot_flag = reset_flag(); if (cold_reboot_flag == 1) { /* Save data section to data_save section */ - memcpy(__data_save_start, __data_save_start - data_size, - data_size); + memcpy(__data_save_start, __data_start, data_size); } else { /* Restore the data_save section to data section */ - memcpy(__data_save_start - data_size, __data_save_start, - data_size); + memcpy(__data_start, __data_save_start, data_size); } cold_reboot_flag++; diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index fed69644b55..c4f83ec9cfc 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -37,6 +37,7 @@ SECTIONS .data : { . = ALIGN(8); + *(.__data_start) *(.data*) } >.sram diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 857f44412e0..f4ce98c82c8 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -36,9 +36,18 @@ SECTIONS __efi_runtime_stop = .; } +#ifdef CONFIG_MMU_PGPROT + .text_rest ALIGN(CONSTANT(COMMONPAGESIZE)) : +#else .text_rest : +#endif { + __text_start = .; *(.text*) +#ifdef CONFIG_MMU_PGPROT + . = ALIGN(CONSTANT(COMMONPAGESIZE)); +#endif + __text_end = .; } #ifdef CONFIG_ARMV8_PSCI @@ -97,35 +106,43 @@ SECTIONS LONG(0x1d1071c); /* Must output something to reset LMA */ } #endif - - . = ALIGN(8); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(8); - .data : { - *(.data*) + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; } - . = ALIGN(8); - - . = .; +#ifdef CONFIG_MMU_PGPROT + .rodata ALIGN(CONSTANT(COMMONPAGESIZE)): { +#else + .rodata ALIGN(8) : { +#endif + __start_rodata = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } - . = ALIGN(8); - __u_boot_list : { + __u_boot_list ALIGN(8) : { KEEP(*(SORT(__u_boot_list*))); +#ifdef CONFIG_MMU_PGPROT + . = ALIGN(CONSTANT(COMMONPAGESIZE)); +#endif + __end_rodata = .; } - .efi_runtime_rel : { - __efi_runtime_rel_start = .; - *(.rel*.efi_runtime) - *(.rel*.efi_runtime.*) - __efi_runtime_rel_stop = .; +#ifdef CONFIG_MMU_PGPROT + .data ALIGN(CONSTANT(COMMONPAGESIZE)) : { +#else + .data ALIGN(8) : { +#endif + __start_data = .; + *(.data*) } . = ALIGN(8); __image_copy_end = .; - .rela.dyn : { + .rela.dyn ALIGN(8) : { __rel_dyn_start = .; *(.rela*) __rel_dyn_end = .; @@ -136,11 +153,15 @@ SECTIONS /* * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0 */ - .bss ALIGN(8) : { + .bss ADDR(.rela.dyn) (OVERLAY) : { __bss_start = .; *(.bss*) . = ALIGN(8); __bss_end = .; +#ifdef CONFIG_MMU_PGPROT + . = ALIGN(CONSTANT(COMMONPAGESIZE)); +#endif + __end_data = .; } /DISCARD/ : { *(.dynsym) } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 267b0179a5f..73231824526 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -121,6 +121,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra124-nyan-big.dtb \ tegra124-cei-tk1-som.dtb \ tegra124-venice2.dtb \ + tegra124-xiaomi-mocha.dtb \ tegra186-p2771-0000-000.dtb \ tegra186-p2771-0000-500.dtb \ tegra210-p2371-0000.dtb \ @@ -795,7 +796,6 @@ dtb-y += \ imx6q-icore-rqs.dtb \ imx6q-kp.dtb \ imx6q-logicpd.dtb \ - imx6q-lxr.dtb \ imx6q-marsboard.dtb \ imx6q-mccmon6.dtb\ imx6q-nitrogen6x.dtb \ @@ -918,8 +918,7 @@ dtb-$(CONFIG_ARCH_IMX9) += \ imx93-var-som-symphony.dtb \ imx93-phyboard-segin.dtb -dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ - imxrt1020-evk.dtb \ +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RZA1) += \ diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 99867d2bf8e..7f00014f13c 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -82,6 +82,11 @@ }; }; +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; +}; + &ebi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; @@ -171,10 +176,20 @@ &macb0 { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; status = "okay"; }; &pinctrl { + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + ebi { pinctrl_ebi_data_0_7: ebi-data-lsb-0 { atmel,pins = @@ -217,6 +232,22 @@ }; }; + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + }; + nand { pinctrl_nand_oe_we: nand-oe-we-0 { atmel,pins = @@ -240,6 +271,36 @@ <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; }; + sdhci0 { + pinctrl_sdhci0: sdhci0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A + (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ + AT91_PIOA 16 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ + AT91_PIOA 18 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ + }; + }; + + sdhci1 { + pinctrl_sdhci1: sdhci1 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ + AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ + AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ + }; + }; + usb1 { pinctrl_usb_default: usb_default { atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE @@ -248,6 +309,16 @@ }; }; +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi index 4ea4202737c..8d496205523 100644 --- a/arch/arm/dts/at91sam9260.dtsi +++ b/arch/arm/dts/at91sam9260.dtsi @@ -401,51 +401,11 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; - pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x600>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - >; atmel,mux-mask = < /* A B */ @@ -767,6 +727,42 @@ atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; }; dbgu: serial@fffff200 { diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi index 804340e75d9..65e0e4f0de0 100644 --- a/arch/arm/dts/at91sam9261.dtsi +++ b/arch/arm/dts/at91sam9261.dtsi @@ -286,51 +286,12 @@ status = "disabled"; }; - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; - pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x600>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - >; + atmel,mux-mask = /* A B */ <0xffffffff 0xfffffff7>, /* pioA */ @@ -573,6 +534,42 @@ <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi index 98cdd8ebcca..55b79667564 100644 --- a/arch/arm/dts/at91sam9263.dtsi +++ b/arch/arm/dts/at91sam9263.dtsi @@ -404,12 +404,6 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; - reg = <0xfffff200 0x200 - 0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; atmel,mux-mask = < /* A B */ @@ -719,66 +713,65 @@ }; }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - bootph-all; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + bootph-all; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - bootph-all; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + bootph-all; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - bootph-all; + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + bootph-all; + }; }; dbgu: serial@ffffee00 { diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi index d0bcd797359..63a061354e4 100644 --- a/arch/arm/dts/at91sam9g45.dtsi +++ b/arch/arm/dts/at91sam9g45.dtsi @@ -435,12 +435,6 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; - reg = <0xfffff200 0x200 - 0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; bootph-all; atmel,mux-mask = < @@ -854,61 +848,61 @@ AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ }; }; - }; - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioDE_clk>; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioDE_clk>; + }; }; dbgu: serial@ffffee00 { diff --git a/arch/arm/dts/at91sam9n12.dtsi b/arch/arm/dts/at91sam9n12.dtsi index cb3a0370b86..84089837013 100644 --- a/arch/arm/dts/at91sam9n12.dtsi +++ b/arch/arm/dts/at91sam9n12.dtsi @@ -492,11 +492,6 @@ #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; atmel,mux-mask = < /* A B C */ @@ -795,54 +790,54 @@ atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; }; }; - }; - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - bootph-all; - }; + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + bootph-all; + }; - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - bootph-all; - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + bootph-all; + }; - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - bootph-all; - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + bootph-all; + }; - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - bootph-all; + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + bootph-all; + }; }; dbgu: serial@fffff200 { diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi index b855c8fe0fe..3b99de21058 100644 --- a/arch/arm/dts/at91sam9rl.dtsi +++ b/arch/arm/dts/at91sam9rl.dtsi @@ -386,11 +386,6 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; atmel,mux-mask = /* A B */ @@ -768,54 +763,54 @@ <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; - }; - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - bootph-all; + pioD: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + bootph-all; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi index 5fca9b13c27..4c6d8b9bb65 100644 --- a/arch/arm/dts/at91sam9x5.dtsi +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -461,14 +461,8 @@ #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - 0xfffffa00 0x200 /* pioD */ - >; bootph-all; - /* shared pinctrl settings */ dbgu { bootph-all; @@ -831,52 +825,52 @@ atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; }; }; - }; - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <19>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; }; ssc0: ssc@f0010000 { diff --git a/arch/arm/dts/imx6q-lxr.dts b/arch/arm/dts/imx6q-lxr.dts deleted file mode 100644 index ae4f8eeb105..00000000000 --- a/arch/arm/dts/imx6q-lxr.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2024 Comvetia AG - -/dts-v1/; -#include "imx6q-phytec-pfla02.dtsi" - -/ { - model = "COMVETIA QSoIP LXR-2"; - compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - spi { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_gpio>; - sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; - num-chipselects = <0>; - #address-cells = <1>; - #size-cells = <0>; - - fpga@0 { - compatible = "altr,fpga-passive-serial"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fpga>; - nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usdhc3 { - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_fpga: fpgagrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - >; - }; - - pinctrl_spi_gpio: spigpiogrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi deleted file mode 100644 index 500944bd2a0..00000000000 --- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include "imx6q.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi deleted file mode 100644 index c0c47adc586..00000000000 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ /dev/null @@ -1,467 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - enable-active-high; - }; - - gpio_leds: leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - compatible = "gpio-leds"; - - led_green: led-green { - label = "phyflex:green"; - gpios = <&gpio1 30 0>; - }; - - led_red: led-red { - label = "phyflex:red"; - gpios = <&gpio2 31 0>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - - som_flash: flash@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-duration = <10>; /* in msecs */ - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - phy-supply = <&vdd_eth_io_reg>; - status = "disabled"; - - fec_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - som_eeprom: eeprom@50 { - compatible = "catalyst,24c32", "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pmic@58 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ - #interrupt-cells = <2>; - interrupt-controller; - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - - da9063_rtc: rtc { - compatible = "dlg,da9063-rtc"; - }; - - da9063_wdog: watchdog { - compatible = "dlg,da9063-watchdog"; - }; - - onkey { - compatible = "dlg,da9063-onkey"; - status = "disabled"; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; -}; - -&iomuxc { - imx6q-phytec-pfla02 { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_sd1_reg>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_sd0_reg>; - status = "disabled"; -}; - -&wdog1 { - /* - * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also - * used for reboot, does not reset all external PMIC voltages on reset. - */ - status = "disabled"; -}; diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts deleted file mode 100644 index 6a9c10decf5..00000000000 --- a/arch/arm/dts/imxrt1050-evk.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -/dts-v1/; -#include "imxrt1050.dtsi" -#include "imxrt1050-pinfunc.h" - -/ { - model = "NXP IMXRT1050-evk board"; - compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; - - chosen { - stdout-path = &lpuart1; - }; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - mmc0 = &usdhc1; - serial0 = &lpuart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x2000000>; - }; -}; - -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 - >; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc0>; - pinctrl-1 = <&pinctrl_usdhc0>; - pinctrl-2 = <&pinctrl_usdhc0>; - pinctrl-3 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h deleted file mode 100644 index 22c14a3262a..00000000000 --- a/arch/arm/dts/imxrt1050-pinfunc.h +++ /dev/null @@ -1,993 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H -#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H - -#define IMX_PAD_SION 0x40000000 - -/* - * The pin function ID is a tuple of - * <mux_reg conf_reg input_reg mux_mode input_val> - */ - -#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 -#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 -#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 - -#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 - -#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 - -#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 - -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi deleted file mode 100644 index a25eae9bd38..00000000000 --- a/arch/arm/dts/imxrt1050.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -#include "armv7-m.dtsi" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/imxrt1050-clock.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - osc3M: osc3M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3000000>; - }; - }; - - soc { - lpuart1: serial@40184000 { - compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x40184000 0x4000>; - interrupts = <20>; - clocks = <&clks IMXRT1050_CLK_LPUART1>; - clock-names = "ipg"; - status = "disabled"; - }; - - iomuxc: pinctrl@401f8000 { - compatible = "fsl,imxrt1050-iomuxc"; - reg = <0x401f8000 0x4000>; - fsl,mux_mask = <0x7>; - }; - - anatop: anatop@400d8000 { - compatible = "fsl,imxrt-anatop"; - reg = <0x400d8000 0x4000>; - }; - - clks: clock-controller@400fc000 { - compatible = "fsl,imxrt1050-ccm"; - reg = <0x400fc000 0x4000>; - interrupts = <95>, <96>; - clocks = <&osc>; - clock-names = "osc"; - #clock-cells = <1>; - assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, - <&clks IMXRT1050_CLK_PLL1_BYPASS>, - <&clks IMXRT1050_CLK_PLL2_BYPASS>, - <&clks IMXRT1050_CLK_PLL3_BYPASS>, - <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, - <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, - <&clks IMXRT1050_CLK_PLL1_ARM>, - <&clks IMXRT1050_CLK_PLL2_SYS>, - <&clks IMXRT1050_CLK_PLL3_USB_OTG>, - <&clks IMXRT1050_CLK_PLL3_USB_OTG>, - <&clks IMXRT1050_CLK_PLL2_SYS>; - }; - - edma1: dma-controller@400e8000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x400e8000 0x4000>, - <0x400ec000 0x4000>; - dma-channels = <32>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; - clock-names = "dma", "dmamux0"; - clocks = <&clks IMXRT1050_CLK_DMA>, - <&clks IMXRT1050_CLK_DMA_MUX>; - }; - - usdhc1: mmc@402c0000 { - compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x402c0000 0x4000>; - interrupts = <110>; - clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, - <&clks IMXRT1050_CLK_AHB_PODF>, - <&clks IMXRT1050_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,wp-controller; - no-1-8-v; - max-frequency = <4000000>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - gpio1: gpio@401b8000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401b8000 0x4000>; - interrupts = <80>, <81>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@401bc000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401bc000 0x4000>; - interrupts = <82>, <83>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@401c0000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401c0000 0x4000>; - interrupts = <84>, <85>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@401c4000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401c4000 0x4000>; - interrupts = <86>, <87>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@400c0000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x400c0000 0x4000>; - interrupts = <88>, <89>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpt: timer@401ec000 { - compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; - reg = <0x401ec000 0x4000>; - interrupts = <100>; - clocks = <&osc3M>; - clock-names = "per"; - }; - }; -}; diff --git a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi index c255ae6530f..ee9e213be84 100644 --- a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi +++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07 - * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time) + * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 + * Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -13,6 +13,8 @@ #define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 +#define DDRSS_REGION_IDX 16 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -847,7 +849,7 @@ #define DDRSS_PHY_62_DATA 0x00000000 #define DDRSS_PHY_63_DATA 0x00000000 #define DDRSS_PHY_64_DATA 0x00000000 -#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_65_DATA 0x00000104 #define DDRSS_PHY_66_DATA 0x00000000 #define DDRSS_PHY_67_DATA 0x00000000 #define DDRSS_PHY_68_DATA 0x00000000 @@ -869,7 +871,7 @@ #define DDRSS_PHY_84_DATA 0x00100010 #define DDRSS_PHY_85_DATA 0x00100010 #define DDRSS_PHY_86_DATA 0x00100010 -#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_87_DATA 0x02000010 #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 @@ -1103,7 +1105,7 @@ #define DDRSS_PHY_318_DATA 0x00000000 #define DDRSS_PHY_319_DATA 0x00000000 #define DDRSS_PHY_320_DATA 0x00000000 -#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_321_DATA 0x00000104 #define DDRSS_PHY_322_DATA 0x00000000 #define DDRSS_PHY_323_DATA 0x00000000 #define DDRSS_PHY_324_DATA 0x00000000 @@ -1125,7 +1127,7 @@ #define DDRSS_PHY_340_DATA 0x00100010 #define DDRSS_PHY_341_DATA 0x00100010 #define DDRSS_PHY_342_DATA 0x00100010 -#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_343_DATA 0x02000010 #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 @@ -2181,7 +2183,7 @@ #define DDRSS_PHY_1396_DATA 0x0089FF00 #define DDRSS_PHY_1397_DATA 0x000C3F11 #define DDRSS_PHY_1398_DATA 0x01990000 -#define DDRSS_PHY_1399_DATA 0x000C3F11 +#define DDRSS_PHY_1399_DATA 0x000C3F91 #define DDRSS_PHY_1400_DATA 0x01990000 #define DDRSS_PHY_1401_DATA 0x3F0DFF11 #define DDRSS_PHY_1402_DATA 0x01990000 diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi index 9f50d7eae69..35202651221 100644 --- a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi +++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01 - * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time) + * AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 + * Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 1866MHz * Density (per channel): 8Gb @@ -12,6 +12,8 @@ #define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_1 933000000 #define DDRSS_PLL_FREQUENCY_2 933000000 +#define DDRSS_SDRAM_IDX 16 +#define DDRSS_REGION_IDX 17 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -402,10 +404,10 @@ #define DDRSS_CTL_386_DATA 0x01090903 #define DDRSS_CTL_387_DATA 0x05020201 #define DDRSS_CTL_388_DATA 0x0E081B1B -#define DDRSS_CTL_389_DATA 0x0008030E -#define DDRSS_CTL_390_DATA 0x0B12030E -#define DDRSS_CTL_391_DATA 0x0B120314 -#define DDRSS_CTL_392_DATA 0x12120814 +#define DDRSS_CTL_389_DATA 0x0008040E +#define DDRSS_CTL_390_DATA 0x0B120406 +#define DDRSS_CTL_391_DATA 0x0B120406 +#define DDRSS_CTL_392_DATA 0x12120806 #define DDRSS_CTL_393_DATA 0x01000000 #define DDRSS_CTL_394_DATA 0x07030701 #define DDRSS_CTL_395_DATA 0x04000103 @@ -417,8 +419,8 @@ #define DDRSS_CTL_401_DATA 0x00000200 #define DDRSS_CTL_402_DATA 0x00000693 #define DDRSS_CTL_403_DATA 0x00000E9C -#define DDRSS_CTL_404_DATA 0x03050202 -#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x37200404 #define DDRSS_CTL_406_DATA 0x000038C8 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 @@ -426,8 +428,8 @@ #define DDRSS_CTL_410_DATA 0x00000200 #define DDRSS_CTL_411_DATA 0x0000FF84 #define DDRSS_CTL_412_DATA 0x000237D0 -#define DDRSS_CTL_413_DATA 0x111F0402 -#define DDRSS_CTL_414_DATA 0x37200C0D +#define DDRSS_CTL_413_DATA 0x111A0402 +#define DDRSS_CTL_414_DATA 0x37200C09 #define DDRSS_CTL_415_DATA 0x000038C8 #define DDRSS_CTL_416_DATA 0x00000200 #define DDRSS_CTL_417_DATA 0x00000200 @@ -435,8 +437,8 @@ #define DDRSS_CTL_419_DATA 0x00000200 #define DDRSS_CTL_420_DATA 0x0000FF84 #define DDRSS_CTL_421_DATA 0x000237D0 -#define DDRSS_CTL_422_DATA 0x111F0402 -#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_422_DATA 0x111A0402 +#define DDRSS_CTL_423_DATA 0x00200C09 #define DDRSS_CTL_424_DATA 0x00000000 #define DDRSS_CTL_425_DATA 0x02000A00 #define DDRSS_CTL_426_DATA 0x00050003 @@ -939,7 +941,7 @@ #define DDRSS_PHY_64_DATA 0x00000000 #define DDRSS_PHY_65_DATA 0x00000000 #define DDRSS_PHY_66_DATA 0x00000000 -#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_67_DATA 0x00000104 #define DDRSS_PHY_68_DATA 0x00000000 #define DDRSS_PHY_69_DATA 0x00000000 #define DDRSS_PHY_70_DATA 0x00000000 @@ -964,7 +966,7 @@ #define DDRSS_PHY_89_DATA 0x00100010 #define DDRSS_PHY_90_DATA 0x00100010 #define DDRSS_PHY_91_DATA 0x00100010 -#define DDRSS_PHY_92_DATA 0x02040010 +#define DDRSS_PHY_92_DATA 0x02000010 #define DDRSS_PHY_93_DATA 0x00000005 #define DDRSS_PHY_94_DATA 0x51516042 #define DDRSS_PHY_95_DATA 0x31C06000 @@ -1195,7 +1197,7 @@ #define DDRSS_PHY_320_DATA 0x00000000 #define DDRSS_PHY_321_DATA 0x00000000 #define DDRSS_PHY_322_DATA 0x00000000 -#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_323_DATA 0x00000104 #define DDRSS_PHY_324_DATA 0x00000000 #define DDRSS_PHY_325_DATA 0x00000000 #define DDRSS_PHY_326_DATA 0x00000000 @@ -1220,7 +1222,7 @@ #define DDRSS_PHY_345_DATA 0x00100010 #define DDRSS_PHY_346_DATA 0x00100010 #define DDRSS_PHY_347_DATA 0x00100010 -#define DDRSS_PHY_348_DATA 0x02040010 +#define DDRSS_PHY_348_DATA 0x02000010 #define DDRSS_PHY_349_DATA 0x00000005 #define DDRSS_PHY_350_DATA 0x51516042 #define DDRSS_PHY_351_DATA 0x31C06000 @@ -1451,7 +1453,7 @@ #define DDRSS_PHY_576_DATA 0x00000000 #define DDRSS_PHY_577_DATA 0x00000000 #define DDRSS_PHY_578_DATA 0x00000000 -#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_579_DATA 0x00000104 #define DDRSS_PHY_580_DATA 0x00000000 #define DDRSS_PHY_581_DATA 0x00000000 #define DDRSS_PHY_582_DATA 0x00000000 @@ -1476,7 +1478,7 @@ #define DDRSS_PHY_601_DATA 0x00100010 #define DDRSS_PHY_602_DATA 0x00100010 #define DDRSS_PHY_603_DATA 0x00100010 -#define DDRSS_PHY_604_DATA 0x02040010 +#define DDRSS_PHY_604_DATA 0x02000010 #define DDRSS_PHY_605_DATA 0x00000005 #define DDRSS_PHY_606_DATA 0x51516042 #define DDRSS_PHY_607_DATA 0x31C06000 @@ -1707,7 +1709,7 @@ #define DDRSS_PHY_832_DATA 0x00000000 #define DDRSS_PHY_833_DATA 0x00000000 #define DDRSS_PHY_834_DATA 0x00000000 -#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_835_DATA 0x00000104 #define DDRSS_PHY_836_DATA 0x00000000 #define DDRSS_PHY_837_DATA 0x00000000 #define DDRSS_PHY_838_DATA 0x00000000 @@ -1732,7 +1734,7 @@ #define DDRSS_PHY_857_DATA 0x00100010 #define DDRSS_PHY_858_DATA 0x00100010 #define DDRSS_PHY_859_DATA 0x00100010 -#define DDRSS_PHY_860_DATA 0x02040010 +#define DDRSS_PHY_860_DATA 0x02000010 #define DDRSS_PHY_861_DATA 0x00000005 #define DDRSS_PHY_862_DATA 0x51516042 #define DDRSS_PHY_863_DATA 0x31C06000 @@ -2699,7 +2701,7 @@ #define DDRSS_PHY_1824_DATA 0x0F0F0804 #define DDRSS_PHY_1825_DATA 0x00800120 #define DDRSS_PHY_1826_DATA 0x00041B42 -#define DDRSS_PHY_1827_DATA 0x00005201 +#define DDRSS_PHY_1827_DATA 0x00004201 #define DDRSS_PHY_1828_DATA 0x00000000 #define DDRSS_PHY_1829_DATA 0x00000000 #define DDRSS_PHY_1830_DATA 0x00000000 @@ -2760,7 +2762,7 @@ #define DDRSS_PHY_1885_DATA 0x00000002 #define DDRSS_PHY_1886_DATA 0x00000000 #define DDRSS_PHY_1887_DATA 0x00000000 -#define DDRSS_PHY_1888_DATA 0x00000AC4 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 #define DDRSS_PHY_1889_DATA 0x04000004 #define DDRSS_PHY_1890_DATA 0x00000000 #define DDRSS_PHY_1891_DATA 0x00001142 @@ -2789,10 +2791,10 @@ #define DDRSS_PHY_1914_DATA 0x0089FF00 #define DDRSS_PHY_1915_DATA 0x000C3F11 #define DDRSS_PHY_1916_DATA 0x01990000 -#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1917_DATA 0x000C3F91 #define DDRSS_PHY_1918_DATA 0x01990000 #define DDRSS_PHY_1919_DATA 0x3F0DFF11 #define DDRSS_PHY_1920_DATA 0x00EF0000 #define DDRSS_PHY_1921_DATA 0x00018011 #define DDRSS_PHY_1922_DATA 0x0089FF00 -#define DDRSS_PHY_1923_DATA 0x20040004 +#define DDRSS_PHY_1923_DATA 0x20040006 diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi index f6643520153..c7e33ba50b9 100644 --- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi +++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02 - * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time) + * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 + * Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 1600MHz * Density (per channel): 16Gb @@ -941,7 +941,7 @@ #define DDRSS_PHY_64_DATA 0x00000000 #define DDRSS_PHY_65_DATA 0x00000000 #define DDRSS_PHY_66_DATA 0x00000000 -#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_67_DATA 0x00000104 #define DDRSS_PHY_68_DATA 0x00000000 #define DDRSS_PHY_69_DATA 0x00000000 #define DDRSS_PHY_70_DATA 0x00000000 @@ -1197,7 +1197,7 @@ #define DDRSS_PHY_320_DATA 0x00000000 #define DDRSS_PHY_321_DATA 0x00000000 #define DDRSS_PHY_322_DATA 0x00000000 -#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_323_DATA 0x00000104 #define DDRSS_PHY_324_DATA 0x00000000 #define DDRSS_PHY_325_DATA 0x00000000 #define DDRSS_PHY_326_DATA 0x00000000 @@ -1453,7 +1453,7 @@ #define DDRSS_PHY_576_DATA 0x00000000 #define DDRSS_PHY_577_DATA 0x00000000 #define DDRSS_PHY_578_DATA 0x00000000 -#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_579_DATA 0x00000104 #define DDRSS_PHY_580_DATA 0x00000000 #define DDRSS_PHY_581_DATA 0x00000000 #define DDRSS_PHY_582_DATA 0x00000000 @@ -1709,7 +1709,7 @@ #define DDRSS_PHY_832_DATA 0x00000000 #define DDRSS_PHY_833_DATA 0x00000000 #define DDRSS_PHY_834_DATA 0x00000000 -#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_835_DATA 0x00000104 #define DDRSS_PHY_836_DATA 0x00000000 #define DDRSS_PHY_837_DATA 0x00000000 #define DDRSS_PHY_838_DATA 0x00000000 diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi index d92e3ce048b..8def52b07f4 100644 --- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60 - * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time) + * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 + * Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb @@ -12,6 +12,8 @@ #define DDRSS_PLL_FHS_CNT 6 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 +#define DDRSS_REGION_IDX 17 #define DDRSS_CTL_0_DATA 0x00000A00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -334,7 +336,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0A000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -901,7 +903,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01000080 -#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1159,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01000080 -#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2152,7 +2154,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000100 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi index 491412119b1..1b5fabc3dd1 100644 --- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 - * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time) + * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 + * Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb @@ -12,6 +12,8 @@ #define DDRSS_PLL_FHS_CNT 6 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 +#define DDRSS_REGION_IDX 15 #define DDRSS_CTL_0_DATA 0x00000A00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -178,7 +180,7 @@ #define DDRSS_CTL_162_DATA 0x0E0A0907 #define DDRSS_CTL_163_DATA 0x0A090000 #define DDRSS_CTL_164_DATA 0x0A090701 -#define DDRSS_CTL_165_DATA 0x0000000E +#define DDRSS_CTL_165_DATA 0x0000080E #define DDRSS_CTL_166_DATA 0x00040003 #define DDRSS_CTL_167_DATA 0x00000007 #define DDRSS_CTL_168_DATA 0x00000000 @@ -334,7 +336,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0A000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -901,7 +903,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01000080 -#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1159,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01000080 -#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2152,7 +2154,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000100 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index b6d2c816acc..55337179f9f 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -14,6 +14,24 @@ spi0 = &ospi0; }; + sysinfo { + compatible = "siemens,sysinfo-iot2050"; + /* TI_SRAM_SCRATCH_BOARD_EEPROM_START */ + offset = <0x40280000>; + bootph-all; + + smbios { + system { + manufacturer = "SIEMENS AG"; + product = "SIMATIC IOT2050"; + }; + + baseboard { + manufacturer = "SIEMENS AG"; + }; + }; + }; + leds { bootph-all; status-led-red { diff --git a/arch/arm/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/dts/nuvoton-common-npcm7xx.dtsi index feb88872fc7..093d5427e30 100644 --- a/arch/arm/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm7xx.dtsi @@ -95,6 +95,11 @@ compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; reg = <0x801000 0x6C>; }; + + timer0: timer@f0801068 { + compatible = "nuvoton,npcm750-timer"; + reg = <0x801068 0x8>; + }; }; ahb { @@ -245,13 +250,6 @@ status = "disabled"; }; - timer0: timer@8000 { - compatible = "nuvoton,npcm750-timer"; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x8000 0x1C>; - clocks = <&clk NPCM7XX_CLK_TIMER>; - }; - watchdog0: watchdog@801C { compatible = "nuvoton,npcm750-wdt"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 3b684fc63d5..60de9140226 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -17,6 +17,7 @@ /{ model = "Microchip SAM9X60 SoC"; compatible = "microchip,sam9x60"; + interrupt-parent = <&aic>; aliases { serial0 = &dbgu; @@ -122,8 +123,6 @@ assigned-clock-rates = <100000000>; assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0>; }; sdhci1: sdhci-host@90000000 { @@ -135,8 +134,6 @@ assigned-clock-rates = <100000000>; assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>; }; apb { @@ -176,8 +173,6 @@ macb0: ethernet@f802c000 { compatible = "cdns,sam9x60-macb", "cdns,macb"; reg = <0xf802c000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; clock-names = "hclk", "pclk"; clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; status = "disabled"; @@ -199,11 +194,17 @@ reg = <0xffffea00 0x100>; }; + aic: interrupt-controller@fffff100 { + compatible = "microchip,sam9x60-aic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffff100 0x100>; + atmel,external-irqs = <31>; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; clock-names = "usart"; }; @@ -211,99 +212,63 @@ pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; - compatible = "microchip,sam9x60-pinctrl", "simple-bus"; + compatible = "microchip,sam9x60-pinctrl", "simple-mfd"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - 0xfffffa00 0x200>; /* pioD */ - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; - }; - }; - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ - }; + /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xef00019d /* pioA */ + 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ + 0xffffffff 0xffffffff 0xf83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; - sdhci0 { - pinctrl_sdhci0: sdhci0 { - atmel,pins = - <AT91_PIOA 17 AT91_PERIPH_A - (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ - AT91_PIOA 16 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ - AT91_PIOA 15 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ - AT91_PIOA 18 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ - AT91_PIOA 19 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ - AT91_PIOA 20 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <26>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; - sdhci1 { - pinctrl_sdhci1: sdhci1 { - atmel,pins = - <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ - AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ - AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ - AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ - AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ - AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 74016f5e288..6521585ee9c 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -78,79 +78,15 @@ }; }; }; - - pinctrl { - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; - }; - }; - - ebi { - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; - }; - - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; - }; - }; - - pinctrl_qspi: qspi { - atmel,pins = - <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE - AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE - AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; - }; - - pinctrl_flx0: flx0_default { - atmel,pins = - <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE - AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; - }; - - pinctrl_onewire_tm_default: onewire_tm_default { - atmel,pins = - <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; - }; - - usb1 { - pinctrl_usb_default: usb_default { - atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE - AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; - }; - }; - - }; }; }; }; +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; +}; + &ebi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; @@ -218,9 +154,148 @@ &macb0 { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; status = "okay"; }; +&pinctrl { + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + qspi { + pinctrl_qspi: qspi { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + }; + + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + }; + + flexcom { + pinctrl_flx0: flx0_default { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + }; + + pinctrl_onewire_tm_default: onewire_tm_default { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + sdhci0 { + pinctrl_sdhci0: sdhci0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A + (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ + AT91_PIOA 16 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ + AT91_PIOA 18 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ + }; + }; + + sdhci1 { + pinctrl_sdhci1: sdhci1 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ + AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ + AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ + }; + }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi index 4c03a302ec7..10d6e74586d 100644 --- a/arch/arm/dts/sama5d3.dtsi +++ b/arch/arm/dts/sama5d3.dtsi @@ -492,12 +492,6 @@ 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ >; - reg = <0xfffff200 0x100 /* pioA */ - 0xfffff400 0x100 /* pioB */ - 0xfffff600 0x100 /* pioC */ - 0xfffff800 0x100 /* pioD */ - 0xfffffa00 0x100 /* pioE */ - >; /* shared pinctrl settings */ adc0 { @@ -873,66 +867,66 @@ AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ }; }; - }; - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - bootph-all; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + bootph-all; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - bootph-all; + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + bootph-all; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi index 5e2c9a1db2f..482cf03e61b 100644 --- a/arch/arm/dts/sama5d4.dtsi +++ b/arch/arm/dts/sama5d4.dtsi @@ -1361,62 +1361,6 @@ status = "disabled"; }; - pioA: gpio@fc06a000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06a000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fc06b000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06b000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fc06c000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06c000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; - - pioD: gpio@fc068000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc068000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - - pioE: gpio@fc06d000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06d000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - }; - pinctrl@fc06a000 { bootph-all; #address-cells = <1>; @@ -1433,12 +1377,62 @@ 0x0003ff00 0x8002a800 0x00000000 /* pioD */ 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ >; - reg = < 0xfc06a000 0x100 - 0xfc06b000 0x100 - 0xfc06c000 0x100 - 0xfc068000 0x100 - 0xfc06d000 0x100 - >; + + pioA: gpio@fc06a000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06a000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fc06b000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06b000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fc06c000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06c000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; + + pioD: gpio@fc068000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc068000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + }; + + pioE: gpio@fc06d000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06d000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + }; /* pinctrl pin settings */ adc0 { diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index a8167e5c14a..8d6503dd091 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_soc64_fit-u-boot.dtsi" @@ -13,6 +14,659 @@ #size-cells = <2>; bootph-all; }; + + soc { + bootph-all; + + socfpga_ccu_config: socfpga-ccu-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUMIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DII2_GICREGS */ + <0x00000424 0x0001d000 0xffffffff>, + <0x00000428 0x00000000 0x000000ff>, + <0x00000420 0xc0800400 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* PSS */ + <0x00000404 0x00010000 0xffffffff>, + <0x00000408 0x00000000 0x000000ff>, + <0x00000400 0xC0F00000 0xc1f03e1f>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUMIFSR0 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUMIFSR1 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DMI0 */ + i_ccu_dmi0@1c007000 { + reg = <0x1c007000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000001 0x00000003>, + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + + /* DMI1 */ + i_ccu_dmi0@1c008000 { + reg = <0x1c008000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000001 0x00000003>, + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + }; + + socfpga_firewall_config: socfpga-firewall-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* L4 peripherals firewall */ + noc_fw_l4_per@10d21000 { + reg = <0x10d21000 0x0000008c>; + intel,offset-settings = + /* NAND */ + <0x00000000 0x01010001 0x01010001>, + /* USB0 */ + <0x0000000c 0x01010001 0x01010001>, + /* USB1 */ + <0x00000010 0x01010001 0x01010001>, + /* SPI_MAIN0 */ + <0x0000001c 0x01010301 0x01010301>, + /* SPI_MAIN1 */ + <0x00000020 0x01010301 0x01010301>, + /* SPI_SECONDARY0 */ + <0x00000024 0x01010301 0x01010301>, + /* SPI_SECONDARY1 */ + <0x00000028 0x01010301 0x01010301>, + /* EMAC0 */ + <0x0000002c 0x01010001 0x01010001>, + /* EMAC1 */ + <0x00000030 0x01010001 0x01010001>, + /* EMAC2 */ + <0x00000034 0x01010001 0x01010001>, + /* SDMMC */ + <0x00000040 0x01010001 0x01010001>, + /* GPIO0 */ + <0x00000044 0x01010301 0x01010301>, + /* GPIO1 */ + <0x00000048 0x01010301 0x01010301>, + /* I2C0 */ + <0x00000050 0x01010301 0x01010301>, + /* I2C1 */ + <0x00000054 0x01010301 0x01010301>, + /* I2C2 */ + <0x00000058 0x01010301 0x01010301>, + /* I2C3 */ + <0x0000005c 0x01010301 0x01010301>, + /* I2C4 */ + <0x00000060 0x01010301 0x01010301>, + /* SP_TIMER0 */ + <0x00000064 0x01010301 0x01010301>, + /* SP_TIMER1 */ + <0x00000068 0x01010301 0x01010301>, + /* UART0 */ + <0x0000006c 0x01010301 0x01010301>, + /* UART1 */ + <0x00000070 0x01010301 0x01010301>, + /* I3C0 */ + <0x00000074 0x01010301 0x01010301>, + /* I3C1 */ + <0x00000078 0x01010301 0x01010301>, + /* DMA0 */ + <0x0000007c 0x01010001 0x01010001>, + /* DMA1 */ + <0x00000080 0x01010001 0x01010001>, + /* COMBO_PHY */ + <0x00000084 0x01010001 0x01010001>, + /* NAND_SDMA */ + <0x00000088 0x01010301 0x01010301>; + bootph-all; + }; + + /* L4 system firewall */ + noc_fw_l4_sys@10d21100 { + reg = <0x10d21100 0x00000098>; + intel,offset-settings = + /* DMA_ECC */ + <0x00000008 0x01010001 0x01010001>, + /* EMAC0RX_ECC */ + <0x0000000c 0x01010001 0x01010001>, + /* EMAC0TX_ECC */ + <0x00000010 0x01010001 0x01010001>, + /* EMAC1RX_ECC */ + <0x00000014 0x01010001 0x01010001>, + /* EMAC1TX_ECC */ + <0x00000018 0x01010001 0x01010001>, + /* EMAC2RX_ECC */ + <0x0000001c 0x01010001 0x01010001>, + /* EMAC2TX_ECC */ + <0x00000020 0x01010001 0x01010001>, + /* NAND_ECC */ + <0x0000002c 0x01010001 0x01010001>, + /* NAND_READ_ECC */ + <0x00000030 0x01010001 0x01010001>, + /* NAND_WRITE_ECC */ + <0x00000034 0x01010001 0x01010001>, + /* OCRAM_ECC */ + <0x00000038 0x01010001 0x01010001>, + /* SDMMC_ECC */ + <0x00000040 0x01010001 0x01010001>, + /* USB0_ECC */ + <0x00000044 0x01010001 0x01010001>, + /* USB1_CACHEECC */ + <0x00000048 0x01010001 0x01010001>, + /* CLOCK_MANAGER */ + <0x0000004c 0x01010001 0x01010001>, + /* IO_MANAGER */ + <0x00000054 0x01010001 0x01010001>, + /* RESET_MANAGER */ + <0x00000058 0x01010001 0x01010001>, + /* SYSTEM_MANAGER */ + <0x0000005c 0x01010001 0x01010001>, + /* OSC0_TIMER */ + <0x00000060 0x01010301 0x01010301>, + /* OSC1_TIMER0*/ + <0x00000064 0x01010301 0x01010301>, + /* WATCHDOG0 */ + <0x00000068 0x01010301 0x01010301>, + /* WATCHDOG1 */ + <0x0000006c 0x01010301 0x01010301>, + /* WATCHDOG2 */ + <0x00000070 0x01010301 0x01010301>, + /* WATCHDOG3 */ + <0x00000074 0x01010301 0x01010301>, + /* DAP */ + <0x00000078 0x03010001 0x03010001>, + /* WATCHDOG4 */ + <0x0000007c 0x01010301 0x01010301>, + /* POWER_MANAGER */ + <0x00000080 0x01010001 0x01010001>, + /* USB1_RXECC */ + <0x00000084 0x01010001 0x01010001>, + /* USB1_TXECC */ + <0x00000088 0x01010001 0x01010001>, + /* L4_NOC_PROBES */ + <0x00000090 0x01010001 0x01010001>, + /* L4_NOC_QOS */ + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + /* Light weight SoC2FPGA */ + noc_fw_lwsoc2fpga@10d21300 { + reg = <0x10d21300 0x0000004>; + intel,offset-settings = + /* LWSOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* SoC2FPGA */ + noc_fw_soc2fpga@10d21200 { + reg = <0x10d21200 0x0000004>; + intel,offset-settings = + /* SOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* TCU */ + noc_fw_tcu@10d21400 { + reg = <0x10d21400 0x0000004>; + intel,offset-settings = + /* TCU_CSR */ + <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + }; + + socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + }; + + socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + }; + + socfpga_smmu_secure_config: socfpga-smmu-secure-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* System manager */ + i_sys_mgt_sysmgr_csr@10d12000 { + reg = <0x10d12000 0x00000500>; + intel,offset-settings = + /* dma_tbu_stream_ctrl_reg_0_dma0 */ + <0x0000017c 0x00000000 0x0000003f>, + /* dma_tbu_stream_ctrl_reg_0_dma1 */ + <0x00000180 0x00000000 0x0000003f>, + /* sdm_tbu_stream_ctrl_reg_1_sdm */ + <0x00000184 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_usb2 */ + <0x00000188 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_sdmmc */ + <0x00000190 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_nand */ + <0x00000194 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_etr */ + <0x00000198 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn0 */ + <0x0000019c 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn1 */ + <0x000001a0 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn2 */ + <0x000001a4 0x00000000 0x0000003f>; + bootph-all; + }; + }; + + socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* noc fw mpfe csr */ + i_noc_fw_mpfe_csr@18000d00 { + reg = <0x18000d00 0x00000100>; + intel,offset-settings = + /* mpfe scr io96b0 reg*/ + <0x00000000 0x00000001 0x00010101>, + /* mpfe scr io96b1 reg*/ + <0x00000004 0x00000001 0x00010101>, + /* mpfe scr noc csr*/ + <0x00000008 0x00000001 0x00010101>; + bootph-all; + }; + }; + }; }; &clkmgr { @@ -57,6 +711,13 @@ bootph-all; }; +&sdr { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; bootph-all; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 64665e499e7..86322d7b0ce 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ /dts-v1/; @@ -558,6 +559,13 @@ status = "disabled"; }; + sdr: sdr@18000000 { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; + }; + /* QSPI address not available yet */ qspi: spi@108d2000 { compatible = "cdns,qspi-nor"; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 23e0354cba9..d7ab58267eb 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex5-u-boot.dtsi" @@ -21,11 +22,38 @@ }; }; - memory { - /* 8GB */ - reg = <0 0x80000000 0 0x80000000>, - <8 0x80000000 1 0x80000000>; - }; + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + */ + /* + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + */ + /* + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + */ + /* + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + */ + /* + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + */ chosen { stdout-path = "serial0:115200n8"; @@ -129,3 +157,37 @@ &watchdog0 { bootph-all; }; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index 976656a35ad..2ab143e38f8 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -62,6 +62,10 @@ status = "okay"; }; +&i2c3 { + status = "okay"; +}; + &i3c0 { status = "okay"; }; diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi index 1c288acec99..32b5c7cea4b 100644 --- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -22,16 +22,6 @@ mmc0 = &sdio1; spi0 = &qspi; }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioc 13 0>; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpiof 10 0>; - }; }; &fmc { diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 1b42d6cbbc1..38d797e49a0 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -22,16 +22,6 @@ mmc0 = &sdio1; spi0 = &qspi; }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioi 11 0>; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpioi 1 0>; - }; }; <dc { diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index add55c96e21..7c99a6e61b6 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -23,16 +23,6 @@ spi0 = &qspi; }; - button1 { - compatible = "st,button1"; - button-gpio = <&gpioa 0 0>; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpioj 5 0>; - }; - panel: panel { compatible = "orisetech,otm8009a"; reset-gpios = <&gpioj 15 1>; diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index c01d39f03ea..52c2a9f24d7 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -215,6 +215,21 @@ }; }; + pwm1_ch3n_pins_a: pwm1-ch3n-0 { + pins { + pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */ + }; + }; + pwm3_pins_a: pwm3-0 { pins { pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi index d718aae16ca..eace94f5fa4 100644 --- a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi @@ -23,3 +23,25 @@ &usbphyc { bootph-all; }; + +&st33htph { + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; +}; + +/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_ldo2 { + bootph-all; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_sd { + bootph-all; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index eea740d097c..275823da3c6 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> #include <dt-bindings/regulator/st,stm32mp13-regulator.h> #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" @@ -207,6 +208,19 @@ status = "disabled"; }; +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + pwm1: pwm { + pinctrl-0 = <&pwm1_ch3n_pins_a>; + pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + &timers3 { /delete-property/dmas; /delete-property/dma-names; diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index 30e3b91bccc..9ff42ab8248 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -13,6 +13,8 @@ config { dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>; dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>; + u-boot,mmc-env-offset = <0x3fc000>; + u-boot,mmc-env-offset-redundant = <0x3fc000>; }; }; diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts new file mode 100644 index 00000000000..6cb1781566f --- /dev/null +++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra124.dtsi" + +/ { + model = "Xiaomi Mi Pad A0101"; + compatible = "xiaomi,mocha", "nvidia,tegra124"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &gen1_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + nvidia,ganged-mode = <&dsib>; + + panel@0 { + compatible = "sharp,lq079l1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + avdd-supply = <&avdd_lcd>; + vddio-supply = <&vdd_lcd_io>; + + vsp-supply = <&vsp_5v5_lcd>; + vsn-supply = <&vsn_5v5_lcd>; + + reset-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>; + + backlight = <&lp8556>; + }; + }; + + dsib: dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel_secondary: panel@0 { + compatible = "sharp,lq079l1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Keys pinmux */ + keys { + nvidia,pins = "kb_col0_pq0", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hall-front { + nvidia,pins = "pi5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hall-back { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Leds pinmux */ + bl-en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + keys-led { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Panel pinmux */ + lcd-rst { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-vsp { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-vsn { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-id { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-pwm { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-cd { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + usd-pwr { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,open-drain = <1>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,open-drain = <1>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,open-drain = <1>; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <1>; + }; + + dsi-b { + nvidia,pins = "mipi_pad_ctrl_dsi_b"; + nvidia,function = "dsi_b"; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + lp8556: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x83>; + init-brt = /bits/ 8 <0x1f>; + + power-supply = <&vdd_3v3_sys>; + enable-supply = <&vddio_1v8_bl>; + + rom-98h { + rom-addr = /bits/ 8 <0x98>; + rom-val = /bits/ 8 <0x80>; + }; + + rom-9eh { + rom-addr = /bits/ 8 <0x9e>; + rom-val = /bits/ 8 <0x21>; + }; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + + rom-a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x00>; + }; + + rom-a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x72>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + + rom-a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf5>; + }; + + rom-a8h { + rom-addr = /bits/ 8 <0xa8>; + rom-val = /bits/ 8 <0x24>; + }; + + rom-a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0xb2>; + }; + + rom-aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x8f>; + }; + + rom-aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_hv_sdmmc: smps9 { + regulator-name = "vdd_hv_sdmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_lcd: ldo2 { + regulator-name = "avdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo5 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@700b0400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_hv_sdmmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vdd_hv_sdmmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-back-hall-sensor { + label = "Hall sensor (back)"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + + switch-front-hall-sensor { + label = "Hall sensor (front)"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + }; + + vdd_3v3_sys: regulator-bl-en { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vddio_1v8_bl: regulator-bl-io { + compatible = "regulator-fixed"; + regulator-name = "vddio_1v8_bl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + }; + + vdd_lcd_io: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + }; + + vsp_5v5_lcd: regulator-vsp { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd_vsp"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + }; + + vsn_5v5_lcd: regulator-vsn { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd_vsn"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra20-u-boot.dtsi b/arch/arm/dts/tegra20-u-boot.dtsi index fa582bcb9fd..b74aa5bb0d4 100644 --- a/arch/arm/dts/tegra20-u-boot.dtsi +++ b/arch/arm/dts/tegra20-u-boot.dtsi @@ -9,5 +9,9 @@ dc@54200000 { bootph-all; }; + + dc@54240000 { + bootph-all; + }; }; }; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index dbff795bd89..8a0ba3c07cc 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -48,7 +48,17 @@ avdd-dsi-csi-supply = <&avdd_dsi_csi>; - panel = <&panel>; + panel@0 { + compatible = "htc,edge-panel"; + reg = <0>; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_3v3_panel>; + vddio-supply = <&vdd_1v8_panel>; + + backlight = <&backlight>; + }; }; }; @@ -1292,17 +1302,6 @@ }; }; - panel: panel { - compatible = "htc,edge-panel"; - - reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; - - vdd-supply = <&vdd_3v3_panel>; - vddio-supply = <&vdd_1v8_panel>; - - backlight = <&backlight>; - }; - vcore_emmc: regulator-emmc { compatible = "regulator-fixed"; regulator-name = "vdd_2v85_sdmmc"; diff --git a/arch/arm/include/asm/arch-npcm8xx/gmac.h b/arch/arm/include/asm/arch-npcm8xx/gmac.h new file mode 100644 index 00000000000..f84eedddc22 --- /dev/null +++ b/arch/arm/include/asm/arch-npcm8xx/gmac.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _NPCM_GMAC_H_ +#define _NPCM_GMAC_H_ + +/* PCS registers */ +#define PCS_BA 0xF0780000 +#define PCS_IND_AC 0x1FE +#define SR_MII_MMD 0x3E0000 +#define SR_MII_MMD_CTRL 0x0 +#define SR_MII_MMD_STS 0x2 +#define VR_MII_MMD 0x3F0000 +#define VR_MII_MMD_CTRL1 0x0 +#define VR_MII_MMD_AN_CTRL 0x2 + +#define LINK_UP_TIMEOUT (3 * CONFIG_SYS_HZ) + +#endif diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 3aba17d21e4..fbe15fc612d 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -578,6 +578,10 @@ static const char * const tegra_pinctrl_to_drvgrp[] = { [PMUX_DRVGRP_AO4] = "ao4", }; +static const char * const tegra_pinctrl_to_mipipadgrp[] = { + [PMUX_MIPIPADCTRLGRP_DSI_B] = "mipi_pad_ctrl_dsi_b", +}; + static const char * const tegra_pinctrl_to_func[] = { [PMUX_FUNC_DEFAULT] = "default", [PMUX_FUNC_BLINK] = "blink", diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h index 861b3d5d07c..82685353bd1 100644 --- a/arch/arm/include/asm/arch-tegra20/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h @@ -32,6 +32,7 @@ enum clock_id { CLOCK_ID_COUNT, /* number of clocks */ CLOCK_ID_NONE = -1, + CLOCK_ID_DISPLAY2 = CLOCK_ID_NONE, /* for compatibility */ }; /* The clocks supported by the hardware */ @@ -159,6 +160,7 @@ enum periph_id { PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, + PERIPH_ID_DSIB = CLOCK_ID_NONE, /* for compatibility */ }; enum pll_out_id { diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0ab681c893d..6af8cd111a4 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -66,6 +66,7 @@ #define PTE_BLOCK_NG (1 << 11) #define PTE_BLOCK_PXN (UL(1) << 53) #define PTE_BLOCK_UXN (UL(1) << 54) +#define PTE_BLOCK_RO (UL(1) << 7) /* * AttrIndx[2:0] @@ -75,6 +76,7 @@ #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ PTE_BLOCK_UXN | \ PMD_ATTRINDX_MASK | \ + PTE_BLOCK_RO | \ PTE_TYPE_VALID) /* diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h index 662bec86321..a9eccf7f632 100644 --- a/arch/arm/include/asm/setjmp.h +++ b/arch/arm/include/asm/setjmp.h @@ -4,13 +4,11 @@ * (C) Copyright 2016 Alexander Graf <agraf@suse.de> */ -#ifndef _SETJMP_H_ -#define _SETJMP_H_ 1 +#ifndef _ASM_SETJMP_H_ +#define _ASM_SETJMP_H_ 1 + +#include <asm-generic/int-ll64.h> -/* - * This really should be opaque, but the EFI implementation wrongly - * assumes that a 'struct jmp_buf_data' is defined. - */ struct jmp_buf_data { #if defined(__aarch64__) u64 regs[13]; @@ -19,9 +17,4 @@ struct jmp_buf_data { #endif }; -typedef struct jmp_buf_data jmp_buf[1]; - -int setjmp(jmp_buf jmp); -void longjmp(jmp_buf jmp, int ret); - -#endif /* _SETJMP_H_ */ +#endif /* _ASM_SETJMP_H_ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 091082281c7..849b3d0efb7 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -303,8 +303,26 @@ void flush_l3_cache(void); * @emerg: Also map the region in the emergency table */ void mmu_map_region(phys_addr_t start, u64 size, bool emerg); + +/** + * mmu_change_region_attr() - change a mapped region attributes + * + * @start: Start address of the region + * @size: Size of the region + * @aatrs: New attributes + */ void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); +/** + * mmu_change_region_attr_nobreak() - change a mapped region attributes without doing + * break-before-make + * + * @start: Start address of the region + * @size: Size of the region + * @aatrs: New attributes + */ +void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs); + /* * smc_call() - issue a secure monitor call * diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 974cbfe8400..7eb764e1f4e 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -61,10 +61,6 @@ static void announce_and_cleanup(int fake) bootstage_report(); #endif -#ifdef CONFIG_USB_DEVICE - udc_disconnect(); -#endif - board_quiesce_devices(); printf("\nStarting kernel ...%s\n\n", fake ? diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 516754caeaf..dd19bd3e4fb 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <asm/cache.h> #include <asm/global_data.h> +#include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -170,3 +171,8 @@ __weak int arm_reserve_mmu(void) return 0; } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 3e4906e273d..a50dde60e8b 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -100,10 +100,8 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) - ldr r0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr r0, =(CONFIG_SPL_STACK) +#if CONFIG_IS_ENABLED(HAVE_INIT_STACK) + ldr r0, =CONFIG_VAL(STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) #endif diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 32401f544a7..30950ddaf9b 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -69,10 +69,8 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) - ldr x0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr x0, =(CONFIG_SPL_STACK) +#if CONFIG_IS_ENABLED(HAVE_INIT_STACK) + ldr x0, =CONFIG_VAL(STACK) #elif defined(CONFIG_INIT_SP_RELATIVE) #if CONFIG_POSITION_INDEPENDENT adrp x0, __bss_start /* x0 <- Runtime &__bss_start */ diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 345e282e3e6..bffadfecba1 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -83,8 +83,6 @@ relocate_base: add r1, r3 /* r1 <- Run &__image_copy_start */ subs r4, r0, r1 /* r4 <- Run to copy offset */ beq relocate_done /* skip relocation */ - ldr r1, _image_copy_start_ofs - add r1, r3 /* r1 <- Run &__image_copy_start */ ldr r2, _image_copy_end_ofs add r2, r3 /* r2 <- Run &__image_copy_end */ copy_loop: diff --git a/arch/arm/lib/xferlist.c b/arch/arm/lib/xferlist.c index f9c5d88bd47..6425936d354 100644 --- a/arch/arm/lib/xferlist.c +++ b/arch/arm/lib/xferlist.c @@ -8,18 +8,16 @@ #include <bloblist.h> #include "xferlist.h" -int xferlist_from_boot_arg(ulong addr, ulong size) +int xferlist_from_boot_arg(ulong *addr) { int ret; - ret = bloblist_check(saved_args[3], size); - if (ret) - return ret; - ret = bloblist_check_reg_conv(saved_args[0], saved_args[2], - saved_args[1]); + saved_args[1], saved_args[3]); if (ret) return ret; - return bloblist_reloc((void *)addr, size); + *addr = bloblist_get_base(); + + return 0; } diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 85dc8b51a14..567e8e9e81a 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1270,8 +1270,9 @@ static int ft_add_optee_node(void *fdt, struct bd_info *bd) } } + /* Locate the optee node if it exists or create it. */ subpath = "optee"; - offs = fdt_add_subnode(fdt, offs, subpath); + offs = fdt_find_or_add_subnode(fdt, offs, subpath); if (offs < 0) { printf("Could not create %s node.\n", subpath); return offs; diff --git a/arch/arm/mach-imx/imx9/container.cfg b/arch/arm/mach-imx/imx9/container.cfg index 91a973161d1..a018c365c82 100644 --- a/arch/arm/mach-imx/imx9/container.cfg +++ b/arch/arm/mach-imx/imx9/container.cfg @@ -12,4 +12,6 @@ IMAGE A55 bl31.bin 0x204C0000 IMAGE A55 bl31.bin 0x204E0000 #endif IMAGE A55 u-boot.bin CONFIG_TEXT_BASE +#ifdef CONFIG_OPTEE IMAGE A55 tee.bin 0x96000000 +#endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 4020e16d92d..2f873ed6ddf 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -550,6 +550,7 @@ config TARGET_LXR2 select DM_THERMAL select SUPPORT_SPL imply CMD_DM + imply OF_UPSTREAM config TARGET_PCM058 bool "Phytec PCM058 i.MX6 Quad" diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index a3ac490f677..1f8cb8e3822 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -159,6 +159,30 @@ config K3_X509_SWRV config NR_DRAM_BANKS default 2 +config K3_REMOTEPROC_R5F + bool "Enable K3 Remoteproc driver for R5F" + depends on ARM64 + imply REMOTEPROC_TI_K3_R5F + default y if (SOC_K3_AM62A7 || SOC_K3_AM654 || SOC_K3_J721E || SOC_K3_J784S4 || SOC_K3_J721S2 || SOC_K3_J722S || SOC_K3_AM62P5 || SOC_K3_AM642) + +config K3_REMOTEPROC_DSP + bool "Enable K3 Remoteproc driver for DSP" + depends on ARM64 + imply REMOTEPROC_TI_K3_DSP + default y if (SOC_K3_AM62A7 || SOC_K3_J721E || SOC_K3_J784S4 || SOC_K3_J721S2 || SOC_K3_J722S) + +config K3_REMOTEPROC_M4F + bool "Enable K3 Remoteproc driver for M4F" + depends on ARM64 + imply REMOTEPROC_TI_K3_M4F + default y if (SOC_K3_AM625 || SOC_K3_AM642) + +config K3_REMOTEPROC_PRU + bool "Enable K3 Remoteproc driver for PRU" + depends on ARM64 + imply REMOTEPROC_TI_PRU + default y if (SOC_K3_AM642 || SOC_K3_AM654) + if CPU_V7R source "arch/arm/mach-k3/r5/Kconfig" endif diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig index 72a8298aebf..056ae118c9e 100644 --- a/arch/arm/mach-k3/am65x/Kconfig +++ b/arch/arm/mach-k3/am65x/Kconfig @@ -35,6 +35,8 @@ config TARGET_IOT2050_A53 select BOARD_LATE_INIT select SYS_DISABLE_DCACHE_OPS select BINMAN + select SYSINFO + select SPL_SYSINFO if SPL help This builds U-Boot for the IOT2050 devices. diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 4a016711566..361b0c0b31b 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -122,10 +122,8 @@ int fdt_fixup_reserved(void *blob, const char *name, /* Find reserved-memory */ nodeoffset = fdt_subnode_offset(blob, 0, "reserved-memory"); - if (nodeoffset < 0) { - debug("Could not find reserved-memory node\n"); - return 0; - } + if (nodeoffset < 0) + goto add_carveout; /* Find existing matching subnode and remove it */ fdt_for_each_subnode(subnode, blob, nodeoffset) { @@ -154,6 +152,7 @@ int fdt_fixup_reserved(void *blob, const char *name, } } +add_carveout: struct fdt_memory carveout = { .start = new_address, .end = new_address + new_size - 1, diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c index f8c5c2a5edc..af211377e7c 100644 --- a/arch/arm/mach-k3/j722s/j722s_init.c +++ b/arch/arm/mach-k3/j722s/j722s_init.c @@ -27,6 +27,9 @@ struct fwl_data cbass_main_fwls[] = { u32 bootindex __section(".data"); static struct rom_extended_boot_data bootdata __section(".data"); +#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK (~BIT(17)) + static void store_boot_info_from_rom(void) { bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); @@ -161,11 +164,40 @@ static void k3_mem_init(void) } } +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { + int ret; + struct udevice *dev; + k3_spl_init(); k3_mem_init(); setup_qos(); + + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) { + printf("esm main init failed: %d\n", ret); + return; + } + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) { + printf("esm mcu init failed: %d\n", ret); + return; + } + enable_mcu_esm_reset(); + } } static u32 __get_backup_bootmedia(u32 devstat) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 39eea055f70..e54c456aec0 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -6,9 +6,6 @@ config SYS_SOC config SYS_VENDOR default "mediatek" -config MT8512 - bool "MediaTek MT8512 SoC" - choice prompt "MediaTek board select" @@ -96,9 +93,8 @@ config TARGET_MT8365 I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. config TARGET_MT8512 - bool "MediaTek MT8512 M1 Board" + bool "MediaTek MT8512 SoC" select ARM64 - select MT8512 help The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, @@ -160,9 +156,8 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string - default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 + default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 default "lk=1" if TARGET_MT7623 config MTK_TZ_MOVABLE diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 344434c6029..c11d6ad8aed 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -4,7 +4,6 @@ obj-y += cpu.o obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o obj-$(CONFIG_XPL_BUILD) += spl.o -obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ @@ -14,5 +13,6 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ +obj-$(CONFIG_TARGET_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index adac11a6b89..c6e347b8d9d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -9,7 +9,7 @@ config ROCKCHIP_PX30 select SPL select TPL select TPL_TINY_FRAMEWORK if TPL - select TPL_NEEDS_SEPARATE_STACK if TPL + select TPL_HAVE_INIT_STACK if TPL imply SPL_SEPARATE_BSS select SPL_SERIAL select TPL_SERIAL @@ -107,7 +107,7 @@ config ROCKCHIP_RK322X select TPL select TPL_DM select TPL_OF_LIBFDT - select TPL_NEEDS_SEPARATE_STACK if TPL + select TPL_HAVE_INIT_STACK if TPL select SPL_DRIVERS_MISC imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL @@ -140,7 +140,7 @@ config ROCKCHIP_RK3288 imply TPL_DRIVERS_MISC imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT - imply TPL_NEEDS_SEPARATE_STACK + imply TPL_HAVE_INIT_STACK imply TPL_OF_CONTROL imply TPL_OF_PLATDATA imply TPL_RAM @@ -198,7 +198,7 @@ config ROCKCHIP_RK3328 select SPL select SUPPORT_TPL select TPL - select TPL_NEEDS_SEPARATE_STACK if TPL + select TPL_HAVE_INIT_STACK if TPL imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN imply MISC @@ -226,7 +226,7 @@ config ROCKCHIP_RK3368 select ARM64 select SUPPORT_SPL select SUPPORT_TPL - select TPL_NEEDS_SEPARATE_STACK if TPL + select TPL_HAVE_INIT_STACK if TPL imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS @@ -258,7 +258,7 @@ config ROCKCHIP_RK3399 select SPL_RAM if SPL select SPL_REGMAP if SPL select SPL_SYSCON if SPL - select TPL_NEEDS_SEPARATE_STACK if TPL + select TPL_HAVE_INIT_STACK if TPL select SPL_SEPARATE_BSS select CLK select FIT @@ -393,7 +393,7 @@ config ROCKCHIP_RV1126 select SKIP_LOWLEVEL_INIT_ONLY select TPL select SUPPORT_TPL - select TPL_NEEDS_SEPARATE_STACK + select TPL_HAVE_INIT_STACK select TPL_ROCKCHIP_BACK_TO_BROM select SPL select SUPPORT_SPL diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 82a0b3efef9..1db38546d55 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -4,11 +4,11 @@ */ #include <hang.h> +#include <setjmp.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/boot_mode.h> #include <asm/cache.h> #include <asm/io.h> -#include <asm/setjmp.h> #include <asm/system.h> /* diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c index f3619206e91..8f13127a660 100644 --- a/arch/arm/mach-sc5xx/soc.c +++ b/arch/arm/mach-sc5xx/soc.c @@ -172,42 +172,6 @@ void fixup_dp83867_phy(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x3100); } -extern char __bss_start, __bss_end; -extern char __rel_dyn_end; - -void bss_clear(void) -{ - char *bss_start = &__bss_start; - char *bss_end = &__bss_end; - char *rel_dyn_end = &__rel_dyn_end; - - char *start; - - if (rel_dyn_end >= bss_start && rel_dyn_end <= bss_end) - start = rel_dyn_end; - else - start = bss_start; - - u32 *pt; - size_t sz = bss_end - start; - - for (int i = 0; i < sz; i += 4) { - pt = (u32 *)(start + i); - *pt = 0; - } -} - -int board_early_init_f(void) -{ - bss_clear(); - return 0; -} - -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = CFG_SYS_SDRAM_SIZE; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6b6a162f568..a76a9fb2a39 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -55,6 +55,7 @@ config TARGET_SOCFPGA_AGILEX select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX + select GICV2 select NCORE_CACHE select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 @@ -64,7 +65,6 @@ config TARGET_SOCFPGA_AGILEX5 select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX - select GICV3 select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 @@ -74,6 +74,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool + select GICV2 select SPL_ALTERA_SDRAM select SPL_BOARD_INIT if SPL select SPL_CACHE if SPL @@ -118,6 +119,7 @@ config TARGET_SOCFPGA_N5X select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select CLK + select GICV2 select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_ALTERA_SDRAM @@ -137,6 +139,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX + select GICV2 select TARGET_SOCFPGA_SOC64 choice diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5fc61b4a5c6..22d48dfae1c 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# Copyright (C) 2012-2017 Altera Corporation <www.altera.com> +# Copyright (C) 2012-2025 Altera Corporation <www.altera.com> # Copyright (C) 2017-2024 Intel Corporation <www.intel.com> obj-y += board.o @@ -62,7 +62,12 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +obj-y += altera-sysmgr.o +obj-y += ccu_ncore3.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -106,6 +111,7 @@ obj-y += spl_n5x.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o +obj-y += spl_agilex5.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/altera-sysmgr.c b/arch/arm/mach-socfpga/altera-sysmgr.c new file mode 100644 index 00000000000..ca3f5ca7dd5 --- /dev/null +++ b/arch/arm/mach-socfpga/altera-sysmgr.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +/* + * This driver supports the SOCFPGA System Manager Register block which + * aggregates different peripheral function into one area. + * On 64 bit ARM parts, the system manager only can be accessed during + * EL3 mode. At lower exception level a SMC call is required to perform + * the read and write operation. + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <dm.h> +#include <log.h> +#include <misc.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/arch/altera-sysmgr.h> +#include <asm/arch/smc_api.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/intel-smc.h> + +static int altr_sysmgr_read_generic(struct udevice *dev, u32 *addr, u32 *value) +{ + u64 args[1]; + u64 ret_arg; + int ret = 0; + + debug("%s: %s(dev=%p, addr=0x%lx):\n", __func__, + dev->name, dev, (uintptr_t)addr); + + if (current_el() == 3) { + ret_arg = readl((uintptr_t)addr); + } else { + if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + args[0] = (u64)(uintptr_t)addr; + ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1); + } else { + pr_err("%s Failed to read system manager at lower privilege and without BL31\n", + dev->name); + return -EPROTONOSUPPORT; + } + } + + *value = (u32)ret_arg; + return ret; +} + +static int altr_sysmgr_write_generic(struct udevice *dev, u32 *addr, u32 value) +{ + u64 args[2]; + int ret = 0; + + debug("%s: %s(dev=%p, addr=0x%lx, val=0x%x):\n", __func__, + dev->name, dev, (uintptr_t)addr, value); + + if (current_el() == 3) { + writel(value, (uintptr_t)addr); + } else { + if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + args[0] = (u64)(uintptr_t)(addr); + args[1] = value; + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0); + } else { + pr_err("%s Failed to write to system manager at lower privilege and without BL31\n", + dev->name); + return -EPROTONOSUPPORT; + } + } + + return ret; +} + +static int altr_sysmgr_probe(struct udevice *dev) +{ + fdt_addr_t addr; + struct altr_sysmgr_priv *altr_priv = dev_get_priv(dev); + + debug("%s: %s(dev=%p):\n", __func__, dev->name, dev); + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + pr_err("%s dev_read_addr() failed\n", dev->name); + return -ENODEV; + } + + altr_priv->regs = (void __iomem *)addr; + return 0; +} + +static const struct altr_sysmgr_ops sysmgr_ops = { + .read = altr_sysmgr_read_generic, + .write = altr_sysmgr_write_generic, +}; + +static const struct udevice_id altr_sysmgr_ids[] = { + { .compatible = "altr,sys-mgr-s10" }, + { .compatible = "altr,sys-mgr" }, + { }, +}; + +U_BOOT_DRIVER(altr_sysmgr) = { + .name = "altr_sysmgr", + .id = UCLASS_NOP, + .of_match = altr_sysmgr_ids, + .probe = altr_sysmgr_probe, + .ops = &sysmgr_ops, + .priv_auto = sizeof(struct altr_sysmgr_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 24a15f7903f..27072e53135 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -6,22 +6,24 @@ */ #include <config.h> -#include <asm/arch/clock_manager.h> -#include <asm/arch/mailbox_s10.h> -#include <asm/arch/misc.h> -#include <asm/arch/reset_manager.h> -#include <asm/arch/secure_vab.h> -#include <asm/arch/smc_api.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> #include <fdtdec.h> +#include <log.h> +#include <init.h> #include <hang.h> +#include <handoff.h> #include <image.h> -#include <init.h> -#include <log.h> #include <usb.h> #include <usb/dwc2_udc.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> +#include <bloblist.h> DECLARE_GLOBAL_DATA_PTR; @@ -57,7 +59,18 @@ int board_init(void) int dram_init_banksize(void) { +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#ifndef CONFIG_SPL_BUILD + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + handoff_load_dram_banks(ho); +#endif +#else fdtdec_setup_memory_banksize(); +#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ return 0; } diff --git a/arch/arm/mach-socfpga/ccu_ncore3.c b/arch/arm/mach-socfpga/ccu_ncore3.c new file mode 100644 index 00000000000..a399aedcd10 --- /dev/null +++ b/arch/arm/mach-socfpga/ccu_ncore3.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ +#include <wait_bit.h> +#include <asm/arch/base_addr_soc64.h> +#include <linux/bitfield.h> + +#define CCU_DMI0_DMIUSMCTCR SOCFPGA_CCU_ADDRESS + 0x7300 +#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_ADDRESS + 0x7340 +#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_ADDRESS + 0x7344 +#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0) +#define MAX_DISTRIBUTED_MEM_INTERFACE 2 +#define FLUSH_ALL_ENTRIES 0x4 +#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16) +#define ARRAY_ID_TAG 0x0 +#define ARRAY_ID_DATA 0x1 +#define CACHE_OPERATION_DONE BIT(0) +#define TIMEOUT_200MS 200 + +int __asm_flush_l3_dcache(void) +{ + int i; + int ret = 0; + + /* Flushing all entries in CCU system memory cache */ + for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) { + /* + * Skipping if the system memory cache is not enabled for + * particular DMI + */ + if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000)))) + continue; + + writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS, + false); + if (ret) { + debug("%s: Timeout while waiting for flushing tag in DMI%d done\n", + __func__, i); + return ret; + } + + writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS, + false); + if (ret) + debug("%s: Timeout waiting for flushing data in DMI%d done\n", + __func__, i); + } + + return ret; +} diff --git a/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h new file mode 100644 index 00000000000..8516617efe5 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +struct altr_sysmgr_ops { + int (*read)(struct udevice *dev, u32 *addr, u32 *value); + int (*write)(struct udevice *dev, u32 *addr, u32 value); +}; + +struct altr_sysmgr_priv { + void __iomem *regs; +}; + +#define altr_sysmgr_get_ops(dev) ((struct altr_sysmgr_ops *)(dev)->driver->ops) +#define altr_sysmgr_get_priv(dev) ((struct altr_sysmgr_priv *)(dev_get_priv(dev))) diff --git a/arch/arm/mach-socfpga/include/mach/board.h b/arch/arm/mach-socfpga/include/mach/board.h new file mode 100644 index 00000000000..2c3127e629f --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/board.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +u8 socfpga_get_board_id(void); + +#endif /* _BOARD_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 5cb7f23f8f0..2b436b64816 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -126,11 +127,27 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff +/* Firewall F2SDRAM DDR SCR registers */ +#define FW_F2SDRAM_DDR_SCR_EN 0x00 +#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c + #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define FW_MPU_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) +#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg)) +#else #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) +#endif void firewall_setup(void); diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index d839f288411..763b077d8c1 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -17,9 +18,9 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 -#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d #else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 #endif @@ -68,7 +69,7 @@ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) -#define SOC64_HANDOFF_SDRAM_LEN 1 +#define SOC64_HANDOFF_SDRAM_LEN 5 #endif #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 8460acb00d9..ab46415168f 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2021 Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SOCFPGA_MISC_H_ @@ -51,6 +52,7 @@ bool is_periph_program_force(void); void set_regular_boot(unsigned int status); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); +void socfpga_get_sys_mgr_addr(const char *compat); int qspi_flash_software_reset(void); #endif /* _SOCFPGA_MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2b..058fdd6e548 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _RESET_MANAGER_SOC64_H_ @@ -23,14 +24,20 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 /* SDM, Watchdogs and MPU warm reset mask */ -#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + RSTMGR_STAT_L4WD0RST_BIT) +#else #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ RSTMGR_STAT_MPU0RST_BITPOS) | \ GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ RSTMGR_STAT_L4WD0RST_BITPOS)) +#endif /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 78eff247978..c2ca0a50e35 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -11,22 +12,43 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -#define SYSMGR_SOC64_WDDBG 0x08 -#define SYSMGR_SOC64_DMA 0x20 -#define SYSMGR_SOC64_DMA_PERIPH 0x24 -#define SYSMGR_SOC64_SDMMC 0x28 -#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c -#define SYSMGR_SOC64_EMAC_GLOBAL 0x40 -#define SYSMGR_SOC64_EMAC0 0x44 -#define SYSMGR_SOC64_EMAC1 0x48 -#define SYSMGR_SOC64_EMAC2 0x4c -#define SYSMGR_SOC64_EMAC0_ACE 0x50 -#define SYSMGR_SOC64_EMAC1_ACE 0x54 -#define SYSMGR_SOC64_EMAC2_ACE 0x58 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SYSMGR_SOC64_SILICONID_1 0x00 +#define SYSMGR_SOC64_SILICONID_2 0x04 +#define SYSMGR_SOC64_MPU_STATUS 0x10 +#define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc +#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1 +#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 +#define SYSMGR_SOC64_USB0_L3MASTER 0x38 +#define SYSMGR_SOC64_USB1_L3MASTER 0x3c +#define SYSMGR_SOC64_DMAC0_L3_MASTER 0x74 +#define SYSMGR_SOC64_ETR_L3_MASTER 0x78 +#define SYSMGR_SOC64_DMAC1_L3_MASTER 0x7C +#define SYSMGR_SOC64_SEC_CTRL_SLT 0x80 +#define SYSMGR_SOC64_OSC_TRIM 0x84 +#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG 0x88 +#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG 0x8C +#define SYSMGR_SOC64_ECC_INTMASK_VALUE 0x90 +#define SYSMGR_SOC64_ECC_INTMASK_SET 0x94 +#define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 +#define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C +#define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_MPFE_CONFIG 0x228 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(31, 0) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT 29 +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK BIT(27) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK BIT(28) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK GENMASK(28, 27) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK BIT(1) +#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) +#else #define SYSMGR_SOC64_NAND_AXUSER 0x5c -#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 -#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c -#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 #define SYSMGR_SOC64_DMA_L3MASTER 0x74 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE 0xb8 @@ -34,39 +56,56 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HMC_CLK 0xb4 #define SYSMGR_SOC64_IO_PA_CTRL 0xb8 #endif -#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 -#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 -#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 -#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 -#define SYSMGR_SOC64_FPGA_CONFIG 0xdc #define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* - * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit - * storing qspi ref clock (kHz) - */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 -/* store osc1 clock freq */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 -/* store fpga clock freq */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 -/* reserved for customer use */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c -/* store PSCI_CPU_ON value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 -/* store PSCI_CPU_ON value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 -/* store VBAR_EL3 value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 -/* store VBAR_EL3 value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ + +#define SYSMGR_SOC64_DMA 0x20 +#define SYSMGR_SOC64_DMA_PERIPH 0x24 +#define SYSMGR_SOC64_WDDBG 0x08 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2C +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6C +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xC0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xC4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xC8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xCC +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xD4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xD8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xDC + +#define SYSMGR_SOC64_TSN_GLOBAL 0x40 +#define SYSMGR_SOC64_TSN_0 0x44 +#define SYSMGR_SOC64_TSN_1 0x48 +#define SYSMGR_SOC64_TSN_2 0x4C +#define SYSMGR_SOC64_TSN_0_ACE 0x50 +#define SYSMGR_SOC64_TSN_1_ACE 0x54 +#define SYSMGR_SOC64_TSN_2_ACE 0x58 +#define SYSMGR_SOC64_EMAC_GLOBAL SYSMGR_SOC64_TSN_GLOBAL +#define SYSMGR_SOC64_EMAC0 SYSMGR_SOC64_TSN_0 +#define SYSMGR_SOC64_EMAC1 SYSMGR_SOC64_TSN_1 +#define SYSMGR_SOC64_EMAC2 SYSMGR_SOC64_TSN_2 +#define SYSMGR_SOC64_EMAC0_ACE SYSMGR_SOC64_TSN_0_ACE +#define SYSMGR_SOC64_EMAC1_ACE SYSMGR_SOC64_TSN_1_ACE +#define SYSMGR_SOC64_EMAC2_ACE SYSMGR_SOC64_TSN_2_ACE + +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 + #define SYSMGR_SOC64_PINSEL0 0x1000 #define SYSMGR_SOC64_IOCTRL0 0x1130 #define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 @@ -97,7 +136,6 @@ void populate_sysmgr_pinmux(void); * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit * storing qspi ref clock (kHz) */ -#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 46f9c82bbb2..97e01140513 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,31 +1,33 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2025 Altera Corporation <www.altera.com> */ #include <config.h> #include <command.h> -#include <cpu_func.h> -#include <hang.h> -#include <asm/cache.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> +#include <init.h> +#include <handoff.h> +#include <hang.h> +#include <watchdog.h> #include <fdtdec.h> #include <linux/libfdt.h> -#include <altera.h> +#include <linux/printk.h> #include <miiphy.h> #include <netdev.h> -#include <watchdog.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/pl310.h> #include <asm/arch/misc.h> +#include <asm/arch/nic301.h> #include <asm/arch/reset_manager.h> #include <asm/arch/scan_manager.h> -#include <asm/arch/system_manager.h> -#include <asm/arch/nic301.h> #include <asm/arch/scu.h> -#include <asm/pl310.h> -#include <linux/printk.h> +#include <asm/arch/system_manager.h> +#include <altera.h> +#include <bloblist.h> +#include <cpu_func.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,8 +53,18 @@ struct bsel bsel_str[] = { int dram_init(void) { +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + gd->ram_size = ho->ram_bank[0].size; + gd->ram_base = ho->ram_bank[0].start; +#else if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; +#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ return 0; } @@ -248,21 +260,32 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) + ret = socfpga_get_base_addr("intel,agilex-clkmgr", + &socfpga_clkmgr_base); + else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + ret = socfpga_get_base_addr("intel,n5x-clkmgr", + &socfpga_clkmgr_base); + else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + ret = socfpga_get_base_addr("altr,clk-mgr", + &socfpga_clkmgr_base); + if (ret) hang(); +} -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) - ret = socfpga_get_base_addr("intel,n5x-clkmgr", - &socfpga_clkmgr_base); -#else - ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); -#endif - if (ret) +void socfpga_get_sys_mgr_addr(const char *compat) +{ + int ret; + struct udevice *sysmgr_dev; + + ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev); + if (ret) { + printf("Altera system manager init failed: %d\n", ret); hang(); + } else { + socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev); + } } phys_addr_t socfpga_get_rstmgr_addr(void) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index a6cc78454da..e0b2b4237e1 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -1,20 +1,23 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ #include <altera.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <log.h> +#include <asm/arch/board.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/io.h> +#include <asm/system.h> #include <asm/global_data.h> -#include <env.h> -#include <errno.h> -#include <init.h> -#include <log.h> #include <mach/clock_manager.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,12 +43,26 @@ static Altera_desc altera_fpga[] = { }; /* + * The Agilex5 platform has enabled the bloblist feature, and the bloblist + * address and size are initialized based on the defconfig settings. + * During the SPL phase, this function is used to prevent the bloblist + * from initializing its address and size with the saved boot parameters, + * which may have been incorrectly set. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + save_boot_params_ret(); +} + +/* * Print CPU information */ #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); + printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; } @@ -55,10 +72,15 @@ int print_cpuinfo(void) int arch_misc_init(void) { char qspi_string[13]; + unsigned long id; sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); + /* Export board_id as environment variable */ + id = socfpga_get_board_id(); + env_set_ulong("board_id", id); + return 0; } #endif diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index ebaa0b8fa17..b212a94b321 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <cpu_func.h> #include <asm/ptrace.h> #include <asm/system.h> #include <linux/errno.h> @@ -40,10 +42,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, args[2] = len; args[3] = urgent; args[4] = (u64)resp_buf; - if (resp_buf_len) + + if (arg && len > 0) + flush_dcache_range((uintptr_t)arg, (uintptr_t)arg + len); + + if (resp_buf && resp_buf_len && *resp_buf_len > 0) { args[5] = *resp_buf_len; - else + flush_dcache_range((uintptr_t)resp_buf, (uintptr_t)resp_buf + *resp_buf_len); + } else { args[5] = 0; + } ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args), resp, ARRAY_SIZE(resp)); diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c new file mode 100644 index 00000000000..3451611082d --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <hang.h> +#include <spl.h> +#include <asm/arch/base_addr_soc64.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <wdt.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 reset_flag(void) +{ + /* Check rstmgr.stat for warm reset status */ + u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); + + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK; + + if (status & warm_reset_mask) + return 0; + + return 1; +} + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + /* Enable Async */ + asm volatile("msr daifclr, #4"); + +#ifdef CONFIG_SPL_BUILD + spl_save_restore_data(); +#endif + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + socfpga_get_managers_addr(); + + sysmgr_pinmux_init(); + + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + + timer_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + + preloader_console_init(); + print_reset_info(); + cm_print_clock_quick_summary(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev); + if (ret) { + printf("HPS CCU settings init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev); + if (ret) { + printf("HPS firewall settings init failed: %d\n", ret); + hang(); + } + + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } + } + + mbox_init(); + + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) + mbox_qspi_open(); + + /* Enable non secure access to ocram */ + clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0)); +} diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 4fe67ea0811..651d9fc9cb8 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -1,10 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020 Intel Corporation. All rights reserved + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <hang.h> #include <spl.h> +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -13,6 +16,109 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; } +/* This function is to map specified node onto SPL boot devices */ +static int spl_node_to_boot_device(int node) +{ + const void *blob = gd->fdt_blob; + struct udevice *parent; + const char *prop; + + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) + return BOOT_DEVICE_MMC1; + else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent)) + return BOOT_DEVICE_NAND; + + prop = fdt_getprop(blob, node, "device_type", NULL); + if (prop) { + if (!strcmp(prop, "memory")) + return BOOT_DEVICE_RAM; + + printf("%s: unknown device_type %s\n", __func__, prop); + } + + return -ENODEV; +} + +static void default_spl_boot_list(u32 *spl_boot_list, int length) +{ + spl_boot_list[0] = spl_boot_device(); + + if (length > 1) + spl_boot_list[1] = BOOT_DEVICE_SPI; + + if (length > 2) + spl_boot_list[2] = BOOT_DEVICE_NAND; +} + +void board_boot_order(u32 *spl_boot_list) +{ + int idx = 0; + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + const char *conf; + int elem; + int boot_device; + int node; + int length; + + /* expect valid initialized spl_boot_list */ + if (!spl_boot_list) + return; + + length = 1; + while (spl_boot_list[length] == spl_boot_list[length - 1]) + length++; + + debug("%s: chosen_node is %d\n", __func__, chosen_node); + if (chosen_node < 0) { + printf("%s: /chosen not found, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + if (idx >= length) { + printf("%s: limit %d to spl_boot_list exceeded\n", __func__, + length); + break; + } + + /* Resolve conf item as a path in device tree */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT\n", __func__, conf); + continue; + } + + /* Try to map spl node back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx] = boot_device; + debug("%s: spl_boot_list[%d] = %u\n", __func__, idx, + spl_boot_list[idx]); + idx++; + } + + if (idx == 0) { + if (!conf && !elem) { + printf("%s: spl-boot-order invalid, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + } else { + printf("%s: no valid element spl-boot-order list\n", __func__); + } + } +} + #if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { @@ -22,3 +128,16 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } #endif + +/* board specific function prior loading SSBL / U-Boot */ +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev); + if (ret) { + printf("HPS SMMU secure settings init failed: %d\n", ret); + hang(); + } +} diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 92051d19b73..7105cdc4905 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -1,15 +1,17 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <errno.h> #include <asm/arch/handoff_soc64.h> #include <asm/io.h> -#include <errno.h> #include "log.h" #ifndef __ASSEMBLY__ +#include <asm/types.h> enum endianness { LITTLE_ENDIAN = 0, BIG_ENDIAN, @@ -26,7 +28,12 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_FPGA: case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: + case SOC64_HANDOFF_MAGIC_SDRAM: +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + case SOC64_HANDOFF_MAGIC_PERI: +#else case SOC64_HANDOFF_MAGIC_MISC: +#endif return BIG_ENDIAN; #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 25663a99464..002da2e3d3b 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -153,6 +153,12 @@ config CMD_STM32KEY This command is used to evaluate the secure boot on stm32mp SOC, it is deactivated by default in real products. +config MFD_STM32_TIMERS + bool "STM32 multifonction timer support" + help + Select this to enable support for the multifunction timer found on + STM32 devices. + source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" source "arch/arm/mach-stm32mp/Kconfig.25x" diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index db7ed19bd91..103e3410ad9 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_STM32MP15X) += stm32mp1/ obj-$(CONFIG_STM32MP13X) += stm32mp1/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ +obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifndef CONFIG_XPL_BUILD obj-y += cmd_stm32prog/ diff --git a/arch/arm/mach-stm32mp/include/mach/timers.h b/arch/arm/mach-stm32mp/include/mach/timers.h new file mode 100644 index 00000000000..a84465bb28e --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/timers.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author: Cheick Traore <cheick.traore@foss.st.com> + * + * Originally based on the Linux kernel v6.1 include/linux/mfd/stm32-timers.h. + */ + +#ifndef __STM32_TIMERS_H +#define __STM32_TIMERS_H + +#include <clk.h> + +#define TIM_CR1 0x00 /* Control Register 1 */ +#define TIM_CR2 0x04 /* Control Register 2 */ +#define TIM_SMCR 0x08 /* Slave mode control reg */ +#define TIM_DIER 0x0C /* DMA/interrupt register */ +#define TIM_SR 0x10 /* Status register */ +#define TIM_EGR 0x14 /* Event Generation Reg */ +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ +#define TIM_CNT 0x24 /* Counter */ +#define TIM_PSC 0x28 /* Prescaler */ +#define TIM_ARR 0x2c /* Auto-Reload Register */ +#define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */ +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ +#define TIM_DCR 0x48 /* DMA control register */ +#define TIM_DMAR 0x4C /* DMA register for transfer */ +#define TIM_TISEL 0x68 /* Input Selection */ + +#define TIM_CR1_CEN BIT(0) /* Counter Enable */ +#define TIM_CR1_ARPE BIT(7) +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) +#define TIM_CCER_CC1E BIT(0) +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ +#define TIM_EGR_UG BIT(0) /* Update Generation */ + +#define MAX_TIM_PSC 0xFFFF + +struct stm32_timers_plat { + void __iomem *base; +}; + +struct stm32_timers_priv { + u32 max_arr; + ulong rate; +}; + +#endif diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index d5eaf6711b6..18175fd12cc 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -138,8 +138,6 @@ int mach_cpu_init(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; - else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD)) - debug_uart_init(); return 0; } diff --git a/arch/arm/mach-stm32mp/timers.c b/arch/arm/mach-stm32mp/timers.c new file mode 100644 index 00000000000..a3207895f40 --- /dev/null +++ b/arch/arm/mach-stm32mp/timers.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author: Cheick Traore <cheick.traore@foss.st.com> + * + * Originally based on the Linux kernel v6.1 drivers/mfd/stm32-timers.c. + */ + +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/timers.h> +#include <dm/device_compat.h> + +static void stm32_timers_get_arr_size(struct udevice *dev) +{ + struct stm32_timers_plat *plat = dev_get_plat(dev); + struct stm32_timers_priv *priv = dev_get_priv(dev); + u32 arr; + + /* Backup ARR to restore it after getting the maximum value */ + arr = readl(plat->base + TIM_ARR); + + /* + * Only the available bits will be written so when readback + * we get the maximum value of auto reload register + */ + writel(~0L, plat->base + TIM_ARR); + priv->max_arr = readl(plat->base + TIM_ARR); + writel(arr, plat->base + TIM_ARR); +} + +static int stm32_timers_of_to_plat(struct udevice *dev) +{ + struct stm32_timers_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get address\n"); + return -ENOENT; + } + + return 0; +} + +static int stm32_timers_probe(struct udevice *dev) +{ + struct stm32_timers_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret = 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock: ret=%d\n", ret); + return ret; + } + + priv->rate = clk_get_rate(&clk); + + stm32_timers_get_arr_size(dev); + + return ret; +} + +static const struct udevice_id stm32_timers_ids[] = { + { .compatible = "st,stm32-timers" }, + {} +}; + +U_BOOT_DRIVER(stm32_timers) = { + .name = "stm32_timers", + .id = UCLASS_NOP, + .of_match = stm32_timers_ids, + .of_to_plat = stm32_timers_of_to_plat, + .plat_auto = sizeof(struct stm32_timers_plat), + .probe = stm32_timers_probe, + .priv_auto = sizeof(struct stm32_timers_priv), + .bind = dm_scan_fdt_dev, +}; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 78b89729f19..4690dcb3ea6 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -247,7 +247,7 @@ config CMD_ENTERRCM config CMD_EBTUPDATE bool "Enable 'ebtupdate' command" - depends on TEGRA20 || TEGRA30 + depends on TEGRA20 || TEGRA30 || TEGRA124 select TEGRA_CRYPTO help Updating u-boot from within u-boot in rather complex or even diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 157e6c4911a..a375693481e 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -358,6 +358,13 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, break; } + /* + * PLLD/PLLD2 raw clock rate is never used, instead plld_out0 is used + * that is PLLD/PLLD2 halved. + */ + if (parent == CLOCK_ID_DISPLAY || parent == CLOCK_ID_DISPLAY2) + parent_rate /= 2; + return get_rate_from_divider(parent_rate, div); } @@ -449,6 +456,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, enum clock_id parent, unsigned rate, int *extra_div) { unsigned effective_rate; + unsigned int parent_rate; int mux_bits, divider_bits, source; int divider; int xdiv = 0; @@ -457,7 +465,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, source = get_periph_clock_source(periph_id, parent, &mux_bits, ÷r_bits); - divider = find_best_divider(divider_bits, pll_rate[parent], + /* + * Clocks derived from PLLD/D2 are actually sourced from its halved + * output, plld_out0/plld2_out0. No peripheral clocks use the raw + * PLLD/D2 frequency. This halving must be accounted for in derived + * clock calculations. + */ + parent_rate = pll_rate[parent]; + if (parent == CLOCK_ID_DISPLAY || parent == CLOCK_ID_DISPLAY2) + parent_rate /= 2; + + divider = find_best_divider(divider_bits, parent_rate, rate, &xdiv); if (extra_div) *extra_div = xdiv; @@ -685,6 +703,16 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) else writel(base_reg, &simple_pll->pll_base); + /* + * Changing clocks was never intended in the U-Boot for Tegra. + * If a clock is changed after clock_init() the parent rate is wrong. + * Usually there is no reason to change peripheral clocks, but Display + * PLLs which needs to generate a precise pixelclock might be adjusted. + * Especially in the case of HDMI display with changing and prior + * unknown resolution. + */ + pll_rate[clkid] = clock_get_rate(clkid); + return 0; } diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 84c8f86bad0..a62b055f7e6 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -30,6 +30,10 @@ config TARGET_CEI_TK1_SOM the SoC are assigned to which functions, and the PCIEe configuration. +config TARGET_MOCHA + bool "Xiaomi Tegra124 Mi Pad board" + select BOARD_LATE_INIT + config TARGET_NYAN_BIG bool "Google/NVIDIA Nyan-big Chromebook" select BOARD_LATE_INIT @@ -54,5 +58,6 @@ source "board/nvidia/jetson-tk1/Kconfig" source "board/nvidia/nyan-big/Kconfig" source "board/nvidia/venice2/Kconfig" source "board/toradex/apalis-tk1/Kconfig" +source "board/xiaomi/mocha/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index dee790015a3..7b93db89c0f 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -6,6 +6,7 @@ # obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o obj-y += clock.o obj-y += pmc.o diff --git a/arch/arm/mach-tegra/tegra124/bct.c b/arch/arm/mach-tegra/tegra124/bct.c new file mode 100644 index 00000000000..a71aa87fce1 --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/bct.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022, Ramin <raminterex@yahoo.com> + * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <command.h> +#include <log.h> +#include <vsprintf.h> +#include <asm/arch-tegra/crypto.h> +#include "bct.h" +#include "uboot_aes.h" + +/* Device with "sbk burned: false" will expose zero key */ +const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; + +/* + * @param bct boot config table start in RAM + * @param ect bootloader start in RAM + * @param ebt_size bootloader file size in bytes + * Return: 0, or 1 if failed + */ +static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) +{ + struct nvboot_config_table *bct_tbl = NULL; + u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; + u8 bct_hash[AES128_KEY_LENGTH] = { 0 }; + u8 sbk[AES128_KEY_LENGTH] = { 0 }; + u8 *sbct = bct + UBCT_LENGTH; + bool encrypted; + int ret; + + ebt_size = roundup(ebt_size, EBT_ALIGNMENT); + + memcpy(sbk, (u8 *)(bct + UBCT_LENGTH + SBCT_LENGTH), + NVBOOT_CMAC_AES_HASH_LENGTH * 4); + + encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + + if (encrypted) { + ret = decrypt_data_block(sbct, SBCT_LENGTH, sbk); + if (ret) + return 1; + + ret = encrypt_data_block(ebt, ebt_size, sbk); + if (ret) + return 1; + } + + ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + if (ret) + return 1; + + bct_tbl = (struct nvboot_config_table *)bct; + + memcpy((u8 *)&bct_tbl->bootloader[0].crypto_hash, + ebt_hash, NVBOOT_CMAC_AES_HASH_LENGTH * 4); + bct_tbl->bootloader[0].entry_point = CONFIG_SPL_TEXT_BASE; + bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE; + bct_tbl->bootloader[0].length = ebt_size; + + if (encrypted) { + ret = encrypt_data_block(sbct, SBCT_LENGTH, sbk); + if (ret) + return 1; + } + + ret = sign_enc_data_block(sbct, SBCT_LENGTH, bct_hash, sbk); + if (ret) + return 1; + + memcpy((u8 *)&bct_tbl->crypto_hash, bct_hash, + NVBOOT_CMAC_AES_HASH_LENGTH * 4); + + return 0; +} + +static int do_ebtupdate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 bct_addr = hextoul(argv[1], NULL); + u32 ebt_addr = hextoul(argv[2], NULL); + u32 ebt_size = hextoul(argv[3], NULL); + + return bct_patch((u8 *)bct_addr, (u8 *)ebt_addr, ebt_size); +} + +U_BOOT_CMD(ebtupdate, 4, 0, do_ebtupdate, + "update bootloader on re-crypted Tegra124 devices", + "" +); diff --git a/arch/arm/mach-tegra/tegra124/bct.h b/arch/arm/mach-tegra/tegra124/bct.h new file mode 100644 index 00000000000..eb0f712d595 --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/bct.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _BCT_H_ +#define _BCT_H_ + +/* + * Defines the BCT parametres for T124 + */ +#define UBCT_LENGTH 0x6b0 /* bytes */ +#define SBCT_LENGTH 0x1950 /* bytes */ + +#define BCT_HASH 0x10 +#define EBT_ALIGNMENT 0x10 + +/* + * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) + */ +#define NVBOOT_CMAC_AES_HASH_LENGTH 4 + +/* + * Defines the RSA modulus length in 32 bit words used for PKC secure boot. + */ +#define NVBOOT_SE_RSA_MODULUS_LENGTH 64 + +/* + * Defines the maximum number of bootloader descriptions in the BCT. + */ +#define NVBOOT_MAX_BOOTLOADERS 4 + +struct nv_bootloader_info { + u32 version; + u32 start_blk; + u32 start_page; + u32 length; + u32 load_addr; + u32 entry_point; + u32 attribute; + + /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ + u32 crypto_hash[NVBOOT_CMAC_AES_HASH_LENGTH]; + u32 bl_rsa_sig[NVBOOT_SE_RSA_MODULUS_LENGTH]; +}; + +struct nvboot_config_table { + u32 ubct_unused1[196]; + u32 crypto_hash[NVBOOT_CMAC_AES_HASH_LENGTH]; + u32 ubct_unused2[228]; + + u32 sbct_unused1[1318]; + u32 bootloader_used; + struct nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; + u32 sbct_unused2; +}; + +#endif /* _BCT_H_ */ diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index 370ad40f142..a21fe327944 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -8,6 +8,7 @@ #include <cpu_func.h> #include <asm/immap.h> #include <asm/cache.h> +#include <linux/errno.h> volatile int *cf_icache_status = (int *)ICACHE_STATUS; volatile int *cf_dcache_status = (int *)DCACHE_STATUS; @@ -151,3 +152,8 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop) { /* An empty stub, real implementation should be in platform code */ } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c index 8f543f2a2f2..d7fd9ca8bd4 100644 --- a/arch/nios2/lib/cache.c +++ b/arch/nios2/lib/cache.c @@ -8,6 +8,7 @@ #include <cpu_func.h> #include <asm/cache.h> #include <asm/global_data.h> +#include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -127,3 +128,8 @@ void dcache_disable(void) { flush_dcache_all(); } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 819250f0090..abdaffbe00b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -133,7 +133,6 @@ #define CFG_FM_PLAT_CLK_DIV 1 #define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV #define CFG_SYS_FM_MURAM_SIZE 0x30000 -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -146,7 +145,6 @@ #define CFG_SYS_FM1_CLK 0 #define CFG_QBMAN_CLK_DIV 1 #define CFG_SYS_FM_MURAM_SIZE 0x30000 -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -165,7 +163,6 @@ #define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV #define CFG_SYS_FM1_CLK 0 #define CFG_SYS_FM_MURAM_SIZE 0x28000 -#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #elif defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index a9cd7b8d30a..e4d9546039d 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -8,6 +8,7 @@ #include <stdio.h> #include <asm/cache.h> #include <watchdog.h> +#include <linux/errno.h> static ulong maybe_watchdog_reset(ulong flushed) { @@ -58,3 +59,8 @@ void invalidate_icache_all(void) { puts("No arch specific invalidate_icache_all available!\n"); } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 3f78932aa9d..7bafdfd390a 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -90,8 +90,8 @@ _start: * Set stackpointer in internal/ex RAM to call board_init_f */ call_board_init_f: -#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) - li t0, CONFIG_SPL_STACK +#if CONFIG_IS_ENABLED(HAVE_INIT_STACK) + li t0, CONFIG_VAL(STACK) #else li t0, SYS_INIT_SP_ADDR #endif diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h index 72383d43303..08687e0f92b 100644 --- a/arch/riscv/include/asm/setjmp.h +++ b/arch/riscv/include/asm/setjmp.h @@ -3,13 +3,9 @@ * (C) Copyright 2018 Alexander Graf <agraf@suse.de> */ -#ifndef _SETJMP_H_ -#define _SETJMP_H_ 1 +#ifndef _ASM_SETJMP_H_ +#define _ASM_SETJMP_H_ 1 -/* - * This really should be opaque, but the EFI implementation wrongly - * assumes that a 'struct jmp_buf_data' is defined. - */ struct jmp_buf_data { /* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */ unsigned long s_regs[12]; /* s0 - s11 */ @@ -17,9 +13,4 @@ struct jmp_buf_data { unsigned long sp; }; -typedef struct jmp_buf_data jmp_buf[1]; - -int setjmp(jmp_buf jmp); -void longjmp(jmp_buf jmp, int ret); - -#endif /* _SETJMP_H_ */ +#endif /* _ASM_SETJMP_H_ */ diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 76c610bcee0..9544907ab1e 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -46,10 +46,6 @@ static void announce_and_cleanup(int fake) bootstage_report(); #endif -#ifdef CONFIG_USB_DEVICE - udc_disconnect(); -#endif - board_quiesce_devices(); /* diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 71e4937ab54..31aa30bc7d7 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -8,6 +8,7 @@ #include <dm.h> #include <asm/insn-def.h> #include <linux/const.h> +#include <linux/errno.h> #define CBO_INVAL(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ @@ -151,3 +152,8 @@ __weak void enable_caches(void) if (!zicbom_block_size) log_debug("Zicbom not initialized.\n"); } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 4c169034d9a..d61a327f151 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -77,7 +77,7 @@ config SANDBOX_BITS_PER_LONG config SYS_FDT_LOAD_ADDR hex "Address at which to load devicetree" - default 0x100 + default 0x1000 help With sandbox the devicetree is loaded into the emulated RAM. This sets the address that is used. There must be enough space at this address diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 6407193c5f1..6db8739e66b 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -10,10 +10,10 @@ #include <errno.h> #include <log.h> #include <os.h> +#include <setjmp.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/malloc.h> -#include <asm/setjmp.h> #include <asm/state.h> #include <dm/ofnode.h> #include <linux/delay.h> diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index b8f3012873e..52e9ddbf50f 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1047,6 +1047,31 @@ }; }; + lvds-encoder { + compatible = "lvds-encoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + /* link to output */ + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + wdt-gpio-toggle { gpios = <&gpio_a 8 0>; compatible = "linux,wdt-gpio"; @@ -1402,6 +1427,27 @@ panel { compatible = "simple-panel"; backlight = <&backlight 0 100>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + hactive = <1280>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + vactive = <800>; + vfront-porch = <3>; + vback-porch = <12>; + vsync-len = <5>; + }; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; }; scsi { @@ -2048,6 +2094,61 @@ sandbox,err-step-size = <512>; }; }; + + graph1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + endpoint@0 { + reg = <0>; + }; + + endpoint@1 { + reg = <1>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + test-property-0; + }; + }; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + graph2_link: endpoint@0 { + reg = <0>; + test-property-1; + remote-endpoint = <&graph1_link>; + }; + + endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + graph2 { + port { + graph1_link: endpoint { + remote-endpoint = <&graph2_link>; + }; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/setjmp.h b/arch/sandbox/include/asm/setjmp.h index 001c7ea322d..3413c747783 100644 --- a/arch/sandbox/include/asm/setjmp.h +++ b/arch/sandbox/include/asm/setjmp.h @@ -4,8 +4,8 @@ * Written by Simon Glass <sjg@chromium.org> */ -#ifndef _SETJMP_H_ -#define _SETJMP_H_ +#ifndef _ASM_SETJMP_H_ +#define _ASM_SETJMP_H_ struct jmp_buf_data { /* @@ -19,17 +19,7 @@ struct jmp_buf_data { * We don't need to worry about 16-byte alignment, since this does not * run on Windows. */ - ulong data[128]; + unsigned long data[128]; }; -typedef struct jmp_buf_data jmp_buf[1]; - -/* - * We have to directly link with the system versions of - * setjmp/longjmp, because setjmp must not return as otherwise - * the stack may become invalid. - */ -int setjmp(jmp_buf jmp); -__noreturn void longjmp(jmp_buf jmp, int ret); - -#endif /* _SETJMP_H_ */ +#endif /* _ASM_SETJMP_H_ */ diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 99acc599965..56161ee72e4 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/system.h> +#include <linux/errno.h> #define CACHE_VALID 1 #define CACHE_UPDATED 2 @@ -126,3 +127,8 @@ int dcache_status(void) { return 0; } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h index 15915d0dc6b..13772574e15 100644 --- a/arch/x86/include/asm/setjmp.h +++ b/arch/x86/include/asm/setjmp.h @@ -5,8 +5,8 @@ * From Linux arch/um/sys-i386/setjmp.S */ -#ifndef __setjmp_h -#define __setjmp_h +#ifndef _ASM_SETJMP_H_ +#define _ASM_SETJMP_H_ 1 #ifdef CONFIG_X86_64 @@ -34,9 +34,4 @@ struct jmp_buf_data { #endif -typedef struct jmp_buf_data jmp_buf[1]; - -int setjmp(jmp_buf env); -void longjmp(jmp_buf env, int val); - -#endif +#endif /* _ASM_SETJMP_H_ */ diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c index e6a7f6827fc..1229b407783 100644 --- a/arch/xtensa/lib/cache.c +++ b/arch/xtensa/lib/cache.c @@ -6,6 +6,7 @@ #include <cpu_func.h> #include <asm/cache.h> +#include <linux/errno.h> /* * We currently run always with caches enabled when running from memory. @@ -57,3 +58,8 @@ void invalidate_icache_all(void) { __invalidate_icache_all(); } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} |