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-rw-r--r--arch/arm/cpu/armv7/omap-common/spl_nand.c2
-rw-r--r--arch/arm/include/asm/arch-spear/spr_i2c.h146
-rw-r--r--arch/blackfin/include/asm/config.h8
-rw-r--r--arch/blackfin/include/asm/global_data.h2
-rw-r--r--arch/blackfin/lib/board.c58
-rw-r--r--arch/nds32/cpu/n1213/ag102/Makefile58
-rw-r--r--arch/nds32/cpu/n1213/ag102/asm-offsets.c54
-rw-r--r--arch/nds32/cpu/n1213/ag102/cpu.c195
-rw-r--r--arch/nds32/cpu/n1213/ag102/lowlevel_init.S297
-rw-r--r--arch/nds32/cpu/n1213/ag102/timer.c205
-rw-r--r--arch/nds32/cpu/n1213/ag102/watchdog.S49
-rw-r--r--arch/nds32/include/asm/arch-ag102/ag102.h97
-rw-r--r--arch/nds32/include/asm/mach-types.h14
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S112
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand.lds4
-rw-r--r--arch/powerpc/cpu/mpc8xxx/srio.c210
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h46
-rw-r--r--arch/powerpc/include/asm/fsl_srio.h64
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h387
20 files changed, 1649 insertions, 368 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c
index 1295e887524..8cf55c9a1c8 100644
--- a/arch/arm/cpu/armv7/omap-common/spl_nand.c
+++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c
@@ -54,7 +54,7 @@ void spl_nand_load_image(void)
* load parameter image
* load to temp position since nand_spl_load_image reads
* a whole block which is typically larger than
- * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite
+ * CONFIG_CMD_SPL_WRITE_SIZE therefore may overwrite
* following sections like BSS
*/
nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS,
diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/arch/arm/include/asm/arch-spear/spr_i2c.h
deleted file mode 100644
index 7521ebc6cf0..00000000000
--- a/arch/arm/include/asm/arch-spear/spr_i2c.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_I2C_H_
-#define __SPR_I2C_H_
-
-struct i2c_regs {
- u32 ic_con;
- u32 ic_tar;
- u32 ic_sar;
- u32 ic_hs_maddr;
- u32 ic_cmd_data;
- u32 ic_ss_scl_hcnt;
- u32 ic_ss_scl_lcnt;
- u32 ic_fs_scl_hcnt;
- u32 ic_fs_scl_lcnt;
- u32 ic_hs_scl_hcnt;
- u32 ic_hs_scl_lcnt;
- u32 ic_intr_stat;
- u32 ic_intr_mask;
- u32 ic_raw_intr_stat;
- u32 ic_rx_tl;
- u32 ic_tx_tl;
- u32 ic_clr_intr;
- u32 ic_clr_rx_under;
- u32 ic_clr_rx_over;
- u32 ic_clr_tx_over;
- u32 ic_clr_rd_req;
- u32 ic_clr_tx_abrt;
- u32 ic_clr_rx_done;
- u32 ic_clr_activity;
- u32 ic_clr_stop_det;
- u32 ic_clr_start_det;
- u32 ic_clr_gen_call;
- u32 ic_enable;
- u32 ic_status;
- u32 ic_txflr;
- u32 ix_rxflr;
- u32 reserved_1;
- u32 ic_tx_abrt_source;
-};
-
-#define IC_CLK 166
-#define NANO_TO_MICRO 1000
-
-/* High and low times in different speed modes (in ns) */
-#define MIN_SS_SCL_HIGHTIME 4000
-#define MIN_SS_SCL_LOWTIME 5000
-#define MIN_FS_SCL_HIGHTIME 800
-#define MIN_FS_SCL_LOWTIME 1700
-#define MIN_HS_SCL_HIGHTIME 60
-#define MIN_HS_SCL_LOWTIME 160
-
-/* Worst case timeout for 1 byte is kept as 2ms */
-#define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
-#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
-#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
-
-/* i2c control register definitions */
-#define IC_CON_SD 0x0040
-#define IC_CON_RE 0x0020
-#define IC_CON_10BITADDRMASTER 0x0010
-#define IC_CON_10BITADDR_SLAVE 0x0008
-#define IC_CON_SPD_MSK 0x0006
-#define IC_CON_SPD_SS 0x0002
-#define IC_CON_SPD_FS 0x0004
-#define IC_CON_SPD_HS 0x0006
-#define IC_CON_MM 0x0001
-
-/* i2c target address register definitions */
-#define TAR_ADDR 0x0050
-
-/* i2c slave address register definitions */
-#define IC_SLAVE_ADDR 0x0002
-
-/* i2c data buffer and command register definitions */
-#define IC_CMD 0x0100
-
-/* i2c interrupt status register definitions */
-#define IC_GEN_CALL 0x0800
-#define IC_START_DET 0x0400
-#define IC_STOP_DET 0x0200
-#define IC_ACTIVITY 0x0100
-#define IC_RX_DONE 0x0080
-#define IC_TX_ABRT 0x0040
-#define IC_RD_REQ 0x0020
-#define IC_TX_EMPTY 0x0010
-#define IC_TX_OVER 0x0008
-#define IC_RX_FULL 0x0004
-#define IC_RX_OVER 0x0002
-#define IC_RX_UNDER 0x0001
-
-/* fifo threshold register definitions */
-#define IC_TL0 0x00
-#define IC_TL1 0x01
-#define IC_TL2 0x02
-#define IC_TL3 0x03
-#define IC_TL4 0x04
-#define IC_TL5 0x05
-#define IC_TL6 0x06
-#define IC_TL7 0x07
-#define IC_RX_TL IC_TL0
-#define IC_TX_TL IC_TL0
-
-/* i2c enable register definitions */
-#define IC_ENABLE_0B 0x0001
-
-/* i2c status register definitions */
-#define IC_STATUS_SA 0x0040
-#define IC_STATUS_MA 0x0020
-#define IC_STATUS_RFF 0x0010
-#define IC_STATUS_RFNE 0x0008
-#define IC_STATUS_TFE 0x0004
-#define IC_STATUS_TFNF 0x0002
-#define IC_STATUS_ACT 0x0001
-
-/* Speed Selection */
-#define IC_SPEED_MODE_STANDARD 1
-#define IC_SPEED_MODE_FAST 2
-#define IC_SPEED_MODE_MAX 3
-
-#define I2C_MAX_SPEED 3400000
-#define I2C_FAST_SPEED 400000
-#define I2C_STANDARD_SPEED 100000
-
-#endif /* __SPR_I2C_H_ */
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 1a8de4906da..25cd8338657 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -109,14 +109,8 @@
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#endif
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR (CONFIG_SYS_GBL_DATA_ADDR - GENERATED_BD_INFO_SIZE)
-#endif
#ifndef CONFIG_STACKBASE
-# define CONFIG_STACKBASE (CONFIG_SYS_BD_INFO_ADDR - 4)
+# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4)
#endif
#ifndef CONFIG_SYS_MEMTEST_START
# define CONFIG_SYS_MEMTEST_START 0
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index 67aa30f04c4..973ea2929a8 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -73,6 +73,6 @@ typedef struct global_data {
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
-#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3")
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P3")
#endif
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index e3ee4cd353e..2d424a2da0b 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -181,6 +181,46 @@ void init_cplbtables(void)
}
}
+static int global_board_data_init(void)
+{
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR 0
+#endif
+#ifndef CONFIG_SYS_BD_INFO_ADDR
+# define CONFIG_SYS_BD_INFO_ADDR 0
+#endif
+
+ bd_t *bd;
+
+ if (CONFIG_SYS_GBL_DATA_ADDR) {
+ gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
+ memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+ } else {
+ static gd_t _bfin_gd;
+ gd = &_bfin_gd;
+ }
+
+ if (CONFIG_SYS_BD_INFO_ADDR) {
+ bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
+ memset(bd, 0, GENERATED_BD_INFO_SIZE);
+ } else {
+ static bd_t _bfin_bd;
+ bd = &_bfin_bd;
+ }
+ gd->bd = bd;
+
+ bd->bi_r_version = version_string;
+ bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+ bd->bi_board_name = BFIN_BOARD_NAME;
+ bd->bi_vco = get_vco();
+ bd->bi_cclk = get_cclk();
+ bd->bi_sclk = get_sclk();
+ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+
+ return 0;
+}
+
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
@@ -201,7 +241,6 @@ extern int timer_init(void);
void board_init_f(ulong bootflag)
{
- bd_t *bd;
char buf[32];
#ifdef CONFIG_BOARD_EARLY_INIT_F
@@ -234,21 +273,8 @@ void board_init_f(ulong bootflag)
hang();
#endif
serial_early_puts("Init global data\n");
- gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
- memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-
- bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
- gd->bd = bd;
- memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
- bd->bi_r_version = version_string;
- bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
- bd->bi_board_name = BFIN_BOARD_NAME;
- bd->bi_vco = get_vco();
- bd->bi_cclk = get_cclk();
- bd->bi_sclk = get_sclk();
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ global_board_data_init();
/* Initialize */
serial_early_puts("IRQ init\n");
@@ -276,7 +302,7 @@ void board_init_f(ulong bootflag)
if (CONFIG_MEM_SIZE) {
printf("RAM: ");
- print_size(bd->bi_memsize, "\n");
+ print_size(gd->bd->bi_memsize, "\n");
}
#if defined(CONFIG_POST)
diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile
new file mode 100644
index 00000000000..8716c4e858c
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y := cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
new file mode 100644
index 00000000000..4769a9521dc
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
@@ -0,0 +1,54 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+ OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
+ OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
+#endif
+ BLANK();
+#ifdef CONFIG_FTAHBC020S
+ OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
+ OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
+#endif
+ BLANK();
+#ifdef CONFIG_ANDES_PCU
+ OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
+#endif
+ BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+ OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
+ OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
+ OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
+ OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
+ OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
+ OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
+ OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
+ OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
+ OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
+ OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
+ OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
+ OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
+ OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
+ OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
+ OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
+ OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
+ OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
+#endif
+ return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
new file mode 100644
index 00000000000..ed88b522a49
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+ * reset to the base addr of andesboot.
+ * currently no ROM loader at addr 0.
+ * do not use reset_cpu(0);
+ */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+ /*
+ * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+ * automatic hardware reset when booting Linux.
+ * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+ */
+ ftwdt010_wdt_reset();
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+ hang();
+
+ /*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+ if (cache == ICACHE)
+ return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+ >> ICM_CFG_OFF_ISZ) - 1);
+ else
+ return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+ >> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(ICACHE);
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ dcache_flush_range(addr, addr + size);
+ icache_inval_range(addr, addr + size);
+}
+
+void icache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x01\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void icache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x01\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int icache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x01\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
+
+void dcache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x02\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void dcache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x02\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int dcache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x02\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S
new file mode 100644
index 00000000000..d842afa4ba6
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE)
+#define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR)
+#define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR)
+#define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
+#define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR)
+#define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR)
+#define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
+#define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
+#define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
+#define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
+#define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
+#define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
+#define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
+#define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
+#define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
+#define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
+#define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
+#define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
+#define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
+#define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR)
+
+#define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR
+#define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2
+#define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR
+#define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR
+#define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR
+#define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR
+#define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0
+#define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0
+#define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR
+#define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR
+
+#define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the ANDES PCU controller
+ */
+#define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
+#define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+/*
+.macro wait_sdram
+ li $r0, DDR2C_CSR_A
+1:
+ lwi $r1, [$r0+FTSDMC021_CR2]
+ bnez $r1, 1b
+.endm
+*/
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+
+ /* U200 */
+! led 0x00
+! jal scale_to_500mhz
+
+ led 0x10
+ jal mem_init
+
+ led 0x20
+ jal remap
+
+ led 0x30
+ ret $r10
+
+scale_to_500mhz:
+ move $r11, $lp
+
+ /*
+ * scale to 500Mhz
+ */
+ led 0x01
+ write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4
+
+ move $lp, $r11
+ ret
+
+mem_init:
+ move $r11, $lp
+
+ /*
+ * config AHB Controller
+ */
+ led 0x12
+ write32 AHBC_BSR6_A, AHBC_BSR6_D
+
+ /*
+ * config Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+ddr2c_init:
+set_dcr:
+ led 0x14
+ write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4
+
+auto_sizing:
+ /*
+ * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
+ */
+set_iocr:
+ led 0x19
+ write32 DDR2C_IOCR_A, DDR2C_IOCR_D
+set_drr:
+ led 0x16
+ write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812
+set_dllcr:
+ led 0x18
+ write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
+set_rslr0:
+ write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040
+set_rdgr0:
+ write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf
+set_dtar:
+ led 0x15
+ write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000
+set_mode:
+ led 0x17
+ write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852
+set_ccr:
+ write32 DDR2C_CCR_A, DDR2C_CCR_D
+
+#ifdef TRIGGER_INIT:
+trigger_init:
+ write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000
+
+ /* Wait for ddr init state to be set */
+ msync ALL
+ isb
+
+ /* Wait until the config initialization is finish */
+1:
+ la $r4, DDR2C_CSR_A
+ lwi $r5, [$r4]
+ srli $r5, $r5, 23
+ bnez $r5, 1b
+#endif
+
+data_training:
+! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004
+
+ /* Wait for ddr init state to be set */
+ msync ALL
+ isb
+
+ /* wait until the ddr data trainning is complete */
+1:
+ la $r4, DDR2C_CSR_A
+ lwi $r5, [$r4]
+ srli $r6, $r5, 23
+ bnez $r6, 1b
+
+ lwi $r1, [$r4]
+ srli $r6, $r5, 20
+ li $r5, 0x00ffffff
+ swi $r1, [$r4]
+ bnez $r6, ddr2c_init
+
+ led 0x1a
+ move $lp, $r11
+ ret
+
+remap:
+ move $r11, $lp
+#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
+ bal 2f
+relo_base:
+ move $r0, $lp
+#else
+relo_base:
+ mfusr $r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+ /*
+ * Remapping
+ */
+#ifdef CONFIG_MEM_REMAP
+ /*
+ * Copy ROM code to SDRAM base for memory remap layout.
+ * This is not the real relocation, the real relocation is the function
+ * relocate_code() is start.S which supports the systems is memory
+ * remapped or not.
+ */
+ /*
+ * Doing memory remap is essential for preparing some non-OS or RTOS
+ * applications.
+ *
+ * This is also a must on ADP-AG101 board.
+ * The reason is because the ROM/FLASH circuit on PCB board.
+ * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+ * ROM/FLASH is used to boot.
+ *
+ * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+ * and the FLASH is connected to BANK1.
+ * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+ * and the FLASH is connected to BANK0.
+ * It will occur problem when doing flash probing if the flash is at
+ * BANK0 (0x00000000) while memory remapping was skipped.
+ *
+ * Other board like ADP-AG101P may not enable this since there is only
+ * a FLASH connected to bank0.
+ */
+ led 0x21
+ li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
+ li $r5, 0x0
+ la $r1, relo_base /* get $pc or $lp */
+ sub $r2, $r0, $r1
+ sethi $r6, hi20(_end)
+ ori $r6, $r6, lo12(_end)
+ add $r6, $r6, $r2
+1:
+ lwi.p $r7, [$r5], #4
+ swi.p $r7, [$r4], #4
+ blt $r5, $r6, 1b
+
+ /* set remap bit */
+ /*
+ * MEM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+ * - after remap: flash/rom 0x80000000, sdram: 0x00000000
+ */
+ led 0x2c
+ setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+ move $lp, $r11
+2:
+ ret
+
+.globl show_led
+show_led:
+ li $r8, (CONFIG_DEBUG_LED)
+ swi $r7, [$r8]
+ ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag102/timer.c b/arch/nds32/cpu/n1213/ag102/timer.c
new file mode 100644
index 00000000000..caa36b8be83
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/timer.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ /* use 32768Hz oscillator for RTC, WDT, TIMER */
+ ftpmu010_32768osc_enable();
+#endif
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+#endif
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ ulong now = readl(&tmr->timer3_counter) / \
+ (CONFIG_SYS_CLK_FREQ / 2 / 1024);
+#endif
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+ long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ return CONFIG_SYS_HZ;
+#else
+ return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag102/watchdog.S b/arch/nds32/cpu/n1213/ag102/watchdog.S
new file mode 100644
index 00000000000..56cecda78f5
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/watchdog.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag102/ag102.h>
+#include <linux/linkage.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ENTRY(turnoff_watchdog)
+
+#define WD_CR 0xC
+#define WD_ENABLE 0x1
+
+ ! Turn off the watchdog, according to Faraday FTWDT010 spec
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ lwi $p1, [$p0] ! Get the config of WD
+ andi $p1, $p1, 0x1f ! Wipe out useless bits
+ li $r0, ~WD_ENABLE
+ and $p1, $p1, $r0 ! Set WD disable
+ sw $p1, [$p0] ! Write back to WD CR
+
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ret
+
+ENDPROC(turnoff_watchdog)
+#endif
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
new file mode 100644
index 00000000000..a12a8c52b73
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG102_H
+#define __AG102_H
+
+/*
+ * Hardware register bases
+ */
+
+/* PCI Controller */
+#define CONFIG_FTPCI100_BASE 0x90000000
+/* LPC Controller */
+#define CONFIG_LPC_IO_BASE 0x90100000
+/* LPC Controller */
+#define CONFIG_LPC_BASE 0x90200000
+
+/* NDS32 Data Local Memory 01 */
+#define CONFIG_NDS_DLM1_BASE 0x90300000
+/* NDS32 Data Local Memory 02 */
+#define CONFIG_NDS_DLM2_BASE 0x90400000
+
+/* Synopsys DWC DDR2/1 Controller */
+#define CONFIG_DWCDDR21MCTL_BASE 0x90500000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE 0x90600000
+/* FTIDE020_S IDE (ATA) Controller */
+#define CONFIG_FTIDE020S_BASE 0x90700000
+/* USB OTG Controller */
+#define CONFIG_FZOTG266HD0A_BASE 0x90800000
+/* Andes L2 Cache Controller */
+#define CONFIG_NCEL2C100_BASE 0x90900000
+/* XGI XG22 GPU */
+#define CONFIG_XGI_XG22_BASE 0x90A00000
+/* GMAC Ethernet Controller */
+#define CONFIG_FTGMAC100_BASE 0x90B00000
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE 0x90C00000
+/* AHB-to-APB Bridge Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
+/* External AHB2AHB Controller */
+#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
+/* Andes Multi-core Interrupt Controller */
+#define CONFIG_NCEMIC100_BASE 0x90F00000
+
+/*
+ * APB Device definitions
+ */
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE 0x94000000
+/* APB - SSP (SPI) (without AC97) Controller */
+#define CONFIG_FTSSP010_01_BASE 0x94100000
+/* UART1 - APB STUART Controller (UART0 in Linux) */
+#define CONFIG_FTUART010_01_BASE 0x94200000
+/* FTSDC010 SD Controller */
+#define CONFIG_FTSDC010_BASE 0x94400000
+/* APB - SSP with HDA/AC97 Controller */
+#define CONFIG_FTSSP010_02_BASE 0x94500000
+/* UART2 - APB STUART Controller (UART1 in Linux) */
+#define CONFIG_FTUART010_02_BASE 0x94600000
+/* PCU Controller */
+#define CONFIG_ANDES_PCU_BASE 0x94800000
+/* FTTMR010 Timer */
+#define CONFIG_FTTMR010_BASE 0x94900000
+/* Watch Dog Controller */
+#define CONFIG_FTWDT010_BASE 0x94A00000
+/* FTRTC010 Real Time Clock */
+#define CONFIG_FTRTC010_BASE 0x98B00000
+/* GPIO Controller */
+#define CONFIG_FTGPIO010_BASE 0x94C00000
+/* I2C Controller */
+#define CONFIG_FTIIC010_BASE 0x94E00000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_FTPWM010_BASE 0x94F00000
+
+/* Debug LED */
+#define CONFIG_DEBUG_LED 0x902FFFFC
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE 0x98100000
+
+#endif /* __AG102_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
index 7b52b989bc1..259e4e7ad94 100644
--- a/arch/nds32/include/asm/mach-types.h
+++ b/arch/nds32/include/asm/mach-types.h
@@ -40,4 +40,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_adpag101p() (1)
#endif
+#define MACH_TYPE_ADPAG102 2
+
+#ifdef CONFIG_ARCH_ADPAG102
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADPAG102
+# endif
+# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102)
+#else
+# define machine_is_adpag102() (2)
+#endif
+
#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2e4a06c35ab..2cd5db7c59b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,7 @@
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
+#include <asm/fsl_srio.h>
#include <linux/compiler.h>
#include "mp.h"
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void);
-
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -443,6 +442,12 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
+#ifdef CONFIG_SRIOBOOT_MASTER
+ srio_boot_master();
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+ srio_boot_master_release_slave();
+#endif
+#endif
#endif
#if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4d37d6e8638..8e99ef6c688 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@@ -179,41 +179,50 @@ l2_disabled:
andi. r1,r3,L1CSR0_DCE@l
beq 2b
+/*
+ * Ne need to setup interrupt vector for NAND SPL
+ * because NAND SPL never compiles it.
+ */
+#if !defined(CONFIG_NAND_SPL)
/* Setup interrupt vectors */
lis r1,CONFIG_SYS_MONITOR_BASE@h
mtspr IVPR,r1
- li r1,0x0100
- mtspr IVOR0,r1 /* 0: Critical input */
- li r1,0x0200
- mtspr IVOR1,r1 /* 1: Machine check */
- li r1,0x0300
- mtspr IVOR2,r1 /* 2: Data storage */
- li r1,0x0400
- mtspr IVOR3,r1 /* 3: Instruction storage */
- li r1,0x0500
- mtspr IVOR4,r1 /* 4: External interrupt */
- li r1,0x0600
- mtspr IVOR5,r1 /* 5: Alignment */
- li r1,0x0700
- mtspr IVOR6,r1 /* 6: Program check */
- li r1,0x0800
- mtspr IVOR7,r1 /* 7: floating point unavailable */
- li r1,0x0900
- mtspr IVOR8,r1 /* 8: System call */
+ lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
+ ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
+
+ addi r4,r3,CriticalInput - _start + _START_OFFSET
+ mtspr IVOR0,r4 /* 0: Critical input */
+ addi r4,r3,MachineCheck - _start + _START_OFFSET
+ mtspr IVOR1,r4 /* 1: Machine check */
+ addi r4,r3,DataStorage - _start + _START_OFFSET
+ mtspr IVOR2,r4 /* 2: Data storage */
+ addi r4,r3,InstStorage - _start + _START_OFFSET
+ mtspr IVOR3,r4 /* 3: Instruction storage */
+ addi r4,r3,ExtInterrupt - _start + _START_OFFSET
+ mtspr IVOR4,r4 /* 4: External interrupt */
+ addi r4,r3,Alignment - _start + _START_OFFSET
+ mtspr IVOR5,r4 /* 5: Alignment */
+ addi r4,r3,ProgramCheck - _start + _START_OFFSET
+ mtspr IVOR6,r4 /* 6: Program check */
+ addi r4,r3,FPUnavailable - _start + _START_OFFSET
+ mtspr IVOR7,r4 /* 7: floating point unavailable */
+ addi r4,r3,SystemCall - _start + _START_OFFSET
+ mtspr IVOR8,r4 /* 8: System call */
/* 9: Auxiliary processor unavailable(unsupported) */
- li r1,0x0a00
- mtspr IVOR10,r1 /* 10: Decrementer */
- li r1,0x0b00
- mtspr IVOR11,r1 /* 11: Interval timer */
- li r1,0x0c00
- mtspr IVOR12,r1 /* 12: Watchdog timer */
- li r1,0x0d00
- mtspr IVOR13,r1 /* 13: Data TLB error */
- li r1,0x0e00
- mtspr IVOR14,r1 /* 14: Instruction TLB error */
- li r1,0x0f00
- mtspr IVOR15,r1 /* 15: Debug */
+ addi r4,r3,Decrementer - _start + _START_OFFSET
+ mtspr IVOR10,r4 /* 10: Decrementer */
+ addi r4,r3,IntervalTimer - _start + _START_OFFSET
+ mtspr IVOR11,r4 /* 11: Interval timer */
+ addi r4,r3,WatchdogTimer - _start + _START_OFFSET
+ mtspr IVOR12,r4 /* 12: Watchdog timer */
+ addi r4,r3,DataTLBError - _start + _START_OFFSET
+ mtspr IVOR13,r4 /* 13: Data TLB error */
+ addi r4,r3,InstructionTLBError - _start + _START_OFFSET
+ mtspr IVOR14,r4 /* 14: Instruction TLB error */
+ addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
+ mtspr IVOR15,r4 /* 15: Debug */
+#endif
/* Clear and set up some registers. */
li r0,0x0000
@@ -434,13 +443,15 @@ create_ccsr_new_tlb:
ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+#ifdef CONFIG_ENABLE_36BIT_PHYS
lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ mtspr MAS7, r7
+#endif
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
mtspr MAS3, r3
- mtspr MAS7, r7
isync
msync
tlbwe
@@ -456,12 +467,14 @@ create_ccsr_old_tlb:
ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
+#ifdef CONFIG_ENABLE_36BIT_PHYS
li r7, 0 /* The default CCSR address is always a 32-bit number */
+ mtspr MAS7, r7
+#endif
mtspr MAS0, r0
/* MAS1 is the same as above */
mtspr MAS2, r2
mtspr MAS3, r3
- mtspr MAS7, r7
isync
msync
tlbwe
@@ -1490,6 +1503,39 @@ trap_init:
cmplw 0,r7,r8
blt 2b
+ /* Update IVORs as per relocated vector table address */
+ li r7,0x0100
+ mtspr IVOR0,r7 /* 0: Critical input */
+ li r7,0x0200
+ mtspr IVOR1,r7 /* 1: Machine check */
+ li r7,0x0300
+ mtspr IVOR2,r7 /* 2: Data storage */
+ li r7,0x0400
+ mtspr IVOR3,r7 /* 3: Instruction storage */
+ li r7,0x0500
+ mtspr IVOR4,r7 /* 4: External interrupt */
+ li r7,0x0600
+ mtspr IVOR5,r7 /* 5: Alignment */
+ li r7,0x0700
+ mtspr IVOR6,r7 /* 6: Program check */
+ li r7,0x0800
+ mtspr IVOR7,r7 /* 7: floating point unavailable */
+ li r7,0x0900
+ mtspr IVOR8,r7 /* 8: System call */
+ /* 9: Auxiliary processor unavailable(unsupported) */
+ li r7,0x0a00
+ mtspr IVOR10,r7 /* 10: Decrementer */
+ li r7,0x0b00
+ mtspr IVOR11,r7 /* 11: Interval timer */
+ li r7,0x0c00
+ mtspr IVOR12,r7 /* 12: Watchdog timer */
+ li r7,0x0d00
+ mtspr IVOR13,r7 /* 13: Data TLB error */
+ li r7,0x0e00
+ mtspr IVOR14,r7 /* 14: Instruction TLB error */
+ li r7,0x0f00
+ mtspr IVOR15,r7 /* 15: Debug */
+
lis r7,0x0
mtspr IVPR,r7
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index 04bc73170a9..b1a1dac16f0 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -87,7 +87,7 @@ SECTIONS
.bootpg ADDR(.text) - 0x1000 :
{
- arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg))
+ KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
. = ADDR(.text) + 0x80000;
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328067d..c7f394972bf 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,16 @@
#include <config.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
+#include <asm/fsl_srio.h>
+
+#define SRIO_PORT_ACCEPT_ALL 0x10000001
+#define SRIO_IB_ATMU_AR 0x80f55000
+#define SRIO_OB_ATMU_AR_MAINT 0x80077000
+#define SRIO_OB_ATMU_AR_RW 0x80045000
+#define SRIO_LCSBA1CSR_OFFSET 0x5c
+#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
+#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
+#define SRIO_LCSBA1CSR 0x60000000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +94,203 @@ void srio_init(void)
setbits_be32(&gur->devdisr, _DEVDISR_RMU);
}
}
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ /* set port accept-all */
+ out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+ SRIO_PORT_ACCEPT_ALL);
+
+ debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /* configure inbound window for slave's u-boot image */
+ debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
+ "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window for slave's u-boot image */
+ debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
+ "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
+ (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+ /* configure inbound window for slave's ucode */
+ debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
+ "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+ (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+ /* configure inbound window for slave's ENV */
+ debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; "
+ "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n",
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
+ CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
+ SRIO_IB_ATMU_AR
+ | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
+}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+ struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ u32 escsr;
+ debug("SRIOBOOT - MASTER: "
+ "Check the port status and release slave core ...\n");
+
+ escsr = in_be32((void *)&srio->lp_serial
+ .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
+ if (escsr & 0x2) {
+ if (escsr & 0x10100) {
+ debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ } else {
+ debug("SRIOBOOT - MASTER: "
+ "Port [ %d ] is ready, now release slave's core ...\n",
+ CONFIG_SRIOBOOT_MASTER_PORT);
+ /*
+ * configure outbound window
+ * with maintenance attribute to set slave's LCSBA1CSR
+ */
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtar, 0);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowtear, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
+ else
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowbar,
+ CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[1].rowar,
+ SRIO_OB_ATMU_AR_MAINT
+ | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
+
+ /*
+ * configure outbound window
+ * with R/W attribute to set slave's BRR
+ */
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[2].rowtar,
+ SRIO_LCSBA1CSR >> 9);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[2].rowtear, 0);
+ if (CONFIG_SRIOBOOT_MASTER_PORT)
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[2].rowbar,
+ (CONFIG_SYS_SRIO2_MEM_PHYS
+ + SRIO_MAINT_WIN_SIZE) >> 12);
+ else
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[2].rowbar,
+ (CONFIG_SYS_SRIO1_MEM_PHYS
+ + SRIO_MAINT_WIN_SIZE) >> 12);
+ out_be32((void *)&srio->atmu
+ .port[CONFIG_SRIOBOOT_MASTER_PORT]
+ .outbw[2].rowar,
+ SRIO_OB_ATMU_AR_RW
+ | atmu_size_mask(SRIO_RW_WIN_SIZE));
+
+ /*
+ * Set the LCSBA1CSR register in slave
+ * by the maint-outbound window
+ */
+ if (CONFIG_SRIOBOOT_MASTER_PORT) {
+ out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ + SRIO_LCSBA1CSR_OFFSET,
+ SRIO_LCSBA1CSR);
+ while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ + SRIO_LCSBA1CSR_OFFSET)
+ != SRIO_LCSBA1CSR)
+ ;
+ /*
+ * And then set the BRR register
+ * to release slave core
+ */
+ out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ + SRIO_MAINT_WIN_SIZE
+ + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
+ CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+ } else {
+ out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ + SRIO_LCSBA1CSR_OFFSET,
+ SRIO_LCSBA1CSR);
+ while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ + SRIO_LCSBA1CSR_OFFSET)
+ != SRIO_LCSBA1CSR)
+ ;
+ /*
+ * And then set the BRR register
+ * to release slave core
+ */
+ out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ + SRIO_MAINT_WIN_SIZE
+ + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
+ CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+ }
+ debug("SRIOBOOT - MASTER: "
+ "Release slave successfully! Now the slave should start up!\n");
+ }
+ } else
+ debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n",
+ CONFIG_SRIOBOOT_MASTER_PORT);
+}
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 8654625facc..191629b6284 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -65,6 +65,11 @@
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1
@@ -85,6 +90,11 @@
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_MPC8569)
#define CONFIG_MAX_CPUS 1
@@ -94,6 +104,11 @@
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_MPC8572)
#define CONFIG_MAX_CPUS 2
@@ -298,6 +313,11 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_PPC_P2040)
#define CONFIG_MAX_CPUS 4
@@ -317,6 +337,9 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P2041)
#define CONFIG_MAX_CPUS 4
@@ -338,6 +361,9 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
@@ -359,6 +385,9 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
@@ -375,6 +404,9 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
@@ -387,6 +419,9 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
@@ -417,6 +452,11 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)
@@ -438,6 +478,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS 2
@@ -458,6 +501,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#error Processor type not defined for this platform
diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h
new file mode 100644
index 00000000000..a905a266c4d
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_srio.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FSL_SRIO_H_
+#define _FSL_SRIO_H_
+
+enum atmu_size {
+ ATMU_SIZE_4K = 0xb,
+ ATMU_SIZE_8K,
+ ATMU_SIZE_16K,
+ ATMU_SIZE_32K,
+ ATMU_SIZE_64K,
+ ATMU_SIZE_128K,
+ ATMU_SIZE_256K,
+ ATMU_SIZE_512K,
+ ATMU_SIZE_1M,
+ ATMU_SIZE_2M,
+ ATMU_SIZE_4M,
+ ATMU_SIZE_8M,
+ ATMU_SIZE_16M,
+ ATMU_SIZE_32M,
+ ATMU_SIZE_64M,
+ ATMU_SIZE_128M,
+ ATMU_SIZE_256M,
+ ATMU_SIZE_512M,
+ ATMU_SIZE_1G,
+ ATMU_SIZE_2G,
+ ATMU_SIZE_4G,
+ ATMU_SIZE_8G,
+ ATMU_SIZE_16G,
+ ATMU_SIZE_32G,
+ ATMU_SIZE_64G,
+};
+
+#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1)
+#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1))
+
+extern void srio_init(void);
+#ifdef CONFIG_SRIOBOOT_MASTER
+extern void srio_boot_master(void);
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+extern void srio_boot_master_release_slave(void);
+#endif
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9b08cb8c1ab..632e3c1669d 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm {
} ccsr_cpm_t;
#endif
-/* RapidIO Registers */
-typedef struct ccsr_rio {
- u32 didcar; /* Device Identity Capability */
- u32 dicar; /* Device Information Capability */
- u32 aidcar; /* Assembly Identity Capability */
- u32 aicar; /* Assembly Information Capability */
- u32 pefcar; /* Processing Element Features Capability */
- u32 spicar; /* Switch Port Information Capability */
- u32 socar; /* Source Operations Capability */
- u32 docar; /* Destination Operations Capability */
+#ifdef CONFIG_SYS_SRIO
+/* Architectural regsiters */
+struct rio_arch {
+ u32 didcar; /* Device Identity CAR */
+ u32 dicar; /* Device Information CAR */
+ u32 aidcar; /* Assembly Identity CAR */
+ u32 aicar; /* Assembly Information CAR */
+ u32 pefcar; /* Processing Element Features CAR */
+ u8 res0[4];
+ u32 socar; /* Source Operations CAR */
+ u32 docar; /* Destination Operations CAR */
u8 res1[32];
- u32 msr; /* Mailbox Cmd And Status */
- u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */
+ u32 mcsr; /* Mailbox CSR */
+ u32 pwdcsr; /* Port-Write and Doorbell CSR */
u8 res2[4];
u32 pellccsr; /* Processing Element Logic Layer CCSR */
u8 res3[12];
- u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */
- u32 bdidcsr; /* Base Device ID Cmd & Status */
+ u32 lcsbacsr; /* Local Configuration Space BACSR */
+ u32 bdidcsr; /* Base Device ID CSR */
u8 res4[4];
- u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */
- u32 ctcsr; /* Component Tag Cmd & Status */
- u8 res5[144];
- u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */
- u8 res6[28];
- u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */
- u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */
- u8 res7[20];
- u32 pgccsr; /* Port General Cmd & Status */
- u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */
- u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */
- u32 plascsr; /* Port Local Ackid Status Cmd & Status */
- u8 res8[12];
- u32 pescsr; /* Port Error & Status Cmd & Status */
- u32 pccsr; /* Port Control Cmd & Status */
- u8 res9[65184];
- u32 cr; /* Port Control Cmd & Status */
- u8 res10[12];
- u32 pcr; /* Port Configuration */
- u32 peir; /* Port Error Injection */
- u8 res11[3048];
- u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */
- u8 res12[12];
- u32 rowar0; /* RIO Outbound Attrs 0 */
- u8 res13[12];
- u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */
- u8 res14[4];
- u32 rowbar1; /* RIO Outbound Window Base Addr 1 */
- u8 res15[4];
- u32 rowar1; /* RIO Outbound Attrs 1 */
- u8 res16[12];
- u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */
- u8 res17[4];
- u32 rowbar2; /* RIO Outbound Window Base Addr 2 */
- u8 res18[4];
- u32 rowar2; /* RIO Outbound Attrs 2 */
- u8 res19[12];
- u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */
- u8 res20[4];
- u32 rowbar3; /* RIO Outbound Window Base Addr 3 */
- u8 res21[4];
- u32 rowar3; /* RIO Outbound Attrs 3 */
- u8 res22[12];
- u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */
- u8 res23[4];
- u32 rowbar4; /* RIO Outbound Window Base Addr 4 */
- u8 res24[4];
- u32 rowar4; /* RIO Outbound Attrs 4 */
- u8 res25[12];
- u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */
- u8 res26[4];
- u32 rowbar5; /* RIO Outbound Window Base Addr 5 */
- u8 res27[4];
- u32 rowar5; /* RIO Outbound Attrs 5 */
- u8 res28[12];
- u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */
- u8 res29[4];
- u32 rowbar6; /* RIO Outbound Window Base Addr 6 */
- u8 res30[4];
- u32 rowar6; /* RIO Outbound Attrs 6 */
- u8 res31[12];
- u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */
- u8 res32[4];
- u32 rowbar7; /* RIO Outbound Window Base Addr 7 */
- u8 res33[4];
- u32 rowar7; /* RIO Outbound Attrs 7 */
- u8 res34[12];
- u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */
- u8 res35[4];
- u32 rowbar8; /* RIO Outbound Window Base Addr 8 */
- u8 res36[4];
- u32 rowar8; /* RIO Outbound Attrs 8 */
- u8 res37[76];
- u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */
- u8 res38[4];
- u32 riwbar4; /* RIO Inbound Window Base Addr 4 */
- u8 res39[4];
- u32 riwar4; /* RIO Inbound Attrs 4 */
- u8 res40[12];
- u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */
- u8 res41[4];
- u32 riwbar3; /* RIO Inbound Window Base Addr 3 */
- u8 res42[4];
- u32 riwar3; /* RIO Inbound Attrs 3 */
- u8 res43[12];
- u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */
- u8 res44[4];
- u32 riwbar2; /* RIO Inbound Window Base Addr 2 */
- u8 res45[4];
- u32 riwar2; /* RIO Inbound Attrs 2 */
- u8 res46[12];
- u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */
- u8 res47[4];
- u32 riwbar1; /* RIO Inbound Window Base Addr 1 */
- u8 res48[4];
- u32 riwar1; /* RIO Inbound Attrs 1 */
- u8 res49[12];
- u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */
- u8 res50[12];
- u32 riwar0; /* RIO Inbound Attrs 0 */
- u8 res51[12];
- u32 pnfedr; /* Port Notification/Fatal Error Detect */
- u32 pnfedir; /* Port Notification/Fatal Error Detect */
- u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */
- u32 pecr; /* Port Error Control */
- u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */
- u32 pepr1; /* Port Error Packet 1 */
- u32 pepr2; /* Port Error Packet 2 */
- u8 res52[4];
- u32 predr; /* Port Recoverable Error Detect */
- u8 res53[4];
- u32 pertr; /* Port Error Recovery Threshold */
- u32 prtr; /* Port Retry Threshold */
- u8 res54[464];
- u32 omr; /* Outbound Mode */
- u32 osr; /* Outbound Status */
- u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */
- u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */
- u32 eosar; /* Extended Outbound Unit Source Addr */
- u32 osar; /* Outbound Unit Source Addr */
- u32 odpr; /* Outbound Destination Port */
- u32 odatr; /* Outbound Destination Attrs */
- u32 odcr; /* Outbound Doubleword Count */
- u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */
- u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */
- u8 res55[52];
- u32 imr; /* Outbound Mode */
- u32 isr; /* Inbound Status */
- u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */
- u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */
- u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */
- u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */
- u8 res56[1000];
- u32 dmr; /* Doorbell Mode */
- u32 dsr; /* Doorbell Status */
- u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */
- u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */
- u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */
- u32 dqhpar; /* Doorbell Queue Head Ptr Addr */
- u8 res57[104];
- u32 pwmr; /* Port-Write Mode */
- u32 pwsr; /* Port-Write Status */
- u32 epwqbar; /* Extended Port-Write Queue Base Addr */
- u32 pwqbar; /* Port-Write Queue Base Addr */
- u8 res58[60176];
-} ccsr_rio_t;
+ u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
+ u32 ctcsr; /* Component Tag CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial Port registers */
+struct rio_lp_serial_port {
+ u32 plmreqcsr; /* Port Link Maintenance Request CSR */
+ u32 plmrespcsr; /* Port Link Maintenance Response CS */
+ u32 plascsr; /* Port Local Ackid Status CSR */
+ u8 res0[12];
+ u32 pescsr; /* Port Error and Status CSR */
+ u32 pccsr; /* Port Control CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial registers */
+struct rio_lp_serial {
+ u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
+ u8 res0[28];
+ u32 pltoccsr; /* Port Link Time-out CCSR */
+ u32 prtoccsr; /* Port Response Time-out CCSR */
+ u8 res1[20];
+ u32 pgccsr; /* Port General CSR */
+ struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Logical error reporting registers */
+struct rio_logical_err {
+ u32 erbh; /* Error Reporting Block Header Register */
+ u8 res0[4];
+ u32 ltledcsr; /* Logical/Transport layer error DCSR */
+ u32 ltleecsr; /* Logical/Transport layer error ECSR */
+ u8 res1[4];
+ u32 ltlaccsr; /* Logical/Transport layer ACCSR */
+ u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
+ u32 ltlcccsr; /* Logical/Transport layer control CCSR */
+};
+
+/* Physical error reporting port registers */
+struct rio_phys_err_port {
+ u32 edcsr; /* Port error detect CSR */
+ u32 erecsr; /* Port error rate enable CSR */
+ u32 ecacsr; /* Port error capture attributes CSR */
+ u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
+ u32 peccsr[3]; /* Port error capture CSR */
+ u8 res0[12];
+ u32 ercsr; /* Port error rate CSR */
+ u32 ertcsr; /* Port error rate threshold CSR */
+ u8 res1[16];
+};
+
+/* Physical error reporting registers */
+struct rio_phys_err {
+ struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Implementation Space: General Port-Common */
+struct rio_impl_common {
+ u8 res0[4];
+ u32 llcr; /* Logical Layer Configuration Register */
+ u8 res1[8];
+ u32 epwisr; /* Error / Port-Write Interrupt SR */
+ u8 res2[12];
+ u32 lretcr; /* Logical Retry Error Threshold CR */
+ u8 res3[92];
+ u32 pretcr; /* Physical Retry Erorr Threshold CR */
+ u8 res4[124];
+};
+
+/* Implementation Space: Port Specific */
+struct rio_impl_port_spec {
+ u32 adidcsr; /* Port Alt. Device ID CSR */
+ u8 res0[28];
+ u32 ptaacr; /* Port Pass-Through/Accept-All CR */
+ u32 lopttlcr;
+ u8 res1[8];
+ u32 iecsr; /* Port Implementation Error CSR */
+ u8 res2[12];
+ u32 pcr; /* Port Phsyical Configuration Register */
+ u8 res3[20];
+ u32 slcsr; /* Port Serial Link CSR */
+ u8 res4[4];
+ u32 sleicr; /* Port Serial Link Error Injection */
+ u32 a0txcr; /* Port Arbitration 0 Tx CR */
+ u32 a1txcr; /* Port Arbitration 1 Tx CR */
+ u32 a2txcr; /* Port Arbitration 2 Tx CR */
+ u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
+ u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
+};
+
+/* Implementation Space: register */
+struct rio_implement {
+ struct rio_impl_common com;
+ struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Revision Control Register */
+struct rio_rev_ctrl {
+ u32 ipbrr[2]; /* IP Block Revision Register */
+};
+
+struct rio_atmu_row {
+ u32 rowtar; /* RapidIO Outbound Window TAR */
+ u32 rowtear; /* RapidIO Outbound Window TEAR */
+ u32 rowbar;
+ u8 res0[4];
+ u32 rowar; /* RapidIO Outbound Attributes Register */
+ u32 rowsr[3]; /* Port RapidIO outbound window segment register */
+};
+
+struct rio_atmu_riw {
+ u32 riwtar; /* RapidIO Inbound Window Translation AR */
+ u8 res0[4];
+ u32 riwbar; /* RapidIO Inbound Window Base AR */
+ u8 res1[4];
+ u32 riwar; /* RapidIO Inbound Attributes Register */
+ u8 res2[12];
+};
+
+/* ATMU window registers */
+struct rio_atmu_win {
+ struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+ u8 res0[64];
+ struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+};
+
+struct rio_atmu {
+ struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+#ifdef CONFIG_SYS_FSL_RMU
+struct rio_msg {
+ u32 omr; /* Outbound Mode Register */
+ u32 osr; /* Outbound Status Register */
+ u32 eodqdpar; /* Extended Outbound DQ DPAR */
+ u32 odqdpar; /* Outbound Descriptor Queue DPAR */
+ u32 eosar; /* Extended Outbound Unit Source AR */
+ u32 osar; /* Outbound Unit Source AR */
+ u32 odpr; /* Outbound Destination Port Register */
+ u32 odatr; /* Outbound Destination Attributes Register */
+ u32 odcr; /* Outbound Doubleword Count Register */
+ u32 eodqepar; /* Extended Outbound DQ EPAR */
+ u32 odqepar; /* Outbound Descriptor Queue EPAR */
+ u32 oretr; /* Outbound Retry Error Threshold Register */
+ u32 omgr; /* Outbound Multicast Group Register */
+ u32 omlr; /* Outbound Multicast List Register */
+ u8 res0[40];
+ u32 imr; /* Outbound Mode Register */
+ u32 isr; /* Inbound Status Register */
+ u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
+ u32 idqdpar; /* Inbound Descriptor Queue DPAR */
+ u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
+ u32 ifqepar; /* Inbound Frame Queue EPAR */
+ u32 imirir; /* Inbound Maximum Interrutp RIR */
+ u8 res1[4];
+ u32 eihqepar; /* Extended inbound message header queue EPAR */
+ u32 ihqepar; /* Inbound message header queue EPAR */
+ u8 res2[120];
+};
+
+struct rio_dbell {
+ u32 odmr; /* Outbound Doorbell Mode Register */
+ u32 odsr; /* Outbound Doorbell Status Register */
+ u8 res0[16];
+ u32 oddpr; /* Outbound Doorbell Destination Port */
+ u32 oddatr; /* Outbound Doorbell Destination AR */
+ u8 res1[12];
+ u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
+ u8 res2[48];
+ u32 idmr; /* Inbound Doorbell Mode Register */
+ u32 idsr; /* Inbound Doorbell Status Register */
+ u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
+ u32 iqdpar; /* Inbound Doorbell Queue DPAR */
+ u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
+ u32 idqepar; /* Inbound Doorbell Queue EPAR */
+ u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
+};
+
+struct rio_pw {
+ u32 pwmr; /* Port-Write Mode Register */
+ u32 pwsr; /* Port-Write Status Register */
+ u32 epwqbar; /* Extended Port-Write Queue BAR */
+ u32 pwqbar; /* Port-Write Queue Base Address Register */
+};
+#endif
+
+/* RapidIO Registers */
+struct ccsr_rio {
+ struct rio_arch arch;
+ u8 res0[144];
+ struct rio_lp_serial lp_serial;
+ u8 res1[1152];
+ struct rio_logical_err logical_err;
+ u8 res2[32];
+ struct rio_phys_err phys_err;
+ u8 res3[63808];
+ struct rio_implement impl;
+ u8 res4[2552];
+ struct rio_rev_ctrl rev;
+ struct rio_atmu atmu;
+#ifdef CONFIG_SYS_FSL_RMU
+ u8 res5[8192];
+ struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+ u8 res6[512];
+ struct rio_dbell dbell;
+ u8 res7[100];
+ struct rio_pw pw;
+#endif
+};
+#endif
/* Quick Engine Block Pin Muxing Registers */
typedef struct par_io {
@@ -2443,6 +2507,7 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
+#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
@@ -2516,6 +2581,8 @@ struct ccsr_rman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CONFIG_SYS_FSL_FM2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
+#define CONFIG_SYS_FSL_SRIO_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-22 00:20:24 +0000