5 files changed, 44 insertions, 11 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 06a20c881d3..206ee76a50b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -153,7 +153,6 @@ config TARGET_T1040RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T1040D4RDB
@@ -162,7 +161,6 @@ config TARGET_T1040D4RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T1042RDB
@@ -171,7 +169,6 @@ config TARGET_T1042RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 
 config TARGET_T1042D4RDB
 	bool "Support T1042D4RDB"
@@ -179,7 +176,6 @@ config TARGET_T1042D4RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T1042RDB_PI
@@ -188,7 +184,6 @@ config TARGET_T1042RDB_PI
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T2080QDS
@@ -806,9 +801,7 @@ config ARCH_T1040
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
-	imply CMD_SATA
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T1042
 	bool
@@ -830,9 +823,7 @@ config ARCH_T1042
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
-	imply CMD_SATA
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T2080
 	bool
@@ -882,10 +873,8 @@ config ARCH_T4160
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
-	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T4240
 	bool
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee2..296e458db4f 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,14 @@ int arch_early_init_r(void)
 {
 	return riscv_cpu_probe();
 }
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care of race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
index 45657b79096..1740ef98b6b 100644
--- a/arch/riscv/cpu/fu540/spl.c
+++ b/arch/riscv/cpu/fu540/spl.c
@@ -6,6 +6,9 @@
 
 #include <dm.h>
 #include <log.h>
+#include <asm/csr.h>
+
+#define CSR_U74_FEATURE_DISABLE	0x7c1
 
 int spl_soc_init(void)
 {
@@ -21,3 +24,15 @@ int spl_soc_init(void)
 
 	return 0;
 }
+
+void harts_early_init(void)
+{
+	/*
+	 * Feature Disable CSR
+	 *
+	 * Clear feature disable CSR to '0' to turn on all features for
+	 * each core. This operation must be in M-mode.
+	 */
+	if (CONFIG_IS_ENABLED(RISCV_MMODE))
+		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e012..308b0a97a58 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,10 @@ call_board_init_f_0:
 	mv	sp, a0
 #endif
 
+	/* Configure proprietary settings and customized CSRs of harts */
+call_harts_early_init:
+	jal	harts_early_init
+
 #ifndef CONFIG_XIP
 	/*
 	 * Pick hart to initialize global data and run U-Boot. The other harts
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 4fde923e9ad..fe26ced31dc 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -53,6 +53,13 @@
 		osd0 = "/osd";
 	};
 
+	config {
+		environment {
+			from_fdt = "yes";
+			fdt_env_path = "";
+		};
+	};
+
 	audio: audio-codec {
 		compatible = "sandbox,audio-codec";
 		#sound-dai-cells = <1>;
@@ -1526,6 +1533,13 @@
 		compatible = "sandbox,sysinfo-sandbox";
 	};
 
+	sysinfo-gpio {
+		compatible = "gpio-sysinfo";
+		gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
+		revisions = <19>, <5>;
+		names = "rev_a", "foo";
+	};
+
 	some_regmapped-bus {
 		#address-cells = <0x1>;
 		#size-cells = <0x1>;