diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/ast2500-evb.dts | 5 | ||||
| -rw-r--r-- | arch/arm/dts/ast2500.dtsi | 20 | ||||
| -rw-r--r-- | arch/arm/dts/ast2600-evb.dts | 10 | ||||
| -rw-r--r-- | arch/arm/dts/ast2600.dtsi | 40 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 16 | ||||
| -rw-r--r-- | arch/arm/include/asm/ti-common/ti-aemif.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/system.h | 14 |
7 files changed, 76 insertions, 30 deletions
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index d481eadfeb0..9a5037deca2 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -129,3 +129,8 @@ reg = <0x4d>; }; }; + +&sgpio { + status = "okay"; + ngpios = <80>; +}; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 320d2e5340a..d677705fe85 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -255,6 +255,21 @@ interrupt-controller; }; + sgpio: sgpio@1e780200 { + compatible = "aspeed,ast2500-sgpio"; + reg = <0x1e780200 0x100>; + interrupts = <40>; + clocks = <&scu ASPEED_CLK_APB>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm_default>; + status = "disabled"; + }; + timer: timer@1e782000 { /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; @@ -1445,4 +1460,9 @@ function = "WDTRST2"; groups = "WDTRST2"; }; + + pinctrl_sgpm_default: sgpm_default { + function = "SGPM"; + groups = "SGPM"; + }; }; diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index 9aac0e26f28..570ba61965a 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -266,3 +266,13 @@ bootph-all; status = "okay"; }; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; +}; + +&sgpiom1 { + status = "okay"; + ngpios = <80>; +}; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 43db80edfe5..cb8ce8b6b6f 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -501,6 +501,36 @@ ngpios = <208>; }; + sgpiom0: sgpiom@1e780500 { + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780500 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scu ASPEED_CLK_APB2>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm1_default>; + status = "disabled"; + }; + + sgpiom1: sgpiom@1e780600 { + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780600 0x100>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scu ASPEED_CLK_APB2>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm2_default>; + status = "disabled"; + }; + gpio1: gpio@1e780800 { compatible = "aspeed,ast2600-gpio"; reg = <0x1e780800 0x800>; @@ -2167,4 +2197,14 @@ function = "PCIE1RC"; groups = "PCIE1RC"; }; + + pinctrl_sgpm1_default: sgpm1_default { + function = "SGPM1"; + groups = "SGPM1"; + }; + + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; }; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9eb30c2ade8..52f6c9b934d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -665,22 +665,6 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys, void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); -#ifdef CONFIG_SYS_NONCACHED_MEMORY -/** - * noncached_init() - Initialize non-cached memory region - * - * Initialize non-cached memory area. This memory region will be typically - * located right below the malloc() area and mapped uncached in the MMU. - * - * It is called during the generic post-relocation init sequence. - * - * Return: 0 if OK - */ -int noncached_init(void); - -phys_addr_t noncached_alloc(size_t size, size_t align); -#endif /* CONFIG_SYS_NONCACHED_MEMORY */ - #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h index a77538673f6..11a7384cec9 100644 --- a/arch/arm/include/asm/ti-common/ti-aemif.h +++ b/arch/arm/include/asm/ti-common/ti-aemif.h @@ -16,6 +16,7 @@ #define AEMIF_PRESERVE -1 struct aemif_config { + void *base; unsigned mode; unsigned select_strobe; unsigned extend_wait; diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 89a2ac209fc..00699c4c11a 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -286,20 +286,6 @@ static inline void instruction_hazard_barrier(void) /* 1MB granularity */ #define MMU_SECTION_SHIFT 20 #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) - -/** - * noncached_init() - Initialize non-cached memory region - * - * Initialize non-cached memory area. This memory region will be typically - * located right below the malloc() area and be accessed from KSEG1. - * - * It is called during the generic post-relocation init sequence. - * - * Return: 0 if OK - */ -int noncached_init(void); - -phys_addr_t noncached_alloc(size_t size, size_t align); #endif /* CONFIG_SYS_NONCACHED_MEMORY */ #endif /* _ASM_SYSTEM_H */ |