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-rw-r--r--arch/m68k/Kconfig10
-rw-r--r--arch/m68k/cpu/mcf523x/interrupts.c2
-rw-r--r--arch/m68k/cpu/mcf52x2/interrupts.c12
-rw-r--r--arch/m68k/cpu/mcf52x2/start.S4
-rw-r--r--arch/m68k/cpu/mcf532x/interrupts.c2
-rw-r--r--arch/m68k/cpu/mcf5445x/interrupts.c2
-rw-r--r--arch/m68k/include/asm/immap.h48
-rw-r--r--arch/m68k/lib/time.c38
8 files changed, 92 insertions, 26 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 76233ef563f..1911563e540 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -198,7 +198,17 @@ source "board/freescale/m5373evb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
+config M68K_QEMU
+ bool "Build with workarounds for incomplete QEMU emulation"
+ default n
+ help
+ QEMU 8.x currently does not implement RAMBAR accesses and
+ DMA timers. Enable this option for U-Boot CI purposes only
+ to skip the RAMBAR accesses.
+
config MCFTMR
bool "Use DMA timer"
+ default y if !M68K_QEMU
+ default n if M68K_QEMU
endmenu
diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index b02ea29f635..09c7f9e67cc 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -22,7 +22,7 @@ int interrupt_init(void)
return 0;
}
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index e787c7605f8..c5ed0600736 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -34,7 +34,7 @@ int interrupt_init(void)
return 0;
}
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
@@ -42,7 +42,7 @@ void dtimer_intr_setup(void)
clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
}
-#endif /* CFG_MCFTMR */
+#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
@@ -63,7 +63,7 @@ int interrupt_init(void)
return 0;
}
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
@@ -72,7 +72,7 @@ void dtimer_intr_setup(void)
clrbits_be32(&intp->imrl0, 0x00000001);
clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
}
-#endif /* CFG_MCFTMR */
+#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -83,11 +83,11 @@ int interrupt_init(void)
return 0;
}
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
}
-#endif /* CFG_MCFTMR */
+#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index d48d0192eea..51d2e23df10 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -98,7 +98,7 @@ _start:
nop
move.w #0x2700,%sr
-#if defined(CONFIG_M5208)
+#if defined(CONFIG_M5208) && !defined(CONFIG_M68K_QEMU)
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
@@ -120,7 +120,7 @@ _start:
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if (defined(CONFIG_M5282) || defined(CONFIG_M5271)) && !defined(CONFIG_M68K_QEMU)
/* set MBAR address + valid flag */
move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index bbe823c0cf7..4f72fa88e58 100644
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -23,7 +23,7 @@ int interrupt_init(void)
return 0;
}
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index fb80a879c7e..400f3dee879 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -26,7 +26,7 @@ int interrupt_init(void)
return 0;
}
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
void dtimer_intr_setup(void)
{
int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 74516cc6219..aafa4f40cb3 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -16,7 +16,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -25,6 +25,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (6)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#define CFG_SYS_INTR_BASE (MMAP_INTC0)
@@ -38,7 +40,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -47,6 +49,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#define CFG_SYS_INTR_BASE (MMAP_INTC0)
@@ -63,7 +67,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
@@ -72,6 +76,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#endif /* CONFIG_M5249 */
@@ -86,7 +92,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
@@ -95,6 +101,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#endif /* CONFIG_M5253 */
@@ -105,7 +113,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -114,6 +122,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#define CFG_SYS_INTR_BASE (MMAP_INTC0)
@@ -130,7 +140,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
#define CFG_SYS_TMR_BASE (MMAP_TMR3)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
@@ -139,6 +149,8 @@
#define CFG_SYS_TMRINTR_PEND (0)
#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#endif /* CONFIG_M5272 */
@@ -152,7 +164,7 @@
#define CFG_SYS_NUM_IRQS (192)
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -161,6 +173,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (0x1E)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#endif /* CONFIG_M5275 */
@@ -174,7 +188,7 @@
#define CFG_SYS_NUM_IRQS (128)
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
@@ -183,6 +197,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#endif /* CONFIG_M5282 */
@@ -196,7 +212,7 @@
#define CFG_SYS_NUM_IRQS (64)
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
@@ -207,6 +223,8 @@
#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#endif /* CONFIG_M5307 */
@@ -217,7 +235,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -226,6 +244,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (6)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#define CFG_SYS_INTR_BASE (MMAP_INTC0)
@@ -239,7 +259,7 @@
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -248,6 +268,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (6)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#define CFG_SYS_INTR_BASE (MMAP_INTC0)
@@ -269,7 +291,7 @@
#define MMAP_DSPI MMAP_DSPI0
/* Timer */
-#ifdef CFG_MCFTMR
+#if CONFIG_IS_ENABLED(MCFTMR)
#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
@@ -278,6 +300,8 @@
#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
#define CFG_SYS_TMRINTR_PRI (6)
#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#else
+#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
#endif
#define CFG_SYS_INTR_BASE (MMAP_INTC0)
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index ca8c0396235..61db1e6c500 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -25,7 +25,7 @@ static volatile ulong timestamp = 0;
#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
-#if defined(CFG_MCFTMR)
+#if CONFIG_IS_ENABLED(MCFTMR)
#ifndef CFG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
@@ -111,8 +111,6 @@ ulong get_timer(ulong base)
return (timestamp - base);
}
-#endif /* CFG_MCFTMR */
-
/*
* This function is derived from PowerPC code (read timebase as long long).
* On M68K it just returns the timer value.
@@ -121,6 +119,40 @@ unsigned long long get_ticks(void)
{
return get_timer(0);
}
+#else
+static u64 timer64 __section(".data");
+static u16 timer16 __section(".data");
+
+uint64_t __weak get_ticks(void)
+{
+ volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
+ u16 val = ~timerp->pcntr;
+
+ if (timer16 > val)
+ timer64 += 0xffff - timer16 + val;
+ else
+ timer64 += val - timer16;
+
+ timer16 = val;
+
+ return timer64;
+}
+
+/* PIT timer */
+int timer_init(void)
+{
+ volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
+
+ timer16 = 0;
+ timer64 = 0;
+
+ /* Set up PIT as timebase clock */
+ timerp->pmr = 0xffff;
+ timerp->pcsr = PIT_PCSR_EN | PIT_PCSR_OVW;
+
+ return 0;
+}
+#endif /* CONFIG_MCFTMR */
unsigned long usec2ticks(unsigned long usec)
{
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-18 16:44:08 +0000