diff options
Diffstat (limited to 'arch')
1140 files changed, 15025 insertions, 27822 deletions
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index e35a26f1eb1..fd9b7fb5f8d 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H +#include <asm/u-boot.h> + #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 593950449f2..269b4dbdd15 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -7,7 +7,7 @@ #include <clock_legacy.h> #include <init.h> #include <malloc.h> -#include <vsprintf.h> +#include <stdio.h> #include <asm/arcregs.h> #include <asm/cache.h> #include <asm/global_data.h> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 38fc757c1f0..db692b2d215 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1235,6 +1235,18 @@ config ARCH_VERSAL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG +config ARCH_VERSAL2 + bool "Support AMD Versal Gen 2 Platform" + select ARM64 + select CLK + select DM + select DM_MMC if MMC + select DM_SERIAL + select OF_CONTROL + imply BOARD_LATE_INIT + imply ENV_VARS_UBOOT_RUNTIME_CONFIG + imply ZYNQMP_FIRMWARE + config ARCH_VERSAL_NET bool "Support Xilinx Versal NET Platform" select ARM64 @@ -1272,7 +1284,7 @@ config ARCH_ZYNQ select OF_CONTROL select MTD select SPI - select SPL_BOARD_INIT if SPL + select SPL_SOC_INIT if SPL select SPL_CLK if SPL select SPL_DM if SPL select SPL_DM_SPI if SPL @@ -1315,7 +1327,7 @@ config ARCH_ZYNQMP imply FIRMWARE select GICV2 select OF_CONTROL - select SPL_BOARD_INIT if SPL + select SPL_SOC_INIT if SPL select SPL_CLK if SPL select SPL_DM if SPL select SPL_DM_SPI if SPI && SPL_DM @@ -1853,6 +1865,9 @@ config TARGET_LS1046AFRWY development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config ARCH_SC5XX + bool "Analog Devices SC5XX-processor family" + config TARGET_SL28 bool "Support sl28" select ARCH_LS1028A @@ -2286,6 +2301,8 @@ source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s5pc1xx/Kconfig" +source "arch/arm/mach-sc5xx/Kconfig" + source "arch/arm/mach-snapdragon/Kconfig" source "arch/arm/mach-socfpga/Kconfig" @@ -2312,6 +2329,8 @@ source "arch/arm/mach-zynqmp/Kconfig" source "arch/arm/mach-versal/Kconfig" +source "arch/arm/mach-versal2/Kconfig" + source "arch/arm/mach-versal-net/Kconfig" source "arch/arm/mach-zynqmp-r5/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a4266a3e366..dbeedbe544b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -78,6 +78,7 @@ machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_RENESAS) += renesas machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx +machine-$(CONFIG_ARCH_SC5XX) += sc5xx machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STM32) += stm32 @@ -89,6 +90,7 @@ machine-$(CONFIG_ARCH_OCTEONTX) += octeontx machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSAL) += versal +machine-$(CONFIG_ARCH_VERSAL2) += versal2 machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 1e16b89d006..01d2e1a125d 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -14,7 +14,6 @@ * CPU specific code */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 9997e8fc339..87ca303e31b 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -6,7 +6,6 @@ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> */ -#include <common.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index a3d4f147962..fc56baccfcd 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -4,7 +4,6 @@ * Sascha Hauer, Pengutronix */ -#include <common.h> #include <div64.h> #include <init.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index a913860491c..b41ca68ae55 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -4,7 +4,6 @@ * Sascha Hauer, Pengutronix */ -#include <common.h> #include <init.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds index f83988fd7e6..b7af29183a9 100644 --- a/arch/arm/cpu/arm1136/u-boot-spl.lds +++ b/arch/arm/cpu/arm1136/u-boot-spl.lds @@ -33,11 +33,7 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } + _end = .; .bss : { diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index f0fc58deadb..e3d0216158f 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -9,7 +9,7 @@ * Alex Zuepke <azu@sysgo.de> */ -#include <common.h> +#include <linux/types.h> #if defined(CONFIG_ARCH_TEGRA) static ulong timestamp; diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c index 305713e7861..61e18230573 100644 --- a/arch/arm/cpu/arm920t/cpu.c +++ b/arch/arm/cpu/arm920t/cpu.c @@ -12,7 +12,6 @@ * CPU specific code */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index cba4a1f0358..e792e8e795e 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -8,7 +8,6 @@ */ #include <asm-offsets.h> -#include <common.h> #include <config.h> /* diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 95963d2665f..5b87a3af91b 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -6,7 +6,6 @@ #include <cpu_func.h> #include <asm/cache.h> #include <linux/types.h> -#include <common.h> #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 2ce413a7f86..07ab04b7b08 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -12,7 +12,6 @@ * CPU specific code */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 4e1cf3a1e32..58f6cf80cae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -9,7 +9,6 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> #include <linux/errno.h> #include <asm/io.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 381264b8a18..851b4deb080 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -6,7 +6,6 @@ * <armlinux@phytec.de> */ -#include <common.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 4f3cb63c56d..7b2bb09551b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -9,7 +9,6 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <hang.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 249f8de8fbe..76a69d7f958 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include <common.h> #include <config.h> #include <init.h> #include <log.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c index 2cfbd780953..b2d3b2b13ef 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include <common.h> #include <config.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a94803ee93d..c3136dd8976 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include <common.h> #include <config.h> #include <init.h> #include <log.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 77bca7e331a..8b65c094a8a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -6,7 +6,6 @@ * on behalf of DENX Software Engineering GmbH */ -#include <common.h> #include <config.h> #include <hang.h> #include <log.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 61982e38a1d..a6eb053cadb 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -20,7 +20,6 @@ #include <asm-offsets.h> #include <config.h> -#include <common.h> #include <system-constants.h> /* diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 3dff3d768d1..cbd3b5d9958 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -9,7 +9,6 @@ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 7e20448f810..7c6309246f8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -49,11 +49,7 @@ SECTIONS __bss_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .dynsym _image_binary_end : { *(.dynsym) } diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index c882bd39eab..5d6c9f0861e 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -16,7 +16,6 @@ #include <asm-offsets.h> #include <config.h> -#include <common.h> #include <linux/linkage.h> /* diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index 334bb542743..efd232d3423 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -12,7 +12,6 @@ * CPU specific code */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 17bd53dae84..f25a8674dea 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -4,7 +4,7 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c index 39217c5b2bf..7f73f893458 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c @@ -9,7 +9,6 @@ * */ -#include <common.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c index 1b3f36aebe1..55dcc2fd78c 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index d7edefee231..b769c451105 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -9,7 +9,6 @@ * */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <linux/delay.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c index 209ceca9a06..5f7cc4a102d 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <linux/delay.h> #include <linux/errno.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c index f2ba354c24f..f3ff29bebe8 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c index f604aec62fa..87918059408 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index 8f6260e7857..b258fea45c8 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -9,7 +9,6 @@ * */ -#include <common.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c index 1b3f36aebe1..55dcc2fd78c 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index 26b673a5405..3f2e021a307 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -9,7 +9,6 @@ * */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <linux/delay.h> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c index 209ceca9a06..5f7cc4a102d 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <linux/delay.h> #include <linux/errno.h> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c index f2ba354c24f..f3ff29bebe8 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c index f604aec62fa..87918059408 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <linux/errno.h> #include <asm/arch/sysmap.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c index 1491e5c88b2..87e4337be4e 100644 --- a/arch/arm/cpu/armv7/bcm281xx/reset.c +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -3,7 +3,6 @@ * Copyright 2013 Broadcom Corporation. */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> #include <asm/arch/sysmap.h> diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c index 63992fd8701..617c8d68a2a 100644 --- a/arch/arm/cpu/armv7/bcmcygnus/reset.c +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c index a3137752e88..c3be33124c6 100644 --- a/arch/arm/cpu/armv7/bcmnsp/reset.c +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 19ff4323528..d11420d2fdd 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -7,7 +7,6 @@ #include <cpu_func.h> #include <asm/cache.h> #include <linux/types.h> -#include <common.h> #include <asm/armv7.h> #include <asm/utils.h> diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index 0ac4e7ba8c8..b2c52db68dc 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -7,7 +7,6 @@ * CP15 specific code */ -#include <common.h> #include <command.h> #include <asm/system.h> #include <asm/cache.h> diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 6259ffa5108..aa981faef00 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -14,7 +14,6 @@ * CPU specific code */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/cpu/armv7/exception_level.c b/arch/arm/cpu/armv7/exception_level.c index f6d25bb682c..7baade61b07 100644 --- a/arch/arm/cpu/armv7/exception_level.c +++ b/arch/arm/cpu/armv7/exception_level.c @@ -8,7 +8,6 @@ * secure mode before booting an operating system. */ -#include <common.h> #include <bootm.h> #include <cpu_func.h> #include <log.h> diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c index 8c3a323f065..b345671b0a6 100644 --- a/arch/arm/cpu/armv7/iproc-common/armpll.c +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <asm/io.h> #include <asm/iproc-common/armpll.h> #include <asm/iproc-common/sysmap.h> diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c index 896d2f95694..eca7e8b512b 100644 --- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <cpu_func.h> #include <asm/cache.h> diff --git a/arch/arm/cpu/armv7/iproc-common/timer.c b/arch/arm/cpu/armv7/iproc-common/timer.c index a4255a44c00..b60d90f7e6a 100644 --- a/arch/arm/cpu/armv7/iproc-common/timer.c +++ b/arch/arm/cpu/armv7/iproc-common/timer.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <div64.h> #include <init.h> #include <time.h> diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 4e1fe281201..e885a85ce65 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index c455969609f..74a2dcbc116 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -4,7 +4,6 @@ * Copyright 2021 NXP */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <net.h> diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 1c3d24bcad9..34eea22eb92 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <net.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c index e31a4fb6c31..664eae532d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/io.h> #include "fsl_epu.h" diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index f74d819ea1e..c1eadb34523 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_ls102xa.h> #include <linux/errno.h> diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c index 8c030be8b36..3032e266c5d 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <linux/kernel.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_ls102xa.h> diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 84d4ea3a8f4..7ff59edd452 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <log.h> #include <asm/arch/clock.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index a1949686235..374de92d026 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> #include <spl.h> u32 spl_boot_device(void) diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index c6126b10c35..6f32ced5aec 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c index 1d31c63e5fd..2d83e4c721d 100644 --- a/arch/arm/cpu/armv7/mpu_v7r.c +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <asm/armv7.h> diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index fb2920950d4..4331dde7643 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -3,7 +3,6 @@ * Copyright (C) 2009 Samsung Electronics * Minkyu Kang <mk7.kang@samsung.com> */ -#include <common.h> #include <display_options.h> #include <fdtdec.h> #include <init.h> diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 5068327d3c5..986b585b70e 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -5,7 +5,7 @@ * Donghwa Lee <dh09.lee@samsung.com> */ -#include <common.h> +#include <config.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/pwm.h> diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c index 0fc170936ae..c0035fb18eb 100644 --- a/arch/arm/cpu/armv7/s5p-common/sromc.c +++ b/arch/arm/cpu/armv7/s5p-common/sromc.c @@ -4,7 +4,7 @@ * Naveen Krishna Ch <ch.naveen@samsung.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/sromc.h> diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 9d981cce145..12994ecc843 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -6,7 +6,6 @@ * Minkyu Kang <mk7.kang@samsung.com> */ -#include <common.h> #include <div64.h> #include <init.h> #include <time.h> diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 8febfe52766..27ffb450378 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -4,7 +4,6 @@ * Hyunseok, Jung <hsjung@nexell.co.kr> */ -#include <common.h> #include <command.h> #include <asm/system.h> #include <asm/cache.h> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 5cb8cfa6cf3..4c30f3294b7 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -7,7 +7,6 @@ * which was based on code by Carl van Schaik <carl@ok-labs.com>. */ #include <config.h> -#include <common.h> #include <asm/cache.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c index 28ff6a1b7c2..bc25719c9c4 100644 --- a/arch/arm/cpu/armv7/sunxi/sram.c +++ b/arch/arm/cpu/armv7/sunxi/sram.c @@ -9,7 +9,6 @@ * SRAM init for older sunxi SoCs. */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c index 7e29636972d..f0eda1ca98d 100644 --- a/arch/arm/cpu/armv7/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c @@ -7,7 +7,6 @@ * Syed Mohammed Khasim <khasim@ti.com> */ -#include <common.h> #include <asm/io.h> /************************************************************ diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index c23ddc12b45..e61ad7b96e9 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -3,7 +3,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include <common.h> #include <clock_legacy.h> #include <command.h> #include <cpu_func.h> diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c index a9c1a8fcebc..7bae0b5574a 100644 --- a/arch/arm/cpu/armv7/vf610/timer.c +++ b/arch/arm/cpu/armv7/vf610/timer.c @@ -3,7 +3,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index c0422485ba4..5dc7ed5e270 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -15,7 +15,6 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include <common.h> #include <errno.h> #include <log.h> #include <stdio_dev.h> diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 5ffeca13d91..811499367d4 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -8,7 +8,6 @@ * needed to enable ARMv7 virtualization for current hypervisors */ -#include <common.h> #include <cpu_func.h> #include <asm/armv7.h> #include <asm/cache.h> diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index d1aecf6a85c..b6d08b7aad7 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -4,7 +4,6 @@ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. */ -#include <common.h> #include <cpu_func.h> #include <errno.h> #include <log.h> diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 65427b5312b..b4440d3f3f8 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -7,7 +7,6 @@ * Kamil Lulko, <kamil.lulko@gmail.com> */ -#include <common.h> #include <cpu_func.h> #include <irq_func.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index c30af4ff7a2..d8fa4f0c707 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -21,7 +21,7 @@ * using CFG_SYS_HZ_CLOCK. */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9f0fb369f77..199335cd604 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -191,6 +191,14 @@ config ARMV8_EA_EL3_FIRST Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. +config ARMV8_UDELAY_EVENT_STREAM + bool "Use the event stream for udelay" + default y if ARCH_VEXPRESS64 + help + Use the event stream provided by the AArch64 architectural timer for + delays. This is more efficient than the default polling + implementation. + menuconfig ARMV8_CRYPTO bool "ARM64 Accelerated Cryptographic Algorithms" diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 57d06f0575d..c3f8dac648b 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -7,7 +7,6 @@ * Alexander Graf <agraf@suse.de> */ -#include <common.h> #include <cpu_func.h> #include <hang.h> #include <log.h> @@ -397,6 +396,251 @@ static int count_ranges(void) return count; } +#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) +#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) + +enum walker_state { + WALKER_STATE_START = 0, + WALKER_STATE_TABLE, + WALKER_STATE_REGION, /* block or page, depending on level */ +}; + + +/** + * __pagetable_walk() - Walk through the pagetable and call cb() for each memory region + * + * This is a software implementation of the ARMv8-A MMU translation table walk. As per + * section D5.4 of the ARMv8-A Architecture Reference Manual. It recursively walks the + * 4 or 3 levels of the page table and calls the callback function for each discrete + * region of memory (that being the discovery of a new table, a collection of blocks + * with the same attributes, or of pages with the same attributes). + * + * U-Boot picks the smallest number of virtual address (VA) bits that it can based on the + * memory map configured by the board. If this is less than 39 then the MMU will only use + * 3 levels of translation instead of 3 - skipping level 0. + * + * Each level has 512 entries of 64-bits each. Each entry includes attribute bits and + * an address. When the attribute bits indicate a table, the address is the physical + * address of the table, so we can recursively call _pagetable_walk() on it (after calling + * @cb). If instead they indicate a block or page, we record the start address and attributes + * and continue walking until we find a region with different attributes, or the end of the + * table, in either case we call @cb with the start and end address of the region. + * + * This approach can be used to fully emulate the MMU's translation table walk, as per + * Figure D5-25 of the ARMv8-A Architecture Reference Manual. + * + * @addr: The address of the table to walk + * @tcr: The TCR register value + * @level: The current level of the table + * @cb: The callback function to call for each region + * @priv: Private data to pass to the callback function + */ +static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, void *priv) +{ + u64 *table = (u64 *)addr; + u64 attrs, last_attrs = 0, last_addr = 0, entry_start = 0; + int i; + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + static enum walker_state state[4] = { 0 }; + static bool exit; + + if (!level) { + exit = false; + if (va_bits < 39) + level = 1; + } + + state[level] = WALKER_STATE_START; + + /* Walk through the table entries */ + for (i = 0; i < MAX_PTE_ENTRIES; i++) { + u64 pte = table[i]; + u64 _addr = pte & GENMASK_ULL(va_bits, PAGE_SHIFT); + + if (exit) + return; + + if (pte_type(&pte) == PTE_TYPE_FAULT) + continue; + + attrs = pte & ALL_ATTRS; + /* If we're currently inside a block or set of pages */ + if (state[level] > WALKER_STATE_START && state[level] != WALKER_STATE_TABLE) { + /* + * Continue walking if this entry has the same attributes as the last and + * is one page/block away -- it's a contiguous region. + */ + if (attrs == last_attrs && _addr == last_addr + (1 << level2shift(level))) { + last_attrs = attrs; + last_addr = _addr; + continue; + } else { + /* We either hit a table or a new region */ + exit = cb(entry_start, last_addr + (1 << level2shift(level)), + va_bits, level, priv); + if (exit) + return; + state[level] = WALKER_STATE_START; + } + } + last_attrs = attrs; + last_addr = _addr; + + if (PTE_IS_TABLE(pte, level)) { + /* After the end of the table might be corrupted data */ + if (!_addr || (pte & 0xfff) > 0x3ff) + return; + state[level] = WALKER_STATE_TABLE; + /* Signify the start of a table */ + exit = cb(pte, 0, va_bits, level, priv); + if (exit) + return; + + /* Go down a level */ + __pagetable_walk(_addr, tcr, level + 1, cb, priv); + state[level] = WALKER_STATE_START; + } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) { + /* We foud a block or page, start walking */ + entry_start = pte; + state[level] = WALKER_STATE_REGION; + } + } + + if (state[level] > WALKER_STATE_START) + exit = cb(entry_start, last_addr + (1 << level2shift(level)), va_bits, level, priv); +} + +static void pretty_print_pte_type(u64 pte) +{ + switch (pte_type(&pte)) { + case PTE_TYPE_FAULT: + printf(" %-5s", "Fault"); + break; + case PTE_TYPE_BLOCK: + printf(" %-5s", "Block"); + break; + case PTE_TYPE_PAGE: + printf(" %-5s", "Pages"); + break; + default: + printf(" %-5s", "Unk"); + } +} + +static void pretty_print_table_attrs(u64 pte) +{ + int ap = (pte & PTE_TABLE_AP) >> 61; + + printf(" | %2s %10s", + (ap & 2) ? "RO" : "", + (ap & 1) ? "!EL0" : ""); + printf(" | %3s %2s %2s", + (pte & PTE_TABLE_PXN) ? "PXN" : "", + (pte & PTE_TABLE_XN) ? "XN" : "", + (pte & PTE_TABLE_NS) ? "NS" : ""); +} + +static void pretty_print_block_attrs(u64 pte) +{ + u64 attrs = pte & PMD_ATTRINDX_MASK; + + switch (attrs) { + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): + printf(" | %-13s", "Device-nGnRnE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE): + printf(" | %-13s", "Device-nGnRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_DEVICE_GRE): + printf(" | %-13s", "Device-GRE"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL_NC): + printf(" | %-13s", "Normal-NC"); + break; + case PTE_BLOCK_MEMTYPE(MT_NORMAL): + printf(" | %-13s", "Normal"); + break; + default: + printf(" | %-13s", "Unknown"); + } +} + +static void pretty_print_block_memtype(u64 pte) +{ + u64 share = pte & (3 << 8); + + switch (share) { + case PTE_BLOCK_NON_SHARE: + printf(" | %-16s", "Non-shareable"); + break; + case PTE_BLOCK_OUTER_SHARE: + printf(" | %-16s", "Outer-shareable"); + break; + case PTE_BLOCK_INNER_SHARE: + printf(" | %-16s", "Inner-shareable"); + break; + default: + printf(" | %-16s", "Unknown"); + } +} + +static void print_pte(u64 pte, int level) +{ + if (PTE_IS_TABLE(pte, level)) { + printf(" %-5s", "Table"); + pretty_print_table_attrs(pte); + } else { + pretty_print_pte_type(pte); + pretty_print_block_attrs(pte); + pretty_print_block_memtype(pte); + } + printf("\n"); +} + +/** + * pagetable_print_entry() - Callback function to print a single pagetable region + * + * This is the default callback used by @dump_pagetable(). It does some basic pretty + * printing (see example in the U-Boot arm64 documentation). It can be replaced by + * a custom callback function if more detailed information is needed. + * + * @start_attrs: The start address and attributes of the region (or table address) + * @end: The end address of the region (or 0 if it's a table) + * @va_bits: The number of bits used for the virtual address + * @level: The level of the region + * @priv: Private data for the callback (unused) + */ +static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int level, void *priv) +{ + u64 _addr = start_attrs & GENMASK_ULL(va_bits, PAGE_SHIFT); + int indent = va_bits < 39 ? level - 1 : level; + + printf("%*s", indent * 2, ""); + if (PTE_IS_TABLE(start_attrs, level)) + printf("[%#011llx]%14s", _addr, ""); + else + printf("[%#011llx - %#011llx]", _addr, end); + + printf("%*s | ", (3 - level) * 2, ""); + print_pte(start_attrs, level); + + return false; +} + +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv) +{ + __pagetable_walk(ttbr, tcr, 0, cb, priv); +} + +void dump_pagetable(u64 ttbr, u64 tcr) +{ + u64 va_bits = 64 - (tcr & (BIT(6) - 1)); + + printf("Walking pagetable at %p, va_bits: %lld. Using %d levels\n", (void *)ttbr, + va_bits, va_bits < 39 ? 3 : 4); + walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL); +} + /* Returns the estimated required size of all page tables */ __weak u64 get_page_table_size(void) { diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 9bfe3815e51..97667e607a8 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -3,7 +3,6 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include <common.h> #include <asm/cache.h> #include <asm/psci.h> #include <asm/system.h> diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index 3c7f36ad8d8..d568efa427a 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -10,7 +10,6 @@ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c index b11936548fb..85c78f55789 100644 --- a/arch/arm/cpu/armv8/exception_level.c +++ b/arch/arm/cpu/armv8/exception_level.c @@ -8,7 +8,6 @@ * level before booting an operating system. */ -#include <common.h> #include <bootm.h> #include <cpu_func.h> #include <log.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 12d31184ad9..d2dbfdd08a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -4,7 +4,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <cpu_func.h> #include <env.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 22ce6992165..ca6be3626fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -4,7 +4,7 @@ * Copyright 2020-2021 NXP */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <efi_loader.h> #include <log.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index b1bb29bcaf5..78961d8089e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -3,11 +3,12 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <log.h> #include <asm/io.h> #include <linux/delay.h> #include <linux/errno.h> +#include <linux/string.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 4455eb1726d..9a24d4b3031 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <cpu_func.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index fbd5fd7d433..b768790437f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -4,7 +4,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <env.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 137778dc136..452246e0e67 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -6,7 +6,7 @@ * Derived from arch/power/cpu/mpc85xx/speed.c */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <cpu_func.h> #include <asm/global_data.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index c22e73253c3..04ffefafbf7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -3,7 +3,7 @@ * Copyright 2018 NXP */ -#include <common.h> +#include <config.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c index 8d7beca7db3..c0e5455507a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_lsch2.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index 86a49b152e4..d48baa63816 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -3,9 +3,9 @@ * Copyright 2019 NXP */ -#include <common.h> #include <fdt_support.h> #include <log.h> +#include <asm/arch/stream_id_lsch3.h> #include <asm/arch-fsl-layerscape/immap_lsch3.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index 80d2910f679..1b4eab3613e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -3,7 +3,8 @@ * Copyright 2019 NXP */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/arch/fsl_serdes.h> struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index e3c3fc6bfb5..ec80e42055d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -3,11 +3,12 @@ * Copyright 2018 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch-fsl-layerscape/immap_lsch2.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> #include <fsl_sec.h> +#include <asm/arch/stream_id_lsch3.h> #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c index 6c5e52ebaa6..1911ca1a175 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_lsch2.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index 333d7e2fa21..a73dd316f8d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -3,10 +3,11 @@ * Copyright 2018 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch-fsl-layerscape/immap_lsch2.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <asm/arch/stream_id_lsch3.h> #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index 9347e516bf6..26ca4ca10f3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_lsch2.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 23743ae10cf..3a076ca04f6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -3,10 +3,11 @@ * Copyright 2019 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch-fsl-layerscape/immap_lsch3.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <asm/arch/stream_id_lsch3.h> struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index fe667f06c39..154b727392e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2017-2019 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 7997422840f..5088c8ebb7f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c index e6403b79526..c320e835c99 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -3,10 +3,11 @@ * Copyright 2019 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch-fsl-layerscape/immap_lsch3.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <asm/arch/stream_id_lsch3.h> struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c index 3a0ed1fa550..df9329df77e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -3,10 +3,11 @@ * Copyright 2019 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch-fsl-layerscape/immap_lsch3.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> #include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <asm/arch/stream_id_lsch3.h> struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c index 5941d90e036..43f0e8c87ba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2018, 2020 NXP */ -#include <common.h> +#include <config.h> #include <asm/arch/fsl_serdes.h> struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index ce0c46ad0d4..db913208b9e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <cpu_func.h> #include <image.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 4c61d28c20f..d85a630f8a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -4,7 +4,7 @@ * Copyright 2019-2021 NXP */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <cpu_func.h> #include <env.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 232adfa843a..a739ff2da58 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <cpu_func.h> #include <debug_uart.h> diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 8f83372cbca..1de7ec596fc 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -4,7 +4,6 @@ * David Feng <fenghua@phytium.com.cn> */ -#include <common.h> #include <bootstage.h> #include <command.h> #include <time.h> @@ -115,3 +114,30 @@ ulong timer_get_boot_us(void) return val / get_tbclk(); } + +#if CONFIG_IS_ENABLED(ARMV8_UDELAY_EVENT_STREAM) +void __udelay(unsigned long usec) +{ + u64 target = get_ticks() + usec_to_tick(usec); + + /* At EL2 or above, use the event stream to avoid polling CNTPCT_EL0 so often */ + if (current_el() >= 2) { + u32 cnthctl_val; + const u8 event_period = 0x7; + + asm volatile("mrs %0, cnthctl_el2" : "=r" (cnthctl_val)); + asm volatile("msr cnthctl_el2, %0" : : "r" + (cnthctl_val | CNTHCTL_EL2_EVNT_EN | CNTHCTL_EL2_EVNT_I(event_period))); + + while (get_ticks() + (1ULL << event_period) <= target) + wfe(); + + /* Reset the event stream */ + asm volatile("msr cnthctl_el2, %0" : : "r" (cnthctl_val)); + } + + /* Fall back to polling CNTPCT_EL0 */ + while (get_ticks() <= target) + ; +} +#endif diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c b/arch/arm/cpu/armv8/hisilicon/pinmux.c index e14057c0a47..d7a5a792610 100644 --- a/arch/arm/cpu/armv8/hisilicon/pinmux.c +++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c @@ -4,7 +4,6 @@ * Peter Griffin <peter.griffin@linaro.org> */ -#include <common.h> #include <fdtdec.h> #include <log.h> #include <asm/gpio.h> diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index c0e8726346f..44372cbe4a1 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -3,7 +3,7 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <errno.h> #include <fdt_support.h> diff --git a/arch/arm/cpu/armv8/sha1_ce_glue.c b/arch/arm/cpu/armv8/sha1_ce_glue.c index 780b119a90b..c88b4dc66e1 100644 --- a/arch/arm/cpu/armv8/sha1_ce_glue.c +++ b/arch/arm/cpu/armv8/sha1_ce_glue.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org> */ -#include <common.h> #include <u-boot/sha1.h> extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, diff --git a/arch/arm/cpu/armv8/sha256_ce_glue.c b/arch/arm/cpu/armv8/sha256_ce_glue.c index 67dd796c122..d5d2b4f4ac7 100644 --- a/arch/arm/cpu/armv8/sha256_ce_glue.c +++ b/arch/arm/cpu/armv8/sha256_ce_glue.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org> */ -#include <common.h> #include <u-boot/sha256.h> extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src, diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c index 42a0962fdcd..485294b88d0 100644 --- a/arch/arm/cpu/armv8/spin_table.c +++ b/arch/arm/cpu/armv8/spin_table.c @@ -4,7 +4,6 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ -#include <common.h> #include <linux/libfdt.h> #include <asm/spin_table.h> diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 8f1231c86eb..259b49ff364 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include <common.h> #include <spl.h> char __data_save_start[0] __section(".__data_save_start"); diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index ef8af67e11c..215cedd69a8 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -53,12 +53,7 @@ SECTIONS . = ALIGN(8); __image_copy_end = .; - - .end : { - . = ALIGN(8); - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : { diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 9ed62395a9c..eee463a1b1c 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -53,12 +53,8 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - _image_binary_end = .; + _end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 707b19795f0..2f50087f57a 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -166,11 +166,7 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; /* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8fb6a8a1f17..06c234afbeb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -52,14 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_PX30) += \ - px30-evb.dtb \ - px30-firefly.dtb \ - px30-engicam-px30-core-ctouch2.dtb \ - px30-engicam-px30-core-ctouch2-of10.dtb \ - px30-engicam-px30-core-edimm2.2.dtb \ - rk3326-odroid-go2.dtb - dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb @@ -341,6 +333,8 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini-qspi-x2-single.dtb \ versal-mini-qspi-x2-stacked.dtb \ xilinx-versal-virt.dtb +dtb-$(CONFIG_ARCH_VERSAL2) += \ + amd-versal2-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ versal-net-mini-emmc.dtb \ @@ -870,7 +864,6 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ - imx6ulz-bsh-smm-m2.dtb \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ @@ -922,10 +915,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ - imx8mm-phyboard-polis-rdk.dtb \ - imx8mm-phygate-tauri-l.dtb \ - imx8mn-bsh-smm-s2.dtb \ - imx8mn-bsh-smm-s2pro.dtb \ imx8mq-cm.dtb \ imx8mn-var-som-symphony.dtb \ imx8mq-mnt-reform2.dtb \ @@ -941,7 +930,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ - imx8mp-phyboard-pollux-rdk.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb @@ -954,9 +942,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ -dtb-$(CONFIG_RCAR_GEN4) += \ - r8a779h0-gray-hawk.dtb - dtb-$(CONFIG_TARGET_RZG2L) += \ r9a07g044l2-smarc.dts @@ -1146,6 +1131,7 @@ dtb-$(CONFIG_ASPEED_AST2600) += \ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb dtb-$(CONFIG_STM32MP13X) += \ + stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb dtb-$(CONFIG_STM32MP15X) += \ @@ -1185,36 +1171,30 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \ k3-am654-icssg2.dtbo -dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ - k3-j721e-r5-common-proc-board.dtb \ - k3-j7200-common-proc-board.dtb \ +dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ k3-j7200-r5-common-proc-board.dtb \ - k3-j721e-sk.dtb \ k3-j721e-r5-sk.dtb \ k3-j721e-beagleboneai64.dtb \ k3-j721e-r5-beagleboneai64.dtb -dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ - k3-am68-sk-r5-base-board.dtb\ - k3-j721s2-common-proc-board.dtb\ +dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ k3-j721s2-r5-common-proc-board.dtb dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \ k3-j784s4-r5-evm.dtb +dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb + dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \ k3-am642-r5-sk.dtb \ k3-am642-r5-phycore-som-2gb.dtb -dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ - k3-am625-r5-sk.dtb \ - k3-am625-beagleplay.dtb \ +dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \ k3-am625-r5-beagleplay.dtb \ k3-am625-verdin-r5.dtb \ k3-am625-r5-phycore-som-2gb.dtb -dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \ - k3-am62a7-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb diff --git a/arch/arm/dts/amd-versal2-virt.dts b/arch/arm/dts/amd-versal2-virt.dts new file mode 100644 index 00000000000..3b6cbbac582 --- /dev/null +++ b/arch/arm/dts/amd-versal2-virt.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Empty device tree for amd-versal2-virt board + * + * Copyright (C) 2024, Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +/ { +}; diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts index 26b0f1b3cea..3076fb9f344 100644 --- a/arch/arm/dts/corstone1000-fvp.dts +++ b/arch/arm/dts/corstone1000-fvp.dts @@ -49,3 +49,28 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; + diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi index 1e0ec075e4c..5d9d95b21cb 100644 --- a/arch/arm/dts/corstone1000.dtsi +++ b/arch/arm/dts/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/dts/imx6ulz-bsh-smm-m2.dts deleted file mode 100644 index 59bcfc9a6b1..00000000000 --- a/arch/arm/dts/imx6ulz-bsh-smm-m2.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include "imx6ulz.dtsi" - -/ { - model = "BSH SMM M2"; - compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz"; - - chosen { - stdout-path = &uart4; - }; - - usdhc2_pwrseq: usdhc2-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy1 { - fsl,tx-d-cal = <106>; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - bus-width = <4>; - no-1-8-v; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - cap-sdio-irq; - mmc-pwrseq = <&usdhc2_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio1>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&wdog1 { - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 - MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b099 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b099 - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x79 /* BT_REG_ON */ - MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x100b1 /* BT_DEV_WAKE out */ - MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BT_HOST_WAKE in */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 - MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x79 /* WL_REG_ON */ - MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x100b1 /* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */ - MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b1 /* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */ - MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */ - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts b/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts deleted file mode 100644 index 03e7679217b..00000000000 --- a/arch/arm/dts/imx8mm-phyboard-polis-rdk.dts +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet <t.remmet@phytec.de> - */ - -/dts-v1/; - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mm-phycore-som.dtsi" - -/ { - model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; - compatible = "phytec,imx8mm-phyboard-polis-rdk", - "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - bt_osc_32k: bt-lp-clock { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "bt_osc_32k"; - #clock-cells = <0>; - }; - - can_osc_40m: can-clock { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "can_osc_40m"; - #clock-cells = <0>; - }; - - fan { - compatible = "gpio-fan"; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 13000 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fan>; - #cooling-cells = <2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - }; - - led-1 { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - }; - - led-2 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_CPU; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - usdhc1_pwrseq: pwr-seq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <60>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - }; - - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "CAN_EN"; - startup-delay-us = <20>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; - regulator-name = "usb_otg1_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <20000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; - - reg_vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VCC_3V3"; - }; -}; - -/* SPI - CAN MCP251XFD */ -&ecspi1 { - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp251xfd"; - clocks = <&can_osc_40m>; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - reg = <0>; - spi-max-frequency = <20000000>; - xceiver-supply = <®_can_en>; - }; -}; - -&gpio1 { - gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", - "", "", "", "RESET_ETHPHY", - "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", - "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", - "", "", "BT_REG_ON", "WL_REG_ON", - "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", - "X_SD2_CD_B", "", "", "", - "", "", "", "SD2_RESET_B"; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "FAN", "miniPCIe_nPERST", "", "", - "COEX1", "COEX2"; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "ECSPI1_SS0"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - -/* PCIe */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie_phy { - clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - status = "okay"; -}; - -&rv3028 { - trickle-resistor-ohms = <3000>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* UART - RS232/RS485 */ -&uart1 { - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -/* UART - Sterling-LWB Bluetooth */ -&uart2 { - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - fsl,dte-mode; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_bt>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&bt_osc_32k>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - interrupt-names = "host-wakeup"; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_EDGE_BOTH>; - max-speed = <2000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt>; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - vddio-supply = <®_vcc_3v3>; - }; -}; - -/* UART - console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - over-current-active-low; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; -}; - -/* SDIO - Sterling-LWB Wifi */ -&usdhc1 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - mmc-pwrseq = <&usdhc1_pwrseq>; - non-removable; - no-1-8-v; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_nvcc_sd2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt: btgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 - >; - }; - - pinctrl_can_en: can-engrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 - >; - }; - - pinctrl_can_int: can-intgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 - >; - }; - - pinctrl_fan: fan0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_leds: leds1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 - >; - }; - - pinctrl_uart2_bt: uart2btgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 - MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 - MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 - MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 - >; - }; - - pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phycore-som.dtsi b/arch/arm/dts/imx8mm-phycore-som.dtsi deleted file mode 100644 index 92616bc4f71..00000000000 --- a/arch/arm/dts/imx8mm-phycore-som.dtsi +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet <t.remmet@phytec.de> - */ - -#include "imx8mm.dtsi" -#include <dt-bindings/net/ti-dp83867.h> - -/ { - model = "PHYTEC phyCORE-i.MX8MM"; - compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_vdd_3v3_s: regulator-vdd-3v3-s { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VDD_3V3_S"; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25000000 { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -/* Ethernet */ -&fec1 { - fsl,magic-packet; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - enet-phy-lane-no-swap; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - reg = <0>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - }; - }; -}; - -/* SPI Flash */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - som_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&gpio1 { - gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", - "", "", "", "RESET_ETHPHY", - "", "", "nENABLE_FLATLINK"; -}; - -/* I2C1 */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default","gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@8 { - compatible = "nxp,pf8121a"; - reg = <0x08>; - - regulators { - reg_nvcc_sd1: ldo1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "NVCC_SD1 (LDO1)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_nvcc_sd2: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "NVCC_SD2 (LDO2)"; - vselect-en; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vcc_enet: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <1500000>; - regulator-name = "VCC_ENET_2V5 (LDO3)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdda_1v8: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1500000>; - regulator-name = "VDDA_1V8 (LDO4)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <1500000>; - regulator-suspend-max-microvolt = <1500000>; - }; - }; - - reg_soc_vdda_phy: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-min-microvolt = <400000>; - regulator-suspend-max-microvolt = <400000>; - }; - }; - - reg_vdd_gpu_dram: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <1000000>; - regulator-name = "VDD_GPU_DRAM (BUCK2)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1000000>; - regulator-suspend-min-microvolt = <1000000>; - }; - }; - - reg_vdd_gpu: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_VPU (BUCK3)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_mipi: buck4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <900000>; - regulator-name = "VDD_MIPI_0P9 (BUCK4)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_arm: buck5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <400000>; - regulator-name = "VDD_ARM (BUCK5)"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - reg_vdd_1v8: buck6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "VDD_1V8 (BUCK6)"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-max-microvolt = <1800000>; - regulator-suspend-min-microvolt = <1800000>; - }; - }; - - reg_nvcc_dram: buck7 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; - }; - - reg_vsnvs: vsnvs { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; - }; - }; - }; - - sn65dsi83: bridge@2d { - compatible = "ti,sn65dsi83"; - enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sn65dsi83>; - reg = <0x2d>; - status = "disabled"; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - vcc-supply = <®_vdd_3v3_s>; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - reg = <0x52>; - }; -}; - -/* EMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - keep-power-in-suspend; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - non-removable; - status = "okay"; -}; - -/* Watchdog */ -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - - pinctrl_sn65dsi83: sn65dsi83grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-phygate-tauri-l.dts b/arch/arm/dts/imx8mm-phygate-tauri-l.dts deleted file mode 100644 index 968f475b9a9..00000000000 --- a/arch/arm/dts/imx8mm-phygate-tauri-l.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - */ - -/dts-v1/; - -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include "imx8mm-phycore-som.dtsi" - -/ { - model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; - compatible = "phytec,imx8mm-phygate-tauri-l", - "phytec,imx8mm-phycore-som", "fsl,imx8mm"; - - chosen { - stdout-path = &uart3; - }; - - can_osc_40m: clock-can { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "can_osc_40m"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - key { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - label = "KEY-A"; - linux,code = <KEY_A>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-1 { - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - led-2 { - color = <LED_COLOR_ID_YELLOW>; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - }; - - usdhc1_pwrseq: pwr-seq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <60>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - }; - - reg_usb_hub_vbus: regulator-hub-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhubpwr>; - regulator-name = "usb_hub_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1pwr>; - regulator-name = "usb_otg1_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <20000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; -}; - -&ecspi1 { - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, - <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio5 2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* CAN MCP251XFD */ - can0: can@0 { - compatible = "microchip,mcp251xfd"; - reg = <0>; - clocks = <&can_osc_40m>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_int>; - spi-max-frequency = <10000000>; - }; - - tpm: tpm@1 { - compatible = "tcg,tpm_tis-spi"; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm>; - reg = <1>; - spi-max-frequency = <38000000>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - temp_sense0: temperature-sensor@49 { - compatible = "ti,tmp102"; - reg = <0x49>; - interrupt-parent = <&gpio4>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tempsense>; - #thermal-sensor-cells = <1>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* PCIe */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_PHY>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <100000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -/* RTC */ -&rv3028 { - trickle-resistor-ohms = <3000>; -}; - -&uart1 { - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* UART2 - RS232 */ -&uart2 { - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* UART - console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - over-current-active-low; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - vbus-supply = <®_usb_hub_vbus>; - status = "okay"; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_nvcc_sd2>; - status = "okay"; -}; - -&iomuxc { - pinctrl_can_int: can-intgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - >; - }; - - pinctrl_ecspi1_cs: ecspi1csgrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 - >; - }; - - pinctrl_gpiokeys: keygrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 - >; - }; - - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 - >; - }; - - pinctrl_leds: leds1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* COEX2 */ - MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 - /* COEX1 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_tempsense: tempsensegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 - >; - }; - - pinctrl_tpm: tpmgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usbhubpwr: usbhubpwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 - >; - }; - - pinctrl_usbotg1pwr: usbotg1pwrgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 6ab8f66256e..c02e11def5f 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -54,126 +54,151 @@ }; #endif - nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <1>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ + + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; }; }; +#ifdef CONFIG_IMX_HAB }; - fit { - description = "Configuration to load ATF before U-Boot"; -#ifndef CONFIG_IMX_HAB - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; -#endif - fit,fdt-list = "of-list"; - #address-cells = <1>; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; #ifdef CONFIG_FSPI_CONF_HEADER offset = <0x58C00>; #else offset = <0x57c00>; #endif - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = <CONFIG_TEXT_BASE>; - type = "standalone"; + args; /* Needed by mkimage etype superclass */ +#endif - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; +#ifndef CONFIG_IMX_HAB + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; +#endif + fit,fdt-list = "of-list"; + #address-cells = <1>; +#ifdef CONFIG_FSPI_CONF_HEADER + offset = <0x58C00>; +#else + offset = <0x57c00>; +#endif + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_TEXT_BASE>; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; }; - }; #ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x920000>; - load = <0x920000>; - type = "firmware"; - - atf-blob { - filename = "bl31.bin"; - type = "atf-bl31"; + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x920000>; + load = <0x920000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; }; - }; #endif - binman_fip: fip { - arch = "arm64"; - compression = "none"; - description = "Trusted Firmware FIP"; - load = <0x40310000>; - type = "firmware"; - }; + binman_fip: fip { + arch = "arm64"; + compression = "none"; + description = "Trusted Firmware FIP"; + load = <0x40310000>; + type = "firmware"; + }; - @fdt-SEQ { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; }; }; - }; - configurations { - default = "@config-DEFAULT-SEQ"; + configurations { + default = "@config-DEFAULT-SEQ"; - @config-SEQ { - description = "NAME"; - fdt = "fdt-SEQ"; - firmware = "uboot"; + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; + loadables = "atf"; #endif + }; }; }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 90183aff8bc..183de46f66a 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -35,12 +35,8 @@ bootph-pre-ram; }; -&binman { - section { - fit { - offset = <0x5fc00>; - }; - }; +&binman_imx_fit { + offset = <0x5fc00>; }; &gpio1 { diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi deleted file mode 100644 index c11895d9d58..00000000000 --- a/arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Collabora Ltd. - * Copyright 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include "imx8mn.dtsi" - -/ { - chosen { - stdout-path = &uart4; - }; - - fec_supply: fec-supply-en { - compatible = "regulator-fixed"; - vin-supply = <&buck4_reg>; - regulator-name = "tja1101_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usdhc2_pwrseq: usdhc2-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwrseq>; - reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - phy-supply = <&fec_supply>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - reset-assert-us = <20>; - reset-deassert-us = <2000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - bd71847: pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - /* PMIC_BUCK1 - VDD_SOC */ - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - /* PMIC_BUCK2 - VDD_ARM */ - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */ - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - /* PMIC_BUCK6 - VDD_3V3 */ - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - /* PMIC_BUCK7 - VDD_1V8 */ - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - /* PMIC_BUCK8 - NVCC_DRAM */ - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - /* PMIC_LDO1 - NVCC_SNVS_1V8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - /* PMIC_LDO2 - VDD_SNVS_0V8 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - /* PMIC_LDO3 - VDDA_1V8 */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - /* PMIC_LDO4 - VDD_MIPI_0V9 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* PMIC_LDO6 - VDD_MIPI_1V2 */ - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MN_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bluetooth>; - shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - }; -}; - -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "peripheral"; - disable-over-current; - status = "okay"; -}; - -&usdhc2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - mmc-pwrseq = <&usdhc2_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: bcrmf@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_bluetooth: bluetoothgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */ - MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */ - MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */ - >; - }; - - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 - MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090 - MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090 - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016 - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016 - MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090 - MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016 - MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */ - MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */ - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */ - MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2 - MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2 - >; - }; - - pinctrl_pmic: pmicirq { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040 - MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040 - MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040 - MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6 - >; - }; - - pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */ - MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */ - MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */ - MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */ - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2.dts b/arch/arm/dts/imx8mn-bsh-smm-s2.dts deleted file mode 100644 index 33f98582eac..00000000000 --- a/arch/arm/dts/imx8mn-bsh-smm-s2.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Collabora Ltd. - * Copyright 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include "imx8mn-bsh-smm-s2-common.dtsi" - -/ { - model = "BSH SMM S2"; - compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn"; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x10000000>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 - MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 - MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 - MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 - MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 - MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 - MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 - MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 - MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 - MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 - MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 - MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 - MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 - MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 - MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts b/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts deleted file mode 100644 index fbbb3367037..00000000000 --- a/arch/arm/dts/imx8mn-bsh-smm-s2pro.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Collabora Ltd. - * Copyright 2021 BSH Hausgeraete GmbH - */ - -/dts-v1/; - -#include "imx8mn-bsh-smm-s2-common.dtsi" -#include <dt-bindings/sound/tlv320aic31xx.h> - -/ { - model = "BSH SMM S2 PRO"; - compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn"; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x20000000>; - }; - - sound-tlv320aic31xx { - compatible = "fsl,imx-audio-tlv320aic31xx"; - model = "tlv320aic31xx-hifi"; - audio-cpu = <&sai3>; - audio-codec = <&tlv320dac3101>; - audio-asrc = <&easrc>; - audio-routing = - "Ext Spk", "SPL", - "Ext Spk", "SPR"; - mclk-id = <PLL_CLKIN_BCLK>; - }; - - vdd_input: vdd_input { - compatible = "regulator-fixed"; - regulator-name = "vdd_input"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&easrc { - fsl,asrc-rate = <48000>; - fsl,asrc-format = <10>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - tlv320dac3101: audio-codec@18 { - compatible = "ti,tlv320dac3101"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dac_rst>; - reg = <0x18>; - #sound-dai-cells = <0>; - HPVDD-supply = <&buck4_reg>; - SPRVDD-supply = <&vdd_input>; - SPLVDD-supply = <&vdd_input>; - AVDD-supply = <&buck4_reg>; - IOVDD-supply = <&buck4_reg>; - DVDD-supply = <&buck5_reg>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - ai31xx-micbias-vg = <MICBIAS_AVDDV>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - }; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_dac_rst: dacrstgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */ - >; - }; - - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 - MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0 - MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0 - MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0 - MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0 - MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0 - MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4 - MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4 - MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4 - MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4 - MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4 - MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6 - MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6 - MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6 - MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6 - MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6 - MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index ba9967dbe4a..732191f5205 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -103,147 +103,172 @@ }; #endif - nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <2>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <2>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ + + section { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-imem-fw { + ddr-1d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_imem_1d_201810.bin"; + filename = "ddr4_imem_1d_201810.bin"; #else - filename = "ddr3_imem_1d.bin"; + filename = "ddr3_imem_1d.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; - ddr-1d-dmem-fw { + ddr-1d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_dmem_1d_201810.bin"; + filename = "ddr4_dmem_1d_201810.bin"; #else - filename = "ddr3_dmem_1d.bin"; + filename = "ddr3_dmem_1d.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; #if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) - ddr-2d-imem-fw { + ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem.bin"; #else - filename = "ddr4_imem_2d_201810.bin"; + filename = "ddr4_imem_2d_201810.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-dmem-fw { + ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem.bin"; #else - filename = "ddr4_dmem_2d_201810.bin"; + filename = "ddr4_dmem_2d_201810.bin"; #endif - type = "blob-ext"; - align-end = <4>; - }; + type = "blob-ext"; + align-end = <4>; + }; #endif + }; }; + +#ifdef CONFIG_IMX_HAB }; - fit { - description = "Configuration to load ATF before U-Boot"; -#ifndef CONFIG_IMX_HAB - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; -#endif - fit,fdt-list = "of-list"; - #address-cells = <1>; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; #ifdef CONFIG_FSPI_CONF_HEADER offset = <0x59000>; #else offset = <0x58000>; #endif + args; /* Needed by mkimage etype superclass */ +#endif - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = <CONFIG_TEXT_BASE>; - type = "standalone"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; +#ifndef CONFIG_IMX_HAB + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; +#endif + fit,fdt-list = "of-list"; + #address-cells = <1>; +#ifdef CONFIG_FSPI_CONF_HEADER + offset = <0x59000>; +#else + offset = <0x58000>; +#endif - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_TEXT_BASE>; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; }; - }; #ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x960000>; - load = <0x960000>; - type = "firmware"; - - atf-blob { - filename = "bl31.bin"; - type = "atf-bl31"; + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x960000>; + load = <0x960000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; }; - }; #endif - binman_fip: fip { - arch = "arm64"; - compression = "none"; - description = "Trusted Firmware FIP"; - load = <0x40310000>; - type = "firmware"; - }; + binman_fip: fip { + arch = "arm64"; + compression = "none"; + description = "Trusted Firmware FIP"; + load = <0x40310000>; + type = "firmware"; + }; - @fdt-SEQ { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; }; }; - }; - configurations { - default = "@config-DEFAULT-SEQ"; + configurations { + default = "@config-DEFAULT-SEQ"; - @config-SEQ { - description = "NAME"; - fdt = "fdt-SEQ"; - firmware = "uboot"; + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; + loadables = "atf"; #endif + }; }; }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index cb37e28f28f..c065fb82994 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -135,73 +135,69 @@ bootph-pre-ram; }; -&binman { - section { - fit { - images { - fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { - description = "imx8mp-dhcom-som-overlay-eth1xfast"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast { - description = "imx8mp-dhcom-som-overlay-eth2xfast"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast { - description = "imx8mp-dhcom-pdk-overlay-eth2xfast"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-som-overlay-rev100 { - description = "imx8mp-dhcom-som-overlay-rev100"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-som-overlay-rev100.dtbo"; - }; - }; - - fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 { - description = "imx8mp-dhcom-pdk3-overlay-rev100"; - type = "flat_dt"; - compression = "none"; - - blob-ext { - filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo"; - }; - }; +&binman_imx_fit { + images { + fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { + description = "imx8mp-dhcom-som-overlay-eth1xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo"; }; + }; + + fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast { + description = "imx8mp-dhcom-som-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast { + description = "imx8mp-dhcom-pdk-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; + }; + }; - configurations { - default = "@config-DEFAULT-SEQ"; - - @config-SEQ { - fdt = "fdt-1", - "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", - "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", - "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", - "fdt-dto-imx8mp-dhcom-som-overlay-rev100", - "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100"; - }; + fdt-dto-imx8mp-dhcom-som-overlay-rev100 { + description = "imx8mp-dhcom-som-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-rev100.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 { + description = "imx8mp-dhcom-pdk3-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo"; }; }; }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + fdt = "fdt-1", + "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-rev100", + "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100"; + }; + }; }; diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts deleted file mode 100644 index c8640cac3ed..00000000000 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet <t.remmet@phytec.de> - */ - -/dts-v1/; - -#include <dt-bindings/leds/leds-pca9532.h> -#include <dt-bindings/pwm/pwm.h> -#include "imx8mp-phycore-som.dtsi" - -/ { - model = "PHYTEC phyBOARD-Pollux i.MX8MP"; - compatible = "phytec,imx8mp-phyboard-pollux-rdk", - "phytec,imx8mp-phycore-som", "fsl,imx8mp"; - - chosen { - stdout-path = &uart1; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can1-stby"; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb1_host_vbus"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - enet-phy-lane-no-swap; - }; - }; -}; - -/* CAN FD */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - leds@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led-1 { - type = <PCA9532_TYPE_LED>; - }; - - led-2 { - type = <PCA9532_TYPE_LED>; - }; - - led-3 { - type = <PCA9532_TYPE_LED>; - }; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* debug console */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 Host mode Type-A */ -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB */ -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* RS232/RS485 */ -&uart2 { - assigned-clocks = <&clk IMX8MP_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -/* SD-Card */ -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "X_PMIC_WDOG_B", "", - "PMIC_SD_VSEL", "", "", "", "", "", - "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "X_SD2_CD_B", "", "", "", - "", "", "", "SD2_RESET_B"; -}; - -&gpio3 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "nCAN1_EN", "nCAN2_EN"; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "", "", "", "", - "", "", "", "", "", "", - "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - >; - }; - - pinctrl_flexcan1_reg: flexcan1reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 - >; - }; - - pinctrl_usb1_vbus: usb1vbusgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 - MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 - >; - }; - - pinctrl_usdhc2_pins: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi b/arch/arm/dts/imx8mp-phycore-som.dtsi deleted file mode 100644 index 79b290a002c..00000000000 --- a/arch/arm/dts/imx8mp-phycore-som.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet <t.remmet@phytec.de> - */ - -#include <dt-bindings/net/ti-dp83867.h> -#include "imx8mp.dtsi" - -/ { - model = "PHYTEC phyCORE-i.MX8MP"; - compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -/* ethernet 1 */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - ti,min-output-impedance; - enet-phy-lane-no-swap; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - som_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic: pmic@25 { - reg = <0x25>; - compatible = "nxp,pca9450c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-compatible = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-compatible = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-compatible = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-compatible = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-compatible = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-compatible = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-compatible = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-compatible = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-compatible = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5: LDO5 { - regulator-compatible = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - reg = <0x52>; - trickle-resistor-ohms = <3000>; - }; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index aff5dcf615d..21eff6d6ad4 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -135,21 +135,17 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; -&binman { - section { - fit { - images { - fip { - description = "Trusted Firmware FIP"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x40310000>; - - fip_blob: blob-ext{ - filename = "fip.bin"; - }; - }; +&binman_imx_fit { + images { + fip { + description = "Trusted Firmware FIP"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x40310000>; + + fip_blob: blob-ext{ + filename = "fip.bin"; }; }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index c4c1a177102..f2655a4d0c8 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -86,110 +86,130 @@ section { pad-byte = <0x00>; - nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <2>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - align-size = <4>; - align = <4>; - - u-boot-spl { - align-end = <4>; - }; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <2>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ + + section { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem_202006.bin"; - type = "blob-ext"; - align-end = <4>; - }; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; - type = "blob-ext"; - align-end = <4>; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; + type = "blob-ext"; + align-end = <4>; + }; }; }; +#ifdef CONFIG_IMX_HAB }; - fit { - description = "Configuration to load ATF before U-Boot"; -#ifndef CONFIG_IMX_HAB - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; -#endif - fit,fdt-list = "of-list"; - #address-cells = <1>; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; offset = <0x58000>; + args; /* Needed by mkimage etype superclass */ +#endif - images { - uboot { - description = "U-Boot (64-bit)"; - type = "standalone"; - arch = "arm64"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - - uboot_blob: blob-ext { - filename = "u-boot-nodtb.bin"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; +#ifndef CONFIG_IMX_HAB + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; +#endif + fit,fdt-list = "of-list"; + #address-cells = <1>; + offset = <0x58000>; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; }; - }; #ifndef CONFIG_ARMV8_PSCI - atf { - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x970000>; - entry = <0x970000>; - - atf_blob: atf-blob { - filename = "bl31.bin"; - type = "atf-bl31"; + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x970000>; + entry = <0x970000>; + + atf_blob: atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; }; - }; #endif - @fdt-SEQ { - description = "NAME"; - type = "flat_dt"; - compression = "none"; + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + compression = "none"; - blob-ext { - filename = "u-boot.dtb"; + blob-ext { + filename = "u-boot.dtb"; + }; }; }; - }; - configurations { - default = "@config-DEFAULT-SEQ"; + configurations { + default = "@config-DEFAULT-SEQ"; - @config-SEQ { - description = "NAME"; - fdt = "fdt-SEQ"; - firmware = "uboot"; + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; + loadables = "atf"; #endif + }; }; }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi index b9e3db7de93..98f71c73c98 100644 --- a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi @@ -4,9 +4,3 @@ */ #include "imx8mp-venice-u-boot.dtsi" - -&eqos { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi index 240fbc1b568..a90794d8108 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -243,3 +243,8 @@ &wdog1 { bootph-pre-ram; }; + +/* gpio-usb-con not supported yet in U-Boot so make this a host for now */ +&usb_dwc3_0 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi index 1a4568dac65..98da015a444 100644 --- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi @@ -10,14 +10,10 @@ bootph-pre-ram; }; -&binman { +&binman_imx_spl { section { - nxp-imx8mimage { - section { - signed-hdmi-imx8m { - filename = "signed_dp_imx8m.bin"; - }; - }; + signed-hdmi-imx8m { + filename = "signed_dp_imx8m.bin"; }; }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 48dbe94f0c4..e1cd6f8996d 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -38,116 +38,136 @@ section { pad-byte = <0x00>; - nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <1>; +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@0 { + filename = "u-boot-spl-mkimage.signed.bin"; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + nxp,unlock; args; /* Needed by mkimage etype superclass */ +#endif - section { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + binman_imx_spl: nxp-imx8mimage { + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ + + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - signed-hdmi-imx8m { - filename = "signed_hdmi_imx8m.bin"; - type = "blob-ext"; + signed-hdmi-imx8m { + filename = "signed_hdmi_imx8m.bin"; + type = "blob-ext"; + }; }; }; +#ifdef CONFIG_IMX_HAB }; - fit { - description = "Configuration to load ATF before U-Boot"; + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; + offset = <0x58000>; + args; /* Needed by mkimage etype superclass */ +#endif + + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; #ifndef CONFIG_IMX_HAB - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif - #address-cells = <1>; - - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = <CONFIG_TEXT_BASE>; - type = "standalone"; - - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_TEXT_BASE>; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; }; - }; #ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x910000>; - load = <0x910000>; - type = "firmware"; - - atf-blob { - filename = "bl31.bin"; - type = "blob-ext"; + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x910000>; + load = <0x910000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "blob-ext"; + }; }; - }; #endif - fdt { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + fdt { + compression = "none"; + description = "NAME"; + type = "flat_dt"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; }; }; - }; - configurations { - default = "conf"; + configurations { + default = "conf"; - conf { - description = "NAME"; - fdt = "fdt"; - firmware = "uboot"; + conf { + description = "NAME"; + fdt = "fdt"; + firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI - loadables = "atf"; + loadables = "atf"; #endif + }; }; }; +#ifdef CONFIG_IMX_HAB }; +#endif }; }; diff --git a/arch/arm/dts/k3-am62-lp-sk-binman.dtsi b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi new file mode 100644 index 00000000000..18341d0d3f2 --- /dev/null +++ b/arch/arm/dts/k3-am62-lp-sk-binman.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" +#include "k3-am625-sk-binman.dtsi" + +#ifdef CONFIG_TARGET_AM625_A53_EVM + +#define SPL_AM62_LP_SK_DTB "spl/dts/ti/k3-am62-lp-sk.dtb" + +&spl_am625_sk_dtb { + filename = SPL_AM62_LP_SK_DTB; +}; + +&spl_am625_sk_dtb_unsigned { + filename = SPL_AM62_LP_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi new file mode 100644 index 00000000000..cbcc7f3bb45 --- /dev/null +++ b/arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62x LP SK dts file for SPLs + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62-lp-sk-binman.dtsi" + +/ { + chosen { + tick-timer = &main_timer0; + }; +}; + +&main_timer0 { + clock-frequency = <25000000>; +}; diff --git a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi new file mode 100644 index 00000000000..c255ae6530f --- /dev/null +++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi @@ -0,0 +1,2190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07 + * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 800MHz + * Density (per channel): 16Gb + * Write DBI: Enable + * Number of Ranks: 1 + */ + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000640 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0000040C +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000081C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x0000081C +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x05000804 +#define DDRSS_CTL_45_DATA 0x00000700 +#define DDRSS_CTL_46_DATA 0x09090004 +#define DDRSS_CTL_47_DATA 0x00000203 +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000190F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900190F +#define DDRSS_CTL_54_DATA 0x000A0A09 +#define DDRSS_CTL_55_DATA 0x040006DB +#define DDRSS_CTL_56_DATA 0x09092004 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 +#define DDRSS_CTL_63_DATA 0x04050002 +#define DDRSS_CTL_64_DATA 0x100F100F +#define DDRSS_CTL_65_DATA 0x01010008 +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x00130803 +#define DDRSS_CTL_73_DATA 0x000000BB +#define DDRSS_CTL_74_DATA 0x00000130 +#define DDRSS_CTL_75_DATA 0x00000C28 +#define DDRSS_CTL_76_DATA 0x00000130 +#define DDRSS_CTL_77_DATA 0x00000C28 +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x0000000A +#define DDRSS_CTL_80_DATA 0x00000010 +#define DDRSS_CTL_81_DATA 0x00000098 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000098 +#define DDRSS_CTL_84_DATA 0x0000017E +#define DDRSS_CTL_85_DATA 0x03004000 +#define DDRSS_CTL_86_DATA 0x00001201 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x05121208 +#define DDRSS_CTL_91_DATA 0x05030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 +#define DDRSS_CTL_94_DATA 0x02010201 +#define DDRSS_CTL_95_DATA 0x00001401 +#define DDRSS_CTL_96_DATA 0x01360014 +#define DDRSS_CTL_97_DATA 0x01360136 +#define DDRSS_CTL_98_DATA 0x00000136 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x05010303 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00030A00 +#define DDRSS_CTL_127_DATA 0x00030A00 +#define DDRSS_CTL_128_DATA 0x00030A00 +#define DDRSS_CTL_129_DATA 0x00030A00 +#define DDRSS_CTL_130_DATA 0x00030A00 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x00005518 +#define DDRSS_CTL_133_DATA 0x00030A00 +#define DDRSS_CTL_134_DATA 0x00030A00 +#define DDRSS_CTL_135_DATA 0x00030A00 +#define DDRSS_CTL_136_DATA 0x00030A00 +#define DDRSS_CTL_137_DATA 0x00030A00 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x00005518 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x03050000 +#define DDRSS_CTL_157_DATA 0x03050305 +#define DDRSS_CTL_158_DATA 0x00000000 +#define DDRSS_CTL_159_DATA 0x08010000 +#define DDRSS_CTL_160_DATA 0x000E0808 +#define DDRSS_CTL_161_DATA 0x01000000 +#define DDRSS_CTL_162_DATA 0x0E080808 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x08080801 +#define DDRSS_CTL_165_DATA 0x0000080E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000002 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x0005000A +#define DDRSS_CTL_193_DATA 0x0404000D +#define DDRSS_CTL_194_DATA 0x0000000D +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000004 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000024 +#define DDRSS_CTL_209_DATA 0x00000012 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000024 +#define DDRSS_CTL_212_DATA 0x00000012 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000004 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000024 +#define DDRSS_CTL_218_DATA 0x00000012 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000024 +#define DDRSS_CTL_221_DATA 0x00000012 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x46004646 +#define DDRSS_CTL_255_DATA 0x00002746 +#define DDRSS_CTL_256_DATA 0x00000027 +#define DDRSS_CTL_257_DATA 0x00000027 +#define DDRSS_CTL_258_DATA 0x00000027 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x0000000F +#define DDRSS_CTL_264_DATA 0x0000000F +#define DDRSS_CTL_265_DATA 0x0000000F +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00001000 +#define DDRSS_CTL_271_DATA 0x00000015 +#define DDRSS_CTL_272_DATA 0x00000015 +#define DDRSS_CTL_273_DATA 0x00000010 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000020 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000100 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00020000 +#define DDRSS_CTL_306_DATA 0x00400100 +#define DDRSS_CTL_307_DATA 0x00080032 +#define DDRSS_CTL_308_DATA 0x01000200 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 +#define DDRSS_CTL_311_DATA 0x00400100 +#define DDRSS_CTL_312_DATA 0x00180320 +#define DDRSS_CTL_313_DATA 0x00030000 +#define DDRSS_CTL_314_DATA 0x00280028 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000000 +#define DDRSS_CTL_318_DATA 0x3FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x00FFFF00 +#define DDRSS_CTL_322_DATA 0x0B000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x01000100 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x00000000 +#define DDRSS_CTL_331_DATA 0x01030303 +#define DDRSS_CTL_332_DATA 0x00000001 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x01000101 +#define DDRSS_CTL_372_DATA 0x01010001 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x01050503 +#define DDRSS_CTL_375_DATA 0x05020201 +#define DDRSS_CTL_376_DATA 0x08080C0C +#define DDRSS_CTL_377_DATA 0x00080308 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 +#define DDRSS_CTL_381_DATA 0x01000000 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 +#define DDRSS_CTL_384_DATA 0x1B000004 +#define DDRSS_CTL_385_DATA 0x00000176 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x00000693 +#define DDRSS_CTL_391_DATA 0x00000E9C +#define DDRSS_CTL_392_DATA 0x03050202 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001850 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00006D68 +#define DDRSS_CTL_400_DATA 0x0000F320 +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001850 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00006D68 +#define DDRSS_CTL_409_DATA 0x0000F320 +#define DDRSS_CTL_410_DATA 0x070D0402 +#define DDRSS_CTL_411_DATA 0x00000405 +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x10100600 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00010000 +#define DDRSS_PI_24_DATA 0x280A0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x01010102 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000015 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x03000000 +#define DDRSS_PI_55_DATA 0x00000000 +#define DDRSS_PI_56_DATA 0x00001701 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x01000210 +#define DDRSS_PI_63_DATA 0x05000404 +#define DDRSS_PI_64_DATA 0x00010001 +#define DDRSS_PI_65_DATA 0x0001000E +#define DDRSS_PI_66_DATA 0x01010100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x0000FFFF +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x08000100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x0000000A +#define DDRSS_PI_137_DATA 0x000186A0 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 +#define DDRSS_PI_167_DATA 0x00000034 +#define DDRSS_PI_168_DATA 0x00000042 +#define DDRSS_PI_169_DATA 0x00020042 +#define DDRSS_PI_170_DATA 0x02000200 +#define DDRSS_PI_171_DATA 0x00000004 +#define DDRSS_PI_172_DATA 0x0000080C +#define DDRSS_PI_173_DATA 0x00081C00 +#define DDRSS_PI_174_DATA 0x001C0000 +#define DDRSS_PI_175_DATA 0x00000013 +#define DDRSS_PI_176_DATA 0x000000BB +#define DDRSS_PI_177_DATA 0x00000130 +#define DDRSS_PI_178_DATA 0x00000C28 +#define DDRSS_PI_179_DATA 0x00000130 +#define DDRSS_PI_180_DATA 0x04000C28 +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001501 +#define DDRSS_PI_183_DATA 0x001D001D +#define DDRSS_PI_184_DATA 0x01000100 +#define DDRSS_PI_185_DATA 0x00000100 +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05050503 +#define DDRSS_PI_188_DATA 0x01010C0C +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x000C0C0A +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x04000000 +#define DDRSS_PI_194_DATA 0x04020808 +#define DDRSS_PI_195_DATA 0x04040204 +#define DDRSS_PI_196_DATA 0x00090031 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 +#define DDRSS_PI_199_DATA 0x01010101 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 +#define DDRSS_PI_203_DATA 0x000E000E +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 +#define DDRSS_PI_207_DATA 0x32103200 +#define DDRSS_PI_208_DATA 0x01013210 +#define DDRSS_PI_209_DATA 0x0A070601 +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D +#define DDRSS_PI_212_DATA 0x000C000D +#define DDRSS_PI_213_DATA 0x00001000 +#define DDRSS_PI_214_DATA 0x00000C00 +#define DDRSS_PI_215_DATA 0x00001000 +#define DDRSS_PI_216_DATA 0x00000C00 +#define DDRSS_PI_217_DATA 0x02001000 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 +#define DDRSS_PI_221_DATA 0x00001900 +#define DDRSS_PI_222_DATA 0x32000056 +#define DDRSS_PI_223_DATA 0x06000101 +#define DDRSS_PI_224_DATA 0x001D0204 +#define DDRSS_PI_225_DATA 0x32120058 +#define DDRSS_PI_226_DATA 0x05000101 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 +#define DDRSS_PI_229_DATA 0x05000101 +#define DDRSS_PI_230_DATA 0x00000408 +#define DDRSS_PI_231_DATA 0x05030900 +#define DDRSS_PI_232_DATA 0x00040900 +#define DDRSS_PI_233_DATA 0x0000062B +#define DDRSS_PI_234_DATA 0x20010004 +#define DDRSS_PI_235_DATA 0x0A0A0A03 +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C +#define DDRSS_PI_246_DATA 0x00000000 +#define DDRSS_PI_247_DATA 0x00000176 +#define DDRSS_PI_248_DATA 0x00000E9C +#define DDRSS_PI_249_DATA 0x00001850 +#define DDRSS_PI_250_DATA 0x0000F320 +#define DDRSS_PI_251_DATA 0x00001850 +#define DDRSS_PI_252_DATA 0x0000F320 +#define DDRSS_PI_253_DATA 0x01360014 +#define DDRSS_PI_254_DATA 0x03030136 +#define DDRSS_PI_255_DATA 0x00000003 +#define DDRSS_PI_256_DATA 0x00000000 +#define DDRSS_PI_257_DATA 0x05030503 +#define DDRSS_PI_258_DATA 0x00000503 +#define DDRSS_PI_259_DATA 0x00002710 +#define DDRSS_PI_260_DATA 0x000186A0 +#define DDRSS_PI_261_DATA 0x00000005 +#define DDRSS_PI_262_DATA 0x00000064 +#define DDRSS_PI_263_DATA 0x00000014 +#define DDRSS_PI_264_DATA 0x00027100 +#define DDRSS_PI_265_DATA 0x000186A0 +#define DDRSS_PI_266_DATA 0x00000005 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000136 +#define DDRSS_PI_269_DATA 0x00027100 +#define DDRSS_PI_270_DATA 0x000186A0 +#define DDRSS_PI_271_DATA 0x00000005 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000136 +#define DDRSS_PI_274_DATA 0x00320040 +#define DDRSS_PI_275_DATA 0x00010008 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 +#define DDRSS_PI_281_DATA 0x03040404 +#define DDRSS_PI_282_DATA 0x00000303 +#define DDRSS_PI_283_DATA 0x02020101 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000000 +#define DDRSS_PI_286_DATA 0x55000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x3C00005A +#define DDRSS_PI_289_DATA 0x00005500 +#define DDRSS_PI_290_DATA 0x00005A00 +#define DDRSS_PI_291_DATA 0x0D100F3C +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000000 +#define DDRSS_PI_298_DATA 0x00000004 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000031 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00100F27 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x00000024 +#define DDRSS_PI_307_DATA 0x00000012 +#define DDRSS_PI_308_DATA 0x000000B1 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00000000 +#define DDRSS_PI_311_DATA 0x46000000 +#define DDRSS_PI_312_DATA 0x00150F27 +#define DDRSS_PI_313_DATA 0x00000000 +#define DDRSS_PI_314_DATA 0x00000024 +#define DDRSS_PI_315_DATA 0x00000012 +#define DDRSS_PI_316_DATA 0x000000B1 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00000000 +#define DDRSS_PI_319_DATA 0x46000000 +#define DDRSS_PI_320_DATA 0x00150F27 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000004 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000031 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00100F27 +#define DDRSS_PI_329_DATA 0x00000000 +#define DDRSS_PI_330_DATA 0x00000024 +#define DDRSS_PI_331_DATA 0x00000012 +#define DDRSS_PI_332_DATA 0x000000B1 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x46000000 +#define DDRSS_PI_336_DATA 0x00150F27 +#define DDRSS_PI_337_DATA 0x00000000 +#define DDRSS_PI_338_DATA 0x00000024 +#define DDRSS_PI_339_DATA 0x00000012 +#define DDRSS_PI_340_DATA 0x000000B1 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00000000 +#define DDRSS_PI_343_DATA 0x46000000 +#define DDRSS_PI_344_DATA 0x00150F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01000000 +#define DDRSS_PHY_6_DATA 0x03000400 +#define DDRSS_PHY_7_DATA 0x00000001 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01010000 +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00001 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660601 +#define DDRSS_PHY_16_DATA 0x00000003 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00071020 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000001 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CC0B01 +#define DDRSS_PHY_75_DATA 0x1003CC0B +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x00100303 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00021000 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51516041 +#define DDRSS_PHY_89_DATA 0x31C06000 +#define DDRSS_PHY_90_DATA 0x07AB0340 +#define DDRSS_PHY_91_DATA 0x0000C0C0 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C1D +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x76543210 +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01800080 +#define DDRSS_PHY_120_DATA 0x01000000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x0000F0F0 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01000000 +#define DDRSS_PHY_262_DATA 0x03000400 +#define DDRSS_PHY_263_DATA 0x00000001 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01010000 +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00001 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660601 +#define DDRSS_PHY_272_DATA 0x00000003 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00071020 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CC0B01 +#define DDRSS_PHY_331_DATA 0x1003CC0B +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x00100303 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00021000 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51516041 +#define DDRSS_PHY_345_DATA 0x31C06000 +#define DDRSS_PHY_346_DATA 0x07AB0340 +#define DDRSS_PHY_347_DATA 0x0000C0C0 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C1D +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x76543210 +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01800080 +#define DDRSS_PHY_376_DATA 0x01000000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x0000F0F0 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000200 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00400000 +#define DDRSS_PHY_524_DATA 0x00000080 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x03000000 +#define DDRSS_PHY_527_DATA 0x00200000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x0000002A +#define DDRSS_PHY_533_DATA 0x00000015 +#define DDRSS_PHY_534_DATA 0x00000015 +#define DDRSS_PHY_535_DATA 0x0000002A +#define DDRSS_PHY_536_DATA 0x00000033 +#define DDRSS_PHY_537_DATA 0x0000000C +#define DDRSS_PHY_538_DATA 0x0000000C +#define DDRSS_PHY_539_DATA 0x00000033 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x003F0000 +#define DDRSS_PHY_542_DATA 0x000F013F +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000803E +#define DDRSS_PHY_553_DATA 0x00000003 +#define DDRSS_PHY_554_DATA 0x00000002 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000200 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00400000 +#define DDRSS_PHY_780_DATA 0x00000080 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x03000000 +#define DDRSS_PHY_783_DATA 0x00200000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x0000002A +#define DDRSS_PHY_789_DATA 0x00000015 +#define DDRSS_PHY_790_DATA 0x00000015 +#define DDRSS_PHY_791_DATA 0x0000002A +#define DDRSS_PHY_792_DATA 0x00000033 +#define DDRSS_PHY_793_DATA 0x0000000C +#define DDRSS_PHY_794_DATA 0x0000000C +#define DDRSS_PHY_795_DATA 0x00000033 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000803E +#define DDRSS_PHY_809_DATA 0x00000003 +#define DDRSS_PHY_810_DATA 0x00000002 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x0000002A +#define DDRSS_PHY_1045_DATA 0x00000015 +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x0000002A +#define DDRSS_PHY_1048_DATA 0x00000033 +#define DDRSS_PHY_1049_DATA 0x0000000C +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x00000033 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10000000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000803E +#define DDRSS_PHY_1065_DATA 0x00000003 +#define DDRSS_PHY_1066_DATA 0x00000002 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000000 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x00002001 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x01010100 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00041B42 +#define DDRSS_PHY_1312_DATA 0x00005201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07030101 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000076 +#define DDRSS_PHY_1334_DATA 0x00000400 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543210 +#define DDRSS_PHY_1360_DATA 0x00040198 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020000 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03000300 +#define DDRSS_PHY_1382_DATA 0x03000300 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x3183BF77 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000DFF +#define DDRSS_PHY_1390_DATA 0x30000DFF +#define DDRSS_PHY_1391_DATA 0x3F0DFF11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x780DFFCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x00018011 +#define DDRSS_PHY_1396_DATA 0x0089FF00 +#define DDRSS_PHY_1397_DATA 0x000C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x000C3F11 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x3F0DFF11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x00018011 +#define DDRSS_PHY_1404_DATA 0x0089FF00 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi deleted file mode 100644 index e5c64c86d1d..00000000000 --- a/arch/arm/dts/k3-am62-main.dtsi +++ /dev/null @@ -1,968 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM625 SoC Family Main Domain peripherals - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_main { - oc_sram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x70000000 0x10000>; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x01 0x00000000 0x00 0x2000>, /* GICC */ - <0x01 0x00010000 0x00 0x1000>, /* GICH */ - <0x01 0x00020000 0x00 0x2000>; /* GICV */ - /* - * vcpumntirq: - * virtual CPU interface maintenance interrupt - */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_conf: syscon@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x00100000 0x20000>; - - phy_gmii_sel: phy@4044 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4044 0x8>; - #phy-cells = <1>; - }; - - epwm_tbclk: clock-controller@4130 { - compatible = "ti,am62-epwm-tbclk"; - reg = <0x4130 0x4>; - #clock-cells = <1>; - }; - - audio_refclk0: clock-controller@82e0 { - compatible = "ti,am62-audio-refclk"; - reg = <0x82e0 0x4>; - clocks = <&k3_clks 157 0>; - assigned-clocks = <&k3_clks 157 0>; - assigned-clock-parents = <&k3_clks 157 8>; - #clock-cells = <0>; - }; - - audio_refclk1: clock-controller@82e4 { - compatible = "ti,am62-audio-refclk"; - reg = <0x82e4 0x4>; - clocks = <&k3_clks 157 10>; - assigned-clocks = <&k3_clks 157 10>; - assigned-clock-parents = <&k3_clks 157 18>; - #clock-cells = <0>; - }; - }; - - dmss: bus@48000000 { - bootph-all; - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - dma-ranges; - ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; - - ti,sci-dev-id = <25>; - - secure_proxy_main: mailbox@4d000000 { - bootph-all; - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x4d000000 0x00 0x80000>, - <0x00 0x4a600000 0x00 0x80000>, - <0x00 0x4a400000 0x00 0x80000>; - interrupt-names = "rx_012"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - }; - - inta_main_dmss: interrupt-controller@48000000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x48000000 0x00 0x100000>; - #interrupt-cells = <0>; - interrupt-controller; - interrupt-parent = <&gic500>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <28>; - ti,interrupt-ranges = <4 68 36>; - ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; - }; - - main_bcdma: dma-controller@485c0100 { - compatible = "ti,am64-dmss-bcdma"; - reg = <0x00 0x485c0100 0x00 0x100>, - <0x00 0x4c000000 0x00 0x20000>, - <0x00 0x4a820000 0x00 0x20000>, - <0x00 0x4aa40000 0x00 0x20000>, - <0x00 0x4bc00000 0x00 0x100000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <3>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <26>; - ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ - ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ - ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ - }; - - main_pktdma: dma-controller@485c0000 { - compatible = "ti,am64-dmss-pktdma"; - reg = <0x00 0x485c0000 0x00 0x100>, - <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <2>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <30>; - ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ - <0x24>, /* CPSW_TX_CHAN */ - <0x25>, /* SAUL_TX_0_CHAN */ - <0x26>; /* SAUL_TX_1_CHAN */ - ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ - <0x11>, /* RING_CPSW_TX_CHAN */ - <0x12>, /* RING_SAUL_TX_0_CHAN */ - <0x13>; /* RING_SAUL_TX_1_CHAN */ - ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ - <0x2b>, /* CPSW_RX_CHAN */ - <0x2d>, /* SAUL_RX_0_CHAN */ - <0x2f>, /* SAUL_RX_1_CHAN */ - <0x31>, /* SAUL_RX_2_CHAN */ - <0x33>; /* SAUL_RX_3_CHAN */ - ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ - <0x2c>, /* FLOW_CPSW_RX_CHAN */ - <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ - <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ - }; - }; - - dmsc: system-controller@44043000 { - bootph-all; - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - mbox-names = "rx", "tx"; - mboxes = <&secure_proxy_main 12>, - <&secure_proxy_main 13>; - reg-names = "debug_messages"; - reg = <0x00 0x44043000 0x00 0xfe0>; - - k3_pds: power-controller { - bootph-all; - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - bootph-all; - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - bootph-all; - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - crypto: crypto@40900000 { - compatible = "ti,am62-sa3ul"; - reg = <0x00 0x40900000 0x00 0x1200>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - - dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, - <&main_pktdma 0x7507 0>; - dma-names = "tx", "rx1", "rx2"; - }; - - secure_proxy_sa3: mailbox@43600000 { - bootph-pre-ram; - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x43600000 0x00 0x10000>, - <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - main_pmx0: pinctrl@f4000 { - bootph-all; - compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2ac>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_esm: esm@420000 { - bootph-pre-ram; - compatible = "ti,j721e-esm"; - reg = <0x00 0x420000 0x00 0x1000>; - ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; - }; - - main_timer0: timer@2400000 { - bootph-all; - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 36 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 36 2>; - assigned-clock-parents = <&k3_clks 36 3>; - power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 37 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 37 2>; - assigned-clock-parents = <&k3_clks 37 3>; - power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 38 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 38 2>; - assigned-clock-parents = <&k3_clks 38 3>; - power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 39 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 39 2>; - assigned-clock-parents = <&k3_clks 39 3>; - power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 40 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 40 2>; - assigned-clock-parents = <&k3_clks 40 3>; - power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 41 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 41 2>; - assigned-clock-parents = <&k3_clks 41 3>; - power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 42 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 42 2>; - assigned-clock-parents = <&k3_clks 42 3>; - power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 43 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 43 2>; - assigned-clock-parents = <&k3_clks 43 3>; - power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 152 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 153 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 154 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 155 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@20000000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20000000 0x00 0x100>; - interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c1: i2c@20010000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20010000 0x00 0x100>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 103 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c2: i2c@20020000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20020000 0x00 0x100>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 104 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c3: i2c@20030000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20030000 0x00 0x100>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_spi0: spi@20100000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x20100000 0x00 0x400>; - interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 141 0>; - status = "disabled"; - }; - - main_spi1: spi@20110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20110000 0x00 0x400>; - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 142 0>; - status = "disabled"; - }; - - main_spi2: spi@20120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20120000 0x00 0x400>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 143 0>; - status = "disabled"; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <3>; - ti,interrupt-ranges = <0 32 16>; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <190>, <191>, <192>, - <193>, <194>, <195>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <92>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 77 0>; - clock-names = "gpio"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <180>, <181>, <182>, - <183>, <184>, <185>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <52>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 78 0>; - clock-names = "gpio"; - }; - - sdhci0: mmc@fa10000 { - compatible = "ti,am62-sdhci"; - reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 57 6>; - assigned-clock-parents = <&k3_clks 57 8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - bus-width = <8>; - ti,clkbuf-sel = <0x7>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x5>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-mmc-hs = <0x1>; - status = "disabled"; - }; - - sdhci1: mmc@fa00000 { - compatible = "ti,am62-sdhci"; - reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; - clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x8>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x4>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-sd-hs = <0x1>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; - status = "disabled"; - }; - - sdhci2: mmc@fa20000 { - compatible = "ti,am62-sdhci"; - reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; - clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x8>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x8>; - ti,itap-del-sel-legacy = <0xa>; - ti,itap-del-sel-sd-hs = <0xa>; - ti,itap-del-sel-sdr12 = <0xa>; - ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; - status = "disabled"; - }; - - usbss0: dwc3-usb@f900000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>; - clocks = <&k3_clks 161 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb0: usb@31000000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31000000 0x00 0x50000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: dwc3-usb@f910000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; - clocks = <&k3_clks 162 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb1: usb@31100000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31100000 0x00 0x50000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - - fss: bus@fc00000 { - compatible = "simple-bus"; - reg = <0x00 0x0fc00000 0x00 0x70000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@fc40000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x0fc40000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 75 7>; - assigned-clocks = <&k3_clks 75 7>; - assigned-clock-parents = <&k3_clks 75 8>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - cpsw3g: ethernet@8000000 { - compatible = "ti,am642-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0x08000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; - clocks = <&k3_clks 13 0>; - assigned-clocks = <&k3_clks 13 3>; - assigned-clock-parents = <&k3_clks 13 11>; - clock-names = "fck"; - power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_pktdma 0xc600 15>, - <&main_pktdma 0xc601 15>, - <&main_pktdma 0xc602 15>, - <&main_pktdma 0xc603 15>, - <&main_pktdma 0xc604 15>, - <&main_pktdma 0xc605 15>, - <&main_pktdma 0xc606 15>, - <&main_pktdma 0xc607 15>, - <&main_pktdma 0x4600 15>; - dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", - "tx7", "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel 1>; - mac-address = [00 00 00 00 00 00]; - ti,syscon-efuse = <&wkup_conf 0x200>; - }; - - cpsw_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - phys = <&phy_gmii_sel 2>; - mac-address = [00 00 00 00 00 00]; - }; - }; - - cpsw3g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 13 0>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 13 3>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - dss: dss@30200000 { - compatible = "ti,am625-dss"; - reg = <0x00 0x30200000 0x00 0x1000>, /* common */ - <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ - <0x00 0x30206000 0x00 0x1000>, /* vid */ - <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ - <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ - <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ - reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; - power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 186 6>, - <&dss_vp1_clk>, - <&k3_clks 186 2>; - clock-names = "fck", "vp1", "vp2"; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - dss_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - hwspinlock: spinlock@2a000000 { - compatible = "ti,am64-hwspinlock"; - reg = <0x00 0x2a000000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@29000000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29000000 0x00 0x200>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - ecap0: pwm@23100000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23100000 0x00 0x100>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 51 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap1: pwm@23110000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23110000 0x00 0x100>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 52 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap2: pwm@23120000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23120000 0x00 0x100>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 53 0>; - clock-names = "fck"; - status = "disabled"; - }; - - main_mcan0: can@20701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x20701000 0x00 0x200>, - <0x00 0x20708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_rti0: watchdog@e000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e000000 0x00 0x100>; - clocks = <&k3_clks 125 0>; - power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 125 0>; - assigned-clock-parents = <&k3_clks 125 2>; - }; - - main_rti1: watchdog@e010000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e010000 0x00 0x100>; - clocks = <&k3_clks 126 0>; - power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 126 0>; - assigned-clock-parents = <&k3_clks 126 2>; - }; - - main_rti2: watchdog@e020000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e020000 0x00 0x100>; - clocks = <&k3_clks 127 0>; - power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 127 0>; - assigned-clock-parents = <&k3_clks 127 2>; - }; - - main_rti3: watchdog@e030000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e030000 0x00 0x100>; - clocks = <&k3_clks 128 0>; - power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 128 0>; - assigned-clock-parents = <&k3_clks 128 2>; - }; - - main_rti15: watchdog@e0f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e0f0000 0x00 0x100>; - clocks = <&k3_clks 130 0>; - power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 130 0>; - assigned-clock-parents = <&k3_clks 130 2>; - }; - - epwm0: pwm@23000000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23000000 0x00 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm1: pwm@23010000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23010000 0x00 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm2: pwm@23020000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23020000 0x00 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - mcasp0: audio-controller@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b00000 0x00 0x2000>, - <0x00 0x02b08000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 190 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 190 0>; - assigned-clock-parents = <&k3_clks 190 2>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp1: audio-controller@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b10000 0x00 0x2000>, - <0x00 0x02b18000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 191 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 191 0>; - assigned-clock-parents = <&k3_clks 191 2>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp2: audio-controller@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b20000 0x00 0x2000>, - <0x00 0x02b28000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 192 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 192 0>; - assigned-clock-parents = <&k3_clks 192 2>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi deleted file mode 100644 index 0e0b234581c..00000000000 --- a/arch/arm/dts/k3-am62-mcu.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM625 SoC Family MCU Domain peripherals - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu { - mcu_pmx0: pinctrl@4084000 { - bootph-all; - compatible = "pinctrl-single"; - reg = <0x00 0x04084000 0x00 0x88>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_esm: esm@4100000 { - bootph-pre-ram; - compatible = "ti,j721e-esm"; - reg = <0x00 0x4100000 0x00 0x1000>; - ti,esm-pins = <0>, <1>, <2>, <85>; - }; - - /* - * The MCU domain timer interrupts are routed only to the ESM module, - * and not currently available for Linux. The MCU domain timers are - * of limited use without interrupts, and likely reserved by the ESM. - */ - mcu_timer0: timer@4800000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4800000 0x00 0x400>; - clocks = <&k3_clks 35 2>; - clock-names = "fck"; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer1: timer@4810000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4810000 0x00 0x400>; - clocks = <&k3_clks 48 2>; - clock-names = "fck"; - power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer2: timer@4820000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4820000 0x00 0x400>; - clocks = <&k3_clks 49 2>; - clock-names = "fck"; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer3: timer@4830000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4830000 0x00 0x400>; - clocks = <&k3_clks 50 2>; - clock-names = "fck"; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_uart0: serial@4a00000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x04a00000 0x00 0x100>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_i2c0: i2c@4900000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x04900000 0x00 0x100>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 2>; - clock-names = "fck"; - status = "disabled"; - }; - - mcu_spi0: spi@4b00000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x04b00000 0x00 0x400>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 147 0>; - status = "disabled"; - }; - - mcu_spi1: spi@4b10000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x04b10000 0x00 0x400>; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 148 0>; - status = "disabled"; - }; - - mcu_gpio_intr: interrupt-controller@4210000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x04210000 0x00 0x200>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <5>; - ti,interrupt-ranges = <0 104 4>; - }; - - mcu_gpio0: gpio@4201000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x4201000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&mcu_gpio_intr>; - interrupts = <30>, <31>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <24>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 79 0>; - clock-names = "gpio"; - }; - - mcu_rti0: watchdog@4880000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x04880000 0x00 0x100>; - clocks = <&k3_clks 131 0>; - power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 131 0>; - assigned-clock-parents = <&k3_clks 131 2>; - /* Tightly coupled to M4F */ - status = "reserved"; - }; - - mcu_mcan0: can@4e08000 { - compatible = "bosch,m_can"; - reg = <0x00 0x4e08000 0x00 0x200>, - <0x00 0x4e00000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@4e18000 { - compatible = "bosch,m_can"; - reg = <0x00 0x4e18000 0x00 0x200>, - <0x00 0x4e10000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts new file mode 100644 index 00000000000..ec5d3f4ba2c --- /dev/null +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62x LP SK dts file for R5 SPL + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62-lp-sk.dts" +#include "k3-am62-lp4-50-800-800.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am62-lp-sk-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&secure_proxy_sa3 { + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_main { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&secure_proxy_sa3 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am62-thermal.dtsi b/arch/arm/dts/k3-am62-thermal.dtsi deleted file mode 100644 index a358757e26f..00000000000 --- a/arch/arm/dts/k3-am62-thermal.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - main0_crit: main0-crit { - temperature = <105000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - main1_crit: main1-crit { - temperature = <105000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi deleted file mode 100644 index fef76f52a52..00000000000 --- a/arch/arm/dts/k3-am62-wakeup.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_wakeup { - wkup_conf: syscon@43000000 { - bootph-all; - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x43000000 0x20000>; - - chipid: chipid@14 { - bootph-all; - compatible = "ti,am654-chipid"; - reg = <0x14 0x4>; - }; - }; - - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_i2c0: i2c@2b200000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2b200000 0x00 0x100>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 4>; - clock-names = "fck"; - status = "disabled"; - }; - - wkup_rtc0: rtc@2b1f0000 { - compatible = "ti,am62-rtc"; - reg = <0x00 0x2b1f0000 0x00 0x100>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; - clock-names = "vbus", "osc32k"; - power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; - wakeup-source; - }; - - wkup_rti0: watchdog@2b000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2b000000 0x00 0x100>; - clocks = <&k3_clks 132 0>; - power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 132 0>; - assigned-clock-parents = <&k3_clks 132 2>; - /* Used by DM firmware */ - status = "reserved"; - }; - - wkup_vtm0: temperature-sensor@b00000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0xb00000 0x00 0x400>, - <0x00 0xb01000 0x00 0x400>; - power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi deleted file mode 100644 index f1e15206e1c..00000000000 --- a/arch/arm/dts/k3-am62.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM62 SoC Family - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 AM625 SoC"; - compatible = "ti,am625"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a53_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@f0000 { - bootph-all; - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ - <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ - <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ - <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ - <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ - <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ - <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ - <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ - <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ - <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ - <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ - <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ - <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ - <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ - <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ - <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ - <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ - <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ - - /* MCU Domain Range */ - <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, - - /* Wakeup Domain Range */ - <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ - <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; - - cbass_mcu: bus@4000000 { - bootph-all; - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ - }; - - cbass_wakeup: bus@b00000 { - bootph-all; - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ - <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; - }; - }; - - dss_vp1_clk: clock-divider-oldi { - compatible = "fixed-factor-clock"; - clocks = <&k3_clks 186 0>; - #clock-cells = <0>; - clock-div = <7>; - clock-mult = <1>; - }; - - #include "k3-am62-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-am62-main.dtsi" -#include "k3-am62-mcu.dtsi" -#include "k3-am62-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index fb2032068d1..467cac68d0f 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -54,12 +54,21 @@ >; }; +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; + #ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY #define SPL_NODTB "spl/u-boot-spl-nodtb.bin" -#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb" +#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/ti/k3-am625-beagleplay.dtb" #define UBOOT_NODTB "u-boot-nodtb.bin" -#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb" +#define AM625_BEAGLEPLAY_DTB "dts/upstream/src/arm64/ti/k3-am625-beagleplay.dtb" &binman { ti-dm { @@ -71,6 +80,7 @@ ti-spl_unsigned { filename = "tispl.bin_unsigned"; + symlink = "tispl.bin"; pad-byte = <0xff>; fit { @@ -205,4 +215,94 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See beagleplay.h +#define BEAGLEPLAY_SPL_IMAGE_GUID_STR "b2e7cc49-1a5a-4036-ae01-3387c3bef657" +#define BEAGLEPLAY_UBOOT_IMAGE_GUID_STR "92c92b11-a7ee-486f-aaa2-713d84425b0e" + +&capsule_tispl { + efi-capsule { + image-guid = BEAGLEPLAY_SPL_IMAGE_GUID_STR; + + blob { + filename = "tispl.bin_unsigned"; + }; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = BEAGLEPLAY_UBOOT_IMAGE_GUID_STR; + + blob { + filename = "u-boot.img_unsigned"; + }; + }; +}; + #endif + +&main_bcdma { + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>, + <0x00 0x48600000 0x00 0x8000>, + <0x00 0x484a4000 0x00 0x2000>, + <0x00 0x484c2000 0x00 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "cfg", "tchan", "rchan"; +}; + +&main_pktdma { + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>, + <0x00 0x485e0000 0x00 0x20000>, + <0x00 0x484a0000 0x00 0x4000>, + <0x00 0x484c0000 0x00 0x2000>, + <0x00 0x48430000 0x00 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", + "tchan", "rchan", "rflow"; + bootph-all; +}; + +&mdio0_pins_default { + bootph-all; +}; + +&cpsw3g_mdio { + bootph-all; +}; + +&cpsw3g_phy0 { + bootph-all; +}; + +&rgmii1_pins_default { + bootph-all; +}; + +&cpsw3g { + bootph-all; + + ethernet-ports { + bootph-all; + }; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&cpsw_port1 { + bootph-all; +}; + +&cpsw_port2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts deleted file mode 100644 index 9a6bd0a3c94..00000000000 --- a/arch/arm/dts/k3-am625-beagleplay.dts +++ /dev/null @@ -1,940 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * https://beagleplay.org/ - * - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation - */ - -/dts-v1/; - -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include "k3-am625.dtsi" - -/ { - compatible = "beagle,am625-beagleplay", "ti,am625"; - model = "BeagleBoard.org BeaglePlay"; - - aliases { - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - gpio0 = &main_gpio0; - gpio1 = &main_gpio1; - gpio2 = &mcu_gpio0; - i2c0 = &main_i2c0; - i2c1 = &main_i2c1; - i2c2 = &main_i2c2; - i2c3 = &main_i2c3; - i2c4 = &wkup_i2c0; - i2c5 = &mcu_i2c0; - mdio-gpio0 = &mdio0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - rtc0 = &rtc; - serial0 = &main_uart5; - serial1 = &main_uart6; - serial2 = &main_uart0; - usb0 = &usb0; - usb1 = &usb1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - bootph-pre-ram; - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops: ramoops@9ca00000 { - compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x00>; - pmsg-size = <0x8000>; - }; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; - - vsys_5v0: regulator-1 { - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3: regulator-2 { - /* output of TLV62595DMQR-U12 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_5v0>; - regulator-always-on; - regulator-boot-on; - }; - - wlan_en: regulator-3 { - /* OUTPUT of SN74AVC2T244DQMR */ - compatible = "regulator-fixed"; - regulator-name = "wlan_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - vin-supply = <&vdd_3v3>; - gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_pins_default>; - }; - - vdd_3v3_sd: regulator-4 { - /* output of TPS22918DBVR-U21 */ - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_3v3_sd_pins_default>; - - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - vin-supply = <&vdd_3v3>; - gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-5 { - bootph-all; - compatible = "regulator-gpio"; - regulator-name = "sd_hs200_switch"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&ldo1_reg>; - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - leds { - bootph-all; - compatible = "gpio-leds"; - - led-0 { - bootph-all; - gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; - - led-1 { - bootph-all; - gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - function = LED_FUNCTION_DISK_ACTIVITY; - default-state = "keep"; - }; - - led-2 { - bootph-all; - gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_CPU; - }; - - led-3 { - bootph-all; - gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_LAN; - }; - - led-4 { - bootph-all; - gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_WLAN; - }; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&usr_button_pins_default>; - - usr: button-usr { - label = "User Key"; - linux,code = <BTN_0>; - gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; - }; - - }; - - hdmi0: connector-hdmi { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&it66121_out>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "it66121 HDMI"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&hdmi_dailink_master>; - simple-audio-card,frame-master = <&hdmi_dailink_master>; - - hdmi_dailink_master: simple-audio-card,cpu { - sound-dai = <&mcasp1>; - system-clock-direction-out; - }; - - simple-audio-card,codec { - sound-dai = <&it66121>; - }; - }; - - /* Workaround for errata i2329 - just use mdio bitbang */ - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio0_pins_default>; - gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ - <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - }; - - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ - }; - }; -}; - -&main_pmx0 { - gpio0_pins_default: gpio0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ - AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ - AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ - AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ - AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ - AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ - AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */ - AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ - AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ - AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ - AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */ - AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ - AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ - AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ - >; - }; - - usr_button_pins_default: usr-button-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ - >; - }; - - grove_pins_default: grove-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ - AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ - >; - }; - - local_i2c_pins_default: local-i2c-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ - AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ - >; - }; - - i2c2_1v8_pins_default: i2c2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ - AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - mdio0_pins_default: mdio0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ - AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ - >; - }; - - rgmii1_pins_default: rgmii1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ - AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ - AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ - AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ - AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ - AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ - AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ - AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ - AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ - AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ - AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ - AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ - >; - }; - - emmc_pins_default: emmc-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ - >; - }; - - sd_pins_default: sd-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ - AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ - AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ - AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ - AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ - AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ - AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ - >; - }; - - wifi_pins_default: wifi-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ - AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ - AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ - AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ - AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ - AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ - AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */ - AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ - >; - }; - - wifi_en_pins_default: wifi-en-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ - >; - }; - - wifi_wlirq_pins_default: wifi-wlirq-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ - >; - }; - - spe_pins_default: spe-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ - AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ - AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */ - AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */ - AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */ - AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ - AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ - AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ - AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ - AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ - AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ - >; - }; - - mikrobus_i2c_pins_default: mikrobus-i2c-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ - AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ - >; - }; - - mikrobus_uart_pins_default: mikrobus-uart-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ - AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ - >; - }; - - mikrobus_spi_pins_default: mikrobus-spi-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ - AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ - AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ - AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ - >; - }; - - mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ - AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ - AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ - >; - }; - - console_pins_default: console-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ - >; - }; - - wifi_debug_uart_pins_default: wifi-debug-uart-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ - AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ - >; - }; - - usb1_pins_default: usb1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ - >; - }; - - pmic_irq_pins_default: pmic-irq-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ - >; - }; - - hdmi_gpio_pins_default: hdmi-gpio-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ - AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ - >; - }; - - mcasp_hdmi_pins_default: mcasp-hdmi-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ - AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ - AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ - AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ - AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */ - AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */ - >; - }; - - dss0_pins_default: dss0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ - AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ - AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ - AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ - AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ - AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ - AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ - AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ - AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ - AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ - AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ - AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ - AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ - AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ - AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ - AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ - AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ - AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ - AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ - AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ - AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ - AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ - AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ - AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ - AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ - AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ - AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ - AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ - >; - }; -}; - -&mcu_pmx0 { - i2c_qwiic_pins_default: i2c-qwiic-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ - AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ - >; - }; - - gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ - >; - }; - - i2c_csi_pins_default: i2c-csi-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ - AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ - >; - }; - - wifi_32k_clk: mcu-clk-out-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ - >; - }; -}; - -&a53_opp_table { - /* Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - }; -}; - -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_csi_pins_default>; - clock-frequency = <400000>; - /* Enable with overlay for camera sensor */ -}; - -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_qwiic_pins_default>; - clock-frequency = <100000>; - status = "okay"; -}; - -&usbss0 { - ti,vbus-divider; - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; -}; - -&usbss1 { - ti,vbus-divider; - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_default>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>, - <&gbe_pmx_obsclk>; - assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>; - assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - phy-mode = "rmii"; - phy-handle = <&cpsw3g_phy1>; -}; - -&cpsw3g_mdio { - /* Workaround for errata i2329 - Use mdio bitbang */ - status = "disabled"; -}; - -&main_gpio0 { - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_pins_default>; - gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ - "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ - "EEPROM_WP", /* 10 */ - "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ - "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ - "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ - "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ - "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ - "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */ - "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */ - "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */ - "", "", "", "", "", "", /* 79-84 */ - "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */ - "", "", "", "", ""; /* 87-91 */ -}; - -&main_gpio1 { - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&mikrobus_gpio_pins_default>; - gpio-line-names = "", "", "", "", "", /* 0-4 */ - "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */ - "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */ - "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */ - "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */ - "MIKROBUS_GPIO1_14", /* 14 */ - "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */ - "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */ - "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */ - "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */ - "", "", "", "", "", "", "", "", "", "", /* 38-47 */ - "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */ -}; - -&main_i2c0 { - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&local_i2c_pins_default>; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - rtc: rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - interrupt-parent = <&main_gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - - tps65219: pmic@30 { - bootph-all; - compatible = "ti,tps65219"; - reg = <0x30>; - buck1-supply = <&vsys_5v0>; - buck2-supply = <&vsys_5v0>; - buck3-supply = <&vsys_5v0>; - ldo1-supply = <&vdd_3v3>; - ldo2-supply = <&buck2_reg>; - ldo3-supply = <&vdd_3v3>; - ldo4-supply = <&vdd_3v3>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins_default>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - system-power-controller; - ti,power-button; - - regulators { - buck1_reg: buck1 { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - buck2_reg: buck2 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck3_reg: buck3 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* - * Regulator is left as is unused, vdd_sd - * is controlled via GPIO with bypass config - * as per the NVM configuration - */ - regulator-name = "VDD_SD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allow-bypass; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-name = "VDDA_0V85"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-name = "VDD_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&grove_pins_default>; - clock-frequency = <100000>; - status = "okay"; -}; - -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_1v8_pins_default>; - clock-frequency = <100000>; - status = "okay"; - - it66121: bridge-hdmi@4c { - compatible = "ite,it66121"; - reg = <0x4c>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_gpio_pins_default>; - vcn33-supply = <&vdd_3v3>; - vcn18-supply = <&buck2_reg>; - vrf12-supply = <&buck3_reg>; - reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>; - interrupt-parent = <&main_gpio0>; - interrupts = <36 IRQ_TYPE_EDGE_FALLING>; - #sound-dai-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - it66121_in: endpoint { - bus-width = <24>; - remote-endpoint = <&dpi1_out>; - }; - }; - - port@1 { - reg = <1>; - - it66121_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&mikrobus_i2c_pins_default>; - clock-frequency = <400000>; - status = "okay"; -}; - -&main_spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mikrobus_spi_pins_default>; - status = "okay"; -}; - -&sdhci0 { - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; - status = "okay"; -}; - -&sdhci1 { - /* SD/MMC */ - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pins_default>; - - vmmc-supply = <&vdd_3v3_sd>; - vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; - disable-wp; - cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; - cd-debounce-delay-ms = <100>; - ti,fails-without-test-cd; - status = "okay"; -}; - -&sdhci2 { - vmmc-supply = <&wlan_en>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; - non-removable; - ti,fails-without-test-cd; - cap-power-off-card; - keep-power-in-suspend; - ti,driver-strength-ohm = <50>; - assigned-clocks = <&k3_clks 157 158>; - assigned-clock-parents = <&k3_clks 157 160>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1807"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_wlirq_pins_default>; - interrupt-parent = <&main_gpio0>; - interrupts = <41 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&main_uart0 { - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&console_pins_default>; - status = "okay"; -}; - -&main_uart1 { - /* Main UART1 is used by TIFS firmware */ - status = "reserved"; -}; - -&main_uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&mikrobus_uart_pins_default>; - status = "okay"; -}; - -&main_uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&wifi_debug_uart_pins_default>; - status = "okay"; - - mcu { - compatible = "ti,cc1352p7"; - reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>; - vdds-supply = <&vdd_3v3>; - }; -}; - -&dss { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss0_pins_default>; -}; - -&dss_ports { - /* VP2: DPI Output */ - port@1 { - reg = <1>; - - dpi1_out: endpoint { - remote-endpoint = <&it66121_in>; - }; - }; -}; - -&mcasp1 { - status = "okay"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp_hdmi_pins_default>; - auxclk-fs-ratio = <2177>; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index 94162282068..2bc5acbec23 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -127,6 +127,32 @@ flash@0 { bootph-all; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00000 0x80000>; + }; + partition@80000 { + label = "ospi.tispl"; + reg = <0x080000 0x200000>; + }; + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + }; }; }; @@ -142,6 +168,15 @@ bootph-all; }; +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; + &vcc_3v3_mmc { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9db58f093c8..f0b66f0cb94 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -79,6 +79,7 @@ &binman { tiboot3-am62x-gp-evm.bin { filename = "tiboot3-am62x-gp-evm.bin"; + symlink = "tiboot3.bin"; ti-secure-rom { content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; @@ -114,3 +115,18 @@ }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See beagleplay.h +#define BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR "0e225a09-f720-4d57-9120-e28f737f5a5e" + +&capsule_tiboot3 { + efi-capsule { + image-guid = BEAGLEPLAY_TIBOOT3_IMAGE_GUID_STR; + + blob { + filename = "tiboot3-am62x-gp-evm.bin"; + }; + }; +}; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index dfd38d64f63..534eb14795b 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -137,11 +137,22 @@ }; }; +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See am62x_evm.h +#define AM62X_SK_TIBOOT3_IMAGE_GUID_STR "abcb83d2-9cb6-4351-b8f1-6494bbe3700a" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM62X_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + #endif #ifdef CONFIG_TARGET_AM625_A53_EVM -#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb" +#define SPL_AM625_SK_DTB "spl/dts/ti/k3-am625-sk.dtb" #define AM625_SK_DTB "u-boot.dtb" &binman { @@ -149,6 +160,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; @@ -452,4 +464,23 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See am62x_evm.h +#define AM62X_SK_SPL_IMAGE_GUID_STR "aee355fc-bf97-4264-8c82-437255efdc1d" +#define AM62X_SK_UBOOT_IMAGE_GUID_STR "28ab8c6c-fca8-41d3-8ea1-5f171b7d2929" + +&capsule_tispl { + efi-capsule { + image-guid = AM62X_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM62X_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index fa778b0ff4c..1fc0d407cbf 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -46,3 +46,12 @@ &cpsw_port2 { status = "disabled"; }; + +&usbss0 { + bootph-all; +}; + +&usb0 { + dr_mode = "peripheral"; + bootph-all; +}; diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts deleted file mode 100644 index b18092497c9..00000000000 --- a/arch/arm/dts/k3-am625-sk.dts +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * AM625 SK: https://www.ti.com/lit/zip/sprr448 - * - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-am62x-sk-common.dtsi" - -/ { - compatible = "ti,am625-sk", "ti,am625"; - model = "Texas Instruments AM625 SK"; - - opp-table { - /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - - }; - - vmain_pd: regulator-0 { - /* TPS65988 PD CONTROLLER OUTPUT */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vmain_pd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_5v0: regulator-1 { - /* Output of LM34936 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sys: regulator-2 { - /* output of LM61460-Q1 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS22918DBVR */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc_3v3_sys>; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-4 { - /* Output of TLV71033 */ - bootph-all; - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vcc_5v0>; - gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - vcc_1v8: regulator-5 { - /* output of TPS6282518DMQ */ - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3_sys>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&main_pmx0 { - main_rgmii2_pins_default: main-rgmii2-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ - AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ - AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ - AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ - AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ - AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ - AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ - AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ - AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ - AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ - AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ - AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ - >; - }; - - ospi0_pins_default: ospi0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ - AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ - AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ - AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ - AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ - AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ - AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ - AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ - AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ - AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ - AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ - >; - }; - - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ - >; - }; -}; - -&main_gpio0 { - bootph-all; -}; - -&main_gpio1 { - bootph-all; -}; - -&main_i2c1 { - bootph-all; - exp1: gpio@22 { - bootph-all; - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", - "PRU_DETECT", "MMC1_SD_EN", - "VPP_LDO_EN", "EXP_PS_3V3_En", - "EXP_PS_5V0_En", "EXP_HAT_DETECT", - "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", - "UART1_FET_BUF_EN", "WL_LT_EN", - "GPIO_HDMI_RSTn", "CSI_GPIO1", - "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "PD_I2C_IRQ", - "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", - "MCASP1_FET_SEL", "UART1_FET_SEL", - "TSINT#", "IO_EXP_TEST_LED"; - - interrupt-parent = <&main_gpio1>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; - }; -}; - -&sdhci1 { - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy1>; -}; - -&cpsw3g_mdio { - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&fss { - bootph-all; -}; - -&ospi0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ospi0_pins_default>; - - flash@0 { - bootph-all; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - bootph-all; - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.env.backup"; - reg = <0x6c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-pre-ram; - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&tlv320aic3106 { - DVDD-supply = <&vcc_1v8>; -}; diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index 841541bb243..5062447547b 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 - * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01 + * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -10,9 +10,11 @@ * Number of Ranks: 1 */ + #define DDRSS_PLL_FHS_CNT 3 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 +#define DDRSS_SDRAM_IDX 15 #define DDRSS_CTL_0_DATA 0x00000B00 @@ -848,7 +850,7 @@ #define DDRSS_PHY_62_DATA 0x00000000 #define DDRSS_PHY_63_DATA 0x00000000 #define DDRSS_PHY_64_DATA 0x00000000 -#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_65_DATA 0x00000104 #define DDRSS_PHY_66_DATA 0x00000000 #define DDRSS_PHY_67_DATA 0x00000000 #define DDRSS_PHY_68_DATA 0x00000000 @@ -1104,7 +1106,7 @@ #define DDRSS_PHY_318_DATA 0x00000000 #define DDRSS_PHY_319_DATA 0x00000000 #define DDRSS_PHY_320_DATA 0x00000000 -#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_321_DATA 0x00000104 #define DDRSS_PHY_322_DATA 0x00000000 #define DDRSS_PHY_323_DATA 0x00000000 #define DDRSS_PHY_324_DATA 0x00000000 diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index a9b86b61e53..0e6188907e4 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -448,4 +448,72 @@ }; }; +&binman { + firmware-verdin-am62-gp.bin { + filename = "firmware-verdin-am62-gp.bin"; + + blob-ext@1 { + filename = "tiboot3-am62x-gp-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin_unsigned"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img_unsigned"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-verdin-am62-hs.bin { + filename = "firmware-verdin-am62-hs.bin"; + + blob-ext@1 { + filename = "tiboot3-am62x-hs-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-verdin-am62-hs-fs.bin { + filename = "firmware-verdin-am62-hs-fs.bin"; + + blob-ext@1 { + filename = "tiboot3-am62x-hs-fs-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; +}; + #endif /* CONFIG_TARGET_VERDIN_AM62_A53 */ diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi deleted file mode 100644 index 4193c2b3eed..00000000000 --- a/arch/arm/dts/k3-am625.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM625 SoC family in Quad core configuration - * - * TRM: https://www.ti.com/lit/pdf/spruiv7 - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-am62.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - - core2 { - cpu = <&cpu2>; - }; - - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - operating-points-v2 = <&a53_opp_table>; - clocks = <&k3_clks 135 0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - operating-points-v2 = <&a53_opp_table>; - clocks = <&k3_clks 136 0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - reg = <0x002>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - operating-points-v2 = <&a53_opp_table>; - clocks = <&k3_clks 137 0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - reg = <0x003>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - operating-points-v2 = <&a53_opp_table>; - clocks = <&k3_clks 138 0>; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2-ti-cpu"; - opp-shared; - syscon = <&wkup_conf>; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-supported-hw = <0x01 0x0007>; - clock-latency-ns = <6000000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-supported-hw = <0x01 0x0007>; - clock-latency-ns = <6000000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-supported-hw = <0x01 0x0007>; - clock-latency-ns = <6000000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-supported-hw = <0x01 0x0007>; - clock-latency-ns = <6000000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-supported-hw = <0x01 0x0006>; - clock-latency-ns = <6000000>; - }; - - opp-1250000000 { - opp-hz = /bits/ 64 <1250000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - opp-suspend; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; -}; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi deleted file mode 100644 index 4ae7fdc5221..00000000000 --- a/arch/arm/dts/k3-am62a-main.dtsi +++ /dev/null @@ -1,879 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM62A SoC Family Main Domain peripherals - * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_main { - oc_sram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x70000000 0x10000>; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x00 0x01880000 0x00 0xc0000>, /* GICR */ - <0x01 0x00000000 0x00 0x2000>, /* GICC */ - <0x01 0x00010000 0x00 0x1000>, /* GICH */ - <0x01 0x00020000 0x00 0x2000>; /* GICV */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - /* - * vcpumntirq: - * virtual CPU interface maintenance interrupt - */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_conf: syscon@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00100000 0x20000>; - - phy_gmii_sel: phy@4044 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4044 0x8>; - #phy-cells = <1>; - }; - - epwm_tbclk: clock-controller@4130 { - compatible = "ti,am62-epwm-tbclk"; - reg = <0x4130 0x4>; - #clock-cells = <1>; - }; - }; - - dmss: bus@48000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - dma-ranges; - ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; - - ti,sci-dev-id = <25>; - - secure_proxy_main: mailbox@4d000000 { - compatible = "ti,am654-secure-proxy"; - reg = <0x00 0x4d000000 0x00 0x80000>, - <0x00 0x4a600000 0x00 0x80000>, - <0x00 0x4a400000 0x00 0x80000>; - reg-names = "target_data", "rt", "scfg"; - #mbox-cells = <1>; - interrupt-names = "rx_012"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - }; - - inta_main_dmss: interrupt-controller@48000000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x48000000 0x00 0x100000>; - #interrupt-cells = <0>; - interrupt-controller; - interrupt-parent = <&gic500>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <28>; - ti,interrupt-ranges = <6 70 34>; - ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; - }; - - main_bcdma: dma-controller@485c0100 { - compatible = "ti,am64-dmss-bcdma"; - reg = <0x00 0x485c0100 0x00 0x100>, - <0x00 0x4c000000 0x00 0x20000>, - <0x00 0x4a820000 0x00 0x20000>, - <0x00 0x4aa40000 0x00 0x20000>, - <0x00 0x4bc00000 0x00 0x100000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <3>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <26>; - ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ - ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ - ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ - }; - - main_pktdma: dma-controller@485c0000 { - compatible = "ti,am64-dmss-pktdma"; - reg = <0x00 0x485c0000 0x00 0x100>, - <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x40000>, - <0x00 0x4b800000 0x00 0x400000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&inta_main_dmss>; - #dma-cells = <2>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <30>; - ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ - <0x24>, /* CPSW_TX_CHAN */ - <0x25>, /* SAUL_TX_0_CHAN */ - <0x26>; /* SAUL_TX_1_CHAN */ - ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ - <0x11>, /* RING_CPSW_TX_CHAN */ - <0x12>, /* RING_SAUL_TX_0_CHAN */ - <0x13>; /* RING_SAUL_TX_1_CHAN */ - ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ - <0x2b>, /* CPSW_RX_CHAN */ - <0x2d>, /* SAUL_RX_0_CHAN */ - <0x2f>, /* SAUL_RX_1_CHAN */ - <0x31>, /* SAUL_RX_2_CHAN */ - <0x33>; /* SAUL_RX_3_CHAN */ - ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ - <0x2c>, /* FLOW_CPSW_RX_CHAN */ - <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ - <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ - }; - }; - - dmsc: system-controller@44043000 { - compatible = "ti,k2g-sci"; - reg = <0x00 0x44043000 0x00 0xfe0>; - reg-names = "debug_messages"; - ti,host-id = <12>; - mbox-names = "rx", "tx"; - mboxes = <&secure_proxy_main 12>, - <&secure_proxy_main 13>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - secure_proxy_sa3: mailbox@43600000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x43600000 0x00 0x10000>, - <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - main_pmx0: pinctrl@f4000 { - compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2ac>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 36 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 36 2>; - assigned-clock-parents = <&k3_clks 36 3>; - power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 37 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 37 2>; - assigned-clock-parents = <&k3_clks 37 3>; - power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 38 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 38 2>; - assigned-clock-parents = <&k3_clks 38 3>; - power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 39 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 39 2>; - assigned-clock-parents = <&k3_clks 39 3>; - power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 40 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 40 2>; - assigned-clock-parents = <&k3_clks 40 3>; - power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 41 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 41 2>; - assigned-clock-parents = <&k3_clks 41 3>; - power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 42 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 42 2>; - assigned-clock-parents = <&k3_clks 42 3>; - power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 43 2>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 43 2>; - assigned-clock-parents = <&k3_clks 43 3>; - power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 152 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 153 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 154 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 155 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@20000000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20000000 0x00 0x100>; - interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c1: i2c@20010000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20010000 0x00 0x100>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 103 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c2: i2c@20020000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20020000 0x00 0x100>; - interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 104 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_i2c3: i2c@20030000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x20030000 0x00 0x100>; - interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 2>; - clock-names = "fck"; - status = "disabled"; - }; - - main_spi0: spi@20100000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x20100000 0x00 0x400>; - interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 141 0>; - status = "disabled"; - }; - - main_spi1: spi@20110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20110000 0x00 0x400>; - interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 142 0>; - status = "disabled"; - }; - - main_spi2: spi@20120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x20120000 0x00 0x400>; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 143 0>; - status = "disabled"; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <3>; - ti,interrupt-ranges = <0 32 16>; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <190>, <191>, <192>, - <193>, <194>, <195>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <87>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 77 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <180>, <181>, <182>, - <183>, <184>, <185>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <88>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 78 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - sdhci1: mmc@fa00000 { - compatible = "ti,am62-sdhci"; - reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; - clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; - no-1-8-v; - status = "disabled"; - }; - - usbss0: dwc3-usb@f900000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>; - clocks = <&k3_clks 161 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb0: usb@31000000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31000000 0x00 0x50000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: dwc3-usb@f910000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; - clocks = <&k3_clks 162 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb1: usb@31100000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31100000 0x00 0x50000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - - fss: bus@fc00000 { - compatible = "simple-bus"; - reg = <0x00 0x0fc00000 0x00 0x70000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - ospi0: spi@fc40000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x0fc40000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 75 7>; - assigned-clocks = <&k3_clks 75 7>; - assigned-clock-parents = <&k3_clks 75 8>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cpsw3g: ethernet@8000000 { - compatible = "ti,am642-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x8000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; - clocks = <&k3_clks 13 0>; - assigned-clocks = <&k3_clks 13 3>; - assigned-clock-parents = <&k3_clks 13 11>; - clock-names = "fck"; - power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - - dmas = <&main_pktdma 0xc600 15>, - <&main_pktdma 0xc601 15>, - <&main_pktdma 0xc602 15>, - <&main_pktdma 0xc603 15>, - <&main_pktdma 0xc604 15>, - <&main_pktdma 0xc605 15>, - <&main_pktdma 0xc606 15>, - <&main_pktdma 0xc607 15>, - <&main_pktdma 0x4600 15>; - dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", - "tx7", "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel 1>; - mac-address = [00 00 00 00 00 00]; - ti,syscon-efuse = <&wkup_conf 0x200>; - }; - - cpsw_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - phys = <&phy_gmii_sel 2>; - mac-address = [00 00 00 00 00 00]; - }; - }; - - cpsw3g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 13 0>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 13 3>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - hwspinlock: spinlock@2a000000 { - compatible = "ti,am64-hwspinlock"; - reg = <0x00 0x2a000000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@29000000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29000000 0x00 0x200>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - mailbox0_cluster1: mailbox@29010000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29010000 0x00 0x200>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - mailbox0_cluster2: mailbox@29020000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29020000 0x00 0x200>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - mailbox0_cluster3: mailbox@29030000 { - compatible = "ti,am64-mailbox"; - reg = <0x00 0x29030000 0x00 0x200>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - }; - - main_mcan0: can@20701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x20701000 0x00 0x200>, - <0x00 0x20708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_rti0: watchdog@e000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e000000 0x00 0x100>; - clocks = <&k3_clks 125 0>; - power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 125 0>; - assigned-clock-parents = <&k3_clks 125 2>; - }; - - main_rti1: watchdog@e010000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e010000 0x00 0x100>; - clocks = <&k3_clks 126 0>; - power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 126 0>; - assigned-clock-parents = <&k3_clks 126 2>; - }; - - main_rti2: watchdog@e020000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e020000 0x00 0x100>; - clocks = <&k3_clks 127 0>; - power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 127 0>; - assigned-clock-parents = <&k3_clks 127 2>; - }; - - main_rti3: watchdog@e030000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e030000 0x00 0x100>; - clocks = <&k3_clks 128 0>; - power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 128 0>; - assigned-clock-parents = <&k3_clks 128 2>; - }; - - main_rti4: watchdog@e040000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x0e040000 0x00 0x100>; - clocks = <&k3_clks 205 0>; - power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 205 0>; - assigned-clock-parents = <&k3_clks 205 2>; - }; - - epwm0: pwm@23000000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23000000 0x00 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm1: pwm@23010000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23010000 0x00 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - epwm2: pwm@23020000 { - compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x23020000 0x00 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap0: pwm@23100000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23100000 0x00 0x100>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 51 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap1: pwm@23110000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23110000 0x00 0x100>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 52 0>; - clock-names = "fck"; - status = "disabled"; - }; - - ecap2: pwm@23120000 { - compatible = "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x00 0x23120000 0x00 0x100>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 53 0>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp0: audio-controller@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b00000 0x00 0x2000>, - <0x00 0x02b08000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 190 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 190 0>; - assigned-clock-parents = <&k3_clks 190 2>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp1: audio-controller@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b10000 0x00 0x2000>, - <0x00 0x02b18000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 191 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 191 0>; - assigned-clock-parents = <&k3_clks 191 2>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp2: audio-controller@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x00 0x02b20000 0x00 0x2000>, - <0x00 0x02b28000 0x00 0x400>; - reg-names = "mpu", "dat"; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 192 0>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 192 0>; - assigned-clock-parents = <&k3_clks 192 2>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi deleted file mode 100644 index a6d16a94088..00000000000 --- a/arch/arm/dts/k3-am62a-mcu.dtsi +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM625 SoC Family MCU Domain peripherals - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu { - mcu_pmx0: pinctrl@4084000 { - compatible = "pinctrl-single"; - reg = <0x00 0x04084000 0x00 0x88>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - status = "disabled"; - }; - - /* - * The MCU domain timer interrupts are routed only to the ESM module, - * and not currently available for Linux. The MCU domain timers are - * of limited use without interrupts, and likely reserved by the ESM. - */ - mcu_timer0: timer@4800000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4800000 0x00 0x400>; - clocks = <&k3_clks 35 2>; - clock-names = "fck"; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer1: timer@4810000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4810000 0x00 0x400>; - clocks = <&k3_clks 48 2>; - clock-names = "fck"; - power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer2: timer@4820000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4820000 0x00 0x400>; - clocks = <&k3_clks 49 2>; - clock-names = "fck"; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_timer3: timer@4830000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x4830000 0x00 0x400>; - clocks = <&k3_clks 50 2>; - clock-names = "fck"; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - status = "reserved"; - }; - - mcu_uart0: serial@4a00000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x04a00000 0x00 0x100>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_i2c0: i2c@4900000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x04900000 0x00 0x100>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 2>; - clock-names = "fck"; - status = "disabled"; - }; - - mcu_spi0: spi@4b00000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x04b00000 0x00 0x400>; - interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 147 0>; - status = "disabled"; - }; - - mcu_spi1: spi@4b10000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x04b10000 0x00 0x400>; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 148 0>; - status = "disabled"; - }; - - mcu_gpio_intr: interrupt-controller@4210000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x04210000 0x00 0x200>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <5>; - ti,interrupt-ranges = <0 104 4>; - }; - - mcu_gpio0: gpio@4201000 { - compatible = "ti,am64-gpio", "ti,keystone-gpio"; - reg = <0x00 0x04201000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&mcu_gpio_intr>; - interrupts = <30>, <31>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <24>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 79 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_rti0: watchdog@4880000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x04880000 0x00 0x100>; - clocks = <&k3_clks 131 0>; - power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 131 0>; - assigned-clock-parents = <&k3_clks 131 2>; - /* Tightly coupled to M4F */ - status = "reserved"; - }; - - mcu_mcan0: can@4e08000 { - compatible = "bosch,m_can"; - reg = <0x00 0x4e08000 0x00 0x200>, - <0x00 0x4e00000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@4e18000 { - compatible = "bosch,m_can"; - reg = <0x00 0x4e18000 0x00 0x200>, - <0x00 0x4e10000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index ec3bf7ce913..2a8c260387b 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -144,7 +144,7 @@ #ifdef CONFIG_TARGET_AM62A7_A53_EVM -#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb" +#define SPL_AM62A7_SK_DTB "spl/dts/ti/k3-am62a7-sk.dtb" #define AM62A7_SK_DTB "u-boot.dtb" &binman { @@ -152,13 +152,108 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; + type = "blob-ext"; + optional; }; }; + ti-spl { insert-template = <&ti_spl_template>; fit { images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; dm { ti-secure { content = <&dm>; @@ -192,7 +287,8 @@ conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "dm", "spl", + "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; fdt = "fdt-0"; }; }; @@ -249,6 +345,44 @@ fit { images { + tifsstub-hs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; dm { ti-dm { filename = "ti-dm.bin"; @@ -272,7 +406,8 @@ conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "dm", "spl", + "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi deleted file mode 100644 index 85ce545633e..00000000000 --- a/arch/arm/dts/k3-am62a-thermal.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - main0_crit: main0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - main1_crit: main1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main2_thermal: main2-thermal { - polling-delay-passive = <250>; /* milliSeconds */ - polling-delay = <500>; /* milliSeconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - main2_crit: main2-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi deleted file mode 100644 index 4e8279fa01e..00000000000 --- a/arch/arm/dts/k3-am62a-wakeup.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals - * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_wakeup { - wkup_conf: syscon@43000000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x43000000 0x20000>; - - chipid: chipid@14 { - compatible = "ti,am654-chipid"; - reg = <0x14 0x4>; - }; - }; - - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_i2c0: i2c@2b200000 { - compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2b200000 0x00 0x100>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 4>; - clock-names = "fck"; - status = "disabled"; - }; - - wkup_rtc0: rtc@2b1f0000 { - compatible = "ti,am62-rtc"; - reg = <0x00 0x2b1f0000 0x00 0x100>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; - clock-names = "vbus", "osc32k"; - power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; - wakeup-source; - status = "disabled"; - }; - - wkup_rti0: watchdog@2b000000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2b000000 0x00 0x100>; - clocks = <&k3_clks 132 0>; - power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 132 0>; - assigned-clock-parents = <&k3_clks 132 2>; - /* Used by DM firmware */ - status = "reserved"; - }; - - wkup_vtm0: temperature-sensor@b00000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0xb00000 0x00 0x400>, - <0x00 0xb01000 0x00 0x400>; - power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi deleted file mode 100644 index 61a210ecd5f..00000000000 --- a/arch/arm/dts/k3-am62a.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM62A SoC Family - * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 AM62A SoC"; - compatible = "ti,am62a7"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a53_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@f0000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ - <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ - <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ - <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ - <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ - <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ - <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ - <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ - <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ - <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ - <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ - <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ - <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ - <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ - <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ - <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ - <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ - <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ - <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */ - <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ - - /* MCU Domain Range */ - <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, - <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ - <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ - <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */ - <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */ - - /* Wakeup Domain Range */ - <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, - <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, - <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */ - <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */ - - cbass_mcu: bus@4000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ - <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ - <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ - <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ - <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ - }; - - cbass_wakeup: bus@b00000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ - <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ - <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ - <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ - }; - }; - - #include "k3-am62a-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-am62a-main.dtsi" -#include "k3-am62a-mcu.dtsi" -#include "k3-am62a-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts deleted file mode 100644 index 8f64ac2c756..00000000000 --- a/arch/arm/dts/k3-am62a7-sk.dts +++ /dev/null @@ -1,546 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * AM62A SK: https://www.ti.com/lit/zip/sprr459 - * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "k3-am62a7.dtsi" - -/ { - compatible = "ti,am62a7-sk", "ti,am62a7"; - model = "Texas Instruments AM62A7 SK"; - - aliases { - serial0 = &wkup_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - mmc1 = &sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; - }; - - vmain_pd: regulator-0 { - /* TPS25750 PD CONTROLLER OUTPUT */ - compatible = "regulator-fixed"; - regulator-name = "vmain_pd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_5v0: regulator-1 { - /* Output of TPS63070 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_main: regulator-2 { - /* output of LM5141-Q1 */ - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_main"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS22918DBVR */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - }; - - vcc_3v3_sys: regulator-4 { - /* output of TPS222965DSGT */ - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_main>; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&usr_led_pins_default>; - - led-0 { - label = "am62a-sk:green:heartbeat"; - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; - }; - - tlv320_mclk: clk-0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12288000>; - }; - - codec_audio: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM62Ax-SKEVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In", - "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In", - "MIC3R", "Microphone Jack", - "Microphone Jack", "Mic Bias"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&tlv320_mclk>; - }; - }; -}; - -&mcu_pmx0 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ - AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ - AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ - AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ - >; - }; -}; - -/* WKUP UART0 is used for DM firmware logs */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; - status = "reserved"; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ - AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ - AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ - AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ - AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ - AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ - AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ - >; - }; - - main_i2c2_pins_default: main-i2c2-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ - AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ - AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ - AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ - AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ - AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ - AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ - AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ - >; - }; - - usr_led_pins_default: usr-led-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ - >; - }; - - main_usb1_pins_default: main-usb1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ - >; - }; - - main_mdio1_pins_default: main-mdio1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ - AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ - >; - }; - - main_rgmii1_pins_default: main-rgmii1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ - AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ - AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */ - AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */ - AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */ - AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */ - AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */ - AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */ - AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */ - AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */ - AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ - AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ - >; - }; - - main_mcasp1_pins_default: main-mcasp1-default-pins { - pinctrl-single,pins = < - AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */ - AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */ - AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */ - AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */ - >; - }; -}; - -&mcu_pmx0 { - status = "okay"; - - pmic_irq_pins_default: pmic-irq-default-pins { - pinctrl-single,pins = < - AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ - >; - }; -}; - -&mcu_gpio0 { - status = "okay"; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - typec_pd0: usb-power-controller@3f { - compatible = "ti,tps6598x"; - reg = <0x3f>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - self-powered; - data-role = "dual"; - power-role = "sink"; - port { - usb_con_hs: endpoint { - remote-endpoint = <&usb0_hs_ep>; - }; - }; - }; - }; - - tps659312: pmic@48 { - compatible = "ti,tps6593-q1"; - reg = <0x48>; - ti,primary-pmic; - system-power-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins_default>; - interrupt-parent = <&mcu_gpio0>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - - buck123-supply = <&vcc_3v3_sys>; - buck4-supply = <&vcc_3v3_sys>; - buck5-supply = <&vcc_3v3_sys>; - ldo1-supply = <&vcc_3v3_sys>; - ldo2-supply = <&vcc_3v3_sys>; - ldo3-supply = <&buck5>; - ldo4-supply = <&vcc_3v3_sys>; - - regulators { - buck123: buck123 { - regulator-name = "vcc_core"; - regulator-min-microvolt = <715000>; - regulator-max-microvolt = <895000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4: buck4 { - regulator-name = "vcc_1v1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: buck5 { - regulator-name = "vcc_1v8_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: ldo1 { - regulator-name = "vddshv5_sdio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: ldo2 { - regulator-name = "vpp_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: ldo3 { - regulator-name = "vcc_0v85"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: ldo4 { - regulator-name = "vdda_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <100000>; - - exp1: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", - "BT_EN_SOC", "MMC1_SD_EN", - "VPP_EN", "EXP_PS_3V3_En", - "EXP_PS_5V0_En", "EXP_HAT_DETECT", - "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", - "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", - "GPIO_HDMI_RSTn", "CSI_GPIO0", - "CSI_GPIO1", "WLAN_ALERTn", - "HDMI_INTn", "TEST_GPIO2", - "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", - "MCASP1_FET_SEL", "UART1_FET_SEL", - "PD_I2C_IRQ", "IO_EXP_TEST_LED"; - }; - - tlv320aic3106: audio-codec@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - ai3x-micbias-vg = <1>; /* 2.0V */ - - /* Regulators */ - AVDD-supply = <&vcc_3v3_sys>; - IOVDD-supply = <&vcc_3v3_sys>; - DRVDD-supply = <&vcc_3v3_sys>; - DVDD-supply = <&buck5>; - }; -}; - -&sdhci1 { - /* SD/MMC */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_gpio0 { - status = "okay"; -}; - -&main_gpio1 { - status = "okay"; -}; - -&main_gpio_intr { - status = "okay"; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -/* Main UART1 is used for TIFS firmware logs */ -&main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; - status = "reserved"; -}; - -&usbss0 { - status = "okay"; - ti,vbus-divider; -}; - -&usb0 { - usb-role-switch; - - port { - usb0_hs_ep: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; -}; - -&usbss1 { - status = "okay"; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&main_usb1_pins_default>; -}; - -&cpsw3g { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default>; -}; - -&cpsw_port1 { - status = "okay"; - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - status = "disabled"; -}; - -&cpsw3g_mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&mcasp1 { - status = "okay"; - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&main_mcasp1_pins_default>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 0 2 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi index 58f1c43edcf..f86a23404e6 100644 --- a/arch/arm/dts/k3-am62a7.dtsi +++ b/arch/arm/dts/k3-am62a7.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A7 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/zip/spruj16 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index dea14945bf5..2177d5428d4 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -59,6 +59,17 @@ }; }; +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See am62px_evm.h +#define AM62PX_SK_TIBOOT3_IMAGE_GUID_STR "b08471b7-be2d-4489-87a1-cab28a0cf743" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM62PX_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + #endif /* CONFIG_TARGET_AM62P5_R5_EVM */ #if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM) @@ -72,7 +83,45 @@ blob-ext { filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; ti-spl { @@ -80,6 +129,31 @@ fit { images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; dm { ti-secure { content = <&dm>; @@ -116,7 +190,8 @@ conf-0 { description = "k3-am62px-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "dm", "spl", + "tifsstub-hs", "tifsstub-fs"; fdt = "fdt-0"; }; }; @@ -170,4 +245,22 @@ }; }; +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See am62px_evm.h +#define AM62PX_SK_SPL_IMAGE_GUID_STR "d02ed781-6d71-4c1a-a999-3c6a41c36324" +#define AM62PX_SK_UBOOT_IMAGE_GUID_STR "7e6aea51-965c-44ab-b388-daeb03b54f66" + +&capsule_tispl { + efi-capsule { + image-guid = AM62PX_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM62PX_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif /* CONFIG_TARGET_AM62P5_A53_EVM */ diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi deleted file mode 100644 index 19f57ead4eb..00000000000 --- a/arch/arm/dts/k3-am62x-sk-common.dtsi +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common dtsi for AM62x SK and derivatives - * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "k3-am625.dtsi" - -/ { - aliases { - serial2 = &main_uart0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - spi0 = &ospi0; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - usb0 = &usb0; - usb1 = &usb1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - bootph-pre-ram; - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@9ca00000 { - compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x00>; - pmsg-size = <0x8000>; - }; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&usr_led_pins_default>; - - led-0 { - label = "am62-sk:green:heartbeat"; - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; - }; - - tlv320_mclk: clk-0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12288000>; - }; - - codec_audio: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM62x-SKEVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line In", - "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In", - "MIC3R", "Microphone Jack", - "Microphone Jack", "Mic Bias"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&tlv320_mclk>; - }; - }; - - hdmi0: connector-hdmi { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&sii9022_out>; - }; - }; - }; -}; - -&main_pmx0 { - /* First pad number is ALW package and second is AMC package */ - main_uart0_pins_default: main-uart0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - bootph-pre-ram; - pinctrl-single,pins = < - AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ - AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ - AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */ - AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ - AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ - AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ - >; - }; - - main_i2c2_pins_default: main-i2c2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ - AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - main_mmc0_pins_default: main-mmc0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ - AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ - >; - }; - - usr_led_pins_default: usr-led-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ - >; - }; - - main_mdio1_pins_default: main-mdio1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ - >; - }; - - main_rgmii1_pins_default: main-rgmii1-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */ - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */ - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */ - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */ - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */ - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */ - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */ - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */ - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */ - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ - >; - }; - - main_usb1_pins_default: main-usb1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ - >; - }; - - main_mcasp1_pins_default: main-mcasp1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ - AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ - AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */ - AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ - >; - }; - - main_dss0_pins_default: main-dss0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ - AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ - AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ - AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ - AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ - AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ - AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ - AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ - AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ - AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ - AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ - AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ - AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ - AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ - AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ - AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ - AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ - AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ - AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ - AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ - AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ - AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ - AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ - AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ - AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ - AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ - AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ - AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ - >; - }; -}; - -&mcu_pmx0 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - bootph-pre-ram; - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ - AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ - AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */ - AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ - >; - }; -}; - -&wkup_uart0 { - /* WKUP UART0 is used by DM firmware */ - bootph-pre-ram; - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&main_uart0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - /* Main UART1 is used by TIFS firmware */ - bootph-pre-ram; - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T or M24512-DFMC6TG */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; - - typec_pd0: tps6598x@3f { - compatible = "ti,tps6598x"; - reg = <0x3f>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - self-powered; - data-role = "dual"; - power-role = "sink"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usb_con_hs: endpoint { - remote-endpoint = <&usb0_hs_ep>; - }; - }; - }; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <100000>; - - tlv320aic3106: audio-codec@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - ai3x-micbias-vg = <1>; /* 2.0V */ - - /* Regulators */ - AVDD-supply = <&vcc_3v3_sys>; - IOVDD-supply = <&vcc_3v3_sys>; - DRVDD-supply = <&vcc_3v3_sys>; - }; - - sii9022: bridge-hdmi@3b { - compatible = "sil,sii9022"; - reg = <0x3b>; - interrupt-parent = <&exp1>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - #sound-dai-cells = <0>; - sil,i2s-data-lanes = < 0 >; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sii9022_in: endpoint { - remote-endpoint = <&dpi1_out>; - }; - }; - - port@1 { - reg = <1>; - - sii9022_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&sdhci0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&sdhci1 { - /* SD/MMC */ - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&cpsw3g { - bootph-all; - pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default>; -}; - -&cpsw_port1 { - bootph-all; - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw3g_mdio { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default>; - - cpsw3g_phy0: ethernet-phy@0 { - bootph-all; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&usbss0 { - status = "okay"; - ti,vbus-divider; -}; - -&usbss1 { - status = "okay"; - ti,vbus-divider; -}; - -&usb0 { - #address-cells = <1>; - #size-cells = <0>; - usb-role-switch; - - port@0 { - reg = <0>; - usb0_hs_ep: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&main_usb1_pins_default>; -}; - -&mcasp1 { - status = "okay"; - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&main_mcasp1_pins_default>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 0 2 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&dss { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_dss0_pins_default>; -}; - -&dss_ports { - /* VP2: DPI Output */ - port@1 { - reg = <1>; - - dpi1_out: endpoint { - remote-endpoint = <&sii9022_in>; - }; - }; -}; diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi index 4677c35e2d9..8f3c3a185ae 100644 --- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -115,6 +115,32 @@ bootph-all; flash@0 { bootph-all; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00000 0x80000>; + }; + partition@80000 { + label = "ospi.tispl"; + reg = <0x080000 0x200000>; + }; + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + }; }; }; diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index 37817ba60d2..f768c4d946d 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -114,6 +114,17 @@ }; }; +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See am64x_evm.h +#define AM64X_SK_TIBOOT3_IMAGE_GUID_STR "ede0a0d5-9116-4bfb-aa54-09e97b5afe1a" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM64X_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + #endif #ifdef CONFIG_TARGET_AM642_A53_EVM @@ -373,4 +384,23 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See am64x_evm.h +#define AM64X_SK_SPL_IMAGE_GUID_STR "77678f5c-64d4-4910-ad75-52c9d95cdb1d" +#define AM64X_SK_UBOOT_IMAGE_GUID_STR "c6ad43a9-7d31-4f5d-83e9-b8efecae05bf" + +&capsule_tispl { + efi-capsule { + image-guid = AM64X_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM64X_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index b8fc62f0dd1..4b8d73a92d6 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -19,10 +19,14 @@ &cbass_mcu_wakeup { bootph-all; +}; + +&wkup_conf { + bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -34,14 +38,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; @@ -129,3 +125,26 @@ dr_mode = "peripheral"; bootph-all; }; + +#ifdef CONFIG_TARGET_J721S2_A72_EVM + +#define SPL_AM68_SK_DTB "spl/dts/ti/k3-am68-sk-base-board.dtb" +#define AM68_SK_DTB "u-boot.dtb" + +&spl_j721s2_evm_dtb { + filename = SPL_AM68_SK_DTB; +}; + +&j721s2_evm_dtb { + filename = AM68_SK_DTB; +}; + +&spl_j721s2_evm_dtb_unsigned { + filename = SPL_AM68_SK_DTB; +}; + +&j721s2_evm_dtb_unsigned { + filename = AM68_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts deleted file mode 100644 index 1e1a82f9d2b..00000000000 --- a/arch/arm/dts/k3-am68-sk-base-board.dts +++ /dev/null @@ -1,611 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * - * Base Board: https://www.ti.com/lit/zip/SPRR463 - */ - -/dts-v1/; - -#include "k3-am68-sk-som.dtsi" -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy.h> - -#include "k3-serdes.h" - -/ { - compatible = "ti,am68-sk", "ti,j721s2"; - model = "Texas Instruments AM68 SK"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc1 = &main_sdhci1; - can0 = &mcu_mcan0; - can1 = &mcu_mcan1; - can2 = &main_mcan6; - can3 = &main_mcan7; - }; - - vusb_main: regulator-vusb-main5v0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb-main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-vsys3v3 { - /* Output of LM5141 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-tlv71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - vsys_io_1v8: regulator-vsys-io-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vsys_io_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_io_1v2: regulator-vsys-io-1v2 { - compatible = "regulator-fixed"; - regulator-name = "vsys_io_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver3: can-phy2 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - transceiver4: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; - - connector-hdmi { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins_default>; - ddc-i2c-bus = <&mcu_i2c1>; - /* HDMI_HPD */ - hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - bridge-dvi { - compatible = "ti,tfp410"; - /* HDMI_PDn */ - powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; - ti,deskew = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi_out0>; - pclk-sample = <1>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_pmx0 { - main_uart8_pins_default: main-uart8-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_mcan6_pins_default: main-mcan6-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ - J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ - >; - }; - - main_mcan7_pins_default: main-mcan7-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ - J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ - J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ - >; - }; - - rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ - J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ - J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ - J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ - J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ - J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ - J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ - J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ - J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ - J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ - J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ - J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ - J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ - J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ - >; - }; - - dss_vout0_pins_default: dss-vout0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ - J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ - J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ - J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ - J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ - J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ - J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ - J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ - J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ - J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ - J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ - J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ - J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ - J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ - J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ - J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ - J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ - J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ - J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ - J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ - J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ - J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ - J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ - J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ - J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ - J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ - >; - }; - - hdmi_hpd_pins_default: hdmi-hpd-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ - >; - }; -}; - -&wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ - >; - }; - - mcu_i2c0_pins_default: mcu-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ - >; - }; - - mcu_i2c1_pins_default: mcu-i2c1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ - J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ - J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ - J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ - J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ - J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ - J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ - >; - }; -}; - -&wkup_pmx3 { - mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ - >; - }; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio0_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; -}; - -&wkup_uart0 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; - /* Shared with TFA on this platform */ - power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = " ", " ", " ", " ", " ", - "BOARDID_EEPROM_WP", "CAN_STB", " ", - "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", - "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; - }; -}; - -&main_i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c4_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c0_pins_default>; - clock-frequency = <400000>; -}; - -&mcu_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c1_pins_default>; - /* i2c1 is used for DVI DDC, so we need to use 100kHz */ - clock-frequency = <100000>; - - exp2: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "HDMI_PDn","HDMI_LS_OE", - "DP0_3V3_EN","eDP_ENABLE"; - }; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan6_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan7_pins_default>; - phys = <&transceiver4>; -}; - -&dss { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout0_pins_default>; - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - assigned-clocks = <&k3_clks 158 2>, - <&k3_clks 158 5>, - <&k3_clks 158 14>, - <&k3_clks 158 18>; - assigned-clock-parents = <&k3_clks 158 3>, - <&k3_clks 158 7>, - <&k3_clks 158 16>, - <&k3_clks 158 22>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - /* HDMI */ - port@1 { - reg = <1>; - - dpi_out0: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; -}; - -&serdes_ln_ctrl { - idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>, - <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - status = "okay"; - - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_usb_link: phy@2 { - status = "okay"; - reg = <2>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz0 3>; - }; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&usb_serdes_mux { - idle-states = <0>; /* USB0 to SERDES lane 2 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes0_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index 695aadc287b..3b2d7af2e52 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -9,77 +9,4 @@ #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" - -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <2000000000>; - ti,sci = <&sms>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - clock-frequency = <250000000>; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; -}; - -&secure_proxy_sa3 { - bootph-pre-ram; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; -}; - -&sms { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi deleted file mode 100644 index 20861a0a46b..00000000000 --- a/arch/arm/dts/k3-am68-sk-som.dtsi +++ /dev/null @@ -1,259 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721s2.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - memory@80000000 { - device_type = "memory"; - /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; diff --git a/arch/arm/dts/k3-binman-capsule-r5.dtsi b/arch/arm/dts/k3-binman-capsule-r5.dtsi new file mode 100644 index 00000000000..959ceb7479d --- /dev/null +++ b/arch/arm/dts/k3-binman-capsule-r5.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&binman { + capsule_tiboot3: capsule-tiboot3 { + filename = "tiboot3-capsule.bin"; + efi-capsule { + image-index = <0x1>; + image-guid = "00000000-0000-0000-0000-000000000000"; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "tiboot3.bin"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-binman-capsule.dtsi b/arch/arm/dts/k3-binman-capsule.dtsi new file mode 100644 index 00000000000..17e83c9fa44 --- /dev/null +++ b/arch/arm/dts/k3-binman-capsule.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&binman { + capsule_tispl: capsule-tispl { + filename = "tispl-capsule.bin"; + efi-capsule { + image-index = <0x2>; + image-guid = "00000000-0000-0000-0000-000000000000"; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "tispl.bin"; + }; + }; + }; +}; + +&binman { + capsule_uboot: capsule-uboot { + filename = "uboot-capsule.bin"; + efi-capsule { + image-index = <0x3>; + image-guid = "00000000-0000-0000-0000-000000000000"; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "u-boot.img"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 06db8659876..ef7d4594f69 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -48,6 +48,52 @@ }; &binman { + tiboot3-j7200-hs-evm.bin { + filename = "tiboot3-j7200-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_sr1>, <&ti_fs_enc_sr1>, <&combined_tifs_cfg_sr1>, + <&combined_dm_cfg_sr1>, <&sysfw_inner_cert_sr1>; + combined; + dm-data; + core-opts = <2>; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_sr1>; + content-sysfw = <&ti_fs_enc_sr1>; + content-sysfw-data = <&combined_tifs_cfg_sr1>; + content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>; + content-dm-data = <&combined_dm_cfg_sr1>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_sr1: u-boot-spl { + no-expanded; + }; + ti_fs_enc_sr1: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_sr1: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_sr1: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_sr1: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { tiboot3-j7200_sr2-hs-evm.bin { filename = "tiboot3-j7200_sr2-hs-evm.bin"; ti-secure-rom { @@ -93,6 +139,53 @@ }; &binman { + tiboot3-j7200-hs-fs-evm.bin { + filename = "tiboot3-j7200-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs_sr1>, <&ti_fs_enc_fs_sr1>, + <&combined_tifs_cfg_fs_sr1>, <&combined_dm_cfg_fs_sr1>, + <&sysfw_inner_cert_fs_sr1>; + combined; + dm-data; + core-opts = <2>; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs_sr1>; + content-sysfw = <&ti_fs_enc_fs_sr1>; + content-sysfw-data = <&combined_tifs_cfg_fs_sr1>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>; + content-dm-data = <&combined_dm_cfg_fs_sr1>; + load = <0x41c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x7f000>; + load-dm-data = <0x41c80000>; + }; + u_boot_spl_fs_sr1: u-boot-spl { + no-expanded; + }; + ti_fs_enc_fs_sr1: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + sysfw_inner_cert_fs_sr1: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + combined_dm_cfg_fs_sr1: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { tiboot3-j7200_sr2-hs-fs-evm.bin { filename = "tiboot3-j7200_sr2-hs-fs-evm.bin"; ti-secure-rom { @@ -180,7 +273,7 @@ #ifdef CONFIG_TARGET_J7200_A72_EVM -#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb" +#define SPL_J7200_EVM_DTB "spl/dts/ti/k3-j7200-common-proc-board.dtb" #define J7200_EVM_DTB "u-boot.dtb" &binman { @@ -188,6 +281,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 485f17c5f06..045ef170e17 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -26,8 +26,12 @@ &cbass_mcu_wakeup { bootph-all; - chipid@43000014 { + wkup_conf: bus@43000000 { bootph-all; + + chipid: chipid@14 { + bootph-all; + }; }; }; @@ -40,14 +44,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts deleted file mode 100644 index cee2b4b0eb8..00000000000 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ /dev/null @@ -1,396 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200-som-p0.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy.h> - -#include "k3-serdes.h" - -/ { - compatible = "ti,j7200-evm", "ti,j7200"; - model = "Texas Instruments J7200 EVM"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial5 = &main_uart3; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: gpio-regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; -}; - -&wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ - >; - }; -}; - -&wkup_pmx2 { - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ - >; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ - J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ - J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ - J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ - J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ - >; - }; - - main_uart3_pins_default: main-uart3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ - J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ - J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ - J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ - J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ - J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ - J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ - J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ - J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ - >; - }; -}; - -&main_pmx1 { - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; - clock-frequency = <96000000>; -}; - -&main_uart0 { - status = "okay"; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - status = "okay"; - /* Default pinmux */ - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_uart2 { - /* MAIN UART 2 is used by R5F firmware */ - status = "reserved"; -}; - -&main_uart3 { - /* Shared with MCAN Interface */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart3_pins_default>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_gpio_pins_default>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -/* - * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be - * swapped on the CPB. - * - * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. - * The i2c1 of the CPB (as it is labeled) is not connected to j7200. - */ -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", - "UB926_LOCK", "UB926_PWR_SW_CNTRL", - "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; - }; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&serdes_ln_ctrl { - idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, - <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - }; - - serdes0_qsgmii_link: phy@1 { - reg = <2>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_QSGMII>; - resets = <&serdes_wiz0 3>; - }; -}; - -&pcie1_rc { - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie1_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi deleted file mode 100644 index 264913f8328..00000000000 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ /dev/null @@ -1,1284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family Main Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - serdes_refclk: serdes-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x100000>; - - atf-sram@0 { - reg = <0x00 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ - }; - - cpsw0_phy_gmii_sel: phy@4044 { - compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; - ti,qsgmii-main-ports = <1>; - reg = <0x4044 0x10>; - #phy-cells = <1>; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <199>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x310e0000 0x00 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>, - <0x00 0x31080000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x310d0000 0x00 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - cpsw0: ethernet@c000000 { - compatible = "ti,j7200-cpswxg-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0xc000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; - clocks = <&k3_clks 19 33>; - clock-names = "fck"; - power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xca00>, - <&main_udmap 0xca01>, - <&main_udmap 0xca02>, - <&main_udmap 0xca03>, - <&main_udmap 0xca04>, - <&main_udmap 0xca05>, - <&main_udmap 0xca06>, - <&main_udmap 0xca07>, - <&main_udmap 0x4a00>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - cpsw0_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - status = "disabled"; - }; - - cpsw0_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - status = "disabled"; - }; - - cpsw0_port3: port@3 { - reg = <3>; - ti,mac-only; - label = "port3"; - status = "disabled"; - }; - - cpsw0_port4: port@4 { - reg = <4>; - ti,mac-only; - label = "port4"; - status = "disabled"; - }; - }; - - cpsw5g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 19 33>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 19 16>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x0 0x104200 0x0 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x000001ff>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x0 0x104280 0x0 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x10c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c11c 0x00 0xc>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2000000 0x00 0x100>; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 1>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2010000 0x00 0x100>; - interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 1>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2020000 0x00 0x100>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 1>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2030000 0x00 0x100>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 1>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2040000 0x00 0x100>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 1>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2050000 0x00 0x100>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 1>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2060000 0x00 0x100>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 1>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - status = "disabled"; - }; - - serdes_wiz0: wiz@5060000 { - compatible = "ti,j721e-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <4>; - #reset-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; - - assigned-clocks = <&k3_clks 292 85>; - assigned-clock-parents = <&k3_clks 292 89>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_pll0_refclk"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_pll1_refclk"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 85>, <&serdes_refclk>; - clock-output-names = "wiz0_refclk_dig"; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 85>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - serdes0: serdes@5060000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&wiz0_pll0_refclk>; - clock-names = "refclk"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - cdns,no-bar-match-nbits = <64>; - vendor-id = <0x104c>; - device-id = <0xb00f>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - cdns,phyrst-a-enable; - }; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <145>, <146>, <147>, <148>, - <149>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00610000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <154>, <155>, <156>, <157>, - <158>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00620000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <163>, <164>, <165>, <166>, - <167>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00630000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <172>, <173>, <174>, <175>, - <176>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <69>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 266 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 267 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 268 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 269 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 270 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 271 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 272 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 273 1>; - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 49 1>; - assigned-clock-parents = <&k3_clks 49 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; - assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 51 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 51 1>; - assigned-clock-parents = <&k3_clks 51 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 52 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; - assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 53 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 53 1>; - assigned-clock-parents = <&k3_clks 53 2>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 54 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; - assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 55 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 55 1>; - assigned-clock-parents = <&k3_clks 55 2>; - power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 57 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; - assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 58 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 58 1>; - assigned-clock-parents = <&k3_clks 58 2>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 59 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; - assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; - power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 60 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 60 1>; - assigned-clock-parents = <&k3_clks 60 2>; - power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 62 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; - assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; - power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; - assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; - assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; - assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; - assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j7200-r5f"; - reg = <0x5c00000 0x00010000>, - <0x5c10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 245 1>; - firmware-name = "j7200-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j7200-r5f"; - reg = <0x5d00000 0x00008000>, - <0x5d10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 246 1>; - firmware-name = "j7200-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <656>, <657>; - }; -}; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi deleted file mode 100644 index 3fc588b848c..00000000000 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ /dev/null @@ -1,647 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_timer0: timer@40400000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer1: timer@40410000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; - assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer2: timer@40420000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer3: timer@40430000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; - assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer4: timer@40440000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer5: timer@40450000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; - assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer6: timer@40460000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer7: timer@40470000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; - assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer8: timer@40480000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_timer9: timer@40490000 { - status = "reserved"; - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; - assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x40f00000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x0 0x40f04200 0x0 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x0 0x40f04280 0x0 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; - status = "reserved"; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x34>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x8>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c068 0x00 0xec>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx3: pinctrl@4301c174 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c174 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 2>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42110000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <85>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42100000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <85>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>, - <0x00 0x28440000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", - "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x2a480000 0x0 0x80000>, - <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0x46000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 1>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 1>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 1>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 274 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 275 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 0>; - status = "disabled"; - }; - - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x47000000 0x00 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - }; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40200000 0x00 0x1000>; - interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j7200-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j7200-r5f"; - reg = <0x41000000 0x00010000>, - <0x41010000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <250>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 250 1>; - firmware-name = "j7200-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j7200-r5f"; - reg = <0x41400000 0x00008000>, - <0x41410000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <251>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 251 1>; - firmware-name = "j7200-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_crypto: crypto@40900000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; - dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, - <&mcu_udmap 0x7503>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@40910000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x40910000 0x00 0x7d>; - interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; /* Used by OP-TEE */ - }; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0x42040000 0x00 0x350>, - <0x00 0x42050000 0x00 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi deleted file mode 100644 index 5a300d4c8ba..00000000000 --- a/arch/arm/dts/k3-j7200-som-p0.dtsi +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x00 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a4000000 { - reg = <0x00 0xa4000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - >; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "hbmc.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "hbmc.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "hbmc.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "hbmc.env"; - reg = <0x700000 0x40000>; - }; - - partition@800000 { - label = "hbmc.rootfs"; - reg = <0x800000 0x3800000>; - }; - }; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp_som: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", - "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", - "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", - "GPIO_LIN_EN", "CAN_STB"; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x100000>; - }; - - partition@100000 { - label = "ospi.tispl"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "ospi.u-boot"; - reg = <0x300000 0x400000>; - }; - - partition@700000 { - label = "ospi.env"; - reg = <0x700000 0x40000>; - }; - - partition@740000 { - label = "ospi.env.backup"; - reg = <0x740000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j7200-thermal.dtsi b/arch/arm/dts/k3-j7200-thermal.dtsi deleted file mode 100644 index e7e3a643a6f..00000000000 --- a/arch/arm/dts/k3-j7200-thermal.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - mcu_thermal: mcu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup_crit: wkup-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - mpu_thermal: mpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu_crit: mpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - main_thermal: main-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - c7x_crit: c7x-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi deleted file mode 100644 index ef73e6d7e85..00000000000 --- a/arch/arm/dts/k3-j7200.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family - * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 J7200 SoC"; - compatible = "ti,j7200"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ - }; - }; - - #include "k3-j7200-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j7200-main.dtsi" -#include "k3-j7200-mcu-wakeup.dtsi" diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index e202ae16644..884f44239e1 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -351,4 +351,27 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See beagleboneai64.h +#define BEAGLEBONEAI64_SPL_IMAGE_GUID_STR "83447222-1e26-40cd-a395-b7de0957e875" +#define BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR "4249ff77-c17d-4eb7-a1db-45aa9887d49e" + +&capsule_tispl { + efi-capsule { + image-guid = BEAGLEBONEAI64_SPL_IMAGE_GUID_STR; + + blob { + filename = "tispl.bin_unsigned"; + }; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = BEAGLEBONEAI64_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 75a6e9599b9..0d607296f0e 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -130,6 +130,94 @@ }; &binman { + tiboot3-j721e_sr1_1-hs-fs-evm.bin { + filename = "tiboot3-j721e_sr1_1-hs-fs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_fs_sr1_1>; + core = "public"; + core-opts = <2>; + load = <CONFIG_SPL_TEXT_BASE>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_fs_sr1_1: u-boot-spl { + no-expanded; + }; + }; + sysfw_fs_sr1_1 { + filename = "sysfw.bin_fs_sr1_1"; + ti-fs-cert-fs.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e-hs-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb_fs_sr1_1 { + filename = "sysfw-j721e_sr1_1-hs-fs-evm.itb"; + fit { + description = "SYSFW and Config fragments"; + #address-cells = <1>; + images { + sysfw.bin { + description = "sysfw"; + type = "firmware"; + arch = "arm"; + compression = "none"; + blob-ext { + filename = "sysfw.bin_fs_sr1_1"; + }; + }; + board-cfg.bin { + description = "board-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + board-cfg { + filename = "board-cfg.bin"; + type = "blob-ext"; + }; + + }; + pm-cfg.bin { + description = "pm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + pm-cfg { + filename = "pm-cfg.bin"; + type = "blob-ext"; + }; + }; + rm-cfg.bin { + description = "rm-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + rm-cfg { + filename = "rm-cfg.bin"; + type = "blob-ext"; + }; + }; + sec-cfg.bin { + description = "sec-cfg"; + type = "firmware"; + arch = "arm"; + compression = "none"; + sec-cfg { + filename = "sec-cfg.bin"; + type = "blob-ext"; + }; + }; + }; + }; + }; +}; + +&binman { tiboot3-j721e_sr2-hs-fs-evm.bin { filename = "tiboot3-j721e_sr2-hs-fs-evm.bin"; ti-secure-rom { @@ -207,21 +295,49 @@ }; }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See j721e_evm.h +#define J721E_SK_TIBOOT3_IMAGE_GUID_STR "e672b518-7cd7-4014-bd8d-40724d0ad4dc" +#define J721E_SK_SYSFW_IMAGE_GUID_STR "6fd10680-361b-431f-80aa-899455819e11" + +&capsule_tiboot3 { + efi-capsule { + image-guid = J721E_SK_TIBOOT3_IMAGE_GUID_STR; + }; +}; + +&binman { + capsule-sysfw { + filename = "sysfw-capsule.bin"; + efi-capsule { + image-index = <0x4>; + image-guid = J721E_SK_SYSFW_IMAGE_GUID_STR; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "sysfw.itb"; + }; + }; + }; +}; + #endif #ifdef CONFIG_TARGET_J721E_A72_EVM -#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb" -#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb" - +#define SPL_J721E_EVM_DTB "spl/dts/ti/k3-j721e-common-proc-board.dtb" #define J721E_EVM_DTB "u-boot.dtb" -#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb" &binman { ti-dm { filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { @@ -361,28 +477,13 @@ arch = "arm"; compression = "none"; ti-secure { - content = <&spl_j721e_evm_dtb>; + content = <&spl_j721e_dtb>; keyfile = "custMpk.pem"; }; - spl_j721e_evm_dtb: blob-ext { + spl_j721e_dtb: blob-ext { filename = SPL_J721E_EVM_DTB; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_j721e_sk_dtb>; - keyfile = "custMpk.pem"; - - }; - spl_j721e_sk_dtb: blob-ext { - filename = SPL_J721E_SK_DTB; - }; - }; }; configurations { @@ -394,13 +495,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -422,35 +516,17 @@ arch = "arm"; compression = "none"; ti-secure { - content = <&j721e_evm_dtb>; + content = <&j721e_dtb>; keyfile = "custMpk.pem"; }; - j721e_evm_dtb: blob-ext { + j721e_dtb: blob-ext { filename = J721E_EVM_DTB; }; hash { algo = "crc32"; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&j721e_sk_dtb>; - keyfile = "custMpk.pem"; - - }; - j721e_sk_dtb: blob-ext { - filename = J721E_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; }; configurations { @@ -462,13 +538,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; @@ -491,20 +560,10 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_j721e_dtb_unsigned: blob { filename = SPL_J721E_EVM_DTB; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_J721E_SK_DTB; - }; - }; }; configurations { @@ -516,13 +575,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -543,26 +595,13 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + j721e_dtb_unsigned: blob { filename = J721E_EVM_DTB; }; hash { algo = "crc32"; }; }; - - fdt-1 { - description = "k3-j721e-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = J721E_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; }; configurations { @@ -574,15 +613,27 @@ loadables = "uboot"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-j721e-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See j721e_evm.h +#define J721E_SK_SPL_IMAGE_GUID_STR "86f710ad-10cf-46ea-ac67-856ae06efad2" +#define J721E_SK_UBOOT_IMAGE_GUID_STR "81b58fb0-3b00-4add-a20a-c185bbaca1ed" + +&capsule_tispl { + efi-capsule { + image-guid = J721E_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = J721E_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index aa919b40702..1b119f27357 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -15,10 +15,10 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -30,14 +30,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts deleted file mode 100644 index fe5207ac7d8..00000000000 --- a/arch/arm/dts/k3-j721e-common-proc-board.dts +++ /dev/null @@ -1,976 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * - * Product Link: https://www.ti.com/tool/J721EXCPXEVM - */ - -/dts-v1/; - -#include "k3-j721e-som-p0.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> - -/ { - compatible = "ti,j721e-evm", "ti,j721e"; - model = "Texas Instruments J721e EVM"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial6 = &main_uart4; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; - - sw10: switch-10 { - label = "GPIO Key USER1"; - linux,code = <BTN_0>; - gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; - }; - - sw11: switch-11 { - label = "GPIO Key USER2"; - linux,code = <BTN_1>; - gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; - }; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LMS140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: gpio-regulator-TLV71033 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tlv71033"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - sound0: sound-0 { - compatible = "ti,j721e-cpb-audio"; - model = "j721e-cpb"; - - ti,cpb-mcasp = <&mcasp10>; - ti,cpb-codec = <&pcm3168a_1>; - - clocks = <&k3_clks 184 1>, - <&k3_clks 184 2>, <&k3_clks 184 4>, - <&k3_clks 157 371>, - <&k3_clks 157 400>, <&k3_clks 157 401>; - clock-names = "cpb-mcasp-auxclk", - "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", - "cpb-codec-scki", - "cpb-codec-scki-48000", "cpb-codec-scki-44100"; - }; - - transceiver1: can-phy0 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; - enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy1 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver3: can-phy2 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; - enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - }; - - transceiver4: can-phy3 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan2_gpio_pins_default>; - standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; - }; - - dp_pwr_3v3: regulator-dp-pwr { - compatible = "regulator-fixed"; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ - J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ - J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ - >; - }; - - main_uart2_pins_default: main-uart2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ - J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ - >; - }; - - main_uart4_pins_default: main-uart4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ - J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ - >; - }; - - sw10_button_pins_default: sw10-button-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ - >; - }; - - main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_i2c6_pins_default: main-i2c6-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ - J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ - >; - }; - - mcasp10_pins_default: mcasp10-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ - J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ - J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ - J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ - J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ - J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ - J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ - J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ - J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ - >; - }; - - audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ - >; - }; - - main_mcan0_pins_default: main-mcan0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ - J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ - >; - }; - - main_mcan2_pins_default: main-mcan2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ - J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ - >; - }; - - main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ - >; - }; -}; - -&wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - sw11_button_pins_default: sw11-button-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ - J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ - J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ - J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ - J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ - J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ - J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ - J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ - J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ - J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ - >; - }; - - wkup_gpio_pins_default: wkup-gpio-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart2_pins_default>; -}; - -&main_uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart4_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_gpio_pins_default>; -}; - -&main_gpio0 { - status = "okay"; -}; - -&main_gpio1 { - status = "okay"; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD/MMC */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&usb_serdes_mux { - idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ -}; - -&serdes_ln_ctrl { - idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, - <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,usb2-only; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qspi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "qspi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "qspi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "qspi.env"; - reg = <0x680000 0x20000>; - }; - - partition@6a0000 { - label = "qspi.env.backup"; - reg = <0x6a0000 0x20000>; - }; - - partition@6c0000 { - label = "qspi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "qspi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fe0000 { - label = "qspi.phypattern"; - reg = <0x3fe0000 0x20000>; - }; - }; - }; -}; - -&tscadc0 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - p09-hog { - /* P11 - MCASP/TRACE_MUX_S0 */ - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP/TRACE_MUX_S0"; - }; - - p10-hog { - /* P12 - MCASP/TRACE_MUX_S1 */ - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "MCASP/TRACE_MUX_S1"; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_exp4_pins_default>; - interrupt-parent = <&main_gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK2 pin as output */ - pinctrl-names = "default"; - pinctrl-0 = <&audi_ext_refclk2_pins_default>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - - #sound-dai-cells = <1>; - - reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; - - /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ - clocks = <&k3_clks 157 371>; - clock-names = "scki"; - - /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ - assigned-clocks = <&k3_clks 157 371>; - assigned-clock-parents = <&k3_clks 157 400>; - assigned-clock-rates = <24576000>; /* for 48KHz */ - - VDD1-supply = <&vsys_3v3>; - VDD2-supply = <&vsys_3v3>; - VCCAD1-supply = <&vsys_5v0>; - VCCAD2-supply = <&vsys_5v0>; - VCCDA1-supply = <&vsys_5v0>; - VCCDA2-supply = <&vsys_5v0>; - }; -}; - -&main_i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c6_pins_default>; - clock-frequency = <400000>; - - exp5: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - - assigned-clocks = <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* PLL19_HSDIV0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* PLL23_HSDIV0 */ -}; - -&dss_ports { - port { - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&mcasp10 { - status = "okay"; - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mcasp10_pins_default>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - auxclk-fs-ratio = <256>; - - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 1 1 1 - 2 2 2 0 - >; - tx-num-evt = <0>; - rx-num-evt = <0>; -}; - -&cmn_refclk1 { - clock-frequency = <100000000>; -}; - -&wiz0_pll1_refclk { - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz0_refclk_dig { - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz1_pll1_refclk { - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz1_refclk_dig { - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz2_pll1_refclk { - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&wiz2_refclk_dig { - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&cmn_refclk1>; -}; - -&serdes0 { - assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz0_pll1_refclk>; - - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz1_pll1_refclk>; - - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&serdes2 { - assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; - assigned-clock-parents = <&wiz2_pll1_refclk>; - - serdes2_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&pcie0_rc { - status = "okay"; - reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_rc { - status = "okay"; - reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&main_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan0_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan2_pins_default>; - phys = <&transceiver4>; -}; diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi deleted file mode 100644 index 746b9f8b1c6..00000000000 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ /dev/null @@ -1,2741 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/phy/phy-ti.h> -#include <dt-bindings/mux/mux.h> - -#include "k3-serdes.h" - -/ { - cmn_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - cmn_refclk1: clock-cmnrefclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x800000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ - idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, - <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; - }; - - cpsw0_phy_gmii_sel: phy@4044 { - compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; - ti,qsgmii-main-ports = <2>, <2>; - reg = <0x4044 0x20>; - #phy-cells = <1>; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; - - ehrpwm_tbclk: clock-controller@4140 { - compatible = "ti,am654-ehrpwm-tbclk"; - reg = <0x4140 0x18>; - #clock-cells = <1>; - }; - }; - - main_ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3000000 0x00 0x100>; - power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3010000 0x00 0x100>; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3020000 0x00 0x100>; - power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3030000 0x00 0x100>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3040000 0x00 0x100>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3050000 0x00 0x100>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <199>; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x0 0x310e0000 0x0 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&main_navss_intr>; - msi-controller; - #interrupt-cells = <0>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - smmu0: iommu@36600000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x36600000 0x0 0x100000>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "gerror"; - #iommu-cells = <1>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>, - <0x0 0x31080000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - cpsw0: ethernet@c000000 { - compatible = "ti,j721e-cpswxg-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0xc000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; - clocks = <&k3_clks 19 89>; - clock-names = "fck"; - power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xca00>, - <&main_udmap 0xca01>, - <&main_udmap 0xca02>, - <&main_udmap 0xca03>, - <&main_udmap 0xca04>, - <&main_udmap 0xca05>, - <&main_udmap 0xca06>, - <&main_udmap 0xca07>, - <&main_udmap 0x4a00>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - cpsw0_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - status = "disabled"; - }; - - cpsw0_port2: port@2 { - reg = <2>; - ti,mac-only; - label = "port2"; - status = "disabled"; - }; - - cpsw0_port3: port@3 { - reg = <3>; - ti,mac-only; - label = "port3"; - status = "disabled"; - }; - - cpsw0_port4: port@4 { - reg = <4>; - ti,mac-only; - label = "port4"; - status = "disabled"; - }; - - cpsw0_port5: port@5 { - reg = <5>; - ti,mac-only; - label = "port5"; - status = "disabled"; - }; - - cpsw0_port6: port@6 { - reg = <6>; - ti,mac-only; - label = "port6"; - status = "disabled"; - }; - - cpsw0_port7: port@7 { - reg = <7>; - ti,mac-only; - label = "port7"; - status = "disabled"; - }; - - cpsw0_port8: port@8 { - reg = <8>; - ti,mac-only; - label = "port8"; - status = "disabled"; - }; - }; - - cpsw9g_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 19 89>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 19 16>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x0 0x4e00000 0x0 0x1200>; - power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, - <&main_udmap 0x4001>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x0 0x4e10000 0x0 0x7d>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x2b4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x00 0x104200 0x00 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000007>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x00 0x104280 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - serdes_wiz0: wiz@5000000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; - assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5000000 0x0 0x5000000 0x10000>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 0>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz0_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes0: serdes@5000000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5000000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz0 0>; - reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, - <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz1: wiz@5010000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; - assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5010000 0x0 0x5010000 0x10000>; - - wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll0_refclk>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&k3_clks 293 0>; - }; - - wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz1_refclk_dig>; - #clock-cells = <0>; - }; - - wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz1_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes1: serdes@5010000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5010000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz1 0>; - reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, - <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz2: wiz@5020000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; - assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5020000 0x0 0x5020000 0x10000>; - - wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll0_refclk>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&k3_clks 294 0>; - }; - - wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz2_refclk_dig>; - #clock-cells = <0>; - }; - - wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz2_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes2: serdes@5020000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5020000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz2 0>; - reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, - <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - serdes_wiz3: wiz@5030000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; - assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5030000 0x0 0x5030000 0x10000>; - - wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll0_refclk>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll1_refclk>; - assigned-clock-parents = <&k3_clks 295 0>; - }; - - wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_refclk_dig>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz3_refclk_dig>; - #clock-cells = <0>; - }; - - wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz3_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes3: serdes@5030000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5030000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - resets = <&serdes_wiz3 0>; - reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, - <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", - "pll0_refclk", "pll1_refclk"; - }; - }; - - pcie0_rc: pcie@2900000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x10000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie2_rc: pcie@2920000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x20000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - pcie3_rc: pcie@2930000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x30000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - status = "disabled"; - }; - - serdes_wiz4: wiz@5050000 { - compatible = "ti,am64-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 297 9>; - assigned-clock-parents = <&k3_clks 297 10>; - assigned-clock-rates = <19200000>; - num-lanes = <4>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x05050000 0x00 0x05050000 0x010000>, - <0x0a030a00 0x00 0x0a030a00 0x40>; - - serdes4: serdes@5050000 { - /* - * Note: we also map DPTX PHY registers as the Torrent - * needs to manage those. - */ - compatible = "ti,j721e-serdes-10g"; - reg = <0x05050000 0x010000>, - <0x0a030a00 0x40>; /* DPTX PHY */ - reg-names = "torrent_phy", "dptx_phy"; - - resets = <&serdes_wiz4 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; - clock-names = "refclk"; - assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 297 9>, - <&k3_clks 297 9>, - <&k3_clks 297 9>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 49 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 49 1>; - assigned-clock-parents = <&k3_clks 49 2>; - power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 50 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; - assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; - power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 51 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 51 1>; - assigned-clock-parents = <&k3_clks 51 2>; - power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 52 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; - assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; - power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 53 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 53 1>; - assigned-clock-parents = <&k3_clks 53 2>; - power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 54 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; - assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; - power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 55 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 55 1>; - assigned-clock-parents = <&k3_clks 55 2>; - power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 57 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; - assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; - power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 58 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 58 1>; - assigned-clock-parents = <&k3_clks 58 2>; - power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 59 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; - assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; - power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 60 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 60 1>; - assigned-clock-parents = <&k3_clks 60 2>; - power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 62 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; - assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; - power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; - assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; - assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; - assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; - assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <256>, <257>, <258>, <259>, - <260>, <261>, <262>, <263>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <288>, <289>, <290>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00610000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <264>, <265>, <266>, <267>, - <268>, <269>, <270>, <271>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio3: gpio@611000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00611000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <292>, <293>, <294>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 108 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00620000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <272>, <273>, <274>, <275>, - <276>, <277>, <278>, <279>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio5: gpio@621000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00621000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <296>, <297>, <298>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 110 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00630000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <280>, <281>, <282>, <283>, - <284>, <285>, <286>, <287>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio7: gpio@631000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00631000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <300>, <301>, <302>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x6>; - ti,otap-del-sel-hs400 = <0x0>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,itap-del-sel-ddr52 = <0x3>; - ti,trm-icp = <0x8>; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; - assigned-clocks = <&k3_clks 92 0>; - assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,itap-del-sel-ddr50 = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - sdhci-caps-mask = <0x2 0x0>; - status = "disabled"; - }; - - main_sdhci2: mmc@4f98000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_ahb", "clk_xin"; - clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; - assigned-clocks = <&k3_clks 93 0>; - assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,itap-del-sel-ddr50 = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - sdhci-caps-mask = <0x2 0x0>; - status = "disabled"; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: cdns-usb@4114000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4114000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb1: usb@6400000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6400000 0x00 0x10000>, - <0x00 0x6410000 0x00 0x10000>, - <0x00 0x6420000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 0>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 0>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 0>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 0>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2040000 0x0 0x100>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 0>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2050000 0x0 0x100>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 0>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2060000 0x0 0x100>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 0>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - ufs_wrapper: ufs-wrapper@4e80000 { - compatible = "ti,j721e-ufs"; - reg = <0x0 0x4e80000 0x0 0x100>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - ufs@4e84000 { - compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; - reg = <0x0 0x4e84000 0x0 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; - clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; - clock-names = "core_clk", "phy_clk", "ref_clk"; - dma-coherent; - }; - }; - - mhdp: dp-bridge@a000000 { - compatible = "ti,j721e-mhdp8546"; - /* - * Note: we do not map DPTX PHY area, as that is handled by - * the PHY driver. - */ - reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ - <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ - reg-names = "mhdptx", "j721e-intg"; - - clocks = <&k3_clks 151 36>; - - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; - - power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; - - dp0_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@4 { - reg = <4>; - }; - }; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = - <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - - dss_ports: ports { - }; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 174 1>; - clock-names = "fck"; - power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 175 1>; - clock-names = "fck"; - power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 176 1>; - clock-names = "fck"; - power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp3: mcasp@2b30000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b30000 0x0 0x2000>, - <0x0 0x02b38000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 177 1>; - clock-names = "fck"; - power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp4: mcasp@2b40000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b40000 0x0 0x2000>, - <0x0 0x02b48000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 178 1>; - clock-names = "fck"; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp5: mcasp@2b50000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b50000 0x0 0x2000>, - <0x0 0x02b58000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 179 1>; - clock-names = "fck"; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp6: mcasp@2b60000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b60000 0x0 0x2000>, - <0x0 0x02b68000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 180 1>; - clock-names = "fck"; - power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp7: mcasp@2b70000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b70000 0x0 0x2000>, - <0x0 0x02b78000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 181 1>; - clock-names = "fck"; - power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp8: mcasp@2b80000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b80000 0x0 0x2000>, - <0x0 0x02b88000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 182 1>; - clock-names = "fck"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp9: mcasp@2b90000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b90000 0x0 0x2000>, - <0x0 0x02b98000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 183 1>; - clock-names = "fck"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp10: mcasp@2ba0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02ba0000 0x0 0x2000>, - <0x0 0x02ba8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 184 1>; - clock-names = "fck"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcasp11: mcasp@2bb0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02bb0000 0x0 0x2000>, - <0x0 0x02bb8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 185 1>; - clock-names = "fck"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5c00000 0x00008000>, - <0x5c10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <245>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 245 1>; - firmware-name = "j7-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5d00000 0x00008000>, - <0x5d10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <246>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 246 1>; - firmware-name = "j7-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@5e00000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5e00000 0x00 0x5e00000 0x20000>, - <0x5f00000 0x00 0x5f00000 0x20000>; - power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@5e00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5e00000 0x00008000>, - <0x5e10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <247>; - ti,sci-proc-ids = <0x08 0xff>; - resets = <&k3_reset 247 1>; - firmware-name = "j7-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@5f00000 { - compatible = "ti,j721e-r5f"; - reg = <0x5f00000 0x00008000>, - <0x5f10000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <248>; - ti,sci-proc-ids = <0x09 0xff>; - resets = <&k3_reset 248 1>; - firmware-name = "j7-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - c66_0: dsp@4d80800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x80800000 0x00 0x00048000>, - <0x4d 0x80e00000 0x00 0x00008000>, - <0x4d 0x80f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <142>; - ti,sci-proc-ids = <0x03 0xff>; - resets = <&k3_reset 142 1>; - firmware-name = "j7-c66_0-fw"; - status = "disabled"; - }; - - c66_1: dsp@4d81800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x81800000 0x00 0x00048000>, - <0x4d 0x81e00000 0x00 0x00008000>, - <0x4d 0x81f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <143>; - ti,sci-proc-ids = <0x04 0xff>; - resets = <&k3_reset 143 1>; - firmware-name = "j7-c66_1-fw"; - status = "disabled"; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721e-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <15>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 15 1>; - firmware-name = "j7-c71_0-fw"; - status = "disabled"; - }; - - icssg0: icssg@b000000 { - compatible = "ti,j721e-icssg"; - reg = <0x00 0xb000000 0x00 0x80000>; - power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x0b000000 0x100000>; - - icssg0_mem: memories@0 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - icssg0_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg0_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ - <&k3_clks 119 1>; /* icssg0_iclk */ - assigned-clocks = <&icssg0_coreclk_mux>; - assigned-clock-parents = <&k3_clks 119 1>; - }; - - icssg0_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ - <&icssg0_coreclk_mux>; /* core_clk */ - assigned-clocks = <&icssg0_iepclk_mux>; - assigned-clock-parents = <&icssg0_coreclk_mux>; - }; - }; - }; - - icssg0_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg0_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg0_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru0_0: pru@34000 { - compatible = "ti,j721e-pru"; - reg = <0x34000 0x3000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru0_0-fw"; - }; - - rtu0_0: rtu@4000 { - compatible = "ti,j721e-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu0_0-fw"; - }; - - tx_pru0_0: txpru@a000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru0_0-fw"; - }; - - pru0_1: pru@38000 { - compatible = "ti,j721e-pru"; - reg = <0x38000 0x3000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru0_1-fw"; - }; - - rtu0_1: rtu@6000 { - compatible = "ti,j721e-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu0_1-fw"; - }; - - tx_pru0_1: txpru@c000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru0_1-fw"; - }; - - icssg0_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 119 1>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - icssg1: icssg@b100000 { - compatible = "ti,j721e-icssg"; - reg = <0x00 0xb100000 0x00 0x80000>; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x0b100000 0x100000>; - - icssg1_mem: memories@b100000 { - reg = <0x0 0x2000>, - <0x2000 0x2000>, - <0x10000 0x10000>; - reg-names = "dram0", "dram1", - "shrdram2"; - }; - - icssg1_cfg: cfg@26000 { - compatible = "ti,pruss-cfg", "syscon"; - reg = <0x26000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x2000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - icssg1_coreclk_mux: coreclk-mux@3c { - reg = <0x3c>; - #clock-cells = <0>; - clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ - <&k3_clks 120 4>; /* icssg1_iclk */ - assigned-clocks = <&icssg1_coreclk_mux>; - assigned-clock-parents = <&k3_clks 120 4>; - }; - - icssg1_iepclk_mux: iepclk-mux@30 { - reg = <0x30>; - #clock-cells = <0>; - clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ - <&icssg1_coreclk_mux>; /* core_clk */ - assigned-clocks = <&icssg1_iepclk_mux>; - assigned-clock-parents = <&icssg1_coreclk_mux>; - }; - }; - }; - - icssg1_mii_rt: mii-rt@32000 { - compatible = "ti,pruss-mii", "syscon"; - reg = <0x32000 0x100>; - }; - - icssg1_mii_g_rt: mii-g-rt@33000 { - compatible = "ti,pruss-mii-g", "syscon"; - reg = <0x33000 0x1000>; - }; - - icssg1_intc: interrupt-controller@20000 { - compatible = "ti,icssg-intc"; - reg = <0x20000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host_intr0", "host_intr1", - "host_intr2", "host_intr3", - "host_intr4", "host_intr5", - "host_intr6", "host_intr7"; - }; - - pru1_0: pru@34000 { - compatible = "ti,j721e-pru"; - reg = <0x34000 0x4000>, - <0x22000 0x100>, - <0x22400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru1_0-fw"; - }; - - rtu1_0: rtu@4000 { - compatible = "ti,j721e-rtu"; - reg = <0x4000 0x2000>, - <0x23000 0x100>, - <0x23400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu1_0-fw"; - }; - - tx_pru1_0: txpru@a000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xa000 0x1800>, - <0x25000 0x100>, - <0x25400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru1_0-fw"; - }; - - pru1_1: pru@38000 { - compatible = "ti,j721e-pru"; - reg = <0x38000 0x4000>, - <0x24000 0x100>, - <0x24400 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-pru1_1-fw"; - }; - - rtu1_1: rtu@6000 { - compatible = "ti,j721e-rtu"; - reg = <0x6000 0x2000>, - <0x23800 0x100>, - <0x23c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-rtu1_1-fw"; - }; - - tx_pru1_1: txpru@c000 { - compatible = "ti,j721e-tx-pru"; - reg = <0xc000 0x1800>, - <0x25800 0x100>, - <0x25c00 0x100>; - reg-names = "iram", "control", "debug"; - firmware-name = "j7-txpru1_1-fw"; - }; - - icssg1_mdio: mdio@32400 { - compatible = "ti,davinci_mdio"; - reg = <0x32400 0x100>; - clocks = <&k3_clks 120 4>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; - }; - }; - - main_mcan0: can@2701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02701000 0x00 0x200>, - <0x00 0x02708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@2711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02711000 0x00 0x200>, - <0x00 0x02718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan2: can@2721000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02721000 0x00 0x200>, - <0x00 0x02728000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan3: can@2731000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02731000 0x00 0x200>, - <0x00 0x02738000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan4: can@2741000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02741000 0x00 0x200>, - <0x00 0x02748000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan5: can@2751000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02751000 0x00 0x200>, - <0x00 0x02758000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan6: can@2761000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02761000 0x00 0x200>, - <0x00 0x02768000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan7: can@2771000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02771000 0x00 0x200>, - <0x00 0x02778000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan8: can@2781000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02781000 0x00 0x200>, - <0x00 0x02788000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan9: can@2791000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02791000 0x00 0x200>, - <0x00 0x02798000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan10: can@27a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027a1000 0x00 0x200>, - <0x00 0x027a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan11: can@27b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027b1000 0x00 0x200>, - <0x00 0x027b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan12: can@27c1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027c1000 0x00 0x200>, - <0x00 0x027c8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan13: can@27d1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027d1000 0x00 0x200>, - <0x00 0x027d8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 266 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 267 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 268 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 269 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 270 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 271 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 272 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 273 1>; - status = "disabled"; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x700000 0x0 0x1000>; - ti,esm-pins = <344>, <345>; - }; -}; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi deleted file mode 100644 index f7ab7719fc0..00000000000 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ /dev/null @@ -1,681 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x0 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x0 0x43000014 0x0 0x4>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04200 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04280 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x0 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mcu_timer0: timer@40400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer1: timer@40410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; - assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer2: timer@40420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer3: timer@40430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; - assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer4: timer@40440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer5: timer@40450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; - assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer6: timer@40460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer7: timer@40470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; - assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer8: timer@40480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer9: timer@40490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; - assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - status = "disabled"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42110000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42100000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 0>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b10000 0x0 0x100>; - interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 0>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x42120000 0x0 0x100>; - interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 0>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - status = "disabled"; - }; - - fss: bus@47000000 { - compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: mux-controller@47000004 { - compatible = "reg-mux"; - reg = <0x00 0x47000004 0x00 0x2>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - status = "disabled"; - }; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 104 0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 1>; - assigned-clocks = <&k3_clks 1 3>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x0 0x2a480000 0x0 0x80000>, - <0x0 0x2a380000 0x0 0x80000>, - <0x0 0x2a400000 0x0 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j721e-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721e-r5f"; - reg = <0x41000000 0x00008000>, - <0x41010000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <250>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 250 1>; - firmware-name = "j7-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721e-r5f"; - reg = <0x41400000 0x00008000>, - <0x41410000 0x00008000>; - reg-names = "atcm", "btcm"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <251>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 251 1>; - firmware-name = "j7-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_mcan0: can@40528000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40528000 0x00 0x200>, - <0x00 0x40500000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@40568000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40568000 0x00 0x200>, - <0x00 0x40540000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 274 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 275 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 0>; - status = "disabled"; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j721e-vtm"; - reg = <0x00 0x42040000 0x00 0x350>, - <0x00 0x42050000 0x00 0x350>, - <0x00 0x43000300 0x00 0x10>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts index 43da4dafba8..586ddb6e7c8 100644 --- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -12,84 +12,8 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-beagleboneai64-u-boot.dtsi" +#include "k3-j721e-r5.dtsi" -/ { - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - chosen { - tick-timer = &mcu_timer0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 6>, - <&secure_proxy_mcu 8>, - <&secure_proxy_mcu 5>; - mbox-names = "rx", "tx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - /* We require this for boot handshake */ - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - bootph-pre-ram; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; - -&wkup_uart0_pins_default { - bootph-pre-ram; -}; &wkup_i2c0 { bootph-pre-ram; @@ -183,3 +107,32 @@ }; }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsue update GUIDs. See beagleboneai64.h. +#define BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR "772a4810-2194-4923-8754-0115870ef367" +#define BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR "dfc9c683-49b7-46bd-b3c1-3a3b2fdb135b" + +&capsule_tiboot3 { + efi-capsule { + image-guid = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID_STR; + }; +}; + +&binman { + capsule-sysfw { + filename = "sysfw-capsule.bin"; + efi-capsule { + image-index = <0x4>; + image-guid = BEAGLEBONEAI64_SYSFW_IMAGE_GUID_STR; + private-key = "arch/arm/mach-k3/keys/custMpk.pem"; + public-key-cert = "arch/arm/mach-k3/keys/custMpk.crt"; + monotonic-count = <0x1>; + + blob { + filename = "sysfw.itb"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 9655ca21d02..c7e344350c8 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -10,76 +10,7 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-common-proc-board-u-boot.dtsi" -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - bootph-pre-ram; - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - }; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721e-r5.dtsi" &wkup_i2c0 { bootph-pre-ram; @@ -111,10 +42,6 @@ }; }; -&wkup_uart0_pins_default { - bootph-pre-ram; -}; - &mcu_uart0_pins_default { bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index b0c108e9693..96a13b2cb2b 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -10,80 +10,7 @@ #include "k3-j721e-ddr.dtsi" #include "k3-j721e-sk-u-boot.dtsi" -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; - assigned-clock-rates = <2000000000>, <200000000>; - ti,sci = <&dmsc>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - status = "okay"; - bootph-pre-ram; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - bootph-pre-ram; - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx"; - }; -}; - -&dmsc { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; - -&wkup_uart0_pins_default { - bootph-pre-ram; -}; +#include "k3-j721e-r5.dtsi" &mcu_uart0_pins_default { bootph-pre-ram; diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi new file mode 100644 index 00000000000..fd0d921272c --- /dev/null +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clock-rates = <2000000000>, <200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + status = "okay"; + bootph-pre-ram; +}; + +&dmsc { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + bootph-pre-ram; + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx"; + }; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; + +&wkup_uart0_pins_default { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 8f4f944263e..07ed7b40fed 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -15,10 +15,10 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&chipid { + bootph-all; }; &mcu_navss { @@ -26,19 +26,11 @@ }; &mcu_ringacc { - bootph-all; + bootph-all; }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; - bootph-all; + bootph-all; }; &secure_proxy_main { @@ -155,3 +147,26 @@ bootph-all; }; }; + +#ifdef CONFIG_TARGET_J721E_A72_EVM + +#define SPL_J721E_SK_DTB "spl/dts/ti/k3-j721e-sk.dtb" +#define J721E_SK_DTB "u-boot.dtb" + +&spl_j721e_dtb { + filename = SPL_J721E_SK_DTB; +}; + +&j721e_dtb { + filename = J721E_SK_DTB; +}; + +&spl_j721e_dtb_unsigned { + filename = SPL_J721E_SK_DTB; +}; + +&j721e_dtb_unsigned { + filename = J721E_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-j721e-sk.dts b/arch/arm/dts/k3-j721e-sk.dts deleted file mode 100644 index 42fe8eee9ec..00000000000 --- a/arch/arm/dts/k3-j721e-sk.dts +++ /dev/null @@ -1,1074 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - compatible = "ti,j721e-sk", "ti,j721e"; - model = "Texas Instruments J721E SK"; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - ethernet0 = &cpsw_port1; - mmc1 = &main_sdhci1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - vusb_main: fixedregulator-vusb-main5v0 { - /* USB MAIN INPUT 5V DC */ - compatible = "regulator-fixed"; - regulator-name = "vusb-main5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5141 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vusb_main>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_mmc1_en_pins_default>; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: gpio-regulator-tps659411 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tps659411"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - dp_pwr_3v3: fixedregulator-dp-prw { - compatible = "regulator-fixed"; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pwr_en_pins_default>; - gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_pins_default>; - - ddc-i2c-bus = <&main_i2c1>; - - /* HDMI_HPD */ - hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; - }; - - dvi-bridge { - compatible = "ti,tfp410"; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pdn_pins_default>; - - powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; - ti,deskew = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint { - remote-endpoint = <&dpi1_out>; - pclk-sample = <1>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint { - remote-endpoint = - <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&main_pmx0 { - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ - J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - main_uart1_pins_default: main-uart1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ - J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ - >; - }; - - dp_pwr_en_pins_default: dp-pwr-en-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ - >; - }; - - dss_vout0_pins_default: dss-vout0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ - J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ - J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ - J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ - J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ - J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ - J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ - J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ - J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ - J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ - J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ - J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ - J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ - J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ - J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ - J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ - J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ - J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ - J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ - J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ - J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ - J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ - J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ - J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ - J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ - J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ - J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ - J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ - >; - }; - - hdmi_hpd_pins_default: hdmi-hpd-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ - >; - }; - - hdmi_pdn_pins_default: hdmi-pdn-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ - >; - }; - - /* Reset for M.2 E Key slot on PCIe0 */ - ekey_reset_pins_default: ekey-reset-pns-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ - J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ - >; - }; - - rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ - J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ - J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ - J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ - J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ - J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ - J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ - J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ - J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ - J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ - J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ - J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ - J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ - J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ - J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ - J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ - J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ - J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ - J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ - J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ - J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ - J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ - J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ - >; - }; - - rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ - >; - }; -}; - -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ - J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ - >; - }; - - vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ - J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - /* Reset for M.2 M Key slot on PCIe1 */ - mkey_reset_pins_default: mkey-reset-pns-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@51 { - /* AT24C512C-MAHM-T */ - compatible = "atmel,24c512"; - reg = <0x51>; - }; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; -}; - -&main_sdhci1 { - /* SD Card */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@7c0000 { - label = "ospi.env.backup"; - reg = <0x7c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - i2c-mux@71 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - /* PCIe1 M.2 M Key I2C */ - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - /* PCIe0 M.2 E Key I2C */ - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - /* i2c1 is used for DVI DDC, so we need to use 100kHz */ - clock-frequency = <100000>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - /* CSI0 I2C */ - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - /* CSI1 I2C */ - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&main_i2c5 { - /* Brought out on RPi Header */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default>; - clock-frequency = <400000>; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio0_pins_default>; -}; - -&main_gpio1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rpi_header_gpio1_pins_default>; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&usb_serdes_mux { - idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ -}; - -&serdes_ln_ctrl { - idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, - <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&serdes2 { - serdes2_usb_link: phy@1 { - reg = <1>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz2 2>; - }; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,vbus-divider; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes2_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout0_pins_default>; - - assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ - <&k3_clks 152 4>, /* VP 2 pixel clock */ - <&k3_clks 152 9>, /* VP 3 pixel clock */ - <&k3_clks 152 13>; /* VP 4 pixel clock */ - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; - - port@1 { - reg = <1>; - - dpi1_out: endpoint { - remote-endpoint = <&tfp410_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&pcie0_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ekey_reset_pins_default>; - reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; - - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mkey_reset_pins_default>; - reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; - - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&ufs_wrapper { - status = "disabled"; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi deleted file mode 100644 index 7f0686c2ce3..00000000000 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ - * - * Product Link: https://www.ti.com/tool/J721EXSOMXEVM - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - >; - }; - - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x20000>; - }; - - partition@6a0000 { - label = "ospi.env.backup"; - reg = <0x6a0000 0x20000>; - }; - - partition@6c0000 { - label = "ospi.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fe0000 { - label = "ospi.phypattern"; - reg = <0x3fe0000 0x20000>; - }; - }; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "hbmc.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "hbmc.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "hbmc.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "hbmc.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "hbmc.sysfw"; - reg = <0x6c0000 0x100000>; - }; - - partition@800000 { - label = "hbmc.rootfs"; - reg = <0x800000 0x3800000>; - }; - }; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721e-thermal.dtsi b/arch/arm/dts/k3-j721e-thermal.dtsi deleted file mode 100644 index c2523279001..00000000000 --- a/arch/arm/dts/k3-j721e-thermal.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -thermal_zones: thermal-zones { - wkup_thermal: wkup-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup_crit: wkup-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - mpu_thermal: mpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu_crit: mpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - c7x_thermal: c7x-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - c7x_crit: c7x-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 3>; - - trips { - gpu_crit: gpu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; - - r5f_thermal: r5f-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 4>; - - trips { - r5f_crit: r5f-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; - }; -}; diff --git a/arch/arm/dts/k3-j721e.dtsi b/arch/arm/dts/k3-j721e.dtsi deleted file mode 100644 index a200810df54..00000000000 --- a/arch/arm/dts/k3-j721e.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ - <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ - <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ - <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ - <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - }; - }; - - #include "k3-j721e-thermal.dtsi" -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j721e-main.dtsi" -#include "k3-j721e-mcu-wakeup.dtsi" diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 7efb135bdff..d121d8c0c54 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -141,17 +141,15 @@ #ifdef CONFIG_TARGET_J721S2_A72_EVM -#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb" -#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb" - +#define SPL_J721S2_EVM_DTB "spl/dts/ti/k3-j721s2-common-proc-board.dtb" #define J721S2_EVM_DTB "u-boot.dtb" -#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb" &binman { ti-dm { filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { @@ -306,20 +304,6 @@ }; }; - - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_am68_sk_dtb>; - keyfile = "custMpk.pem"; - }; - spl_am68_sk_dtb: blob-ext { - filename = SPL_AM68_SK_DTB; - }; - }; }; configurations { @@ -331,13 +315,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -370,25 +347,6 @@ algo = "crc32"; }; }; - - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&am68_sk_dtb>; - keyfile = "custMpk.pem"; - }; - am68_sk_dtb: blob-ext { - filename = AM68_SK_DTB; - }; - - hash { - algo = "crc32"; - }; - }; - }; configurations { @@ -400,13 +358,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; - }; }; }; @@ -429,20 +380,10 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + spl_j721s2_evm_dtb_unsigned: blob { filename = SPL_J721S2_EVM_DTB; }; }; - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_AM68_SK_DTB; - }; - }; - }; configurations { @@ -454,12 +395,6 @@ loadables = "tee", "dm", "spl"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "atf"; - loadables = "tee", "dm", "spl"; - fdt = "fdt-1"; - }; }; }; }; @@ -480,26 +415,13 @@ type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + j721s2_evm_dtb_unsigned: blob { filename = J721S2_EVM_DTB; }; hash { algo = "crc32"; }; }; - fdt-1 { - description = "k3-am68-sk-base-board"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = AM68_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; configurations { @@ -511,12 +433,6 @@ loadables = "uboot"; fdt = "fdt-0"; }; - conf-1 { - description = "k3-am68-sk-base-board"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-1"; - }; }; }; }; diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 19b2d48c7f8..54eb9b4072c 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -19,10 +19,14 @@ &cbass_mcu_wakeup { bootph-all; +}; - chipid@43000014 { - bootph-all; - }; +&wkup_conf { + bootph-all; +}; + +&chipid { + bootph-all; }; &mcu_navss { @@ -34,14 +38,6 @@ }; &mcu_udmap { - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x284c0000 0x0 0x4000>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x284a0000 0x0 0x4000>, - <0x0 0x2aa00000 0x0 0x40000>, - <0x0 0x28400000 0x0 0x2000>; - reg-names = "gcfg", "rchan", "rchanrt", "tchan", - "tchanrt", "rflow"; bootph-all; }; @@ -106,7 +102,9 @@ }; &ospi0 { - status = "disabled"; + flash@0 { + bootph-all; + }; }; &ospi1 { diff --git a/arch/arm/dts/k3-j721s2-common-proc-board.dts b/arch/arm/dts/k3-j721s2-common-proc-board.dts deleted file mode 100644 index c6b85bbf9a1..00000000000 --- a/arch/arm/dts/k3-j721s2-common-proc-board.dts +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM - */ - -/dts-v1/; - -#include "k3-j721s2-som-p0.dtsi" -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy.h> - -#include "k3-serdes.h" - -/ { - compatible = "ti,j721s2-evm", "ti,j721s2"; - model = "Texas Instruments J721S2 EVM"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - serial1 = &mcu_uart0; - serial2 = &main_uart8; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - can0 = &main_mcan16; - can1 = &mcu_mcan0; - can2 = &mcu_mcan1; - can3 = &main_mcan3; - can4 = &main_mcan5; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: fixedregulator-sd { - /* Output of TPS22918 */ - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: gpio-regulator-TLV71033 { - /* Output of TLV71033 */ - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - transceiver1: can-phy1 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>; - enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - transceiver2: can-phy2 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; - standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver3: can-phy3 { - compatible = "ti,tcan1043"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; - enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; - mux-states = <&mux0 1>; - }; - - transceiver4: can-phy4 { - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; - mux-states = <&mux1 1>; - }; -}; - -&main_pmx0 { - main_uart8_pins_default: main-uart8-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ - J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ - J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ - J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ - J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ - J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ - J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ - J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ - J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ - J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ - J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ - >; - }; - - main_mcan3_pins_default: main-mcan3-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ - J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ - >; - }; - - main_mcan5_pins_default: main-mcan5-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ - J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ - >; - }; -}; - -&wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ - J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ - >; - }; - - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ - >; - }; - - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ - >; - }; - - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ - J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ - J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ - J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ - J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ - J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ - J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ - J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ - J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ - J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ - J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ - J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ - J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ - J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ - >; - }; -}; - -&wkup_pmx1 { - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ - J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ - >; - }; -}; - -&main_gpio0 { - status = "okay"; -}; - -&wkup_gpio0 { - status = "okay"; -}; - -&wkup_uart0 { - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&mcu_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; -}; - -&main_uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart8_pins_default>; - /* Shared with TFA on this platform */ - power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; -}; - -&main_i2c0 { - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ", - "PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ", - "PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#", - "PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1", - "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz"; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN", - "USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#", - "MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1", - "MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL", - "CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL", - "ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2"; - }; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - status = "okay"; - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - disable-wp; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&serdes_ln_ctrl { - idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, - <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; -}; - -&serdes_refclk { - clock-frequency = <100000000>; -}; - -&serdes0 { - status = "okay"; - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 1 */ -}; - -&usbss0 { - status = "okay"; - pinctrl-0 = <&main_usbss0_pins_default>; - pinctrl-names = "default"; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - }; -}; - -&pcie1_rc { - status = "okay"; - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&mcu_mcan0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - phys = <&transceiver1>; -}; - -&mcu_mcan1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - phys = <&transceiver2>; -}; - -&tscadc0 { - pinctrl-0 = <&mcu_adc0_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - pinctrl-0 = <&mcu_adc1_pins_default>; - pinctrl-names = "default"; - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_mcan3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan3_pins_default>; - phys = <&transceiver3>; -}; - -&main_mcan5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mcan5_pins_default>; - phys = <&transceiver4>; -}; diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi deleted file mode 100644 index b03731b53a2..00000000000 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ /dev/null @@ -1,1928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family Main Domain peripherals - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/phy/phy-ti.h> - -/ { - serdes_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x400000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - - tifs-sram@1f0000 { - reg = <0x1f0000 0x10000>; - }; - - l3cache-sram@200000 { - reg = <0x200000 0x200000>; - }; - }; - - scm_conf: syscon@104000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00104000 0x00 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00104000 0x18000>; - - usb_serdes_mux: mux-controller@0 { - compatible = "mmio-mux"; - reg = <0x0 0x4>; - #mux-control-cells = <1>; - mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - - phy_gmii_sel_cpsw: phy@34 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x34 0x4>; - #phy-cells = <1>; - }; - - serdes_ln_ctrl: mux-controller@80 { - compatible = "mmio-mux"; - reg = <0x80 0x10>; - #mux-control-cells = <1>; - mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ - }; - - ehrpwm_tbclk: clock-controller@140 { - compatible = "ti,am654-ehrpwm-tbclk"; - reg = <0x140 0x18>; - #clock-cells = <1>; - }; - }; - - main_ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3000000 0x00 0x100>; - power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3010000 0x00 0x100>; - power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3020000 0x00 0x100>; - power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3030000 0x00 0x100>; - power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3040000 0x00 0x100>; - power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - main_ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x00 0x3050000 0x00 0x100>; - power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller@a00000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <148>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x120>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ - main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; - reg = <0x00 0x104200 0x00 0x50>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000007>; - }; - - /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ - main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; - reg = <0x00 0x104280 0x00 0x20>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000001f>; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x00 0x04e00000 0x00 0x1200>; - power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; - - dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, - <&main_udmap 0x4a41>; - dma-names = "tx", "rx1", "rx2"; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x00 0x04e10000 0x00 0x7d>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - main_timer0: timer@2400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2400000 0x00 0x400>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 63 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 63 1>; - assigned-clock-parents = <&k3_clks 63 2>; - power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer1: timer@2410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2410000 0x00 0x400>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 64 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 64 1>; - assigned-clock-parents = <&k3_clks 64 2>; - power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer2: timer@2420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2420000 0x00 0x400>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 65 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 65 1>; - assigned-clock-parents = <&k3_clks 65 2>; - power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer3: timer@2430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2430000 0x00 0x400>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 66 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 66 1>; - assigned-clock-parents = <&k3_clks 66 2>; - power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer4: timer@2440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2440000 0x00 0x400>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 67 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 67 1>; - assigned-clock-parents = <&k3_clks 67 2>; - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer5: timer@2450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2450000 0x00 0x400>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 68 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 68 1>; - assigned-clock-parents = <&k3_clks 68 2>; - power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer6: timer@2460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2460000 0x00 0x400>; - interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 69 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 69 1>; - assigned-clock-parents = <&k3_clks 69 2>; - power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer7: timer@2470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2470000 0x00 0x400>; - interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 70 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 70 1>; - assigned-clock-parents = <&k3_clks 70 2>; - power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer8: timer@2480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2480000 0x00 0x400>; - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 71 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 71 1>; - assigned-clock-parents = <&k3_clks 71 2>; - power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer9: timer@2490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2490000 0x00 0x400>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 72 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 72 1>; - assigned-clock-parents = <&k3_clks 72 2>; - power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer10: timer@24a0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24a0000 0x00 0x400>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 73 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 73 1>; - assigned-clock-parents = <&k3_clks 73 2>; - power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer11: timer@24b0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24b0000 0x00 0x400>; - interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 74 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 74 1>; - assigned-clock-parents = <&k3_clks 74 2>; - power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer12: timer@24c0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24c0000 0x00 0x400>; - interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 75 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 75 1>; - assigned-clock-parents = <&k3_clks 75 2>; - power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer13: timer@24d0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24d0000 0x00 0x400>; - interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 76 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 76 1>; - assigned-clock-parents = <&k3_clks 76 2>; - power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer14: timer@24e0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24e0000 0x00 0x400>; - interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 77 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 77 1>; - assigned-clock-parents = <&k3_clks 77 2>; - power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer15: timer@24f0000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x24f0000 0x00 0x400>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 78 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 78 1>; - assigned-clock-parents = <&k3_clks 78 2>; - power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer16: timer@2500000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2500000 0x00 0x400>; - interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 79 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 79 1>; - assigned-clock-parents = <&k3_clks 79 2>; - power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer17: timer@2510000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2510000 0x00 0x400>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 80 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 80 1>; - assigned-clock-parents = <&k3_clks 80 2>; - power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer18: timer@2520000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2520000 0x00 0x400>; - interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 81 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 81 1>; - assigned-clock-parents = <&k3_clks 81 2>; - power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_timer19: timer@2530000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x2530000 0x00 0x400>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 82 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 82 1>; - assigned-clock-parents = <&k3_clks 82 2>; - power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x200>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 146 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x200>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 350 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x200>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 351 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x200>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 352 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x200>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 353 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x200>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 354 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x200>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 355 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x200>; - interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 356 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x200>; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 357 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x200>; - interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 358 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00600000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <145>, <146>, <147>, <148>, <149>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00610000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <154>, <155>, <156>, <157>, <158>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00620000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <163>, <164>, <165>, <166>, <167>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x00630000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <172>, <173>, <174>, <175>, <176>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <66>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02000000 0x00 0x100>; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 214 1>; - clock-names = "fck"; - power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02010000 0x00 0x100>; - interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 215 1>; - clock-names = "fck"; - power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02020000 0x00 0x100>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 216 1>; - clock-names = "fck"; - power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02030000 0x00 0x100>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 217 1>; - clock-names = "fck"; - power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02040000 0x00 0x100>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 218 1>; - clock-names = "fck"; - power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02050000 0x00 0x100>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 219 1>; - clock-names = "fck"; - power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02060000 0x00 0x100>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 220 1>; - clock-names = "fck"; - power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x1000>, - <0x00 0x04f88000 0x00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 98 1>; - assigned-clock-parents = <&k3_clks 98 2>; - bus-width = <8>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; - ti,itap-del-sel-legacy = <0x10>; - ti,itap-del-sel-mmc-hs = <0xa>; - ti,strobe-sel = <0x77>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - dma-coherent; - status = "disabled"; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x1000>, - <0x00 0x04fb8000 0x00 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; - clock-names = "clk_ahb", "clk_xin"; - assigned-clocks = <&k3_clks 99 1>; - assigned-clock-parents = <&k3_clks 99 2>; - bus-width = <4>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; - dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; - status = "disabled"; - }; - - main_navss: bus@30000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <224>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller@310e0000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x310e0000 0x00 0x4000>; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <227>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&sms>; - ti,sci-dev-id = <265>; - ti,interrupt-ranges = <0 0 256>; - ti,unmapped-event-sources = <&main_bcdma_csi>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster0: mailbox@31f90000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f90000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster1: mailbox@31f91000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f91000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster2: mailbox@31f92000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f92000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster3: mailbox@31f93000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f93000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster4: mailbox@31f94000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f94000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster5: mailbox@31f95000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f95000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster6: mailbox@31f96000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f96000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster7: mailbox@31f97000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f97000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster8: mailbox@31f98000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f98000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster9: mailbox@31f99000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f99000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster10: mailbox@31f9a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f9a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - mailbox1_cluster11: mailbox@31f9b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f9b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - status = "disabled"; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>, - <0x0 0x31080000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; - ti,sci = <&sms>; - ti,sci-dev-id = <259>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x80000>, - <0x0 0x35000000 0x0 0x200000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&sms>; - ti,sci-dev-id = <263>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - main_bcdma_csi: dma-controller@311a0000 { - compatible = "ti,j721s2-dmss-bcdma-csi"; - reg = <0x00 0x311a0000 0x00 0x100>, - <0x00 0x35d00000 0x00 0x20000>, - <0x00 0x35c00000 0x00 0x10000>, - <0x00 0x35e00000 0x00 0x80000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <3>; - ti,sci = <&sms>; - ti,sci-dev-id = <225>; - ti,sci-rm-range-rchan = <0x21>; - ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 226 5>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ - assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - main_cpsw: ethernet@c200000 { - compatible = "ti,j721e-cpsw-nuss"; - reg = <0x00 0xc200000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - dma-coherent; - clocks = <&k3_clks 28 28>; - clock-names = "fck"; - power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&main_udmap 0xc640>, - <&main_udmap 0xc641>, - <&main_udmap 0xc642>, - <&main_udmap 0xc643>, - <&main_udmap 0xc644>, - <&main_udmap 0xc645>, - <&main_udmap 0xc646>, - <&main_udmap 0xc647>, - <&main_udmap 0x4640>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - main_cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - phys = <&phy_gmii_sel_cpsw 1>; - status = "disabled"; - }; - }; - - main_cpsw_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 28 28>; - clock-names = "fck"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 28 3>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x04104000 0x00 0x100>; - clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 360 17>; - power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - - status = "disabled"; /* Needs pinmux */ - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x06000000 0x00 0x10000>, - <0x00 0x06010000 0x00 0x10000>, - <0x00 0x06020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host", "peripheral", "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - serdes_wiz0: wiz@5060000 { - compatible = "ti,j721s2-wiz-10g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - num-lanes = <4>; - #reset-cells = <1>; - #clock-cells = <1>; - ranges = <0x5060000 0x0 0x5060000 0x10000>; - - assigned-clocks = <&k3_clks 365 3>; - assigned-clock-parents = <&k3_clks 365 7>; - - serdes0: serdes@5060000 { - compatible = "ti,j721e-serdes-10g"; - reg = <0x05060000 0x00010000>; - reg-names = "torrent_phy"; - resets = <&serdes_wiz0 0>; - reset-names = "torrent_reset"; - clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; - clock-names = "refclk", "phy_en_refclk"; - assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, - <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, - <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; - assigned-clock-parents = <&k3_clks 365 3>, - <&k3_clks 365 3>, - <&k3_clks 365 3>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - status = "disabled"; /* Needs lane config */ - }; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 276 41>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb013>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ - <0 0 0 2 &pcie1_intc 0>, /* INT B */ - <0 0 0 3 &pcie1_intc 0>, /* INT C */ - <0 0 0 4 &pcie1_intc 0>; /* INT D */ - - status = "disabled"; /* Needs gpio and serdes info */ - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; - }; - }; - - main_mcan0: can@2701000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02701000 0x00 0x200>, - <0x00 0x02708000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan1: can@2711000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02711000 0x00 0x200>, - <0x00 0x02718000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan2: can@2721000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02721000 0x00 0x200>, - <0x00 0x02728000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan3: can@2731000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02731000 0x00 0x200>, - <0x00 0x02738000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan4: can@2741000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02741000 0x00 0x200>, - <0x00 0x02748000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan5: can@2751000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02751000 0x00 0x200>, - <0x00 0x02758000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan6: can@2761000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02761000 0x00 0x200>, - <0x00 0x02768000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan7: can@2771000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02771000 0x00 0x200>, - <0x00 0x02778000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan8: can@2781000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02781000 0x00 0x200>, - <0x00 0x02788000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan9: can@2791000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02791000 0x00 0x200>, - <0x00 0x02798000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan10: can@27a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027a1000 0x00 0x200>, - <0x00 0x027a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan11: can@27b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027b1000 0x00 0x200>, - <0x00 0x027b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan12: can@27c1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027c1000 0x00 0x200>, - <0x00 0x027c8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan13: can@27d1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x027d1000 0x00 0x200>, - <0x00 0x027d8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan14: can@2681000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02681000 0x00 0x200>, - <0x00 0x02688000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan15: can@2691000 { - compatible = "bosch,m_can"; - reg = <0x00 0x02691000 0x00 0x200>, - <0x00 0x02698000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan16: can@26a1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x026a1000 0x00 0x200>, - <0x00 0x026a8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_mcan17: can@26b1000 { - compatible = "bosch,m_can"; - reg = <0x00 0x026b1000 0x00 0x200>, - <0x00 0x026b8000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02100000 0x00 0x400>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 339 1>; - status = "disabled"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02110000 0x00 0x400>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 340 1>; - status = "disabled"; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02120000 0x00 0x400>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 341 1>; - status = "disabled"; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02130000 0x00 0x400>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 342 1>; - status = "disabled"; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02140000 0x00 0x400>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 343 1>; - status = "disabled"; - }; - - main_spi5: spi@2150000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02150000 0x00 0x400>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 344 1>; - status = "disabled"; - }; - - main_spi6: spi@2160000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02160000 0x00 0x400>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 345 1>; - status = "disabled"; - }; - - main_spi7: spi@2170000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x00 0x02170000 0x00 0x400>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 346 1>; - status = "disabled"; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - clocks = <&k3_clks 158 0>, - <&k3_clks 158 2>, - <&k3_clks 158 5>, - <&k3_clks 158 14>, - <&k3_clks 158 18>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - status = "disabled"; - - dss_ports: ports { - }; - }; - - main_r5fss0: r5fss@5c00000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c00000 0x00 0x5c00000 0x20000>, - <0x5d00000 0x00 0x5d00000 0x20000>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss0_core0: r5f@5c00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5c00000 0x00010000>, - <0x5c10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <279>; - ti,sci-proc-ids = <0x06 0xff>; - resets = <&k3_reset 279 1>; - firmware-name = "j721s2-main-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss0_core1: r5f@5d00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5d00000 0x00010000>, - <0x5d10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <280>; - ti,sci-proc-ids = <0x07 0xff>; - resets = <&k3_reset 280 1>; - firmware-name = "j721s2-main-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - main_r5fss1: r5fss@5e00000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5e00000 0x00 0x5e00000 0x20000>, - <0x5f00000 0x00 0x5f00000 0x20000>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - - main_r5fss1_core0: r5f@5e00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5e00000 0x00010000>, - <0x5e10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <281>; - ti,sci-proc-ids = <0x08 0xff>; - resets = <&k3_reset 281 1>; - firmware-name = "j721s2-main-r5f1_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - main_r5fss1_core1: r5f@5f00000 { - compatible = "ti,j721s2-r5f"; - reg = <0x5f00000 0x00010000>, - <0x5f10000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <282>; - ti,sci-proc-ids = <0x09 0xff>; - resets = <&k3_reset 282 1>; - firmware-name = "j721s2-main-r5f1_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&sms>; - ti,sci-dev-id = <8>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 8 1>; - firmware-name = "j721s2-c71_0-fw"; - status = "disabled"; - }; - - c71_1: dsp@65800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x65800000 0x00 0x00080000>, - <0x00 0x65e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&sms>; - ti,sci-dev-id = <11>; - ti,sci-proc-ids = <0x31 0xff>; - resets = <&k3_reset 11 1>; - firmware-name = "j721s2-c71_1-fw"; - status = "disabled"; - }; - - main_esm: esm@700000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x700000 0x00 0x1000>; - ti,esm-pins = <688>, <689>; - bootph-pre-ram; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2200000 0x00 0x100>; - clocks = <&k3_clks 286 1>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 286 1>; - assigned-clock-parents = <&k3_clks 286 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2210000 0x00 0x100>; - clocks = <&k3_clks 287 1>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 287 1>; - assigned-clock-parents = <&k3_clks 287 5>; - }; - - /* - * The following RTI instances are coupled with MCU R5Fs, c7x and - * GPU so keeping them reserved as these will be used by their - * respective firmware - */ - watchdog2: watchdog@22f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x22f0000 0x00 0x100>; - clocks = <&k3_clks 290 1>; - power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 290 1>; - assigned-clock-parents = <&k3_clks 290 5>; - /* reserved for GPU */ - status = "reserved"; - }; - - watchdog3: watchdog@2300000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2300000 0x00 0x100>; - clocks = <&k3_clks 288 1>; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 288 1>; - assigned-clock-parents = <&k3_clks 288 5>; - /* reserved for C7X_0 */ - status = "reserved"; - }; - - watchdog4: watchdog@2310000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2310000 0x00 0x100>; - clocks = <&k3_clks 289 1>; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 289 1>; - assigned-clock-parents = <&k3_clks 289 5>; - /* reserved for C7X_1 */ - status = "reserved"; - }; - - watchdog5: watchdog@23c0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23c0000 0x00 0x100>; - clocks = <&k3_clks 291 1>; - power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 291 1>; - assigned-clock-parents = <&k3_clks 291 5>; - /* reserved for MAIN_R5F0_0 */ - status = "reserved"; - }; - - watchdog6: watchdog@23d0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23d0000 0x00 0x100>; - clocks = <&k3_clks 292 1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 292 1>; - assigned-clock-parents = <&k3_clks 292 5>; - /* reserved for MAIN_R5F0_1 */ - status = "reserved"; - }; - - watchdog7: watchdog@23e0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23e0000 0x00 0x100>; - clocks = <&k3_clks 293 1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 293 1>; - assigned-clock-parents = <&k3_clks 293 5>; - /* reserved for MAIN_R5F1_0 */ - status = "reserved"; - }; - - watchdog8: watchdog@23f0000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x23f0000 0x00 0x100>; - clocks = <&k3_clks 294 1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 294 1>; - assigned-clock-parents = <&k3_clks 294 5>; - /* reserved for MAIN_R5F1_1 */ - status = "reserved"; - }; -}; diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi deleted file mode 100644 index 7254f3bd363..00000000000 --- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi +++ /dev/null @@ -1,738 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - sms: system-controller@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes = <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clock-controller { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - secure_proxy_sa3: mailbox@43600000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x43600000 0x00 0x10000>, - <0x00 0x44880000 0x00 0x20000>, - <0x00 0x44860000 0x00 0x20000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x034>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x02C>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c068 0x00 0x120>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_pmx3: pinctrl@4301c190 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c190 0x00 0x004>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ - mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04200 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ - mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; - reg = <0x00 0x40f04280 0x00 0x28>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - wkup_gpio_intr: interrupt-controller@42200000 { - compatible = "ti,sci-intr"; - reg = <0x00 0x42200000 0x00 0x400>; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&sms>; - ti,sci-dev-id = <125>; - ti,interrupt-ranges = <16 960 16>; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - - }; - - mcu_timer0: timer@40400000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40400000 0x00 0x400>; - interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 35 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 35 1>; - assigned-clock-parents = <&k3_clks 35 2>; - power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer1: timer@40410000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40410000 0x00 0x400>; - interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 83 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 83 1>; - assigned-clock-parents = <&k3_clks 83 2>; - power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer2: timer@40420000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40420000 0x00 0x400>; - interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 84 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 84 1>; - assigned-clock-parents = <&k3_clks 84 2>; - power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer3: timer@40430000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40430000 0x00 0x400>; - interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 85 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 85 1>; - assigned-clock-parents = <&k3_clks 85 2>; - power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer4: timer@40440000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40440000 0x00 0x400>; - interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 86 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 86 1>; - assigned-clock-parents = <&k3_clks 86 2>; - power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer5: timer@40450000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40450000 0x00 0x400>; - interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 87 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 87 1>; - assigned-clock-parents = <&k3_clks 87 2>; - power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer6: timer@40460000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40460000 0x00 0x400>; - interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 88 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 88 1>; - assigned-clock-parents = <&k3_clks 88 2>; - power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer7: timer@40470000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40470000 0x00 0x400>; - interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 89 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 89 1>; - assigned-clock-parents = <&k3_clks 89 2>; - power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer8: timer@40480000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40480000 0x00 0x400>; - interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 90 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 90 1>; - assigned-clock-parents = <&k3_clks 90 2>; - power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - mcu_timer9: timer@40490000 { - compatible = "ti,am654-timer"; - reg = <0x00 0x40490000 0x00 0x400>; - interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 91 1>; - clock-names = "fck"; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - ti,timer-pwm; - /* Non-MPU Firmware usage */ - status = "reserved"; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x200>; - interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 359 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x200>; - interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; - clocks = <&k3_clks 149 3>; - clock-names = "fclk"; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42110000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <89>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 115 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x00 0x42100000 0x00 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <89>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 116 0>; - clock-names = "gpio"; - status = "disabled"; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 223 1>; - clock-names = "fck"; - power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 221 1>; - clock-names = "fck"; - power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 222 1>; - clock-names = "fck"; - power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; - status = "disabled"; - }; - - mcu_mcan0: can@40528000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40528000 0x00 0x200>, - <0x00 0x40500000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_mcan1: can@40568000 { - compatible = "bosch,m_can"; - reg = <0x00 0x40568000 0x00 0x200>, - <0x00 0x40540000 0x00 0x8000>; - reg-names = "m_can", "message_ram"; - power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; - clock-names = "hclk", "cclk"; - interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040300000 0x00 0x400>; - interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 347 0>; - status = "disabled"; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040310000 0x00 0x400>; - interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 348 0>; - status = "disabled"; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; - reg = <0x00 0x040320000 0x00 0x400>; - interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 349 0>; - status = "disabled"; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <267>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>, - <0x0 0x28440000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; - ti,sci = <&sms>; - ti,sci-dev-id = <272>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&sms>; - ti,sci-dev-id = <273>; - ti,ringacc = <&mcu_ringacc>; - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - secure_proxy_mcu: mailbox@2a480000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x2a480000 0x00 0x80000>, - <0x00 0x2a380000 0x00 0x80000>, - <0x00 0x2a400000 0x00 0x80000>; - /* - * Marked Disabled: - * Node is incomplete as it is meant for bootloaders and - * firmware on non-MPU processors - */ - status = "disabled"; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 29 28>; - clock-names = "fck"; - power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 29 28>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 29 3>; - clock-names = "cpts"; - assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ - assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40200000 0x00 0x1000>; - interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 0>; - assigned-clocks = <&k3_clks 0 2>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x00 0x40210000 0x00 0x1000>; - interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 0>; - assigned-clocks = <&k3_clks 1 2>; - assigned-clock-rates = <60000000>; - clock-names = "fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - status = "disabled"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - fss: bus@47000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x47040000 0x00 0x100>, - <0x05 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 109 5>; - assigned-clocks = <&k3_clks 109 5>; - assigned-clock-parents = <&k3_clks 109 7>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; /* Needs pinmux */ - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x00 0x47050000 0x00 0x100>, - <0x07 0x00000000 0x01 0x00000000>; - interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 110 5>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; /* Needs pinmux */ - }; - }; - - wkup_vtm0: temperature-sensor@42040000 { - compatible = "ti,j7200-vtm"; - reg = <0x00 0x42040000 0x0 0x350>, - <0x00 0x42050000 0x0 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; - #thermal-sensor-cells = <1>; - }; - - mcu_r5fss0: r5fss@41000000 { - compatible = "ti,j721s2-r5fss"; - ti,cluster-mode = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x41000000 0x00 0x41000000 0x20000>, - <0x41400000 0x00 0x41400000 0x20000>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - - mcu_r5fss0_core0: r5f@41000000 { - compatible = "ti,j721s2-r5f"; - reg = <0x41000000 0x00010000>, - <0x41010000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <284>; - ti,sci-proc-ids = <0x01 0xff>; - resets = <&k3_reset 284 1>; - firmware-name = "j721s2-mcu-r5f0_0-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - - mcu_r5fss0_core1: r5f@41400000 { - compatible = "ti,j721s2-r5f"; - reg = <0x41400000 0x00010000>, - <0x41410000 0x00010000>; - reg-names = "atcm", "btcm"; - ti,sci = <&sms>; - ti,sci-dev-id = <285>; - ti,sci-proc-ids = <0x02 0xff>; - resets = <&k3_reset 285 1>; - firmware-name = "j721s2-mcu-r5f0_1-fw"; - ti,atcm-enable = <1>; - ti,btcm-enable = <1>; - ti,loczrama = <1>; - }; - }; - - mcu_esm: esm@40800000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x40800000 0x00 0x1000>; - ti,esm-pins = <95>; - bootph-pre-ram; - }; - - wkup_esm: esm@42080000 { - compatible = "ti,j721e-esm"; - reg = <0x00 0x42080000 0x00 0x1000>; - ti,esm-pins = <63>; - bootph-pre-ram; - }; - - /* - * The 2 RTI instances are couple with MCU R5Fs so keeping them - * reserved as these will be used by their respective firmware - */ - mcu_watchdog0: watchdog@40600000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x40600000 0x00 0x100>; - clocks = <&k3_clks 295 1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 295 1>; - assigned-clock-parents = <&k3_clks 295 5>; - /* reserved for MCU_R5F0_0 */ - status = "reserved"; - }; - - mcu_watchdog1: watchdog@40610000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x40610000 0x00 0x100>; - clocks = <&k3_clks 296 1>; - power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 296 1>; - assigned-clock-parents = <&k3_clks 296 5>; - /* reserved for MCU_R5F0_1 */ - status = "reserved"; - }; -}; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index 03bd680f442..e92b1917df4 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -9,80 +9,4 @@ #include "k3-j721s2-ddr-evm-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-j721s2-common-proc-board-u-boot.dtsi" - -/ { - chosen { - tick-timer = &mcu_timer0; - }; - - aliases { - remoteproc0 = &sysctrler; - remoteproc1 = &a72_0; - }; - - a72_0: a72@0 { - compatible = "ti,am654-rproc"; - reg = <0x0 0x00a90000 0x0 0x10>; - power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; - resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <2000000000>; - ti,sci = <&sms>; - ti,sci-proc-id = <32>; - ti,sci-host-id = <10>; - bootph-pre-ram; - }; - - dm_tifs: dm-tifs { - compatible = "ti,j721e-dm-sci"; - ti,host-id = <3>; - ti,secure-host; - mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_mcu 21>, - <&secure_proxy_mcu 23>; - bootph-pre-ram; - }; -}; - -&mcu_timer0 { - clock-frequency = <250000000>; - bootph-pre-ram; -}; - -&secure_proxy_sa3 { - bootph-pre-ram; - status = "okay"; -}; - -&secure_proxy_mcu { - bootph-pre-ram; - status = "okay"; -}; - -&cbass_mcu_wakeup { - sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; - mbox-names = "tx", "rx", "boot_notify"; - bootph-pre-ram; - }; -}; - -&sms { - mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; - mbox-names = "tx", "rx", "notify"; - ti,host-id = <4>; - ti,secure-host; -}; - -&mcu_ringacc { - ti,sci = <&dm_tifs>; -}; - -&mcu_udmap { - ti,sci = <&dm_tifs>; -}; +#include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi new file mode 100644 index 00000000000..caf696c2d96 --- /dev/null +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + tick-timer = &mcu_timer0; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a72_0; + }; + + a72_0: a72@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 202 0>; + clocks = <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; + assigned-clock-parents = <&k3_clks 61 3>; + assigned-clock-rates = <200000000>, <2000000000>; + ti,sci = <&sms>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_mcu 21>, + <&secure_proxy_mcu 23>; + bootph-pre-ram; + }; +}; + +&mcu_timer0 { + clock-frequency = <250000000>; + bootph-pre-ram; +}; + +&secure_proxy_sa3 { + bootph-pre-ram; + status = "okay"; +}; + +&secure_proxy_mcu { + bootph-pre-ram; + status = "okay"; +}; + +&cbass_mcu_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&sms { + mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&fss { + /* fss node has 64 bit address regions mapped to it and since the ospi + * nodes is being override, override the fss node ranges as well + */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi deleted file mode 100644 index dcad372620b..00000000000 --- a/arch/arm/dts/k3-j721s2-som-p0.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SoM: https://www.ti.com/lit/zip/sprr439 - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721s2.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - memory@80000000 { - device_type = "memory"; - /* 16 GB RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x03 0x80000000>; - }; - - /* Reserving memory regions still pending */ - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: c71-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: c71-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - mux0: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; - }; - - mux1: mux-controller { - compatible = "gpio-mux"; - #mux-state-cells = <1>; - mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; - }; - - transceiver0: can-phy0 { - /* standby pin has been grounded by default */ - compatible = "ti,tcan1042"; - #phy-cells = <0>; - max-bitrate = <5000000>; - }; -}; - -&wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ - J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ - J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ - J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ - J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ - J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ - J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ - J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ - J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ - J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ - J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ - J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ - >; - }; -}; - -&wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ - J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ - >; - }; - - main_mcan16_pins_default: main-mcan16-default-pins { - pinctrl-single,pins = < - J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ - J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ - >; - }; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp_som: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", - "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", - "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", - "GPIO_LIN_EN", "CAN_STB"; - }; -}; - -&main_mcan16 { - status = "okay"; - pinctrl-0 = <&main_mcan16_pins_default>; - pinctrl-names = "default"; - phys = <&transceiver0>; -}; - -&ospi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - }; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; diff --git a/arch/arm/dts/k3-j721s2-thermal.dtsi b/arch/arm/dts/k3-j721s2-thermal.dtsi deleted file mode 100644 index f7b1a15b8fa..00000000000 --- a/arch/arm/dts/k3-j721s2-thermal.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include <dt-bindings/thermal/thermal.h> - -wkup0_thermal: wkup0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - wkup0_crit: wkup0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -wkup1_thermal: wkup1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - wkup1_crit: wkup1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main0_thermal: main0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - main0_crit: main0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main1_thermal: main1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 3>; - - trips { - main1_crit: main1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main2_thermal: main2-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 4>; - - trips { - main2_crit: main2-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main3_thermal: main3-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 5>; - - trips { - main3_crit: main3-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -main4_thermal: main4-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 6>; - - trips { - main4_crit: main4-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm/dts/k3-j721s2.dtsi b/arch/arm/dts/k3-j721s2.dtsi deleted file mode 100644 index 1f636acd4ee..00000000000 --- a/arch/arm/dts/k3-j721s2.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721S2 SoC Family - * - * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 - * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/soc/ti,sci_pm_domain.h> - -#include "k3-pinctrl.h" - -/ { - - model = "Texas Instruments K3 J721S2 SoC"; - compatible = "ti,j721s2"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - cache-unified; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ - - }; - - pmu: pmu { - compatible = "arm,cortex-a72-pmu"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ - <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - - }; - - }; - - thermal_zones: thermal-zones { - #include "k3-j721s2-thermal.dtsi" - }; -}; - -/* Now include peripherals from each bus segment */ -#include "k3-j721s2-main.dtsi" -#include "k3-j721s2-mcu-wakeup.dtsi" diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi new file mode 100644 index 00000000000..28087a3b6fb --- /dev/null +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" + +#if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM) + +&binman { + tiboot3-j722s-hs-fs-evm.bin { + filename = "tiboot3-j722s-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c7a800>; + }; + + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; +#endif /*CONFIG_TARGET_J722S_R5_EVM*/ + +#if IS_ENABLED(CONFIG_TARGET_J722S_A53_EVM) + +#define SPL_J722S_EVM_DTB "spl/dts/ti/k3-j722s-evm.dtb" +#define J722S_EVM_DTB "u-boot.dtb" + +&binman { + ti-dm { + filename = "ti-dm.bin"; + + blob-ext { + filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + images { + dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + + dm: ti-dm { + filename = "ti-dm.bin"; + }; + }; + + fdt-0 { + description = "k3-j722s-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&spl_j722s_evm_dtb>; + keyfile = "custMpk.pem"; + }; + + spl_j722s_evm_dtb: blob-ext { + filename = SPL_J722S_EVM_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j722s-evm"; + firmware = "atf"; + loadables = "tee", "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for J722S board"; + }; + + fdt-0 { + description = "k3-j722s-evm"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&j722s_evm_dtb>; + keyfile = "custMpk.pem"; + }; + + j722s_evm_dtb: blob-ext { + filename = J722S_EVM_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-j722s-evm"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; +#endif /*CONFIG_TARGET_J722S_A53_EVM*/ diff --git a/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi b/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi new file mode 100644 index 00000000000..f11aa60e614 --- /dev/null +++ b/arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi @@ -0,0 +1,2795 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the Jacinto7_DDRSS_RegConfigTool, Revision: J722S - v0.0.0 + * This file was generated on Fri Nov 17 2023 13:18:41 GMT-0600 (Central Standard Time) + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 25000000 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004B4B +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000800 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000204 +#define DDRSS_CTL_50_DATA 0x007A0012 +#define DDRSS_CTL_51_DATA 0x09140054 +#define DDRSS_CTL_52_DATA 0x00003A26 +#define DDRSS_CTL_53_DATA 0x007A0012 +#define DDRSS_CTL_54_DATA 0x09140054 +#define DDRSS_CTL_55_DATA 0x09003A26 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x0400036D +#define DDRSS_CTL_58_DATA 0x090F2005 +#define DDRSS_CTL_59_DATA 0x00001B13 +#define DDRSS_CTL_60_DATA 0x0E007FE6 +#define DDRSS_CTL_61_DATA 0x090F200F +#define DDRSS_CTL_62_DATA 0x00001B13 +#define DDRSS_CTL_63_DATA 0x0E007FE6 +#define DDRSS_CTL_64_DATA 0x0304200F +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x24262426 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x044A4A08 +#define DDRSS_CTL_69_DATA 0x042B2B04 +#define DDRSS_CTL_70_DATA 0x00002B2B +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x00000059 +#define DDRSS_CTL_76_DATA 0x000002C5 +#define DDRSS_CTL_77_DATA 0x00000E2E +#define DDRSS_CTL_78_DATA 0x000002C5 +#define DDRSS_CTL_79_DATA 0x00000E2E +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x0000000A +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000163 +#define DDRSS_CTL_84_DATA 0x00000386 +#define DDRSS_CTL_85_DATA 0x00000163 +#define DDRSS_CTL_86_DATA 0x00000386 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000E0005 +#define DDRSS_CTL_90_DATA 0x2908000E +#define DDRSS_CTL_91_DATA 0x0A050529 +#define DDRSS_CTL_92_DATA 0x1B0E0A03 +#define DDRSS_CTL_93_DATA 0x1B0E0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x00140014 +#define DDRSS_CTL_97_DATA 0x02D302D3 +#define DDRSS_CTL_98_DATA 0x02D302D3 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041C04 +#define DDRSS_CTL_103_DATA 0x0E0A0E0A +#define DDRSS_CTL_104_DATA 0x0A04041C +#define DDRSS_CTL_105_DATA 0x030E0A0E +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00001640 +#define DDRSS_CTL_120_DATA 0x00001640 +#define DDRSS_CTL_121_DATA 0x00001640 +#define DDRSS_CTL_122_DATA 0x00001640 +#define DDRSS_CTL_123_DATA 0x00001640 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000026F +#define DDRSS_CTL_126_DATA 0x00038B80 +#define DDRSS_CTL_127_DATA 0x00038B80 +#define DDRSS_CTL_128_DATA 0x00038B80 +#define DDRSS_CTL_129_DATA 0x00038B80 +#define DDRSS_CTL_130_DATA 0x00038B80 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x00006342 +#define DDRSS_CTL_133_DATA 0x00038B80 +#define DDRSS_CTL_134_DATA 0x00038B80 +#define DDRSS_CTL_135_DATA 0x00038B80 +#define DDRSS_CTL_136_DATA 0x00038B80 +#define DDRSS_CTL_137_DATA 0x00038B80 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x00006342 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x07010A09 +#define DDRSS_CTL_162_DATA 0x000E0A09 +#define DDRSS_CTL_163_DATA 0x010A0900 +#define DDRSS_CTL_164_DATA 0x0E0A0907 +#define DDRSS_CTL_165_DATA 0x0A090000 +#define DDRSS_CTL_166_DATA 0x0A090701 +#define DDRSS_CTL_167_DATA 0x0000000E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00BB0176 +#define DDRSS_CTL_199_DATA 0x0E0E01D3 +#define DDRSS_CTL_200_DATA 0x000001D3 +#define DDRSS_CTL_201_DATA 0x00BB0176 +#define DDRSS_CTL_202_DATA 0x0E0E01D3 +#define DDRSS_CTL_203_DATA 0x000001D3 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000084 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x000000E4 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x000000E4 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000084 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x000000E4 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x000000E4 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000033 +#define DDRSS_CTL_228_DATA 0x00000033 +#define DDRSS_CTL_229_DATA 0x00000033 +#define DDRSS_CTL_230_DATA 0x00000033 +#define DDRSS_CTL_231_DATA 0x00000033 +#define DDRSS_CTL_232_DATA 0x00000033 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x35000000 +#define DDRSS_CTL_257_DATA 0x35353535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x0000000F +#define DDRSS_CTL_270_DATA 0x0000000F +#define DDRSS_CTL_271_DATA 0x0000000F +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00001600 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000016 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x074A0040 +#define DDRSS_CTL_316_DATA 0x00020038 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x0038074A +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x005E005E +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x3FFF2000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0E081B1B +#define DDRSS_CTL_389_DATA 0x0009040E +#define DDRSS_CTL_390_DATA 0x0B0D040F +#define DDRSS_CTL_391_DATA 0x0B0D0406 +#define DDRSS_CTL_392_DATA 0x0D0D0906 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x07030701 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x000000B2 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000321 +#define DDRSS_CTL_403_DATA 0x000006F4 +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_406_DATA 0x00001C5C +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x00007F9E +#define DDRSS_CTL_412_DATA 0x00011B98 +#define DDRSS_CTL_413_DATA 0x111A0402 +#define DDRSS_CTL_414_DATA 0x37200C09 +#define DDRSS_CTL_415_DATA 0x00001C5C +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x00007F9E +#define DDRSS_CTL_421_DATA 0x00011B98 +#define DDRSS_CTL_422_DATA 0x111A0402 +#define DDRSS_CTL_423_DATA 0x00200C09 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F12 +#define DDRSS_PI_101_DATA 0x08111413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x01180118 +#define DDRSS_PI_178_DATA 0x00262601 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005E +#define DDRSS_PI_181_DATA 0x0002005E +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x00000013 +#define DDRSS_PI_188_DATA 0x00000059 +#define DDRSS_PI_189_DATA 0x000002C5 +#define DDRSS_PI_190_DATA 0x00000E2E +#define DDRSS_PI_191_DATA 0x000002C5 +#define DDRSS_PI_192_DATA 0x04000E2E +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00270027 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001B0043 +#define DDRSS_PI_210_DATA 0x001B0043 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301D3 +#define DDRSS_PI_214_DATA 0x010001D3 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01D40100 +#define DDRSS_PI_217_DATA 0x010001D4 +#define DDRSS_PI_218_DATA 0x01D401D4 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1C11090D +#define DDRSS_PI_223_DATA 0x1C110913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0021000D +#define DDRSS_PI_231_DATA 0x002101D3 +#define DDRSS_PI_232_DATA 0x000001D3 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000301 +#define DDRSS_PI_236_DATA 0x00300204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000301 +#define DDRSS_PI_239_DATA 0x00300C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000301 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05040900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x00000315 +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x2B0F0000 +#define DDRSS_PI_249_DATA 0x24140026 +#define DDRSS_PI_250_DATA 0x0000731B +#define DDRSS_PI_251_DATA 0x20070054 +#define DDRSS_PI_252_DATA 0x1B131B1C +#define DDRSS_PI_253_DATA 0x2B0F0000 +#define DDRSS_PI_254_DATA 0x24140026 +#define DDRSS_PI_255_DATA 0x0000731B +#define DDRSS_PI_256_DATA 0x20070054 +#define DDRSS_PI_257_DATA 0x1B131B1C +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x000000B2 +#define DDRSS_PI_260_DATA 0x000006F4 +#define DDRSS_PI_261_DATA 0x00001C5C +#define DDRSS_PI_262_DATA 0x00011B98 +#define DDRSS_PI_263_DATA 0x00001C5C +#define DDRSS_PI_264_DATA 0x00011B98 +#define DDRSS_PI_265_DATA 0x02D30014 +#define DDRSS_PI_266_DATA 0x030302D3 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x00000014 +#define DDRSS_PI_276_DATA 0x0005B18F +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000E94 +#define DDRSS_PI_280_DATA 0x000002D3 +#define DDRSS_PI_281_DATA 0x0005B18F +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000E94 +#define DDRSS_PI_285_DATA 0x010002D3 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x074A0040 +#define DDRSS_PI_289_DATA 0x00010038 +#define DDRSS_PI_290_DATA 0x074A0040 +#define DDRSS_PI_291_DATA 0x00000338 +#define DDRSS_PI_292_DATA 0x0028005D +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13100A18 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000084 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000033 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x35000000 +#define DDRSS_PI_335_DATA 0x20160F27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x000000E4 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x00000033 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20160F27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x000000E4 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x00000033 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20160F27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000084 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000033 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x35000000 +#define DDRSS_PI_359_DATA 0x20160F27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x000000E4 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x00000033 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20160F27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x000000E4 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x00000033 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20160F27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000084 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000033 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x35000000 +#define DDRSS_PI_383_DATA 0x20160F27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x000000E4 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x00000033 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20160F27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x000000E4 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x00000033 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20160F27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000084 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000033 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x35000000 +#define DDRSS_PI_407_DATA 0x20160F27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x000000E4 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x00000033 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20160F27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x000000E4 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x00000033 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20160F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000301 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071040 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C32 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x011E0120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x000002DD +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x045D045D +#define DDRSS_PHY_114_DATA 0x045D045D +#define DDRSS_PHY_115_DATA 0x045D045D +#define DDRSS_PHY_116_DATA 0x045D045D +#define DDRSS_PHY_117_DATA 0x0000045D +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00B200A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000301 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071040 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C32 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x011E0120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x000002DD +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x045D045D +#define DDRSS_PHY_370_DATA 0x045D045D +#define DDRSS_PHY_371_DATA 0x045D045D +#define DDRSS_PHY_372_DATA 0x045D045D +#define DDRSS_PHY_373_DATA 0x0000045D +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00B200A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000301 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071040 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C32 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x011E0120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x000002DD +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x045D045D +#define DDRSS_PHY_626_DATA 0x045D045D +#define DDRSS_PHY_627_DATA 0x045D045D +#define DDRSS_PHY_628_DATA 0x045D045D +#define DDRSS_PHY_629_DATA 0x0000045D +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00B200A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000301 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071040 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C32 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x011E0120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x000002DD +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x045D045D +#define DDRSS_PHY_882_DATA 0x045D045D +#define DDRSS_PHY_883_DATA 0x045D045D +#define DDRSS_PHY_884_DATA 0x045D045D +#define DDRSS_PHY_885_DATA 0x0000045D +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00B200A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F0F +#define DDRSS_PHY_1822_DATA 0x0F0F0F0F +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x02010804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j722s-evm-u-boot.dtsi b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi new file mode 100644 index 00000000000..88c4a72db61 --- /dev/null +++ b/arch/arm/dts/k3-j722s-evm-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common J722S EVM dts file for SPLs + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-j722s-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &main_timer0; + }; +}; + +&dmsc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts new file mode 100644 index 00000000000..aff83cd5d91 --- /dev/null +++ b/arch/arm/dts/k3-j722s-r5-evm.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * J722S EVM dts file for R5 SPL + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-j722s-evm.dts" +#include "k3-j722s-evm-u-boot.dtsi" + +#include "k3-j722s-ddr-lp4-50-3733.dtsi" +#include "k3-am62a-ddr.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial2 = &main_uart0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-all; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-all; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-all; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-all; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index e4dd6e14a66..85bdd1f5b6c 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -157,6 +157,22 @@ }; }; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See j784s4_evm.h +#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR; + + blob { + filename = "tiboot3-j784s4-hs-fs-evm.bin"; + }; + }; +}; + #endif #ifdef CONFIG_TARGET_J784S4_A72_EVM @@ -170,6 +186,7 @@ blob-ext { filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; @@ -342,4 +359,23 @@ }; }; }; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See j784s4_evm.h +#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e" +#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617" + +&capsule_tispl { + efi-capsule { + image-guid = AM69_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + #endif diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi deleted file mode 100644 index 3429e124d95..00000000000 --- a/arch/arm/dts/px30-engicam-common.dtsi +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/ { - aliases { - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; /* +5V */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&xin32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - }; - - vcc3v3_btreg: vcc3v3-btreg { - compatible = "regulator-gpio"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&bt_enable_h>; - regulator-name = "btreg-gpio-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - states = <3300000 0x0>; - }; - - vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_rf_aux_mod"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&sdio { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_3v3>; /* +3V3_SOM */ - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - card-detect-delay = <800>; - vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ - vqmmc-supply = <&vcc_3v3>; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi deleted file mode 100644 index bf10a3d29fc..00000000000 --- a/arch/arm/dts/px30-engicam-ctouch2.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions - * Copyright (c) 2020 Amarula Solutions(India) - */ - -#include "px30-engicam-common.dtsi" - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -}; - -&vcc3v3_btreg { - enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi deleted file mode 100644 index 449b8eb6454..00000000000 --- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -#include "px30-engicam-common.dtsi" - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - panel { - compatible = "yes-optoelectronics,ytc700tlag-05-201c"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - power-supply = <&vcc3v3_lcd>; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi_dphy { - status = "okay"; -}; - -/* LVDS_B(secondary) */ -&lvds { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts deleted file mode 100644 index 47aa30505a4..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "px30.dtsi" -#include "px30-engicam-ctouch2.dtsi" -#include "px30-engicam-px30-core.dtsi" - -/ { - model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; - compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", - "rockchip,px30"; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - panel { - compatible = "ampire,am-1280800n3tzqw-t00h"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd>; - data-mapping = "vesa-24"; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi_dphy { - status = "okay"; -}; - -&lvds { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts deleted file mode 100644 index 5a0ecb8faec..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "px30.dtsi" -#include "px30-engicam-ctouch2.dtsi" -#include "px30-engicam-px30-core.dtsi" - -/ { - model = "Engicam PX30.Core C.TOUCH 2.0"; - compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", - "rockchip,px30"; - - chosen { - stdout-path = "serial2:115200n8"; - }; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts deleted file mode 100644 index d759478e1c8..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "px30.dtsi" -#include "px30-engicam-edimm2.2.dtsi" -#include "px30-engicam-px30-core.dtsi" - -/ { - model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; - compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", - "rockchip,px30"; - - chosen { - stdout-path = "serial2:115200n8"; - }; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; -}; - -&vcc3v3_btreg { - enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi deleted file mode 100644 index 7249871530a..00000000000 --- a/arch/arm/dts/px30-engicam-px30-core.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons - * Copyright (c) 2020 Amarula Solutons(India) - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/rockchip.h> - -/ { - compatible = "engicam,px30-core", "rockchip,px30"; - - aliases { - mmc0 = &emmc; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v3_sys: DCDC_REG5 { - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v0: LDO_REG1 { - regulator-name = "vcc_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v0_pmu: LDO_REG4 { - regulator-name = "vcc3v0_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v3_lcd: SWITCH_REG1 { - regulator-boot-on; - regulator-name = "vcc3v3_lcd"; - }; - - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vcc_3v3>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc_3v3>; - pmuio2-supply = <&vcc_3v3>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts deleted file mode 100644 index 848bc39cf86..00000000000 --- a/arch/arm/dts/px30-evb.dts +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "px30.dtsi" - -/ { - model = "Rockchip PX30 EVB"; - compatible = "rockchip,px30-evb", "rockchip,px30"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - }; - - chosen { - stdout-path = "serial5:115200n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - esc-key { - label = "esc"; - linux,code = <KEY_ESC>; - press-threshold-microvolt = <1310000>; - }; - - home-key { - label = "home"; - linux,code = <KEY_HOME>; - press-threshold-microvolt = <624000>; - }; - - menu-key { - label = "menu"; - linux,code = <KEY_MENU>; - press-threshold-microvolt = <987000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = <KEY_VOLUMEDOWN>; - press-threshold-microvolt = <300000>; - }; - - vol-up-key { - label = "volume up"; - linux,code = <KEY_VOLUMEUP>; - press-threshold-microvolt = <17000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 25000 0>; - power-supply = <&vcc3v3_lcd>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ - }; - - vcc5v0_sys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&csi_dphy { - status = "okay"; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi { - status = "okay"; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - panel@0 { - compatible = "xinpeng,xpp055c272"; - reg = <0>; - backlight = <&backlight>; - iovcc-supply = <&vcc_1v8>; - vci-supply = <&vcc3v3_lcd>; - - port { - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; -}; - -&dsi_dphy { - status = "okay"; -}; - -&emmc { - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v0>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_rmii>; - snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_log>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <0>; - clock-output-names = "xin32k"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v0: vcc_rmii: DCDC_REG4 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_sys: DCDC_REG5 { - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v0: LDO_REG1 { - regulator-name = "vcc_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v0_pmu: LDO_REG4 { - regulator-name = "vcc3v0_pmu"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc2v8_dvp: LDO_REG7 { - regulator-name = "vcc2v8_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v5_dvp: LDO_REG9 { - regulator-name = "vcc1v5_dvp"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc3v3_lcd: SWITCH_REG1 { - regulator-name = "vcc3v3_lcd"; - regulator-boot-on; - }; - - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - sensor@d { - compatible = "asahi-kasei,ak8963"; - reg = <0x0d>; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&vcc3v0_pmu>; - mount-matrix = "1", /* x0 */ - "0", /* y0 */ - "0", /* z0 */ - "0", /* x1 */ - "1", /* y1 */ - "0", /* z1 */ - "0", /* x2 */ - "0", /* y2 */ - "1"; /* z2 */ - }; - - touchscreen@14 { - compatible = "goodix,gt1151"; - reg = <0x14>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>; - irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - VDDIO-supply = <&vcc3v3_lcd>; - }; - - sensor@4c { - compatible = "fsl,mma7660"; - reg = <0x4c>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - status = "okay"; - - clock-frequency = <100000>; - - /* These are relatively safe rise/fall times; TODO: measure */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - ov5695: ov5695@36 { - compatible = "ovti,ov5695"; - reg = <0x36>; - avdd-supply = <&vcc2v8_dvp>; - clocks = <&cru SCLK_CIF_OUT>; - clock-names = "xvclk"; - dvdd-supply = <&vcc1v5_dvp>; - dovdd-supply = <&vcc1v8_dvp>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_clkout_m0>; - reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - - port { - ucam_out: endpoint { - remote-endpoint = <&mipi_in_ucam>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2s1_2ch { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_sdio>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v0>; - vccio4-supply = <&vcc3v0_pmu>; - vccio5-supply = <&vcc_3v0>; - vccio6-supply = <&vccio_flash>; -}; - -&isp { - status = "okay"; - - ports { - port@0 { - mipi_in_ucam: endpoint@0 { - reg = <0>; - data-lanes = <1 2>; - remote-endpoint = <&ucam_out>; - }; - }; - }; -}; - -&isp_mmu { - status = "okay"; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = - <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = - <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_none>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = - <0 RK_PA4 2 &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - - pmuio1-supply = <&vcc3v0_pmu>; - pmuio2-supply = <&vcc3v0_pmu>; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <800>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdio { - cap-sd-highspeed; - keep-power-in-suspend; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - sd-uhs-sdr104; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi index e04766ad09c..29ea2763636 100644 --- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi +++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi @@ -15,14 +15,6 @@ }; }; -&binman { - simple-bin { - fit { - offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; - }; - }; -}; - &emmc_clk { bootph-all; }; diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts deleted file mode 100644 index 08a3ad3e7ae..00000000000 --- a/arch/arm/dts/px30-ringneck-haikou.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "px30-ringneck.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit"; - compatible = "tsd,px30-ringneck-haikou", "rockchip,px30"; - - aliases { - mmc2 = &sdmmc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&haikou_keys_pin>; - pinctrl-names = "default"; - - button-batlow-n { - label = "BATLOW#"; - linux,code = <KEY_BATTERY>; - gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - }; - - button-slp-btn-n { - label = "SLP_BTN#"; - linux,code = <KEY_SLEEP>; - gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; - }; - - button-wake-n { - label = "WAKE#"; - linux,code = <KEY_WAKEUP>; - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - switch-lid-btn-n { - label = "LID_BTN#"; - linux,code = <SW_LID>; - linux,input-type = <EV_SW>; - gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; - - sd_card_led: led-1 { - gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - function = LED_FUNCTION_SD; - color = <LED_COLOR_ID_BLUE>; - }; - }; - - i2s0-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Haikou,I2S-codec"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - clocks = <&sgtl5000_clk>; - sound-dai = <&sgtl5000>; - }; - - simple-audio-card,cpu { - bitclock-master; - frame-master; - sound-dai = <&i2s0_8ch>; - }; - }; - - sgtl5000_clk: sgtl5000-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_baseboard: vcc3v3-baseboard-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_baseboard: vcc5v0-baseboard-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdda_codec: vdda-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdda_codec"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_baseboard>; - }; - - vddd_codec: vddd-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "vddd_codec"; - regulator-boot-on; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1600000>; - vin-supply = <&vcc5v0_baseboard>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&sgtl5000_clk>; - #sound-dai-cells = <0>; - VDDA-supply = <&vdda_codec>; - VDDIO-supply = <&vcc3v3_baseboard>; - VDDD-supply = <&vddd_codec>; - }; -}; - -&i2c3 { - eeprom@50 { - reg = <0x50>; - compatible = "atmel,24c01"; - pagesize = <8>; - size = <128>; - vcc-supply = <&vcc3v3_baseboard>; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&gmac { - status = "okay"; -}; - -&pinctrl { - haikou { - haikou_keys_pin: haikou-keys-pin { - rockchip,pins = - /* WAKE# */ - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, - /* SLP_BTN# */ - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, - /* LID_BTN */ - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - /* BATLOW# */ - <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ - <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - sd_card_led_pin: sd-card-led-pin { - rockchip,pins = - <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <&vcc3v3_baseboard>; - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart5 { - pinctrl-0 = <&uart5_xfer>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi deleted file mode 100644 index 12397755830..00000000000 --- a/arch/arm/dts/px30-ringneck.dtsi +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "px30.dtsi" -#include <dt-bindings/leds/common.h> - -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdio; - rtc0 = &rtc_twi; - rtc1 = &rk809; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&module_led_pin>; - status = "okay"; - - module_led: led-0 { - gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - linux,default-trigger = "heartbeat"; - color = <LED_COLOR_ID_AMBER>; - }; - }; - - vcc5v0_sys: vccsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - supports-emmc; - mmc-pwrseq = <&emmc_pwrseq>; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_emmc>; - - status = "okay"; -}; - -/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ -&gmac { - snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - phy-supply = <&vcc_3v3>; - clock_in_out = "output"; -}; - -&gpio2 { - /* - * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module - * eMMC powered-down initially (in fact it keeps the reset signal - * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after - * the SPL has been booted from SD Card. - */ - bios-disable-override-hog { - gpios = <RK_PB5 GPIO_ACTIVE_LOW>; - output-high; - line-name = "bios_disable_override"; - gpio-hog; - }; - - /* - * The BIOS_DISABLE hog is a feedback pin for the actual status of the - * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually - * represents the state of a switch on the baseboard. - */ - bios-disable-n-hog { - gpios = <RK_PC2 GPIO_ACTIVE_LOW>; - line-name = "bios_disable"; - input; - gpio-hog; - }; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pmic_int>; - pinctrl-names = "default"; - #clock-cells = <0>; - clock-output-names = "xin32k"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_3v3>; - vcc6-supply = <&vcc_3v3>; - vcc7-supply = <&vcc_3v3>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { - regulator-name = "vcc_3v0_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_3v3: DCDC_REG5 { - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v0: LDO_REG3 { - regulator-name = "vcc_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vcc_lcd"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_1v8_lcd: LDO_REG8 { - regulator-name = "vcc_1v8_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG9 { - regulator-name = "vcca_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - /* SE05x is limited to Fast Mode */ - clock-frequency = <400000>; - - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2s0_8ch { - rockchip,trcm-sync-tx-only; - - pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx - &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_emmc>; - vccio-oscgpi-supply = <&vcc_3v3>; - - status = "okay"; -}; - -&pinctrl { - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - module_led_pin: module-led-pin { - rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = - <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - vqmmc-supply = <&vccio_sd>; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -/* Mule UCAN */ -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 046da022ffe..59fa9f43a97 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -33,11 +33,27 @@ bootph-all; }; +&uart2m0_xfer { + bootph-all; +}; + &uart5 { clock-frequency = <24000000>; bootph-all; }; +&uart5_cts { + bootph-all; +}; + +&uart5_rts { + bootph-all; +}; + +&uart5_xfer { + bootph-all; +}; + &sdmmc { bootph-all; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi deleted file mode 100644 index c8a46219826..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Gray Hawk CPU board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -#include "r8a779h0.dtsi" - -/ { - model = "Renesas Gray Hawk CPU board"; - compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0"; - - aliases { - ethernet0 = &avb0; - serial0 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:921600n8"; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x1 0x80000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - }; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&scif_clk { - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi deleted file mode 100644 index fcdd8eb8d54..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -&i2c0 { - eeprom@52 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "csi-dsi-sub-board-id"; - reg = <0x52>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi deleted file mode 100644 index 5a8e598c986..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -&i2c0 { - eeprom@53 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "ethernet-sub-board-id"; - reg = <0x53>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi deleted file mode 100644 index 92c13151613..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Gray Hawk board - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include "r8a779h0-u-boot.dtsi" - -/ { - aliases { - spi0 = &rpc; - }; -}; - -&pfc { - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <40000000>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk.dts b/arch/arm/dts/r8a779h0-gray-hawk.dts deleted file mode 100644 index 59e5e493ad1..00000000000 --- a/arch/arm/dts/r8a779h0-gray-hawk.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Gray Hawk CPU and BreakOut boards - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a779h0-gray-hawk-cpu.dtsi" -#include "r8a779h0-gray-hawk-csi-dsi.dtsi" -#include "r8a779h0-gray-hawk-ethernet.dtsi" - -/ { - model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0"; - compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0"; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi deleted file mode 100644 index b2f7e054eef..00000000000 --- a/arch/arm/dts/r8a779h0-u-boot.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include "r8a779x-u-boot.dtsi" -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - bank-width = <2>; - num-cs = <1>; - status = "disabled"; - }; - }; -}; - -&extalr_clk { - bootph-all; -}; diff --git a/arch/arm/dts/r8a779h0.dtsi b/arch/arm/dts/r8a779h0.dtsi deleted file mode 100644 index a896bc27f5a..00000000000 --- a/arch/arm/dts/r8a779h0.dtsi +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4M (R8A779H0) SoC - * - * Copyright (C) 2023 Renesas Electronics Corp. - */ - -#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/renesas,r8a779h0-sysc.h> - -/ { - compatible = "renesas,r8a779h0"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a76_0: cpu@0 { - compatible = "arm,cortex-a76"; - reg = <0>; - device_type = "cpu"; - power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; - }; - }; - - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a779h0"; - reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, - <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, - <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, - <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; - }; - - gpio0: gpio@e6050180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050180 0 0x54>; - interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 19>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - }; - - gpio1: gpio@e6050980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050980 0 0x54>; - interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - }; - - gpio2: gpio@e6058180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058180 0 0x54>; - interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - }; - - gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058980 0 0x54>; - interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - }; - - gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060180 0 0x54>; - interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 25>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060980 0 0x54>; - interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - gpio6: gpio@e6061180 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6061180 0 0x54>; - interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - gpio7: gpio@e6061980 { - compatible = "renesas,gpio-r8a779h0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6061980 0 0x54>; - interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a779h0-cpg-mssr"; - reg = <0 0xe6150000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a779h0-rst"; - reg = <0 0xe6160000 0 0x4000>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a779h0-sysc"; - reg = <0 0xe6180000 0 0x4000>; - #power-domain-cells = <1>; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 518>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 519>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 520>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a779h0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 521>; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 521>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a779h0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 514>; - status = "disabled"; - }; - - avb0: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a779h0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; - interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A779H0_PD_C4>; - resets = <&cpg 211>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb1: ethernet@e6810000 { - compatible = "renesas,etheravb-r8a779h0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 212>; - power-domains = <&sysc R8A779H0_PD_C4>; - resets = <&cpg 212>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb2: ethernet@e6820000 { - compatible = "renesas,etheravb-r8a779h0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6820000 0 0x1000>; - interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 213>; - power-domains = <&sysc R8A779H0_PD_C4>; - resets = <&cpg 213>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779h0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 706>, - <&cpg CPG_CORE R8A779H0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - status = "disabled"; - }; - - gic: interrupt-controller@f1000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1000000 0 0x20000>, - <0x0 0xf1060000 0 0x110000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 04028bf649f..a31dea8db3e 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -74,6 +74,21 @@ bootph-all; }; +&rk817 { + regulators { + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; +}; + &saradc { bootph-all; status = "okay"; diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts deleted file mode 100644 index ea0695b51ec..00000000000 --- a/arch/arm/dts/rk3326-odroid-go2.dts +++ /dev/null @@ -1,642 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Hardkernel Co., Ltd - * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "rk3326.dtsi" - -/ { - model = "ODROID-GO Advance"; - compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; - - aliases { - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - adc-joystick { - compatible = "adc-joystick"; - io-channels = <&saradc 1>, - <&saradc 2>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - abs-flat = <10>; - abs-fuzz = <10>; - abs-range = <172 772>; - linux,code = <ABS_X>; - }; - - axis@1 { - reg = <1>; - abs-flat = <10>; - abs-fuzz = <10>; - abs-range = <278 815>; - linux,code = <ABS_Y>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_bl>; - pwms = <&pwm1 0 25000 0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&btn_pins>; - - /* - * *** ODROIDGO2-Advance Switch layout *** - * |------------------------------------------------| - * | sw15 sw16 | - * |------------------------------------------------| - * | sw1 |-------------------| sw8 | - * | sw3 sw4 | | sw7 sw5 | - * | sw2 | LCD Display | sw6 | - * | | | | - * | |-------------------| | - * | sw9 sw10 sw11 sw12 sw13 sw14 | - * |------------------------------------------------| - */ - - sw1 { - gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; - label = "DPAD-UP"; - linux,code = <BTN_DPAD_UP>; - }; - sw2 { - gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; - label = "DPAD-DOWN"; - linux,code = <BTN_DPAD_DOWN>; - }; - sw3 { - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; - }; - sw4 { - gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - }; - sw5 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; - label = "BTN-A"; - linux,code = <BTN_EAST>; - }; - sw6 { - gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - label = "BTN-B"; - linux,code = <BTN_SOUTH>; - }; - sw7 { - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; - label = "BTN-Y"; - linux,code = <BTN_WEST>; - }; - sw8 { - gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; - label = "BTN-X"; - linux,code = <BTN_NORTH>; - }; - sw9 { - gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; - label = "F1"; - linux,code = <BTN_TRIGGER_HAPPY1>; - }; - sw10 { - gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; - label = "F2"; - linux,code = <BTN_TRIGGER_HAPPY2>; - }; - sw11 { - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - label = "F3"; - linux,code = <BTN_TRIGGER_HAPPY3>; - }; - sw12 { - gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; - label = "F4"; - linux,code = <BTN_TRIGGER_HAPPY4>; - }; - sw13 { - gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; - label = "F5"; - linux,code = <BTN_TRIGGER_HAPPY5>; - }; - sw14 { - gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; - label = "F6"; - linux,code = <BTN_TRIGGER_HAPPY6>; - }; - sw15 { - gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; - label = "TOP-LEFT"; - linux,code = <BTN_TL>; - }; - sw16 { - gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; - label = "TOP-RIGHT"; - linux,code = <BTN_TR>; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin>; - - blue_led: led-0 { - label = "blue:heartbeat"; - gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - rk817-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Analog"; - simple-audio-card,format = "i2s"; - simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MICL", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker", "SPKO"; - - simple-audio-card,codec { - sound-dai = <&rk817>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s1_2ch>; - }; - }; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v8_sys"; - regulator-always-on; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; - - vcc_host: vcc_host { - compatible = "regulator-fixed"; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - vin-supply = <&usb_midu>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&cru { - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, - <&cru PLL_CPLL>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>, - <17000000>; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi { - status = "okay"; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - panel@0 { - compatible = "elida,kd35t133"; - reg = <0>; - backlight = <&backlight>; - iovcc-supply = <&vcc_lcd>; - reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - rotation = <270>; - vdd-supply = <&vcc_lcd>; - - port { - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; -}; - -&dsi_dphy { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_logic>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <16>; - i2c-scl-rising-time-ns = <280>; - status = "okay"; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; - clock-output-names = "rk808-clkout1", "xin32k"; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S1_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; - wakeup-source; - #clock-cells = <1>; - #sound-dai-cells = <0>; - - vcc1-supply = <&vccsys>; - vcc2-supply = <&vccsys>; - vcc3-supply = <&vccsys>; - vcc4-supply = <&vccsys>; - vcc5-supply = <&vccsys>; - vcc6-supply = <&vccsys>; - vcc7-supply = <&vccsys>; - vcc8-supply = <&vccsys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v3_pmu: LDO_REG4 { - regulator-name = "vcc3v3_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_bl: LDO_REG7 { - regulator-name = "vcc_bl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lcd: LDO_REG8 { - regulator-name = "vcc_lcd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc_cam: LDO_REG9 { - regulator-name = "vcc_cam"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - usb_midu: BOOST { - regulator-name = "usb_midu"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5400000>; - regulator-always-on; - regulator-boot-on; - }; - }; - - rk817_codec: codec { - rockchip,mic-in-differential; - }; - }; -}; - -/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -/* I2S 1 Channel Used */ -&i2s1_2ch { - status = "okay"; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sfc { - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <1>; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "disabled"; - }; -}; - -&usb20_otg { - status = "okay"; -}; - -/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&pinctrl { - btns { - btn_pins: btn-pins { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - blue_led_pin: blue-led-pin { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dc_det: dc-det { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 5a9bd320ec4..55895d0dd19 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -33,12 +33,6 @@ }; &binman { - simple-bin { - fit { - offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; - }; - }; - #ifdef CONFIG_ROCKCHIP_SPI_IMAGE simple-bin-spi { fit { diff --git a/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi new file mode 100644 index 00000000000..af96d2fa8fb --- /dev/null +++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 ArmSoM Technology Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi new file mode 100644 index 00000000000..275ae6fdaea --- /dev/null +++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&emmc_pwrseq { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_reset { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */ + /delete-property/ mmc-ddr-1_8v; + /delete-property/ cap-mmc-highspeed; +}; + +&uart2m2_xfer { + bootph-all; +}; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 4623580c610..bfe6645c30e 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -4,77 +4,3 @@ */ #include "rk3588s-u-boot.dtsi" - -/ { - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - usbdpphy1_grf: syscon@fd5cc000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5cc000 0x0 0x4000>; - }; - - usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d4000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy1: usb2phy@4000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x4000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY1_IMMORTAL>, - <&cru PCLK_USBDPPHY1>, - <&u2phy1>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, - <&cru SRST_USBDP_COMBO_PHY1_CMN>, - <&cru SRST_USBDP_COMBO_PHY1_LANE>, - <&cru SRST_USBDP_COMBO_PHY1_PCS>, - <&cru SRST_P_USBDPPHY1>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index e9d38d5c83b..09d8b311cec 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -19,95 +19,10 @@ bootph-all; }; - usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d0000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy0: usb2phy@0 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x0 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; }; - - usbdp_phy0: phy@fed80000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed80000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY0_IMMORTAL>, - <&cru PCLK_USBDPPHY0>, - <&u2phy0>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, - <&cru SRST_USBDP_COMBO_PHY0_CMN>, - <&cru SRST_USBDP_COMBO_PHY0_LANE>, - <&cru SRST_USBDP_COMBO_PHY0_PCS>, - <&cru SRST_P_USBDPPHY0>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index 27e0c382678..c01d39f03ea 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,12 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + adc1_pins_a: adc1-pins-0 { + pins { + pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ + }; + }; + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ @@ -13,6 +19,104 @@ }; }; + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -47,6 +151,63 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ + }; + }; + + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_a: m_can1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ + <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ + }; + }; + mcp23017_pins_a: mcp23017-0 { pins { pinmux = <STM32_PINMUX('G', 12, GPIO)>; @@ -84,6 +245,21 @@ }; }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ @@ -99,6 +275,21 @@ }; }; + pwm13_pins_a: pwm13-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm13_sleep_pins_a: pwm13-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ + }; + }; + pwm14_pins_a: pwm14-0 { pins { pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ @@ -114,6 +305,89 @@ }; }; + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ + }; + }; + + qspi_bk1_pins_a: qspi-bk1-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + sai1a_pins_a: sai1a-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ + <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ + <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ + <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ + <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ + }; + }; + + sai1b_pins_a: sai1b-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ + bias-disable; + }; + }; + + sai1b_sleep_pins_a: sai1b-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -216,6 +490,73 @@ }; }; + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ + <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + spi2_pins_a: spi2-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ + <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_sleep_pins_a: spi2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ + <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ + <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ + }; + }; + + spi3_pins_a: spi3-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ + <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ + <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ + }; + }; + spi5_pins_a: spi5-0 { pins1 { pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ @@ -276,6 +617,77 @@ }; }; + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_idle_pins_b: uart4-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_sleep_pins_b: uart4-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ + <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ + <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ + bias-disable; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ + <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -347,6 +759,36 @@ }; }; + usart1_pins_b: usart1-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ @@ -387,4 +829,45 @@ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ }; }; + + usart2_pins_b: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_b: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 215ad9298de..ad331b73d18 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -1092,6 +1092,30 @@ <&scmi_clk CK_SCMI_LSI>; }; + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + status = "disabled"; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp13-exti", "syscon"; interrupt-controller; @@ -1304,6 +1328,37 @@ status = "disabled"; }; + eth1: eth1@5800a000 { + compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; @@ -1380,6 +1435,12 @@ ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; /* diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi index df451c3c2a2..5cd5bde9535 100644 --- a/arch/arm/dts/stm32mp133.dtsi +++ b/arch/arm/dts/stm32mp133.dtsi @@ -64,5 +64,35 @@ }; }; }; + + eth2: eth2@5800e000 { + compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; }; }; diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi new file mode 100644 index 00000000000..d718aae16ca --- /dev/null +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp13xx-dhcor-u-boot.dtsi" + +&uart4 { + bootph-all; +}; + +&uart4_pins_b { + bootph-all; + + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + +&usbphyc { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts new file mode 100644 index 00000000000..fc1c48ad56d --- /dev/null +++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + * + * DHCOR STM32MP13 variant: + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG + * DHCOR PCB number: 718-100 or newer + * DHSBC PCB number: 719-100 or newer + */ + +/dts-v1/; + +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP135F DHCOR DHSBC"; + compatible = "dh,stm32mp135f-dhcor-dhsbc", + "dh,stm32mp135f-dhcor-som", + "st,stm32mp135"; + + aliases { + ethernet0 = ð1; + ethernet1 = ð2; + serial2 = &usart1; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + + adc1: adc@0 { + status = "okay"; + + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + * + * The pinmux pins must be set as ANALOG, use datasheet + * DS13483 Table 7. STM32MP135C/F ball definitions to + * find out which 'pin name' maps to which 'additional + * functions', which lists the mapping between pin and + * ADC channel. In this case, PA5 maps to ADC1_INP2 and + * PF13 maps to ADC1_INP11 . + */ + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; + + channel@11 { + reg = <11>; + st,min-sample-time-ns = <5000>; + }; + + /* Expansion connector: INP12:pin29 */ + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +ð1 { + status = "okay"; + pinctrl-0 = <ð1_rgmii_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + st,ext-phyclk; + nvmem-cells = <ðernet_mac1_address>; + nvmem-cell-names = "mac-address"; + + mdio1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð2 { + status = "okay"; + pinctrl-0 = <ð2_rgmii_pins_a>; + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + st,ext-phyclk; + nvmem-cells = <ðernet_mac2_address>; + nvmem-cell-names = "mac-address"; + + mdio1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy2: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpiog>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "DHSBC_USB_PWR_CC1", "", "", + "", "", "", "DHSBC_nETH1_RST", + "", "DHCOR_HW-CODING_0", "", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "", "", "DHCOR_BT_HOST_WAKE", + "", "", "", "", + "", "DHSBC_nTPM_CS", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "DHCOR_RAM-CODING_0", "", "", + "", "DHCOR_RAM-CODING_1", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "DHSBC_nTPM_RST", "", "", + "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", ""; +}; + +&gpiof { + gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "", + "", "", "", "", + "", "", "", "", + "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "", + "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; +}; + +&gpioi { + gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", + "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", + "DHSBC_BOOT0", "DHSBC_BOOT1", + "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS"; +}; + +&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + status = "okay"; +}; + +&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */ + clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>; + pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>; +}; + +&scmi_voltd { + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_sleep_pins_a>; + cs-gpios = <&gpiob 13 0>; + status = "okay"; + + st33htph: tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + cs-gpios = <&gpiof 3 0>; + status = "disabled"; +}; + +&timers5 { /* Expansion connector: CH3:pin31 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&timers13 { /* Expansion connector: CH1:pin32 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm13_pins_a>; + pinctrl-1 = <&pwm13_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@12 { + status = "okay"; + }; +}; + +&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b>; + pinctrl-1 = <&usart1_sleep_pins_b>; + pinctrl-2 = <&usart1_idle_pins_b>; + status = "okay"; +}; + +&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + pinctrl-2 = <&usart2_idle_pins_b>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb33d-supply = <&usb33>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + self-powered; + type = "micro"; + }; +}; diff --git a/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi new file mode 100644 index 00000000000..ddad6497775 --- /dev/null +++ b/arch/arm/dts/stm32mp13xx-dhcor-som.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/st,stpmic1.h> +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "DH electronics STM32MP13xx DHCOR SoM"; + compatible = "dh,stm32mp131a-dhcor-som", + "st,stm32mp131"; + + aliases { + mmc0 = &sdmmc2; + mmc1 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + rtc0 = &rv3032; + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&vin>; + ldo2-supply = <&vin>; + ldo3-supply = <&vin>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcpu: buck1 { /* VDD_CPU_1V2 */ + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { /* VDD_DDR_1V35 */ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { /* VDD_3V3_1V8 */ + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vddcore: buck4 { /* VDD_CORE_1V2 */ + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_adc: ldo1 { /* VDD_ADC_1V8 */ + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */ + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vdd_ldo3: ldo3 { /* LDO3_OUT */ + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO3 0>; + }; + + vdd_usb: ldo4 { /* VDD_USB_3V3 */ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */ + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO5 0>; + }; + + vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */ + regulator-name = "vdd_sd2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { /* VREF_DDR_0V675 */ + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { /* BST_OUT_5V2 */ + regulator-name = "bst_out"; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; /* ST M24256 */ + reg = <0x50>; + pagesize = <64>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* Console UART */ +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_b>; + pinctrl-1 = <&uart4_sleep_pins_b>; + pinctrl-2 = <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed = <3000000>; + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + }; +}; + +/* SDIO WiFi */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + mmc-pwrseq = <&sdio_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 1YN */ + reg = <1>; + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + interrupt-parent = <&gpioe>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + bus-width = <8>; + mmc-ddr-3_3v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi new file mode 100644 index 00000000000..30e3b91bccc --- /dev/null +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp13-u-boot.dtsi" + +/ { + aliases { + eeprom0 = &eeprom0; + }; + + config { + dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>; + dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>; + }; +}; + +&flash0 { + bootph-pre-ram; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@80000 { + label = "u-boot"; + reg = <0x00080000 0x00360000>; + }; + partition@3e0000 { + label = "u-boot-env-a"; + reg = <0x003e0000 0x00010000>; + }; + partition@3f0000 { + label = "u-boot-env-b"; + reg = <0x003f0000 0x00010000>; + }; + }; +}; + +&sdmmc1 { + status = "disabled"; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; +}; diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e2..d07fdcf4bc3 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; }; - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; + cfg = < 3 124 5 9 9 PQR(1,1,1) >; bootph-all; }; }; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 17bcf56f744..4cc5e076838 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,13 +75,15 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; + phy-reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + st,ext-phyclk; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; + phy0: ethernet-phy@7 { + reg = <7>; }; }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index 1ef9ac29cea..90625bf6b60 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -11,5 +11,7 @@ / { model = "DH Electronics STM32MP15xx DHCOM DRC02"; - compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcom-drc02", + "dh,stm32mp15xx-dhcom-som", + "st,stm32mp1xx"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts index e2e01e2146c..b2e450aa13b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts @@ -11,5 +11,7 @@ / { model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; - compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x"; + compatible = "dh,stm32mp15xx-dhcom-pdk2", + "dh,stm32mp15xx-dhcom-som", + "st,stm32mp15x"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts index 06770b47873..3e908102f61 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts @@ -11,5 +11,7 @@ / { model = "DH Electronics STM32MP15xx DHCOM PicoITX"; - compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcom-picoitx", + "dh,stm32mp15xx-dhcom-som", + "st,stm32mp1xx"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 1b445619325..d7b78cdcfa9 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -26,6 +26,7 @@ u-boot,error-led = "error"; dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; + dh,mac-coding-gpios = <&gpioc 3 0>; }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index 76ac5a873c1..dd8fcecbca5 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -14,5 +14,7 @@ / { model = "Arrow Electronics STM32MP15xx Avenger96 board"; - compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x"; + compatible = "arrow,stm32mp15xx-avenger96", + "dh,stm32mp15xx-dhcor-som", + "st,stm32mp15x"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts index 77dd944ff53..c1f99c1685e 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts @@ -12,5 +12,7 @@ / { model = "DH electronics STM32MP15xx DHCOR DRC Compact"; - compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcor-drc-compact", + "dh,stm32mp15xx-dhcor-som", + "st,stm32mp1xx"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts index c9163e1c028..5fdd762ddbf 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts @@ -9,7 +9,9 @@ / { model = "DH electronics STM32MP15xx DHCOR Testbench"; - compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcor-testbench", + "dh,stm32mp15xx-dhcor-som", + "st,stm32mp1xx"; aliases { ethernet0 = ðernet0; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 5889d436edb..e08a7840d8e 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -46,8 +46,8 @@ status = "okay"; reg = <0x0 0xff100000 0x1000>; clock-names = "clk_sys", "clk_flash"; - #address-cells = <2>; - #size-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; arasan,has-mdma; num-cs = <2>; nand@0 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 53a606c340a..34f592c1a85 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -314,19 +314,76 @@ ranges; }; - remoteproc { + rproc_lockstep: remoteproc@ffe00000 { compatible = "xlnx,zynqmp-r5fss"; xlnx,cluster-mode = <1>; + xlnx,tcm-mode = <1>; - r5f-0 { + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, + <0x0 0x20000 0x0 0x10000>, + <0x0 0x10000 0x0 0x10000>, + <0x0 0x30000 0x0 0x10000>; + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>; + }; + }; + + rproc_split: remoteproc-split@ffe00000 { + status = "disabled"; + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + xlnx,tcm-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_0>; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; memory-region = <&rproc_0_fw_image>; }; - r5f-1 { + r5f@1 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_1>; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_1_fw_image>; }; }; diff --git a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h new file mode 100644 index 00000000000..683e3d412ce --- /dev/null +++ b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ +#ifndef ARCH_ADI_SC5XX_SC5XX_H +#define ARCH_ADI_SC5XX_SC5XX_H + +#include <linux/types.h> + +#define TWI0_CLKDIV 0x31001400 // TWI0 SCL Clock Divider Register +#define TWI1_CLKDIV 0x31001500 // TWI1 SCL Clock Divider Register +#define TWI2_CLKDIV 0x31001600 // TWI2 SCL Clock Divider Register + +const char *sc5xx_get_boot_mode(u32 *bmode); +void sc5xx_enable_rgmii(void); + +void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base); +void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end); +void sc5xx_enable_pmu(void); + +/** + * Per-SoC init function to be used to initialize hw-specific things. Examples: + * enable PMU on armv7, enable coresight timer on armv8, etc. + */ +void sc5xx_soc_init(void); + +/* + * Reconfigure SPI memory map region for OSPI use. The adi-spi3 driver + * does not use the memory map, while the OSPI driver requires it. Only + * available on sc59x and sc59x-64 + */ +void sc59x_remap_ospi(void); + +#endif diff --git a/arch/arm/include/asm/arch-adi/sc5xx/soc.h b/arch/arm/include/asm/arch-adi/sc5xx/soc.h new file mode 100644 index 00000000000..430dbe2dae4 --- /dev/null +++ b/arch/arm/include/asm/arch-adi/sc5xx/soc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef BOARD_ADI_COMMON_SOC_H +#define BOARD_ADI_COMMON_SOC_H + +#include <phy.h> + +void fixup_dp83867_phy(struct phy_device *phydev); + +#endif diff --git a/arch/arm/include/asm/arch-adi/sc5xx/spl.h b/arch/arm/include/asm/arch-adi/sc5xx/spl.h new file mode 100644 index 00000000000..c215e6b892a --- /dev/null +++ b/arch/arm/include/asm/arch-adi/sc5xx/spl.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ +#ifndef ARCH_ADI_SC5XX_SPL_H +#define ARCH_ADI_SC5XX_SPL_H + +#include <linux/types.h> + +struct adi_boot_args { + phys_addr_t addr; + u32 flags; + u32 cmd; +}; + +extern u32 bmode; + +/** + * This table stores the arguments to the rom boot function per bootmode, + * and it is populated per SoC in the corresponding SoC support file (sc7x, sc58x, + * and so on). + */ +extern const struct adi_boot_args adi_rom_boot_args[8]; + +/** + * Struct layout for the boot config is also specific to an SoC, so you should + * only access it inside an SoC-specific boot hook function, which will be called + * from the boot rom while going from SPL to proper u-boot + */ +struct ADI_ROM_BOOT_CONFIG; +int32_t adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *cfg, int32_t cause); + +typedef void (*adi_rom_boot_fn)(void *address, uint32_t flags, int32_t count, + void *hook, uint32_t command); + +extern adi_rom_boot_fn adi_rom_boot; + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h index 8e3d55f3e76..393bc7a6a8a 100644 --- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h +++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -10,6 +10,8 @@ #ifndef __CLK_SYNTHESIZER_H #define __CLK_SYNTHESIZER_H +#include <linux/types.h> + #define CLK_SYNTHESIZER_ID_REG 0x0 #define CLK_SYNTHESIZER_XCSEL 0x05 #define CLK_SYNTHESIZER_MUX_REG 0x14 diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index 50d6a6bc760..a415693de6e 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -140,6 +140,7 @@ #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) #ifndef __ASSEMBLY__ +#include <linux/types.h> struct ast2500_clk_priv { struct ast2500_scu *scu; diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h index 251bfa269bf..a2c8852db84 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -125,6 +125,8 @@ #define SCU_MISC_CTRL1_UART5_DIV BIT(12) #ifndef __ASSEMBLY__ +#include <linux/types.h> + struct ast2600_scu { uint32_t prot_key1; /* 0x000 */ uint32_t chip_id1; /* 0x004 */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 9e29350ca4b..a02bec9371c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -7,6 +7,8 @@ #ifndef __FSL_SERDES_H__ #define __FSL_SERDES_H__ +#include <linux/types.h> + #ifdef CONFIG_FSL_LSCH3 enum srds_prtcl { /* diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 9794db04499..147ca2f99de 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -6,6 +6,7 @@ #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ #define __ARCH_FSL_LSCH2_IMMAP_H__ +#include <config.h> #include <fsl_immap.h> #ifndef __ASSEMBLY__ #include <linux/bitops.h> diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index c14855d177e..1f81d91977c 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/types.h> -#include <asm/arch/ddr.h> +#include <asm/arch/imx-regs.h> #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR_0 0x3f400000 diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index 9244e0a78fd..35e3ec7a987 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -6,6 +6,8 @@ #ifndef __FSL_SERDES_H #define __FSL_SERDES_H +#include <linux/types.h> + enum srds_prtcl { /* * Nobody will check whether the device 'NONE' has been configured, diff --git a/arch/arm/include/asm/arch-meson/usb-gx.h b/arch/arm/include/asm/arch-meson/usb-gx.h deleted file mode 100644 index 61f1809df9c..00000000000 --- a/arch/arm/include/asm/arch-meson/usb-gx.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _ARCH_MESON_USB_GX_H_ -#define _ARCH_MESON_USB_GX_H_ - -#include <generic-phy.h> -#include <linux/usb/otg.h> - -/* TOFIX add set_mode to struct phy_ops */ -void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode); - -int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode); - -#endif diff --git a/arch/arm/include/asm/arch-meson/usb.h b/arch/arm/include/asm/arch-meson/usb.h deleted file mode 100644 index b794b5ce77a..00000000000 --- a/arch/arm/include/asm/arch-meson/usb.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef __MESON_USB_H__ -#define __MESON_USB_H__ - -int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode); - -#endif /* __MESON_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index d585b5cf4b2..58013a85951 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -7,6 +7,8 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <stdbool.h> + #ifdef CONFIG_SYS_MX5_HCLK #define MXC_HCLK CONFIG_SYS_MX5_HCLK #else diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h index 634736cc09c..5da0037b2c6 100644 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -7,6 +7,8 @@ #include <asm/mach-imx/sys_proto.h> +struct wdog_regs; + void set_wdog_reset(struct wdog_regs *wdog); #endif /* __SYS_PROTO_IMX7_ */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index ecf3b4e7428..e736772fda7 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_BOOTROM_H #define _ASM_ARCH_BOOTROM_H +#include <linux/types.h> + /* * Saved Stack pointer address. * Access might be needed in some special cases. diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index f01c5aeb71c..73e5283108b 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_CLOCK_H #define _ASM_ARCH_CLOCK_H +#include <linux/types.h> + struct udevice; /* define pll mode */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h index a995bb950d9..f4bbc240131 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARCH_GRF_rk3308_H #define _ASM_ARCH_GRF_rk3308_H +#include <linux/kernel.h> + struct rk3308_grf { unsigned int gpio0a_iomux; unsigned int reserved0; diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h index 5ab9b2809f2..e26459fdd3b 100644 --- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h +++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h @@ -8,6 +8,8 @@ #ifndef _SUNXI_PMIC_BUS_H #define _SUNXI_PMIC_BUS_H +#include <linux/types.h> + int pmic_bus_init(void); int pmic_bus_read(u8 reg, u8 *data); int pmic_bus_write(u8 reg, u8 data); diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h index 46cd87e79e8..4fbb4b91c86 100644 --- a/arch/arm/include/asm/arch-sunxi/tve.h +++ b/arch/arm/include/asm/arch-sunxi/tve.h @@ -9,6 +9,8 @@ #ifndef _TVE_H #define _TVE_H +#include <linux/types.h> + enum tve_mode { tve_mode_vga, tve_mode_composite_pal, diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 78aeb25ac78..b922b2d30ea 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -4,6 +4,7 @@ * NVIDIA Corporation <www.nvidia.com> */ #include <asm/types.h> +#include <asm/arch-tegra/tegra.h> /* Stabilization delays, in usec */ #define PLL_STABILIZATION_DELAY (300) diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h index 4e1da98d1f2..d0ba83ae8bc 100644 --- a/arch/arm/include/asm/arch-tegra/cboot.h +++ b/arch/arm/include/asm/arch-tegra/cboot.h @@ -6,6 +6,8 @@ #ifndef _TEGRA_CBOOT_H_ #define _TEGRA_CBOOT_H_ +#include <linux/errno.h> +#include <linux/types.h> #include <net.h> #ifdef CONFIG_ARM64 diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index fe7b3a50e0d..3c1838cf137 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -6,6 +6,7 @@ #ifndef _TEGRA_GPIO_H_ #define _TEGRA_GPIO_H_ +#include <linux/types.h> #include <dt-bindings/gpio/tegra-gpio.h> #define TEGRA_GPIOS_PER_PORT 8 diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index afec6bbdda3..dc8db391221 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/types.h> +#include <asm/arch/tegra.h> struct udevice; diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index ce655ce7a95..0ab681c893d 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -51,7 +51,7 @@ #define PTE_TABLE_PXN (1UL << 59) #define PTE_TABLE_XN (1UL << 60) -#define PTE_TABLE_AP (1UL << 61) +#define PTE_TABLE_AP (3UL << 61) #define PTE_TABLE_NS (1UL << 63) /* @@ -129,6 +129,62 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) asm volatile("isb"); } +static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr) +{ + if (el == 1) { + asm volatile("mrs %0, ttbr0_el1" : "=r" (*table)); + asm volatile("mrs %0, tcr_el1" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el1" : "=r" (*attr)); + } else if (el == 2) { + asm volatile("mrs %0, ttbr0_el2" : "=r" (*table)); + asm volatile("mrs %0, tcr_el2" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el2" : "=r" (*attr)); + } else if (el == 3) { + asm volatile("mrs %0, ttbr0_el3" : "=r" (*table)); + asm volatile("mrs %0, tcr_el3" : "=r" (*tcr)); + asm volatile("mrs %0, mair_el3" : "=r" (*attr)); + } else { + hang(); + } +} + +/** + * typedef pte_walker_cb_t - callback function for walk_pagetable. + * + * This function is called when the walker finds a table entry + * or after parsing a block or pages. For a table the @end address + * is 0, and @addr is the address of the table. Otherwise, they + * are the start and end physical addresses of the block or page. + * + * @addr: PTE start address (PA), or address of table. Includes attributes. + * @end: End address of the region (or 0 for a table) + * @va_bits: Number of bits in the virtual address + * @level: Table level + * @priv: Private data for the callback + * + * Return: true to stop walking, false to continue + */ +typedef bool (*pte_walker_cb_t)(u64 addr, u64 end, int va_bits, int level, void *priv); + +/** + * walk_pagetable() - Walk the pagetable at ttbr and call @cb for each region + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + * @cb: Callback function to call for each entry + * @priv: Private data for the callback + */ +void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv); + +/** + * dump_pagetable() - Dump the pagetable at ttbr, printing each region and + * level. + * + * @ttbr: Address of the pagetable to dump + * @tcr: TCR value to use + */ +void dump_pagetable(u64 ttbr, u64 tcr); + struct mm_region { u64 virt; u64 phys; diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h index f19e4e726a1..99488730998 100644 --- a/arch/arm/include/asm/esr.h +++ b/arch/arm/include/asm/esr.h @@ -7,6 +7,7 @@ #ifndef __ASM_ESR_H #define __ASM_ESR_H +#include <stdbool.h> #include <asm/memory.h> #include <linux/const.h> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 452bcd1b8fd..45401d5e3c8 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -12,6 +12,7 @@ #include <config.h> #include <linux/types.h> +#include <asm/u-boot.h> /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arm/include/asm/mach-imx/gpio.h b/arch/arm/include/asm/mach-imx/gpio.h index 1b7c9cd5249..25763526f5f 100644 --- a/arch/arm/include/asm/mach-imx/gpio.h +++ b/arch/arm/include/asm/mach-imx/gpio.h @@ -9,6 +9,8 @@ #define __ASM_ARCH_IMX_GPIO_H #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <linux/types.h> + /* GPIO registers */ struct gpio_regs { u32 gpio_dr; /* data */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 43f7503571d..7e30cac32a0 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -69,8 +69,10 @@ /* * CNTHCTL_EL2 bits definitions */ -#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ -#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ +#define CNTHCTL_EL2_EVNT_EN BIT(2) /* Enable the event stream */ +#define CNTHCTL_EL2_EVNT_I(val) ((val) << 4) /* Event stream trigger bits */ +#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ +#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ /* * HCR_EL2 bits definitions @@ -154,6 +156,13 @@ enum dcache_option { "wfi" : : : "memory"); \ }) +#define wfe() \ + ({asm volatile( \ + "wfe" : : : "memory"); \ + }) + +#define sev() asm volatile("sev") + static inline unsigned int current_el(void) { unsigned long el; @@ -369,6 +378,8 @@ void switch_to_hypervisor_ret(void); #ifdef __ARM_ARCH_7A__ #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") +#define wfe() __asm__ __volatile__ ("wfe" : : : "memory") +#define sev() __asm__ __volatile__ ("sev") #else #define wfi() #endif diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 38a1a6ea0d7..84fe01e3b71 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -9,6 +9,7 @@ #ifndef _DAVINCI_NAND_H_ #define _DAVINCI_NAND_H_ +#include <config.h> #include <asm/arch/hardware.h> #define NAND_READ_START 0x00 diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 181a8ac4c27..9afd8375999 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -16,7 +16,6 @@ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> */ -#include <common.h> #include <linux/kbuild.h> #include <linux/arm-smccc.h> diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index b88b01eefdc..7c49462c8eb 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/global_data.h> #include <asm/mach-types.h> diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 29020bd1c6b..2671f9a0ebf 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -14,7 +14,6 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ -#include <common.h> #include <fdt_support.h> #ifdef CONFIG_ARMV7_NONSEC #include <asm/armv7.h> diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f30a483ed8b..192c120a7d2 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -11,7 +11,6 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ -#include <common.h> #include <bootm.h> #include <bootstage.h> #include <command.h> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0893915b300..947012f2996 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <cpu_func.h> #include <log.h> #include <asm/global_data.h> diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index d05314ee57f..0afd3880447 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -9,7 +9,6 @@ #include <asm/armv7.h> #include <asm/pl310.h> #include <config.h> -#include <common.h> struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 7a160158671..b2ae74a59f1 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -6,7 +6,7 @@ /* for now: just dummy functions to satisfy the linker */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <log.h> #include <malloc.h> diff --git a/arch/arm/lib/cmd_boot.c b/arch/arm/lib/cmd_boot.c index c905ecc4bd9..5df5bc305a2 100644 --- a/arch/arm/lib/cmd_boot.c +++ b/arch/arm/lib/cmd_boot.c @@ -17,7 +17,6 @@ * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> */ -#include <common.h> #include <command.h> /* diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index f7029918d4f..0a96ba1355f 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -5,7 +5,9 @@ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> */ -#include <common.h> +#include <stdio.h> +#include <linux/stddef.h> +#include <linux/string.h> int raise (int signum) { diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index f4bbd21da91..2cc0a32f9d4 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -2,7 +2,6 @@ /* * Copyright 2019 Broadcom. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <asm/gic.h> diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index e394c1ad909..1f672eee2c8 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <image.h> #include <mapmem.h> #include <asm/global_data.h> diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 9961472f69f..333a5026a46 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -18,7 +18,6 @@ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> */ -#include <common.h> #include <cpu_func.h> #include <efi_loader.h> #include <irq_func.h> diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 125dc0bb390..b3024ba514e 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -4,7 +4,6 @@ * David Feng <fenghua@phytium.com.cn> */ -#include <common.h> #include <asm/esr.h> #include <asm/global_data.h> #include <asm/ptrace.h> diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 277854aa878..b977961bde8 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -4,9 +4,10 @@ * Kamil Lulko, <kamil.lulko@gmail.com> */ -#include <common.h> +#include <stdio.h> #include <cpu_func.h> #include <irq_func.h> +#include <vsprintf.h> /* * Upon exception entry ARMv7-M processors automatically save stack diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 903b3357048..be800a3bc9e 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -3,7 +3,6 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include <common.h> #include <asm/cache.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 3e051e36f12..c9796a4435c 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -20,7 +20,6 @@ * (C) Copyright 2004 Texas Insturments */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c index b286bac9bf0..4357acaef6c 100644 --- a/arch/arm/lib/save_prev_bl_data.c +++ b/arch/arm/lib/save_prev_bl_data.c @@ -10,7 +10,6 @@ #include <fdtdec.h> #include <fdt_support.h> #include <fdt.h> -#include <common.h> #include <linux/errno.h> #include <asm/system.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index db5463b2bbb..07efabaa7dc 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -23,4 +23,3 @@ char __secure_start[0] __section(".__secure_start"); char __secure_end[0] __section(".__secure_end"); char __secure_stack_start[0] __section(".__secure_stack_start"); char __secure_stack_end[0] __section(".__secure_stack_end"); -char _end[0] __section(".__end"); diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index b13897495da..c43a63f1819 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -7,7 +7,6 @@ * Tom Rini <trini@ti.com> */ -#include <common.h> #include <config.h> #include <init.h> #include <log.h> diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index 656084c7e51..ea1b937add7 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -10,7 +10,6 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> */ -#include <common.h> #include <init.h> #include <lmb.h> #include <asm/global_data.h> diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c index 45e9c4506a9..51287251b3f 100644 --- a/arch/arm/lib/zimage.c +++ b/arch/arm/lib/zimage.c @@ -6,7 +6,6 @@ * bootz code: * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com> */ -#include <common.h> #include <image.h> #define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 7a6151a9722..8bace3005eb 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> */ -#include <common.h> #include <dm.h> #include <dm/uclass-internal.h> #include <efi_loader.h> diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c index a550b553b66..b8f4771e5e7 100644 --- a/arch/arm/mach-apple/rtkit.c +++ b/arch/arm/mach-apple/rtkit.c @@ -4,13 +4,14 @@ * (C) Copyright 2021 Copyright The Asahi Linux Contributors */ -#include <common.h> #include <mailbox.h> #include <malloc.h> #include <asm/arch/rtkit.h> #include <linux/apple-mailbox.h> #include <linux/bitfield.h> +#include <linux/errno.h> +#include <linux/types.h> #define APPLE_RTKIT_EP_MGMT 0 #define APPLE_RTKIT_EP_CRASHLOG 1 diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index bae10271844..531c2ad1562 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -2,7 +2,7 @@ /* * Copyright (c) 2016 Google, Inc */ -#include <common.h> +#include <config.h> #include <dm.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c index 02bd3f67c96..50d7f99b264 100644 --- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <asm/io.h> #include <asm/arch/scu_ast2500.h> diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index dc6cdc35d15..4c0b705ea88 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -2,7 +2,7 @@ /* * Copyright (c) Aspeed Technology Inc. */ -#include <common.h> +#include <config.h> #include <dm.h> #include <ram.h> #include <timer.h> diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 0952e73a457..05390c16f3a 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -2,7 +2,6 @@ /* * Copyright (c) Aspeed Technology Inc. */ -#include <common.h> #include <debug_uart.h> #include <dm.h> #include <spl.h> diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index ada6570d971..9502a7384b5 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -61,11 +61,7 @@ SECTIONS __rel_dyn_end = .; } > .nor - .end : - { - *(.__end) - } > .nor - + _end = .; _image_binary_end = .; .bss : { diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c index 5bc442ef33c..c420940d1cb 100644 --- a/arch/arm/mach-aspeed/ast_wdt.c +++ b/arch/arm/mach-aspeed/ast_wdt.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Google, Inc */ -#include <common.h> #include <asm/io.h> #include <asm/arch/wdt.h> #include <linux/err.h> diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c index c849885bc2b..459edadb587 100644 --- a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c @@ -10,7 +10,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index 09ac66d619d..ac55a61be64 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -7,7 +7,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ -#include <common.h> +#include <config.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 9bf03fd68ec..579e76b339d 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -10,7 +10,7 @@ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/io.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-at91/arm920t/reset.c b/arch/arm/mach-at91/arm920t/reset.c index 91e375146ad..7582cef417f 100644 --- a/arch/arm/mach-at91/arm920t/reset.c +++ b/arch/arm/mach-at91/arm920t/reset.c @@ -13,7 +13,6 @@ * Alex Zuepke <azu@sysgo.de> */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index 8ef5764e315..f7b4116344c 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -13,7 +13,7 @@ * Alex Zuepke <azu@sysgo.de> */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index c10571fa28a..201c99ade4e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <dm.h> #include <asm/io.h> #include <asm/arch/at91sam9260_matrix.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c index 0c2b9f2ecc9..b8d209cbec8 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c index 3b8a4623866..1749662dae9 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c @@ -9,7 +9,6 @@ * esd electronic system design gmbh <www.esd.eu> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index d517810c991..4c481484c3d 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <dm.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index 9f98ce7a45c..4dc6e51aba8 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -4,7 +4,6 @@ * Josh Wu <josh.wu@atmel.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pio.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c index b4002eb7504..4f5bafb8c2e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c @@ -5,7 +5,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index f44760bed31..40c8a58b563 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Atmel Corporation */ -#include <common.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index 013daf43b74..241de6a5378 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -7,7 +7,8 @@ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ -#include <common.h> +#include <config.h> +#include <time.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 5e84b0a40e1..e476cd5bcf3 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -6,7 +6,7 @@ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ -#include <common.h> +#include <config.h> #include <init.h> #include <vsprintf.h> #include <asm/io.h> diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index aade13cc014..bb66700566e 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -42,7 +42,6 @@ * someone puts a jffs2 into them) * do a read-modify-write for partially programmed pages */ -#include <common.h> #include <display_options.h> #include <flash.h> #include <log.h> diff --git a/arch/arm/mach-at91/arm926ejs/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c index 6acbfa33011..01b2663f96c 100644 --- a/arch/arm/mach-at91/arm926ejs/reset.c +++ b/arch/arm/mach-at91/arm926ejs/reset.c @@ -5,7 +5,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c index e3d3dd880ca..97c572deaaf 100644 --- a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c +++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries */ -#include <common.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index a8cf0e4bd79..137a5e5b8fd 100644 --- a/arch/arm/mach-at91/arm926ejs/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -5,7 +5,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 1a8bf94dee0..09cf838cf96 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -33,12 +33,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 6bfa02d1d0a..5357b4cffc2 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -9,7 +9,7 @@ * Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com> */ -#include <common.h> +#include <config.h> #include <asm/global_data.h> #include <linux/delay.h> #include <linux/errno.h> diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 5ea7e2609f5..f4b2f4f351c 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -8,7 +8,7 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <init.h> #include <vsprintf.h> diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index edc20574c31..469c2211766 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -4,7 +4,6 @@ * Wenyou Yang <wenyou.yang@atmel.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clk.h> #include <asm/arch/sama5d2.h> diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 04b700a94d7..67b63208eda 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -4,7 +4,6 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> #include <asm/arch/sama5d3.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index e68ae994078..76fff9cd466 100644 --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -4,7 +4,6 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c index 1f54c5dcad9..bfdb75ce39a 100644 --- a/arch/arm/mach-at91/armv7/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c @@ -8,7 +8,6 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index 6ca725fc4ce..460a91d93ec 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -40,12 +40,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 62108d2bd0a..019ef930022 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -4,7 +4,7 @@ * Wenyou Yang <wenyou.yang@atmel.com> */ -#include <common.h> +#include <config.h> #include <asm/hardware.h> #include <asm/io.h> #include <asm/arch/at91_sfr.h> diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 8344daeb39a..442b822fe77 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -4,8 +4,8 @@ * Wenyou Yang <wenyou.yang@atmel.com> */ -#include <common.h> #include <dm.h> +#include <time.h> #include <wdt.h> #include <asm/io.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index f7b411cf7df..683e539b1b3 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -8,6 +8,8 @@ #ifndef AT91_COMMON_H #define AT91_COMMON_H +#include <linux/types.h> + void at91_can_hw_init(void); void at91_gmac_hw_init(void); void at91_macb_hw_init(void); diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c index 2fa8493a0bd..3bef5648d4a 100644 --- a/arch/arm/mach-at91/matrix.c +++ b/arch/arm/mach-at91/matrix.c @@ -4,7 +4,6 @@ * Wenyou Yang <wenyou.yang@atmel.com> */ -#include <common.h> #include <asm/hardware.h> #include <asm/io.h> #include <asm/arch/sama5_matrix.h> diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index 5422c05456e..ac6a719d9c0 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -7,7 +7,6 @@ * Wenyou Yang <wenyou.yang@atmel.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/atmel_mpddrc.h> #include <asm/arch/at91_common.h> diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c index f4484a77c7d..ec38f5bc931 100644 --- a/arch/arm/mach-at91/phy.c +++ b/arch/arm/mach-at91/phy.c @@ -11,7 +11,7 @@ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de */ -#include <common.h> +#include <time.h> #include <asm/hardware.h> #include <asm/io.h> #include <linux/delay.h> diff --git a/arch/arm/mach-at91/sdram.c b/arch/arm/mach-at91/sdram.c index 6638aa82bb6..be3e91c7dba 100644 --- a/arch/arm/mach-at91/sdram.c +++ b/arch/arm/mach-at91/sdram.c @@ -9,7 +9,6 @@ * Lead Tech Design <www.leadtechdesign.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91sam9_sdramc.h> diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 8d537998c98..5feb8f73551 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -4,7 +4,6 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> #include <hang.h> #include <asm/io.h> #include <asm/arch/at91_common.h> diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index dfba9f730c1..cde1700a283 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -8,7 +8,7 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> +#include <config.h> #include <hang.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index a30c4f6c075..62a7df8a195 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -4,7 +4,7 @@ * Bo Shen <voice.shen@atmel.com> */ -#include <common.h> +#include <config.h> #include <hang.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 016bc1eb412..1b459707bc6 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -6,7 +6,6 @@ * project. */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <dm/device.h> diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c index da9faafe1dd..c7cbfa72ffc 100644 --- a/arch/arm/mach-bcm283x/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c @@ -3,9 +3,9 @@ * (C) Copyright 2012 Stephen Warren */ -#include <common.h> #include <cpu_func.h> #include <log.h> +#include <time.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/arch/base.h> diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index 2188b38d84b..4993c0bdb81 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -3,7 +3,6 @@ * (C) Copyright 2012 Stephen Warren */ -#include <common.h> #include <memalign.h> #include <phys2bus.h> #include <asm/arch/mbox.h> diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index f13ac0c6375..9199234917f 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -6,7 +6,7 @@ * project. */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <asm/io.h> #include <asm/arch/base.h> diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c index 5ab04083cc6..ca403bae991 100644 --- a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c index 52a53a2c76d..b11effe0667 100644 --- a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c index c6b7a54fbdf..a883e74ac00 100644 --- a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c index fe7efb30e22..eb3cc3e5aec 100644 --- a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c index eb736bf7d50..458624e87aa 100644 --- a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c index 8e53b4929eb..83c07727573 100644 --- a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c index 898291075f5..82aba326dcb 100644 --- a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c @@ -2,7 +2,6 @@ /* * Copyright 2022 Broadcom Ltd. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index dae60262f5b..7c0a2638977 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -4,7 +4,7 @@ * Copyright (C) 2009 David Brownell */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <init.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 08c8f592524..936b5e11667 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include <common.h> +#include <config.h> #include <init.h> #include <nand.h> #include <ns16550.h> diff --git a/arch/arm/mach-davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c index f2536c8dd6d..4ee3cd0d5b3 100644 --- a/arch/arm/mach-davinci/da850_pinmux.c +++ b/arch/arm/mach-davinci/da850_pinmux.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 OMICRON electronics GmbH */ -#include <common.h> #include <asm/arch/davinci_misc.h> #include <asm/arch/hardware.h> #include <asm/arch/pinmux_defs.h> diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 1133a23bdee..0d0ad1e593e 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -6,6 +6,7 @@ #ifndef __MISC_H #define __MISC_H +#include <linux/types.h> #include <asm/arch/hardware.h> /* pin muxer definitions */ diff --git a/arch/arm/mach-davinci/include/mach/timer_defs.h b/arch/arm/mach-davinci/include/mach/timer_defs.h index 110e67e454c..a25f6d1796a 100644 --- a/arch/arm/mach-davinci/include/mach/timer_defs.h +++ b/arch/arm/mach-davinci/include/mach/timer_defs.h @@ -20,24 +20,4 @@ struct davinci_timer { u_int32_t wdtcr; }; -#define DV_TIMER_TCR_ENAMODE_MASK 3 - -#define DV_TIMER_TCR_ENAMODE12_SHIFT 6 -#define DV_TIMER_TCR_CLKSRC12_SHIFT 8 -#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10 -#define DV_TIMER_TCR_CAPMODE12_SHIFT 11 -#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12 -#define DV_TIMER_TCR_ENAMODE34_SHIFT 22 -#define DV_TIMER_TCR_CLKSRC34_SHIFT 24 -#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26 -#define DV_TIMER_TCR_CAPMODE34_SHIFT 27 -#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28 - -#define DV_WDT_ENABLE_SYS_RESET 0x00020000 -#define DV_WDT_TRIGGER_SYS_RESET 0x00020002 - -#ifdef CONFIG_HW_WATCHDOG -void davinci_hw_watchdog_enable(void); -void davinci_hw_watchdog_reset(void); -#endif #endif /* _TIMER_DEFS_H_ */ diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index cfad28c43d0..6c97e5810cd 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -8,7 +8,7 @@ * Copyright (C) 2004 Texas Instruments. */ -#include <common.h> +#include <config.h> #include <env.h> #include <i2c.h> #include <init.h> diff --git a/arch/arm/mach-davinci/pinmux.c b/arch/arm/mach-davinci/pinmux.c index 7904257b4a4..5ecb434b03b 100644 --- a/arch/arm/mach-davinci/pinmux.c +++ b/arch/arm/mach-davinci/pinmux.c @@ -8,7 +8,6 @@ * Copyright (C) 2004 Texas Instruments. */ -#include <common.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index dae10aa03bb..90b817860a6 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -7,7 +7,6 @@ * Copyright (C) 2004 Texas Instruments. */ -#include <common.h> #include <asm/arch/hardware.h> #include <asm/io.h> diff --git a/arch/arm/mach-davinci/reset.c b/arch/arm/mach-davinci/reset.c index 0d59eb6e3ce..e3e2c56a676 100644 --- a/arch/arm/mach-davinci/reset.c +++ b/arch/arm/mach-davinci/reset.c @@ -6,7 +6,6 @@ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> #include <asm/arch/timer_defs.h> diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 5f5b9ebbf97..8c6cf9c2192 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -3,12 +3,10 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include <common.h> #include <config.h> #include <hang.h> #include <init.h> #include <spl.h> -#include <asm/u-boot.h> #include <asm/utils.h> #include <nand.h> #include <asm/arch/dm365_lowlevel.h> diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index 83c190b620e..474dc6b1abd 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -20,7 +20,7 @@ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> @@ -98,34 +98,3 @@ ulong get_tbclk(void) { return gd->arch.timer_rate_hz; } - -#ifdef CONFIG_HW_WATCHDOG -static struct davinci_timer * const wdttimer = - (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE; - -/* - * See prufw2.pdf for using Timer as a WDT - */ -void davinci_hw_watchdog_enable(void) -{ - writel(0x0, &wdttimer->tcr); - writel(0x0, &wdttimer->tgcr); - /* TIMMODE = 2h */ - writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr); - writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12); - writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34); - writel(2 << 22, &wdttimer->tcr); - writel(0x0, &wdttimer->tim12); - writel(0x0, &wdttimer->tim34); - /* set WDEN bit, WDKEY 0xa5c6 */ - writel(0xa5c64000, &wdttimer->wdtcr); - /* clear counter register */ - writel(0xda7e4000, &wdttimer->wdtcr); -} - -void davinci_hw_watchdog_reset(void) -{ - writel(0xa5c64000, &wdttimer->wdtcr); - writel(0xda7e4000, &wdttimer->wdtcr); -} -#endif diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index f91f2ee862d..ee71b95237d 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -4,9 +4,10 @@ * Minkyu Kang <mk7.kang@samsung.com> */ -#include <common.h> #include <clock_legacy.h> #include <log.h> +#include <time.h> +#include <mach/cpu.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-exynos/clock_init_exynos4.c b/arch/arm/mach-exynos/clock_init_exynos4.c index 584e4bac09f..95ed1956a07 100644 --- a/arch/arm/mach-exynos/clock_init_exynos4.c +++ b/arch/arm/mach-exynos/clock_init_exynos4.c @@ -23,7 +23,6 @@ * MA 02111-1307 USA */ -#include <common.h> #include <config.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c index 1cb8d391e7c..232a2482dc6 100644 --- a/arch/arm/mach-exynos/clock_init_exynos5.c +++ b/arch/arm/mach-exynos/clock_init_exynos5.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Samsung Electronics */ -#include <common.h> #include <config.h> #include <asm/io.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index d7f02231fdf..4f56160ee50 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -23,6 +23,8 @@ * MA 02111-1307 USA */ +#include <linux/types.h> +#include <mach/cpu.h> #include <asm/arch/system.h> #define DMC_OFFSET 0x10000 diff --git a/arch/arm/mach-exynos/dmc_common.c b/arch/arm/mach-exynos/dmc_common.c index 44923dd5520..a96ded443b9 100644 --- a/arch/arm/mach-exynos/dmc_common.c +++ b/arch/arm/mach-exynos/dmc_common.c @@ -5,7 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include <common.h> +#include <linux/types.h> #include <asm/arch/spl.h> #include "clock_init.h" diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index cad8ccc5315..193de4c3a59 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Samsung Electronics */ -#include <common.h> #include <config.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h index e9874a8c1b2..4e508edba0c 100644 --- a/arch/arm/mach-exynos/exynos5_setup.h +++ b/arch/arm/mach-exynos/exynos5_setup.h @@ -8,6 +8,7 @@ #ifndef _SMDK5250_SETUP_H #define _SMDK5250_SETUP_H +#include <linux/types.h> #include <asm/arch/dmc.h> #define NOT_AVAILABLE 0 diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h index a3d8974dcb5..757e1586bde 100644 --- a/arch/arm/mach-exynos/include/mach/power.h +++ b/arch/arm/mach-exynos/include/mach/power.h @@ -8,6 +8,8 @@ #define __ASM_ARM_ARCH_POWER_H_ #ifndef __ASSEMBLY__ +#include <linux/types.h> + struct exynos4_power { unsigned int om_stat; unsigned char res1[0x8]; diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 5d0bebac573..0aed4c3e2bf 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -36,25 +36,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) -/* - * This instruction causes an event to be signaled to all cores - * within a multiprocessor system. If SEV is implemented, - * WFE must also be implemented. - */ -#define sev() __asm__ __volatile__ ("sev\n\t" : : ); -/* - * If the Event Register is not set, WFE suspends execution until - * one of the following events occurs: - * - an IRQ interrupt, unless masked by the CPSR I-bit - * - an FIQ interrupt, unless masked by the CPSR F-bit - * - an Imprecise Data abort, unless masked by the CPSR A-bit - * - a Debug Entry request, if Debug is enabled - * - an Event signaled by another processor using the SEV instruction. - * If the Event Register is set, WFE clears it and returns immediately. - * If WFE is implemented, SEV must also be implemented. - */ -#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); - /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index c57b8aee798..0967ab995a9 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -23,7 +23,6 @@ * MA 02111-1307 USA */ -#include <common.h> #include <config.h> #include <debug_uart.h> #include <asm/system.h> diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index 4c154950f73..fdaacc70c9b 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -4,7 +4,6 @@ * Thomas Abraham <thomas.ab@samsung.com> */ -#include <common.h> #include <asm/armv8/mmu.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index ad3fbf2da7a..4061dd4aafa 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -4,7 +4,6 @@ * Abhilash Kesavan <a.kesavan@samsung.com> */ -#include <common.h> #include <fdtdec.h> #include <log.h> #include <asm/gpio.h> diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index f2a6c00dd62..599d3ccff60 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -4,7 +4,7 @@ * Donghwa Lee <dh09.lee@samsung.com> */ -#include <common.h> +#include <mach/cpu.h> #include <asm/io.h> #include <asm/arch/power.h> diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index aff2b5e1b6e..be18f181a7a 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -4,7 +4,6 @@ * Minkyu Kang <mk7.kang@samsung.com> */ -#include <common.h> #include <cpu_func.h> #include <asm/cache.h> #include <asm/io.h> diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index 553dac75b61..bd5a06447b9 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -3,7 +3,6 @@ * Copyright (C) 2012 Samsung Electronics */ -#include <common.h> #include <config.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-exynos/system.c b/arch/arm/mach-exynos/system.c index 12d0d8fd34a..f5090613c0d 100644 --- a/arch/arm/mach-exynos/system.c +++ b/arch/arm/mach-exynos/system.c @@ -4,7 +4,7 @@ * Donghwa Lee <dh09.lee@samsung.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/system.h> diff --git a/arch/arm/mach-exynos/tzpc.c b/arch/arm/mach-exynos/tzpc.c index abe8e7f4589..320a0cf3513 100644 --- a/arch/arm/mach-exynos/tzpc.c +++ b/arch/arm/mach-exynos/tzpc.c @@ -5,7 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include <common.h> +#include <mach/cpu.h> #include <asm/arch/tzpc.h> #include <asm/io.h> diff --git a/arch/arm/mach-highbank/timer.c b/arch/arm/mach-highbank/timer.c index 2423a0e3785..32ec6f0ac0e 100644 --- a/arch/arm/mach-highbank/timer.c +++ b/arch/arm/mach-highbank/timer.c @@ -5,7 +5,6 @@ * Based on arm926ejs/mx27/timer.c */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/arch-armv7/systimer.h> diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c index a26c2066e02..84d02c9aca2 100644 --- a/arch/arm/mach-histb/board_common.c +++ b/arch/arm/mach-histb/board_common.c @@ -5,7 +5,6 @@ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <asm/system.h> diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c index 83a2bb94179..76414558379 100644 --- a/arch/arm/mach-histb/sysmap-histb.c +++ b/arch/arm/mach-histb/sysmap-histb.c @@ -5,7 +5,6 @@ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com> */ -#include <common.h> #include <asm/armv8/mmu.h> static struct mm_region histb_mem_map[] = { diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index ab9b621a2a6..b368db49fce 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <asm/armv7.h> #include <asm/cache.h> diff --git a/arch/arm/mach-imx/cmd_bmode.c b/arch/arm/mach-imx/cmd_bmode.c index 5b2f4686230..c20e80725f8 100644 --- a/arch/arm/mach-imx/cmd_bmode.c +++ b/arch/arm/mach-imx/cmd_bmode.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ -#include <common.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 2f389dbe8df..56e1a8f8be7 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -6,7 +6,7 @@ * Command for encapsulating DEK blob */ -#include <common.h> +#include <config.h> #include <command.h> #include <log.h> #include <malloc.h> @@ -17,6 +17,7 @@ #include <asm/arch/clock.h> #include <mapmem.h> #include <tee.h> +#include <vsprintf.h> #ifdef CONFIG_IMX_SECO_DEK_ENCAP #include <imx_container.h> #include <firmware/imx/sci/sci.h> @@ -394,10 +395,10 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, } /***************************************************/ -static char dek_blob_help_text[] = +U_BOOT_LONGHELP(dek_blob, "src dst len - Encapsulate and create blob of data\n" " $len bits long at address $src and\n" - " store the result at address $dst.\n"; + " store the result at address $dst.\n"); U_BOOT_CMD( dek_blob, 4, 1, do_dek_blob, diff --git a/arch/arm/mach-imx/cmd_hdmidet.c b/arch/arm/mach-imx/cmd_hdmidet.c index e2571adfb00..8104ab26b08 100644 --- a/arch/arm/mach-imx/cmd_hdmidet.c +++ b/arch/arm/mach-imx/cmd_hdmidet.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ -#include <common.h> #include <command.h> #include <asm/arch/imx-regs.h> #include <asm/arch/mxc_hdmi.h> diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 9576b48dde3..9f37e611a1e 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -11,7 +11,7 @@ #include <asm/arch/clock.h> #include <linux/compiler.h> #include <command.h> -#include <common.h> +#include <config.h> #include <env.h> #include <fsl_sec.h> #include <mapmem.h> @@ -134,12 +134,12 @@ free_m: } /***************************************************/ -static char mfgprot_help_text[] = +U_BOOT_LONGHELP(mfgprot, "Usage:\n" "Print the public key for Manufacturing Protection\n" "\tmfgprot pubk\n" "Generates a Manufacturing Protection signature\n" - "\tmfgprot sign <data_addr> <size>"; + "\tmfgprot sign <data_addr> <size>\n"); U_BOOT_CMD( mfgprot, 4, 1, do_mfgprot, diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 70a213a49dd..c2e452b6927 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <command.h> #include <log.h> #include <malloc.h> diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 488638c9058..ceee31eecd7 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -7,7 +7,6 @@ */ #include <bootm.h> -#include <common.h> #include <dm.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c index 7d787d04598..2cf684322ea 100644 --- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c +++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c @@ -7,7 +7,6 @@ * */ /* #define DEBUG */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index 7895ee66f8a..e449fa6f552 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -6,7 +6,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux-vf610.h> diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index d02316ed6cb..c13d9f0e00e 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include <common.h> #include <command.h> #include <errno.h> #include <imx_container.h> diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 27e053ef701..85d90686f68 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -3,7 +3,6 @@ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <config.h> #include <display_options.h> diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index a5866cf9f70..256db150818 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -2,8 +2,8 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ -#include <common.h> #include <malloc.h> +#include <time.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <linux/delay.h> diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 35da0ae0425..e2388e3fef8 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -3,7 +3,7 @@ * Copyright 2019 NXP */ -#include <common.h> +#include <config.h> #include <errno.h> #include <imx_container.h> #include <log.h> diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 1c072f6af11..ed44df394b1 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -3,7 +3,6 @@ * Copyright 2018-2019, 2022 NXP */ -#include <common.h> #include <command.h> #include <errno.h> #include <imx_container.h> diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 9941b57b4be..4e49b5bf375 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include <common.h> #include <asm/global_data.h> #include <linux/errno.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 6e643188f40..627baa1d83f 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -3,7 +3,6 @@ * Copyright 2018, 2021 NXP */ -#include <common.h> #include <clk.h> #include <cpu.h> #include <cpu_func.h> diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index c2bed3e0c1f..6d0585f5cc6 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include <common.h> #include <log.h> #include <firmware/imx/sci/sci.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index e4f7651bd1d..3e27d75827a 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -3,7 +3,6 @@ * Copyright 2018 NXP */ -#include <common.h> #include <log.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index 0ce3036818b..c77104d0338 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -#include <common.h> #include <log.h> #include <firmware/imx/sci/sci.h> #include <asm/mach-imx/sys_proto.h> diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index 1eaa68f8d5f..df8c22b5706 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -14,7 +14,6 @@ #include <command.h> #include <log.h> #include <stddef.h> -#include <common.h> #include <firmware/imx/sci/sci.h> #include <asm/arch-imx8/imx8-pins.h> #include <asm/arch-imx8/snvs_security_sc.h> @@ -598,7 +597,7 @@ exit: } #endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */ -static char snvs_cfg_help_text[] = +U_BOOT_LONGHELP(snvs_cfg, "snvs_cfg\n" "\thp.lock\n" "\thp.secvio_ctl\n" @@ -619,7 +618,7 @@ static char snvs_cfg_help_text[] = "\tlp.act_tamper_routing_ctl1\n" "\tlp.act_tamper_routing_ctl2\n" "\n" - "ALL values should be in hexadecimal format"; + "ALL values should be in hexadecimal format\n"); #define NB_REGISTERS 18 static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc, @@ -663,7 +662,7 @@ U_BOOT_CMD(snvs_cfg, snvs_cfg_help_text ); -static char snvs_dgo_cfg_help_text[] = +U_BOOT_LONGHELP(snvs_dgo_cfg, "snvs_dgo_cfg\n" "\ttamper_offset_ctl\n" "\ttamper_pull_ctl\n" @@ -672,7 +671,7 @@ static char snvs_dgo_cfg_help_text[] = "\ttamper_misc_ctl\n" "\ttamper_core_volt_mon_ctl\n" "\n" - "ALL values should be in hexadecimal format"; + "ALL values should be in hexadecimal format\n"); static int do_snvs_dgo_cfg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -703,12 +702,12 @@ U_BOOT_CMD(snvs_dgo_cfg, snvs_dgo_cfg_help_text ); -static char tamper_pin_cfg_help_text[] = +U_BOOT_LONGHELP(tamper_pin_cfg, "snvs_dgo_cfg\n" "\tpad\n" "\tvalue\n" "\n" - "ALL values should be in hexadecimal format"; + "ALL values should be in hexadecimal format\n"); static int do_tamper_pin_cfg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -735,7 +734,7 @@ U_BOOT_CMD(tamper_pin_cfg, tamper_pin_cfg_help_text ); -static char snvs_clear_status_help_text[] = +U_BOOT_LONGHELP(snvs_clear_status, "snvs_clear_status\n" "\tHPSR\n" "\tHPSVSR\n" @@ -743,7 +742,7 @@ static char snvs_clear_status_help_text[] = "\tLPTDSR\n" "\n" "Write the status registers with the value provided," - " clearing the status"; + " clearing the status\n"); static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -779,9 +778,9 @@ U_BOOT_CMD(snvs_clear_status, snvs_clear_status_help_text ); -static char snvs_sec_status_help_text[] = +U_BOOT_LONGHELP(snvs_sec_status, "snvs_sec_status\n" - "Display information about the security related to tamper and secvio"; + "Display information about the security related to tamper and secvio\n"); static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 23d9217fcc2..d1fdaec7043 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -137,12 +137,14 @@ config TARGET_IMX8MN_BSH_SMM_S2 select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L + imply OF_UPSTREAM config TARGET_IMX8MN_BSH_SMM_S2PRO bool "imx8mn-bsh-smm-s2pro" select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L + imply OF_UPSTREAM config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" @@ -296,12 +298,14 @@ config TARGET_PHYCORE_IMX8MM select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_PHYCORE_IMX8MP bool "PHYTEC PHYCORE i.MX8MP" select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 47219957b58..de630e940c9 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -5,7 +5,6 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 9db62b944e4..7e6c3748716 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -5,7 +5,6 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> #include <command.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index b5ed27a923e..7cfdc46d349 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -5,7 +5,6 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c index 62f0b768cfa..f5644c642bd 100644 --- a/arch/arm/mach-imx/imx8m/psci.c +++ b/arch/arm/mach-imx/imx8m/psci.c @@ -10,7 +10,6 @@ #include <asm/io.h> #include <asm/psci.h> #include <asm/secure.h> -#include <common.h> #include <cpu_func.h> #include <debug_uart.h> #include <fsl_wdog.h> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 0c49fb9cd48..be38ca52885 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -5,7 +5,7 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <event.h> #include <init.h> diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d2fadb4877c..f9d8ed5b048 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP */ -#include <common.h> #include <div64.h> #include <asm/io.h> #include <errno.h> diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 36d12943a05..fadf165ece2 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include <common.h> #include <command.h> #include <div64.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c b/arch/arm/mach-imx/imx8ulp/iomux.c index c6d20f54680..43f856bf732 100644 --- a/arch/arm/mach-imx/imx8ulp/iomux.c +++ b/arch/arm/mach-imx/imx8ulp/iomux.c @@ -3,7 +3,6 @@ * Copyright 2020-2021 NXP */ -#include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c index e3c6d6760be..449e496521f 100644 --- a/arch/arm/mach-imx/imx8ulp/pcc.c +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -3,7 +3,6 @@ * Copyright 2021 NXP */ -#include <common.h> #include <div64.h> #include <asm/io.h> #include <errno.h> diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index cfc09e79cbd..ca657748ed9 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -3,7 +3,8 @@ * Copyright 2021 NXP */ -#include <common.h> +#include <config.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/types.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 75d92af036a..0abf4579a1e 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -5,7 +5,6 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> #include <command.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 7d7ae865946..47106fffefb 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -5,7 +5,7 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> +#include <config.h> #include <command.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 6afb59e0515..73f2e72263d 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -3,11 +3,12 @@ * Copyright 2022 NXP */ -#include <common.h> #include <command.h> #include <log.h> #include <imx_sip.h> +#include <vsprintf.h> #include <linux/arm-smccc.h> +#include <linux/errno.h> int arch_auxiliary_core_check_up(u32 core_id) { diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 2117489f232..32208220b20 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -5,7 +5,7 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c index d0f855bb1bc..8cdb28459a3 100644 --- a/arch/arm/mach-imx/imx9/trdc.c +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -3,8 +3,8 @@ * Copyright 2022 NXP */ -#include <common.h> #include <log.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/types.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index f7b14ca38d9..26374fdc33e 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -3,15 +3,18 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> +#include <asm/arch/imx-regs.h> #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> #include <command.h> #include <elf.h> #include <imx_sip.h> +#include <vsprintf.h> #include <linux/arm-smccc.h> #include <linux/compiler.h> +#include <linux/errno.h> +#include <linux/string.h> #include <cpu_func.h> #ifndef CONFIG_IMX8 diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index 34162a3976f..3028957953b 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/armv7_mpu.h> diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c index 18131a20f43..c134e95ed78 100644 --- a/arch/arm/mach-imx/iomux-v3.c +++ b/arch/arm/mach-imx/iomux-v3.c @@ -7,7 +7,6 @@ * * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/mach-imx/iomux-v3.h> diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c index 9bb63d25b48..e739fd14c89 100644 --- a/arch/arm/mach-imx/mac.c +++ b/arch/arm/mach-imx/mac.c @@ -5,7 +5,6 @@ * Peng Fan <peng.fan@nxp.com> */ -#include <common.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 09a758ff6e8..7452b82f110 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -3,7 +3,6 @@ * Copyright 2013 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <lmb.h> #include <log.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 9c822f721c6..34a7d1706f3 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 NXP */ -#include <common.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c index 41a5af6bd30..2b1d203f863 100644 --- a/arch/arm/mach-imx/mmdc_size.c +++ b/arch/arm/mach-imx/mmdc_size.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include <common.h> +#include <config.h> #include <asm/io.h> #if defined(CONFIG_MX53) diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index bbaddd5a33f..0b8a10fd729 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index f7441441947..180a745d435 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -4,7 +4,6 @@ * Patrick Bruenn <p.bruenn@beckhoff.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c index 47f531dc856..4df5f9c1641 100644 --- a/arch/arm/mach-imx/mx5/soc.c +++ b/arch/arm/mach-imx/mx5/soc.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <cpu_func.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 15ee2b933f6..7800553ae8d 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -481,6 +481,7 @@ config TARGET_MX6ULZ_SMM_M2 select DM_MTD select DM_THERMAL select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_MYS_6ULX bool "MYiR MYS-6ULX" diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index e0da9c23958..fb9f56d2e63 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -3,10 +3,10 @@ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <div64.h> #include <log.h> +#include <time.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 3c87c577737..5a1258e002d 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -4,7 +4,6 @@ * Author: Tim Harvey <tharvey@gateworks.com> */ -#include <common.h> #include <hang.h> #include <log.h> #include <linux/delay.h> diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 2ba3245e226..ab5de266577 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -17,7 +17,7 @@ #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> #include <asm/io.h> -#include <common.h> +#include <config.h> #include <fsl_esdhc_imx.h> #include <linux/delay.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index b58f11c1e56..8b23d48a854 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include <common.h> #include <fdt_support.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c index de9ace083ce..091a3723831 100644 --- a/arch/arm/mach-imx/mx6/mp.c +++ b/arch/arm/mach-imx/mx6/mp.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> #include <linux/errno.h> diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 38ead8ace20..340e6147b63 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -10,7 +10,7 @@ #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> -#include <common.h> +#include <config.h> #include <env.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index c2875e727c9..3a3e01f3d0a 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -7,7 +7,6 @@ * Copyright 2021 NXP */ -#include <common.h> #include <env.h> #include <init.h> #include <linux/delay.h> diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 4e232385afc..a8606fa9b24 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -6,11 +6,12 @@ * Peng Fan <Peng.Fan@freescale.com> */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <command.h> #include <div64.h> #include <log.h> +#include <time.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/errno.h> diff --git a/arch/arm/mach-imx/mx7/clock_slice.c b/arch/arm/mach-imx/mx7/clock_slice.c index dd731d94962..2a1304fc112 100644 --- a/arch/arm/mach-imx/mx7/clock_slice.c +++ b/arch/arm/mach-imx/mx7/clock_slice.c @@ -6,7 +6,6 @@ * Peng Fan <Peng.Fan@freescale.com> */ -#include <common.h> #include <div64.h> #include <asm/io.h> #include <linux/errno.h> diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index cf25569765e..c4a90be3945 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -12,7 +12,6 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/mx7-ddr.h> -#include <common.h> #include <linux/delay.h> /* diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 0b71fa40344..12d6a63b925 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -13,7 +13,6 @@ #include <asm/armv7.h> #include <asm/gic.h> #include <linux/bitops.h> -#include <common.h> #include <fsl_wdog.h> #define GPC_LPCR_A7_BSC 0x0 diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 689dbefe8ee..16c77cbf7be 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -4,7 +4,6 @@ * Copyright 2021 NXP */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 37d8565c20f..fb19c62a520 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <command.h> #include <div64.h> diff --git a/arch/arm/mach-imx/mx7ulp/iomux.c b/arch/arm/mach-imx/mx7ulp/iomux.c index 05ddeed2a64..2c87a8c18b9 100644 --- a/arch/arm/mach-imx/mx7ulp/iomux.c +++ b/arch/arm/mach-imx/mx7ulp/iomux.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/mach-imx/mx7ulp/pcc.c b/arch/arm/mach-imx/mx7ulp/pcc.c index aa7ea86a443..0bfd8f71815 100644 --- a/arch/arm/mach-imx/mx7ulp/pcc.c +++ b/arch/arm/mach-imx/mx7ulp/pcc.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include <common.h> #include <div64.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 4c066557c1c..d4fb5389cac 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <div64.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 217b7c45867..198ae2d919c 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index 5b022d5c820..65924483bc8 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -11,7 +11,6 @@ */ #include <asm/io.h> -#include <common.h> #include <command.h> #include <fsl_sec.h> diff --git a/arch/arm/mach-imx/rdc-sema.c b/arch/arm/mach-imx/rdc-sema.c index e683673753e..56725cc109f 100644 --- a/arch/arm/mach-imx/rdc-sema.c +++ b/arch/arm/mach-imx/rdc-sema.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/mach-imx/rdc-sema.h> diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c index 0e81cc880a1..98a42b22f9c 100644 --- a/arch/arm/mach-imx/speed.c +++ b/arch/arm/mach-imx/speed.c @@ -7,7 +7,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index b30cd962553..bc291dcd129 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -6,7 +6,7 @@ * Author: Tim Harvey <tharvey@gateworks.com> */ -#include <common.h> +#include <config.h> #include <hang.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index b9ff9bb83b3..9a86f5c133f 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -3,7 +3,6 @@ * Copyright 2019 NXP */ -#include <common.h> #include <errno.h> #include <image.h> #include <imx_container.h> diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 16df1186759..922f851c56b 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -5,7 +5,7 @@ * The file use ls102xa/timer.c as a reference. */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index fcd45f09f18..5ac8f28e670 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -6,7 +6,6 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 1bc9b7cc7e1..6cbb49da53c 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -#include <common.h> +#include <stdio.h> #include <env.h> #include <linux/errno.h> +#include <asm/arch/imx-regs.h> #include <asm/mach-imx/video.h> #ifdef CONFIG_IMX_HDMI diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 2bb970c2d4c..f3f42b39213 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -25,6 +25,9 @@ config SOC_K3_J721E config SOC_K3_J721S2 bool "TI's K3 based J721S2 SoC Family Support" +config SOC_K3_J722S + bool "TI's K3 based J722S SoC Family Support" + config SOC_K3_J784S4 bool "TI's K3 based J784S4 SoC Family Support" @@ -84,6 +87,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R default 0x7000f290 if SOC_K3_AM62A7 && ARM64 default 0x43c4f290 if SOC_K3_AM62P5 + default 0x43c7f290 if SOC_K3_J722S help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -122,7 +126,7 @@ config K3_EARLY_CONS_IDX config K3_ATF_LOAD_ADDR hex "Load address of ATF image" - default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5) + default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S) default 0x70000000 help The load address for the ATF image. This value is used to build the @@ -163,6 +167,7 @@ source "arch/arm/mach-k3/am62ax/Kconfig" source "arch/arm/mach-k3/am62px/Kconfig" source "arch/arm/mach-k3/j721e/Kconfig" source "arch/arm/mach-k3/j721s2/Kconfig" +source "arch/arm/mach-k3/j722s/Kconfig" source "arch/arm/mach-k3/j784s4/Kconfig" endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 4e9d0925f13..8c4f6786a5b 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -6,24 +6,13 @@ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_CPU_V7R) += r5/ obj-$(CONFIG_OF_LIBFDT) += common_fdt.o -ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy) -obj-$(CONFIG_SOC_K3_AM654) += am654_fdt.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_fdt.o -obj-$(CONFIG_SOC_K3_J721S2) += j721s2_fdt.o -obj-$(CONFIG_SOC_K3_AM625) += am625_fdt.o -obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_fdt.o -obj-$(CONFIG_SOC_K3_J784S4) += j784s4_fdt.o -obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_fdt.o -endif -ifeq ($(CONFIG_SPL_BUILD),y) -obj-$(CONFIG_SOC_K3_AM654) += am654_init.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o -obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o -obj-$(CONFIG_SOC_K3_AM642) += am642_init.o -obj-$(CONFIG_SOC_K3_AM625) += am625_init.o -obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o -obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o -obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o -endif obj-y += common.o security.o +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ +obj-$(CONFIG_SOC_K3_AM642) += am64x/ +obj-$(CONFIG_SOC_K3_AM654) += am65x/ +obj-$(CONFIG_SOC_K3_J721E) += j721e/ +obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ +obj-$(CONFIG_SOC_K3_J722S) += j722s/ +obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile new file mode 100644 index 00000000000..1717ca343d6 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o +obj-$(CONFIG_SPL_BUILD) += am62a7_init.o diff --git a/arch/arm/mach-k3/am62ax/am62a7_fdt.c b/arch/arm/mach-k3/am62ax/am62a7_fdt.c new file mode 100644 index 00000000000..7f764ab36b5 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/am62a7_fdt.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/hardware.h> +#include <fdt_support.h> + +#include "../common_fdt.h" + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); + fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); + + return 0; +} diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 658828cf75f..0f62f39075b 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -8,12 +8,13 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile new file mode 100644 index 00000000000..eed91a033eb --- /dev/null +++ b/arch/arm/mach-k3/am62px/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o +obj-$(CONFIG_SPL_BUILD) += am62p5_init.o diff --git a/arch/arm/mach-k3/am62p5_fdt.c b/arch/arm/mach-k3/am62px/am62p5_fdt.c index d67f012a5dc..29c832d28ac 100644 --- a/arch/arm/mach-k3/am62p5_fdt.c +++ b/arch/arm/mach-k3/am62px/am62p5_fdt.c @@ -4,7 +4,7 @@ */ #include <asm/hardware.h> -#include "common_fdt.h" +#include "../common_fdt.h" #include <fdt_support.h> int ft_system_setup(void *blob, struct bd_info *bd) diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index aab99aa0c95..34ed01cd78c 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -8,12 +8,13 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include "../sysfw-loader.h" +#include "../common.h" + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile index acf09c3426c..8494cdda482 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/am62x/Makefile @@ -1,2 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o +obj-$(CONFIG_SPL_BUILD) += am625_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c index c56adef13bd..8fe200a4231 100644 --- a/arch/arm/mach-k3/am625_fdt.c +++ b/arch/arm/mach-k3/am62x/am625_fdt.c @@ -4,9 +4,10 @@ */ #include <asm/hardware.h> -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + static void fdt_fixup_cores_nodes_am625(void *blob, int core_nr) { char node_path[32]; diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index 668f9a51ef4..72a752d38e8 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -9,13 +9,14 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> #include <dm/ofnode.h> +#include "../sysfw-loader.h" +#include "../common.h" + #define RTC_BASE_ADDRESS 0x2b1f0000 #define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) #define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70) @@ -212,6 +213,8 @@ void board_init_f(ulong dummy) preloader_console_init(); + do_board_detect(); + /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive" diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile new file mode 100644 index 00000000000..d0b286276c8 --- /dev/null +++ b/arch/arm/mach-k3/am64x/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_SPL_BUILD) += am642_init.o +obj-y += boot.o diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index 80c3cb3479f..41812b7dbf7 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -11,8 +11,6 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -21,6 +19,9 @@ #include <dm/root.h> #include <command.h> +#include "../sysfw-loader.h" +#include "../common.h" + #define CTRLMMR_MCU_RST_CTRL 0x04518170 #define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) @@ -285,97 +286,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) } } -static u32 __get_backup_bootmedia(u32 main_devstat) -{ - u32 bkup_bootmode = - (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; - u32 bkup_bootmode_cfg = - (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; - - switch (bkup_bootmode) { - case BACKUP_BOOT_DEVICE_UART: - return BOOT_DEVICE_UART; - - case BACKUP_BOOT_DEVICE_DFU: - if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - - case BACKUP_BOOT_DEVICE_ETHERNET: - return BOOT_DEVICE_ETHERNET; - - case BACKUP_BOOT_DEVICE_MMC: - if (bkup_bootmode_cfg) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BACKUP_BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BACKUP_BOOT_DEVICE_I2C: - return BOOT_DEVICE_I2C; - }; - - return BOOT_DEVICE_RAM; -} - -static u32 __get_primary_bootmedia(u32 main_devstat) -{ - u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; - u32 bootmode_cfg = - (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; - - switch (bootmode) { - case BOOT_DEVICE_OSPI: - fallthrough; - case BOOT_DEVICE_QSPI: - fallthrough; - case BOOT_DEVICE_XSPI: - fallthrough; - case BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BOOT_DEVICE_ETHERNET_RGMII: - fallthrough; - case BOOT_DEVICE_ETHERNET_RMII: - return BOOT_DEVICE_ETHERNET; - - case BOOT_DEVICE_EMMC: - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_NAND: - return BOOT_DEVICE_NAND; - - case BOOT_DEVICE_MMC: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> - MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_DFU: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - case BOOT_DEVICE_NOBOOT: - return BOOT_DEVICE_RAM; - } - - return bootmode; -} - u32 spl_boot_device(void) { - u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - - if (bootindex == K3_PRIMARY_BOOTMODE) - return __get_primary_bootmedia(devstat); - else - return __get_backup_bootmedia(devstat); + return get_boot_device(); } diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c new file mode 100644 index 00000000000..ce8ae941be6 --- /dev/null +++ b/arch/arm/mach-k3/am64x/boot.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spl.h> + +static u32 __get_backup_bootmedia(u32 main_devstat) +{ + u32 bkup_bootmode = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 main_devstat) +{ + u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_NAND: + return BOOT_DEVICE_NAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 get_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + u32 bootmedia; + + if (bootmode == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n", + __func__, devstat, bootmedia, bootmode); + + return bootmedia; +} diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile new file mode 100644 index 00000000000..20d5f1d3bf1 --- /dev/null +++ b/arch/arm/mach-k3/am65x/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o +obj-$(CONFIG_SPL_BUILD) += am654_init.o diff --git a/arch/arm/mach-k3/am654_fdt.c b/arch/arm/mach-k3/am65x/am654_fdt.c index 652fe8d32bb..bcb15208be9 100644 --- a/arch/arm/mach-k3/am654_fdt.c +++ b/arch/arm/mach-k3/am65x/am654_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am65x/am654_init.c index 7c2a143ed1b..a4f038029d7 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am65x/am654_init.c @@ -12,8 +12,6 @@ #include <asm/io.h> #include <spl.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> @@ -22,6 +20,9 @@ #include <mmc.h> #include <stdlib.h> +#include "../sysfw-loader.h" +#include "../common.h" + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_K3_LOAD_SYSFW diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 1a269d6934a..eaa7d361767 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -283,8 +283,10 @@ int misc_init_r(void) } /* Default FIT boot on HS-SE devices */ - if (get_device_type() == K3_DEVICE_TYPE_HS_SE) + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) { env_set("boot_fit", "1"); + env_set("secure_rprocs", "1"); + } return 0; } diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 53aa186b31a..7bd72da1de8 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -2,12 +2,13 @@ /* * K3: Architecture common definitions * - * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ #include <asm/armv7_mpu.h> #include <asm/hardware.h> +#include <mach/security.h> #define K3_FIREWALL_BACKGROUND_BIT (8) @@ -41,7 +42,6 @@ void spl_enable_cache(void); void mmr_unlock(uintptr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); enum k3_device_type get_device_type(void); -void ti_secure_image_post_process(void **p_image, size_t *p_size); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index c724450638c..b191d53a0f5 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -8,37 +8,42 @@ #include <asm/io.h> -#ifdef CONFIG_SOC_K3_AM654 -#include "am6_hardware.h" +#ifdef CONFIG_SOC_K3_AM625 +#include "am62_hardware.h" #endif -#ifdef CONFIG_SOC_K3_J721E -#include "j721e_hardware.h" +#ifdef CONFIG_SOC_K3_AM62A7 +#include "am62a_hardware.h" #endif -#ifdef CONFIG_SOC_K3_J721S2 -#include "j721s2_hardware.h" +#ifdef CONFIG_SOC_K3_AM62P5 +#include "am62p_hardware.h" #endif #ifdef CONFIG_SOC_K3_AM642 #include "am64_hardware.h" #endif -#ifdef CONFIG_SOC_K3_AM625 -#include "am62_hardware.h" +#ifdef CONFIG_SOC_K3_AM654 +#include "am6_hardware.h" #endif -#ifdef CONFIG_SOC_K3_AM62A7 -#include "am62a_hardware.h" +#ifdef CONFIG_SOC_K3_J721E +#include "j721e_hardware.h" +#endif + +#ifdef CONFIG_SOC_K3_J721S2 +#include "j721s2_hardware.h" +#endif + +#ifdef CONFIG_SOC_K3_J722S +#include "j722s_hardware.h" #endif #ifdef CONFIG_SOC_K3_J784S4 #include "j784s4_hardware.h" #endif -#ifdef CONFIG_SOC_K3_AM62P5 -#include "am62p_hardware.h" -#endif /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) @@ -54,6 +59,7 @@ #define JTAG_ID_PARTNO_J7200 0xbb6d #define JTAG_ID_PARTNO_J721E 0xbb64 #define JTAG_ID_PARTNO_J721S2 0xbb75 +#define JTAG_ID_PARTNO_J722S 0xbba0 #define JTAG_ID_PARTNO_J784S4 0xbb80 #define K3_SOC_ID(id, ID) \ @@ -63,14 +69,15 @@ static inline bool soc_is_##id(void) \ JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \ return soc == JTAG_ID_PARTNO_##ID; \ } -K3_SOC_ID(am65x, AM65X) -K3_SOC_ID(j721e, J721E) -K3_SOC_ID(j7200, J7200) -K3_SOC_ID(am64x, AM64X) -K3_SOC_ID(j721s2, J721S2) K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) K3_SOC_ID(am62px, AM62PX) +K3_SOC_ID(am64x, AM64X) +K3_SOC_ID(am65x, AM65X) +K3_SOC_ID(j7200, J7200) +K3_SOC_ID(j721e, J721E) +K3_SOC_ID(j721s2, J721S2) +K3_SOC_ID(j722s, J722S) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h b/arch/arm/mach-k3/include/mach/j722s_hardware.h new file mode 100644 index 00000000000..8d0bec22068 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: J722S SoC definitions, structures etc. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __ASM_ARCH_J722S_HARDWARE_H +#define __ASM_ARCH_J722S_HARDWARE_H + +#include <config.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c7f1e0 + +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 + +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +static const u32 put_device_ids[] = {}; + +static const u32 put_core_ids[] = {}; + +#endif + +#endif /* __ASM_ARCH_J722S_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j722s_spl.h b/arch/arm/mach-k3/include/mach/j722s_spl.h new file mode 100644 index 00000000000..eab8c511b7c --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j722s_spl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_J722S_SPL_H_ +#define _ASM_ARCH_J722S_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_SPI_NAND 0x00 +#define BOOT_DEVICE_RAM 0xFF +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x10 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_J722S_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h index e00e1de5b9c..eb0f2a0448a 100644 --- a/arch/arm/mach-k3/include/mach/k3-qos.h +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -9,6 +9,26 @@ #include <linux/kernel.h> +/* K3_QOS_REG: Registers to configure the channel for a given endpoint */ + +#define K3_QOS_REG(base_reg, i) (base_reg + 0x100 + (i) * 4) + +#define K3_QOS_VAL(qos, orderid, asel, epriority, virtid, atype) \ + (qos << 0 | \ + orderid << 4 | \ + asel << 8 | \ + epriority << 12 | \ + virtid << 16 | \ + atype << 28) + +/* + * K3_QOS_GROUP_REG: Registers to set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. + */ +#define K3_QOS_GROUP_REG(base_reg, i) (base_reg + (i) * 4) + +#define K3_QOS_GROUP_DEFAULT_VAL_LOW 0x76543210 +#define K3_QOS_GROUP_DEFAULT_VAL_HIGH 0xfedcba98 struct k3_qos_data { u32 reg; u32 val; diff --git a/arch/arm/mach-k3/include/mach/security.h b/arch/arm/mach-k3/include/mach/security.h new file mode 100644 index 00000000000..8502b57bd80 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/security.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: Security related definitions + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Manorit Chawdhry <m-chawdhry@ti.com> + */ + +#include <linux/types.h> + +void ti_secure_image_post_process(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 83942779225..ac1a34502ed 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -38,4 +38,8 @@ #include "am62p_spl.h" #endif +#ifdef CONFIG_SOC_K3_J722S +#include "j722s_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile new file mode 100644 index 00000000000..982b88db57d --- /dev/null +++ b/arch/arm/mach-k3/j721e/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o +obj-$(CONFIG_SPL_BUILD) += j721e_init.o diff --git a/arch/arm/mach-k3/j721e_fdt.c b/arch/arm/mach-k3/j721e/j721e_fdt.c index 652fe8d32bb..bcb15208be9 100644 --- a/arch/arm/mach-k3/j721e_fdt.c +++ b/arch/arm/mach-k3/j721e/j721e_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index 7ee9b75de4d..e9ed8cb267c 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -11,8 +11,6 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -22,6 +20,25 @@ #include <mmc.h> #include <remoteproc.h> +#include "../sysfw-loader.h" +#include "../common.h" + +/* NAVSS North Bridge (NB) registers */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03803000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-7 to VBUSM.C thread number + * Bit[1] maps orderID 8-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM) @@ -123,6 +140,13 @@ void k3_mmc_restart_clock(void) } #endif +/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -287,6 +311,11 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif spl_enable_cache(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile new file mode 100644 index 00000000000..ceef68297c9 --- /dev/null +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o +obj-$(CONFIG_SPL_BUILD) += j721s2_init.o diff --git a/arch/arm/mach-k3/j721s2_fdt.c b/arch/arm/mach-k3/j721s2/j721s2_fdt.c index 652fe8d32bb..bcb15208be9 100644 --- a/arch/arm/mach-k3/j721s2_fdt.c +++ b/arch/arm/mach-k3/j721s2/j721s2_fdt.c @@ -3,9 +3,10 @@ * Copyright 2023 Toradex - https://www.toradex.com/ */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 3374889558a..05453fcad41 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -11,8 +11,6 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -21,6 +19,27 @@ #include <mmc.h> #include <remoteproc.h> +#include "../sysfw-loader.h" +#include "../common.h" + +/* NAVSS North Bridge (NB) */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-3 to VBUSM.C thread number + * Bit[1] maps orderID 4-9 to VBUSM.C thread number + * Bit[2] maps orderID 10-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) +#define NB_THREADMAP_BIT2 BIT(2) + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, @@ -122,6 +141,13 @@ void k3_mmc_restart_clock(void) } } +/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -294,6 +320,11 @@ void board_init_f(ulong dummy) do_dt_magic(); #endif k3_mem_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } #endif diff --git a/arch/arm/mach-k3/j722s/Kconfig b/arch/arm/mach-k3/j722s/Kconfig new file mode 100644 index 00000000000..39d38ea5cf5 --- /dev/null +++ b/arch/arm/mach-k3/j722s/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# + +if SOC_K3_J722S + +choice + prompt "TI K3 J722S based boards" + optional + +config TARGET_J722S_A53_EVM + bool "TI K3 based J722S EVM running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + +config TARGET_J722S_R5_EVM + bool "TI K3 based J722S EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +source "board/ti/j722s/Kconfig" + +endif diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile new file mode 100644 index 00000000000..2b1fec131ed --- /dev/null +++ b/arch/arm/mach-k3/j722s/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Jayesh Choudhary <j-choudhary@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o +obj-$(CONFIG_SPL_BUILD) += j722s_init.o diff --git a/arch/arm/mach-k3/am62a7_fdt.c b/arch/arm/mach-k3/j722s/j722s_fdt.c index d67f012a5dc..29c832d28ac 100644 --- a/arch/arm/mach-k3/am62a7_fdt.c +++ b/arch/arm/mach-k3/j722s/j722s_fdt.c @@ -4,7 +4,7 @@ */ #include <asm/hardware.h> -#include "common_fdt.h" +#include "../common_fdt.h" #include <fdt_support.h> int ft_system_setup(void *blob, struct bd_info *bd) diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c new file mode 100644 index 00000000000..01b00681f68 --- /dev/null +++ b/arch/arm/mach-k3/j722s/j722s_init.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * J722S: SoC specific initialization + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/pinctrl.h> + +#include "../sysfw-loader.h" +#include "../common.h" + +struct fwl_data cbass_main_fwls[] = { + { "FSS_DAT_REG3", 7, 8 }, +}; + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +static void k3_spl_init(void) +{ + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_k3_mpu_regions(); + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed: %d\n", ret); + + /* + * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue + * regardless of the result of pinctrl. Do this without probing the + * device, but instead by searching the device that would request the + * given sequence number if probed. The UART will be used by the DM + * firmware image for various purposes and TIFS depends on us to + * initialize its pin settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) { + /* + * Allow establishing an early console as required for example + * when doing a UART-based boot. Note that this console may not + * "survive" through a SYSFW PM-init step and will need a re-init + * in some way due to changing module clock frequencies. + */ + ret = early_console_init(); + if (ret) + panic("early_console_init() failed: %d\n", ret); + } + + if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) { + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM + * configuration callback hook, effectively switching on (or + * over) the console output. + */ + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); + } + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + preloader_console_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* Disable ROM configured firewalls right after loading sysfw */ + remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls)); + } + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); +} + +static void k3_mem_init(void) +{ + struct udevice *dev; + int ret; + + if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); + } +} + +void board_init_f(ulong dummy) +{ + k3_spl_init(); + k3_mem_init(); +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_SPI_NAND: + return BOOT_DEVICE_SPINAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("j722s_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + return bootmedia; +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_EMMC: + return MMCSD_MODE_EMMCBOOT; + case BOOT_DEVICE_MMC: + if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) + return MMCSD_MODE_RAW; + default: + return MMCSD_MODE_FS; + } +} diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile new file mode 100644 index 00000000000..6d1841e3f9e --- /dev/null +++ b/arch/arm/mach-k3/j784s4/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o +obj-$(CONFIG_SPL_BUILD) += j784s4_init.o diff --git a/arch/arm/mach-k3/j784s4_fdt.c b/arch/arm/mach-k3/j784s4/j784s4_fdt.c index d05ed8b9911..e1275097051 100644 --- a/arch/arm/mach-k3/j784s4_fdt.c +++ b/arch/arm/mach-k3/j784s4/j784s4_fdt.c @@ -6,9 +6,10 @@ * Apurva Nandan <a-nandan@ti.com> */ -#include "common_fdt.h" #include <fdt_support.h> +#include "../common_fdt.h" + int ft_system_setup(void *blob, struct bd_info *bd) { return fdt_fixup_msmc_ram_k3(blob); diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index ae4420362d0..07b5d7d7504 100644 --- a/arch/arm/mach-k3/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -11,8 +11,6 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include "sysfw-loader.h" -#include "common.h" #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -20,8 +18,29 @@ #include <mmc.h> #include <remoteproc.h> +#include "../sysfw-loader.h" +#include "../common.h" + #define J784S4_MAX_DDR_CONTROLLERS 4 +/* NAVSS North Bridge (NB) */ +#define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000 +#define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000 +#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10) +#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10) +/* + * Thread Map for North Bridge Configuration + * Each bit is for each VBUSM source. + * Bit[0] maps orderID 0-3 to VBUSM.C thread number + * Bit[1] maps orderID 4-9 to VBUSM.C thread number + * Bit[2] maps orderID 10-15 to VBUSM.C thread number + * When bit has value 0: VBUSM.C thread 0 (non-real time traffic) + * When bit has value 1: VBUSM.C thread 2 (real time traffic) + */ +#define NB_THREADMAP_BIT0 BIT(0) +#define NB_THREADMAP_BIT1 BIT(1) +#define NB_THREADMAP_BIT2 BIT(2) + struct fwl_data infra_cbass0_fwls[] = { { "PSC0", 5, 1 }, { "PLL_CTRL0", 6, 1 }, @@ -93,6 +112,13 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 7); } +/* Setup North Bridge registers to map ORDERID 10-15 to RT traffic */ +static void setup_navss_nb(void) +{ + writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP); + writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -209,6 +235,11 @@ void board_init_f(ulong dummy) { k3_spl_init(); k3_mem_init(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) + setup_navss_nb(); + + setup_qos(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile index 1cfc8e3ade9..d3886caa064 100644 --- a/arch/arm/mach-k3/r5/Makefile +++ b/arch/arm/mach-k3/r5/Makefile @@ -3,13 +3,14 @@ # Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ # Andrew Davis <afd@ti.com> +obj-$(CONFIG_SOC_K3_AM625) += am62x/ +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-$(CONFIG_SOC_K3_J721E) += j721e/ obj-$(CONFIG_SOC_K3_J721E) += j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ -obj-$(CONFIG_SOC_K3_AM625) += am62x/ -obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_SOC_K3_J722S) += j722s/ obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ -obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-y += common.o obj-y += lowlevel_init.o diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h index c74d69a28f8..84a6dc72406 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos.h +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h @@ -6,80 +6,6 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ -#define QOS_0 (0 << 0) -#define QOS_1 (1 << 0) -#define QOS_2 (2 << 0) -#define QOS_3 (3 << 0) -#define QOS_4 (4 << 0) -#define QOS_5 (5 << 0) -#define QOS_6 (6 << 0) -#define QOS_7 (7 << 0) - -#define ORDERID_0 (0 << 4) -#define ORDERID_1 (1 << 4) -#define ORDERID_2 (2 << 4) -#define ORDERID_3 (3 << 4) -#define ORDERID_4 (4 << 4) -#define ORDERID_5 (5 << 4) -#define ORDERID_6 (6 << 4) -#define ORDERID_7 (7 << 4) -#define ORDERID_8 (8 << 4) -#define ORDERID_9 (9 << 4) -#define ORDERID_10 (10 << 4) -#define ORDERID_11 (11 << 4) -#define ORDERID_12 (12 << 4) -#define ORDERID_13 (13 << 4) -#define ORDERID_14 (14 << 4) -#define ORDERID_15 (15 << 4) - -#define ASEL_0 (0 << 8) -#define ASEL_1 (1 << 8) -#define ASEL_2 (2 << 8) -#define ASEL_3 (3 << 8) -#define ASEL_4 (4 << 8) -#define ASEL_5 (5 << 8) -#define ASEL_6 (6 << 8) -#define ASEL_7 (7 << 8) -#define ASEL_8 (8 << 8) -#define ASEL_9 (9 << 8) -#define ASEL_10 (10 << 8) -#define ASEL_11 (11 << 8) -#define ASEL_12 (12 << 8) -#define ASEL_13 (13 << 8) -#define ASEL_14 (14 << 8) -#define ASEL_15 (15 << 8) - -#define EPRIORITY_0 (0 << 12) -#define EPRIORITY_1 (1 << 12) -#define EPRIORITY_2 (2 << 12) -#define EPRIORITY_3 (3 << 12) -#define EPRIORITY_4 (4 << 12) -#define EPRIORITY_5 (5 << 12) -#define EPRIORITY_6 (6 << 12) -#define EPRIORITY_7 (7 << 12) - -#define VIRTID_0 (0 << 16) -#define VIRTID_1 (1 << 16) -#define VIRTID_2 (2 << 16) -#define VIRTID_3 (3 << 16) -#define VIRTID_4 (4 << 16) -#define VIRTID_5 (5 << 16) -#define VIRTID_6 (6 << 16) -#define VIRTID_7 (7 << 16) -#define VIRTID_8 (8 << 16) -#define VIRTID_9 (9 << 16) -#define VIRTID_10 (10 << 16) -#define VIRTID_11 (11 << 16) -#define VIRTID_12 (12 << 16) -#define VIRTID_13 (13 << 16) -#define VIRTID_14 (14 << 16) -#define VIRTID_15 (15 << 16) - -#define ATYPE_0 (0 << 28) -#define ATYPE_1 (1 << 28) -#define ATYPE_2 (2 << 28) -#define ATYPE_3 (3 << 28) - #define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 #define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 #define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800 diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c index 9a82944d5fe..1d588acea4d 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c @@ -12,20 +12,20 @@ struct k3_qos_data qos_data[] = { /* modules_qosConfig0 - 1 endpoints, 4 channels */ { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, - .val = ORDERID_8, + .reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 8, 0, 0, 0, 0), }, /* Following registers set 1:1 mapping for orderID MAP1/MAP2 @@ -35,12 +35,12 @@ struct k3_qos_data qos_data[] = { /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, - .val = 0x76543210, + .reg = K3_QOS_GROUP_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, }, { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, - .val = 0xfedcba98, + .reg = K3_QOS_GROUP_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, }, }; diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile index 78325db402c..07bfb0dd935 100644 --- a/arch/arm/mach-k3/r5/j721e/Makefile +++ b/arch/arm/mach-k3/r5/j721e/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721e_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h b/arch/arm/mach-k3/r5/j721e/j721e_qos.h new file mode 100644 index 00000000000..9ec0b7c6301 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define PULSAR_SL_MCU_0_MEMBDG_RMST0 0x45D10000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST0 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_MEMBDG_RMST1 0x45D11000 +#define PULSAR_SL_MCU_0_MEMBDG_WMST1 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA2_UL_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define ICSS_G_MAIN_0_PR1_EXT_VBUSM 0x45D80000 +#define ICSS_G_MAIN_1_PR1_EXT_VBUSM 0x45D80400 +#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000 +#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D82C00 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST0 0x45D84000 +#define PULSAR_SL_MAIN_0_MEMBDG_RMST1 0x45D84400 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST0 0x45D84800 +#define PULSAR_SL_MAIN_0_MEMBDG_WMST1 0x45D84C00 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST0 0x45D85000 +#define PULSAR_SL_MAIN_1_MEMBDG_RMST1 0x45D85400 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST0 0x45D85800 +#define PULSAR_SL_MAIN_1_MEMBDG_WMST1 0x45D85C00 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define K3_C66_COREPAC_MAIN_0_C66_CFG 0x45D87000 +#define K3_C66_COREPAC_MAIN_1_C66_CFG 0x45D87400 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D88800 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D89800 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D89C00 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D8A000 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D8A400 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45D8A800 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45D8AC00 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45D8B000 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45D8B400 +#define VPFE_MAIN_0_VBUSM_DMA 0x45D8C000 +#define VPE_MAIN_0_VPDMA_MST0 0x45D8C400 +#define VPE_MAIN_0_VPDMA_MST1 0x45D8C800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_HP 0x45D90000 +#define PCIE_G4X2_MAIN_0_PCIE_MST_RD_LP 0x45D90400 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_HP 0x45D90800 +#define PCIE_G4X2_MAIN_0_PCIE_MST_WR_LP 0x45D90C00 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_HP 0x45D91000 +#define PCIE_G4X2_MAIN_1_PCIE_MST_RD_LP 0x45D91400 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_HP 0x45D91800 +#define PCIE_G4X2_MAIN_1_PCIE_MST_WR_LP 0x45D91C00 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_HP 0x45D92000 +#define PCIE_G4X2_MAIN_2_PCIE_MST_RD_LP 0x45D92400 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_HP 0x45D92800 +#define PCIE_G4X2_MAIN_2_PCIE_MST_WR_LP 0x45D92C00 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_HP 0x45D93000 +#define PCIE_G4X2_MAIN_3_PCIE_MST_RD_LP 0x45D93400 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_HP 0x45D93800 +#define PCIE_G4X2_MAIN_3_PCIE_MST_WR_LP 0x45D93C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D98000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D98400 +#define USB3P0SS_16FFC_MAIN_1_MSTR0 0x45D98800 +#define USB3P0SS_16FFC_MAIN_1_MSTW0 0x45D98C00 +#define USB3P0SS_16FFC_MAIN_2_MSTR0 0x45D99000 +#define USB3P0SS_16FFC_MAIN_2_MSTW0 0x45D99400 +#define MLBSS2P0_MAIN_0_MLBSS_DMA_VBUSP 0x45D99C00 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9A000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9B000 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B400 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_RD 0x45D9B800 +#define UFSHCI2P1SS_16FFC_MAIN_1_UFSHCI_VBM_MST_WR 0x45D9BC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_0_CPU0_PMST 0x45DA4000 +#define PULSAR_SL_MAIN_0_CPU1_PMST 0x45DA4400 +#define PULSAR_SL_MAIN_1_CPU0_PMST 0x45DA4800 +#define PULSAR_SL_MAIN_1_CPU1_PMST 0x45DA4C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_D5520MP2_MAIN_0_M_VBUSM_R 0x45DC0400 +#define K3_D5520MP2_MAIN_0_M_VBUSM_W 0x45DC0800 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_R 0x45DC0C00 +#define K3_VXE384MP2_MAIN_0_M_VBUSM_W 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_R_ASYNC 0x45DC5000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M0_VBUSM_W_ASYNC 0x45DC5800 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_R_ASYNC 0x45DC6000 +#define J7_LASCAR_GPU_WRAP_MAIN_0_M1_VBUSM_W_ASYNC 0x45DC6800 diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c new file mode 100644 index 00000000000..713849a41b3 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j721e Quality of Service (QoS) Configuration Data + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/arch/k3-qos.h> +#include "j721e_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 2 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data); diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile index 8588c5e4c39..89c0284b568 100644 --- a/arch/arm/mach-k3/r5/j721s2/Makefile +++ b/arch/arm/mach-k3/r5/j721s2/Makefile @@ -3,3 +3,4 @@ # Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j721s2_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h new file mode 100644 index 00000000000..ab3e4773a4f --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 +#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 +#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 +#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 +#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 +#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 +#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 +#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 +#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 +#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 +#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 +#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 +#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 +#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 +#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 +#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 +#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 +#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 +#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 +#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 +#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 +#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 +#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 +#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 diff --git a/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c new file mode 100644 index 00000000000..54d81d929a2 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/j721s2_qos_uboot.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j721s2 Quality of Service (QoS) Configuration Data + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/arch/k3-qos.h> +#include "j721s2_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data); diff --git a/arch/arm/mach-k3/r5/j722s/Makefile b/arch/arm/mach-k3/r5/j722s/Makefile new file mode 100644 index 00000000000..2a0dbf5f5a8 --- /dev/null +++ b/arch/arm/mach-k3/r5/j722s/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c new file mode 100644 index 00000000000..b4f27af333d --- /dev/null +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J722S specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/clk-provider.h> +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const main_timerclkn_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "clk_32k_rc_sel_out0", + "postdiv4_16ff_main_0_hsdivout7_clk", + "gluelogic_rcosc_clkout", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "board_0_cp_gemac_cpts0_rft_clk_out", + "hsdiv4_16fft_main_1_hsdivout3_clk", + "postdiv4_16ff_main_2_hsdivout6_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv3_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(36, 2, "main_timerclkn_sel_out0"), + DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"), + DEV_CLK(36, 4, "clk_32k_rc_sel_out0"), + DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"), + DEV_CLK(36, 6, "gluelogic_rcosc_clkout"), + DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(36, 8, "board_0_ext_refclk1_out"), + DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), + DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 54, "clkout0_ctrl_out0"), + DEV_CLK(157, 55, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 56, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 159, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 173, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 175, "wkup_clkout_sel_out0"), + DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 178, "dmtimer_dmc1ms_main_0_timer_pwm"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j722s_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = ARRAY_SIZE(clk_list), + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), +}; diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c new file mode 100644 index 00000000000..59176c98999 --- /dev/null +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J722S specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), + [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), + [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), + [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(75, &soc_lpsc_list[6]), + PSC_DEV(36, &soc_lpsc_list[7]), + PSC_DEV(102, &soc_lpsc_list[7]), + PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(166, &soc_lpsc_list[8]), + PSC_DEV(135, &soc_lpsc_list[9]), + PSC_DEV(170, &soc_lpsc_list[10]), + PSC_DEV(177, &soc_lpsc_list[11]), + PSC_DEV(55, &soc_lpsc_list[12]), +}; + +const struct ti_k3_pd_platdata j722s_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/j784s4/Makefile b/arch/arm/mach-k3/r5/j784s4/Makefile index 9ce88305f57..0fd6cabd3fa 100644 --- a/arch/arm/mach-k3/r5/j784s4/Makefile +++ b/arch/arm/mach-k3/r5/j784s4/Makefile @@ -5,3 +5,4 @@ obj-y += clk-data.o obj-y += dev-data.o +obj-y += j784s4_qos_uboot.o diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index feaa13ee266..793bcac9324 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -134,7 +134,7 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { static const char * const mcu_clkout_mux_out0_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", }; static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { @@ -338,7 +338,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 174, "mcu_clkout_mux_out0"), DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h new file mode 100644 index 00000000000..5851f889fe2 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000 +#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400 +#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000 +#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400 +#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800 +#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000 +#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400 +#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800 +#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000 +#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000 +#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400 +#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800 +#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000 +#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400 +#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400 +#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00 +#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000 +#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00 +#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400 +#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800 +#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00 +#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000 +#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400 +#define PCIE_G3X4_128_MAIN_2_PCIE_MST_RD 0x45D9CC00 +#define PCIE_G3X4_128_MAIN_3_PCIE_MST_WR 0x45D9D400 +#define PCIE_G3X4_128_MAIN_2_PCIE_MST_WR 0x45D9D800 +#define PCIE_G3X4_128_MAIN_3_PCIE_MST_RD 0x45D9DC00 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400 +#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000 +#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400 +#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800 +#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00 +#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000 +#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400 +#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800 +#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00 +#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000 +#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400 +#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800 +#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000 +#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400 +#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800 +#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00 +#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00 +#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400 +#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000 +#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800 +#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000 +#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400 +#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800 +#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00 +#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000 +#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400 +#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800 +#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00 +#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000 +#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400 +#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800 +#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00 diff --git a/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c new file mode 100644 index 00000000000..8c96da6ce56 --- /dev/null +++ b/arch/arm/mach-k3/r5/j784s4/j784s4_qos_uboot.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * j784s4 Quality of Service (QoS) Configuration Data + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <asm/arch/k3-qos.h> +#include "j784s4_qos.h" + +struct k3_qos_data qos_data[] = { + /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL1 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 2), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 3), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VID2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 4), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 5), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* DSS_PIPE_VIDL2 - 2 endpoints, 2 channels */ + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 6), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + { + .reg = K3_QOS_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 7), + .val = K3_QOS_VAL(0, 15, 0, 0, 0, 0), + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, + + /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC - 1 groups */ + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 0), + .val = K3_QOS_GROUP_DEFAULT_VAL_LOW, + }, + { + .reg = K3_QOS_GROUP_REG(K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC, 1), + .val = K3_QOS_GROUP_DEFAULT_VAL_HIGH, + }, +}; + +u32 qos_count = ARRAY_SIZE(qos_data); diff --git a/arch/arm/mach-kirkwood/cache.c b/arch/arm/mach-kirkwood/cache.c index 009b7deeca6..acd2e8b1145 100644 --- a/arch/arm/mach-kirkwood/cache.c +++ b/arch/arm/mach-kirkwood/cache.c @@ -3,7 +3,6 @@ * Copyright (c) 2012 Michael Walle * Michael Walle <michael@walle.cc> */ -#include <common.h> #include <asm/arch/cpu.h> #include <asm/cache.h> diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 2b493b36c20..a432abe615d 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -5,7 +5,6 @@ * Written-by: Prafulla Wadaskar <prafulla@marvell.com> */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <env.h> diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h index 4d1f58c0cbd..e2757942590 100644 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h @@ -8,6 +8,8 @@ #ifndef __KIRKWOOD_MPP_H #define __KIRKWOOD_MPP_H +#include <linux/types.h> + #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ /* MPP number */ ((_num) & 0xff) | \ /* MPP select value */ (((_sel) & 0xf) << 8) | \ diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 4fdad99cade..7938820e513 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -9,7 +9,6 @@ * warranty of any kind, whether express or implied. */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-lpc32xx/clk.c b/arch/arm/mach-lpc32xx/clk.c index cb2344d79fe..2e11903e7e0 100644 --- a/arch/arm/mach-lpc32xx/clk.c +++ b/arch/arm/mach-lpc32xx/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> */ -#include <common.h> #include <clock_legacy.h> #include <div64.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index a97f9a1958a..80f5e7c88eb 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com> */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <net.h> diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 6a67a3591aa..49308d6d4be 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -3,7 +3,7 @@ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> */ -#include <common.h> +#include <config.h> #include <dm.h> #include <ns16550.h> diff --git a/arch/arm/mach-lpc32xx/dram.c b/arch/arm/mach-lpc32xx/dram.c index 16022379235..ab7c13512a5 100644 --- a/arch/arm/mach-lpc32xx/dram.c +++ b/arch/arm/mach-lpc32xx/dram.c @@ -10,7 +10,6 @@ * This code runs from SRAM. */ -#include <common.h> #include <netdev.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 90183e3014e..523f9cfc8c4 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 82018bd9d3e..ff1fdee5c8d 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -23,6 +23,7 @@ config TARGET_MT7622 config TARGET_MT7623 bool "MediaTek MT7623 SoC" select CPU_V7A + select MMC_SUPPORTS_TUNING help The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-450 graphics, several DDR3 options, diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c index c329e7cc98a..8e8bc4f9cea 100644 --- a/arch/arm/mach-mediatek/cpu.c +++ b/arch/arm/mach-mediatek/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <init.h> diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 1f32ff947dc..368f2916224 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -9,7 +9,6 @@ #include <asm/armv8/mmu.h> #include <asm/system.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 988b057e598..3d6ba3f383c 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/global_data.h> #include <linux/io.h> diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index 0130554ff35..7cb8b72c364 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -5,7 +5,7 @@ */ #include <clk.h> -#include <common.h> +#include <config.h> #include <dm.h> #include <fdtdec.h> #include <init.h> diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index 862f0ca4793..07da5897190 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -9,7 +9,6 @@ #include <asm/armv8/mmu.h> #include <asm/system.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index 905a3ab4e27..a521c95bd9d 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -9,7 +9,6 @@ #include <asm/armv8/mmu.h> #include <asm/system.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 082f12bf65e..2efc8c6a88f 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -8,7 +8,6 @@ #include <init.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include <asm/system.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt8183/init.c b/arch/arm/mach-mediatek/mt8183/init.c index 7496029705f..37243547da8 100644 --- a/arch/arm/mach-mediatek/mt8183/init.c +++ b/arch/arm/mach-mediatek/mt8183/init.c @@ -6,7 +6,6 @@ */ #include <clk.h> -#include <common.h> #include <dm.h> #include <fdtdec.h> #include <ram.h> diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index 5a21e9a4485..3b48caf5196 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -7,7 +7,6 @@ */ #include <clk.h> -#include <common.h> #include <dm.h> #include <fdtdec.h> #include <init.h> diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 3460dcc2494..892bd441a33 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -6,7 +6,6 @@ */ #include <clk.h> -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index f7e03de3650..c04bcb63517 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -7,7 +7,6 @@ */ #include <clk.h> -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index d3cda94617e..247d7ee6f1d 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -5,7 +5,6 @@ */ #include <clk.h> -#include <common.h> #include <hang.h> #include <init.h> #include <spl.h> diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c index 967bb671822..f848c0f068e 100644 --- a/arch/arm/mach-meson/board-a1.c +++ b/arch/arm/mach-meson/board-a1.c @@ -3,12 +3,12 @@ * (C) Copyright 2023 SberDevices, Inc. */ -#include <common.h> #include <asm/arch/a1.h> #include <asm/arch/boot.h> #include <asm/armv8/mmu.h> #include <asm/io.h> #include <linux/compiler.h> +#include <linux/errno.h> #include <linux/sizes.h> phys_size_t get_effective_memsize(void) diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index fdf18752cdd..6535539184c 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> */ -#include <common.h> #include <init.h> #include <net.h> #include <asm/arch/boot.h> diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 7ceba7cede8..39774c43049 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> */ -#include <common.h> #include <cpu_func.h> #include <fastboot.h> #include <init.h> diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index d5a830fb1db..dc4abe1e107 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> */ -#include <common.h> #include <init.h> #include <log.h> #include <net.h> diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index c3fbdfffeae..0370ed57e20 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -4,7 +4,6 @@ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> */ -#include <common.h> #include <init.h> #include <net.h> #include <asm/arch/boot.h> diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index d51d9b8f064..b4058f59323 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -4,7 +4,6 @@ * (C) Copyright 2019 Neil Armstrong <narmstrong@baylibre.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 914fd11c989..4d9f83d3b38 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -5,7 +5,6 @@ * Secure monitor calls. */ -#include <common.h> #include <dm.h> #include <log.h> #include <regmap.h> diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index 0f72ae1709b..be2d9a25bf9 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marvell International Ltd. */ -#include <common.h> +#include <config.h> #include <dm.h> #include <fdtdec.h> #include <linux/libfdt.h> diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c index 734b0a87dd4..98e66735eb9 100644 --- a/arch/arm/mach-mvebu/alleycat5/soc.c +++ b/arch/arm/mach-mvebu/alleycat5/soc.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Marvell International Ltd. */ -#include <common.h> #include <asm/arch-armada8k/cache_llc.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 4c67f1aba4d..63a12f7d774 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese <sr@denx.de> */ -#include <common.h> +#include <config.h> #include <dm.h> #include <fdtdec.h> #include <init.h> diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index ab72b304e5d..17525691e68 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -4,7 +4,6 @@ * Copyright (C) 2020 Marek Behún <kabel@kernel.org> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 07d5f394354..84a1e388c11 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -5,9 +5,10 @@ */ #include <config.h> -#include <common.h> #include <asm/io.h> #include <linux/delay.h> +#include <linux/errno.h> +#include <linux/types.h> #include <mach/mbox.h> #include <mach/soc.h> diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c index 6555b8673ce..5ac543abce5 100644 --- a/arch/arm/mach-mvebu/armada3700/mbox.c +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -4,11 +4,11 @@ * Copyright (C) 2021 Pali Rohár <pali@kernel.org> */ -#include <common.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/errno.h> #include <mach/mbox.h> #define RWTM_BASE (MVEBU_REGISTER(0xb0000)) diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 939abce000f..7908f75809c 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index 6c801bfa1db..fd58551d0e3 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese <sr@denx.de> */ -#include <common.h> +#include <config.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 7c62a5dbb6a..e603ab9ffb7 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -3,7 +3,7 @@ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> */ -#include <common.h> +#include <config.h> #include <ahci.h> #include <cpu_func.h> #include <init.h> diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index d398d0f7676..c00c6b9b3fc 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -6,7 +6,6 @@ */ #include <config.h> -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c index be5dc0e07d9..475687955e0 100644 --- a/arch/arm/mach-mvebu/efuse.c +++ b/arch/arm/mach-mvebu/efuse.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/gpio.c b/arch/arm/mach-mvebu/gpio.c index 1d1e3df8ba9..587cbb00e7f 100644 --- a/arch/arm/mach-mvebu/gpio.c +++ b/arch/arm/mach-mvebu/gpio.c @@ -5,7 +5,6 @@ * Written-by: Prafulla Wadaskar <prafulla@marvell.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 959ca8e9260..9baeece3c85 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -46,7 +46,7 @@ * mvebu_mbus_del_window(). */ -#include <common.h> +#include <config.h> #include <malloc.h> #include <linux/bitops.h> #include <linux/errno.h> diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c index 12596ec2d8b..4582871556d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include <common.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 3349f4eb549..efc31d5218a 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -3,7 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include <common.h> +#include <config.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c b/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c index 2a51b7113ce..9a1bbba7f2f 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include <common.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index fb8ec11dfb9..8290b861c07 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include <common.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 68f8eade272..61b7f168697 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -3,7 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include <common.h> +#include <config.h> #include <i2c.h> #include <spl.h> #include <asm/io.h> diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c index 539d237623a..9b7bb2c3851 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c @@ -3,7 +3,6 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include <common.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 79f8877745b..4f4f7e00e3c 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 682431ee11d..d94bde0777c 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -4,7 +4,6 @@ * Copyright (C) 2024 Marek Behún <kabel@kernel.org> */ -#include <common.h> #include <dm.h> #include <dm/lists.h> #include <regmap.h> diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c index 59ffa26255f..3082f6077b7 100644 --- a/arch/arm/mach-nexell/clock.c +++ b/arch/arm/mach-nexell/clock.c @@ -4,8 +4,8 @@ * Hyunseok, Jung <hsjung@nexell.co.kr> */ -#include <common.h> #include <command.h> +#include <vsprintf.h> #include <linux/err.h> #include <asm/io.h> #include <asm/arch/nexell.h> diff --git a/arch/arm/mach-nexell/include/mach/mipi_display.h b/arch/arm/mach-nexell/include/mach/mipi_display.h index f3fdec64647..9183ffdd9c3 100644 --- a/arch/arm/mach-nexell/include/mach/mipi_display.h +++ b/arch/arm/mach-nexell/include/mach/mipi_display.h @@ -11,6 +11,8 @@ #ifndef MIPI_DISPLAY_H #define MIPI_DISPLAY_H +#include <linux/types.h> + /* MIPI DSI Processor-to-Peripheral transaction types */ enum { MIPI_DSI_V_SYNC_START = 0x01, diff --git a/arch/arm/mach-nexell/include/mach/reset.h b/arch/arm/mach-nexell/include/mach/reset.h index e1301d4e53d..0c6a13043f9 100644 --- a/arch/arm/mach-nexell/include/mach/reset.h +++ b/arch/arm/mach-nexell/include/mach/reset.h @@ -7,6 +7,8 @@ #ifndef __NEXELL_RESET__ #define __NEXELL_RESET__ +#include <linux/types.h> + #define NUMBER_OF_RESET_MODULE_PIN 69 enum rstcon { diff --git a/arch/arm/mach-nexell/reset.c b/arch/arm/mach-nexell/reset.c index 1f732a3d373..627f568270b 100644 --- a/arch/arm/mach-nexell/reset.c +++ b/arch/arm/mach-nexell/reset.c @@ -8,7 +8,6 @@ *FIXME : Not support device tree & reset control driver. * will remove after support device tree & reset control driver. */ -#include <common.h> #include <asm/io.h> #include <asm/arch/nexell.h> #include <asm/arch/reset.h> diff --git a/arch/arm/mach-nexell/tieoff.c b/arch/arm/mach-nexell/tieoff.c index 5a4744c296a..51cca6744d6 100644 --- a/arch/arm/mach-nexell/tieoff.c +++ b/arch/arm/mach-nexell/tieoff.c @@ -4,7 +4,6 @@ * Youngbok, Park <park@nexell.co.kr> */ -#include <common.h> #include <asm/arch/nexell.h> #include <asm/arch/clk.h> #include <asm/arch/reset.h> diff --git a/arch/arm/mach-nexell/timer.c b/arch/arm/mach-nexell/timer.c index 3b311fd22a5..b35c7b1bb33 100644 --- a/arch/arm/mach-nexell/timer.c +++ b/arch/arm/mach-nexell/timer.c @@ -4,7 +4,6 @@ * Hyunseok, Jung <hsjung@nexell.co.kr> */ -#include <common.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-npcm/npcm7xx/cpu.c b/arch/arm/mach-npcm/npcm7xx/cpu.c index dd74bb9e087..47d51cab5c7 100644 --- a/arch/arm/mach-npcm/npcm7xx/cpu.c +++ b/arch/arm/mach-npcm/npcm7xx/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include <common.h> #include <cpu_func.h> #include <asm/armv7.h> #include <asm/io.h> diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index ed4b1ca5c98..df80687c857 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -3,7 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/pl310.h> diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c index af594526094..a1fb400b264 100644 --- a/arch/arm/mach-npcm/npcm8xx/cpu.c +++ b/arch/arm/mach-npcm/npcm8xx/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include <common.h> #include <dm.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-npcm/npcm8xx/reset.c b/arch/arm/mach-npcm/npcm8xx/reset.c index 6954e6c6a17..e28b4ae7ae4 100644 --- a/arch/arm/mach-npcm/npcm8xx/reset.c +++ b/arch/arm/mach-npcm/npcm8xx/reset.c @@ -3,7 +3,6 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include <common.h> #include <asm/io.h> #include <asm/arch/gcr.h> #include <asm/arch/rst.h> diff --git a/arch/arm/mach-octeontx/clock.c b/arch/arm/mach-octeontx/clock.c index 9da21077ecd..ffdee8799fb 100644 --- a/arch/arm/mach-octeontx/clock.c +++ b/arch/arm/mach-octeontx/clock.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include <common.h> #include <asm/io.h> #include <asm/arch/board.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c index aa5f4585c6f..90454edca25 100644 --- a/arch/arm/mach-octeontx/cpu.c +++ b/arch/arm/mach-octeontx/cpu.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include <common.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-octeontx2/clock.c b/arch/arm/mach-octeontx2/clock.c index 9da21077ecd..ffdee8799fb 100644 --- a/arch/arm/mach-octeontx2/clock.c +++ b/arch/arm/mach-octeontx2/clock.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include <common.h> #include <asm/io.h> #include <asm/arch/board.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c index 723deef719b..0a44af71a40 100644 --- a/arch/arm/mach-octeontx2/cpu.c +++ b/arch/arm/mach-octeontx2/cpu.c @@ -5,7 +5,6 @@ * https://spdx.org/licenses */ -#include <common.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-omap2/abb.c b/arch/arm/mach-omap2/abb.c index 722e6db0566..ce33d2fe129 100644 --- a/arch/arm/mach-omap2/abb.c +++ b/arch/arm/mach-omap2/abb.c @@ -8,7 +8,6 @@ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> */ -#include <common.h> #include <asm/omap_common.h> #include <asm/arch/clock.h> #include <asm/io.h> diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 09659da5867..78c1e965c9f 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <config.h> #include <dm.h> #include <debug_uart.h> #include <errno.h> diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index d4f2abe17a9..4765ce0adee 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -4,7 +4,6 @@ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ -#include <common.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/clk_synthesizer.h> diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c index 0969a404bf6..b75eb58ee82 100644 --- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c +++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c @@ -7,8 +7,7 @@ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/ */ - -#include <common.h> +#include <stdio.h> #include <asm/arch/clk_synthesizer.h> #include <i2c.h> diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c index 3273632c648..f07003c95bc 100644 --- a/arch/arm/mach-omap2/am33xx/clock.c +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -7,7 +7,6 @@ * * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <hang.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index d39e7e4fed1..c33d974dccd 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -7,7 +7,6 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c index 8039bc2fe75..abd65ffd77f 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c @@ -8,7 +8,6 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 61b95c93733..41eec005cb1 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <config.h> #include <log.h> #include <asm/arch/cpu.h> #include <asm/arch/ddr_defs.h> diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index b29250b8d20..f19c66822d2 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -7,7 +7,6 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-omap2/am33xx/fdt.c b/arch/arm/mach-omap2/am33xx/fdt.c index 2ec30b1f9c3..3e81616cb74 100644 --- a/arch/arm/mach-omap2/am33xx/fdt.c +++ b/arch/arm/mach-omap2/am33xx/fdt.c @@ -3,7 +3,6 @@ * Copyright 2017 Texas Instruments, Inc. */ -#include <common.h> #include <hang.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c index 49605593979..06b08e89e7f 100644 --- a/arch/arm/mach-omap2/am33xx/mux.c +++ b/arch/arm/mach-omap2/am33xx/mux.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <common.h> #include <asm/arch/mux.h> #include <asm/arch/hardware.h> #include <asm/io.h> diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 390d540e85a..87afc096602 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -11,7 +11,6 @@ * Syed Mohammed Khasim <khasim@ti.com> */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index aa0ab13d5fb..e1ea3515ac1 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -7,7 +7,6 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include <common.h> #include <ahci.h> #include <log.h> #include <dm/uclass.h> diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 390d1f2a649..2a0c22841d0 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -12,7 +12,6 @@ * Santosh Shilimkar <santosh.shilimkar@ti.com> * Rajendra Nayak <rnayak@ti.com> */ -#include <common.h> #include <hang.h> #include <i2c.h> #include <init.h> diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 9daaeef7319..4d431e20779 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -8,7 +8,7 @@ * Aneesh V <aneesh@ti.com> */ -#include <common.h> +#include <config.h> #include <hang.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-omap2/fdt-common.c b/arch/arm/mach-omap2/fdt-common.c index e90d5776703..c6b4c03b508 100644 --- a/arch/arm/mach-omap2/fdt-common.c +++ b/arch/arm/mach-omap2/fdt-common.c @@ -3,7 +3,7 @@ * Copyright 2016-2017 Texas Instruments, Inc. */ -#include <common.h> +#include <config.h> #include <log.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 0e4572ca41a..138501602c3 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -10,7 +10,6 @@ * Aneesh V <aneesh@ti.com> * Steve Sakoman <steve@sakoman.com> */ -#include <common.h> #include <debug_uart.h> #include <event.h> #include <fdtdec.h> diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 19197482aa4..00f144eb747 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -12,7 +12,7 @@ * Syed Mohammed Khasim <khasim@ti.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/cpu.h> #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 36db5882433..200a08fa5c8 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -11,9 +11,9 @@ * Steve Sakoman <steve@sakoman.com> */ -#include <common.h> #include <cpu_func.h> #include <log.h> +#include <linux/string.h> #include <asm/cache.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-omap2/omap3/am35x_musb.c b/arch/arm/mach-omap2/omap3/am35x_musb.c index 1121acc0058..d3807623bc6 100644 --- a/arch/arm/mach-omap2/omap3/am35x_musb.c +++ b/arch/arm/mach-omap2/omap3/am35x_musb.c @@ -8,8 +8,8 @@ * Hema HK <hemahk@ti.com> */ -#include <common.h> #include <log.h> +#include <time.h> #include <dm/device.h> #include <asm/io.h> #include <asm/arch/am35x_def.h> diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index c76a95dd5d0..c5ada607f97 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -15,7 +15,6 @@ * Syed Mohammed Khasim <khasim@ti.com> * */ -#include <common.h> #include <command.h> #include <dm.h> #include <init.h> diff --git a/arch/arm/mach-omap2/omap3/boot.c b/arch/arm/mach-omap2/omap3/boot.c index ea26115b711..2a36a25e279 100644 --- a/arch/arm/mach-omap2/omap3/boot.c +++ b/arch/arm/mach-omap2/omap3/boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <spl.h> diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index 13685e0567a..417d1eb846f 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -11,11 +11,12 @@ * Syed Mohammed Khasim <khasim@ti.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/clocks_omap3.h> #include <asm/arch/mem.h> +#include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <command.h> diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c index d0d0b7a75a6..7348e92cabd 100644 --- a/arch/arm/mach-omap2/omap3/emac.c +++ b/arch/arm/mach-omap2/omap3/emac.c @@ -6,7 +6,6 @@ * (C) Copyright 2011, Ilya Yanok, Emcraft Systems */ -#include <common.h> #include <net.h> #include <asm/io.h> #include <asm/arch/am35x_def.h> diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 4fbfb387ab0..049eedfeb65 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -9,7 +9,7 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 4d27d82c788..404333689f6 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -21,7 +21,6 @@ * Manikandan Pillai <mani.pillai@ti.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-omap2/omap3/spl_id_nand.c b/arch/arm/mach-omap2/omap3/spl_id_nand.c index 84a0b0ade93..d4712629d9d 100644 --- a/arch/arm/mach-omap2/omap3/spl_id_nand.c +++ b/arch/arm/mach-omap2/omap3/spl_id_nand.c @@ -11,7 +11,6 @@ * Jian Zhang <jzhang@ti.com> */ -#include <common.h> #include <jffs2/load_kernel.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/omap_gpmc.h> diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c index 5f535e27827..1e3fcd59796 100644 --- a/arch/arm/mach-omap2/omap3/sys_info.c +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -11,9 +11,10 @@ * Syed Mohammed Khasim <khasim@ti.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/mem.h> /* get mem tables */ +#include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <asm/bootm.h> #include <asm/omap_common.h> diff --git a/arch/arm/mach-omap2/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c index 90b5380ae39..a60249f7fd6 100644 --- a/arch/arm/mach-omap2/omap4/boot.c +++ b/arch/arm/mach-omap2/omap4/boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> */ -#include <common.h> #include <asm/io.h> #include <asm/omap_common.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-omap2/omap4/emif.c b/arch/arm/mach-omap2/omap4/emif.c index 35a51645be7..5b0d3b5c78a 100644 --- a/arch/arm/mach-omap2/omap4/emif.c +++ b/arch/arm/mach-omap2/omap4/emif.c @@ -8,7 +8,6 @@ * Aneesh V <aneesh@ti.com> */ -#include <common.h> #include <asm/emif.h> #include <asm/arch/sys_proto.h> #include <asm/utils.h> diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c index d587a4d4def..a81d7655494 100644 --- a/arch/arm/mach-omap2/omap4/hw_data.c +++ b/arch/arm/mach-omap2/omap4/hw_data.c @@ -8,7 +8,6 @@ * * Sricharan R <r.sricharan@ti.com> */ -#include <common.h> #include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c index 27dfa9142dc..e3e6cc8e578 100644 --- a/arch/arm/mach-omap2/omap4/hwinit.c +++ b/arch/arm/mach-omap2/omap4/hwinit.c @@ -10,7 +10,6 @@ * Aneesh V <aneesh@ti.com> * Steve Sakoman <steve@sakoman.com> */ -#include <common.h> #include <palmas.h> #include <asm/armv7.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-omap2/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c index 2a18cf0215d..a29a264016e 100644 --- a/arch/arm/mach-omap2/omap4/sdram_elpida.c +++ b/arch/arm/mach-omap2/omap4/sdram_elpida.c @@ -9,7 +9,6 @@ * Aneesh V <aneesh@ti.com> */ -#include <common.h> #include <asm/emif.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c index 2f9f8e65d03..21da0b11661 100644 --- a/arch/arm/mach-omap2/omap5/abb.c +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -8,7 +8,7 @@ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> */ -#include <common.h> +#include <asm/arch/omap.h> #include <asm/omap_common.h> #include <asm/io.h> #include <linux/bitops.h> diff --git a/arch/arm/mach-omap2/omap5/boot.c b/arch/arm/mach-omap2/omap5/boot.c index 15d6836c6ea..5b479a87516 100644 --- a/arch/arm/mach-omap2/omap5/boot.c +++ b/arch/arm/mach-omap2/omap5/boot.c @@ -5,7 +5,6 @@ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> */ -#include <common.h> #include <asm/io.h> #include <asm/omap_common.h> #include <spl.h> diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index 8569eff31ab..d50452b5a30 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -6,7 +6,7 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> +#include <config.h> #include <hang.h> #include <log.h> #include <asm/utils.h> diff --git a/arch/arm/mach-omap2/omap5/emif.c b/arch/arm/mach-omap2/omap5/emif.c index 2de36b6feca..d243ff3bd8f 100644 --- a/arch/arm/mach-omap2/omap5/emif.c +++ b/arch/arm/mach-omap2/omap5/emif.c @@ -8,7 +8,6 @@ * Aneesh V <aneesh@ti.com> for OMAP4 */ -#include <common.h> #include <log.h> #include <asm/emif.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index 0ca02e664c4..f75ec47d821 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -3,7 +3,7 @@ * Copyright 2016 Texas Instruments, Inc. */ -#include <common.h> +#include <config.h> #include <hang.h> #include <log.h> #include <linux/libfdt.h> diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index b39132222ee..e65727026ef 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -8,7 +8,6 @@ * * Sricharan R <r.sricharan@ti.com> */ -#include <common.h> #include <palmas.h> #include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index edab9a92982..7f41e85c4a6 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -11,7 +11,6 @@ * Steve Sakoman <steve@sakoman.com> * Sricharan <r.sricharan@ti.com> */ -#include <common.h> #include <cpu_func.h> #include <palmas.h> #include <asm/armv7.h> diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 786da45fac8..6bf4cf4a758 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -10,7 +10,6 @@ * Sricharan R <r.sricharan@ti.com> */ -#include <common.h> #include <asm/emif.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 64560b21e3f..16bbc93f4a3 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -12,7 +12,7 @@ * Andrew F. Davis <afd@ti.com> */ -#include <common.h> +#include <config.h> #include <command.h> #include <cpu_func.h> #include <hang.h> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 71fdf5bf487..ed0620e7b63 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -15,7 +15,7 @@ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-boot-spl.lds index 1d6e5d45b46..3bb759d8a1c 100644 --- a/arch/arm/mach-omap2/u-boot-spl.lds +++ b/arch/arm/mach-omap2/u-boot-spl.lds @@ -39,12 +39,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; - - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; .bss : diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 0623281a3c7..2326d153b12 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -3,9 +3,9 @@ * Copyright 2011 Linaro Limited * Aneesh V <aneesh@ti.com> */ -#include <common.h> #include <env.h> #include <part.h> +#include <vsprintf.h> #include <asm/setup.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 054782efbdb..cb377aa1272 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <common.h> +#include <config.h> #include <asm/omap_common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index ffae9a01e37..58ee67eca50 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -8,7 +8,6 @@ * Written-by: Prafulla Wadaskar <prafulla@marvell.com> */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <net.h> diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index 5647f847d78..228a3f7ad07 100644 --- a/arch/arm/mach-orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c @@ -8,7 +8,6 @@ * Written-by: Prafulla Wadaskar <prafulla@marvell.com> */ -#include <common.h> #include <config.h> #include <init.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index b373e59e6fe..85736f04e67 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -7,7 +7,7 @@ * Written-by: Prafulla Wadaskar <prafulla@marvell.com> */ -#include <common.h> +#include <config.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index f0f46f2dcb7..0130cad7678 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -5,13 +5,13 @@ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ +#include <config.h> #include <cpu_func.h> #include <init.h> #include <asm/cache.h> #include <asm/global_data.h> #include <linux/arm-smccc.h> #include <linux/psci.h> -#include <common.h> #include <asm/io.h> #include <asm/mach-types.h> #include <asm/psci.h> diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c index 81f6ca2e491..6f0a220320e 100644 --- a/arch/arm/mach-owl/sysmap-owl.c +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ -#include <common.h> #include <asm/armv8/mmu.h> static struct mm_region owl_mem_map[] = { diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index 4dff9e07629..c50700df078 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -7,7 +7,6 @@ #include <asm/armv8/mmu.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include <cpu_func.h> #define GEN3_NR_REGIONS 16 diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 9934a775220..3b3c6f7cde9 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -8,7 +8,6 @@ #include <asm/armv8/mmu.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include <cpu_func.h> #define RZG2L_NR_REGIONS 16 diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 661e7fd1c9f..14b3ab1a572 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -3,6 +3,7 @@ if ARCH_ROCKCHIP config ROCKCHIP_PX30 bool "Support Rockchip PX30" select ARM64 + imply OF_UPSTREAM select SUPPORT_SPL select SUPPORT_TPL select SPL diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index cd226844b63..8a57b8217ff 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -8,7 +8,7 @@ * Based on puma-rk3399.c: * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include <common.h> +#include <config.h> #include <clk.h> #include <cpu_func.h> #include <env.h> diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index f9be396aa55..55e9456668a 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <adc.h> #include <command.h> #include <env.h> diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index b36e559e871..82a0b3efef9 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Google, Inc */ -#include <common.h> #include <hang.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/boot_mode.h> diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index a62ff53c6a0..14c7331e1ab 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -4,7 +4,6 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ -#include <common.h> #include <env.h> #include <init.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index db368a7b8c2..f0b3c5f83f4 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <debug_uart.h> #include <dm.h> #include <init.h> diff --git a/arch/arm/mach-rockchip/px30/clk_px30.c b/arch/arm/mach-rockchip/px30/clk_px30.c index 7edf1321feb..410134769f8 100644 --- a/arch/arm/mach-rockchip/px30/clk_px30.c +++ b/arch/arm/mach-rockchip/px30/clk_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 2ec3289d75b..8b1509e55f2 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <clk.h> #include <dm.h> #include <fdt_support.h> diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c index 37e88f5ccb9..c9de57493d8 100644 --- a/arch/arm/mach-rockchip/px30/syscon_px30.c +++ b/arch/arm/mach-rockchip/px30/syscon_px30.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <log.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 73f6d241a1c..64e100172fa 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -3,7 +3,6 @@ * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <debug_uart.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c index 116dccd7b87..9046601a75e 100644 --- a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index e8130abdd77..6c92b31dc84 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/arch-rockchip/grf_rk3036.h> diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 07cd29a33e6..308b9e6b8a8 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/types.h> #include <asm/arch-rockchip/cru_rk3036.h> diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c index c2fd1607990..23b75269d50 100644 --- a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -3,7 +3,6 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c index c47526dca5d..88057fad050 100644 --- a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 9a95ff85041..70b55ca8abf 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3066.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c index a598f6400de..ff269b53b54 100644 --- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <log.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c index a1b038c6486..ae552af3ff5 100644 --- a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c index 1406d5d0d32..f81c57a48be 100644 --- a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c index 94d1d23e1f4..c0e71c3fa90 100644 --- a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index ffdcaa49a1e..53b2eaa2d53 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <hang.h> #include <init.h> diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index 917ff37c0fc..6df054e5b27 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <log.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c index 2e57672b246..4703125392e 100644 --- a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c index 0d9dca8173c..c471a4c9fb7 100644 --- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index fb4c0891d0d..af6c5d1f59b 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 70cf5002912..d1170f7e23d 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <command.h> #include <dm.h> #include <env.h> diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index 8b2c2f323a7..6413d0a88a1 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <dt-structs.h> #include <log.h> diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c index 201bf661f9b..557e21f8199 100644 --- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index a0915c72bfa..6f88638d156 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -2,7 +2,6 @@ /* *Copyright (c) 2018 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <init.h> #include <malloc.h> #include <asm/arch-rockchip/bootrom.h> diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c index b380ff57233..2d7e9711015 100644 --- a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c @@ -3,7 +3,6 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index 70c0eb6f98e..b0c5af53da6 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rk3328.h> diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index ca3fa81e127..c86d11943d6 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <init.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index d2f267e6353..02ed366d8b6 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <asm/arch-rockchip/clock.h> #include <dm.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c index b075319720d..c4d41e52af0 100644 --- a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -4,7 +4,6 @@ * Author: Andy Yan <andy.yan@rock-chips.org> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 8f5ca1dfa7c..f589bf67328 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -4,7 +4,6 @@ * Copyright (c) 2016 Andreas Färber */ -#include <common.h> #include <init.h> #include <syscon.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index dc2d831dd84..7389c028364 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -5,7 +5,6 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include <common.h> #include <dm.h> #include <log.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 9d9a837fc74..de552b5903b 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 7fa1d7c7b7a..2d7d0f82a2f 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <fdt_support.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 2b5746cb31b..b92ad54ede5 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <log.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c index 8917edcbd30..1c6b2ece602 100644 --- a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index b30ea04f737..1b3e40074e3 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c index 5407e7827f5..255259eabfd 100644 --- a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 820e979abb1..9a35c7d9cc2 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -161,6 +161,31 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_SIGE7_RK3588 + bool "ArmSoM Sige7 RK3588 board" + select BOARD_LATE_INIT + help + ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) + by ArmSoM. + + There are two variants depending on the DRAM size : 8G and 16G. + + Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + 64GB/128GB on board eMMC + uSD slot + 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C + 1x HDMI 2.1 output + 2x 2.5 Gbps Ethernet port + 40-pin IO header including UART, SPI and I2C + USB PD over USB Type-C + Size: 92mm x 62mm + config TARGET_QUARTZPRO64_RK3588 bool "Pine64 QuartzPro64 RK3588 board" select BOARD_LATE_INIT @@ -168,6 +193,36 @@ config TARGET_QUARTZPRO64_RK3588 Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board Computer) by Pine64. +config TARGET_TIGER_RK3588 + bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)" + select BOARD_LATE_INIT + help + The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 + connector) system-on-module from Theobroma Systems, featuring the + Rockchip RK3588. + + It provides the following feature set: + * up to 16GB LPDDR4x + * on-module eMMC + * SD card (on a baseboard) via edge connector + * Gigabit Ethernet with on-module GbE PHY + * HDMI/eDP + * MIPI-DSI + * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) + * HDMI input over FPC connector + * CAN + * USB + - 1x USB 3.0 dual-role (direct connection) + - 2x USB 3.0 host + 1x USB 2.0 host + * PCIe + - 1x PCIe 2.1 Gen3, 4 lanes + - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes + * on-module ATtiny816 companion controller, implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + * on-module Secure Element with Global Platform 2.2.1 compliant + JavaCard environment + config TARGET_TURINGRK1_RK3588 bool "Turing Machines RK1 RK3588 board" select BOARD_LATE_INIT @@ -230,6 +285,7 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x00a00000 +source "board/armsom/sige7-rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/indiedroid/nova/Kconfig" @@ -240,5 +296,6 @@ source "board/radxa/rock5b-rk3588/Kconfig" source "board/rockchip/evb_rk3588/Kconfig" source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" +source "board/theobroma-systems/tiger_rk3588/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c index 3df0bf223e3..250ec423bd2 100644 --- a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c @@ -3,7 +3,6 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd. */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eb65dafe3a2..d3162d3447e 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include <common.h> #include <spl.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c index 7b2cf37d9da..f86567fcaf4 100644 --- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c @@ -3,7 +3,6 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c index 44b53c407a7..5659ae03d71 100644 --- a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -4,7 +4,6 @@ * Author: Andy Yan <andy.yan@rock-chips.com> */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c index babdf5720b2..d68fbf1bd25 100644 --- a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -3,7 +3,6 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c index bd8902718f2..3d64fcd4594 100644 --- a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include <common.h> #include <dm.h> #include <syscon.h> #include <asm/arch-rockchip/clock.h> diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 40eb9eb7b19..1c10e9b9f23 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include <common.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rv1126.h> diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c index 599ea66e3d6..67d2f18a8d0 100644 --- a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c @@ -4,7 +4,6 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include <common.h> #include <dm.h> #include <log.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index f2a3d6b1400..1fb01e1c4b1 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -3,7 +3,7 @@ * Copyright (C) 2017 Rockchip Electronics Co., Ltd. */ -#include <common.h> +#include <config.h> #include <dm.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 3543267aa57..3dce9b30898 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -3,7 +3,6 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include <common.h> #include <dm.h> #include <fdt_support.h> #include <log.h> diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 2c3e9789cc8..50f04f9474a 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include <common.h> #include <bootstage.h> #include <debug_uart.h> #include <dm.h> diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds index ad32654085b..958a1b70aef 100644 --- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -46,12 +46,7 @@ SECTIONS . = ALIGN(8); __image_copy_end = .; - - .end : { - . = ALIGN(8); - *(.__end) - } - + _end = .; _image_binary_end = .; .bss ALIGN(8) : { diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index b390bdf8278..f0aec7c0fe0 100644 --- a/arch/arm/mach-s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c @@ -7,7 +7,6 @@ * based on arch/arm/cpu/armv7/omap3/cache.S */ -#include <common.h> #include <cpu_func.h> #include <asm/cache.h> diff --git a/arch/arm/mach-s5pc1xx/clock.c b/arch/arm/mach-s5pc1xx/clock.c index c90c341b508..b92ce1152f6 100644 --- a/arch/arm/mach-s5pc1xx/clock.c +++ b/arch/arm/mach-s5pc1xx/clock.c @@ -5,7 +5,7 @@ * Heungjun Kim <riverful.kim@samsung.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-s5pc1xx/pinmux.c b/arch/arm/mach-s5pc1xx/pinmux.c index 818d75164de..23b9252827a 100644 --- a/arch/arm/mach-s5pc1xx/pinmux.c +++ b/arch/arm/mach-s5pc1xx/pinmux.c @@ -6,7 +6,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <asm/arch/pinmux.h> int exynos_pinmux_config(int peripheral, int flags) diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig new file mode 100644 index 00000000000..3846b4fd5b6 --- /dev/null +++ b/arch/arm/mach-sc5xx/Kconfig @@ -0,0 +1,475 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> +# Contact: Greg Malysa <greg.malysa@timesys.com> +# + +# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH +# But it is ignored if selected here, so it must be in the defconfig + +if ARCH_SC5XX + +config SC57X + bool + select SUPPORT_SPL + select CPU_V7A + select PANIC_HANG + select COMMON_CLK_ADI_SC57X + select TIMER + select ADI_SC5XX_TIMER + +config SC58X + bool + select SUPPORT_SPL + select CPU_V7A + select PANIC_HANG + select COMMON_CLK_ADI_SC58X + select TIMER + select ADI_SC5XX_TIMER + +config SC59X + bool + select SUPPORT_SPL + select CPU_V7A + select PANIC_HANG + select COMMON_CLK_ADI_SC594 + select TIMER + select ADI_SC5XX_TIMER + select NOP_PHY + +config SC59X_64 + bool + select SUPPORT_SPL + select PANIC_HANG + select MMC_SDHCI_ADMA_FORCE_32BIT + select ARM64 + select DM + select DM_SERIAL + select COMMON_CLK_ADI_SC598 + select GICV3 + select GIC_600_CLEAR_RDPD + select NOP_PHY + +config SC_BOOT_MODE + int "SC5XX boot mode select" + default 1 + range 0 7 + help + Mode 0: do nothing, just idle + Mode 1: boot ldr out of serial flash + Mode 7: boot ldr over uart + +config SC_BOOT_SPI_BUS + int "sc5xx spi boot bus" + default 2 + range 0 4 + help + This is the SPI peripheral number to use for booting, X in the + expression `sf probe X:Y` + +config SC_BOOT_SPI_SSEL + int "sc5xx spi boot chipselect" + default 1 + range 0 6 + help + This is the SPI chip select number to use for booting, Y in the + expression `sf probe X:Y` + +config SC_BOOT_OSPI_BUS + int "sc5xx ospi boot bus" + default 0 + help + This is the OSPI peripheral number to use for booting, X in the + expression `sf probe X:Y` + +config SC_BOOT_OSPI_SSEL + int "sc5xx ospi boot chipselect" + default 0 + help + This is the OSPI chip select number to use for booting, Y in the + expression `sf probe X:Y` + +config SYS_FLASH_BASE + hex + default 0x60000000 + +config UART_CONSOLE + int + default 0 + +config UART4_SERIAL + bool + depends on DM_SERIAL + default y + +config WDT_ADI + bool + default y + +config WATCHDOG_TIMEOUT_MSECS + int + default 30000 + +config DW_PORTS + int + default 1 + +config ADI_BUG_EZKHW21 + bool "SC584 EZKIT phy bug workaround" + depends on SC58X + help + This workaround affects the SC584 EZKIT and addresses bug EZKHW21. + It disables gigabit ethernet mode and limits the board to 100 Mbps + +config ADI_CARRIER_SOMCRR_EZKIT + bool "Support the EV-SOMCRR-EZKIT" + depends on (SC59X || SC59X_64) + help + Say y to include support for the EV-SOMCRR-EZKIT carrier board, + which is compatible with the SC594 and SC598 SOMs. The EZKIT is + mutually incompatible with the EZLITE. + +config ADI_CARRIER_SOMCRR_EZLITE + bool "Support the EV-SOMCRR-EZLITE" + depends on (SC59X || SC59X_64) + help + Say y to include support for the EV-SOMCRR-EZLITE carrier board, + which is compatible with the SC594 and SC598 SOMs. The EZLITE is + mutually incompatible with the EZKIT. + +config ADI_SPL_FORCE_BMODE + int "Force the SPL to use this BMODE device during next boot stage" + default 0 + range 0 9 + depends on SPL + help + Force the SPL to use this BMODE device during next boot stage. + For example, if booting via QSPI, we can force the second stage + Of the boot process to use other peripherals via: + 1 = QSPI -> QSPI + 5 = QSPI -> OSPI + 6 = QSPI -> eMMC + +config ADI_USE_DMC0 + bool "Configure DMC0" + default y + help + During hardware initialization, channel 0 of the DMC will be + initialized. Select this if you have DMC0 connected to external + DDR memory. This is expected to be true for every board using + an SC5xx SoC. + +config ADI_USE_DMC1 + bool "Configure DMC1" + help + During hardware initialization, channel 1 of the DMC will be + initialized. Not all processors have a DMC1. Select this if your + SoC has DMC1 and you have it connected to external DDR memory. + +config ADI_USE_DDR2 + bool "Configure DMC for DDR2 mode" + help + Configure the DMC in DDR2 mode. The default is DDR3 and not all + parts may actually support DDR2. Please consult the manual for + the SoC that you are using to determine if DDR2 mode is supported. + This also requires that DDR2 memory is present on the board or it + will probably cause strange failure. + +menu "Clock configuration" + +config CGU0_DF_DIV + int "CGU0_DF_DIV" + range 0 1 + help + Select 0 to pass CLKIN to PLL + Select 1 to pass CLKIN/2 to PLL + +config CGU0_VCO_MULT + int "CGU0_VCO_MULT" + range 0 127 + help + VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL + A value of 0 means 128 + +config CGU0_CCLK_DIV + int "CGU0_CCLK_DIV" + range 0 31 + help + CCLK_DIV controls the core clock divider + A value of 0 means 32 + CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV + +config CGU0_SCLK_DIV + int "CGU0_SCLK_DIV" + range 0 31 + help + SCLK_DIV controls the system clock divider + A value of 0 means 32 + SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV + +config CGU0_SCLK0_DIV + int "CGU0_SCLK0_DIV" + range 0 7 + help + A value of 0 means 8 + SCLK0 = SCLK / SCLK0_DIV + +config CGU0_SCLK1_DIV + int "CGU0_SCLK1_DIV" + depends on (SC57X || SC58X) + range 0 7 + help + A value of 0 means 8 + SCLK1 = SCLK / SCLK1_DIV + +config CGU0_DCLK_DIV + int "CGU0_DCLK_DIV" + range 0 31 + help + DCLK_DIV controls the DDR clock divider + A value of 0 means 32 + DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV + +config CGU0_OCLK_DIV + int "CGU0_OCLK_DIV" + range 0 127 + help + OCLK_DIV controls the output clock divider + A value of 0 means 128 + OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV + +config CGU0_DIV_S1SELEX + int "CGU0_DIV_S1SELEX" + depends on !SC57X && !SC58X + range 0 255 + help + CGU0 SCLK1 Extended divisor register. + A value of 0 means 256. + SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX + +config CGU0_CLKOUTSEL + int "CGU0_CLKOUTSEL" + default 0 + range 0 31 + help + Select signal driven through CLKOUT pin multiplexer. + This value varies on each SOC. Refer to + CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual + for values applicable to each SOC. + Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively. + +config CGU1_PLL3_DDRCLK + bool "DDRCLK From 3rd PLL" + depends on SC59X_64 + help + 3rd PLL output is connected to DMC block when set. + When cleared, DDR clock is CLKO3 output of CDU. + +config CGU1_PLL3_VCO_MSEL + int "CGU0_PLL3_VCO_MSEL" + depends on CGU1_PLL3_DDRCLK + range 1 128 + help + PLL multiplier value for the 3rd PLL. + DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV + +config CGU1_PLL3_DCLK_DIV + int "CGU0_PLL3_DCLK_DIV" + depends on CGU1_PLL3_DDRCLK + range 1 32 + help + PLL divider value for the 3rd PLL. + DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV + +config CGU1_DF_DIV + int "CGU1_DF_DIV" + range 0 1 + help + Select 0 to pass CLKIN to PLL + Select 1 to pass CLKIN/2 to PLL + +config CGU1_VCO_MULT + int "CGU1_VCO_MULT" + range 0 127 + help + VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL + A value of 0 means 128 + +config CGU1_CCLK_DIV + int "CGU1_CCLK_DIV" + range 0 31 + help + CCLK_DIV controls the core clock divider + A value of 0 means 32 + CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV + +config CGU1_SCLK_DIV + int "CGU1_SCLK_DIV" + range 0 31 + help + SCLK_DIV controls the system clock divider + A value of 0 means 32 + SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV + +config CGU1_SCLK0_DIV + int "CGU1_SCLK0_DIV" + depends on (SC57X || SC58X || SC59X) + range 0 7 + help + A value of 0 means 8 + SCLK0 = SCLK / SCLK0_DIV + +config CGU1_SCLK1_DIV + int "CGU1_SCLK1_DIV" + depends on (SC57X || SC58X) + range 0 7 + help + A value of 0 means 8 + SCLK1 = SCLK / SCLK1_DIV + +config CGU1_DCLK_DIV + int "CGU1_DCLK_DIV" + range 0 31 + help + DCLK_DIV controls the DDR clock divider + A value of 0 means 32 + DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV + +config CGU1_OCLK_DIV + int "CGU1_OCLK_DIV" + range 0 127 + help + OCLK_DIV controls the output clock divider + A value of 0 means 128 + OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV + +config CGU1_DIV_S0SELEX + int "CGU1_DIV_S0SELEX" + depends on !SC57X && !SC58X && !SC59X + range 0 255 + help + CGU1 SCLK0 Extended divisor register. + A value of 0 means 256. + SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX + +config CGU1_DIV_S1SELEX + int "CGU1_DIV_S1SELEX" + depends on !SC57X && !SC58X + range 0 255 + help + CGU1 SCLK1 Extended divisor register. + A value of 0 means 256. + SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX + +config CDU0_CGU1_CLKIN + int "CDU0 CGU1 CLKINn Select" + default 0 + range 0 1 + help + Selects source clock for CGU1. + 0 for CLKIN0 + 1 for CLKIN1 + +config CDU0_CLKO0 + int "CDU0_CLKO0" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO1 + int "CDU0_CLKO1" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO2 + int "CDU0_CLKO2" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO3 + int "CDU0_CLKO3" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO4 + int "CDU0_CLKO4" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO5 + int "CDU0_CLKO5" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO6 + int "CDU0_CLKO6" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO7 + int "CDU0_CLKO7" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO8 + int "CDU0_CLKO8" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO9 + int "CDU0_CLKO9" + range 1 7 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO10 + int "CDU0_CLKO10" + range 1 7 + depends on (SC59X || SC59X_64) + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO12 + int "CDU0_CLKO12" + range 1 7 + depends on (SC59X || SC59X_64) + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO13 + int "CDU0_CLKO13" + range 1 7 + depends on SC59X_64 + help + Clock source select. Refer to SOC Hardware Reference Manual + +config CDU0_CLKO14 + int "CDU0_CLKO14" + range 1 7 + depends on SC59X_64 + help + Clock source select. Refer to SOC Hardware Reference Manual + +endmenu + +config ADI_GPIO + bool + default y + +config PINCTRL_ADI + bool + default y + +endif diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile new file mode 100644 index 00000000000..eeb56c078b3 --- /dev/null +++ b/arch/arm/mach-sc5xx/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> +# Contact: Greg Malysa <greg.malysa@timesys.com> +# + +obj-y += soc.o init/ + +obj-$(CONFIG_SC57X) += sc57x.o +obj-$(CONFIG_SC58X) += sc58x.o +obj-$(CONFIG_SC59X) += sc59x.o +obj-$(CONFIG_SC59X_64) += sc59x_64.o + +obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_SYSCON) += rcu.o diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk new file mode 100644 index 00000000000..580964e559c --- /dev/null +++ b/arch/arm/mach-sc5xx/config.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> +# Contact: Greg Malysa <greg.malysa@timesys.com> +# + +ifdef CONFIG_SPL_BUILD +INPUTS-y += $(obj)/u-boot-spl.ldr +endif + +LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE) +LDR_FLAGS += --use-vmas diff --git a/arch/arm/mach-sc5xx/init/Makefile b/arch/arm/mach-sc5xx/init/Makefile new file mode 100644 index 00000000000..9d4920fe076 --- /dev/null +++ b/arch/arm/mach-sc5xx/init/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# (C) Copyright 2022 - Analog Devices, Inc. +# +# Written and/or maintained by Timesys Corporation +# +# Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> +# Contact: Greg Malysa <greg.malysa@timesys.com> +# + +obj-y += dmcinit.o clkinit.o diff --git a/arch/arm/mach-sc5xx/init/clkinit.c b/arch/arm/mach-sc5xx/init/clkinit.c new file mode 100644 index 00000000000..ae53cd61efd --- /dev/null +++ b/arch/arm/mach-sc5xx/init/clkinit.c @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/io.h> +#include <linux/types.h> +#include "clkinit.h" +#include "dmcinit.h" + +#ifdef CONFIG_CGU0_SCLK0_DIV + #define VAL_CGU0_SCLK0_DIV CONFIG_CGU0_SCLK0_DIV +#else + #define VAL_CGU0_SCLK0_DIV 1 +#endif +#ifdef CONFIG_CGU0_SCLK1_DIV + #define VAL_CGU0_SCLK1_DIV CONFIG_CGU0_SCLK1_DIV +#else + #define VAL_CGU0_SCLK1_DIV 1 +#endif +#ifdef CONFIG_CGU0_DIV_S0SELEX + #define VAL_CGU0_DIV_S0SELEX CONFIG_CGU0_DIV_S0SELEX +#else + #define VAL_CGU0_DIV_S0SELEX -1 +#endif +#ifdef CONFIG_CGU0_DIV_S1SELEX + #define VAL_CGU0_DIV_S1SELEX CONFIG_CGU0_DIV_S1SELEX +#else + #define VAL_CGU0_DIV_S1SELEX -1 +#endif +#ifdef CONFIG_CGU0_CLKOUTSEL + #define VAL_CGU0_CLKOUTSEL CONFIG_CGU0_CLKOUTSEL +#else + #define VAL_CGU0_CLKOUTSEL -1 +#endif +#ifdef CONFIG_CGU1_SCLK0_DIV + #define VAL_CGU1_SCLK0_DIV CONFIG_CGU1_SCLK0_DIV +#else + #define VAL_CGU1_SCLK0_DIV 1 +#endif +#ifdef CONFIG_CGU1_SCLK1_DIV + #define VAL_CGU1_SCLK1_DIV CONFIG_CGU1_SCLK1_DIV +#else + #define VAL_CGU1_SCLK1_DIV 1 +#endif +#ifdef CONFIG_CGU1_DIV_S0SELEX + #define VAL_CGU1_DIV_S0SELEX CONFIG_CGU1_DIV_S0SELEX +#else + #define VAL_CGU1_DIV_S0SELEX -1 +#endif +#ifdef CONFIG_CGU1_DIV_S1SELEX + #define VAL_CGU1_DIV_S1SELEX CONFIG_CGU1_DIV_S1SELEX +#else + #define VAL_CGU1_DIV_S1SELEX -1 +#endif +#ifdef CONFIG_CGU1_CLKOUTSEL + #define VAL_CGU1_CLKOUTSEL CONFIG_CGU1_CLKOUTSEL +#else + #define VAL_CGU1_CLKOUTSEL -1 +#endif + +#define REG_MISC_REG10_tst_addr 0x310A902C + +#define CGU0_REGBASE 0x3108D000 +#define CGU1_REGBASE 0x3108E000 + +#define CGU_CTL 0x00 // CGU0 Control Register +#define CGU_PLLCTL 0x04 // CGU0 PLL Control Register +#define CGU_STAT 0x08 // CGU0 Status Register +#define CGU_DIV 0x0C // CGU0 Clocks Divisor Register +#define CGU_CLKOUTSEL 0x10 // CGU0 CLKOUT Select Register +#define CGU_DIVEX 0x40 // CGU0 DIV Register Extension + +#define BITP_CGU_DIV_OSEL 22 // OUTCLK Divisor +#define BITP_CGU_DIV_DSEL 16 // DCLK Divisor +#define BITP_CGU_DIV_S1SEL 13 // SCLK 1 Divisor +#define BITP_CGU_DIV_SYSSEL 8 // SYSCLK Divisor +#define BITP_CGU_DIV_S0SEL 5 // SCLK 0 Divisor +#define BITP_CGU_DIV_CSEL 0 // CCLK Divisor + +#define BITP_CGU_CTL_MSEL 8 // Multiplier Select +#define BITP_CGU_CTL_DF 0 // Divide Frequency + +#define BITM_CGU_STAT_CLKSALGN 0x00000008 +#define BITM_CGU_STAT_PLOCK 0x00000004 +#define BITM_CGU_STAT_PLLBP 0x00000002 +#define BITM_CGU_STAT_PLLEN 0x00000001 + +/* PLL Multiplier and Divisor Selections (Required Value, Bit Position) */ +/* PLL Multiplier Select */ +#define MSEL(X) (((X) << BITP_CGU_CTL_MSEL) & \ + BITM_CGU_CTL_MSEL) +/* Divide frequency[true or false] */ +#define DF(X) (((X) << BITP_CGU_CTL_DF) & \ + BITM_CGU_CTL_DF) +/* Core Clock Divisor Select */ +#define CSEL(X) (((X) << BITP_CGU_DIV_CSEL) & \ + BITM_CGU_DIV_CSEL) +/* System Clock Divisor Select */ +#define SYSSEL(X) (((X) << BITP_CGU_DIV_SYSSEL) & \ + BITM_CGU_DIV_SYSSEL) +/* SCLK0 Divisor Select */ +#define S0SEL(X) (((X) << BITP_CGU_DIV_S0SEL) & \ + BITM_CGU_DIV_S0SEL) +/* SCLK1 Divisor Select */ +#define S1SEL(X) (((X) << BITP_CGU_DIV_S1SEL) & \ + BITM_CGU_DIV_S1SEL) +/* DDR Clock Divisor Select */ +#define DSEL(X) (((X) << BITP_CGU_DIV_DSEL) & \ + BITM_CGU_DIV_DSEL) +/* OUTCLK Divisor Select */ +#define OSEL(X) (((X) << BITP_CGU_DIV_OSEL) & \ + BITM_CGU_DIV_OSEL) +/* CLKOUT select */ +#define CLKOUTSEL(X) (((X) << BITP_CGU_CLKOUTSEL_CLKOUTSEL) & \ + BITM_CGU_CLKOUTSEL_CLKOUTSEL) +#define S0SELEX(X) (((X) << BITP_CGU_DIVEX_S0SELEX) & \ + BITM_CGU_DIVEX_S0SELEX) +#define S1SELEX(X) (((X) << BITP_CGU_DIVEX_S1SELEX) & \ + BITM_CGU_DIVEX_S1SELEX) + +struct CGU_Settings { + phys_addr_t rbase; + u32 ctl_MSEL:7; + u32 ctl_DF:1; + u32 div_CSEL:5; + u32 div_SYSSEL:5; + u32 div_S0SEL:3; + u32 div_S1SEL:3; + u32 div_DSEL:5; + u32 div_OSEL:7; + s16 divex_S0SELEX; + s16 divex_S1SELEX; + s8 clkoutsel; +}; + +/* CGU Registers */ +#define BITM_CGU_CTL_LOCK 0x80000000 /* Lock */ + +#define BITM_CGU_CTL_MSEL 0x00007F00 /* Multiplier Select */ +#define BITM_CGU_CTL_DF 0x00000001 /* Divide Frequency */ +#define BITM_CGU_CTL_S1SELEXEN 0x00020000 /* SCLK1 Extension Divider Enable */ +#define BITM_CGU_CTL_S0SELEXEN 0x00010000 /* SCLK0 Extension Divider Enable */ + +#define BITM_CGU_DIV_LOCK 0x80000000 /* Lock */ +#define BITM_CGU_DIV_UPDT 0x40000000 /* Update Clock Divisors */ +#define BITM_CGU_DIV_ALGN 0x20000000 /* Align */ +#define BITM_CGU_DIV_OSEL 0x1FC00000 /* OUTCLK Divisor */ +#define BITM_CGU_DIV_DSEL 0x001F0000 /* DCLK Divisor */ +#define BITM_CGU_DIV_S1SEL 0x0000E000 /* SCLK 1 Divisor */ +#define BITM_CGU_DIV_SYSSEL 0x00001F00 /* SYSCLK Divisor */ +#define BITM_CGU_DIV_S0SEL 0x000000E0 /* SCLK 0 Divisor */ +#define BITM_CGU_DIV_CSEL 0x0000001F /* CCLK Divisor */ + +#define BITP_CGU_DIVEX_S0SELEX 0 +#define BITM_CGU_DIVEX_S0SELEX 0x000000FF /* SCLK 0 Extension Divisor */ + +#define BITP_CGU_DIVEX_S1SELEX 16 +#define BITM_CGU_DIVEX_S1SELEX 0x00FF0000 /* SCLK 1 Extension Divisor */ + +#define BITM_CGU_PLLCTL_PLLEN 0x00000008 /* PLL Enable */ +#define BITM_CGU_PLLCTL_PLLBPCL 0x00000002 /* PLL Bypass Clear */ +#define BITM_CGU_PLLCTL_PLLBPST 0x00000001 /* PLL Bypass Set */ + +#define BITP_CGU_CLKOUTSEL_CLKOUTSEL 0 /* CLKOUT Select */ +#define BITM_CGU_CLKOUTSEL_CLKOUTSEL 0x0000001F /* CLKOUT Select */ + +#define CGU_STAT_MASK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK | \ + BITM_CGU_STAT_CLKSALGN) +#define CGU_STAT_ALGN_LOCK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK) + +/* Clock Distribution Unit Registers */ +#define REG_CDU0_CFG0 0x3108F000 +#define REG_CDU0_CFG1 0x3108F004 +#define REG_CDU0_CFG2 0x3108F008 +#define REG_CDU0_CFG3 0x3108F00C +#define REG_CDU0_CFG4 0x3108F010 +#define REG_CDU0_CFG5 0x3108F014 +#define REG_CDU0_CFG6 0x3108F018 +#define REG_CDU0_CFG7 0x3108F01C +#define REG_CDU0_CFG8 0x3108F020 +#define REG_CDU0_CFG9 0x3108F024 +#define REG_CDU0_CFG10 0x3108F028 +#define REG_CDU0_CFG11 0x3108F02C +#define REG_CDU0_CFG12 0x3108F030 +#define REG_CDU0_CFG13 0x3108F034 +#define REG_CDU0_CFG14 0x3108F038 +#define REG_CDU0_STAT 0x3108F040 +#define REG_CDU0_CLKINSEL 0x3108F044 +#define REG_CDU0_REVID 0x3108F048 + +#define BITM_REG10_MSEL3 0x000007F0 +#define BITP_REG10_MSEL3 4 + +#define BITM_REG10_DSEL3 0x0001F000 +#define BITP_REG10_DSEL3 12 + +/* Selected clock macros */ +#define CGUn_MULT(cgu) ((CONFIG_CGU##cgu##_VCO_MULT == 0) ? \ + 128 : CONFIG_CGU##cgu##_VCO_MULT) +#define CGUn_DIV(clkname, cgu) ((CONFIG_CGU##cgu##_##clkname##_DIV == 0) ? \ + 32 : CONFIG_CGU##cgu##_##clkname##_DIV) +#define CCLK1_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ + CGUn_DIV(CCLK, cgu)) +#define CCLK2_n_RATIO(cgu) (((CGUn_MULT(cgu) * 2) / 3) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) +#define DCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ + CGUn_DIV(DCLK, cgu)) +#define SYSCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ + (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ + CGUn_DIV(SCLK, cgu)) +#define PLL3_RATIO ((CONFIG_CGU1_PLL3_VCO_MSEL) / \ + (CONFIG_CGU1_PLL3_DCLK_DIV)) + +#if (1 == CONFIG_CDU0_CLKO2) + #define ARMCLK_IN 0 + #define ARMCLK_RATIO CCLK1_n_RATIO(0) +#elif (3 == CONFIG_CDU0_CLKO2) && \ + (defined(CONFIG_SC57X) || defined(CONFIG_SC58X)) + #define ARMCLK_IN 0 + #define ARMCLK_RATIO SYSCLK_n_RATIO(0) +#elif (5 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64) + #define ARMCLK_IN 0 + #define ARMCLK_RATIO CCLK2_n_RATIO(0) +#elif (7 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64) + #define ARMCLK_IN CDU0_CGU1_CLKIN + #define ARMCLK_RATIO CCLK2_n_RATIO(1) +#endif + +#ifdef CONFIG_CGU1_PLL3_DDRCLK + #define DDRCLK_IN CDU0_CGU1_CLKIN + #define DDRCLK_RATIO PLL3_RATIO +#elif (1 == CONFIG_CDU0_CLKO3) + #define DDRCLK_IN 0 + #define DDRCLK_RATIO DCLK_n_RATIO(0) +#elif (3 == CONFIG_CDU0_CLKO3) + #define DDRCLK_IN CDU0_CGU1_CLKIN + #define DDRCLK_RATIO DCLK_n_RATIO(1) +#endif + +#ifndef ARMCLK_RATIO + #error Invalid/unknown ARMCLK selection! +#endif +#ifndef DDRCLK_RATIO + #error Invalid/unknown DDRCLK selection! +#endif + +#define ARMDDR_CLK_RATIO_FPERCISION 1000 + +#if ARMCLK_IN != DDRCLK_IN + #ifndef CUSTOM_ARMDDR_CLK_RATIO + /** + * SYS_CLKINx are defined within the device tree, not configs. + * Thus, we can only determine cross-CGU clock ratios if they + * use the same SYS_CLKINx. + */ + #error Define CUSTOM_ARMDDR_CLK_RATIO for different SYS_CLKINs + #else + #define ARMDDR_CLK_RATIO CUSTOM_ARMDDR_CLK_RATIO + #endif +#else + #define ARMDDR_CLK_RATIO (ARMDDR_CLK_RATIO_FPERCISION *\ + ARMCLK_RATIO / DDRCLK_RATIO) +#endif + +void dmcdelay(uint32_t delay) +{ + /* There is no zero-overhead loop on ARM, so assume each iteration + * takes 4 processor cycles (based on examination of -O3 and -Ofast + * output). + */ + u32 i, remainder; + + /* Convert DDR cycles to core clock cycles */ + u32 f = delay * ARMDDR_CLK_RATIO; + + delay = f + 500; + delay /= ARMDDR_CLK_RATIO_FPERCISION; + + /* Round up to multiple of 4 */ + remainder = delay % 4; + if (remainder != 0u) + delay += (4u - remainder); + + for (i = 0; i < delay; i += 4) + asm("nop"); +} + +static void program_cgu(const struct CGU_Settings *cgu) +{ + const uintptr_t b = cgu->rbase; + const bool use_extension0 = cgu->divex_S0SELEX >= 0; + const bool use_extension1 = cgu->divex_S1SELEX >= 0; + u32 temp; + + temp = OSEL(cgu->div_OSEL); + temp |= SYSSEL(cgu->div_SYSSEL); + temp |= CSEL(cgu->div_CSEL); + temp |= DSEL(cgu->div_DSEL); + temp |= (S0SEL(cgu->div_S0SEL)); + temp |= (S1SEL(cgu->div_S1SEL)); + temp &= ~BITM_CGU_DIV_LOCK; + + //Put PLL in to Bypass Mode + writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPST, + b + CGU_PLLCTL); + while (!(readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP)) + ; + + while (!((readl(b + CGU_STAT) & CGU_STAT_MASK) == CGU_STAT_ALGN_LOCK)) + ; + + dmcdelay(1000); + + writel(temp & (~BITM_CGU_DIV_ALGN) & (~BITM_CGU_DIV_UPDT), + b + CGU_DIV); + + dmcdelay(1000); + + temp = MSEL(cgu->ctl_MSEL) | DF(cgu->ctl_DF); + if (use_extension0) + temp |= BITM_CGU_CTL_S0SELEXEN; + if (use_extension1) + temp |= BITM_CGU_CTL_S1SELEXEN; + + writel(temp & (~BITM_CGU_CTL_LOCK), b + CGU_CTL); + + if (use_extension0 || use_extension1) { + u32 mask = BITM_CGU_CTL_S1SELEXEN | BITM_CGU_CTL_S0SELEXEN; + + while (!(readl(b + CGU_CTL) & mask)) + ; + + temp = readl(b + CGU_DIVEX); + + if (use_extension0) { + temp &= ~BITM_CGU_DIVEX_S0SELEX; + temp |= S0SELEX(cgu->divex_S0SELEX); + } + + if (use_extension1) { + temp &= ~BITM_CGU_DIVEX_S1SELEX; + temp |= S1SELEX(cgu->divex_S1SELEX); + } + + writel(temp, b + CGU_DIVEX); + } + + dmcdelay(1000); + + //Take PLL out of Bypass Mode + writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPCL, + b + CGU_PLLCTL); + while ((readl(b + CGU_STAT) & + (BITM_CGU_STAT_PLLBP | BITM_CGU_STAT_CLKSALGN))) + ; + + dmcdelay(1000); + + if (cgu->clkoutsel >= 0) { + temp = readl(b + CGU_CLKOUTSEL); + temp &= ~BITM_CGU_CLKOUTSEL_CLKOUTSEL; + temp |= CLKOUTSEL(cgu->clkoutsel); + writel(temp, b + CGU_CLKOUTSEL); + } +} + +void adi_config_third_pll(void) +{ +#if defined(CONFIG_CGU1_PLL3_VCO_MSEL) && defined(CONFIG_CGU1_PLL3_DCLK_DIV) + u32 temp; + + u32 msel = CONFIG_CGU1_PLL3_VCO_MSEL - 1; + u32 dsel = CONFIG_CGU1_PLL3_DCLK_DIV - 1; + + temp = readl(REG_MISC_REG10_tst_addr); + temp &= 0xFFFE0000; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(4000u); + + //update MSEL [10:4] + temp = readl(REG_MISC_REG10_tst_addr); + temp |= ((msel << BITP_REG10_MSEL3) & BITM_REG10_MSEL3); + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x2; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(100000u); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x1; + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x800; + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp &= 0xFFFFF7F8; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(4000u); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= ((dsel << BITP_REG10_DSEL3) & BITM_REG10_DSEL3); + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x4; + writel(temp, REG_MISC_REG10_tst_addr); + + dmcdelay(100000u); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x1; + writel(temp, REG_MISC_REG10_tst_addr); + + temp = readl(REG_MISC_REG10_tst_addr); + temp |= 0x800; + writel(temp, REG_MISC_REG10_tst_addr); +#endif +} + +static void Active_To_Fullon(const struct CGU_Settings *pCGU) +{ + u32 tmp; + + while (1) { + tmp = readl(pCGU->rbase + CGU_STAT); + if ((tmp & BITM_CGU_STAT_PLLEN) && + (tmp & BITM_CGU_STAT_PLLBP)) + break; + } + + writel(BITM_CGU_PLLCTL_PLLBPCL, pCGU->rbase + CGU_PLLCTL); + + while (1) { + tmp = readl(pCGU->rbase + CGU_STAT); + if ((tmp & BITM_CGU_STAT_PLLEN) && + ~(tmp & BITM_CGU_STAT_PLLBP) && + ~(tmp & BITM_CGU_STAT_CLKSALGN)) + break; + } +} + +static void CGU_Init(const struct CGU_Settings *pCGU) +{ + const uintptr_t b = pCGU->rbase; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLEN) + writel(BITM_CGU_PLLCTL_PLLEN, b + CGU_PLLCTL); + + dmcdelay(1000); +#endif + + /* Check if processor is in Active mode */ + if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP) + Active_To_Fullon(pCGU); + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmcdelay(1000); +#endif + + program_cgu(pCGU); +} + +void cgu_init(void) +{ + const struct CGU_Settings dividers0 = { + .rbase = CGU0_REGBASE, + .ctl_MSEL = CONFIG_CGU0_VCO_MULT, + .ctl_DF = CONFIG_CGU0_DF_DIV, + .div_CSEL = CONFIG_CGU0_CCLK_DIV, + .div_SYSSEL = CONFIG_CGU0_SCLK_DIV, + .div_S0SEL = VAL_CGU0_SCLK0_DIV, + .div_S1SEL = VAL_CGU0_SCLK1_DIV, + .div_DSEL = CONFIG_CGU0_DCLK_DIV, + .div_OSEL = CONFIG_CGU0_OCLK_DIV, + .divex_S0SELEX = VAL_CGU0_DIV_S0SELEX, + .divex_S1SELEX = VAL_CGU0_DIV_S1SELEX, + .clkoutsel = VAL_CGU0_CLKOUTSEL, + }; + const struct CGU_Settings dividers1 = { + .rbase = CGU1_REGBASE, + .ctl_MSEL = CONFIG_CGU1_VCO_MULT, + .ctl_DF = CONFIG_CGU1_DF_DIV, + .div_CSEL = CONFIG_CGU1_CCLK_DIV, + .div_SYSSEL = CONFIG_CGU1_SCLK_DIV, + .div_S0SEL = VAL_CGU1_SCLK0_DIV, + .div_S1SEL = VAL_CGU1_SCLK1_DIV, + .div_DSEL = CONFIG_CGU1_DCLK_DIV, + .div_OSEL = CONFIG_CGU1_OCLK_DIV, + .divex_S0SELEX = VAL_CGU1_DIV_S0SELEX, + .divex_S1SELEX = VAL_CGU1_DIV_S1SELEX, + .clkoutsel = VAL_CGU1_CLKOUTSEL, + }; + + CGU_Init(÷rs0); + CGU_Init(÷rs1); +} + +#define CONFIGURE_CDU0(a, b, c) \ + writel(a, b); \ + while (readl(REG_CDU0_STAT) & (1 << (c))) + +void cdu_init(void) +{ + while (readl(REG_CDU0_STAT) & 0xffff) + ; + writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL); + + CONFIGURE_CDU0(CONFIG_CDU0_CLKO0, REG_CDU0_CFG0, 0); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO1, REG_CDU0_CFG1, 1); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO2, REG_CDU0_CFG2, 2); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO3, REG_CDU0_CFG3, 3); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO4, REG_CDU0_CFG4, 4); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO5, REG_CDU0_CFG5, 5); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO6, REG_CDU0_CFG6, 6); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO7, REG_CDU0_CFG7, 7); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO8, REG_CDU0_CFG8, 8); + CONFIGURE_CDU0(CONFIG_CDU0_CLKO9, REG_CDU0_CFG9, 9); +#ifdef CONFIG_CDU0_CLKO10 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO10, REG_CDU0_CFG10, 10); +#endif +#ifdef CONFIG_CDU0_CLKO12 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO12, REG_CDU0_CFG12, 12); +#endif +#ifdef CONFIG_CDU0_CLKO13 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO13, REG_CDU0_CFG13, 13); +#endif +#ifdef CONFIG_CDU0_CLKO14 + CONFIGURE_CDU0(CONFIG_CDU0_CLKO14, REG_CDU0_CFG14, 14); +#endif +} + +void clks_init(void) +{ + adi_dmc_reset_lanes(true); + + cdu_init(); + cgu_init(); + + adi_config_third_pll(); + + adi_dmc_reset_lanes(false); +} diff --git a/arch/arm/mach-sc5xx/init/clkinit.h b/arch/arm/mach-sc5xx/init/clkinit.h new file mode 100644 index 00000000000..b05f4325bfc --- /dev/null +++ b/arch/arm/mach-sc5xx/init/clkinit.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef CLKINIT_H_ +#define CLKINIT_H_ + +void clks_init(void); + +void dmcdelay(uint32_t delay); + +#endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c new file mode 100644 index 00000000000..e375b5c9dfa --- /dev/null +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -0,0 +1,954 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/io.h> +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <linux/types.h> +#include "clkinit.h" +#include "dmcinit.h" + +#define REG_DMC0_BASE 0x31070000 +#define REG_DMC1_BASE 0x31073000 + +#define REG_DMC_CTL 0x0004 // Control Register +#define REG_DMC_STAT 0x0008 // Status Register +#define REG_DMC_CFG 0x0040 // Configuration Register +#define REG_DMC_TR0 0x0044 // Timing 0 Register +#define REG_DMC_TR1 0x0048 // Timing 1 Register +#define REG_DMC_TR2 0x004C // Timing 2 Register +#define REG_DMC_MR 0x0060 // Shadow MR Register (DDR3) +#define REG_DMC_EMR1 0x0064 // Shadow EMR1 Register +#define REG_DMC_EMR2 0x0068 // Shadow EMR2 Register +#define REG_DMC_EMR3 0x006C +#define REG_DMC_DLLCTL 0x0080 // DLL Control Register +#define REG_DMC_DT_CALIB_ADDR 0x0090 // Data Calibration Address Register +#define REG_DMC_CPHY_CTL 0x01C0 // Controller to PHY Interface Register + +/* SC57x && SC58x DMC REGs */ +#define REG_DMC_PHY_CTL0 0x1000 // PHY Control 0 Register +#define REG_DMC_PHY_CTL1 0x1004 // PHY Control 1 Register +#define REG_DMC_PHY_CTL2 0x1008 // PHY Control 2 Register +#define REG_DMC_PHY_CTL3 0x100c // PHY Control 3 Register +#define REG_DMC_PHY_CTL4 0x1010 // PHY Control 4 Register +#define REG_DMC_CAL_PADCTL0 0x1034 // CALIBRATION PAD CTL 0 Register +#define REG_DMC_CAL_PADCTL2 0x103C // CALIBRATION PAD CTL2 Register +/* END */ + +/* SC59x DMC REGs */ +#define REG_DMC_DDR_LANE0_CTL0 0x1000 // Data Lane 0 Control Register 0 +#define REG_DMC_DDR_LANE0_CTL1 0x1004 // Data Lane 0 Control Register 1 +#define REG_DMC_DDR_LANE1_CTL0 0x100C // Data Lane 1 Control Register 0 +#define REG_DMC_DDR_LANE1_CTL1 0x1010 // Data Lane 1 Control Register 1 +#define REG_DMC_DDR_ROOT_CTL 0x1018 // DDR ROOT Module Control Register +#define REG_DMC_DDR_ZQ_CTL0 0x1034 // DDR Calibration Control Register 0 +#define REG_DMC_DDR_ZQ_CTL1 0x1038 // DDR Calibration Control Register 1 +#define REG_DMC_DDR_ZQ_CTL2 0x103C // DDR Calibration Control Register 2 +#define REG_DMC_DDR_CA_CTL 0x1068 // DDR CA Lane Control Register +/* END */ + +#define REG_DMC_DDR_SCRATCH_2 0x1074 +#define REG_DMC_DDR_SCRATCH_3 0x1078 +#define REG_DMC_DDR_SCRATCH_6 0x1084 +#define REG_DMC_DDR_SCRATCH_7 0x1088 + +#define REG_DMC_DDR_SCRATCH_STAT0 0x107C +#define REG_DMC_DDR_SCRATCH_STAT1 0x1080 + +#define DMC0_DATA_CALIB_ADD 0x80000000 +#define DMC1_DATA_CALIB_ADD 0xC0000000 + +#define BITM_DMC_CFG_EXTBANK 0x0000F000 /* External Banks */ +#define ENUM_DMC_CFG_EXTBANK1 0x00000000 /* EXTBANK: 1 External Bank */ +#define BITM_DMC_CFG_SDRSIZE 0x00000F00 /* SDRAM Size */ +#define ENUM_DMC_CFG_SDRSIZE64 0x00000000 /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */ +#define ENUM_DMC_CFG_SDRSIZE128 0x00000100 /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */ +#define ENUM_DMC_CFG_SDRSIZE256 0x00000200 /* SDRSIZE: 256M Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE512 0x00000300 /* SDRSIZE: 512M Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE1G 0x00000400 /* SDRSIZE: 1G Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE2G 0x00000500 /* SDRSIZE: 2G Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE4G 0x00000600 /* SDRSIZE: 4G Bit SDRAM */ +#define ENUM_DMC_CFG_SDRSIZE8G 0x00000700 /* SDRSIZE: 8G Bit SDRAM */ +#define BITM_DMC_CFG_SDRWID 0x000000F0 /* SDRAM Width */ +#define ENUM_DMC_CFG_SDRWID16 0x00000020 /* SDRWID: 16-Bit Wide SDRAM */ +#define BITM_DMC_CFG_IFWID 0x0000000F /* Interface Width */ +#define ENUM_DMC_CFG_IFWID16 0x00000002 /* IFWID: 16-Bit Wide Interface */ + +#define BITM_DMC_CTL_DDR3EN 0x00000001 +#define BITM_DMC_CTL_INIT 0x00000004 +#define BITP_DMC_STAT_INITDONE 2 /* Initialization Done */ +#define BITM_DMC_STAT_INITDONE 0x00000004 + +#define BITP_DMC_CTL_AL_EN 27 +#define BITP_DMC_CTL_ZQCL 25 /* ZQ Calibration Long */ +#define BITP_DMC_CTL_ZQCS 24 /* ZQ Calibration Short */ +#define BITP_DMC_CTL_DLLCAL 13 /* DLL Calibration Start */ +#define BITP_DMC_CTL_PPREF 12 /* Postpone Refresh */ +#define BITP_DMC_CTL_RDTOWR 9 /* Read-to-Write Cycle */ +#define BITP_DMC_CTL_ADDRMODE 8 /* Addressing (Page/Bank) Mode */ +#define BITP_DMC_CTL_RESET 7 /* Reset SDRAM */ +#define BITP_DMC_CTL_PREC 6 /* Precharge */ +#define BITP_DMC_CTL_DPDREQ 5 /* Deep Power Down Request */ +#define BITP_DMC_CTL_PDREQ 4 /* Power Down Request */ +#define BITP_DMC_CTL_SRREQ 3 /* Self Refresh Request */ +#define BITP_DMC_CTL_INIT 2 /* Initialize DRAM Start */ +#define BITP_DMC_CTL_LPDDR 1 /* Low Power DDR Mode */ +#define BITP_DMC_CTL_DDR3EN 0 /* DDR3 Mode */ + +#ifdef CONFIG_TARGET_SC584_EZKIT + #define DMC_PADCTL2_VALUE 0x0078283C +#elif CONFIG_TARGET_SC573_EZKIT + #define DMC_PADCTL2_VALUE 0x00782828 +#elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT + #define DMC_PADCTL2_VALUE 0x00783C3C +#elif defined(CONFIG_SC57X) || defined(CONFIG_SC58X) + #error "PADCTL2 not specified for custom board!" +#else + //Newer DMC. Legacy calibration obsolete + #define DMC_PADCTL2_VALUE 0x0 +#endif + +#define DMC_CPHYCTL_VALUE 0x0000001A + +#define BITP_DMC_MR1_QOFF 12 /* Output Buffer Enable */ +#define BITP_DMC_MR1_TDQS 11 /* Termination Data Strobe */ +#define BITP_DMC_MR1_RTT2 9 /* Rtt_nom */ +#define BITP_DMC_MR1_WL 7 /* Write Leveling Enable. */ +#define BITP_DMC_MR1_RTT1 6 /* Rtt_nom */ +#define BITP_DMC_MR1_DIC1 5 /* Output Driver Impedance Control */ +#define BITP_DMC_MR1_AL 3 /* Additive Latency */ +#define BITP_DMC_MR1_RTT0 2 /* Rtt_nom */ +#define BITP_DMC_MR1_DIC0 1 /* Output Driver Impedance control */ +#define BITP_DMC_MR1_DLLEN 0 /* DLL Enable */ + +#define BITP_DMC_MR2_CWL 3 /* CAS write Latency */ + +#define BITP_DMC_TR0_TMRD 28 /* Timing Mode Register Delay */ +#define BITP_DMC_TR0_TRC 20 /* Timing Row Cycle */ +#define BITP_DMC_TR0_TRAS 12 /* Timing Row Active Time */ +#define BITP_DMC_TR0_TRP 8 /* Timing RAS Precharge. */ +#define BITP_DMC_TR0_TWTR 4 /* Timing Write to Read */ +#define BITP_DMC_TR0_TRCD 0 /* Timing RAS to CAS Delay */ + +#define BITP_DMC_TR1_TRRD 28 /* Timing Read-Read Delay */ +#define BITP_DMC_TR1_TRFC 16 /* Timing Refresh-to-Command */ +#define BITP_DMC_TR1_TREF 0 /* Timing Refresh Interval */ + +#define BITP_DMC_TR2_TCKE 20 /* Timing Clock Enable */ +#define BITP_DMC_TR2_TXP 16 /* Timing Exit Powerdown */ +#define BITP_DMC_TR2_TWR 12 /* Timing Write Recovery */ +#define BITP_DMC_TR2_TRTP 8 /* Timing Read-to-Precharge */ +#define BITP_DMC_TR2_TFAW 0 /* Timing Four-Activated-Window */ + +#define BITP_DMC_MR_PD 12 /* Active Powerdown Mode */ +#define BITP_DMC_MR_WRRECOV 9 /* Write Recovery */ +#define BITP_DMC_MR_DLLRST 8 /* DLL Reset */ +#define BITP_DMC_MR_CL 4 /* CAS Latency */ +#define BITP_DMC_MR_CL0 2 /* CAS Latency */ +#define BITP_DMC_MR_BLEN 0 /* Burst Length */ + +#define BITP_DMC_DLLCTL_DATACYC 8 /* Data Cycles */ +#define BITP_DMC_DLLCTL_DLLCALRDCNT 0 /* DLL Calibration RD Count */ + +#define BITM_DMC_DLLCTL_DATACYC 0x00000F00 /* Data Cycles */ +#define BITM_DMC_DLLCTL_DLLCALRDCNT 0x000000FF /* DLL Calib RD Count */ + +#define BITP_DMC_STAT_PHYRDPHASE 20 /* PHY Read Phase */ + +#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */ +#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */ +#define BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */ +#define BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */ +#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */ +#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */ +#define BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE 10 /* Pipeline offset for PHYC_DATACYCLE */ +#define BITM_DMC_DDR_ROOT_CTL_SW_REFRESH 0x00002000 /* Refresh Lane DLL Code */ +#define BITM_DMC_DDR_CA_CTL_SW_REFRESH 0x00004000 /* Refresh Lane DLL Code */ + +#define BITP_DMC_CTL_RL_DQS 26 /* RL_DQS */ +#define BITM_DMC_CTL_RL_DQS 0x04000000 /* RL_DQS */ +#define BITP_DMC_EMR3_MPR 2 /* Multi Purpose Read Enable (Read Leveling)*/ +#define BITM_DMC_EMR3_MPR 0x00000004 /* Multi Purpose Read Enable (Read Leveling)*/ +#define BITM_DMC_MR1_WL 0x00000080 /* Write Leveling Enable.*/ +#define BITM_DMC_STAT_PHYRDPHASE 0x00F00000 /* PHY Read Phase */ + +#define BITP_DMC_DDR_LANE0_CTL1_BYPCODE 10 +#define BITM_DMC_DDR_LANE0_CTL1_BYPCODE 0x00007C00 +#define BITP_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 15 +#define BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 0x00008000 + +#define DMC_ZQCTL0_VALUE 0x00785A64 +#define DMC_ZQCTL1_VALUE 0 +#define DMC_ZQCTL2_VALUE 0x70000000 + +#define DMC_TRIG_CALIB 0 +#define DMC_OFSTDCYCLE 2 + +#define BITP_DMC_CAL_PADCTL0_RTTCALEN 31 /* RTT Calibration Enable */ +#define BITP_DMC_CAL_PADCTL0_PDCALEN 30 /* PULLDOWN Calib Enable */ +#define BITP_DMC_CAL_PADCTL0_PUCALEN 29 /* PULLUP Calib Enable */ +#define BITP_DMC_CAL_PADCTL0_CALSTRT 28 /* Start New Calib ( Hardware Cleared) */ +#define BITM_DMC_CAL_PADCTL0_RTTCALEN 0x80000000 /* RTT Calibration Enable */ +#define BITM_DMC_CAL_PADCTL0_PDCALEN 0x40000000 /* PULLDOWN Calib Enable */ +#define BITM_DMC_CAL_PADCTL0_PUCALEN 0x20000000 /* PULLUP Calib Enable */ +#define BITM_DMC_CAL_PADCTL0_CALSTRT 0x10000000 /* Start New Calib ( Hardware Cleared) */ +#define ENUM_DMC_PHY_CTL4_DDR3 0x00000000 /* DDRMODE: DDR3 Mode */ +#define ENUM_DMC_PHY_CTL4_DDR2 0x00000001 /* DDRMODE: DDR2 Mode */ +#define ENUM_DMC_PHY_CTL4_LPDDR 0x00000003 /* DDRMODE: LPDDR Mode */ + +#define BITP_DMC_DDR_ZQ_CTL0_IMPRTT 16 /* Data/DQS ODT */ +#define BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ 8 /* Data/DQS/DM/CLK Drive Strength */ +#define BITP_DMC_DDR_ZQ_CTL0_IMPWRADD 0 /* Address/Command Drive Strength */ +#define BITM_DMC_DDR_ZQ_CTL0_IMPRTT 0x00FF0000 /* Data/DQS ODT */ +#define BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ 0x0000FF00 /* Data/DQS/DM/CLK Drive Strength */ +#define BITM_DMC_DDR_ZQ_CTL0_IMPWRADD 0x000000FF /* Address/Command Drive Strength */ + +#define BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL 0x00200000 /* All Lane Read Status */ + +#if defined(CONFIG_ADI_USE_DDR2) + #define DMC_MR0_VALUE \ + ((DMC_BL / 4 + 1) << BITP_DMC_MR_BLEN) | \ + (DMC_CL << BITP_DMC_MR_CL) | \ + (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) + + #define DMC_MR1_VALUE \ + (DMC_MR1_AL << BITP_DMC_MR1_AL | 0x04) \ + + #define DMC_MR2_VALUE 0 + #define DMC_MR3_VALUE 0 + + #define DMC_CTL_VALUE \ + (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \ + (1 << BITP_DMC_CTL_DLLCAL) | \ + (BITM_DMC_CTL_INIT) +#else + #define DMC_MR0_VALUE \ + (0 << BITP_DMC_MR_BLEN) | \ + (DMC_CL0 << BITP_DMC_MR_CL0) | \ + (DMC_CL123 << BITP_DMC_MR_CL) | \ + (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) | \ + (1 << BITP_DMC_MR_DLLRST) + + #define DMC_MR1_VALUE \ + (DMC_MR1_DLLEN << BITP_DMC_MR1_DLLEN) | \ + (DMC_MR1_DIC0 << BITP_DMC_MR1_DIC0) | \ + (DMC_MR1_RTT0 << BITP_DMC_MR1_RTT0) | \ + (DMC_MR1_AL << BITP_DMC_MR1_AL) | \ + (DMC_MR1_DIC1 << BITP_DMC_MR1_DIC1) | \ + (DMC_MR1_RTT1 << BITP_DMC_MR1_RTT1) | \ + (DMC_MR1_RTT2 << BITP_DMC_MR1_RTT2) | \ + (DMC_MR1_WL << BITP_DMC_MR1_WL) | \ + (DMC_MR1_TDQS << BITP_DMC_MR1_TDQS) | \ + (DMC_MR1_QOFF << BITP_DMC_MR1_QOFF) + + #define DMC_MR2_VALUE \ + ((DMC_WL) << BITP_DMC_MR2_CWL) + + #define DMC_MR3_VALUE \ + ((DMC_WL) << BITP_DMC_MR2_CWL) + + #define DMC_CTL_VALUE \ + (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \ + (BITM_DMC_CTL_INIT) | \ + (BITM_DMC_CTL_DDR3EN) | \ + (DMC_CTL_AL_EN << BITP_DMC_CTL_AL_EN) +#endif + +#define DMC_DLLCTL_VALUE \ + (DMC_DATACYC << BITP_DMC_DLLCTL_DATACYC) | \ + (DMC_DLLCALRDCNT << BITP_DMC_DLLCTL_DLLCALRDCNT) + +#define DMC_CFG_VALUE \ + ENUM_DMC_CFG_IFWID16 | \ + ENUM_DMC_CFG_SDRWID16 | \ + SDR_CHIP_SIZE | \ + ENUM_DMC_CFG_EXTBANK1 + +#define DMC_TR0_VALUE \ + (DMC_TRCD << BITP_DMC_TR0_TRCD) | \ + (DMC_TWTR << BITP_DMC_TR0_TWTR) | \ + (DMC_TRP << BITP_DMC_TR0_TRP) | \ + (DMC_TRAS << BITP_DMC_TR0_TRAS) | \ + (DMC_TRC << BITP_DMC_TR0_TRC) | \ + (DMC_TMRD << BITP_DMC_TR0_TMRD) + +#define DMC_TR1_VALUE \ + (DMC_TREF << BITP_DMC_TR1_TREF) | \ + (DMC_TRFC << BITP_DMC_TR1_TRFC) | \ + (DMC_TRRD << BITP_DMC_TR1_TRRD) + +#define DMC_TR2_VALUE \ + (DMC_TFAW << BITP_DMC_TR2_TFAW) | \ + (DMC_TRTP << BITP_DMC_TR2_TRTP) | \ + (DMC_TWR << BITP_DMC_TR2_TWR) | \ + (DMC_TXP << BITP_DMC_TR2_TXP) | \ + (DMC_TCKE << BITP_DMC_TR2_TCKE) + +enum DDR_MODE { + DDR3_MODE, + DDR2_MODE, + LPDDR_MODE, +}; + +enum CALIBRATION_MODE { + CALIBRATION_LEGACY, + CALIBRATION_METHOD1, + CALIBRATION_METHOD2, +}; + +static struct dmc_param { + phys_addr_t reg; + u32 ddr_mode; + u32 padctl2_value; + u32 dmc_cphyctl_value; + u32 dmc_cfg_value; + u32 dmc_dllctl_value; + u32 dmc_ctl_value; + u32 dmc_tr0_value; + u32 dmc_tr1_value; + u32 dmc_tr2_value; + u32 dmc_mr0_value; + u32 dmc_mr1_value; + u32 dmc_mr2_value; + u32 dmc_mr3_value; + u32 dmc_zqctl0_value; + u32 dmc_zqctl1_value; + u32 dmc_zqctl2_value; + u32 dmc_data_calib_add_value; + bool phy_init_required; + bool anomaly_20000037_applicable; + enum CALIBRATION_MODE calib_mode; +} dmc; + +#ifdef CONFIG_SC59X_64 +#define DQS_DEFAULT_DELAY 3ul + +#define DELAYTRIM 1 +#define LANE0_DQS_DELAY 1 +#define LANE1_DQS_DELAY 1 + +#define CLKDIR 0ul + +#define DQSTRIM 0 +#define DQSCODE 0ul + +#define CLKTRIM 0 +#define CLKCODE 0ul +#endif + +static inline void calibration_legacy(void) +{ + u32 temp; + + /* 1. Set DDR mode to DDR3/DDR2/LPDDR in DMCx_PHY_CTL4 register */ + if (dmc.ddr_mode == DDR3_MODE) + writel(ENUM_DMC_PHY_CTL4_DDR3, dmc.reg + REG_DMC_PHY_CTL4); + else if (dmc.ddr_mode == DDR2_MODE) + writel(ENUM_DMC_PHY_CTL4_DDR2, dmc.reg + REG_DMC_PHY_CTL4); + else if (dmc.ddr_mode == LPDDR_MODE) + writel(ENUM_DMC_PHY_CTL4_LPDDR, dmc.reg + REG_DMC_PHY_CTL4); + + /* + * 2. Make sure that the bits 6, 7, 25, and 27 of the DMC_PHY_ + * CTL3 register are set + */ + writel(0x0A0000C0, dmc.reg + REG_DMC_PHY_CTL3); + + /* + * 3. For DDR2/DDR3 mode, make sure that the bits 0, 1, 2, 3 of + * the DMC_PHY_CTL0 register and the bits 26, 27, 28, 29, 30, 31 + * of the DMC_PHY_CTL2 are set. + */ + if (dmc.ddr_mode == DDR3_MODE || + dmc.ddr_mode == DDR2_MODE) { + writel(0XFC000000, dmc.reg + REG_DMC_PHY_CTL2); + writel(0x0000000f, dmc.reg + REG_DMC_PHY_CTL0); + } + + writel(0x00000000, dmc.reg + REG_DMC_PHY_CTL1); + + /* 4. For DDR3 mode, set bit 1 and configure bits [5:2] of the + * DMC_CPHY_CTL register with WL=CWL+AL in DCLK cycles. + */ + if (dmc.ddr_mode == DDR3_MODE) + writel(dmc.dmc_cphyctl_value, dmc.reg + REG_DMC_CPHY_CTL); + /* 5. Perform On Die Termination(ODT) & Driver Impedance Calibration */ + if (dmc.ddr_mode == LPDDR_MODE) { + /* Bypass processor ODT */ + writel(0x80000, dmc.reg + REG_DMC_PHY_CTL1); + } else { + /* Set bits RTTCALEN, PDCALEN, PUCALEN of register */ + temp = BITM_DMC_CAL_PADCTL0_RTTCALEN | + BITM_DMC_CAL_PADCTL0_PDCALEN | + BITM_DMC_CAL_PADCTL0_PUCALEN; + writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0); + /* Configure ODT and drive impedance values in the + * DMCx_CAL_PADCTL2 register + */ + writel(dmc.padctl2_value, dmc.reg + REG_DMC_CAL_PADCTL2); + /* start calibration */ + temp |= BITM_DMC_CAL_PADCTL0_CALSTRT; + writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0); + /* Wait for PAD calibration to complete - 300 DCLK cycle. + * Worst case: CCLK=450 MHz, DCLK=125 MHz + */ + dmcdelay(300); + } +} + +static inline void calibration_method1(void) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_ZQ_CTL0); + writel(dmc.dmc_zqctl1_value, dmc.reg + REG_DMC_DDR_ZQ_CTL1); + writel(dmc.dmc_zqctl2_value, dmc.reg + REG_DMC_DDR_ZQ_CTL2); + + /* Generate the trigger */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x00010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(8000u); + + /* The [31:26] bits may change if pad ring changes */ + writel(0x0C000001ul | DMC_TRIG_CALIB, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(8000u); + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); +#endif +} + +static inline void calibration_method2(void) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + u32 stat_value = 0x0u; + u32 drv_pu, drv_pd, odt_pu, odt_pd; + u32 ro_dt, clk_dqs_drv_impedance; + u32 temp; + + /* Reset trigger */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + + /* Writing internal registers in calib pad to zero. Calib mode set + * to 1 [26], trig M1 S1 write [16], this enables usage of scratch + * registers instead of ZQCTL registers + */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + /* TRIGGER FOR M2-S2 WRITE -> slave id 31:26 trig m2,s2 write + * bit 1->1 slave1 address is 4 + */ + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + /* reset Trigger */ + writel(0x0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + + /* write to slave 1, make the power down bit high */ + writel(0x1ul << 12, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + dmcdelay(2500u); + + /* Calib mode set to 1 [26], trig M1 S1 write [16] */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0, dmc.reg + REG_DMC_DDR_SCRATCH_3); + + /* for slave 0 */ + writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_SCRATCH_2); + + /* Calib mode set to 1 [26], trig M1 S1 write [16] */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + writel(0x0C000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + + /* writing to slave 1 + * calstrt is 0, but other programming is done + * + * make power down LOW again, to kickstart BIAS circuit + */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x30000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + + /* write to ca_ctl lane, calib mode set to 1 [26], + * trig M1 S1 write [16] + */ + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + + /* copies data to lane controller slave + * TRIGGER FOR M2-S2 WRITE -> slave id 31:26 + * trig m2,s2 write bit 1->1 + * slave1 address is 4 + */ + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + + /* reset Trigger */ + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); + writel(0x50000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x0C000004u, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL, + dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + // calculate ODT PU and PD values + stat_value = ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_7) & 0x0000FFFFu) << + 16); + stat_value |= ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_6) & 0xFFFF0000u) >> + 16); + clk_dqs_drv_impedance = ((dmc.dmc_zqctl0_value) & + BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ) >> BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ; + ro_dt = ((dmc.dmc_zqctl0_value) & BITM_DMC_DDR_ZQ_CTL0_IMPRTT) >> + BITP_DMC_DDR_ZQ_CTL0_IMPRTT; + drv_pu = stat_value & 0x0000003Fu; + drv_pd = (stat_value >> 12) & 0x0000003Fu; + odt_pu = (drv_pu * clk_dqs_drv_impedance) / ro_dt; + odt_pd = (drv_pd * clk_dqs_drv_impedance) / ro_dt; + temp = ((1uL << 24) | + ((drv_pd & 0x0000003Fu)) | + ((odt_pd & 0x0000003Fu) << 6) | + ((drv_pu & 0x0000003Fu) << 12) | + ((odt_pu & 0x0000003Fu) << 18)); + temp |= readl(dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(temp, dmc.reg + REG_DMC_DDR_SCRATCH_2); + writel(0x0C010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x08000002u, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + writel(0x04010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x80000002u, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(2500u); + writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); + writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); +#endif +} + +static inline void adi_dmc_lane_reset(bool reset, uint32_t dmc_no) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + u32 temp; + phys_addr_t base = (dmc_no == 0) ? REG_DMC0_BASE : REG_DMC1_BASE; + phys_addr_t ln0 = base + REG_DMC_DDR_LANE0_CTL0; + phys_addr_t ln1 = base + REG_DMC_DDR_LANE1_CTL0; + + if (reset) { + temp = readl(ln0); + temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL; + writel(temp, ln0); + + temp = readl(ln1); + temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL; + writel(temp, ln1); + } else { + temp = readl(ln0); + temp &= ~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL; + writel(temp, ln0); + + temp = readl(ln1); + temp &= ~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL; + writel(temp, ln1); + } + dmcdelay(9000u); +#endif +} + +void adi_dmc_reset_lanes(bool reset) +{ + if (!IS_ENABLED(CONFIG_ADI_USE_DDR2)) { + if (IS_ENABLED(CONFIG_SC59X) || IS_ENABLED(CONFIG_SC59X_64)) { + if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) + adi_dmc_lane_reset(reset, 0); + if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) + adi_dmc_lane_reset(reset, 1); + } + else { + u32 temp = reset ? 0x800 : 0x0; + + if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) + writel(temp, REG_DMC0_BASE + REG_DMC_PHY_CTL0); + if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) + writel(temp, REG_DMC1_BASE + REG_DMC_PHY_CTL0); + } + } +} + +static inline void dmc_controller_init(void) +{ +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + u32 phyphase, rd_cnt, t_EMR1, t_EMR3, t_CTL, data_cyc, temp; +#endif + + /* 1. Program the DMC controller registers: DMCx_CFG, DMCx_TR0, + * DMCx_TR1, DMCx_TR2, DMCx_MR(DDR2/LPDDR)/DMCx_MR0(DDR3), + * DMCx_EMR1(DDR2)/DMCx_MR1(DDR3), + * DMCx_EMR2(DDR2)/DMCx_EMR(LPDDR)/DMCx_MR2(DDR3) + */ + writel(dmc.dmc_cfg_value, dmc.reg + REG_DMC_CFG); + writel(dmc.dmc_tr0_value, dmc.reg + REG_DMC_TR0); + writel(dmc.dmc_tr1_value, dmc.reg + REG_DMC_TR1); + writel(dmc.dmc_tr2_value, dmc.reg + REG_DMC_TR2); + writel(dmc.dmc_mr0_value, dmc.reg + REG_DMC_MR); + writel(dmc.dmc_mr1_value, dmc.reg + REG_DMC_EMR1); + writel(dmc.dmc_mr2_value, dmc.reg + REG_DMC_EMR2); + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + writel(dmc.dmc_mr3_value, dmc.reg + REG_DMC_EMR3); + writel(dmc.dmc_dllctl_value, dmc.reg + REG_DMC_DLLCTL); + dmcdelay(2000u); + + temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL); + temp |= BITM_DMC_DDR_CA_CTL_SW_REFRESH; + writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL); + dmcdelay(5u); + + temp = readl(dmc.reg + REG_DMC_DDR_ROOT_CTL); + temp |= BITM_DMC_DDR_ROOT_CTL_SW_REFRESH | + (DMC_OFSTDCYCLE << BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE); + writel(temp, dmc.reg + REG_DMC_DDR_ROOT_CTL); +#endif + + /* 2. Make sure that the REG_DMC_DT_CALIB_ADDR register is programmed + * to an unused DMC location corresponding to a burst of 16 bytes + * (by default it is the starting address of the DMC address range). + */ +#ifndef CONFIG_SC59X + writel(dmc.dmc_data_calib_add_value, dmc.reg + REG_DMC_DT_CALIB_ADDR); +#endif + /* 3. Program the DMCx_CTL register with INIT bit set to start + * the DMC initialization sequence + */ + writel(dmc.dmc_ctl_value, dmc.reg + REG_DMC_CTL); + /* 4. Wait for the DMC initialization to complete by polling + * DMCx_STAT.INITDONE bit. + */ + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmcdelay(722000u); + + /* Add necessary delay depending on the configuration */ + t_EMR1 = (dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL; + + dmcdelay(600u); + if (t_EMR1 != 0u) + while ((readl(dmc.reg + REG_DMC_EMR1) & BITM_DMC_MR1_WL) != 0) + ; + + t_EMR3 = (dmc.dmc_mr3_value & BITM_DMC_EMR3_MPR) >> + BITP_DMC_EMR3_MPR; + dmcdelay(2000u); + if (t_EMR3 != 0u) + while ((readl(dmc.reg + REG_DMC_EMR3) & BITM_DMC_EMR3_MPR) != 0) + ; + + t_CTL = (dmc.dmc_ctl_value & BITM_DMC_CTL_RL_DQS) >> BITP_DMC_CTL_RL_DQS; + dmcdelay(600u); + if (t_CTL != 0u) + while ((readl(dmc.reg + REG_DMC_CTL) & BITM_DMC_CTL_RL_DQS) != 0) + ; +#endif + + /* check if DMC initialization finished*/ + while ((readl(dmc.reg + REG_DMC_STAT) & BITM_DMC_STAT_INITDONE) == 0) + ; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + /* toggle DCYCLE */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp |= BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp |= BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + + dmcdelay(10u); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp &= (~BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp &= (~BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + + /* toggle RSTDAT */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); + temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); + temp &= (~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); + temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); + temp &= (~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); + + dmcdelay(2500u); + + /* Program phyphase*/ + phyphase = (readl(dmc.reg + REG_DMC_STAT) & + BITM_DMC_STAT_PHYRDPHASE) >> BITP_DMC_STAT_PHYRDPHASE; + data_cyc = (phyphase << BITP_DMC_DLLCTL_DATACYC) & + BITM_DMC_DLLCTL_DATACYC; + rd_cnt = dmc.dmc_dllctl_value; + rd_cnt <<= BITP_DMC_DLLCTL_DLLCALRDCNT; + rd_cnt &= BITM_DMC_DLLCTL_DLLCALRDCNT; + writel(rd_cnt | data_cyc, dmc.reg + REG_DMC_DLLCTL); + writel((dmc.dmc_ctl_value & (~BITM_DMC_CTL_INIT) & + (~BITM_DMC_CTL_RL_DQS)), dmc.reg + REG_DMC_CTL); + +#if DELAYTRIM + /* DQS delay trim*/ + u32 stat_value, WL_code_LDQS, WL_code_UDQS; + + /* For LDQS */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1) | (0x000000D0); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + dmcdelay(2500u); + writel(0x00400000, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL); + stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT0) & + (0xFFFF0000)) >> 16; + WL_code_LDQS = (stat_value) & (0x0000001F); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + + /* If write leveling is enabled */ + if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) { + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp |= (((WL_code_LDQS + LANE0_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + } else { + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); + temp |= (((DQS_DEFAULT_DELAY + LANE0_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); + } + dmcdelay(2500u); + + /* For UDQS */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1) | (0x000000D0); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + dmcdelay(2500u); + writel(0x00800000, dmc.reg + REG_DMC_DDR_ROOT_CTL); + dmcdelay(2500u); + writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL); + stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT1) & + (0xFFFF0000)) >> 16; + WL_code_UDQS = (stat_value) & (0x0000001F); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + + /* If write leveling is enabled */ + if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) { + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp |= (((WL_code_UDQS + LANE1_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + } else { + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); + temp |= (((DQS_DEFAULT_DELAY + LANE1_DQS_DELAY) << + BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & + BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | + BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); + } + dmcdelay(2500u); +#endif + +#else + /* 5. Program the DMCx_CTL.DLLCTL register with 0x948 value + * (DATACYC=9, DLLCALRDCNT=72). + */ + writel(0x00000948, dmc.reg + REG_DMC_DLLCTL); +#endif + + /* 6. Workaround for anomaly#20000037 */ + if (dmc.anomaly_20000037_applicable) { + /* Perform dummy read to any DMC location */ + readl(0x80000000); + + writel(readl(dmc.reg + REG_DMC_PHY_CTL0) | 0x1000, + dmc.reg + REG_DMC_PHY_CTL0); + /* Clear DMCx_PHY_CTL0.RESETDAT bit */ + writel(readl(dmc.reg + REG_DMC_PHY_CTL0) & (~0x1000), + dmc.reg + REG_DMC_PHY_CTL0); + } +} + +static inline void dmc_init(void) +{ + /* PHY Calibration+Initialization */ + if (!dmc.phy_init_required) + goto out; + + switch (dmc.calib_mode) { + case CALIBRATION_LEGACY: + calibration_legacy(); + break; + case CALIBRATION_METHOD1: + calibration_method1(); + break; + case CALIBRATION_METHOD2: + calibration_method2(); + break; + } + +#if DQSTRIM + /* DQS duty trim */ + temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); + temp |= ((DQSCODE) << BITP_DMC_DDR_LANE0_CTL0_BYPENB) & + (BITM_DMC_DDR_LANE1_CTL0_BYPENB | + BITM_DMC_DDR_LANE0_CTL0_BYPSELP | + BITM_DMC_DDR_LANE0_CTL0_BYPCODE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); + + temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); + temp |= ((DQSCODE) << BITP_DMC_DDR_LANE1_CTL0_BYPENB) & + (BITM_DMC_DDR_LANE1_CTL1_BYPCODE | + BITM_DMC_DDR_LANE1_CTL0_BYPSELP | + BITM_DMC_DDR_LANE1_CTL0_BYPCODE); + writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); +#endif + +#if CLKTRIM + /* Clock duty trim */ + temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL); + temp |= (((CLKCODE << BITP_DMC_DDR_CA_CTL_BYPCODE1) & + BITM_DMC_DDR_CA_CTL_BYPCODE1) | + BITM_DMC_DDR_CA_CTL_BYPENB | + ((CLKDIR << BITP_DMC_DDR_CA_CTL_BYPSELP) & + BITM_DMC_DDR_CA_CTL_BYPSELP)); + writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL); +#endif + +out: + /* Controller Initialization */ + dmc_controller_init(); +} + +static inline void __dmc_config(uint32_t dmc_no) +{ + if (dmc_no == 0) { + dmc.reg = REG_DMC0_BASE; + dmc.dmc_data_calib_add_value = DMC0_DATA_CALIB_ADD; + } else if (dmc_no == 1) { + dmc.reg = REG_DMC1_BASE; + dmc.dmc_data_calib_add_value = DMC1_DATA_CALIB_ADD; + } else { + return; + } + + if (IS_ENABLED(CONFIG_ADI_USE_DDR2)) + dmc.ddr_mode = DDR2_MODE; + else + dmc.ddr_mode = DDR3_MODE; + + dmc.phy_init_required = true; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmc.anomaly_20000037_applicable = false; + dmc.dmc_dllctl_value = DMC_DLLCTL_VALUE; + dmc.calib_mode = CALIBRATION_METHOD2; +#else + dmc.anomaly_20000037_applicable = true; + dmc.calib_mode = CALIBRATION_LEGACY; +#endif + + dmc.dmc_ctl_value = DMC_CTL_VALUE; + dmc.dmc_cfg_value = DMC_CFG_VALUE; + dmc.dmc_tr0_value = DMC_TR0_VALUE; + dmc.dmc_tr1_value = DMC_TR1_VALUE; + dmc.dmc_tr2_value = DMC_TR2_VALUE; + dmc.dmc_mr0_value = DMC_MR0_VALUE; + dmc.dmc_mr1_value = DMC_MR1_VALUE; + dmc.dmc_mr2_value = DMC_MR2_VALUE; + +#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + dmc.dmc_mr3_value = DMC_MR3_VALUE; + dmc.dmc_zqctl0_value = DMC_ZQCTL0_VALUE; + dmc.dmc_zqctl1_value = DMC_ZQCTL1_VALUE; + dmc.dmc_zqctl2_value = DMC_ZQCTL2_VALUE; +#endif + + dmc.padctl2_value = DMC_PADCTL2_VALUE; + dmc.dmc_cphyctl_value = DMC_CPHYCTL_VALUE; + + /* Initialize DMC now */ + dmc_init(); +} + +void DMC_Config(void) +{ + if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) + __dmc_config(0); + + if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) + __dmc_config(1); +} diff --git a/arch/arm/mach-sc5xx/init/dmcinit.h b/arch/arm/mach-sc5xx/init/dmcinit.h new file mode 100644 index 00000000000..46ff729282d --- /dev/null +++ b/arch/arm/mach-sc5xx/init/dmcinit.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef DMCINIT_H_ +#define DMCINIT_H_ + +#include <config.h> + +#ifdef MEM_MT41K512M16HA + #include "mem/mt41k512m16ha.h" +#elif defined(MEM_MT41K128M16JT) + #include "mem/mt41k128m16jt.h" +#elif defined(MEM_MT47H128M16RT) + #include "mem/mt47h128m16rt.h" +#elif defined(MEM_IS43TR16512BL) + #include "mem/is43tr16512bl.h" +#else + #error "No DDR part name is defined for this board." +#endif + +void DMC_Config(void); +void adi_dmc_reset_lanes(bool reset); + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h new file mode 100644 index 00000000000..a5838370555 --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef IS43TR16512BL_H +#define IS43TR16512BL_H + +/* DMC0 setup for the EV-21593-SOM and EV-SC594-SOM : + * - uses a single 8GB IS43TR16512BL-125KBL DDR3 chip configured for + * 800 MHz DCLK. + * DMC0 setup for the EV-SC594-SOMS : + * - uses a single 4GB IS43TR16256BL-093NBL DDR3 chip configured for + * 800 MHz DCLK. + */ +#define DMC_DLLCALRDCNT 240 +#define DMC_DATACYC 12 +#define DMC_TRCD 11 +#define DMC_TWTR 6 +#define DMC_TRP 11 +#define DMC_TRAS 28 +#define DMC_TRC 39 +#define DMC_TMRD 4 +#define DMC_TREF 6240 +#define DMC_TRRD 6 +#define DMC_TFAW 32 +#define DMC_TRTP 6 +#define DMC_TWR 12 +#define DMC_TXP 5 +#define DMC_TCKE 4 +#define DMC_CL0 0 +#define DMC_CL123 7 +#define DMC_WRRECOV 6 +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 0 +#define DMC_MR1_RTT0 0 +#define DMC_MR1_AL 0 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 1 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_WL 3 +#define DMC_RDTOWR 5 +#define DMC_CTL_AL_EN 1 +#if defined(MEM_ISSI_4Gb_DDR3_800MHZ) + #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE4G) + #define DMC_TRFC 208ul +#elif defined(MEM_ISSI_8Gb_DDR3_800MHZ) + #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE8G) + #define DMC_TRFC 280ul +#else + #error "Need to select MEM_ISSI_4Gb_DDR3_800MHZ or MEM_ISSI_8Gb_DDR3_800MHZ" +#endif + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h new file mode 100644 index 00000000000..882777521b8 --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef MT41K128M16JT_H +#define MT41K128M16JT_H + +/* Default DDR3 part assumed: MT41K128M16JT-125, 2Gb part */ +/* For DCLK= 450 MHz */ +#define DMC_DLLCALRDCNT 72 +#define DMC_DATACYC 9 +#define DMC_TRCD 6 +#define DMC_TWTR 4 +#define DMC_TRP 6 +#define DMC_TRAS 17 +#define DMC_TRC 23 +#define DMC_TMRD 4 +#define DMC_TREF 3510 +#define DMC_TRFC 72 +#define DMC_TRRD 4 +#define DMC_TFAW 17 +#define DMC_TRTP 4 +#define DMC_TWR 7 +#define DMC_TXP 4 +#define DMC_TCKE 3 +#define DMC_CL0 0 +#define DMC_CL123 3 +#define DMC_WRRECOV (DMC_TWR - 1) +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 1 +#define DMC_MR1_RTT0 1 +#define DMC_MR1_AL 0 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 0 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_WL 1 +#define DMC_RDTOWR 2 +#define DMC_CTL_AL_EN 0 +#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h new file mode 100644 index 00000000000..5735b87871c --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef MT41K512M16HA_H +#define MT41K512M16HA_H + +/* Default DDR3 part assumed: MT41K512M16HA-107, 8Gb part */ +/* For DCLK= 450 MHz */ +#define DMC_DLLCALRDCNT 72 +#define DMC_DATACYC 9 +#define DMC_TRCD 7 +#define DMC_TWTR 4 +#define DMC_TRP 7 +#define DMC_TRAS 10 +#define DMC_TRC 16 +#define DMC_TMRD 4 +#define DMC_TREF 3510 +#define DMC_TRFC 158 +#define DMC_TRRD 6 +#define DMC_TFAW 16 +#define DMC_TRTP 4 +#define DMC_TWR 7 +#define DMC_TXP 3 +#define DMC_TCKE 3 +#define DMC_CL0 0 +#define DMC_CL123 3 +#define DMC_WRRECOV (DMC_TWR - 1) +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 1 +#define DMC_MR1_RTT0 1 +#define DMC_MR1_AL 0 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 0 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_WL 1 +#define DMC_RDTOWR 2 +#define DMC_CTL_AL_EN 0 +#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE8G + +#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h new file mode 100644 index 00000000000..5ada7f2985b --- /dev/null +++ b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#ifndef MT47H128M16RT_H +#define MT47H128M16RT_H + +/* Default DDR2 part: MT47H128M16RT-25E XIT:C, 2 Gb part */ +/* For DCLK= 400 MHz */ +#define DMC_DLLCALRDCNT 72 +#define DMC_DATACYC 9 +#define DMC_TRCD 5 +#define DMC_TWTR 3 +#define DMC_TRP 5 +#define DMC_TRAS 16 +#define DMC_TRC 22 +#define DMC_TMRD 2 +#define DMC_TREF 3120 +#define DMC_TRFC 78 +#define DMC_TRRD 4 +#define DMC_TFAW 18 +#define DMC_TRTP 3 +#define DMC_TWR 6 +#define DMC_TXP 2 +#define DMC_TCKE 3 +#define DMC_CL 5 +#define DMC_WRRECOV (DMC_TWR - 1) +#define DMC_MR1_DLLEN 0 +#define DMC_MR1_DIC0 1 +#define DMC_MR1_RTT0 1 +#define DMC_MR1_AL 4 +#define DMC_MR1_DIC1 0 +#define DMC_MR1_RTT1 0 +#define DMC_MR1_WL 0 +#define DMC_MR1_RTT2 0 +#define DMC_MR1_TDQS 0 +#define DMC_MR1_QOFF 0 +#define DMC_BL 4 +#define DMC_RDTOWR 2 +#define DMC_CTL_AL_EN 0 +#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G + +#endif diff --git a/arch/arm/mach-sc5xx/rcu.c b/arch/arm/mach-sc5xx/rcu.c new file mode 100644 index 00000000000..49357501a93 --- /dev/null +++ b/arch/arm/mach-sc5xx/rcu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Ian Roberts <ian.roberts@timesys.com> + */ + +#include <dm.h> +#include <syscon.h> + +static const struct udevice_id adi_syscon_ids[] = { + { .compatible = "adi,reset-controller" }, + { } +}; + +U_BOOT_DRIVER(syscon_sc5xx_rcu) = { + .name = "sc5xx_rcu", + .id = UCLASS_SYSCON, + .of_match = adi_syscon_ids, +}; diff --git a/arch/arm/mach-sc5xx/sc57x.c b/arch/arm/mach-sc5xx/sc57x.c new file mode 100644 index 00000000000..b0587686d73 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc57x.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/io.h> +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch-adi/sc5xx/spl.h> + +#define REG_SPU0_SECUREC0 0x3108B980 +#define REG_PADS0_PCFG0 0x31004404 +#define REG_SPU0_SECUREP_START 0x3108BA00 +#define REG_SPU0_SECUREP_END 0x3108BD24 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); +} + +void sc5xx_soc_init(void) +{ + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); + sc5xx_enable_pmu(); +} diff --git a/arch/arm/mach-sc5xx/sc58x.c b/arch/arm/mach-sc5xx/sc58x.c new file mode 100644 index 00000000000..0f892774309 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc58x.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/io.h> +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch-adi/sc5xx/spl.h> + +#define REG_SPU0_SECUREC0 0x3108C980 +#define REG_PADS0_PCFG0 0x31004404 +#define REG_SPU0_SECUREP_START 0x3108CA00 +#define REG_SPU0_SECUREP_END 0x3108CCF0 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); +} + +void sc5xx_soc_init(void) +{ + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); + sc5xx_enable_pmu(); +} diff --git a/arch/arm/mach-sc5xx/sc59x.c b/arch/arm/mach-sc5xx/sc59x.c new file mode 100644 index 00000000000..174c6f5c445 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc59x.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/io.h> +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch-adi/sc5xx/spl.h> + +#define REG_SPU0_SECUREC0 0x3108B980 +#define REG_PADS0_PCFG0 0x31004604 +#define REG_SPU0_SECUREP_START 0x3108BA00 +#define REG_SPU0_SECUREP_END 0x3108BD24 + +#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 +#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 +#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e9; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); +} + +void sc59x_remap_ospi(void) +{ + clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, + BITM_SCB5_SPI2_OSPI_REMAP_REMAP, + ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); +} + +void sc5xx_soc_init(void) +{ + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); + sc5xx_enable_pmu(); +} diff --git a/arch/arm/mach-sc5xx/sc59x_64.c b/arch/arm/mach-sc5xx/sc59x_64.c new file mode 100644 index 00000000000..82537bf1965 --- /dev/null +++ b/arch/arm/mach-sc5xx/sc59x_64.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/io.h> +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch-adi/sc5xx/spl.h> + +#define REG_TSGENWR0_CNTCR 0x310AE000 +#define REG_PADS0_PCFG0 0x31004604 +#define REG_RCU0_BCODE 0x3108C028 + +#define REG_SPU0_SECUREP_START 0x3108BA00 +#define REG_SPU0_WP_START 0x3108B400 +#define REG_SPU0_SECUREC0 0x3108B980 + +#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 +#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 +#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 + +adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e4; + +void sc5xx_enable_rgmii(void) +{ + writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); + + // Set dw for little endian operation as well + writel(readl(REG_PADS0_PCFG0) & ~(1 << 19), REG_PADS0_PCFG0); + writel(readl(REG_PADS0_PCFG0) & ~(1 << 20), REG_PADS0_PCFG0); +} + +void sc59x_remap_ospi(void) +{ + clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, + BITM_SCB5_SPI2_OSPI_REMAP_REMAP, + ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); +} + +/** + * SPU/SMPU configuration is the default for permissive access from non-secure + * EL1. If TFA and OPTEE are configured, they run *after* this code, as the + * current boot flow is SPL -> TFA -> OPTEE -> Proper -> Linux, and will + * be expected to configure peripheral security correctly. If they are not + * configured, then this permissive setting will allow Linux (which always + * runs in NS EL1) to control all access to these peripherals. Without it, + * the peripherals would simply be unavailable in a non-security build, + * which is not OK. + */ +void sc5xx_soc_init(void) +{ + phys_addr_t smpus[] = { + 0x31007800, //SMPU0 + 0x31083800, //SMPU2 + 0x31084800, //SMPU3 + 0x31085800, //SMPU4 + 0x31086800, //SMPU5 + 0x31087800, //SMPU6 + 0x310A0800, //SMPU9 + 0x310A1800, //SMPU11 + 0x31012800, //SMPU12 + }; + size_t i; + + // Enable coresight timer + writel(1, REG_TSGENWR0_CNTCR); + + //Do not rerun preboot routine -- + // Without this, hardware resets triggered by RCU0_CTL:SYSRST + // lead to a deadlock somewhere in the boot ROM + writel(0x200, REG_RCU0_BCODE); + + /* Alter outstanding transactions property of A55*/ + writel(0x1, 0x30643108); /* SCB6 A55 M0 Ib.fn Mod */ + isb(); + + /* configure DDR prefetch behavior, per ADI */ + writel(0x1, 0x31076000); + + /* configure smart mode, per ADI */ + writel(0x1307, 0x31076004); + + // Disable SPU and SPU WP registers + sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_START + 4*213); + sc5xx_disable_spu0(REG_SPU0_WP_START, REG_SPU0_WP_START + 4*213); + + /* configure smpus permissively */ + for (i = 0; i < ARRAY_SIZE(smpus); ++i) + writel(0x500, smpus[i]); + + sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); +} diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c new file mode 100644 index 00000000000..8f13127a660 --- /dev/null +++ b/arch/arm/mach-sc5xx/soc.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch-adi/sc5xx/soc.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <cpu_func.h> + +#ifdef CONFIG_SC58X + #define RCU0_CTL 0x3108B000 + #define RCU0_STAT 0x3108B004 + #define RCU0_CRCTL 0x3108B008 + #define RCU0_CRSTAT 0x3108B00C + #define RCU0_SIDIS 0x3108B010 + #define RCU0_MSG_SET 0x3108B064 +#elif defined(CONFIG_SC57X) || defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) + #define RCU0_CTL 0x3108C000 + #define RCU0_STAT 0x3108C004 + #define RCU0_CRCTL 0x3108C008 + #define RCU0_CRSTAT 0x3108C00C + #define RCU0_SIDIS 0x3108C01C + #define RCU0_MSG_SET 0x3108C070 +#else + #error "No SC5xx SoC CONFIG_ enabled" +#endif + +#define BITP_RCU_STAT_BMODE 8 +#define BITM_RCU_STAT_BMODE 0x00000F00 + +#define REG_ARMPMU0_PMCR 0x31121E04 +#define REG_ARMPMU0_PMUSERENR 0x31121E08 +#define REG_ARMPMU0_PMLAR 0x31121FB0 + +DECLARE_GLOBAL_DATA_PTR; + +void reset_cpu(void) +{ + u32 val = readl(RCU0_CTL); + writel(val | 1, RCU0_CTL); +} + +void enable_caches(void) +{ + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) + dcache_enable(); +} + +void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base) +{ + writel(0, securec0_base); + writel(0, securec0_base + 0x4); + writel(0, securec0_base + 0x8); +} + +void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end) +{ + for (uintptr_t i = spu0_start; i <= spu0_end; i += 4) + writel(0, i); +} + +/** + * PMU is only available on armv7 platforms and all share the same location + */ +void sc5xx_enable_pmu(void) +{ + if (!IS_ENABLED(CONFIG_SC59X_64)) { + writel(readl(REG_ARMPMU0_PMUSERENR) | 0x01, REG_ARMPMU0_PMUSERENR); + writel(0xc5acce55, REG_ARMPMU0_PMLAR); + writel(readl(REG_ARMPMU0_PMCR) | (1 << 1), REG_ARMPMU0_PMCR); + } +} + +const char *sc5xx_get_boot_mode(u32 *bmode) +{ + static const char * const bmodes[] = { + "JTAG/BOOTROM", + "QSPI Master", + "QSPI Slave", + "UART", + "LP0 Slave", + "OSPI", +#ifdef CONFIG_SC59X_64 + "eMMC" +#endif + }; + u32 local_mode; + + local_mode = (readl(RCU0_STAT) & BITM_RCU_STAT_BMODE) >> BITP_RCU_STAT_BMODE; + +#if CONFIG_ADI_SPL_FORCE_BMODE != 0 + /* + * In case we want to force boot sequences such as: + * QSPI -> OSPI + * QSPI -> eMMC + * If this is not set, then we will always try to use the BMODE setting + * for both stages... i.e. + * QSPI -> QSPI + */ + + // (Don't allow skipping JTAG/UART BMODE settings) + if (local_mode != 0 && local_mode != 3) + local_mode = CONFIG_ADI_SPL_FORCE_BMODE; +#endif + + *bmode = local_mode; + + if (local_mode >= 0 && local_mode <= ARRAY_SIZE(bmodes)) + return bmodes[local_mode]; + return "unknown"; +} + +void print_cpu_id(void) +{ + if (!IS_ENABLED(CONFIG_ARM64)) { + u32 cpuid = 0; + + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); + + printf("Detected Revision: %d.%d\n", cpuid & 0xf00000 >> 20, cpuid & 0xf); + } +} + +int print_cpuinfo(void) +{ + u32 bmode; + + printf("CPU: ADSP %s (%s boot)\n", CONFIG_LDR_CPU, sc5xx_get_boot_mode(&bmode)); + print_cpu_id(); + + return 0; +} + +void fixup_dp83867_phy(struct phy_device *phydev) +{ + int phy_data = 0; + + phy_data = phy_read(phydev, MDIO_DEVAD_NONE, 0x32); + phy_write(phydev, MDIO_DEVAD_NONE, 0x32, (1 << 7) | phy_data); + int cfg3 = 0; + #define MII_DP83867_CFG3 (0x1e) + /* + * Pin INT/PWDN on DP83867 should be configured as an Interrupt Output + * instead of a Power-Down Input on ADI SC5XX boards in order to + * prevent the signal interference from other peripherals during they + * are running at the same time. + */ + cfg3 = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3); + cfg3 |= (1 << 7); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3, cfg3); + + // Mystery second port fixup on ezkits with two PHYs + if (CONFIG_DW_PORTS & 2) + phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 3); + + if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) { + phydev->advertising &= PHY_BASIC_FEATURES; + phydev->speed = SPEED_100; + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) + phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x3100); +} + +int dram_init(void) +{ + gd->ram_size = CFG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/arm/mach-sc5xx/spl.c b/arch/arm/mach-sc5xx/spl.c new file mode 100644 index 00000000000..68e0310f5af --- /dev/null +++ b/arch/arm/mach-sc5xx/spl.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2022 - Analog Devices, Inc. + * + * Written and/or maintained by Timesys Corporation + * + * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> + * Contact: Greg Malysa <greg.malysa@timesys.com> + */ + +#include <spl.h> +#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch-adi/sc5xx/spl.h> +#include "init/clkinit.h" +#include "init/dmcinit.h" + +static bool adi_start_uboot_proper; + +static int adi_sf_default_bus = CONFIG_SF_DEFAULT_BUS; +static int adi_sf_default_cs = CONFIG_SF_DEFAULT_CS; +static int adi_sf_default_speed = CONFIG_SF_DEFAULT_SPEED; + +u32 bmode; + +int spl_start_uboot(void) +{ + return adi_start_uboot_proper; +} + +unsigned int spl_spi_get_default_speed(void) +{ + return adi_sf_default_speed; +} + +unsigned int spl_spi_get_default_bus(void) +{ + return adi_sf_default_bus; +} + +unsigned int spl_spi_get_default_cs(void) +{ + return adi_sf_default_cs; +} + +void board_boot_order(u32 *spl_boot_list) +{ + const char *bmodestring = sc5xx_get_boot_mode(&bmode); + + printf("ADI Boot Mode: 0x%x (%s)\n", bmode, bmodestring); + + /* + * By default everything goes back to the bootrom, where we'll read table + * parameters and ask for another image to be loaded + */ + spl_boot_list[0] = BOOT_DEVICE_BOOTROM; + + if (bmode == 0) { + printf("SPL execution has completed. Please load U-Boot Proper via JTAG"); + while (1) + ; + } +} + +int32_t __weak adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *config, int32_t cause) +{ + return 0; +} + +int board_return_to_bootrom(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ +#if CONFIG_ADI_SPL_FORCE_BMODE != 0 + // see above + if (bmode != 0 && bmode != 3) + bmode = CONFIG_ADI_SPL_FORCE_BMODE; +#endif + + if (bmode >= (ARRAY_SIZE(adi_rom_boot_args))) + bmode = 0; + + adi_rom_boot((void *)adi_rom_boot_args[bmode].addr, + adi_rom_boot_args[bmode].flags, + 0, &adi_rom_boot_hook, + adi_rom_boot_args[bmode].cmd); + return 0; +}; + +void board_init_f(ulong dummy) +{ + int ret; + + clks_init(); + DMC_Config(); + sc5xx_soc_init(); + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed\n"); + + preloader_console_init(); +} + diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 616e1afe5de..feaf5ce4596 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -5,7 +5,7 @@ * Copyright (C) 2015 Marek Vasut <marex@denx.de> */ -#include <common.h> +#include <config.h> #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 9e645a42531..160f6e73ca9 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> */ -#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 28f593b60e6..9987d5bcee6 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -5,7 +5,6 @@ */ #include <clk.h> -#include <common.h> #include <dm.h> #include <log.h> #include <malloc.h> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c index b92f0b3af80..7ec28d91ef3 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex5.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -16,7 +16,6 @@ #include <vsprintf.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/u-boot.h> #include <linux/kernel.h> #include <linux/string.h> #include <linux/types.h> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 8ab18f6b725..58b9321131a 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -3,7 +3,6 @@ * Copyright (C) 2016-2017 Intel Corporation */ -#include <common.h> #include <fdtdec.h> #include <malloc.h> #include <asm/io.h> diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 8fa2760798b..154ad2154ae 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> */ -#include <common.h> #include <time.h> #include <asm/io.h> #include <dm.h> diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c index 0ed480de670..c4c071330fc 100644 --- a/arch/arm/mach-socfpga/clock_manager_n5x.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 45300336d52..1e148947a33 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -4,7 +4,7 @@ * */ -#include <common.h> +#include <linux/errno.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 69229dc651e..4dec47b8e96 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -4,8 +4,8 @@ * */ +#include <mach/base_addr_soc64.h> #include <asm/io.h> -#include <common.h> #include <asm/arch/firewall.h> #include <asm/arch/system_manager.h> diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index 18d692c6314..c946d4c38d9 100644 --- a/arch/arm/mach-socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c @@ -7,7 +7,7 @@ * platform code, the real meat is located in drivers/fpga/socfpga.c . */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/arch/fpga_manager.h> diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 561d3408cd8..7c86350d5ea 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -4,7 +4,7 @@ */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> #include <asm/arch/freeze_controller.h> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 6c9d32b9dd8..49f3fb2e705 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -6,6 +6,8 @@ #ifndef _CLOCK_MANAGER_H_ #define _CLOCK_MANAGER_H_ +#include <linux/types.h> + phys_addr_t socfpga_get_clkmgr_addr(void); #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h index d5a11122c72..01335dc9310 100644 --- a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h @@ -7,6 +7,8 @@ #ifndef _SECURE_REG_HELPER_H_ #define _SECURE_REG_HELPER_H_ +#include <linux/types.h> + #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 101af238552..4c86f1e9917 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/system_manager.h> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 80ad0870341..495ba2a0d41 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -3,7 +3,7 @@ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> */ -#include <common.h> +#include <config.h> #include <command.h> #include <cpu_func.h> #include <hang.h> diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 93c9e8b0fb4..34c21317894 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -4,7 +4,7 @@ */ #include <altera.h> -#include <common.h> +#include <config.h> #include <errno.h> #include <fdtdec.h> #include <init.h> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index e7500c16f72..b898b6f8f22 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -3,7 +3,7 @@ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 2acdfad07b3..ad1ef0db186 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -5,7 +5,6 @@ */ #include <altera.h> -#include <common.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 91c6d7c55f1..b8e40d9a788 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c b/arch/arm/mach-socfpga/pinmux_arria10.c index f378fce7f02..c8074f47e76 100644 --- a/arch/arm/mach-socfpga/pinmux_arria10.c +++ b/arch/arm/mach-socfpga/pinmux_arria10.c @@ -4,9 +4,9 @@ */ #include <log.h> +#include <linux/errno.h> #include <asm/arch/pinmux.h> #include <asm/io.h> -#include <common.h> #include <fdtdec.h> static int do_pinctr_pin(const void *blob, int child, const char *node_name) diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 27c03080113..da335f4292c 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -9,7 +9,6 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <common.h> #include <errno.h> #include <fdtdec.h> #include <wait_bit.h> diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index a65860ef021..9395122dae1 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -4,7 +4,7 @@ */ -#include <common.h> +#include <mach/base_addr_ac5.h> #include <asm/io.h> #include <asm/arch/fpga_manager.h> #include <asm/arch/reset_manager.h> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f47fec10a0c..dd0383c7c76 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <hang.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c index 36d6880141e..f8811525da4 100644 --- a/arch/arm/mach-socfpga/scan_manager.c +++ b/arch/arm/mach-socfpga/scan_manager.c @@ -3,7 +3,7 @@ * Copyright (C) 2013 Altera Corporation <www.altera.com> */ -#include <common.h> +#include <config.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/freeze_controller.h> diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c index 0d4f45f33da..802a966ce87 100644 --- a/arch/arm/mach-socfpga/secure_reg_helper.c +++ b/arch/arm/mach-socfpga/secure_reg_helper.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <hang.h> #include <asm/io.h> #include <asm/system.h> diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index e2db5885064..4347bf6e792 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -8,7 +8,6 @@ #include <asm/arch/secure_vab.h> #include <asm/arch/smc_api.h> #include <asm/unaligned.h> -#include <common.h> #include <exports.h> #include <linux/errno.h> #include <linux/intel-smc.h> diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index 8ffc7a472b5..ebaa0b8fa17 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -4,10 +4,11 @@ * */ -#include <common.h> #include <asm/ptrace.h> #include <asm/system.h> +#include <linux/errno.h> #include <linux/intel-smc.h> +#include <linux/string.h> int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len) { diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 3981d2d4f14..c20376f7f8e 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -3,14 +3,13 @@ * Copyright (C) 2012-2021 Altera Corporation <www.altera.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <hang.h> #include <init.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/pl310.h> -#include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> #include <asm/arch/reset_manager.h> diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index ee5a9dc1e2f..52617a39cca 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -8,9 +8,7 @@ #include <log.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/u-boot.h> #include <asm/utils.h> -#include <common.h> #include <hang.h> #include <image.h> #include <spl.h> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 287fbd1713c..df79cfe0f7f 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -3,13 +3,11 @@ * Copyright (C) 2012 Altera Corporation <www.altera.com> */ -#include <common.h> #include <hang.h> #include <init.h> #include <log.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> #include <asm/arch/reset_manager.h> diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index d056871d292..5ff137e5c6f 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> @@ -13,7 +12,6 @@ #include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/u-boot.h> #include <asm/utils.h> #include <dm/uclass.h> #include <hang.h> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index c20e87cdbef..53852cb7443 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -9,9 +9,7 @@ #include <log.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/u-boot.h> #include <asm/utils.h> -#include <common.h> #include <debug_uart.h> #include <image.h> #include <spl.h> diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index ba6efc1d864..4fe67ea0811 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <spl.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c index 09caebb3c88..c377d1c32c7 100644 --- a/arch/arm/mach-socfpga/system_manager_gen5.c +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/system_manager.h> #include <asm/arch/fpga_manager.h> diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 958bb5107b5..4b42158be9d 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,7 +8,6 @@ #include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> -#include <common.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index d9e8c84bfcf..99de5744c48 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Altera Corporation <www.altera.com> */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/io.h> #include <asm/arch/timer.h> diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 84b13ce9d3a..80933586319 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <init.h> #include <div64.h> #include <asm/io.h> diff --git a/arch/arm/mach-socfpga/vab.c b/arch/arm/mach-socfpga/vab.c index e146f2c5290..e74c71cfbb4 100644 --- a/arch/arm/mach-socfpga/vab.c +++ b/arch/arm/mach-socfpga/vab.c @@ -4,9 +4,9 @@ * */ +#include <vsprintf.h> #include <asm/arch/secure_vab.h> #include <command.h> -#include <common.h> #include <linux/ctype.h> static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 6aa9bb26b4e..92051d19b73 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -6,7 +6,6 @@ #include <asm/arch/handoff_soc64.h> #include <asm/io.h> -#include <common.h> #include <errno.h> #include "log.h" diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c index ce86f04cad1..43ce329dd10 100644 --- a/arch/arm/mach-socfpga/wrap_iocsr_config.c +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Marek Vasut <marex@denx.de> */ -#include <common.h> +#include <config.h> #include <errno.h> #include <asm/arch/clock_manager.h> diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c index 33ca14c9dc7..e494d2eb3f9 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -3,8 +3,9 @@ * Copyright (C) 2015 Marek Vasut <marex@denx.de> */ -#include <common.h> #include <errno.h> +#include <linux/kernel.h> +#include <linux/types.h> /* Board-specific header. */ #include <qts/pinmux_config.h> diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 0c40ae98761..e0d0f8f81b7 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Marek Vasut <marex@denx.de> */ -#include <common.h> +#include <config.h> #include <asm/arch/clock_manager.h> #include <qts/pll_config.h> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c index 6a0d6b5ead7..f13581033e6 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/arch/clock_manager.h> #include <asm/io.h> #include <asm/arch/handoff_soc64.h> diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index cd3a0f66335..8f3fbaf80c8 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -3,8 +3,10 @@ * Copyright (C) 2015 Marek Vasut <marex@denx.de> */ -#include <common.h> +#include <config.h> #include <errno.h> +#include <linux/types.h> +#include <linux/kernel.h> #include <asm/arch/sdram.h> /* Board-specific header. */ diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 0bd8d7b22c4..737e6809f8d 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -4,7 +4,6 @@ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/armv7_mpu.h> diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index b9af03d57e3..d5934a92771 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -155,4 +155,21 @@ source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" + +config STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR" + depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) + default y if STM32MP15X + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR. + +config SPL_STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR in SPL" + depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X) + default y if STM32MP15X + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR in SPL. + endif diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x index 71c14eb4955..d99aa9fd694 100644 --- a/arch/arm/mach-stm32mp/Kconfig.15x +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -77,22 +77,6 @@ config TARGET_ICORE_STM32MP1 endchoice -config STM32MP15_PWR - bool "Enable driver for STM32MP15x PWR" - depends on DM_REGULATOR && DM_PMIC - default y - help - This config enables implementation of driver-model pmic and - regulator uclass features for access to STM32MP15x PWR. - -config SPL_STM32MP15_PWR - bool "Enable driver for STM32MP15x PWR in SPL" - depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC - default y - help - This config enables implementation of driver-model pmic and - regulator uclass features for access to STM32MP15x PWR in SPL. - config TEXT_BASE default 0xC0100000 diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c index 158bf40cb97..ebddf6a7dbc 100644 --- a/arch/arm/mach-stm32mp/boot_params.c +++ b/arch/arm/mach-stm32mp/boot_params.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> +#include <config.h> #include <log.h> #include <linux/libfdt.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 5b869017ec1..9ba7a6c9a89 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_MISC -#include <common.h> #include <clk.h> #include <dm.h> #include <log.h> diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index c7fe232f86e..040a70f581c 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -3,7 +3,6 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ -#include <common.h> #include <command.h> #include <console.h> #include <log.h> @@ -420,12 +419,12 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co return CMD_RET_SUCCESS; } -static char stm32key_help_text[] = +U_BOOT_LONGHELP(stm32key, "list : list the supported key with description\n" "stm32key select [<key>] : Select the key identified by <key> or display the key used for read/fuse command\n" "stm32key read [<addr> | -a ] : Read the curent key at <addr> or current / all (-a) key in OTP\n" "stm32key fuse [-y] <addr> : Fuse the current key at addr in OTP\n" - "stm32key close [-y] : Close the device\n"; + "stm32key close [-y] : Close the device\n"); U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text, U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list), diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index adee6e05b63..967fa4e06c0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -3,7 +3,6 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include <common.h> #include <bootm.h> #include <command.h> #include <dfu.h> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 35bed319942..07c5e0456f8 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -3,12 +3,12 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include <common.h> #include <console.h> #include <dm.h> #include <dfu.h> #include <malloc.h> #include <serial.h> +#include <time.h> #include <watchdog.h> #include <asm/arch/sys_proto.h> #include <dm/lists.h> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index d18455bf36f..4b1ed50e9fe 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -3,7 +3,6 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -#include <common.h> #include <dfu.h> #include <g_dnl.h> #include <usb.h> diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index fb1208fc5d5..6024959b97e 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -5,8 +5,8 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <dm.h> +#include <efi_loader.h> #include <image.h> #include <init.h> #include <lmb.h> @@ -75,3 +75,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return reg + size; } + +void efi_add_known_memory(void) +{ + if (IS_ENABLED(CONFIG_EFI_LOADER)) + /* + * Memory over ram_top is reserved to OPTEE. + * Declare to EFI only memory area below ram_top + */ + efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base, + EFI_CONVENTIONAL_MEMORY); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 524778f00c6..478c3efae73 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <clk.h> #include <cpu_func.h> #include <debug_uart.h> diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c index d0b6c3cc5a5..e1e4dc04e01 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c @@ -5,11 +5,11 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <fdtdec.h> #include <fdt_support.h> #include <log.h> #include <tee.h> +#include <mach/stm32.h> #include <asm/arch/sys_proto.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <linux/io.h> diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index e99103910d9..bfbf420fdb5 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <asm/armv7.h> #include <asm/cache.h> #include <asm/gic.h> @@ -13,6 +12,7 @@ #include <asm/secure.h> #include <hang.h> #include <linux/bitops.h> +#include <linux/errno.h> /* PWR */ #define PWR_CR3 0x0c diff --git a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c index 846637ab162..79c44188cc5 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c @@ -5,10 +5,10 @@ #define LOG_CATEGORY UCLASS_REGULATOR -#include <common.h> #include <dm.h> #include <errno.h> #include <syscon.h> +#include <time.h> #include <asm/io.h> #include <dm/device_compat.h> #include <dm/device-internal.h> diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index beda69f3359..6eae5c2f557 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <dm.h> #include <hang.h> diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 845d973ad1b..4a811065fc3 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> +#include <config.h> #include <log.h> #include <syscon.h> #include <asm/io.h> diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index d75ec99d6a1..f096fe538d8 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <env.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index a2e351d74a7..8bcbd979340 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include <common.h> #include <clk.h> #include <dm.h> #include <syscon.h> diff --git a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c index 9077f86a8b4..3666dddca15 100644 --- a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c +++ b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c @@ -1,4 +1,3 @@ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c index 0471e8a49e5..ceaafd6ec6f 100644 --- a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -1,4 +1,3 @@ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c index 232b4fe2df7..3faf8d5bd97 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c index b6d6a687468..ce2ffa7a020 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c index c11cb8678f6..e6446b9180d 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c @@ -9,7 +9,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index 2136ca3a4cb..afe8e25c7f5 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -19,7 +19,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c index 10008601134..c243b574406 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c @@ -6,7 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c index bd57e2f6aac..bc47a463853 100644 --- a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -1,4 +1,3 @@ -#include <common.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 532730fe727..1ea620e4ab5 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -6,7 +6,7 @@ /* Tegra AP (Application Processor) code */ -#include <common.h> +#include <config.h> #include <log.h> #include <linux/bug.h> #include <asm/io.h> diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index ea4eac392d9..4fbe47a91e1 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -7,7 +7,6 @@ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <asm/system.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 327d70bd4cc..c382e042860 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -4,7 +4,7 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <dm.h> #include <init.h> diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index adea12c9b7f..479137e457c 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -4,7 +4,7 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> +#include <config.h> #include <dm.h> #include <env.h> #include <errno.h> diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index d7063490e22..462364abf03 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -5,7 +5,6 @@ /* Tegra cache routines */ -#include <common.h> #include <asm/io.h> #include <asm/arch-tegra/ap.h> #if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL) diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index 8f5bb2f261a..c12543d71ac 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -3,7 +3,6 @@ * Copyright (c) 2016-2018, NVIDIA CORPORATION. */ -#include <common.h> #include <env.h> #include <fdt_support.h> #include <fdtdec.h> diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 575da2bdb5a..157e6c4911a 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -5,7 +5,6 @@ /* Tegra SoC common clock control functions */ -#include <common.h> #include <div64.h> #include <dm.h> #include <errno.h> diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index 92ff6cb1bf8..8fa1207e97a 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -24,7 +24,6 @@ * (C) Copyright 2004 Texas Insturments */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <irq_func.h> diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 59ca8aeabac..5f2a5917102 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-tegra/crypto.c b/arch/arm/mach-tegra/crypto.c index 893da35e0b9..49e6a45243a 100644 --- a/arch/arm/mach-tegra/crypto.c +++ b/arch/arm/mach-tegra/crypto.c @@ -4,7 +4,6 @@ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <log.h> #include <linux/errno.h> #include <asm/arch-tegra/crypto.h> diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index c11494722bc..f4ae602d523 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2016, NVIDIA CORPORATION. */ -#include <common.h> #include <fdtdec.h> #include <stdlib.h> #include <asm/arch-tegra/cboot.h> diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 2eea14b5a74..83fad35d4dc 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -3,7 +3,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include <common.h> #include <asm/global_data.h> #include "emc.h" #include <asm/io.h> diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 83bd5055384..e9b5259ac70 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -7,7 +7,6 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> #include <linux/delay.h> #include <asm/io.h> diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 36538e7f96a..23381759b79 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -5,7 +5,6 @@ /* Tegra vpr routines */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/tegra.h> diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c index 66c1276f4b8..0445d5d48e5 100644 --- a/arch/arm/mach-tegra/ivc.c +++ b/arch/arm/mach-tegra/ivc.c @@ -3,11 +3,11 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ -#include <common.h> #include <cpu_func.h> #include <asm/io.h> #include <asm/arch-tegra/ivc.h> #include <linux/bug.h> +#include <linux/errno.h> #include <linux/printk.h> #define TEGRA_IVC_ALIGN 64 diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index c4f5106750b..3f968d4aeae 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -3,7 +3,6 @@ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <cpu_func.h> #include <log.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 631bc04e950..2a2f8467216 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -3,8 +3,8 @@ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <errno.h> +#include <time.h> #include <linux/delay.h> #include <asm/io.h> diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index ed897efc5f0..5df0eb28c96 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -5,7 +5,6 @@ * * Allen Martin <amartin@nvidia.com> */ -#include <common.h> #include <debug_uart.h> #include <log.h> #include <spl.h> diff --git a/arch/arm/mach-tegra/sys_info.c b/arch/arm/mach-tegra/sys_info.c index 5ad586ac17f..11b40480246 100644 --- a/arch/arm/mach-tegra/sys_info.c +++ b/arch/arm/mach-tegra/sys_info.c @@ -4,7 +4,6 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <init.h> #include <linux/ctype.h> #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 2ee755bc649..d5cc8ac44dd 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -6,7 +6,6 @@ /* Tegra114 Clock control functions */ -#include <common.h> #include <init.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 7d8f080c310..3fe2d2d7324 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -4,7 +4,6 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index ed8b6d96381..4ac0c10c597 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -6,7 +6,7 @@ /* Tegra124 Clock control functions */ -#include <common.h> +#include <config.h> #include <init.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index b1bfe8fb5e1..07892aedd3c 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -4,7 +4,6 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/ahb.h> diff --git a/arch/arm/mach-tegra/tegra124/pmc.c b/arch/arm/mach-tegra/tegra124/pmc.c index 3921ffb52af..2294911501e 100644 --- a/arch/arm/mach-tegra/tegra124/pmc.c +++ b/arch/arm/mach-tegra/tegra124/pmc.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 Google, Inc */ -#include <common.h> #include <dm.h> #include <syscon.h> diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index ab102a62261..a50b681935a 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -4,7 +4,6 @@ * Author: Jan Kiszka <jan.kiszka@siemens.com> */ -#include <common.h> #include <asm/io.h> #include <asm/psci.h> #include <asm/arch/flow.h> diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 69736aa3925..1153444267d 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -5,9 +5,9 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt -#include <common.h> #include <errno.h> #include <log.h> +#include <time.h> #include <dm/of_access.h> #include <dm/ofnode.h> #include <linux/delay.h> diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index b2c44f3d237..e155b98cf65 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -4,7 +4,6 @@ * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> #include <command.h> #include <log.h> #include <asm/arch-tegra/crypto.h> diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 109b73bfbe7..6af20e9c782 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -7,7 +7,6 @@ /* Tegra20 Clock control functions */ -#include <common.h> #include <errno.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index e5b60598f7f..1ba3930b5e6 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/pmc.h> diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 4ba3fb23fd6..207e50aac90 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -4,7 +4,6 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/tegra.h> diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index fb5e699c940..e2ee8f124ac 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -3,7 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include <common.h> +#include <config.h> #include <fdtdec.h> #include <log.h> #include <asm/io.h> diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index 05d0668cdba..f2fe5d0fa9d 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -4,7 +4,6 @@ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <i2c.h> #include <log.h> #include <tps6586x.h> diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5e3a9ebaceb..18034c83a1c 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -4,7 +4,6 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/errno.h> diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 94ce762e01f..65bbe182535 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -4,7 +4,7 @@ * NVIDIA Corporation <www.nvidia.com> */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/flow.h> diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 74817e0440b..57ff0b2a19a 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -6,10 +6,10 @@ /* Tegra210 Clock control functions */ -#include <common.h> #include <errno.h> #include <init.h> #include <log.h> +#include <time.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 30d0395bb0e..e409c2842e2 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -5,9 +5,9 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt -#include <common.h> #include <errno.h> #include <log.h> +#include <time.h> #include <asm/global_data.h> #include <dm/of_access.h> #include <dm/ofnode.h> diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index cff1a3e98d2..250009ea8d8 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -4,9 +4,9 @@ * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <common.h> #include <command.h> #include <log.h> +#include <vsprintf.h> #include <asm/arch-tegra/crypto.h> #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 0af8cde8c64..7d61127920b 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -6,7 +6,6 @@ /* Tegra30 Clock control functions */ -#include <common.h> #include <errno.h> #include <init.h> #include <log.h> diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 60bbf13ea52..51a9deab1fd 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index 28fdebe50a3..a3515d903a6 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -5,7 +5,6 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt -#include <common.h> #include <errno.h> #include <log.h> #include <linux/printk.h> diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index f2d90302f6d..1345b80747e 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -3,9 +3,9 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ -#include <common.h> #include <errno.h> +#include <linux/compiler.h> #include <asm/arch-tegra/xusb-padctl.h> struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type) diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index 05a91346a89..7541b567d0f 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -3,7 +3,7 @@ * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <asm/armv7.h> #include <asm/cache.h> diff --git a/arch/arm/mach-u8500/cpuinfo.c b/arch/arm/mach-u8500/cpuinfo.c index ab05b8a51b2..6d4c6196c3d 100644 --- a/arch/arm/mach-u8500/cpuinfo.c +++ b/arch/arm/mach-u8500/cpuinfo.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net> */ -#include <common.h> #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index e6f1286e71f..0e1164a2680 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -12,7 +12,6 @@ #include <linux/printk.h> #include <linux/sizes.h> #include <asm/global_data.h> -#include <asm/u-boot.h> #include "init.h" #include "sg-regs.h" diff --git a/arch/arm/mach-versal-net/clk.c b/arch/arm/mach-versal-net/clk.c index d097de7afa6..61b8fe71b1a 100644 --- a/arch/arm/mach-versal-net/clk.c +++ b/arch/arm/mach-versal-net/clk.c @@ -6,7 +6,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index a82741e70fc..d088e440f63 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -6,7 +6,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <init.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c index 5e3f44c7782..19943dfdd4c 100644 --- a/arch/arm/mach-versal/clk.c +++ b/arch/arm/mach-versal/clk.c @@ -4,7 +4,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index e4dc305d928..363ce3007fd 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -4,7 +4,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <init.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 2487b482ddb..921ca49c359 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -4,7 +4,8 @@ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ -#include <common.h> +#include <config.h> +#include <linux/string.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig new file mode 100644 index 00000000000..3f18e3351aa --- /dev/null +++ b/arch/arm/mach-versal2/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_VERSAL2 + +config SYS_BOARD + string "Board name" + default "versal2" + +config SYS_VENDOR + string "Vendor name" + default "amd" + +config SYS_SOC + default "versal2" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "amd_versal2" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. + +config COUNTER_FREQUENCY + int "Timer clock frequency" + default 0 + help + Setup time clock frequency for certain platform + +config IOU_SWITCH_DIVISOR0 + hex "IOU switch divisor0" + default 0x20 + help + Setup time clock divisor for input clock. + +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + +config GICV3 + def_bool y + +config SYS_MALLOC_LEN + default 0x2000000 + +config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +source "board/xilinx/Kconfig" +source "board/amd/versal2/Kconfig" + +endif diff --git a/arch/arm/mach-versal2/Makefile b/arch/arm/mach-versal2/Makefile new file mode 100644 index 00000000000..96497b1dfd0 --- /dev/null +++ b/arch/arm/mach-versal2/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. +# +# Michal Simek <michal.simek@amd.com> +# + +obj-y += clk.o +obj-y += cpu.o diff --git a/arch/arm/mach-versal2/clk.c b/arch/arm/mach-versal2/clk.c new file mode 100644 index 00000000000..e73ae9af076 --- /dev/null +++ b/arch/arm/mach-versal2/clk.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <init.h> +#include <time.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info - Initialize clock framework + * + * Return: 0 always. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c new file mode 100644 index 00000000000..2dfcadb369e --- /dev/null +++ b/arch/arm/mach-versal2/cpu.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/cache.h> +#include <dm/platdata.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSAL2_MEM_MAP_USED 5 + +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS + +/* +1 is end of list which needs to be empty */ +#define VERSAL2_MEM_MAP_MAX (VERSAL2_MEM_MAP_USED + DRAM_BANKS + 1) + +static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x70000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x0fe00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x600000000UL, + .phys = 0x600000000UL, + .size = 0x800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe00000000UL, + .phys = 0xe00000000UL, + .size = 0xf200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + } +}; + +void mem_map_fill(void) +{ + int banks = VERSAL2_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Zero size means no more DDR that's this is end */ + if (!gd->bd->bi_dram[i].size) + break; + + versal2_mem_map[banks].virt = gd->bd->bi_dram[i].start; + versal2_mem_map[banks].phys = gd->bd->bi_dram[i].start; + versal2_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; + } +} + +struct mm_region *mem_map = versal2_mem_map; + +u64 get_page_table_size(void) +{ + return 0x14000; +} + +U_BOOT_DRVINFO(soc_amd_versal2) = { + .name = "soc_amd_versal2", +}; diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h new file mode 100644 index 00000000000..42e3061a0ae --- /dev/null +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +struct crlapb_regs { + u32 reserved0[67]; + u32 cpu_r5_ctrl; + u32 reserved; + u32 iou_switch_ctrl; /* 0x114 */ + u32 reserved1[13]; + u32 timestamp_ref_ctrl; /* 0x14c */ + u32 reserved3[108]; + u32 rst_cpu_r5; + u32 reserved2[17]; + u32 rst_timestamp; /* 0x348 */ +}; + +struct iou_scntrs_regs { + u32 counter_control_register; /* 0x0 */ + u32 reserved0[7]; + u32 base_frequency_id_register; /* 0x20 */ +}; + +struct crp_regs { + u32 reserved0[128]; + u32 boot_mode_usr; /* 0x200 */ +}; + +#define VERSAL2_CRL_APB_BASEADDR 0xEB5E0000 +#define VERSAL2_CRP_BASEADDR 0xF1260000 +#define VERSAL2_IOU_SCNTR_SECURE 0xEC920000 + +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define IOU_SCNTRS_CONTROL_EN 1 + +#define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR) +#define crp_base ((struct crp_regs *)VERSAL2_CRP_BASEADDR) +#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL2_IOU_SCNTR_SECURE) + +#define PMC_TAP 0xF11A0000 + +#define PMC_TAP_IDCODE (PMC_TAP + 0) +#define PMC_TAP_VERSION (PMC_TAP + 0x4) +# define PMC_VERSION_MASK GENMASK(7, 0) +# define PS_VERSION_MASK GENMASK(15, 8) +# define PS_VERSION_PRODUCTION 0x20 +# define RTL_VERSION_MASK GENMASK(23, 16) +# define PLATFORM_MASK GENMASK(27, 24) +# define PLATFORM_VERSION_MASK GENMASK(31, 28) +#define PMC_TAP_USERCODE (PMC_TAP + 0x8) + +/* Bootmode setting values */ +#define BOOT_MODES_MASK 0x0000000F +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 +#define OSPI_MODE 0x00000008 +#define SELECTMAP_MODE 0x0000000A +#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ +#define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 + +enum versal2_platform { + VERSAL2_SILICON = 0, + VERSAL2_SPP = 1, + VERSAL2_EMU = 2, + VERSAL2_QEMU = 3, + VERSAL2_SPP_MMD = 5, + VERSAL2_EMU_MMD = 6, +}; + +#define VERSAL2_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL2_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) + +#define FLASH_RESET_GPIO 0xc +#define WPROT_CRP 0xF126001C +#define RST_GPIO 0xF1260318 +#define WPROT_LPD_MIO 0xFF080728 +#define WPROT_PMC_MIO 0xF1060828 +#define BOOT_MODE_DIR 0xF1020204 +#define BOOT_MODE_OUT 0xF1020208 +#define MIO_PIN_12 0xF1060030 +#define BANK0_OUTPUT 0xF1020040 +#define BANK0_TRI 0xF1060200 diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h new file mode 100644 index 00000000000..7b1726a7ef4 --- /dev/null +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#include <linux/build_bug.h> + +void mem_map_fill(void); diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile deleted file mode 100644 index 858ca9414c0..00000000000 --- a/arch/arm/mach-versatile/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = timer.o -obj-y += reset.o diff --git a/arch/arm/mach-versatile/reset.S b/arch/arm/mach-versatile/reset.S deleted file mode 100644 index c7f1225fb29..00000000000 --- a/arch/arm/mach-versatile/reset.S +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> - */ - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c deleted file mode 100644 index b471412186d..00000000000 --- a/arch/arm/mach-versatile/timer.c +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> - */ - -#include <common.h> - -#define TIMER_ENABLE (1 << 7) -#define TIMER_MODE_MSK (1 << 6) -#define TIMER_MODE_FR (0 << 6) -#define TIMER_MODE_PD (1 << 6) - -#define TIMER_INT_EN (1 << 5) -#define TIMER_PRS_MSK (3 << 2) -#define TIMER_PRS_8S (1 << 3) -#define TIMER_SIZE_MSK (1 << 2) -#define TIMER_ONE_SHT (1 << 0) - -int timer_init (void) -{ - ulong tmr_ctrl_val; - - /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); - tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - - /* - * The Timer Control Register has one Undefined/Shouldn't Use Bit - * So we should do read/modify/write Operation - */ - - /* - * Timer Mode : Free Running - * Interrupt : Disabled - * Prescale : 8 Stage, Clk/256 - * Tmr Siz : 16 Bit Counter - * Tmr in Wrapping Mode - */ - tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); - tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); - tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - - *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; - - return 0; -} diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 5e1ba8d43ed..c1b018cf22e 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -4,7 +4,6 @@ * Copyright (C) 2013 Xilinx, Inc. All rights reserved. */ #include <clk.h> -#include <common.h> #include <dm.h> #include <init.h> #include <malloc.h> diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 3b6518c71c9..c75e453d573 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -3,10 +3,11 @@ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> * Copyright (C) 2012 Xilinx, Inc. All rights reserved. */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <init.h> #include <zynqpl.h> +#include <linux/errno.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index 28988ef95b5..b9a2eef5a6f 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -4,7 +4,7 @@ * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved. */ -#include <common.h> +#include <linux/string.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 5d9f4d23f34..ef877df0fe8 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 - 2017 Xilinx Inc. */ -#include <common.h> #include <asm/io.h> #include <malloc.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index fea1c9b12ad..dc964dc2f9f 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -2,7 +2,6 @@ /* * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek */ -#include <common.h> #include <debug_uart.h> #include <hang.h> #include <image.h> @@ -32,8 +31,8 @@ void board_init_f(ulong dummy) arch_cpu_init(); } -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init(void) +#ifdef CONFIG_SPL_SOC_INIT +void spl_soc_init(void) { preloader_console_init(); #if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA) diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index 3e0c96c5055..f52523edf49 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -68,11 +68,7 @@ SECTIONS __rel_dyn_end = .; } - .end : - { - *(.__end) - } - + _end = .; _image_binary_end = .; /* diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index 0d368443d82..9a912dd5bd7 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <asm/armv7_mpu.h> diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 0d2238ace1e..aea13622b68 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -189,7 +189,18 @@ config SD1_LSHFT_MODE endchoice +config CMD_ZYNQMP + bool "Enable ZynqMP specific commands" + depends on ZYNQMP_FIRMWARE + default y + help + Enable ZynqMP specific commands like "zynqmp secure" + which is used for zynqmp secure image verification. + The secure image is a xilinx specific BOOT.BIN with + either authentication or encryption or both encryption + and authentication feature enabled while generating + BOOT.BIN using Xilinx bootgen tool. + source "board/xilinx/Kconfig" -source "board/xilinx/zynqmp/Kconfig" endif diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 8f897a37d14..38be1627eeb 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,3 +8,7 @@ obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o +endif # !CONFIG_SPL_BUILD diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c index 8a2b7fdcbe9..9a05fbf9c11 100644 --- a/arch/arm/mach-zynqmp/aes.c +++ b/arch/arm/mach-zynqmp/aes.c @@ -7,9 +7,8 @@ * Christian Taedcke <christian.taedcke@weidmueller.com> */ -#include <common.h> #include <mach/zynqmp_aes.h> - +#include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <cpu_func.h> #include <memalign.h> diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c index 3b05f8455bf..9b573b1746a 100644 --- a/arch/arm/mach-zynqmp/clk.c +++ b/arch/arm/mach-zynqmp/clk.c @@ -4,7 +4,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/arch/clk.h> diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 6ae27894ecd..07668c94689 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -4,9 +4,10 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <init.h> #include <time.h> +#include <linux/errno.h> +#include <linux/types.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/mach-zynqmp/ecc_spl_init.c b/arch/arm/mach-zynqmp/ecc_spl_init.c index f547d8e3a5b..1eef1078951 100644 --- a/arch/arm/mach-zynqmp/ecc_spl_init.c +++ b/arch/arm/mach-zynqmp/ecc_spl_init.c @@ -5,7 +5,6 @@ * Jorge Ramirez-Ortiz <jorge@foundries.io> */ -#include <common.h> #include <cpu_func.h> #include <asm/arch/hardware.h> #include <asm/arch/ecc_spl_init.h> diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index dce92438926..b007307e1f3 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -5,7 +5,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h index 2a9cffbd0f8..01a13d4c7c0 100644 --- a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h +++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h @@ -9,6 +9,8 @@ #ifndef ZYNQMP_AES_H #define ZYNQMP_AES_H +#include <linux/types.h> + struct zynqmp_aes { u64 srcaddr; u64 ivaddr; diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index aff9054212c..9b46a25a1cb 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -4,14 +4,16 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <log.h> +#include <vsprintf.h> #include <zynqmp_firmware.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <linux/delay.h> +#include <linux/string.h> #define LOCK 0 #define SPLIT 1 diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index b4d7f44bbee..5b4d66359bf 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -4,7 +4,6 @@ * * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <asm/io.h> #include <asm/arch/psu_init_gpl.h> #include <linux/delay.h> diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 979ff3aef6c..4a2d240abbb 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -5,7 +5,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <image.h> #include <init.h> #include <log.h> @@ -57,8 +56,8 @@ static void ps_mode_reset(ulong mode) # define MODE_RESET PS_MODE1 #endif -#ifdef CONFIG_SPL_BOARD_INIT -void spl_board_init(void) +#ifdef CONFIG_SPL_SOC_INIT +void spl_soc_init(void) { preloader_console_init(); ps_mode_reset(MODE_RESET); diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c new file mode 100644 index 00000000000..bf39c5472ea --- /dev/null +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx, Inc. + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> + */ + +#include <command.h> +#include <cpu_func.h> +#include <env.h> +#include <malloc.h> +#include <memalign.h> +#include <vsprintf.h> +#include <zynqmp_firmware.h> +#include <linux/errno.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <mach/zynqmp_aes.h> + +static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u64 src_addr, addr; + u32 len, src_lo, src_hi; + u8 *key_ptr = NULL; + int ret; + u32 key_lo = 0; + u32 key_hi = 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + if (argc < 4) + return CMD_RET_USAGE; + + src_addr = simple_strtoull(argv[2], NULL, 16); + len = hextoul(argv[3], NULL); + + if (argc == 5) + key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4], + NULL, 16); + + if ((ulong)src_addr != ALIGN((ulong)src_addr, + CONFIG_SYS_CACHELINE_SIZE)) { + printf("Failed: source address not aligned:%lx\n", + (ulong)src_addr); + return -EINVAL; + } + + src_lo = lower_32_bits((ulong)src_addr); + src_hi = upper_32_bits((ulong)src_addr); + flush_dcache_range((ulong)src_addr, (ulong)(src_addr + len)); + + if (key_ptr) { + key_lo = lower_32_bits((ulong)key_ptr); + key_hi = upper_32_bits((ulong)key_ptr); + flush_dcache_range((ulong)key_ptr, + (ulong)(key_ptr + KEY_PTR_LEN)); + } + + ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi, + key_lo, key_hi, ret_payload); + if (ret) { + printf("Failed: secure op status:0x%x\n", ret); + } else { + addr = (u64)ret_payload[1] << 32 | ret_payload[2]; + printf("Verified image at 0x%llx\n", addr); + env_set_hex("zynqmp_verified_img_addr", addr); + } + + return ret; +} + +static int do_zynqmp_mmio_read(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 read_val, addr; + int ret; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + addr = hextoul(argv[2], NULL); + + ret = zynqmp_mmio_read(addr, &read_val); + if (!ret) + printf("mmio read value at 0x%x = 0x%x\n", + addr, read_val); + else + printf("Failed: mmio read\n"); + + return ret; +} + +static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 addr, mask, val; + int ret; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + addr = hextoul(argv[2], NULL); + mask = hextoul(argv[3], NULL); + val = hextoul(argv[4], NULL); + + ret = zynqmp_mmio_write(addr, mask, val); + if (ret != 0) + printf("Failed: mmio write\n"); + + return ret; +} + +static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1); + + if (zynqmp_firmware_version() <= PMUFW_V1_0) { + puts("ERR: PMUFW v1.0 or less is detected\n"); + puts("ERR: Encrypt/Decrypt feature is not supported\n"); + puts("ERR: Please upgrade PMUFW\n"); + return CMD_RET_FAILURE; + } + + if (argc < cmdtp->maxargs - 1) + return CMD_RET_USAGE; + + aes->srcaddr = hextoul(argv[2], NULL); + aes->ivaddr = hextoul(argv[3], NULL); + aes->len = hextoul(argv[4], NULL); + aes->op = hextoul(argv[5], NULL); + aes->keysrc = hextoul(argv[6], NULL); + aes->dstaddr = hextoul(argv[7], NULL); + + if (aes->keysrc == 0) { + if (argc < cmdtp->maxargs) + return CMD_RET_USAGE; + + aes->keyaddr = hextoul(argv[8], NULL); + } + + return zynqmp_aes_operation(aes); +} + +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP +static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u8 mode; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) { + printf("mode param should be lockstep or split\n"); + return CMD_RET_FAILURE; + } + + mode = hextoul(argv[2], NULL); + if (mode != TCM_LOCK && mode != TCM_SPLIT) { + printf("Mode should be either 0(lock)/1(split)\n"); + return CMD_RET_FAILURE; + } + + dcache_disable(); + tcm_init(mode); + dcache_enable(); + + return CMD_RET_SUCCESS; +} +#endif + +static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr, size; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + if (!strncmp(argv[2], "node", 4)) { + u32 id; + int ret; + + if (!strncmp(argv[3], "close", 5)) + return zynqmp_pmufw_config_close(); + + id = dectoul(argv[3], NULL); + if (!id) { + printf("Incorrect ID passed\n"); + return CMD_RET_USAGE; + } + + printf("Enable permission for node ID %d\n", id); + + ret = zynqmp_pmufw_node(id); + if (ret == -ENODEV) + ret = 0; + + return ret; + } + + addr = hextoul(argv[2], NULL); + size = hextoul(argv[3], NULL); + + zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr, + (size_t)size); + + return 0; +} + +static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u64 srcaddr, mod, exp; + u32 srclen, rsaop, size, ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + if (zynqmp_firmware_version() <= PMUFW_V1_0) { + puts("ERR: PMUFW v1.0 or less is detected\n"); + puts("ERR: Encrypt/Decrypt feature is not supported\n"); + puts("ERR: Please upgrade PMUFW\n"); + return CMD_RET_FAILURE; + } + + srcaddr = hextoul(argv[2], NULL); + srclen = hextoul(argv[3], NULL); + if (srclen != RSA_KEY_SIZE) { + puts("ERR: srclen should be equal to 0x200(512 bytes)\n"); + return CMD_RET_USAGE; + } + + mod = hextoul(argv[4], NULL); + exp = hextoul(argv[5], NULL); + rsaop = hextoul(argv[6], NULL); + if (!(rsaop == 0 || rsaop == 1)) { + puts("ERR: rsaop should be either 0 or 1\n"); + return CMD_RET_USAGE; + } + + memcpy((void *)srcaddr + srclen, (void *)mod, MODULUS_LEN); + + /* + * For encryption we load public exponent (key size 4096-bits), + * for decryption we load private exponent (32-bits) + */ + if (rsaop) { + memcpy((void *)srcaddr + srclen + MODULUS_LEN, + (void *)exp, PUB_EXPO_LEN); + size = srclen + MODULUS_LEN + PUB_EXPO_LEN; + } else { + memcpy((void *)srcaddr + srclen + MODULUS_LEN, + (void *)exp, PRIV_EXPO_LEN); + size = srclen + MODULUS_LEN + PRIV_EXPO_LEN; + } + + flush_dcache_range((ulong)srcaddr, + (ulong)(srcaddr) + roundup(size, ARCH_DMA_MINALIGN)); + + ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr), + lower_32_bits((ulong)srcaddr), srclen, rsaop, + ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: RSA status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + u64 srcaddr, hashaddr; + u32 srclen, ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (argc > cmdtp->maxargs || argc < (cmdtp->maxargs - 1)) + return CMD_RET_USAGE; + + if (zynqmp_firmware_version() <= PMUFW_V1_0) { + puts("ERR: PMUFW v1.0 or less is detected\n"); + puts("ERR: Encrypt/Decrypt feature is not supported\n"); + puts("ERR: Please upgrade PMUFW\n"); + return CMD_RET_FAILURE; + } + + srcaddr = hextoul(argv[2], NULL); + srclen = hextoul(argv[3], NULL); + + if (argc == 5) { + hashaddr = hextoul(argv[4], NULL); + flush_dcache_range(hashaddr, + hashaddr + roundup(ZYNQMP_SHA3_SIZE, + ARCH_DMA_MINALIGN)); + } else { + hashaddr = srcaddr; + } + + /* Check srcaddr or srclen != 0 */ + if (!srcaddr || !srclen) { + puts("ERR: srcaddr & srclen should not be 0\n"); + return CMD_RET_USAGE; + } + + flush_dcache_range(srcaddr, + srcaddr + roundup(srclen, ARCH_DMA_MINALIGN)); + + ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0, + ZYNQMP_SHA3_INIT, ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr), + lower_32_bits((ulong)srcaddr), + srclen, ZYNQMP_SHA3_UPDATE, ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr), + lower_32_bits((ulong)hashaddr), + ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL, + ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static struct cmd_tbl cmd_zynqmp_sub[] = { + U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), + U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""), + U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), + U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), + U_BOOT_CMD_MKENT(aes, 9, 0, do_zynqmp_aes, "", ""), + U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""), + U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""), +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP + U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""), +#endif +}; + +/** + * do_zynqmp - Handle the "zynqmp" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Processes the zynqmp specific commands + * + * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error + */ +static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *c; + int ret = CMD_RET_USAGE; + + if (argc < 2) + return CMD_RET_USAGE; + + c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0], + ARRAY_SIZE(cmd_zynqmp_sub)); + if (c) + ret = c->cmd(c, flag, argc, argv); + + return cmd_process_error(c, ret); +} + +/***************************************************/ +U_BOOT_LONGHELP(zynqmp, + "secure src len [key_addr] - verifies secure images of $len bytes\n" + " long at address $src. Optional key_addr\n" + " can be specified if user key needs to\n" + " be used for decryption\n" + "zynqmp mmio_read address - read from address\n" + "zynqmp mmio_write address mask value - write value after masking to\n" + " address\n" + "zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr] -\n" + " Encrypts or decrypts blob of data at src address and puts it\n" + " back to dstaddr using key and iv at keyaddr and ivaddr\n" + " respectively. keysrc value specifies from which source key\n" + " has to be used, it can be User/Device/PUF key. A value of 0\n" + " for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n" + " aesop value specifies the operation which can be 0 for\n" + " decrypt and 1 for encrypt operation\n" +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP + "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" + " initialized before accessing to avoid ECC\n" + " errors. mode specifies in which mode TCM has\n" + " to be initialized. Supported modes will be\n" + " lock(0)/split(1)\n" +#endif + "zynqmp pmufw address size - load PMU FW configuration object\n" + "zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n" + "zynqmp pmufw node close - disable config object loading\n" + " node: keyword, id: NODE_ID in decimal format\n" + "zynqmp rsa srcaddr srclen mod exp rsaop -\n" + " Performs RSA encryption and RSA decryption on blob of data\n" + " at srcaddr and puts it back in srcaddr using modulus and\n" + " public or private exponent\n" + " srclen : must be key size(4096 bits)\n" + " exp : private key exponent for RSA decryption(4096 bits)\n" + " public key exponent for RSA encryption(32 bits)\n" + " rsaop : 0 for RSA Decryption, 1 for RSA Encryption\n" + "zynqmp sha3 srcaddr srclen [key_addr] -\n" + " Generates sha3 hash value for data blob at srcaddr and puts\n" + " 48 bytes hash value into srcaddr\n" + " Optional key_addr can be specified for saving sha3 hash value\n" + " Note: srcaddr/srclen should not be 0\n" + ); + +U_BOOT_CMD( + zynqmp, 9, 1, do_zynqmp, + "ZynqMP sub-system", + zynqmp_help_text +); diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 6bfde5e9bd7..d0a0a4500a9 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -108,26 +108,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 0; }; -#if defined(CONFIG_WATCHDOG) -void watchdog_reset(void) -{ - mbar_writeShort(MCF_WTM_WSR, 0x5555); - mbar_writeShort(MCF_WTM_WSR, 0xAAAA); -} - -int watchdog_disable(void) -{ - mbar_writeShort(MCF_WTM_WCR, 0); - return (0); -} - -int watchdog_init(void) -{ - mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); - return (0); -} -#endif /* #ifdef CONFIG_WATCHDOG */ - #endif #ifdef CONFIG_M5272 @@ -174,49 +154,6 @@ int print_cpuinfo(void) }; #endif /* CONFIG_DISPLAY_CPUINFO */ -#if defined(CONFIG_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ - wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - - out_be16(&wdt->wdog_wcr, 0); -} - -int watchdog_disable(void) -{ - wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - - /* reset watchdog counter */ - out_be16(&wdt->wdog_wcr, 0); - /* disable watchdog interrupt */ - out_be16(&wdt->wdog_wirr, 0); - /* disable watchdog timer */ - out_be16(&wdt->wdog_wrrr, 0); - - puts("WATCHDOG:disabled\n"); - return (0); -} - -int watchdog_init(void) -{ - wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - - /* disable watchdog interrupt */ - out_be16(&wdt->wdog_wirr, 0); - - /* set timeout and enable watchdog */ - out_be16(&wdt->wdog_wrrr, - (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); - - /* reset watchdog counter */ - out_be16(&wdt->wdog_wcr, 0); - - puts("WATCHDOG:enabled\n"); - return (0); -} -#endif /* #ifdef CONFIG_WATCHDOG */ - #endif /* #ifdef CONFIG_M5272 */ #ifdef CONFIG_M5275 @@ -243,51 +180,6 @@ int print_cpuinfo(void) }; #endif /* CONFIG_DISPLAY_CPUINFO */ -#if defined(CONFIG_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ - wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - - out_be16(&wdt->wsr, 0x5555); - out_be16(&wdt->wsr, 0xaaaa); -} - -int watchdog_disable(void) -{ - wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - - /* reset watchdog counter */ - out_be16(&wdt->wsr, 0x5555); - out_be16(&wdt->wsr, 0xaaaa); - - /* disable watchdog timer */ - out_be16(&wdt->wcr, 0); - - puts("WATCHDOG:disabled\n"); - return (0); -} - -int watchdog_init(void) -{ - wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - - /* disable watchdog */ - out_be16(&wdt->wcr, 0); - - /* set timeout and enable watchdog */ - out_be16(&wdt->wmr, - (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); - - /* reset watchdog counter */ - out_be16(&wdt->wsr, 0x5555); - out_be16(&wdt->wsr, 0xaaaa); - - puts("WATCHDOG:enabled\n"); - return (0); -} -#endif /* #ifdef CONFIG_WATCHDOG */ - #endif /* #ifdef CONFIG_M5275 */ #ifdef CONFIG_M5282 diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index c2ef5770a3d..93efc722ba8 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -7,6 +7,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <asm/u-boot.h> + /* Architecture-specific global data */ struct arch_global_data { #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 3719f11c03c..cf6ae5adddf 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -8,7 +8,6 @@ #include <config.h> #include <init.h> -#include <asm/u-boot.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index cb224bd2542..52177670578 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -10,7 +10,6 @@ #include <log.h> #include <spl.h> #include <asm/io.h> -#include <asm/u-boot.h> #include <linux/stringify.h> void board_boot_order(u32 *spl_boot_list) diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index 93506dec894..bb4112f22a3 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -9,6 +9,7 @@ #define __ASM_GBL_DATA_H #include <asm/cpuinfo.h> +#include <asm/u-boot.h> /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 34b7e0bed94..147a95ecea8 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -9,6 +9,7 @@ #include <linux/types.h> #include <asm/regdef.h> +#include <asm/u-boot.h> struct octeon_eeprom_mac_addr { u8 mac_addr_base[6]; diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 40469d1be09..89846c9723c 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -20,7 +20,6 @@ #include <asm/mipsregs.h> #include <asm/addrspace.h> #include <asm/system.h> -#include <asm/u-boot.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 15b2792e619..3fcd0b8465b 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -80,6 +80,7 @@ config SOC_MT7621 bool "MT7621" select MIPS_CM select MIPS_L2_CACHE + select MMC_SUPPORTS_TUNING select SYS_CACHE_SHIFT_5 select SYS_MIPS_CACHE_INIT_RAM_LOAD select PINCTRL_MT7621 diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index de7bfa947f1..792fa01ab9e 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -4,7 +4,7 @@ * Scott McNutt <smcnutt@psyent.com> */ -#include <common.h> +#include <config.h> #include <command.h> #include <cpu.h> #include <cpu_func.h> diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 90cabb67571..27093c4faa3 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -7,7 +7,6 @@ * Scott McNutt <smcnutt@psyent.com> */ -#include <common.h> #include <command.h> #include <irq_func.h> #include <asm/nios2.h> diff --git a/arch/nios2/cpu/traps.c b/arch/nios2/cpu/traps.c index 087a05097d9..59690214f14 100644 --- a/arch/nios2/cpu/traps.c +++ b/arch/nios2/cpu/traps.c @@ -4,8 +4,8 @@ * Scott McNutt <smcnutt@psyent.com> */ -#include <common.h> #include <hang.h> +#include <stdio.h> #include <asm/ptrace.h> void trap_handler (struct pt_regs *regs) diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index b56e8a5078e..d9bbd54734e 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -7,6 +7,7 @@ #define __ASM_NIOS2_GLOBALDATA_H_ #include <linux/types.h> +#include <asm/u-boot.h> /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 657a17c7204..ce939ff5e15 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -4,7 +4,6 @@ * Scott McNutt <smcnutt@psyent.com> */ -#include <common.h> #include <bootm.h> #include <cpu_func.h> #include <env.h> diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c index 5864d8f0f47..8f543f2a2f2 100644 --- a/arch/nios2/lib/cache.c +++ b/arch/nios2/lib/cache.c @@ -5,7 +5,6 @@ * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com */ -#include <common.h> #include <cpu_func.h> #include <asm/cache.h> #include <asm/global_data.h> diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index f6ffe295b8e..3c8cbd4252d 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -9,7 +9,6 @@ * Derived from the MPC8260 and MPC85xx. */ -#include <common.h> #include <cpu_func.h> #include <irq_func.h> #include <net.h> @@ -165,21 +164,6 @@ unsigned long get_tbclk(void) } #endif -#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts(); - - /* Reset the 83xx watchdog */ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - immr->wdt.swsrr = 0x556c; - immr->wdt.swsrr = 0xaa39; - - if (re_enable) - enable_interrupts(); -} -#endif - /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 3e24752e2f6..9ab5ea313d3 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -6,7 +6,6 @@ * based on the contribution of Marian Balakowicz <m8@semihalf.com> */ -#include <common.h> #include <irq_func.h> #include <mpc83xx.h> #include <command.h> diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 33b2151f878..1bd4f2b3449 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <linux/libfdt.h> diff --git a/arch/powerpc/cpu/mpc83xx/interrupts.c b/arch/powerpc/cpu/mpc83xx/interrupts.c index f9486678af3..d86c981811e 100644 --- a/arch/powerpc/cpu/mpc83xx/interrupts.c +++ b/arch/powerpc/cpu/mpc83xx/interrupts.c @@ -6,7 +6,6 @@ * Copyright 2004 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <irq_func.h> #include <mpc83xx.h> diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index 5e02f4094bb..ae60be9e877 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -3,7 +3,6 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> #include <asm/fsl_law.h> #include <asm/mmu.h> diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 65ef0497c2a..6f378c4e221 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -6,7 +6,6 @@ * with some bits from older board-specific PCI initialization. */ -#include <common.h> #include <init.h> #include <pci.h> #include <asm/bitops.h> diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 47ca74c5c35..efa30c68338 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -7,7 +7,6 @@ * Anton Vorontsov <avorontsov@ru.mvista.com> */ -#include <common.h> #include <clock_legacy.h> #include <pci.h> #include <mpc83xx.h> diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 52360703a7d..256dbfe8a4b 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include <common.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/immap_83xx.h> diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index d4848b2ec4d..d3ca24422a5 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -9,7 +9,6 @@ */ #include <config.h> -#include <common.h> #include <asm/io.h> #include <asm/fsl_mpc83xx_serdes.h> #include <linux/delay.h> diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 6da8fc4381d..e847c03f378 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -12,7 +12,6 @@ #ifndef CONFIG_MPC83XX_SDRAM -#include <common.h> #include <cpu_func.h> #include <log.h> #include <time.h> diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b7a87fec2f5..72464962613 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -8,7 +8,6 @@ #ifndef CONFIG_CLK_MPC83XX -#include <common.h> #include <clock_legacy.h> #include <mpc83xx.h> #include <command.h> diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index b55bfaffcae..7036e3fae0c 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -3,7 +3,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <asm-offsets.h> #include <clock_legacy.h> #include <mpc83xx.h> diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index 94e6323d736..79ea1a9bb3c 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -11,7 +11,6 @@ * exceptions */ -#include <common.h> #include <asm/global_data.h> #include <asm/ptrace.h> #include <command.h> diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 013a171ed87..df2f0efe3ed 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -3,7 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 8e18e12f634..25fdb4b0421 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -3,7 +3,6 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index 79213348274..9ebb3d838fa 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -5,7 +5,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index e53dd43f31f..bbe4a0dd62b 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index c7d473d4a1b..f91a4d441d3 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <init.h> #include <linux/compiler.h> diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index e8a3e82765f..ebce2fe3935 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -9,7 +9,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <clock_legacy.h> #include <display_options.h> @@ -350,37 +349,6 @@ __weak unsigned long get_tbclk(void) } -#ifndef CONFIG_WDT -#if defined(CONFIG_WATCHDOG) -#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) -void -init_85xx_watchdog(void) -{ - mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | - TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC)); -} - -void -reset_85xx_watchdog(void) -{ - /* - * Clear TSR(WIS) bit by writing 1 - */ - mtspr(SPRN_TSR, TSR_WIS); -} - -void -watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - - reset_85xx_watchdog(); - if (re_enable) - enable_interrupts(); -} -#endif /* CONFIG_WATCHDOG */ -#endif - /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index a67f37e3af9..574510fa088 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -3,8 +3,9 @@ * Copyright 2009-2012 Freescale Semiconductor, Inc */ -#include <common.h> +#include <asm/ppc.h> #include <system-constants.h> +#include <linux/types.h> #include <asm-offsets.h> #include <asm/global_data.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index e26436bf570..c56e98d4b49 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <config.h> #include <clock_legacy.h> #include <env.h> #include <log.h> diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 9b6577e547e..945020f7ecb 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -3,7 +3,6 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> #include <asm/fsl_serdes.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7c2de02c4c5..78316ea5ffe 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -3,7 +3,7 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <env.h> #include <log.h> #include <time.h> diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index bcbdfac0279..3c98768f22e 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -10,7 +10,7 @@ * Xianghua Xiao (X.Xiao@motorola.com) */ -#include <common.h> +#include <asm/ppc.h> #include <irq_func.h> #include <log.h> #include <time.h> diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 4b8844a4d96..af6731cbb3a 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -3,7 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <log.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 7c47e415f05..b638f24ed14 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -3,7 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <env.h> #include <log.h> diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index cbcb57fe3a5..bafff2083b3 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -5,7 +5,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index a48f3c15128..ad979caf6a7 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index 479ee085d3a..924afa096d1 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 56e5ef6468c..d38041ef5c2 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -5,7 +5,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 47f13e3c1cd..ec0f14ae6a7 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index 7a8f653727e..6d306d99c32 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -5,7 +5,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index 8c5d82ae8ad..49626fc1d1b 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 540a6e6e191..ae5227a1eed 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -3,7 +3,8 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index 3eca3a69326..3943859a518 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 8f645258a5f..0675a59414b 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -3,7 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c index ec8234c1c1e..b1586f110e8 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index db411162022..15ab4ac9385 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -3,7 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c index 463fa119c9b..438fd446be3 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c @@ -3,7 +3,6 @@ * Copyright 2009-2010 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/io.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index bd05eae2551..0a34e066e94 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -3,7 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c index 2327b2c2a41..409f2ac938d 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 6b4cbddcdfe..782874d79d7 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -3,7 +3,6 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 3cf41ca76d5..c3f7493efc7 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -6,7 +6,7 @@ * based on source code of Shlomi Gridish */ -#include <common.h> +#include <config.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/immap_85xx.h> diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9af40310b46..a7e1b3c98a9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <cpu_func.h> #include <clock_legacy.h> #include <ppc_asm.tmpl> diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index ce2b9c21667..29318fad5f0 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -3,7 +3,6 @@ * Copyright 2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/processor.h> #include <asm/global_data.h> #include <fsl_ifc.h> diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index bab076b2b18..7239d28f936 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -3,7 +3,8 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c index 16458e73be1..0d958fe131b 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 59f4f9c6692..bb92fc392cc 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -3,7 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 3a7fdef79c2..2033ebbaa5e 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -3,10 +3,11 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <linux/kernel.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/ppc.h> static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 390bb115375..26a2d745a86 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -3,7 +3,8 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 5f34aab4531..6702acaf772 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -5,9 +5,10 @@ * Shengzhou Liu <Shengzhou.Liu@freescale.com> */ -#include <common.h> +#include <linux/kernel.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> +#include <asm/ppc.h> #include "fsl_corenet2_serdes.h" struct serdes_config { diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 37ea7788ccf..c319bf5cff5 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -3,7 +3,8 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> +#include <linux/kernel.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 61402e84ef6..36fe34f11ec 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -3,7 +3,6 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/fsl_serdes.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 2a78f0fe502..e0b36f869a9 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <config.h> #include <display_options.h> #include <init.h> #include <asm/bitops.h> diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 8f451b48624..db70f07500c 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -19,7 +19,7 @@ * This file handles the architecture-dependent parts of hardware exceptions */ -#include <common.h> +#include <asm/ppc.h> #include <asm/global_data.h> #include <asm/ptrace.h> #include <command.h> diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 73d28f2a4e2..82f28749eb1 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -8,7 +8,6 @@ */ #include <config.h> -#include <common.h> #include <command.h> #include <cpu_func.h> #include <init.h> diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 30042902487..f1c1cbc1c3c 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -8,7 +8,6 @@ * cpu specific common code for 85xx/86xx processors. */ -#include <common.h> #include <cpu_func.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 29489b46e6c..843dd191ccf 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <hang.h> #include <init.h> #include <asm/fsl_lbc.h> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 8e1f6c964d3..29399bcd8b6 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -5,12 +5,14 @@ * Copyright 2012-2016 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <log.h> #include <linux/bitops.h> #include <linux/log2.h> #include <malloc.h> #include <asm/fsl_pamu.h> +#include <asm/io.h> +#include <asm/ppc.h> struct paace *ppaact; struct paace *sec; diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 35409dc8824..f16bc199663 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <display_options.h> #include <asm/bitops.h> #include <asm/global_data.h> diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index b906279226a..831a11736cc 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -3,7 +3,6 @@ * Copyright 2012-2016 Freescale Semiconductor, Inc. */ -#include <common.h> #include <log.h> #include <asm/fsl_pamu.h> #include <asm/global_data.h> diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c0b4a1217d3..0c7288c7574 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -3,13 +3,13 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <config.h> #include <log.h> #include <time.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> +#include <asm/ppc.h> #include <linux/delay.h> #include <linux/errno.h> diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index b94faa5408e..21dfce4c8c7 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -39,6 +39,8 @@ #endif #if defined(__KERNEL__) && !defined(__ASSEMBLY__) +#include <linux/types.h> + extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 1459db74bee..e69e7dbefe8 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -8,7 +8,7 @@ #ifndef _ASM_FSL_DMA_H_ #define _ASM_FSL_DMA_H_ -#include <asm/types.h> +#include <linux/types.h> #ifdef CONFIG_MPC83xx typedef struct fsl_dma { diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 0af3d8902ac..4ce869b5c18 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -6,7 +6,9 @@ #ifndef _FSL_LIODN_H_ #define _FSL_LIODN_H_ -#include <asm/types.h> +#include <config.h> +#include <linux/types.h> +#include <asm/ppc.h> #include <fsl_qbman.h> struct srio_liodn_id_table { diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index 54ef4fb6295..021eec72382 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -6,6 +6,8 @@ #ifndef _FSL_PORTALS_H_ #define _FSL_PORTALS_H_ +#include <linux/types.h> + /* entries must be in order and contiguous */ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index ddde4f80c63..fdf76115233 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -7,6 +7,7 @@ #define __FSL_SERDES_H #include <config.h> +#include <linux/types.h> enum srds_prtcl { /* diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index f7860122a00..a9efbbdd3d4 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -93,4 +93,6 @@ struct arch_global_data { #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") +#include <asm/u-boot.h> + #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/powerpc/include/asm/immap_8xx.h b/arch/powerpc/include/asm/immap_8xx.h index cf1300f6e29..e11300cab20 100644 --- a/arch/powerpc/include/asm/immap_8xx.h +++ b/arch/powerpc/include/asm/immap_8xx.h @@ -12,6 +12,8 @@ #ifndef __IMMAP_8XX__ #define __IMMAP_8XX__ +#include <linux/types.h> + /* System configuration registers. */ typedef struct sys_conf { diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c index 55dcad5df8e..6491c210f4e 100644 --- a/arch/powerpc/lib/bdinfo.c +++ b/arch/powerpc/lib/bdinfo.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 75c6bfd2bf8..f55b5ff8320 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -7,7 +7,7 @@ */ -#include <common.h> +#include <config.h> #include <bootm.h> #include <bootstage.h> #include <cpu_func.h> diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index c4c5c2d4513..e480b269649 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <cpu_func.h> #include <asm/cache.h> #include <watchdog.h> diff --git a/arch/powerpc/lib/extable.c b/arch/powerpc/lib/extable.c index 7e9d4f22f39..fd45e8a790d 100644 --- a/arch/powerpc/lib/extable.c +++ b/arch/powerpc/lib/extable.c @@ -5,7 +5,6 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <log.h> /* diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index df312dfa28e..92b8a0bceac 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -7,7 +7,7 @@ * Gleb Natapov <gnatapov@mrv.com> */ -#include <common.h> +#include <asm/ppc.h> #include <irq_func.h> #include <asm/processor.h> #include <watchdog.h> diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 8727d18884c..20fcb7eef0e 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -1,4 +1,3 @@ -#include <common.h> #include <command.h> #include <kgdb.h> #include <asm/ptrace.h> diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index b638ea7be61..3a24cbfff3b 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -2,7 +2,6 @@ /* * Copyright 2012 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <config.h> #include <log.h> #include <spl.h> diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c index 2e731aa8701..afd869e4ac3 100644 --- a/arch/powerpc/lib/stack.c +++ b/arch/powerpc/lib/stack.c @@ -10,7 +10,6 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/mp.h> diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index 8d6babfb83d..0a0e75e726b 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/io.h> diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c index 03014c56dce..161335abee1 100644 --- a/arch/riscv/lib/boot.c +++ b/arch/riscv/lib/boot.c @@ -4,7 +4,8 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <asm/u-boot.h> +#include <linux/types.h> +#include <asm/u-boot-riscv.h> unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char *const argv[]) diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index 001b2b53c1c..309422f75e3 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -10,6 +10,7 @@ #define __ASM_GBL_DATA_H #include <linux/types.h> +#include <asm/u-boot.h> /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile index 7403a2c3047..6d7e05ebc29 100644 --- a/arch/sh/cpu/sh4/Makefile +++ b/arch/sh/cpu/sh4/Makefile @@ -6,4 +6,4 @@ # (C) Copyright 2007 # Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -obj-y = cpu.o interrupts.o watchdog.o cache.o +obj-y = cpu.o interrupts.o cache.o diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 0f7dfdd3cf7..8c1839935ca 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -4,7 +4,6 @@ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <asm/cache.h> diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index 1b2f50dbe6e..47a8549beba 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -4,13 +4,22 @@ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ -#include <common.h> #include <command.h> #include <irq_func.h> #include <cpu_func.h> #include <net.h> #include <netdev.h> #include <asm/processor.h> +#include <asm/system.h> + +void reset_cpu(void) +{ + /* Address error with SR.BL=1 first. */ + trigger_address_error(); + + while (1) + ; +} int checkcpu(void) { diff --git a/arch/sh/cpu/sh4/interrupts.c b/arch/sh/cpu/sh4/interrupts.c index 278a3e32ac9..eace09aeabf 100644 --- a/arch/sh/cpu/sh4/interrupts.c +++ b/arch/sh/cpu/sh4/interrupts.c @@ -4,7 +4,6 @@ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ -#include <common.h> #include <irq_func.h> int interrupt_init(void) diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c deleted file mode 100644 index bf403d3c520..00000000000 --- a/arch/sh/cpu/sh4/watchdog.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <common.h> -#include <cpu_func.h> -#include <asm/processor.h> -#include <asm/system.h> -#include <asm/io.h> - -#define WDT_BASE WTCNT - -#define WDT_WD (1 << 6) -#define WDT_RST_P (0) -#define WDT_RST_M (1 << 5) -#define WDT_ENABLE (1 << 7) - -#if defined(CONFIG_WATCHDOG) -static unsigned char csr_read(void) -{ - return inb(WDT_BASE + 0x04); -} - -static void cnt_write(unsigned char value) -{ - outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00); -} - -static void csr_write(unsigned char value) -{ - outl((unsigned short)value | 0xA500, WDT_BASE + 0x04); -} - -void watchdog_reset(void) -{ - outl(0x55000000, WDT_BASE + 0x08); -} - -int watchdog_init(void) -{ - /* Set overflow time*/ - cnt_write(0); - /* Power on reset */ - csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE); - - return 0; -} - -int watchdog_disable(void) -{ - csr_write(csr_read() & ~WDT_ENABLE); - return 0; -} -#endif - -void reset_cpu(void) -{ - /* Address error with SR.BL=1 first. */ - trigger_address_error(); - - while (1) - ; -} diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h index bd946ffd8fd..933c302d68c 100644 --- a/arch/sh/include/asm/global_data.h +++ b/arch/sh/include/asm/global_data.h @@ -10,6 +10,8 @@ #ifndef __ASM_SH_GLOBALDATA_H_ #define __ASM_SH_GLOBALDATA_H_ +#include <asm/u-boot.h> + /* Architecture-specific global data */ struct arch_global_data { }; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index b31fa6d7031..53b1c147c2e 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com> */ -#include <common.h> +#include <config.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 05d586b1b6c..e298d766b52 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -7,7 +7,7 @@ * (c) Copyright 2008 Renesas Solutions Corp. */ -#include <common.h> +#include <config.h> #include <bootm.h> #include <command.h> #include <env.h> diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index 19c8e3ca3e7..5feb1983556 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -10,7 +10,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/arch/sh/lib/time_sh2.c b/arch/sh/lib/time_sh2.c index 5484c543c6c..0ee7dc756ba 100644 --- a/arch/sh/lib/time_sh2.c +++ b/arch/sh/lib/time_sh2.c @@ -7,7 +7,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <time.h> #include <asm/io.h> diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index c2e285ff0f6..e731c6a7cb3 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -9,10 +9,10 @@ * Linux SuperH zImage loading and boot */ -#include <common.h> #include <command.h> #include <env.h> #include <irq_func.h> +#include <vsprintf.h> #include <asm/io.h> #include <asm/zimage.h> diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index da01e71335f..13fe695014b 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -6,10 +6,10 @@ #define LOG_CATEGORY UCLASS_IRQ -#include <common.h> #include <dm.h> #include <irq.h> #include <log.h> +#include <time.h> #include <acpi/acpi_device.h> #include <asm/io.h> #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index c610a7f4477..76230aea837 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <cpu.h> #include <dm.h> #include <log.h> diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index 647c9df6a72..f480bb1d8c3 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <log.h> diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c index 9a5502617bf..498b306cd61 100644 --- a/arch/x86/cpu/apollolake/cpu_common.c +++ b/arch/x86/cpu/apollolake/cpu_common.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <dm.h> #include <log.h> #include <asm/cpu_common.h> diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8f48457ee22..8798fa79d4c 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -5,7 +5,6 @@ * Portions taken from coreboot */ -#include <common.h> #include <dm.h> #include <ec_commands.h> #include <init.h> diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index fb75e1f7095..f6fbddce922 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -3,7 +3,6 @@ * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com */ -#include <common.h> #include <dm.h> #include <log.h> #include <asm/arch/fsp_bindings.h> diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index c6be707e4ea..19065e17ae0 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <log.h> #include <asm/arch/iomap.h> diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index a9b13c0c704..5fca19f90d3 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <binman.h> #include <bootstage.h> #include <dm.h> diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 2405dec8525..9ee362239ef 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_NORTHBRIDGE -#include <common.h> #include <dm.h> #include <dt-structs.h> #include <log.h> diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index 4be6366f043..531ff1cd91f 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -5,7 +5,6 @@ * From coreboot Apollo Lake support lpc.c */ -#include <common.h> #include <dm.h> #include <log.h> #include <spl.h> diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index a0f9b031dea..32190312ff8 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <dm.h> #include <pch.h> #include <spl.h> diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 163119e2e9e..32fd0344861 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC -#include <common.h> #include <dm.h> #include <dt-structs.h> #include <log.h> diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c index 5ed7963579e..b1503c25140 100644 --- a/arch/x86/cpu/apollolake/punit.c +++ b/arch/x86/cpu/apollolake/punit.c @@ -3,10 +3,10 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <dm.h> #include <log.h> #include <spl.h> +#include <time.h> #include <asm/cpu.h> #include <asm/cpu_common.h> #include <asm/intel_regs.h> diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index 6078d5a200e..b351d73e7d8 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include <common.h> #include <binman_sym.h> #include <bootstage.h> #include <dm.h> diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c index b6bc2ba14f1..f966b9083fc 100644 --- a/arch/x86/cpu/apollolake/systemagent.c +++ b/arch/x86/cpu/apollolake/systemagent.c @@ -4,7 +4,6 @@ * Take from coreboot project file of the same name */ -#include <common.h> #include <asm/intel_regs.h> #include <asm/io.h> #include <asm/arch/systemagent.h> diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c index a9362436000..7e4c816dcef 100644 --- a/arch/x86/cpu/apollolake/uart.c +++ b/arch/x86/cpu/apollolake/uart.c @@ -7,7 +7,6 @@ * Some code from coreboot lpss.c */ -#include <common.h> #include <dm.h> #include <dt-structs.h> #include <malloc.h> diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index ccc4851b188..7821964f1fc 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <log.h> diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index c270426d820..7756a1a4a8e 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -5,7 +5,6 @@ * Based on code from coreboot */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <event.h> diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index 08dbd5538f7..3736127239e 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include <common.h> #include <errno.h> #include <asm/io.h> diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index fb3f946c45f..9eb456f90d1 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -5,7 +5,6 @@ * Copyright (C) 2015, Kodak Alaris, Inc */ -#include <common.h> #include <fdtdec.h> #include <log.h> #include <asm/fsp1/fsp_support.h> diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index f73738ce5c0..839ff4d2bf2 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <init.h> #include <mmc.h> #include <pci_ids.h> @@ -11,6 +10,7 @@ #include <asm/mrccache.h> #include <asm/post.h> #include <asm/arch/iomap.h> +#include <asm/u-boot-x86.h> #include <linux/bitops.h> /* GPIO SUS */ diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c index 3345049993d..8cf4b628d41 100644 --- a/arch/x86/cpu/braswell/braswell.c +++ b/arch/x86/cpu/braswell/braswell.c @@ -3,10 +3,10 @@ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <init.h> #include <asm/mrccache.h> #include <asm/post.h> +#include <asm/u-boot-x86.h> int arch_cpu_init(void) { diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c index d78c6b0feb6..8b28d28d136 100644 --- a/arch/x86/cpu/braswell/early_uart.c +++ b/arch/x86/cpu/braswell/early_uart.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <asm/io.h> #define PCI_DEV_CONFIG(segbus, dev, fn) ( \ diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c index 243298fd571..aaf3e67f81c 100644 --- a/arch/x86/cpu/braswell/fsp_configs.c +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <log.h> #include <asm/fsp1/fsp_support.h> diff --git a/arch/x86/cpu/broadwell/adsp.c b/arch/x86/cpu/broadwell/adsp.c index 1fa18237809..90b2449475e 100644 --- a/arch/x86/cpu/broadwell/adsp.c +++ b/arch/x86/cpu/broadwell/adsp.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY UCLASS_SYSCON -#include <common.h> #include <dm.h> #include <log.h> #include <pci.h> diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index cbd4a3b6797..dc6717eca40 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -5,7 +5,6 @@ * Based on code from coreboot src/soc/intel/broadwell/cpu.c */ -#include <common.h> #include <dm.h> #include <cpu.h> #include <event.h> diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c b/arch/x86/cpu/broadwell/cpu_from_spl.c index df5a9675ee4..a48be295994 100644 --- a/arch/x86/cpu/broadwell/cpu_from_spl.c +++ b/arch/x86/cpu/broadwell/cpu_from_spl.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <bloblist.h> #include <cpu_func.h> #include <debug_uart.h> @@ -13,6 +12,7 @@ #include <log.h> #include <asm/global_data.h> #include <asm/mtrr.h> +#include <linux/errno.h> int misc_init_r(void) { diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 2049dbfe24a..c43fb7a608b 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -5,7 +5,6 @@ * Based on code from coreboot src/soc/intel/broadwell/cpu.c */ -#include <common.h> #include <dm.h> #include <cpu.h> #include <init.h> diff --git a/arch/x86/cpu/broadwell/iobp.c b/arch/x86/cpu/broadwell/iobp.c index cb5595c930e..f8b2a60d09f 100644 --- a/arch/x86/cpu/broadwell/iobp.c +++ b/arch/x86/cpu/broadwell/iobp.c @@ -5,7 +5,6 @@ * Modified from coreboot */ -#include <common.h> #include <errno.h> #include <asm/intel_regs.h> #include <asm/io.h> diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c index d2638a4e7a6..b945693f1cf 100644 --- a/arch/x86/cpu/broadwell/lpc.c +++ b/arch/x86/cpu/broadwell/lpc.c @@ -5,7 +5,6 @@ * From coreboot broadwell support */ -#include <common.h> #include <dm.h> #include <log.h> #include <pch.h> diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c index ae16ce26499..3399d822e5b 100644 --- a/arch/x86/cpu/broadwell/me.c +++ b/arch/x86/cpu/broadwell/me.c @@ -5,7 +5,6 @@ * Based on code from coreboot src/soc/intel/broadwell/me_status.c */ -#include <common.h> #include <errno.h> #include <log.h> #include <asm/arch/me.h> diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c index 141babc51c3..d67ab03627d 100644 --- a/arch/x86/cpu/broadwell/northbridge.c +++ b/arch/x86/cpu/broadwell/northbridge.c @@ -3,7 +3,6 @@ * Copyright (C) 2011 The Chromium Authors */ -#include <common.h> #include <dm.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 37fcddbb9b0..2c8b7380d96 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <log.h> #include <pch.h> diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c index 85bd37101ba..b6313c3466a 100644 --- a/arch/x86/cpu/broadwell/pinctrl_broadwell.c +++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c index 62fd2e8d2c0..e1d60915f55 100644 --- a/arch/x86/cpu/broadwell/power_state.c +++ b/arch/x86/cpu/broadwell/power_state.c @@ -5,7 +5,6 @@ * Copyright (C) 2016 Google, Inc. */ -#include <common.h> #include <log.h> #include <pci.h> #include <asm/io.h> diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index df2df7972e9..653d31dd67c 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -6,7 +6,7 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> +#include <config.h> #include <display_options.h> #include <errno.h> #include <init.h> diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c index be3c9e764ef..0f67ba9666f 100644 --- a/arch/x86/cpu/broadwell/sata.c +++ b/arch/x86/cpu/broadwell/sata.c @@ -5,7 +5,6 @@ * From coreboot src/soc/intel/broadwell/sata.c */ -#include <common.h> #include <dm.h> #include <log.h> #include <asm/global_data.h> diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index d30ebee021e..cd534a17cf1 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include <common.h> #include <dm.h> #include <init.h> #include <log.h> diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 82fe4c71cd2..d474c79e25e 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -5,7 +5,6 @@ * Graeme Russ, graeme.russ@gmail.com. */ -#include <common.h> #include <cpu_func.h> #include <event.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c index 36661871e92..566c65a96ae 100644 --- a/arch/x86/cpu/coreboot/coreboot_spl.c +++ b/arch/x86/cpu/coreboot/coreboot_spl.c @@ -3,7 +3,6 @@ * Copyright 2020 Google LLC */ -#include <common.h> #include <init.h> int dram_init(void) diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 26352df421f..013225f129a 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -5,7 +5,6 @@ * Graeme Russ, <graeme.russ@gmail.com> */ -#include <common.h> #include <init.h> #include <asm/e820.h> #include <asm/cb_sysinfo.h> diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index 3ad611a530c..ec4003c4e77 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -5,10 +5,10 @@ * Modified from the coreboot version */ -#include <common.h> #include <bootstage.h> #include <asm/arch/timestamp.h> #include <asm/cb_sysinfo.h> +#include <asm/u-boot-x86.h> #include <linux/compiler.h> static struct timestamp_table *ts_table __section(".data"); diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ce55efc454b..c8433360f28 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -20,7 +20,6 @@ #define LOG_CATEGORY UCLASS_CPU -#include <common.h> #include <bootstage.h> #include <command.h> #include <cpu_func.h> diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 59da41f3833..6c53f0ea821 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <errno.h> diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index f754489784a..218a68c4642 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -3,11 +3,11 @@ * Copyright (c) 2015 Google, Inc */ -#include <common.h> #include <cpu_func.h> #include <fdtdec.h> #include <init.h> #include <netdev.h> +#include <asm/u-boot-x86.h> int arch_cpu_init(void) { diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 708bfbe7ee4..642a87a37d8 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <cpu_func.h> #include <efi.h> #include <efi_api.h> @@ -17,6 +16,7 @@ #include <asm/e820.h> #include <asm/global_data.h> #include <asm/post.h> +#include <asm/u-boot-x86.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 56f3326146c..6fe40071140 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -3,7 +3,6 @@ * Copyright (c) 2015 Google, Inc */ -#include <common.h> #include <efi.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 8882532ebf3..db2727d7485 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -18,7 +18,6 @@ * src/arch/x86/lib/cpu.c */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <log.h> @@ -32,6 +31,7 @@ #include <asm/msr.h> #include <asm/mtrr.h> #include <asm/processor-flags.h> +#include <asm/u-boot-x86.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index f3f3527237f..b3f4214acdb 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -10,7 +10,6 @@ * Copyright (C) 1991, 1992 Linus Torvalds */ -#include <common.h> #include <dm.h> #include <efi_loader.h> #include <hang.h> diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c index d94ec208f65..29676b4abfa 100644 --- a/arch/x86/cpu/intel_common/acpi.c +++ b/arch/x86/cpu/intel_common/acpi.c @@ -8,7 +8,6 @@ * Modified from coreboot src/soc/intel/common/block/acpi.c */ -#include <common.h> #include <bloblist.h> #include <cpu.h> #include <dm.h> diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index 00308dbdef9..46d9ede09cb 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -10,7 +10,6 @@ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> */ -#include <common.h> #include <asm/microcode.h> #include <asm/msr-index.h> #include <asm/mtrr.h> diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 8f489e6c651..e7f41913042 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -7,7 +7,6 @@ * Some code taken from coreboot cpulib.c */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <errno.h> diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index 1c0dcedb582..48b2ef253cb 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <errno.h> #include <handoff.h> diff --git a/arch/x86/cpu/intel_common/fast_spi.c b/arch/x86/cpu/intel_common/fast_spi.c index 5d3944dee2c..e1d536be212 100644 --- a/arch/x86/cpu/intel_common/fast_spi.c +++ b/arch/x86/cpu/intel_common/fast_spi.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <asm/io.h> #include <asm/cpu_common.h> #include <asm/fast_spi.h> diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 61ec5391b09..75fa4e01d8a 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -6,7 +6,6 @@ * Modified from coreboot src/drivers/wifi/generic.c */ -#include <common.h> #include <log.h> #include <acpi/acpigen.h> #include <acpi/acpi_device.h> diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c index 1eed21d8cdf..78caff0dc12 100644 --- a/arch/x86/cpu/intel_common/intel_opregion.c +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -6,7 +6,6 @@ * Modified from coreboot src/soc/intel/gma/opregion.c */ -#include <common.h> #include <binman.h> #include <bloblist.h> #include <dm.h> diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index ec73b3d8931..6d3184f969f 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -9,7 +9,6 @@ * Taken from coreboot itss.c */ -#include <common.h> #include <dm.h> #include <dt-structs.h> #include <irq.h> diff --git a/arch/x86/cpu/intel_common/lpc.c b/arch/x86/cpu/intel_common/lpc.c index af68c0f079c..f2bdf8c1e87 100644 --- a/arch/x86/cpu/intel_common/lpc.c +++ b/arch/x86/cpu/intel_common/lpc.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/intel_common/lpss.c b/arch/x86/cpu/intel_common/lpss.c index 26a2d2d1e36..44cd3f0ca5f 100644 --- a/arch/x86/cpu/intel_common/lpss.c +++ b/arch/x86/cpu/intel_common/lpss.c @@ -7,7 +7,6 @@ * Some code from coreboot lpss.c */ -#include <common.h> #include <dm.h> #include <pci.h> #include <asm/io.h> diff --git a/arch/x86/cpu/intel_common/me_status.c b/arch/x86/cpu/intel_common/me_status.c index abc5f6fbc77..a09bd5029eb 100644 --- a/arch/x86/cpu/intel_common/me_status.c +++ b/arch/x86/cpu/intel_common/me_status.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. */ -#include <common.h> #include <log.h> #include <asm/arch/me.h> diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 4d8e1d21083..6cad2727075 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -6,7 +6,6 @@ * Microcode update for Intel PIII and later CPUs */ -#include <common.h> #include <errno.h> #include <fdtdec.h> #include <log.h> diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index ff959d1bd8d..c834c05d130 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -5,17 +5,17 @@ #define LOG_CATEGORY UCLASS_RAM -#include <common.h> +#include <config.h> #include <dm.h> #include <init.h> #include <log.h> #include <spl.h> #include <syscon.h> +#include <time.h> #include <asm/cpu.h> #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/intel_regs.h> -#include <asm/mrc_common.h> #include <asm/pch_common.h> #include <asm/post.h> #include <asm/arch/me.h> diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index e4e53f73c08..7aad8f8ca56 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY UCLASS_P2SB -#include <common.h> #include <dm.h> #include <dt-structs.h> #include <log.h> diff --git a/arch/x86/cpu/intel_common/pch.c b/arch/x86/cpu/intel_common/pch.c index af82b64a13c..c4cc478b306 100644 --- a/arch/x86/cpu/intel_common/pch.c +++ b/arch/x86/cpu/intel_common/pch.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <asm/pch_common.h> diff --git a/arch/x86/cpu/intel_common/report_platform.c b/arch/x86/cpu/intel_common/report_platform.c index a3612817c45..a7524435ba0 100644 --- a/arch/x86/cpu/intel_common/report_platform.c +++ b/arch/x86/cpu/intel_common/report_platform.c @@ -5,12 +5,12 @@ * Copyright (C) 2012 Google Inc. */ -#include <common.h> #include <log.h> #include <asm/cpu.h> #include <asm/pci.h> #include <asm/report_platform.h> #include <asm/arch/pch.h> +#include <linux/string.h> static void report_cpu_info(void) { diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c index 4f99de6ece2..fa912bac57d 100644 --- a/arch/x86/cpu/ioapic.c +++ b/arch/x86/cpu/ioapic.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/ioapic.h> diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 766b2451a2c..d4dd1816092 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 417290f559e..8ae4798f125 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2014 Google, Inc */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index e71a10bfd44..d71ab0a6385 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -10,7 +10,6 @@ * Copyright (C) 2011 Google Inc. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index bee1671baf8..ac868025f8e 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. */ -#include <common.h> #include <dm.h> #include <errno.h> #include <log.h> diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c index 3c4ea6c267f..19b6ef283bc 100644 --- a/arch/x86/cpu/ivybridge/fsp_configs.c +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <log.h> #include <asm/fsp1/fsp_support.h> diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c index eb3f362e4e9..81b54bb8dda 100644 --- a/arch/x86/cpu/ivybridge/ivybridge.c +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -3,10 +3,10 @@ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <init.h> #include <asm/post.h> #include <asm/processor.h> +#include <asm/u-boot-x86.h> int arch_cpu_init(void) { diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index f931d2be1b5..17a47edadbb 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -5,7 +5,6 @@ * Copyright (C) 2008-2009 coresystems GmbH */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 3906a69796f..b72de96a277 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -6,7 +6,6 @@ * Copyright (C) 2011 The Chromium Authors */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 994f8a4ff6a..76e52f38ad8 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -6,7 +6,6 @@ * Copyright (C) 2011 The Chromium Authors */ -#include <common.h> #include <dm.h> #include <log.h> #include <asm/global_data.h> diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index f47ecdffae7..4e2484fa956 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -4,7 +4,6 @@ * Copyright (C) 2008-2009 coresystems GmbH */ -#include <common.h> #include <ahci.h> #include <dm.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 95a826da713..bddec6c66b6 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -11,7 +11,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index 51dfe23f94d..d20c9a2a379 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c index c0691454f12..55b1b1833ee 100644 --- a/arch/x86/cpu/lapic.c +++ b/arch/x86/cpu/lapic.c @@ -6,7 +6,6 @@ * Copyright (C) 2014 Google, Inc */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/lapic.h> diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index a133a5d8116..aa1f47d7227 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -5,13 +5,13 @@ * Based on code from the coreboot file of the same name */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <errno.h> #include <log.h> #include <malloc.h> #include <qfw.h> +#include <time.h> #include <asm/atomic.h> #include <asm/cpu.h> #include <asm/global_data.h> diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 9c24ae984e9..50cba5fb88d 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -16,7 +16,6 @@ * since the MTRR registers are sometimes in flux. */ -#include <common.h> #include <cpu_func.h> #include <log.h> #include <sort.h> diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 8a992ed8233..a7ad57f6de0 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -8,7 +8,6 @@ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> */ -#include <common.h> #include <dm.h> #include <errno.h> #include <log.h> diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index 735b6560843..0708a380626 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com> */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <errno.h> diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index d83abf00527..62a301c0fd3 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/post.h> diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index ebfe5956442..17a04f86479 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -6,7 +6,6 @@ * (C) Copyright 2019 Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <env_internal.h> #include <malloc.h> #include <asm/e820.h> diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 70414556086..262584d01f0 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <pci.h> @@ -14,6 +13,7 @@ #include <asm/processor.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> +#include <asm/u-boot-x86.h> static bool i440fx; diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c index ee00b8fe732..468df5a36e6 100644 --- a/arch/x86/cpu/qfw_cpu.c +++ b/arch/x86/cpu/qfw_cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Google, Inc */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <malloc.h> diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 0e18ceab68d..80e94600fc5 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -3,13 +3,13 @@ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <mapmem.h> #include <acpi/acpi_table.h> #include <asm/processor.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> +#include <linux/string.h> static int quark_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index ad98f3e07ba..34e576940d4 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu_func.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index df14779357d..3cca6bd4c22 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -7,7 +7,6 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ -#include <common.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> #include "mrc_util.h" diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index ce3c2b8ab42..be9c36b96c4 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -32,9 +32,9 @@ * DRAM unit configuration based on Valleyview MRC. */ -#include <common.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> +#include <asm/u-boot-x86.h> #include "mrc_util.h" #include "smc.h" diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index b0bc59b71ef..85408b3e335 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -7,12 +7,12 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ -#include <common.h> #include <hang.h> #include <asm/arch/device.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> +#include <asm/u-boot-x86.h> #include "mrc_util.h" #include "hte.h" #include "smc.h" diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c index d4f8c082ffc..6261766cdf8 100644 --- a/arch/x86/cpu/quark/msg_port.c +++ b/arch/x86/cpu/quark/msg_port.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <asm/arch/device.h> #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 62b83c228cf..fdf92b2c0c3 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu_func.h> #include <event.h> #include <init.h> @@ -19,6 +18,7 @@ #include <asm/arch/device.h> #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> +#include <asm/u-boot-x86.h> #include <linux/delay.h> static void quark_setup_mtrr(void) diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index b4b3e1204bd..a7e92b3f5c1 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -7,11 +7,12 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ -#include <common.h> #include <pci.h> #include <asm/arch/device.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> +#include <asm/u-boot-x86.h> +#include <linux/string.h> #include "mrc_util.h" #include "hte.h" #include "smc.h" diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 381edd07615..3b5cbdb44f1 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <asm/fsp1/fsp_support.h> void fsp_update_configs(struct fsp_config_data *config, diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 4a008622d19..7c7eb413f99 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <dm.h> #include <init.h> #include <dm/device-internal.h> diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index fbb33b246e5..75ca5273625 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation <www.intel.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <linux/sizes.h> diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c index d28b280890d..4c889dad6d2 100644 --- a/arch/x86/cpu/slimbootloader/serial.c +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation <www.intel.com> */ -#include <common.h> #include <dm.h> #include <log.h> #include <ns16550.h> diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c index ec5b87cfd63..142c9341cf8 100644 --- a/arch/x86/cpu/slimbootloader/slimbootloader.c +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Intel Corporation <www.intel.com> */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <log.h> diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 1d37cc9e2b0..d4d0ef6f855 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -5,7 +5,6 @@ * Partially based on acpi.c for other x86 platforms */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <mapmem.h> diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c index 23bfa7c18d2..6afb8646a98 100644 --- a/arch/x86/cpu/tangier/pinmux.c +++ b/arch/x86/cpu/tangier/pinmux.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Emlid Limited */ -#include <common.h> #include <dm.h> #include <log.h> #include <dm/pinctrl.h> diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 374b262b134..6192f2296b8 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Intel Corporation */ -#include <common.h> #include <init.h> #include <log.h> #include <asm/e820.h> diff --git a/arch/x86/cpu/tangier/sysreset.c b/arch/x86/cpu/tangier/sysreset.c index b03bc28f935..f57423a611d 100644 --- a/arch/x86/cpu/tangier/sysreset.c +++ b/arch/x86/cpu/tangier/sysreset.c @@ -5,7 +5,6 @@ * Reset driver for tangier processor */ -#include <common.h> #include <dm.h> #include <sysreset.h> #include <asm/scu.h> diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c index 1e2f6cc8b70..8a8f7d27a9d 100644 --- a/arch/x86/cpu/tangier/tangier.c +++ b/arch/x86/cpu/tangier/tangier.c @@ -3,7 +3,6 @@ * Copyright (c) 2017 Intel Corporation */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <asm/u-boot-x86.h> diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index e2c84cddec8..c9b402c4dc7 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -5,7 +5,6 @@ * Copyright (C) 2011 The Chromium Authors. */ -#include <common.h> #include <log.h> #include <asm/cpu.h> #include <asm/global_data.h> diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 5ea746ecce4..80eab710315 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <cpu_func.h> #include <debug_uart.h> #include <init.h> diff --git a/arch/x86/cpu/x86_64/interrupts.c b/arch/x86/cpu/x86_64/interrupts.c index 634f7660c03..b84ff798814 100644 --- a/arch/x86/cpu/x86_64/interrupts.c +++ b/arch/x86/cpu/x86_64/interrupts.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <irq_func.h> #include <asm/processor-flags.h> diff --git a/arch/x86/cpu/x86_64/misc.c b/arch/x86/cpu/x86_64/misc.c index 691b67ff68a..294511e6eba 100644 --- a/arch/x86/cpu/x86_64/misc.c +++ b/arch/x86/cpu/x86_64/misc.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <init.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/include/asm/arch-quark/mrc.h b/arch/x86/include/asm/arch-quark/mrc.h index 2353426cd6d..40c92a549cd 100644 --- a/arch/x86/include/asm/arch-quark/mrc.h +++ b/arch/x86/include/asm/arch-quark/mrc.h @@ -10,6 +10,8 @@ #ifndef _MRC_H_ #define _MRC_H_ +#include <linux/types.h> + #define MRC_VERSION 0x0111 /* architectural definitions */ diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h index 9527fdad3fd..98a9360d543 100644 --- a/arch/x86/include/asm/arch-quark/msg_port.h +++ b/arch/x86/include/asm/arch-quark/msg_port.h @@ -34,6 +34,8 @@ #ifndef __ASSEMBLY__ +#include <linux/types.h> + /** * msg_port_setup - set up the message port control register * diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index feca1983ba8..dec30e2b27f 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -71,6 +71,8 @@ #ifndef __ASSEMBLY__ +#include <linux/types.h> + /* variable range MTRR usage */ enum { MTRR_VAR_ROM, diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 12fa395ffd2..5864b2700ce 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -9,6 +9,7 @@ #define _COREBOOT_SYSINFO_H #include <asm/coreboot_tables.h> +#include <linux/types.h> /* Maximum number of memory range definitions */ #define SYSINFO_MAX_MEM_RANGES 32 diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 0dfb64babb9..54aeffb9889 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -8,6 +8,9 @@ #ifndef _COREBOOT_TABLES_H #define _COREBOOT_TABLES_H +#include <linux/kernel.h> +#include <linux/types.h> + struct timestamp_entry { u32 entry_id; u64 entry_stamp; diff --git a/arch/x86/include/asm/early_cmos.h b/arch/x86/include/asm/early_cmos.h index 543a9e69f03..007aeb7c23e 100644 --- a/arch/x86/include/asm/early_cmos.h +++ b/arch/x86/include/asm/early_cmos.h @@ -6,6 +6,8 @@ #ifndef __EARLY_CMOS_H #define __EARLY_CMOS_H +#include <linux/types.h> + /* CMOS actually resides in the RTC SRAM */ #define CMOS_IO_PORT 0x70 diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 1ef7f1f0349..06bd80ccc13 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -12,6 +12,7 @@ #include <linux/types.h> #include <asm/processor.h> #include <asm/mrccache.h> +#include <asm/u-boot.h> enum pei_boot_mode_t { PEI_BOOT_NONE = 0, diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h index aec49b9b815..5f6691939eb 100644 --- a/arch/x86/include/asm/handoff.h +++ b/arch/x86/include/asm/handoff.h @@ -9,6 +9,8 @@ #ifndef __x86_asm_handoff_h #define __x86_asm_handoff_h +#include <linux/types.h> + /** * struct arch_spl_handoff - architecture-specific handoff info * diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h index 85703683149..aa478594ec9 100644 --- a/arch/x86/include/asm/me_common.h +++ b/arch/x86/include/asm/me_common.h @@ -13,6 +13,7 @@ #define __ASM_ME_COMMON_H #include <linux/compiler.h> +#include <linux/string.h> #include <linux/types.h> #include <pci.h> diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index f4c4d6c257c..7c08f7a1d5c 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -11,6 +11,7 @@ #include <asm/atomic.h> #include <asm/cache.h> #include <linux/bitops.h> +#include <linux/errno.h> struct udevice; diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c index 155fffabf08..a73a2539ad3 100644 --- a/arch/x86/lib/acpi.c +++ b/arch/x86/lib/acpi.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <log.h> #include <acpi/acpi_table.h> #include <asm/io.h> diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 08e13fdea67..880ef31df7d 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <binman.h> #include <dm.h> #include <log.h> diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 2c70acbe7b0..3a1e3318a15 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -3,7 +3,6 @@ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <acpi/acpi_s3.h> #include <acpi/acpi_table.h> #include <asm/acpi.h> diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a5683132b01..a42a7e6bbd6 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <bloblist.h> #include <cpu.h> #include <dm.h> diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c index ea2ec2a9083..b486f8fb37d 100644 --- a/arch/x86/lib/acpigen.c +++ b/arch/x86/lib/acpigen.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Google LLC */ -#include <common.h> #include <acpi/acpigen.h> #include <acpi/acpi_table.h> #include <asm/acpigen.h> diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c index 8df67db65c3..7b2905dda56 100644 --- a/arch/x86/lib/asm-offsets.c +++ b/arch/x86/lib/asm-offsets.c @@ -11,7 +11,6 @@ * #defines from the assembly-language output. */ -#include <common.h> #include <asm/global_data.h> #include <linux/kbuild.h> diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 124058442c5..165e8ab944f 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -5,7 +5,6 @@ * Copyright 2021 Google LLC */ -#include <common.h> #include <efi.h> #include <init.h> #include <asm/cpu.h> diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index f146bbd5422..03f7360032c 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -5,7 +5,6 @@ * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2009-2010 coresystems GmbH */ -#include <common.h> #include <compiler.h> #include <bios_emul.h> #include <irq_func.h> diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index d6b4da7e250..b2cf1527b1c 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -7,7 +7,6 @@ * Copyright (C) 2007-2009 coresystems GmbH */ -#include <common.h> #include <log.h> #include <asm/pci.h> #include "bios_emul.h" diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 050c420e86b..2c889bcd33c 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -7,7 +7,6 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ -#include <common.h> #include <bootm.h> #include <bootstage.h> #include <command.h> diff --git a/arch/x86/lib/cmd_boot.c b/arch/x86/lib/cmd_boot.c index 4facbe5f32f..0444a5f89d3 100644 --- a/arch/x86/lib/cmd_boot.c +++ b/arch/x86/lib/cmd_boot.c @@ -14,7 +14,6 @@ * Marius Groeger <mgroeger@sysgo.de> */ -#include <common.h> #include <command.h> #include <malloc.h> #include <asm/global_data.h> diff --git a/arch/x86/lib/coreboot/cb_support.c b/arch/x86/lib/coreboot/cb_support.c index ebb45cdfb5b..b4d5fa4af32 100644 --- a/arch/x86/lib/coreboot/cb_support.c +++ b/arch/x86/lib/coreboot/cb_support.c @@ -5,9 +5,9 @@ * Copyright 2021 Google LLC */ -#include <common.h> #include <asm/cb_sysinfo.h> #include <asm/e820.h> +#include <linux/kernel.h> unsigned int cb_install_e820_map(unsigned int max_entries, struct e820_entry *entries) diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c index f7fd9ea5bcb..ec997fa49cf 100644 --- a/arch/x86/lib/coreboot/cb_sysinfo.c +++ b/arch/x86/lib/coreboot/cb_sysinfo.c @@ -6,12 +6,12 @@ * Copyright (C) 2009 coresystems GmbH */ -#include <common.h> #include <asm/cb_sysinfo.h> #include <init.h> #include <mapmem.h> #include <net.h> #include <asm/global_data.h> +#include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 05519d851a9..33fce5d0a5e 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -3,7 +3,6 @@ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <malloc.h> #include <net.h> #include <vesa.h> diff --git a/arch/x86/lib/div64.c b/arch/x86/lib/div64.c index 2bea205f60f..57da889ef49 100644 --- a/arch/x86/lib/div64.c +++ b/arch/x86/lib/div64.c @@ -6,7 +6,7 @@ * Copyright 2014 Google Inc. */ -#include <common.h> +#include <linux/types.h> union overlay64 { u64 longw; diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index 12fcff12380..122b4f7ca01 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -3,7 +3,6 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <efi_loader.h> #include <asm/e820.h> #include <asm/global_data.h> diff --git a/arch/x86/lib/early_cmos.c b/arch/x86/lib/early_cmos.c index f7b3bb2a8e1..5635d08718f 100644 --- a/arch/x86/lib/early_cmos.c +++ b/arch/x86/lib/early_cmos.c @@ -10,7 +10,6 @@ * uclass write ops, that data is stored in little-endian mode. */ -#include <common.h> #include <asm/early_cmos.h> #include <asm/io.h> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 8f2977a8070..c47e6ca4738 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index cc889a688d8..730721dc176 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <handoff.h> #include <init.h> #include <log.h> diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 09d5da8c841..5f7701265a9 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_VIDEO -#include <common.h> #include <dm.h> #include <init.h> #include <log.h> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index fd4d98ef627..19f9f65b2e4 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <log.h> #include <asm/fsp/fsp_support.h> #include <asm/post.h> diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index df18f476756..ebf655a1143 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <dm.h> #include <errno.h> #include <init.h> diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index eee9ce54b1c..f3a8134a3f2 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <init.h> #include <asm/fsp/fsp_support.h> #include <asm/global_data.h> diff --git a/arch/x86/lib/fsp1/fsp_support.c b/arch/x86/lib/fsp1/fsp_support.c index d84c632f140..6e311a12d20 100644 --- a/arch/x86/lib/fsp1/fsp_support.c +++ b/arch/x86/lib/fsp1/fsp_support.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <log.h> #include <asm/fsp1/fsp_support.h> #include <asm/post.h> diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c index d802a86967d..45a274c0512 100644 --- a/arch/x86/lib/fsp2/fsp_common.c +++ b/arch/x86/lib/fsp2/fsp_common.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <init.h> #include <asm/fsp/fsp_support.h> diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index a1432239cfc..83c6d7bcc93 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <handoff.h> #include <init.h> #include <log.h> diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index aadc08cf3c4..ecbadaae75c 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <binman.h> #include <binman_sym.h> #include <bootstage.h> diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index 022e2cb64e5..f4817830cc2 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -6,7 +6,6 @@ * Mostly taken from coreboot fsp2_0/memory_init.c */ -#include <common.h> #include <binman.h> #include <bootstage.h> #include <dm.h> diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c index a96d2b183f6..16d30c25a57 100644 --- a/arch/x86/lib/fsp2/fsp_silicon_init.c +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_NORTHBRIDGE -#include <common.h> #include <binman.h> #include <bootstage.h> #include <dm.h> diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c index b2c76582453..808f0eb9d29 100644 --- a/arch/x86/lib/fsp2/fsp_support.c +++ b/arch/x86/lib/fsp2/fsp_support.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <init.h> #include <log.h> diff --git a/arch/x86/lib/hob.c b/arch/x86/lib/hob.c index b35248e5fde..46e83aa395a 100644 --- a/arch/x86/lib/hob.c +++ b/arch/x86/lib/hob.c @@ -4,7 +4,6 @@ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <asm/hob.h> /** diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c index a8d1db188ec..8a590c6191f 100644 --- a/arch/x86/lib/i8254.c +++ b/arch/x86/lib/i8254.c @@ -4,10 +4,10 @@ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> */ -#include <common.h> #include <asm/io.h> #include <asm/i8254.h> #include <asm/ibmpc.h> +#include <linux/errno.h> #define TIMER1_VALUE 18 /* 15.6us */ #define BEEP_FREQUENCY_HZ 440 diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c index a0e3c092573..465ff70146f 100644 --- a/arch/x86/lib/i8259.c +++ b/arch/x86/lib/i8259.c @@ -13,7 +13,6 @@ * Programmable Interrupt Controllers. */ -#include <common.h> #include <log.h> #include <asm/io.h> #include <asm/i8259.h> diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index bf0c921577d..bd0efde00c1 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -4,11 +4,11 @@ * Graeme Russ, <graeme.russ@gmail.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <linux/errno.h> #include <asm/mtrr.h> +#include <asm/u-boot-x86.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index ff52959ed28..f96b2bfd70e 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -29,7 +29,6 @@ * Daniel Engström */ -#include <common.h> #include <command.h> #include <irq_func.h> #include <asm/interrupt.h> diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index 67b931d3b28..4f89db4e538 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> UCLASS_DRIVER(lpc) = { diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 8e97d9ff36d..5abd9288c2a 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -5,7 +5,6 @@ * Adapted from coreboot src/arch/x86/boot/mpspec.c */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <errno.h> diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 6494b8d2634..970704a8dd6 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY UCLASS_RAM -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c index 38388872484..1d1780535a2 100644 --- a/arch/x86/lib/northbridge-uclass.c +++ b/arch/x86/lib/northbridge-uclass.c @@ -4,7 +4,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <dm.h> #include <dm/root.h> diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index 382f768149f..48cd1073c15 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -8,7 +8,6 @@ * Software Foundation. */ -#include <common.h> #include <log.h> #include <physmem.h> #include <asm/cpu.h> diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index c93f245845d..d4f71c562f8 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index caeaec9287f..5178940901c 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -5,7 +5,6 @@ * Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c */ -#include <common.h> #include <log.h> #include <pci.h> #include <asm/global_data.h> diff --git a/arch/x86/lib/pmu.c b/arch/x86/lib/pmu.c index 083aec8d8dd..2127257cd43 100644 --- a/arch/x86/lib/pmu.c +++ b/arch/x86/lib/pmu.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2017 Intel Corporation */ -#include <common.h> #include <dm.h> #include <regmap.h> #include <syscon.h> diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c index 03385396325..16cd6e49437 100644 --- a/arch/x86/lib/ramtest.c +++ b/arch/x86/lib/ramtest.c @@ -5,9 +5,9 @@ * From Coreboot src/lib/ramtest.c */ -#include <common.h> #include <asm/io.h> #include <asm/post.h> +#include <vsprintf.h> static void write_phys(unsigned long addr, u32 value) { diff --git a/arch/x86/lib/reloc_ia32_efi.c b/arch/x86/lib/reloc_ia32_efi.c index d56cd50bd93..17ab54dc246 100644 --- a/arch/x86/lib/reloc_ia32_efi.c +++ b/arch/x86/lib/reloc_ia32_efi.c @@ -7,7 +7,6 @@ * All rights reserved. */ -#include <common.h> #include <efi.h> #include <elf.h> diff --git a/arch/x86/lib/reloc_x86_64_efi.c b/arch/x86/lib/reloc_x86_64_efi.c index 2694de71104..c7a21d9393d 100644 --- a/arch/x86/lib/reloc_x86_64_efi.c +++ b/arch/x86/lib/reloc_x86_64_efi.c @@ -9,7 +9,6 @@ * All rights reserved. */ -#include <common.h> #include <efi.h> #include <elf.h> diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index da819b9bdd2..9ce56062d24 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -14,7 +14,6 @@ * Marius Groeger <mgroeger@sysgo.de> */ -#include <common.h> #include <log.h> #include <relocate.h> #include <asm/global_data.h> diff --git a/arch/x86/lib/scu.c b/arch/x86/lib/scu.c index 90ef239bcd3..02fed601fb6 100644 --- a/arch/x86/lib/scu.c +++ b/arch/x86/lib/scu.c @@ -9,7 +9,6 @@ * * This driver enables IPC channel to SCU. */ -#include <common.h> #include <dm.h> #include <regmap.h> #include <syscon.h> diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 85e963b634b..04d97327a4d 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -12,7 +12,6 @@ * See https://simplefirmware.org/ for details */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <asm/cpu.h> diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index c15f11f8cdf..f761fbc8bc3 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include <common.h> #include <cpu_func.h> #include <debug_uart.h> #include <dm.h> @@ -29,6 +28,7 @@ #include <asm/processor.h> #include <asm/qemu.h> #include <asm/spl.h> +#include <asm/u-boot-x86.h> #include <asm-generic/sections.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 1095dc92c5a..45a70e92763 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <bloblist.h> #include <log.h> #include <malloc.h> diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 273e9c8e1ca..7c03dea0711 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include <common.h> #include <debug_uart.h> #include <dm.h> #include <hang.h> diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index d7403876c13..73a21bc8f03 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -14,7 +14,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include <common.h> #include <bootm.h> #include <command.h> #include <env.h> diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index 98d9753b7e3..abcd8f7984f 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -8,7 +8,7 @@ * CPU specific code */ -#include <common.h> +#include <config.h> #include <command.h> #include <init.h> #include <vsprintf.h> diff --git a/arch/xtensa/cpu/exceptions.c b/arch/xtensa/cpu/exceptions.c index cf9af4326a2..206767094e9 100644 --- a/arch/xtensa/cpu/exceptions.c +++ b/arch/xtensa/cpu/exceptions.c @@ -10,12 +10,12 @@ * (Note that alloca is a special case and handled in start.S) */ -#include <common.h> #include <command.h> #include <irq_func.h> #include <asm/ptrace.h> #include <asm/string.h> #include <asm/regs.h> +#include <vsprintf.h> typedef void (*handler_t)(struct pt_regs *); diff --git a/arch/xtensa/include/asm/global_data.h b/arch/xtensa/include/asm/global_data.h index 1157978ab68..40c129db4ac 100644 --- a/arch/xtensa/include/asm/global_data.h +++ b/arch/xtensa/include/asm/global_data.h @@ -6,6 +6,8 @@ #ifndef _XTENSA_GBL_DATA_H #define _XTENSA_GBL_DATA_H +#include <asm/u-boot.h> + /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 9780d46e9b8..1de06b7fb53 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -4,7 +4,6 @@ * (C) Copyright 2014 Cadence Design Systems Inc. */ -#include <common.h> #include <bootm.h> #include <bootstage.h> #include <command.h> diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c index 4e0c0acc3bb..e6a7f6827fc 100644 --- a/arch/xtensa/lib/cache.c +++ b/arch/xtensa/lib/cache.c @@ -4,7 +4,6 @@ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. */ -#include <common.h> #include <cpu_func.h> #include <asm/cache.h> diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index 1c927d2a6a3..c6739584bbf 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -3,7 +3,6 @@ * (C) Copyright 2008 - 2013 Tensilica Inc. */ -#include <common.h> #include <clock_legacy.h> #include <time.h> #include <asm/global_data.h> |