diff options
Diffstat (limited to 'arch')
34 files changed, 2175 insertions, 467 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 13be6b6195c..3243bd0ee01 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1860,11 +1860,6 @@ config TARGET_TEN64 Support for Traverse Technologies Ten64 board, based on NXP LS1088A. -config TARGET_COLIBRI_PXA270 - bool "Support colibri_pxa270" - select CPU_PXA27X - select GPIO_EXTRA_HEADER - config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select BOARD_LATE_INIT @@ -2328,7 +2323,6 @@ source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/toradex/colibri_pxa270/Kconfig" source "board/traverse/ten64/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e7b95d74e8b..1032ce4c856 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -899,7 +899,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ - fsl-imx8qxp-apalis.dtb \ fsl-imx8qxp-mek.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb @@ -939,6 +938,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-venice.dtb \ + imx8mp-venice-gw74xx.dtb \ imx8mp-verdin.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb diff --git a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi deleted file mode 100644 index e41911a04aa..00000000000 --- a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&{/imx8qx-pm} { - - u-boot,dm-pre-proper; -}; - -&mu { - u-boot,dm-pre-proper; -}; - -&clk { - u-boot,dm-pre-proper; -}; - -&iomuxc { - u-boot,dm-pre-proper; -}; - -&pd_lsio { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio0 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio1 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio2 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio3 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio4 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio5 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio6 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio7 { - u-boot,dm-pre-proper; -}; - -&pd_dma { - u-boot,dm-pre-proper; -}; - -&pd_dma_lpuart0 { - u-boot,dm-pre-proper; -}; - -&pd_dma_lpuart3 { - u-boot,dm-pre-proper; -}; - -&pd_conn { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch0 { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch1 { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch2 { - u-boot,dm-pre-proper; -}; - -&pd_conn_enet0 { - u-boot,dm-pre-proper; -}; - -&gpio0 { - u-boot,dm-pre-proper; -}; - -&gpio1 { - u-boot,dm-pre-proper; -}; - -&gpio2 { - u-boot,dm-pre-proper; -}; - -&gpio3 { - u-boot,dm-pre-proper; -}; - -&gpio4 { - u-boot,dm-pre-proper; -}; - -&gpio5 { - u-boot,dm-pre-proper; -}; - -&gpio6 { - u-boot,dm-pre-proper; -}; - -&gpio7 { - u-boot,dm-pre-proper; -}; - -&lpuart3 { - u-boot,dm-pre-proper; -}; - -&lpuart0 { - u-boot,dm-pre-proper; -}; - -&usdhc1 { - u-boot,dm-pre-proper; - /delete-property/ assigned-clock-parents; -}; - -&usdhc2 { - u-boot,dm-pre-proper; - /delete-property/ assigned-clock-parents; -}; diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts deleted file mode 100644 index 9cb3d3a809b..00000000000 --- a/arch/arm/dts/fsl-imx8qxp-apalis.dts +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-apalis-u-boot.dtsi" - -/ { - model = "Toradex Apalis iMX8X"; - compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; - - chosen { - bootargs = "console=ttyLP1,115200"; - stdout-path = &lpuart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>; - - apalis-imx8x { - /* Apalis UART1 */ - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */ - SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */ - >; - }; - - /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 - /* On-module ETH_RESET# */ - SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020 - /* On-module ETH_INT# */ - SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 - >; - }; - - /* Apalis BKL_ON */ - pinctrl_gpio_bkl_on: gpio-bkl-on { - fsl,pins = < - SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - /* Apalis USBO1_EN */ - SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */ - >; - }; - - /* Apalis RESET_MOCI# */ - pinctrl_reset_moci: gpioresetmocigrp { - fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21 - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Apalis MMC1_CD# */ - pinctrl_usdhc2_gpio: mmc1gpiogrp { - fsl,pins = < - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { - fsl,pins = < - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */ - >; - }; - - /* Apalis USBH_EN */ - pinctrl_usbh_en: usbhen { - fsl,pins = < - SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */ - >; - }; - - /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */ - SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - }; -}; - -/* Apalis Gigabit LAN */ -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-post-delay = <150>; - phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - }; - }; -}; - -/* Apalis UART1 */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Apalis MMC1 */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi index f5d52c2fe25..b3592331c72 100644 --- a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi @@ -3,3 +3,49 @@ * Copyright 2021 Gateworks Corporation */ #include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + pci_usb_sel { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + dio_1 { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; +}; + +&gpio4 { + dio_2 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "dio2"; + }; + + dio_3 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "dio3"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi index f5d52c2fe25..92e44d4ba96 100644 --- a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi @@ -3,3 +3,84 @@ * Copyright 2021 Gateworks Corporation */ #include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + rs485_term { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + mipi_gpio4 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + dio_1 { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; +}; + +&gpio4 { + rs485_en { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + mipi_gpio3 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + rs485_half { + gpio-hog; + output-low; + gpios = <2 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; + + mipi_gpio2 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; + + mipi_gpio1 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi index f5d52c2fe25..92e44d4ba96 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi @@ -3,3 +3,84 @@ * Copyright 2021 Gateworks Corporation */ #include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + rs485_term { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + mipi_gpio4 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + dio_1 { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; +}; + +&gpio4 { + rs485_en { + gpio-hog; + output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + mipi_gpio3 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + rs485_half { + gpio-hog; + output-low; + gpios = <2 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; + + mipi_gpio2 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; + + mipi_gpio1 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index a801ee1deb9..11c773bb70d 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -5,6 +5,124 @@ #include "imx8mm-venice-u-boot.dtsi" +&gpio1 { + uart1_rs422 { + gpio-hog; + output-high; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs422#"; + }; + + uart1rs485 { + gpio-hog; + output-high; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs485#"; + }; + + uart1rs232 { + gpio-hog; + output-high; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs232#"; + }; + + dig1in { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "dig1_in"; + }; + + dig1out { + gpio-hog; + output-low; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "dig1_out"; + }; +}; + +&gpio4 { + uart3_rs232 { + gpio-hog; + output-high; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "uart3_rs232#"; + }; + + uart3_rs422 { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "uart3_rs422#"; + }; + + uart3_rs485 { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "uart3_rs485#"; + }; + + uart4_rs485 { + gpio-hog; + output-high; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "uart4_rs485#"; + }; + + sim1det { + gpio-hog; + input; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "sim1_det"; + }; + + sim2det { + gpio-hog; + input; + gpios = <30 GPIO_ACTIVE_HIGH>; + line-name = "sim2_det"; + }; +}; + +&gpio5 { + dig2out { + gpio-hog; + output-low; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "dig2_out"; + }; + + dig2in { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "dig2_in"; + }; + + sim2sel { + gpio-hog; + output-low; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "sim2_sel"; + }; + + uart4_rs232 { + gpio-hog; + output-high; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "uart4_rs232#"; + }; + + uart4_rs422 { + gpio-hog; + output-high; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "uart4_rs422#"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index d0e5d6c5b63..f21e46b12dd 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -5,10 +5,160 @@ #include "imx8mm-venice-u-boot.dtsi" +&gpio1 { + m2rst { + gpio-hog; + output-low; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "m2_reset"; + }; + + m2wdis { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + line-name = "m2_wdis#"; + }; +}; + +&gpio2 { + uart2en { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "uart2_en#"; + }; +}; + +&gpio3 { + m2gdis { + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "m2_gdis#"; + }; + + m2off { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "m2_off#"; + }; +}; + +&gpio4 { + ampgpio3 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio3"; + }; + + ampgpio2 { + gpio-hog; + input; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio2"; + }; + + ampgpio1 { + gpio-hog; + input; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio1"; + }; + + ltrpwr { + gpio-hog; + output-low; + gpios = <16 GPIO_ACTIVE_HIGH>; + line-name = "lte_pwr#"; + }; + + lterst { + gpio-hog; + output-low; + gpios = <17 GPIO_ACTIVE_HIGH>; + line-name = "lte_rst"; + }; + + ampgpio4 { + gpio-hog; + input; + gpios = <20 GPIO_ACTIVE_HIGH>; + line-name = "amp_gpio4"; + }; + + appgpio1 { + gpio-hog; + input; + gpios = <21 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio1"; + }; + + uart1rs485 { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs485"; + }; + + uart1term { + gpio-hog; + output-low; + gpios = <25 GPIO_ACTIVE_HIGH>; + line-name = "uart1_term"; + }; + + uart1half { + gpio-hog; + output-low; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "uart1_half"; + }; + + appgpio2 { + gpio-hog; + input; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio2"; + }; + + mipigpio1 { + gpio-hog; + input; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; +}; + +&gpio5 { + mipigpio4 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + mipigpio3 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + mipigpio2 { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; - phy-reset-post-delay = <1>; + phy-reset-post-delay = <300>; }; &pinctrl_fec1 { diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index adf521632d6..b0404ec4c8a 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -243,10 +243,14 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + /* TI DP83867 props */ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + /* GPY111 props */ + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2500>; }; }; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi index 36a605468b2..896e5d4edde 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi @@ -5,6 +5,89 @@ #include "imx8mm-venice-u-boot.dtsi" +&gpio1 { + rs422en { + gpio-hog; + output-high; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "rs422_en#"; + }; + + rs485en { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en#"; + }; + + rs232en { + gpio-hog; + output-low; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "rs232_en#"; + }; +}; + +&gpio2 { + dig2in { + gpio-hog; + input; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "dig2_in"; + }; + + dig2out { + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "dig2_out#"; + }; + + dig1out { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "dig1_out#"; + }; + + dig1in { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "dig1_in"; + }; +}; + +&gpio5 { + sim1det { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_LOW>; + line-name = "sim1_det#"; + }; + + sim2det { + gpio-hog; + input; + gpios = <8 GPIO_ACTIVE_LOW>; + line-name = "sim2_det#"; + }; + + sim2sel { + gpio-hog; + output-low; + gpios = <9 GPIO_ACTIVE_HIGH>; + line-name = "sim2_sel"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi index 42b2903f040..c61c6de935f 100644 --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi @@ -57,6 +57,10 @@ u-boot,dm-spl; }; +&gsc { + u-boot,dm-spl; +}; + &i2c2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts index 54505a03c6f..39b030691e5 100644 --- a/arch/arm/dts/imx8mm-venice.dts +++ b/arch/arm/dts/imx8mm-venice.dts @@ -27,6 +27,13 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + eeprom@51 { compatible = "atmel,24c02"; reg = <0x51>; diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi index b334b56b82a..17e6828c79f 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi @@ -5,10 +5,118 @@ #include "imx8mn-venice-u-boot.dtsi" +&gpio1 { + m2rst { + gpio-hog; + output-low; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "m2_reset"; + }; + + m2wdis { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + line-name = "m2_wdis#"; + }; +}; + +&gpio2 { + uart2en { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "uart2_en#"; + }; +}; + +&gpio3 { + m2gdis { + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "m2_gdis#"; + }; + + m2off { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "m2_off#"; + }; +}; + +&gpio4 { + appgpio1 { + gpio-hog; + input; + gpios = <21 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio1"; + }; + + uart1rs485 { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "uart1_rs485"; + }; + + uart1term { + gpio-hog; + output-low; + gpios = <25 GPIO_ACTIVE_HIGH>; + line-name = "uart1_term"; + }; + + uart1half { + gpio-hog; + output-low; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "uart1_half"; + }; + + appgpio2 { + gpio-hog; + input; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "app_gpio2"; + }; + + mipigpio1 { + gpio-hog; + input; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; +}; + +&gpio5 { + mipigpio4 { + gpio-hog; + input; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + mipigpio3 { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + mipigpio2 { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; +}; + &fec1 { phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; - phy-reset-post-delay = <1>; + phy-reset-post-delay = <300>; }; &pinctrl_fec1 { diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index 29897c161b9..d026d965580 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -242,10 +242,14 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + /* TI DP83867 props */ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + /* GPY111 props */ + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2500>; }; }; }; diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi index 055406e77b3..4f23da35676 100644 --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi @@ -94,6 +94,10 @@ u-boot,dm-spl; }; +&gsc { + u-boot,dm-spl; +}; + &i2c2 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts index e906a560581..eeae225632d 100644 --- a/arch/arm/dts/imx8mn-venice.dts +++ b/arch/arm/dts/imx8mn-venice.dts @@ -27,6 +27,13 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + eeprom@51 { compatible = "atmel,24c02"; reg = <0x51>; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index cfc352ae34a..20edd90cfad 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -99,8 +99,9 @@ fit { description = "Configuration to load ATF before U-Boot"; - #address-cells = <1>; fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,fdt-list = "of-list"; + #address-cells = <1>; images { uboot { @@ -129,7 +130,7 @@ }; }; - fdt { + @fdt-SEQ { description = "NAME"; type = "flat_dt"; compression = "none"; @@ -141,13 +142,13 @@ }; configurations { - default = "conf"; + default = "@config-DEFAULT-SEQ"; - conf { + @config-SEQ { description = "NAME"; + fdt = "fdt-SEQ"; firmware = "uboot"; loadables = "atf"; - fdt = "fdt"; }; }; }; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi new file mode 100644 index 00000000000..920246d577e --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + u-boot,dm-spl; + wdt = <&wdog1>; + }; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +ðphy0 { + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <300000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&gpio1 { + u-boot,dm-spl; + + dio0_hog { + gpio-hog; + input; + gpios = <9 GPIO_ACTIVE_LOW>; + line-name = "dio0"; + }; + + dio1_hog { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_LOW>; + line-name = "dio1"; + }; +}; + +&gpio2 { + u-boot,dm-spl; + + pcie1_wdis_hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie1_wdis#"; + }; + + pcie2_wdis_hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie2_wdis#"; + }; + + pcie3_wdis_hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie3_wdis#"; + }; +}; + +&gpio3 { + u-boot,dm-spl; + + m2_dis2_hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_gdis#"; + }; + + m2rst_hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_rst#"; + }; + + m2_off_hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_off#"; + }; +}; + +&gpio4 { + u-boot,dm-spl; + + m2_dis1_hog { + gpio-hog; + gpios = <18 GPIO_ACTIVE_LOW>; + output-high; + line-name = "m2_wdis#"; + }; + + uart_rs485_hog { + gpio-hog; + gpios = <31 GPIO_ACTIVE_LOW>; + output-low; + line-name = "uart_rs485"; + }; +}; + +&gpio5 { + u-boot,dm-spl; + + uart_half_hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "uart_half"; + }; + + uart_term_hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "uart_term"; + }; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; + +&usdhc2 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; + assigned-clock-rates = <400000000>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + sd-uhs-ddr50; + sd-uhs-sdr104; + u-boot,dm-spl; +}; + +&usdhc3 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; + assigned-clock-rates = <400000000>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts new file mode 100644 index 00000000000..ecb117a7a2a --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -0,0 +1,923 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +#include "imx8mp.dtsi" + +/ { + model = "Gateworks Venice GW74xx i.MX8MP board"; + compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + ethernet2 = &lan1; + ethernet3 = &lan2; + ethernet4 = &lan3; + ethernet5 = &lan4; + ethernet6 = &lan5; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + key-1 { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-2 { + label = "key_erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-3 { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-4 { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + key-5 { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb2_vbus"; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can>; + regulator-name = "can2_stby"; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wifi_en: regulator-wifi-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "dio0", "", "dio1", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "m2_gdis#", "", "", "", "", "", "", "m2_rst#", + "", "", "", "", "", "", "", "", + "m2_off#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "m2_wdis#", "", "", "", + "", "", "", "", "", "", "", "uart_rs485"; +}; + +&gpio5 { + gpio-line-names = + "uart_half", "uart_term", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_arm"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p2"; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; + + switch: switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + pinctrl-0 = <&pinctrl_ksz>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy0>; + phy-mode = "internal"; + }; + + lan2: port@1 { + reg = <1>; + label = "lan2"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy1>; + phy-mode = "internal"; + }; + + lan3: port@2 { + reg = <2>; + label = "lan3"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy2>; + phy-mode = "internal"; + }; + + lan4: port@3 { + reg = <3>; + label = "lan4"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy3>; + phy-mode = "internal"; + }; + + lan5: port@4 { + reg = <4>; + label = "lan5"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&sw_phy4>; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0>; + compatible = "microchip,ksz-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + }; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +/* GPS / off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RS232 console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - Type C front panel */ +&usb3_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ksz: kszgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 + MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 + >; + }; + + pinctrl_reg_can: regcangrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 + >; + }; + + pinctrl_reg_wifi: regwifigrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi new file mode 100644 index 00000000000..37f3edc9817 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&gsc { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts new file mode 100644 index 00000000000..6b1a7f1a89d --- /dev/null +++ b/arch/arm/dts/imx8mp-venice.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "Gateworks Venice i.MX8MP board"; + compatible = "gateworks,imx8mp-venice", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index f9d64253c8a..79b65750da9 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -434,6 +435,44 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; + }; + + pgc_usb1_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; + }; + + pgc_usb2_phy: power-domain@3 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; + }; + + pgc_hsiomix: power-domains@17 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + }; + }; + }; }; aips2: bus@30400000 { @@ -842,6 +881,28 @@ }; }; + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -865,17 +926,20 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; #phy-cells = <0>; status = "disabled"; }; usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10100 0x8>; + reg = <0x32f10100 0x8>, + <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -907,16 +971,20 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; #phy-cells = <0>; + status = "disabled"; }; usb3_1: usb@32f10108 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10108 0x8>; + reg = <0x32f10108 0x8>, + <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 6f9c81462ea..919c1f66d38 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -2,6 +2,34 @@ #include "imx8mq-u-boot.dtsi" +&{/soc@0} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30000000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30400000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@32c00000} { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + &usdhc1 { mmc-hs400-1_8v; }; @@ -10,3 +38,7 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&uart1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h deleted file mode 100644 index 7a833e564b5..00000000000 --- a/arch/arm/include/asm/arch-imx8m/power-domain.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2017 NXP - */ - -#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H -#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H - -struct imx8m_power_domain_plat { - int resource_id; - int has_pd; - struct power_domain pd; -}; - -#endif diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c49759af92d..7845fa8e569 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -18,9 +18,6 @@ #define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \ USBPHY_PWD_RXPWDRX)) -int imx6_pcie_toggle_power(void); -int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high); - enum ldo_reg { LDO_ARM, LDO_SOC, diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 9aa1d84336b..ad0fb365023 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -137,7 +137,7 @@ config CMD_NANDBCB config FSL_MFGPROT bool "Support the 'mfgprot' command" - depends on IMX_HAB && ARCH_MX7 + depends on IMX_HAB && (ARCH_MX7 || ARCH_IMX8M) help This option enables the manufacturing protection command which can be used has a protection feature for Manufacturing diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 77e72702bba..aa0b6447f14 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -38,8 +38,12 @@ ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +endif +ifeq ($(SOC),$(filter $(SOC),mx7 imx8m)) +ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif +endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index aed3b2f83da..ec8a8756f7f 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -12,13 +12,11 @@ #include <linux/compiler.h> #include <command.h> #include <common.h> -#include <environment.h> +#include <env.h> #include <fsl_sec.h> #include <mapmem.h> #include <memalign.h> -DECLARE_GLOBAL_DATA_PTR; - /** * do_mfgprot() - Handle the "mfgprot" command-line command * @cmdtp: Command data struct pointer diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index f969833baba..5e1b20a4229 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -54,11 +54,6 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP -config TARGET_APALIS_IMX8X - bool "Support Apalis iMX8X module" - select BOARD_LATE_INIT - select IMX8QXP - config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT @@ -105,7 +100,6 @@ source "board/congatec/cgtqmx8/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" -source "board/toradex/apalis-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" config IMX_SNVS_SEC_SC diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 55db25062a9..24299ae037f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -97,6 +97,8 @@ config TARGET_IMX8MM_VENICE select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select GATEWORKS_SC + select MISC config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" @@ -143,6 +145,8 @@ config TARGET_IMX8MN_VENICE select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select GATEWORKS_SC + select MISC config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" @@ -154,6 +158,15 @@ config TARGET_IMX8MP_EVK select ARCH_MISC_INIT select SPL_CRYPTO if SPL +config TARGET_IMX8MP_VENICE + bool "Support Gateworks Venice iMX8M Plus module" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + select GATEWORKS_SC + select MISC + config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" select BINMAN diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7059d87e336..8e23e6da326 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -331,7 +331,7 @@ phys_size_t get_effective_memsize(void) ulong board_get_usable_ram_top(ulong total_size) { - ulong top_addr = PHYS_SDRAM + gd->ram_size; + ulong top_addr; /* * Some IPs have their accessible address space restricted by @@ -339,8 +339,7 @@ ulong board_get_usable_ram_top(ulong total_size) * space below the 4G address boundary (which is 3GiB big), * even when the effective available memory is bigger. */ - if (top_addr > 0x80000000) - top_addr = 0x80000000; + top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff); /* * rom_pointer[0] stores the TEE memory start address. diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 3e71a4f6c3b..3e88f4633c2 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -440,10 +440,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) { diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3d675fcd73e..947b73fab29 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -227,6 +227,8 @@ config TARGET_GW_VENTANA bool "gw_ventana" depends on MX6QDL select SUPPORT_SPL + select GATEWORKS_SC + select MISC imply CMD_SATA imply CMD_SPL |