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-rw-r--r--arch/arm/Kconfig10
-rw-r--r--arch/arm/dts/omap5-u-boot.dtsi4
-rw-r--r--arch/arm/mach-rmobile/cpu_info.c4
-rw-r--r--arch/arm/mach-rmobile/memmap-gen3.c24
-rw-r--r--arch/sandbox/dts/test.dts6
-rw-r--r--arch/x86/Kconfig11
-rw-r--r--arch/x86/cpu/Makefile2
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c3
-rw-r--r--arch/x86/cpu/efi/payload.c3
-rw-r--r--arch/x86/cpu/i386/interrupt.c2
-rw-r--r--arch/x86/include/asm/arch-tangier/acpi/platform.asl13
-rw-r--r--arch/x86/include/asm/arch-tangier/acpi/southcluster.asl12
-rw-r--r--arch/x86/lib/interrupts.c16
13 files changed, 82 insertions, 28 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13ba774a484..cb7ec580796 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -817,15 +817,11 @@ config ARCH_SOCFPGA
select SPL_DM_RESET if DM_RESET
select SPL_DM_SERIAL
select SPL_LIBCOMMON_SUPPORT
- select SPL_LIBDISK_SUPPORT
select SPL_LIBGENERIC_SUPPORT
- select SPL_MMC_SUPPORT if DM_MMC
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
- select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
- select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_NS16550
@@ -836,8 +832,12 @@ config ARCH_SOCFPGA
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_MMC_SUPPORT
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ imply SPL_SPI_FLASH_SUPPORT
+ imply SPL_SPI_SUPPORT
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
@@ -932,6 +932,7 @@ config ARCH_ZYNQMP_R5
select DM_SERIAL
select OF_CONTROL
imply CMD_DM
+ imply DM_USB_GADGET
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
@@ -949,6 +950,7 @@ config ARCH_ZYNQMP
imply CMD_DM
imply FAT_WRITE
imply MP
+ imply DM_USB_GADGET
config TEGRA
bool "NVIDIA Tegra"
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 30833a3cc90..1eb50cd4381 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -15,6 +15,10 @@
ocp {
u-boot,dm-spl;
+ ocp2scp@4a080000 {
+ compatible = "ti,omap-ocp2scp", "simple-bus";
+ };
+
ocp2scp@4a090000 {
compatible = "ti,omap-ocp2scp", "simple-bus";
};
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 65a9ca8c013..aa5be52dfd7 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -7,8 +7,6 @@
#include <asm/io.h>
#include <linux/ctype.h>
-/* R-Car Gen3 caches are enabled in memmap-gen3.c */
-#ifndef CONFIG_RCAR_GEN3
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
@@ -17,6 +15,8 @@ int arch_cpu_init(void)
}
#endif
+/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
+#ifndef CONFIG_RCAR_GEN3
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c
index 7e29ccc351b..1a9eb72bb97 100644
--- a/arch/arm/mach-rmobile/memmap-gen3.c
+++ b/arch/arm/mach-rmobile/memmap-gen3.c
@@ -21,7 +21,13 @@ static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
}, {
.virt = 0x40000000UL,
.phys = 0x40000000UL,
- .size = 0x80000000UL,
+ .size = 0x03F00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E00000UL,
+ .phys = 0x47E00000UL,
+ .size = 0x78200000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -76,8 +82,16 @@ void enable_caches(void)
/* Mark memory reserved by ATF as cacheable too. */
if (start == 0x48000000) {
- start = 0x40000000ULL;
- size += 0x08000000ULL;
+ /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
+ gen3_mem_map[i].virt = 0x40000000ULL;
+ gen3_mem_map[i].phys = 0x40000000ULL;
+ gen3_mem_map[i].size = 0x03F00000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+
+ start = 0x47E00000ULL;
+ size += 0x00200000ULL;
}
gen3_mem_map[i].virt = start;
@@ -126,6 +140,8 @@ void enable_caches(void)
gen3_mem_map[i].attrs = 0;
}
- icache_enable();
+ if (!icache_status())
+ icache_enable();
+
dcache_enable();
}
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 082fcec3f9e..6b1c2692baa 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -460,6 +460,8 @@
test4 {
compatible = "denx,u-boot-probe-test";
+ first-syscon = <&syscon0>;
+ second-sys-ctrl = <&another_system_controller>;
};
};
@@ -540,12 +542,12 @@
};
};
- syscon@0 {
+ syscon0: syscon@0 {
compatible = "sandbox,syscon0";
reg = <0x10 16>;
};
- syscon@1 {
+ another_system_controller: syscon@1 {
compatible = "sandbox,syscon1";
reg = <0x20 5
0x28 6
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a1c18d26e1d..e0520937751 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -729,13 +729,22 @@ config PCIE_ECAM_SIZE
maximum number of PCI buses as defined by the PCI specification.
config I8259_PIC
- bool
+ bool "Enable Intel 8259 compatible interrupt controller"
default y
help
Intel 8259 ISA compatible chipset incorporates two 8259 (master and
slave) interrupt controllers. Include this to have U-Boot set up
the interrupt correctly.
+config APIC
+ bool "Enable Intel Advanced Programmable Interrupt Controller"
+ default y
+ help
+ The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
+ for catching interrupts and distributing them to one or more CPU
+ cores. In most cases there are some LAPICs (local) for each core and
+ one I/O APIC. This conjunction is found on most modern x86 systems.
+
config PINCTRL_ICH6
bool
help
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index f862d8c071e..54668aab240 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-$(CONFIG_INTEL_TANGIER) += tangier/
-obj-y += lapic.o ioapic.o
+obj-$(CONFIG_APIC) += lapic.o ioapic.o
obj-y += irq.o
ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index aaf0d071924..4c6ed0bfb28 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -77,7 +77,8 @@ int last_stage_init(void)
timestamp_add_to_bootstage();
/* start usb so that usb keyboard can be used as input device */
- usb_init();
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
board_final_cleanup();
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index c323c7b19a5..225aef7bf6a 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -166,7 +166,8 @@ int reserve_arch(void)
int last_stage_init(void)
{
/* start usb so that usb keyboard can be used as input device */
- usb_init();
+ if (CONFIG_IS_ENABLED(USB_KEYBOARD))
+ usb_init();
return 0;
}
diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index ed8423e0799..1ea415b876d 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -264,7 +264,9 @@ int interrupt_init(void)
i8259_init();
#endif
+#ifdef CONFIG_APIC
lapic_setup();
+#endif
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts();
diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
index 7abea4bb96e..353b879918a 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/platform.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
@@ -21,6 +21,19 @@ Method(_WAK, 1)
Return (Package() {0, 0})
}
+Scope (_SB)
+{
+ /* Real Time Clock */
+ Device (RTC0)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x70, 0x70, 0x01, 0x08)
+ })
+ }
+}
+
/* ACPI global NVS */
#include "global_nvs.asl"
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index 48193ba9570..e166e510cb7 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -295,16 +295,16 @@ Device (PCI0)
Method (_CRS, 0, Serialized)
{
- Name (RBUF, ResourceTemplate ()
+ Name (RBUF, ResourceTemplate()
{
- UartSerialBus (0x0001C200, DataBitsEight, StopBitsOne,
+ UartSerialBus(0x0001C200, DataBitsEight, StopBitsOne,
0xFC, LittleEndian, ParityTypeNone, FlowControlHardware,
0x20, 0x20, "\\_SB.PCI0.HSU0", 0, ResourceConsumer, , )
- GpioInt (Level, ActiveHigh, Exclusive, PullNone, 0,
+ GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 185 }
- GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 184 }
- GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+ GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 71 }
})
Return (RBUF)
@@ -328,7 +328,7 @@ Device (FLIS)
Name (_DDN, "Intel Merrifield Family-Level Interface Shim")
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000, )
+ Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000)
PinGroup("spi5", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 }
PinGroup("uart0", ResourceProducer, ) { 115, 116, 117, 118 }
PinGroup("uart1", ResourceProducer, ) { 119, 120, 121, 122 }
diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c
index 297067df710..39f8deaed13 100644
--- a/arch/x86/lib/interrupts.c
+++ b/arch/x86/lib/interrupts.c
@@ -64,7 +64,8 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
irq_handlers[irq].arg = arg;
irq_handlers[irq].count = 0;
- unmask_irq(irq);
+ if (CONFIG_IS_ENABLED(I8259_PIC))
+ unmask_irq(irq);
if (status)
enable_interrupts();
@@ -83,7 +84,8 @@ void irq_free_handler(int irq)
status = disable_interrupts();
- mask_irq(irq);
+ if (CONFIG_IS_ENABLED(I8259_PIC))
+ mask_irq(irq);
irq_handlers[irq].handler = NULL;
irq_handlers[irq].arg = NULL;
@@ -104,14 +106,16 @@ void do_irq(int hw_irq)
}
if (irq_handlers[irq].handler) {
- mask_irq(irq);
+ if (CONFIG_IS_ENABLED(I8259_PIC))
+ mask_irq(irq);
irq_handlers[irq].handler(irq_handlers[irq].arg);
irq_handlers[irq].count++;
- unmask_irq(irq);
- specific_eoi(irq);
-
+ if (CONFIG_IS_ENABLED(I8259_PIC)) {
+ unmask_irq(irq);
+ specific_eoi(irq);
+ }
} else {
if ((irq & 7) != 7) {
spurious_irq_cnt++;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 00:44:12 +0000