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-rw-r--r--arch/arm/config.mk4
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c12
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c2
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h23
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware_am43xx.h3
-rw-r--r--arch/arm/include/asm/arch-am33xx/omap.h2
-rw-r--r--arch/arm/include/asm/emif.h15
-rw-r--r--arch/blackfin/include/asm/config-pre.h3
-rw-r--r--arch/blackfin/lib/cache.c10
-rw-r--r--arch/m68k/cpu/mcf523x/cpu_init.c39
-rw-r--r--arch/m68k/cpu/mcf5445x/speed.c2
-rw-r--r--arch/powerpc/cpu/mpc824x/start.S3
-rw-r--r--arch/powerpc/cpu/mpc8xx/cpu.c8
-rw-r--r--arch/powerpc/cpu/mpc8xx/cpu_init.c6
-rw-r--r--arch/powerpc/cpu/mpc8xx/fec.c46
-rw-r--r--arch/powerpc/cpu/mpc8xx/scc.c34
-rw-r--r--arch/powerpc/cpu/mpc8xx/serial.c14
-rw-r--r--arch/powerpc/cpu/mpc8xx/video.c48
-rw-r--r--arch/powerpc/cpu/ppc4xx/speed.c2
-rw-r--r--arch/sandbox/include/asm/sound.h (renamed from arch/sandbox/include/asm/arch-sandbox/sound.h)0
20 files changed, 92 insertions, 184 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 66ecc2ee4d1..5fa182536d7 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -116,6 +116,10 @@ else
OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
endif
+ifdef CONFIG_OF_EMBED
+OBJCOPYFLAGS += -j .dtb.init.rodata
+endif
+
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index bbe9d1a8dea..fc66872a317 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -94,6 +94,18 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->emif_rd_wr_exec_thresh,
&emif_reg[nr]->emif_rd_wr_exec_thresh);
+ /*
+ * for most SOCs these registers won't need to be changed so only
+ * write to these registers if someone explicitly has set the
+ * register's value.
+ */
+ if(regs->emif_cos_config) {
+ writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+ writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+ writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+ writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+ }
+
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index a7a3e88cd75..8b7527c5b40 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -115,7 +115,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
- while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+ while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
writel(0x80000000, &ddrctrl->ddrioctrl);
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index aa10fab4dd8..8dd69b3c80e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -489,6 +489,12 @@ struct ctrl_stat {
#define OMAP_GPIO_SETDATAOUT 0x0194
/* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
+
struct ctrl_dev {
unsigned int deviceid; /* offset 0x00 */
unsigned int resv1[7];
@@ -502,10 +508,25 @@ struct ctrl_dev {
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
- unsigned int resv5[106];
+ unsigned int resv5[7];
+ unsigned int mreqprio_0; /* offset 0x70 */
+ unsigned int mreqprio_1; /* offset 0x74 */
+ unsigned int resv6[97];
unsigned int efuse_sma; /* offset 0x1FC */
};
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+ u32 padding0[2];
+ u32 modena_init0_bw_fractional;
+ u32 modena_init0_bw_integer;
+ u32 modena_init0_watermark_0;
+};
+
/* gmii_sel register defines */
#define GMII1_SEL_MII 0x0
#define GMII1_SEL_RMII 0x1
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 15399dcc747..b4703192499 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -13,6 +13,9 @@
/* Module base addresses */
+/* L3 Fast Configuration Bandwidth Limiter Base Address */
+#define L3F_CFG_BWLIMITER 0x44005200
+
/* UART Base Address */
#define UART0_BASE 0x44E09000
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 0855d16ce54..e5c0b0d08ff 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -29,6 +29,8 @@
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD
+#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14
#define QSPI_BASE 0x47900000
#endif
#endif
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 45668ca4dd7..b8d6bdca9b1 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -642,11 +642,16 @@ struct emif_reg_struct {
u32 emif_ddr_phy_ctrl_1;
u32 emif_ddr_phy_ctrl_1_shdw;
u32 emif_ddr_phy_ctrl_2;
- u32 padding7[12];
+ u32 padding7[4];
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 padding8[5];
u32 emif_rd_wr_exec_thresh;
- u32 padding8[7];
+ u32 emif_cos_config;
+ u32 padding9[6];
u32 emif_ddr_phy_status[21];
- u32 padding9[27];
+ u32 padding10[27];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@@ -1137,6 +1142,10 @@ struct emif_regs {
u32 emif_rd_wr_lvl_rmp_ctl;
u32 emif_rd_wr_lvl_ctl;
u32 emif_rd_wr_exec_thresh;
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 emif_cos_config;
};
struct lpddr2_mr_regs {
diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h
index d0fd537d88d..2d8b293c3ea 100644
--- a/arch/blackfin/include/asm/config-pre.h
+++ b/arch/blackfin/include/asm/config-pre.h
@@ -9,9 +9,6 @@
#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
#define __ASM_BLACKFIN_CONFIG_PRE_H__
-/* Misc helper functions */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
* Depending on your cpu, some of these may not be valid, check your HRM.
* The actual values here are meaningless as long as they're unique.
diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c
index 0a321a448f4..e8a0cb5deb2 100644
--- a/arch/blackfin/lib/cache.c
+++ b/arch/blackfin/lib/cache.c
@@ -111,3 +111,13 @@ int dcache_status(void)
{
return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ blackfin_dcache_flush_range((const void *)start, (const void *)stop);
+}
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 5a789540fc9..af1fd560688 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -20,6 +20,13 @@
#include <asm/fec.h>
#endif
+/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
+#ifdef CONFIG_M5235
+#define out_be_fbcs_reg out_be16
+#else
+#define out_be_fbcs_reg out_be32
+#endif
+
/*
* Breath some life into the CPU...
*
@@ -45,57 +52,57 @@ void cpu_init_f(void)
out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
- out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
- out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
- out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
- out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
- out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
- out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+ out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+ out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
- out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
- out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+ out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+ out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 07a9b359b5f..4e363a41900 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -115,7 +115,7 @@ void setup_5441x_clocks(void)
gd->cpu_clk = vco / temp; /* cpu clock */
gd->arch.flb_clk = vco / temp; /* FlexBus clock */
gd->arch.flb_clk >>= 1;
- if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
+ if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
gd->arch.flb_clk >>= 1;
temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
index b1fb062a08f..55238df4562 100644
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ b/arch/powerpc/cpu/mpc824x/start.S
@@ -56,9 +56,6 @@
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
-#if defined(CONFIG_FADS)
- GOT_ENTRY(environment)
-#endif
END_GOT
/*
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 5c96b5fe16e..eb4432f6d77 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -97,14 +97,8 @@ static int check_CPU (long clock, uint pvr, uint immr)
pre = 'M'; m = 1;
if (id_str == NULL)
id_str =
-# if defined(CONFIG_MPC852T)
- "PC852T";
-# elif defined(CONFIG_MPC859T)
+# if defined(CONFIG_MPC859T)
"PC859T";
-# elif defined(CONFIG_MPC859DSL)
- "PC859DSL";
-# elif defined(CONFIG_MPC866T)
- "PC866T";
# else
"PC866x"; /* Unknown chip from MPC866 family */
# endif
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 9c3102dc69f..e51fec7260a 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -138,8 +138,6 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
- defined(CONFIG_RPXLITE) || \
- defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
@@ -206,10 +204,6 @@ void cpu_init_f (volatile immap_t * immr)
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
-#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
- rpxlite_init ();
-#endif
-
#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
/* write config value */
immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 65dfeabba43..d12b3df4a15 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -377,26 +377,6 @@ static void fec_pin_init(int fecidx)
*/
immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
- {
- volatile fec_t *fecp;
-
- /*
- * only two FECs please
- */
- if ((unsigned int)fecidx >= 2)
- hang();
-
- if (fecidx == 0)
- fecp = &immr->im_cpm.cp_fec1;
- else
- fecp = &immr->im_cpm.cp_fec2;
-
- /* our PHYs are the limit at 2.5 MHz */
- fecp->fec_mii_speed <<= 1;
- }
-#endif
-
#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
/* use MDC for MII */
immr->im_ioport.iop_pdpar |= 0x0080;
@@ -562,32 +542,6 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
(volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
- if (efis->ether_index == 0) {
-#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
-#if defined(CONFIG_MPC885ADS)
- *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
-#else
- /* configure FADS for fast (FEC) ethernet, half-duplex */
- /* The LXT970 needs about 50ms to recover from reset, so
- * wait for it by discovering the PHY before leaving eth_init().
- */
- {
- volatile uint *bcsr4 = (volatile uint *) BCSR4;
-
- *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
- | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
- BCSR4_FETHRST);
-
- /* reset the LXT970 PHY */
- *bcsr4 &= ~BCSR4_FETHRST;
- udelay (10);
- *bcsr4 |= BCSR4_FETHRST;
- udelay (10);
- }
-#endif /* CONFIG_MPC885ADS */
-#endif /* CONFIG_FADS */
- }
-
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* the MII interface is connected to FEC1
* so for the miiphy_xxx function to work we must
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 5da697366de..01029ff68a2 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -197,19 +197,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
reset_phy();
#endif
-#ifdef CONFIG_FADS
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
- /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
- *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#else
- *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif
-#endif
-
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
@@ -461,20 +448,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
-#ifdef CONFIG_RPXLITE
- *((uchar *) BCSR0) |= BCSR0_ETHEN;
-#endif
-
-#if defined(CONFIG_QS860T)
- /*
- * PB27=FDE-, set output low for full duplex
- * PB26=Link Test Enable, normally high output
- */
- immr->im_cpm.cp_pbdir |= 0x00000030;
- immr->im_cpm.cp_pbdat |= 0x00000020;
- immr->im_cpm.cp_pbdat &= ~0x00000010;
-#endif /* QS860T */
-
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
@@ -502,13 +475,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
- /*
- * Work around transmit problem with first eth packet
- */
-#if defined (CONFIG_FADS)
- udelay (10000); /* wait 10 ms */
-#endif
-
return 1;
}
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
index 932141144ce..b1625fba16b 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/arch/powerpc/cpu/mpc8xx/serial.c
@@ -173,20 +173,6 @@ static int smc_init (void)
# endif
#endif
-#if defined(CONFIG_FADS)
- /* Enable RS232 */
-#if defined(CONFIG_8xx_CONS_SMC1)
- *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
-#else
- *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
-#endif
-#endif /* CONFIG_FADS */
-
-#if defined(CONFIG_RPXLITE)
- /* Enable Monitor Port Transceiver */
- *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
-#endif /* CONFIG_RPXLITE */
-
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c
index fc351585bef..2fd5b11fe40 100644
--- a/arch/powerpc/cpu/mpc8xx/video.c
+++ b/arch/powerpc/cpu/mpc8xx/video.c
@@ -798,22 +798,6 @@ static void video_encoder_init (void)
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
-#ifdef CONFIG_FADS
- /* Reset ADV7176 chip */
- debug ("[VIDEO ENCODER] Resetting encoder...\n");
- (*(int *) BCSR4) &= ~(1 << 21);
-
- /* Wait for 5 ms inside the reset */
- debug ("[VIDEO ENCODER] Waiting for encoder reset...\n");
- udelay (5000);
-
- /* Take ADV7176 out of reset */
- (*(int *) BCSR4) |= 1 << 21;
-
- /* Wait for 5 ms after the reset */
- udelay (5000);
-#endif /* CONFIG_FADS */
-
/* Send configuration */
#ifdef DEBUG
{
@@ -860,16 +844,6 @@ static void video_ctrl_init (void *memptr)
debug ("[VIDEO CTRL] Turning off video controller...\n");
SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0);
-#ifdef CONFIG_FADS
- /* Turn on Video Port LED */
- debug ("[VIDEO CTRL] Turning off video port led...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1);
-
- /* Disable internal clock */
- debug ("[VIDEO CTRL] Disabling internal clock...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0);
-#endif
-
/* Generate and make active a new video mode */
debug ("[VIDEO CTRL] Generating video mode...\n");
video_mode_generate ();
@@ -892,15 +866,6 @@ static void video_ctrl_init (void *memptr)
immap->im_ioport.iop_pdpar = 0x1fff;
immap->im_ioport.iop_pddir = 0x0000;
-#ifdef CONFIG_FADS
- /* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */
- debug ("[VIDEO CTRL] Turning on video clock...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1);
-
- /* Turn on Video Port LED */
- debug ("[VIDEO CTRL] Turning on video port led...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0);
-#endif
#ifdef CONFIG_RRVISION
debug ("PC5->Output(1): enable PAL clock");
immap->im_ioport.iop_pcpar &= ~(0x0400);
@@ -1153,9 +1118,7 @@ static void *video_logo (void)
{
u16 *screen = video_fb_address, width = VIDEO_COLS;
#ifdef VIDEO_INFO
-# ifndef CONFIG_FADS
char temp[32];
-# endif
char info[80];
#endif /* VIDEO_INFO */
@@ -1173,7 +1136,7 @@ static void *video_logo (void)
sprintf (info, " Wolfgang DENK, wd@denx.de");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
-#ifndef CONFIG_FADS /* all normal boards */
+
/* leave one blank line */
sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash",
@@ -1182,15 +1145,6 @@ static void *video_logo (void)
gd->bd->bi_flashsize >> 20 );
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4,
info);
-#else /* FADS :-( */
- sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board");
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
- info);
-
- sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM");
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
- info);
-#endif
#endif
return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN;
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 7e077d5a9f2..4baee7774c5 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -19,8 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define DEBUGF(fmt,args...)
#endif
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
#if defined(CONFIG_405GP)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
diff --git a/arch/sandbox/include/asm/arch-sandbox/sound.h b/arch/sandbox/include/asm/sound.h
index a32e8c802d7..a32e8c802d7 100644
--- a/arch/sandbox/include/asm/arch-sandbox/sound.h
+++ b/arch/sandbox/include/asm/sound.h
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 11:53:05 +0000