diff options
Diffstat (limited to 'arch')
31 files changed, 342 insertions, 284 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index ef1f45650f3..c496e643919 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,7 +7,6 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008997 if USB - select SYS_FSL_ERRATUM_A009007 if USB select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009798 if USB diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4d4469c8843..09f3f50fa22 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -90,6 +90,7 @@ config SPL_RECOVER_DATA_SECTION config SEC_FIRMWARE_ARMV8_PSCI bool "PSCI implementation in secure monitor firmware" depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT + depends on ARMV8_PSCI=n help This config enables the ARMv8 PSCI implementation in secure monitor firmware. This is a private PSCI implementation and different from @@ -131,6 +132,9 @@ config PSCI_RESET Select Y here to make use of PSCI calls for system reset +config SYS_HAS_ARMV8_SECURE_BASE + bool + config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help @@ -158,23 +162,27 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. -config ARMV8_EA_EL3_FIRST - bool "External aborts and SError interrupt exception are taken in EL3" +config ARMV8_PSCI_RELOCATE + bool "Relocate PSCI code" + depends on ARMV8_PSCI + depends on SYS_HAS_ARMV8_SECURE_BASE help - Exception handling at all exception levels for External Abort and - SError interrupt exception are taken in EL3. - -if SYS_HAS_ARMV8_SECURE_BASE + Relocate PSCI code, for example to a secure memory on the SoC. If not + set, the PSCI sections are placed together with the u-boot and the + regions will be marked as reserved before linux is started. config ARMV8_SECURE_BASE hex "Secure address for PSCI image" - depends on ARMV8_PSCI + depends on ARMV8_PSCI_RELOCATE + default 0x18000000 if ARCH_LS1028A help Address for placing the PSCI text, data and stack sections. - If not defined, the PSCI sections are placed together with the u-boot - but platform can choose to place PSCI code image separately in other - places such as some secure RAM built-in SOC etc. -endif + +config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. endif diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 61c38b17cbf..9bfe3815e51 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -8,9 +8,9 @@ #include <asm/psci.h> #include <asm/system.h> #include <asm/armv8/sec_firmware.h> +#include <linux/libfdt.h> -#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) -int psci_update_dt(void *fdt) +__weak int psci_update_dt(void *fdt) { /* * If the PSCI in SEC Firmware didn't work, avoid to update the @@ -18,8 +18,10 @@ int psci_update_dt(void *fdt) * number to support detecting PSCI dynamically and then switching * the SMP boot method between PSCI and spin-table. */ - if (sec_firmware_support_psci_version() == PSCI_INVALID_VER) + if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) && + sec_firmware_support_psci_version() == PSCI_INVALID_VER) return 0; + fdt_psci(fdt); #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE) @@ -30,4 +32,3 @@ int psci_update_dt(void *fdt) return 0; } -#endif diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index ea40c55dd2c..db5d460eb46 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -79,6 +79,9 @@ static void relocate_secure_section(void) void armv8_setup_psci(void) { + if (current_el() != 3) + return; + relocate_secure_section(); secure_ram_addr(psci_setup_vectors)(); secure_ram_addr(psci_arch_init)(); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5ea99c459ce..80a1642447d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -55,6 +55,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select RESV_RAM if GIC_V3_ITS + select SYS_HAS_ARMV8_SECURE_BASE imply PANIC_HANG config ARCH_LS1043A @@ -74,7 +75,6 @@ config ARCH_LS1043A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009660 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT @@ -91,6 +91,7 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + select SYS_HAS_ARMV8_SECURE_BASE imply CMD_PCI imply ID_EEPROM @@ -112,7 +113,6 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A008511 if !TFABOOT select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 @@ -335,6 +335,7 @@ menu "Layerscape architecture" config FSL_LAYERSCAPE bool + select ARM_SMCCC config HAS_FEATURE_GIC64K_ALIGN bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cf469804c51..a71ee636afe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -17,6 +17,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/ptrace.h> +#include <linux/arm-smccc.h> #include <linux/errno.h> #include <asm/system.h> #include <fm_eth.h> @@ -768,7 +769,7 @@ enum boot_src __get_boot_src(u32 porsr1) enum boot_src get_boot_src(void) { - struct pt_regs regs; + struct arm_smccc_res res; u32 porsr1 = 0; #if defined(CONFIG_FSL_LSCH3) @@ -778,11 +779,9 @@ enum boot_src get_boot_src(void) #endif if (current_el() == 2) { - regs.regs[0] = SIP_SVC_RCW; - - smc_call(®s); - if (!regs.regs[0]) - porsr1 = regs.regs[1]; + arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0) + porsr1 = res.a1; } if (current_el() == 3 || !porsr1) { @@ -1081,9 +1080,9 @@ static void config_core_prefetch(void) char *buf = NULL; char buffer[HWCONFIG_BUFFER_SIZE]; const char *prefetch_arg = NULL; + struct arm_smccc_res res; size_t arglen; unsigned int mask; - struct pt_regs regs; if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; @@ -1101,11 +1100,10 @@ static void config_core_prefetch(void) } #define SIP_PREFETCH_DISABLE_64 0xC200FF13 - regs.regs[0] = SIP_PREFETCH_DISABLE_64; - regs.regs[1] = mask; - smc_call(®s); + arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0, + &res); - if (regs.regs[0]) + if (res.a0) printf("Prefetch disable config failed for mask "); else printf("Prefetch disable config passed for mask "); @@ -1345,25 +1343,20 @@ phys_size_t get_effective_memsize(void) #ifdef CONFIG_TFABOOT phys_size_t tfa_get_dram_size(void) { - struct pt_regs regs; - phys_size_t dram_size = 0; - - regs.regs[0] = SMC_DRAM_BANK_INFO; - regs.regs[1] = -1; + struct arm_smccc_res res; - smc_call(®s); - if (regs.regs[0]) + arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) return 0; - dram_size = regs.regs[1]; - return dram_size; + return res.a1; } static int tfa_dram_init_banksize(void) { int i = 0, ret = 0; - struct pt_regs regs; phys_size_t dram_size = tfa_get_dram_size(); + struct arm_smccc_res res; debug("dram_size %llx\n", dram_size); @@ -1371,19 +1364,15 @@ static int tfa_dram_init_banksize(void) return -EINVAL; do { - regs.regs[0] = SMC_DRAM_BANK_INFO; - regs.regs[1] = i; - - smc_call(®s); - if (regs.regs[0]) { + arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { ret = -EINVAL; break; } - debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], - regs.regs[2]); - gd->bd->bi_dram[i].start = regs.regs[1]; - gd->bd->bi_dram[i].size = regs.regs[2]; + debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); + gd->bd->bi_dram[i].start = res.a1; + gd->bd->bi_dram[i].size = res.a2; dram_size -= gd->bd->bi_dram[i].size; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index fad7a935662..181bd9c1b4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -147,10 +147,14 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, cfg >>= sd_prctl_shift; cfg = serdes_get_number(sd, cfg); - printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + if (cfg == 0) { + printf("SERDES%d is disabled\n", sd + 1); + } else { + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); - if (!is_serdes_prtcl_valid(sd, cfg)) - printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + } for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 2fb4e404a24..87410c73a92 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2022 NXP * * Extracted from armv8/start.S */ @@ -344,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err) ldr x0, =DCSR_DCFG_MBEESR2 str w1, [x0] ret -ENDPROC(fsl_ocram_init) +ENDPROC(fsl_ocram_clear_ecc_err) #endif #ifdef CONFIG_FSL_LSCH3 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 2e2688eadca..72221191493 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -302,6 +302,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) u64 boot_addr; u64 *table = get_spin_tbl_addr(); int pos; + int ret; boot_addr = simple_strtoull(argv[0], NULL, 16); @@ -326,16 +327,10 @@ int cpu_release(u32 nr, int argc, char *const argv[]) asm volatile("sev"); } else { /* Use PSCI to kick the core */ - struct pt_regs regs; - printf("begin to kick cpu core #%d to address %llx\n", nr, boot_addr); - regs.regs[0] = PSCI_0_2_FN64_CPU_ON; - regs.regs[1] = nr; - regs.regs[2] = boot_addr; - regs.regs[3] = 0; - smc_call(®s); - if (regs.regs[0]) + ret = invoke_psci_fn(PSCI_0_2_FN64_CPU_ON, nr, boot_addr, 0); + if (ret) return -1; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d3a5cfaac19..926f8f21b63 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -206,6 +206,9 @@ static void erratum_a008997(void) static void erratum_a009007(void) { + if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007)) + return; + #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ defined(CONFIG_ARCH_LS1012A) void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 267894fbcb3..7e6e4064ffe 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -13,6 +13,7 @@ #include <asm/global_data.h> #include <asm/ptrace.h> #include <linux/kernel.h> +#include <linux/arm-smccc.h> #include <asm/io.h> #include <asm/system.h> #include <asm/types.h> @@ -374,29 +375,25 @@ bool sec_firmware_support_hwrng(void) */ int sec_firmware_get_random(uint8_t *rand, int bytes) { + struct arm_smccc_res res; unsigned long long num; - struct pt_regs regs; int param1; if (!bytes || bytes > 8) { printf("Max Random bytes genration supported is 8\n"); return -1; } -#define SIP_RNG_64 0xC200FF11 - regs.regs[0] = SIP_RNG_64; - if (bytes <= 4) param1 = 0; else param1 = 1; - regs.regs[1] = param1; - - smc_call(®s); - if (regs.regs[0]) +#define SIP_RNG_64 0xC200FF11 + arm_smccc_smc(SIP_RNG_64, param1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) return -1; - num = regs.regs[1]; + num = res.a1; memcpy(rand, &num, bytes); return 0; @@ -473,8 +470,8 @@ int fdt_fixup_kaslr(void *fdt) return 0; } - ret = sec_firmware_get_random(rand, 8); - if (ret < 0) { + err = sec_firmware_get_random(rand, 8); + if (err < 0) { printf("WARNING: No random number to set kaslr-seed\n"); return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cc1d02df811..a82516a75bd 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -143,8 +143,10 @@ int checkcpu (void) printf("Core: "); switch(ver) { case PVR_VER_E500_V1: + puts("e500v1"); + break; case PVR_VER_E500_V2: - puts("e500"); + puts("e500v2"); break; case PVR_VER_E500MC: puts("e500mc"); diff --git a/arch/powerpc/cpu/mpc85xx/resetvec.S b/arch/powerpc/cpu/mpc85xx/resetvec.S index 29555d4a009..9a552f6624e 100644 --- a/arch/powerpc/cpu/mpc85xx/resetvec.S +++ b/arch/powerpc/cpu/mpc85xx/resetvec.S @@ -1,2 +1,2 @@ .section .resetvec,"ax" - b _start_e500 + b _start diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9ddd3711190..2b2ad973599 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -46,7 +46,6 @@ GOT_ENTRY(_FIXUP_TABLE_) #ifndef MINIMAL_SPL - GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) @@ -71,9 +70,9 @@ */ .section .bootpg,"ax" - .globl _start_e500 + .globl _start -_start_e500: +_start: /* Enable debug exception */ li r1,MSR_DE mtmsr r1 @@ -1128,16 +1127,12 @@ switch_as: /*--------------------------------------------------------------*/ lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start + addi r3,r3,_start_cont - _start_cont mtlr r3 blr #endif .text - .globl _start -_start: - .long 0x27051956 /* U-BOOT Magic Number */ - .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ @@ -1604,7 +1599,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start + addi r0,r10,in_ram - _start_cont /* * As IVPR is going to point RAM address, diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds deleted file mode 100644 index 75b0285e4e5..00000000000 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2012 Freescale Semiconductor, Inc. - */ - -#include "config.h" - -#ifndef CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .text : - { - *(.text*) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - _end = .; - - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - - . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss*) - *(.bss*) - *(COMMON) - } :bss - - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds deleted file mode 100644 index a2193bf7680..00000000000 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de - * - * Copyright 2009 Freescale Semiconductor, Inc. - */ - -#include "config.h" - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - . = 0xfff00000; - .text : { - *(.text*) - } - _etext = .; - - .reloc : { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - . = ALIGN(8); - .data : { - *(.rodata*) - *(.data*) - *(.sdata*) - } - _edata = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(8); - __init_begin = .; - __init_end = .; - _end = .; -#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : - { - start.o (.bootpg) - } -#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ -#elif defined(CONFIG_FSL_ELBC) -#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ -#else -#error unknown NAND controller -#endif - .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { - KEEP(*(.resetvec)) - } = 0xffff - - __bss_start = .; - .bss : { - *(.sbss*) - *(.bss*) - } - __bss_end = .; -} -ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 27a5fe6306a..1b4d1e05a4a 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -18,6 +18,13 @@ PHDRS #endif SECTIONS { +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg IMAGE_TEXT_BASE - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#endif . = IMAGE_TEXT_BASE; .text : { *(.text*) @@ -67,18 +74,13 @@ SECTIONS __bss_end = .; #endif -/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(*(.bootpg)) - } :text = 0xffff -#else +/* For nor and nand is needed the SPL with section .resetvec */ +#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 #endif - .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : + .bootpg IMAGE_TEXT_BASE + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } @@ -90,7 +92,7 @@ SECTIONS #else #error unknown NAND controller #endif - .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff #endif diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 22bbac51aa3..e1bbee43bcb 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -11,12 +11,8 @@ #define RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - OUTPUT_ARCH(powerpc) -ENTRY(_start_e500) +ENTRY(_start) PHDRS { @@ -27,8 +23,13 @@ PHDRS SECTIONS { /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + { + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) + } :text = 0xffff + . = CONFIG_SYS_TEXT_BASE; +#endif .text : { *(.text*) @@ -75,21 +76,15 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; - . = ALIGN(256); + . = ALIGN(4); __init_begin = .; .text.init : { *(.text.init) } .data.init : { *(.data.init) } - . = ALIGN(256); + . = ALIGN(4); __init_end = .; _end = .; -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; -#else +#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) diff --git a/arch/powerpc/dts/fsl/p2020si-post.dtsi b/arch/powerpc/dts/fsl/p2020si-post.dtsi new file mode 120000 index 00000000000..b51ebf58b7a --- /dev/null +++ b/arch/powerpc/dts/fsl/p2020si-post.dtsi @@ -0,0 +1 @@ +../p2020-post.dtsi
\ No newline at end of file diff --git a/arch/powerpc/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/dts/fsl/p2020si-pre.dtsi new file mode 120000 index 00000000000..1e4b16fbe46 --- /dev/null +++ b/arch/powerpc/dts/fsl/p2020si-pre.dtsi @@ -0,0 +1 @@ +../p2020.dtsi
\ No newline at end of file diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 2206f2da9fe..97c3ce6e74d 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -27,7 +27,7 @@ }; &pcie { - compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 03b68869918..668ca0fa07e 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -37,7 +37,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6d46f7d8dd7..1c3f78798ef 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -14,8 +14,11 @@ bus-frequency = <0x0>; usb@22000 { - compatible = "fsl-usb2-dr"; + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; phy_type = "ulpi"; }; @@ -31,9 +34,10 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { - compatible = "fsl,esdhc"; + esdhc: sdhc@2e000 { + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; /* Filled in by U-Boot */ clock-frequency = <0>; }; @@ -43,44 +47,126 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x7000 0x1000>; + interrupts = < 0x3b 0x02 0x00 0x00 >; fsl,espi-num-chipselects = <4>; - status = "disabled"; }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" +/include/ "pq3-gpio-0.dtsi" + + L2: l2-cache-controller@20000 { + compatible = "fsl,p2020-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; /* 32 bytes */ + cache-size = <0x80000>; /* L2,512K */ + interrupts = <16 2 0 0>; + }; /include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-timer-0.dtsi" + + ptp_clock@24e00 { + interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; + }; + /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" }; /* PCIe controller base address 0x8000 */ &pci2 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <24 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <24 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 + >; + }; }; /* PCIe controller base address 0x9000 */ &pci1 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <25 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <25 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; }; /* PCIe controller base address 0xa000 */ &pci0 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <26 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <26 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 + >; + }; +}; + +&lbc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; + interrupts = <19 2 0 0>; }; diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index 7c4c2061d4c..7fdcb85c809 100644 --- a/arch/powerpc/dts/p2020.dtsi +++ b/arch/powerpc/dts/p2020.dtsi @@ -22,10 +22,12 @@ cpu0: PowerPC,P2020@0 { device_type = "cpu"; reg = <0>; + next-level-cache = <&L2>; }; cpu1: PowerPC,P2020@1 { device_type = "cpu"; reg = <1>; + next-level-cache = <&L2>; }; }; }; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index b37931ac449..84d32360baa 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -15,6 +15,10 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + }; + soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; @@ -45,7 +49,6 @@ /include/ "p2020-post.dtsi" &espi0 { - status = "okay"; flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index ecdc022d997..c847417df99 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -15,6 +15,10 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + lbc: localbus@fffe05000 { + reg = <0xf 0xffe05000 0 0x1000>; + }; + soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; @@ -45,7 +49,6 @@ /include/ "p2020-post.dtsi" &espi0 { - status = "okay"; flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; diff --git a/arch/powerpc/dts/pq3-duart-0.dtsi b/arch/powerpc/dts/pq3-duart-0.dtsi new file mode 100644 index 00000000000..5e268fdb9d1 --- /dev/null +++ b/arch/powerpc/dts/pq3-duart-0.dtsi @@ -0,0 +1,51 @@ +/* + * PQ3 DUART device tree stub [ controller @ offset 0x4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; +}; + +serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi new file mode 100644 index 00000000000..efe2ca04bce --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi @@ -0,0 +1,39 @@ +/* + * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +ptp_clock@24e00 { + compatible = "fsl,etsec-ptp"; + reg = <0x24e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0>; +}; diff --git a/arch/powerpc/dts/pq3-gpio-0.dtsi b/arch/powerpc/dts/pq3-gpio-0.dtsi new file mode 100644 index 00000000000..a1b48546b02 --- /dev/null +++ b/arch/powerpc/dts/pq3-gpio-0.dtsi @@ -0,0 +1,41 @@ +/* + * PQ3 GPIO device tree stub [ controller @ offset 0xfc00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +gpio-controller@fc00 { + #gpio-cells = <2>; + compatible = "fsl,pq3-gpio"; + reg = <0xfc00 0x100>; + interrupts = <47 0x2 0 0>; + gpio-controller; +}; diff --git a/arch/powerpc/dts/pq3-i2c-0.dtsi b/arch/powerpc/dts/pq3-i2c-0.dtsi index 86a91e63365..0ed519c2e53 100644 --- a/arch/powerpc/dts/pq3-i2c-0.dtsi +++ b/arch/powerpc/dts/pq3-i2c-0.dtsi @@ -12,4 +12,5 @@ i2c@3000 { u-boot,dm-pre-reloc; reg = <0x3000 0x100>; interrupts = <43 2 0 0>; + dfsrr; }; diff --git a/arch/powerpc/dts/pq3-i2c-1.dtsi b/arch/powerpc/dts/pq3-i2c-1.dtsi index 5d79b1fb4c3..78b0fcf81dc 100644 --- a/arch/powerpc/dts/pq3-i2c-1.dtsi +++ b/arch/powerpc/dts/pq3-i2c-1.dtsi @@ -12,4 +12,5 @@ i2c@3100 { u-boot,dm-pre-reloc; reg = <0x3100 0x100>; interrupts = <43 2 0 0>; + dfsrr; }; |