diff options
Diffstat (limited to 'arch')
363 files changed, 29612 insertions, 31098 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 35b19f9bfdc..ea33d07c086 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -13,6 +13,13 @@ config HAVE_SETJMP help The architecture supports setjmp() and longjmp(). +config HAVE_INITJMP + bool + depends on HAVE_SETJMP + help + The architecture supports initjmp(), a non-standard companion to + setjmp() and longjmp(). + config SUPPORT_BIG_ENDIAN bool @@ -88,6 +95,7 @@ config ARC config ARM bool "ARM architecture" select HAVE_SETJMP + select HAVE_INITJMP select ARCH_SUPPORTS_LTO select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC if !ARM64 @@ -145,6 +153,7 @@ config RISCV bool "RISC-V architecture" select CREATE_ARCH_SYMLINK select HAVE_SETJMP + select HAVE_INITJMP select SUPPORT_ACPI select SUPPORT_LITTLE_ENDIAN select SUPPORT_OF_CONTROL @@ -171,6 +180,7 @@ config RISCV config SANDBOX bool "Sandbox" select HAVE_SETJMP + select HAVE_INITJMP select ARCH_SUPPORTS_LTO select BOARD_LATE_INIT select BZIP2 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b7311d3b754..fedfdb21457 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1120,12 +1120,13 @@ config ARCH_SNAPDRAGON select SPMI select BOARD_LATE_INIT select OF_BOARD - select SAVE_PREV_BL_FDT_ADDR + select SAVE_PREV_BL_FDT_ADDR if !ENABLE_ARM_SOC_BOOT0_HOOK select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK select SYSRESET select SYSRESET_PSCI imply OF_UPSTREAM imply CMD_DM + imply DM_USB_GADGET config ARCH_SOCFPGA bool "Altera SOCFPGA family" @@ -1137,6 +1138,7 @@ config ARCH_SOCFPGA select DM_SERIAL select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64 select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL @@ -1170,8 +1172,6 @@ config ARCH_SOCFPGA imply SPL_DM_SPI_FLASH imply SPL_LIBDISK_SUPPORT imply SPL_MMC - imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI imply L2X0_CACHE @@ -1190,6 +1190,7 @@ config ARCH_SUNXI select DM_SPI_FLASH if SPI && MTD select DM_KEYBOARD select DM_SERIAL + select MMU_PGPROT if ARM64 select OF_BOARD_SETUP select OF_CONTROL select PINCTRL diff --git a/arch/arm/config.mk b/arch/arm/config.mk index e0045e22271..6e725ba1081 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -40,7 +40,7 @@ PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm endif # Choose between ARM/Thumb instruction sets -ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \ $(call cc-option, -mthumb -mthumb-interwork,\ @@ -53,7 +53,7 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \ endif # Only test once -ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y) archprepare: checkthumb checkgcc6 checkthumb: @@ -116,7 +116,7 @@ LDFLAGS_u-boot += -pie # # http://sourceware.org/bugzilla/show_bug.cgi?id=12532 # -ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y) ifeq ($(GAS_BUG_12532),) export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ then echo y; else echo n; fi) diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 06456fe5a81..9929b5ab878 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -9,6 +9,6 @@ obj-y += cpu.o # some files can only build in ARM mode -ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD CFLAGS_cpu.o := -marm endif diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 750cb94dc6e..41d8af506d8 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 6461f5f5bde..318a71f24b1 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index b4126c61df1..dd0191a12fa 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -9,7 +9,7 @@ obj-y += cpu.o ifndef CONFIG_$(PHASE_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif -ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF +ifndef CONFIG_$(PHASE_)SYS_DCACHE_OFF obj-y += cache_v8.o obj-y += cache.o endif @@ -33,7 +33,7 @@ obj-$(CONFIG_ACPI_PARKING_PROTOCOL) += acpi_park_v8.o else obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o endif -obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o +obj-$(CONFIG_$(PHASE_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 12ae9bd0603..1c1e33bec24 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -575,8 +575,12 @@ static void pretty_print_block_attrs(u64 pte) if (perm_attrs & PTE_BLOCK_PXN) cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN "); - if (perm_attrs & PTE_BLOCK_UXN) - cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN "); + if (perm_attrs & PTE_BLOCK_UXN) { + if (get_effective_el() == 1) + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN "); + else + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "XN "); + } if (perm_attrs & PTE_BLOCK_RO) cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO"); if (!mem_attrs[0]) @@ -1039,13 +1043,29 @@ int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) switch (perm) { case MMU_ATTR_RO: - attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO; + /* + * get_effective_el() will return 1 if + * - Running in EL1 so we assume an EL1 translation regime + * with HCR_EL2.{NV, NV1} != {1,1} + * - Running in EL2 with HCR_EL2.E2H = 1 so we assume an + * EL2&0 translation regime. Since we don't have accesses + * from EL0 we don't have to check HCR_EL2.TGE + * + * Both of these requires PXN to be set + */ + if (get_effective_el() == 1) + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO; + else + attrs |= PTE_BLOCK_UXN | PTE_BLOCK_RO; break; case MMU_ATTR_RX: attrs |= PTE_BLOCK_RO; break; case MMU_ATTR_RW: - attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN; + if (get_effective_el() == 1) + attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN; + else + attrs |= PTE_BLOCK_UXN; break; default: log_err("Unknown attribute %d\n", perm); diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index f7707acdf1a..044a7c16cc5 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -74,10 +74,19 @@ back_in_32: .word 0xf57ff06f // isb .word 0xe590d000 // ldr sp, [r0] .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901014 // ldr r1, [r0, #20] + .word 0xe121f301 // msr SP_irq, r1 .word 0xe5901010 // ldr r1, [r0, #16] .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR .word 0xe590100c // ldr r1, [r0, #12] .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR .word 0xf57ff06f // isb +#ifdef CONFIG_MACH_SUN55I_A523 + .word 0xe5901018 // ldr r1, [r0, #24] + .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR + .word 0xe590101c // ldr r1, [r0, #28] + .word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1 +#endif + .word 0xe12fff1e // bx lr ; return to FEL ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c index 485294b88d0..5ba20efa33b 100644 --- a/arch/arm/cpu/armv8/spin_table.c +++ b/arch/arm/cpu/armv8/spin_table.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ +#include <errno.h> #include <linux/libfdt.h> #include <asm/spin_table.h> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index d3a8a7c4787..829a620faeb 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -334,6 +334,9 @@ WEAK(lowlevel_init) /* * All slaves will enter EL2 and optionally EL1. */ +#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_XPL_BUILD) + bl psci_setup_vectors +#endif adr x4, lowlevel_in_el2 ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el2 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fcfff5bc117..82f5c374f10 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra20-asus-tf101g.dtb \ tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ + tegra20-motorola-daytona.dtb \ + tegra20-motorola-olympus.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ tegra20-seaboard.dtb \ @@ -116,7 +118,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-ouya.dtb \ tegra30-tec-ng.dtb \ tegra30-wexler-qc750.dtb \ + tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ + tegra114-nvidia-tegratab.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ @@ -299,6 +303,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb +dtb-$(CONFIG_TARGET_ZYNQ_BR) += \ + zynq-brcp1_2r.dtb \ + zynq-brcp1_1r.dtb \ + zynq-brcp1_1r_switch.dtb \ + zynq-brsmarc2.dtb \ + zynq-brcp150.dtb \ + zynq-brcp170.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo @@ -519,17 +530,6 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb -dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ - stm32429i-eval.dtb \ - stm32f469-disco.dtb - -dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ - stm32f769-disco.dtb \ - stm32746g-eval.dtb -dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ - stm32h743i-eval.dtb \ - stm32h750i-art-pi.dtb - dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-inet-3f.dtb \ sun4i-a10-inet-3w.dtb @@ -1076,37 +1076,18 @@ dtb-$(CONFIG_ASPEED_AST2600) += \ ast2600-sbp1.dtb \ ast2600-x4tf.dtb -dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb - -dtb-$(CONFIG_STM32MP13X) += \ - stm32mp135f-dk.dtb - dtb-$(CONFIG_STM32MP15X) += \ - stm32mp157a-dk1.dtb \ - stm32mp157a-dk1-scmi.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2.dtb \ - stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ - stm32mp157c-dk2.dtb \ - stm32mp157c-dk2-scmi.dtb \ - stm32mp157c-ed1.dtb \ - stm32mp157c-ed1-scmi.dtb \ - stm32mp157c-ev1.dtb \ - stm32mp157c-ev1-scmi.dtb \ stm32mp157c-odyssey.dtb -dtb-$(CONFIG_STM32MP25X) += \ - stm32mp257f-ev1.dtb - dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ - k3-j7200-r5-common-proc-board.dtb \ k3-j721e-r5-sk.dtb \ k3-j721e-r5-beagleboneai64.dtb +dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb + dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ k3-j721s2-r5-common-proc-board.dtb diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi index 0316b73f3a5..a9297ca6503 100644 --- a/arch/arm/dts/an7581-u-boot.dtsi +++ b/arch/arm/dts/an7581-u-boot.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/reset/airoha,en7581-reset.h> + / { reserved-memory { #address-cells = <2>; @@ -11,6 +13,94 @@ reg = <0x0 0x80000000 0x0 0x40000>; }; }; + + clk25m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clkxtal"; + }; + + vmmc_3v3: regulator-vmmc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + chip_scu: syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + + eth: ethernet@1fb50000 { + compatible = "airoha,en7581-eth"; + reg = <0 0x1fb50000 0 0x2600>, + <0 0x1fb54000 0 0x2000>, + <0 0x1fb56000 0 0x2000>; + reg-names = "fe", "qdma0", "qdma1"; + + resets = <&scuclk EN7581_FE_RST>, + <&scuclk EN7581_FE_PDMA_RST>, + <&scuclk EN7581_FE_QDMA_RST>, + <&scuclk EN7581_DUAL_HSI0_MAC_RST>, + <&scuclk EN7581_DUAL_HSI1_MAC_RST>, + <&scuclk EN7581_HSI_MAC_RST>, + <&scuclk EN7581_XFP_MAC_RST>; + reset-names = "fe", "pdma", "qdma", + "hsi0-mac", "hsi1-mac", "hsi-mac", + "xfp-mac"; + }; + + switch: switch@1fb58000 { + compatible = "airoha,en7581-switch"; + reg = <0 0x1fb58000 0 0x8000>; + }; + + snfi: spi@1fa10000 { + compatible = "airoha,en7581-snand"; + reg = <0x0 0x1fa10000 0x0 0x140>, + <0x0 0x1fa11000 0x0 0x600>; + + clocks = <&scuclk EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <2>; + }; + }; + + mmc0: mmc@1fa0e000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0x0 0x1fa0e000 0x0 0x1000>, + <0x0 0x1fa0c000 0x0 0x60>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>; + clock-names = "source", "hclk"; + bus-width = <4>; + max-frequency = <52000000>; + vmmc-supply = <&vmmc_3v3>; + disable-wp; + cap-mmc-highspeed; + non-removable; + + assigned-clocks = <&scuclk EN7581_CLK_EMMC>; + assigned-clock-rates = <200000000>; + }; + }; +}; + +&scuclk { + compatible = "airoha,en7581-scu", "syscon"; }; &uart1 { diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi index 585d54d2962..c8a46ed1448 100644 --- a/arch/arm/dts/apq8016-sbc-u-boot.dtsi +++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi @@ -6,7 +6,7 @@ / { /* When running as a first-stage bootloader this isn't filled in automatically */ memory@80000000 { - reg = <0 0x80000000 0 0x3da00000>; + reg = <0 0x80000000 0 0x40000000>; }; }; diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 7f00014f13c..1c7f0fa6a49 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -319,6 +319,10 @@ pinctrl-0 = <&pinctrl_sdhci1>; }; +&usb0 { + status = "okay"; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index abb3aa5b635..59453dc36d3 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -240,6 +240,11 @@ bootph-pre-ram; }; +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + #ifdef CONFIG_FSL_CAAM &sec_jr0 { bootph-pre-ram; diff --git a/arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi new file mode 100644 index 00000000000..a94e48ecb67 --- /dev/null +++ b/arch/arm/dts/imx8mp-toradex-smarc-dev-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (C) 2024 Toradex */ + +#include "imx8mp-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bt_uart_gpio { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + input; + line-name = "BT_UART_RXD_GPIO"; + }; +}; + +&gpio3 { + wifi_en_gpio { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "CTRL_EN_WIFI"; + }; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pca9450 { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +&pinctrl_i2c1 { + bootph-pre-ram; +}; + +&pinctrl_i2c1_gpio { + bootph-pre-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; +}; + +&pinctrl_uart4 { + bootph-pre-ram; +}; + +&uart3 { + status = "disabled"; +}; + +&uart4 { + bootph-pre-ram; +}; + +&usdhc1 { + status = "disabled"; +}; + +&usdhc3 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-toradex-smarc-dev.dts b/arch/arm/dts/imx8mp-toradex-smarc-dev.dts new file mode 100644 index 00000000000..581f221323b --- /dev/null +++ b/arch/arm/dts/imx8mp-toradex-smarc-dev.dts @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (C) 2025 Toradex */ + +/dts-v1/; + +#include "imx8mp-toradex-smarc.dtsi" + +/ { + model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board"; + compatible = "toradex,smarc-imx8mp-dev", + "toradex,smarc-imx8mp", + "fsl,imx8mp"; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "J64"; + type = "a"; + + port { + native_hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "tdx-smarc-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; +}; + +&aud2htx { + status = "okay"; +}; + +/* SMARC SPI0 */ +&ecspi1 { + status = "okay"; +}; + +/* SMARC GBE0 */ +&eqos { + status = "okay"; +}; + +/* SMARC GBE1 */ +&fec { + status = "okay"; +}; + +/* SMARC CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* SMARC CAN0 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>, + <&pinctrl_gpio8>, + <&pinctrl_gpio9>, + <&pinctrl_gpio10>, + <&pinctrl_gpio11>, + <&pinctrl_gpio12>, + <&pinctrl_gpio13>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_dsi_sel>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>; +}; + +&hdmi_pvi { + status = "okay"; +}; + +/* SMARC HDMI */ +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&native_hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +/* SMARC I2C_LCD */ +&i2c2 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pins 4/6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pins 52/54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* SMARC I2C_CAM0 */ +&i2c3 { + status = "okay"; +}; + +/* SMARC I2C_GP */ +&i2c4 { + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + }; + + /* On-Carrier Temperature Sensor */ + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* On-Carrier EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* SMARC I2C_CAM1 */ +&i2c5 { + status = "okay"; +}; + +/* SMARC I2C_PM */ +&i2c6 { + clock-frequency = <100000>; + status = "okay"; + + /* Fan controller */ + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + /* Current measurement into module VDD */ + hwmon@40 { + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +/* SMARC PCIE_A, M2 Key B */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* SMARC LCD1_BKLT_PWM */ +&pwm1 { + status = "okay"; +}; + +/* SMARC LCD0_BKLT_PWM */ +&pwm2 { + status = "okay"; +}; + +/* SMARC I2S0 */ +&sai1 { + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* SMARC HDMI Audio */ +&sound_hdmi { + status = "okay"; +}; + +/* SMARC SER0, RS485. Optional M.2 KEY E */ +&uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* SMARC SER2 */ +&uart2 { + status = "okay"; +}; + +/* SMARC SER1, used as the Linux Console */ +&uart4 { + status = "okay"; +}; + +/* SMARC USB0 */ +&usb3_0 { + status = "okay"; +}; + +/* SMARC USB1..4 */ +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* SMARC SDIO */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx8mp-toradex-smarc.dtsi b/arch/arm/dts/imx8mp-toradex-smarc.dtsi new file mode 100644 index 00000000000..0a8b9eee5ed --- /dev/null +++ b/arch/arm/dts/imx8mp-toradex-smarc.dtsi @@ -0,0 +1,1284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (C) 2025 Toradex */ + +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "imx8mp.dtsi" + +/ { + aliases { + can0 = &flexcan2; + can1 = &flexcan1; + ethernet0 = &eqos; + ethernet1 = &fec; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart4; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart4; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + label = "USB0"; + self-powered; + type = "micro"; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_0_dwc>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sleep>; + + smarc_key_sleep: key-sleep { + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + label = "SMARC_SLEEP#"; + wakeup-source; + linux,code = <KEY_SLEEP>; + }; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en_oc>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB0_EN_OC#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_en_oc>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB2_EN_OC#"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3V3_SD"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_USDHC_VSELECT"; + vin-supply = <®_sd_3v3_1v8>; + }; + + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CTRL_EN_WIFI"; + startup-delay-us = <2000>; + }; + + reserved-memory { + linux,cma { + size = <0 0x20000000>; + alloc-ranges = <0 0x40000000 0 0x80000000>; + }; + }; + + sound_hdmi: sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +/* SMARC SPI0 */ +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>; +}; + +/* SMARC SPI1 */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio4 3 GPIO_ACTIVE_LOW>, + <&gpio3 6 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + spi-max-frequency = <18500000>; + }; +}; + +/* SMARC GBE0 */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>, + <&pinctrl_eth_mdio>, + <&pinctrl_eqos_1588_event>; + phy-handle = <&eqos_phy>; + phy-mode = "rgmii-id"; + snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; +}; + +/* SMARC GBE1 */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>; + phy-handle = <&fec_phy>; + phy-mode = "rgmii-id"; + fsl,magic-packet; +}; + +/* SMARC CAN1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* SMARC CAN0 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&gpio1 { + gpio-line-names = "SMARC_GPIO7", /* 0 */ + "SMARC_GPIO8", + "", + "PMIC_INT#", + "PMIC_USDHC_VSELECT", + "SMARC_GPIO9", + "SMARC_GPIO10", + "SMARC_GPIO11", + "SMARC_GPIO12", + "", + "SMARC_GPIO5", /* 10 */ + "", + "SMARC_USB0_EN_OC#", + "SMARC_GPIO13", + "SMARC_USB2_EN_OC#"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "SMARC_SDIO_CD#", + "", + "", + "", + "", + "", + "", + "SMARC_SDIO_PWR_EN", + "SMARC_SDIO_WP"; /* 20 */ +}; + +&gpio3 { + gpio-line-names = "ETH_0_INT#", /* 0 */ + "SLEEP#", + "", + "", + "", + "", + "TPM_CS#", + "LVDS_DSI_SEL", + "MCU_INT#", + "GPIO_EX_INT#", + "", /* 10 */ + "", + "", + "", + "", + "", + "SMARC_SMB_ALERT#", + "", + "", + "", + "SMARC_I2C_PM_DAT", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_I2C_PM_CK"; + + lvds_dsi_mux_hog: lvds-dsi-mux-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "LVDS_DSI_SEL"; + /* LVDS_DSI_SEL as DSI */ + output-low; + }; +}; + +&gpio4 { + gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */ + "", + "", + "SMARC_SPI1_CS1#", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_GPIO4", + "SMARC_PCIE_A_RST#", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_SPI0_CS1#", + "SMARC_GPIO6"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "SMARC_USB0_OTG_ID", + "SMARC_I2C_CAM1_CK", + "SMARC_I2C_CAM1_DAT", + "", + "", + "", + "", + "SMARC_SPI0_CS0#", + "", /* 10 */ + "", + "", + "SMARC_SPI1_CS0#", + "CTRL_I2C_SCL", + "CTRL_I2C_SDA", + "SMARC_I2C_LCD_CK", + "SMARC_I2C_LCD_DAT", + "SMARC_I2C_CAM0_CK", + "SMARC_I2C_CAM0_DAT", + "SMARC_I2C_GP_CK", /* 20 */ + "SMARC_I2C_GP_DAT"; +}; + +/* SMARC HDMI */ +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; +}; + +/* On-module I2C */ +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + status = "okay"; + + som_gpio_expander: gpio-expander@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6408>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "SMARC_GPIO0", + "SMARC_GPIO1", + "SMARC_GPIO2", + "SMARC_GPIO3", + "SMARC_LCD0_VDD_EN", + "SMARC_LCD0_BKLT_EN", + "SMARC_LCD1_VDD_EN", + "SMARC_LCD1_BKLT_EN"; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; + regulator-name = "+VDD_SOC (PMIC BUCK1)"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; + regulator-name = "+VDD_ARM (PMIC BUCK2)"; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3 (PMIC BUCK4)"; + }; + + reg_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK5)"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "+VDD_DDR (PMIC BUCK6)"; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1710000>; + regulator-name = "+V1.8_SNVS (PMIC LDO1)"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_ADC (PMIC LDO4)"; + }; + + reg_sd_3v3_1v8: LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO5)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* SMARC I2C_LCD */ +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* SMARC I2C_CAM0 */ +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* SMARC I2C_GP */ +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + status = "okay"; + + eeprom@50 { + compatible = "st,24c32", "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +/* SMARC I2C_CAM1 */ +&i2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* SMARC I2C_PM */ +&i2c6 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + clock-frequency = <400000>; + scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +&mdio { + eqos_phy: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; + + fec_phy: ethernet-phy@2 { + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +/* SMARC PCIE_A */ +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; +}; + +/* SMARC LCD1_BKLT_PWM */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>; +}; + +/* SMARC LCD0_BKLT_PWM */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>; +}; + +/* SMARC GPIO5 as PWM */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5_pwm>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* SMARC SER0 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; +}; + +/* SMARC SER2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +/* On-module Bluetooth, optional SMARC SER3 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + status = "okay"; + + som_bt: bluetooth { + compatible = "mrvl,88w8997"; + max-speed = <921600>; + }; +}; + +/* SMARC SER1, used as the Linux Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +/* SMARC USB0 */ +&usb3_0 { + fsl,disable-port-power-control; +}; + +/* SMARC USB1..4 */ +&usb3_1 { + fsl,disable-port-power-control; +}; + +&usb3_phy1 { + vbus-supply = <®_usb1_vbus>; +}; + +&usb_dwc3_0 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + maximum-speed = "high-speed"; + srp-disable; + usb-role-switch; + + port { + usb3_0_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +/* On-module Wi-Fi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +/* SMARC SDIO */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, + <&pinctrl_usdhc2_cd>, + <&pinctrl_usdhc2_wp>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, + <&pinctrl_usdhc2_cd>, + <&pinctrl_usdhc2_wp>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, + <&pinctrl_usdhc2_cd>, + <&pinctrl_usdhc2_wp>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, + <&pinctrl_usdhc2_cd_sleep>, + <&pinctrl_usdhc2_wp>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +}; + +/* On-module eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + /* On-module Bluetooth */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x1c4>, /* WiFi_UART_TXD */ + <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x1c4>, /* WiFi_UART_RXD */ + <MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x1c4>, /* WiFi_UART_RTS */ + <MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x1c4>; /* WiFi_UART_CTS */ + }; + + /* SMARC CAM_MCK */ + pinctrl_csi_mclk: csimclkgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x16>; /* SMARC S6 - CAM_MCK */ + }; + + /* SMARC SPI0 */ + pinctrl_ecspi1: ecspi1grp { + fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SMARC P45 - SPI0_DIN */ + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SMARC P46 - SPI0_DO */ + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SMARC P44 - SPI0_CK */ + <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>, /* SMARC P43 - SPI0_CS0# */ + <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SMARC P31 - SPI0_CS1# */ + }; + + /* SMARC SPI1 */ + pinctrl_ecspi2: ecspi2grp { + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c4>, /* SMARC P56 - SPI1_DIN */ + <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x4>, /* SMARC P57 - SPI1_DO */ + <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x4>, /* SMARC P58 - SPI1_CK */ + <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>, /* SMARC P54 - SPI1_CS0# */ + <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4>; /* SMARC P55 - SPI1_CS1# */ + }; + + /* ETH_0 RGMII (On-module PHY) */ + pinctrl_eqos: eqosgrp { + fsl,pins = <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, /* ETH0_RGMII_RXD0 */ + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, /* ETH0_RGMII_RXD1 */ + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, /* ETH0_RGMII_RXD2 */ + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, /* ETH0_RGMII_RXD3 */ + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, /* ETH0_RGMII_RXC */ + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, /* ETH0_RGMII_RX_CTL */ + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16>, /* ETH0_RGMII_TXD0 */ + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16>, /* ETH0_RGMII_TXD1 */ + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16>, /* ETH0_RGMII_TXD2 */ + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16>, /* ETH0_RGMII_TXD3 */ + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16>, /* ETH0_RGMII_TX_CTL */ + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16>; /* ETH0_RGMII_TXC */ + }; + + /* SMARC GBE0_SDP */ + pinctrl_eqos_1588_event: eqos1588eventgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x4>; /* SMARC P6 - GBE0_SDP */ + }; + + /* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */ + pinctrl_eth_mdio: ethmdiogrp { + fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2>, /* ETH_0_MDC */ + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2>, /* ETH_0_MDIO */ + <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x80>; /* ETH_0_INT# */ + }; + + /* ETH_1 RGMII (On-module PHY) */ + pinctrl_fec: fecgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, /* ETH1_RGMII_RXD0 */ + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, /* ETH1_RGMII_RXD1 */ + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, /* ETH1_RGMII_RXD2 */ + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, /* ETH1_RGMII_RXD3 */ + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, /* ETH1_RGMII_RXC */ + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, /* ETH1_RGMII_RX_CTL */ + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16>, /* ETH1_RGMII_TXD0 */ + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16>, /* ETH1_RGMII_TXD1 */ + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16>, /* ETH1_RGMII_TXD2 */ + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16>, /* ETH1_RGMII_TXD3 */ + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16>, /* ETH1_RGMII_TX_CTL */ + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16>; /* ETH1_RGMII_TXC */ + }; + + /* SMARC GBE1_SDP */ + pinctrl_fec_1588_event: fec1588eventgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x4>; /* SMARC P5 - GBE1_SDP */ + }; + + /* SMARC CAN1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154>, /* SMARC P146 - CAN1_RX */ + <MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154>; /* SMARC P145 - CAN1_TX */ + }; + + /* SMARC CAN0 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SMARC P144 - CAN0_RX */ + <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SMARC P143 - CAN0_TX */ + }; + + /* SMARC GPIO4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x144>; /* SMARC P112 - GPIO4 */ + }; + + /* SMARC GPIO5 */ + pinctrl_gpio5: gpio5grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x144>; /* SMARC P113 - GPIO5 */ + }; + + /* SMARC GPIO5 as PWM */ + pinctrl_gpio5_pwm: gpio5pwmgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x12>; /* SMARC P113 - PWM_OUT */ + }; + + /* SMARC GPIO6 */ + pinctrl_gpio6: gpio6grp { + fsl,pins = <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x144>; /* SMARC P114 - GPIO6 */ + }; + + /* SMARC GPIO7 */ + pinctrl_gpio7: gpio7grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x144>; /* SMARC P115 - GPIO7 */ + }; + + /* SMARC GPIO8 */ + pinctrl_gpio8: gpio8grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x144>; /* SMARC P116 - GPIO8 */ + }; + + /* SMARC GPIO9 */ + pinctrl_gpio9: gpio9grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x144>; /* SMARC P117 - GPIO9 */ + }; + + /* SMARC GPIO10 */ + pinctrl_gpio10: gpio10grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x144>; /* SMARC P118 - GPIO10 */ + }; + + /* SMARC GPIO11 */ + pinctrl_gpio11: gpio11grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x144>; /* SMARC P119 - GPIO11 */ + }; + + /* SMARC GPIO12 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x144>; /* SMARC S142 - GPIO12 */ + }; + + /* SMARC GPIO13 */ + pinctrl_gpio13: gpio13grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144>; /* SMARC S123 - GPIO13 */ + }; + + /* SMARC HDMI */ + pinctrl_hdmi: hdmigrp { + fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c6>, /* SMARC P105 - HDMI_CTRL_CK */ + <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c6>, /* SMARC P106 - HDMI_CTRL_DAT */ + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SMARC P104 - HDMI_HPD */ + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* CTRL_I2C_SCL */ + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* CTRL_I2C_SDA */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* CTRL_I2C_SCL */ + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* CTRL_I2C_SDA */ + }; + + /* SMARC I2C_LCD */ + pinctrl_i2c2: i2c2grp { + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */ + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */ + }; + + /* SMARC I2C_LCD as GPIOs */ + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */ + <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */ + }; + + /* SMARC I2C_CAM0 */ + pinctrl_i2c3: i2c3grp { + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */ + <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */ + }; + + /* SMARC I2C_CAM0 as GPIOs */ + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */ + <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */ + }; + + /* SMARC I2C_GP */ + pinctrl_i2c4: i2c4grp { + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SMARC S48 - I2C_GP_CK */ + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */ + }; + + /* SMARC I2C_GP as GPIOs */ + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SMARC S48 - I2C_GP_CK */ + <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */ + }; + + /* SMARC I2C_CAM1 */ + pinctrl_i2c5: i2c5grp { + fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */ + <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */ + }; + + /* SMARC I2C_CAM1 as GPIOs */ + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */ + <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */ + }; + + /* SMARC I2C_PM */ + pinctrl_i2c6: i2c6grp { + fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x400001c6>, /* SMARC P121 - I2C_PM_CK */ + <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */ + }; + + /* SMARC I2C_PM as GPIOs */ + pinctrl_i2c6_gpio: i2c6gpiogrp { + fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x400001c6>, /* SMARC P121 - I2C_PM_CK */ + <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */ + }; + + pinctrl_lvds_dsi_sel: lvdsdsiselgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x104>; /* LVDS_DSI_SEL */ + }; + + pinctrl_mcu_int: mcuintgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */ + }; + + /* SMARC LCD1_BKLT_PWM */ + pinctrl_lcd1_bklt_pwm1: pwm1grp { + fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x12>; /* SMARC S122 - LCD1_BKLT_PWM */ + }; + + /* SMARC LCD0_BKLT_PWM */ + pinctrl_lcd0_bklt_pwm2: pwm2grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x12>; /* SMARC S141 - LCD0_BKLT_PWM */ + }; + + /* PCAL6408 Interrupt */ + pinctrl_pcal6408: pcal6408intgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x1c4>; /* GPIO_EX_INT# */ + }; + + /* SMARC PCIE_A */ + pinctrl_pcie: pciegrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c0>, /* SMARC S146 - PCIE_WAKE# */ + <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x04>; /* SMARC P75 - PCIE_A_RST# */ + }; + + /* PMIC Interrupt */ + pinctrl_pmic: pmicintgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ + }; + + /* SMARC I2S0 */ + pinctrl_sai1: sai1grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x94>, /* SMARC S42 - I2S0_CK */ + <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x94>, /* SMARC S39 - I2S0_LRCLK */ + <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x94>, /* SMARC S41 - I2S0_SDIN */ + <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x94>; /* SMARC S40 - I2S0_SDOUT */ + }; + + /* SMARC AUDIO_MCK */ + pinctrl_sai1_mclk: sai1mclkgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>; /* SMARC S38 - AUDIO_MCK */ + }; + + /* SMARC I2S2 */ + pinctrl_sai3: sai3grp { + fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94>, /* SMARC S52 - I2S2_SDIN */ + <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94>, /* SMARC S53 - I2S2_CK */ + <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94>, /* SMARC S51 - I2S2_SDOUT */ + <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94>; /* SMARC S50 - I2S2_LRCLK */ + }; + + /* SMARC SLEEP# */ + pinctrl_sleep: sleepgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */ + }; + + /* SMARC SMB_ALERT# */ + pinctrl_smb_alert: smbalertgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */ + }; + + /* TPM_CS# */ + pinctrl_tpm_cs: tpmcsgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x82>; /* TPM_CS# */ + }; + + /* WIFI_BT_WKUP_HOST/TPM_INT# */ + pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x16>; /* WIFI_BT_WKUP_HOST/TPM_INT# */ + }; + + /* SMARC SER0 */ + pinctrl_uart1: uart1grp { + fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SMARC P132 - SER2_CTS */ + <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SMARC P131 - SER2_RTS */ + <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SMARC P130 - SER2_RX */ + <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SMARC P139 - SER2_TX */ + }; + + /* SMARC SER2 */ + pinctrl_uart2: uart2grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SMARC P139 - SER2_CTS */ + <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SMARC P138 - SER2_RTS */ + <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SMARC P137 - SER2_RX */ + <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SMARC P136 - SER2_TX */ + }; + + /* SMARC SER3 */ + pinctrl_uart3: uart3grp { + fsl,pins = <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SMARC P141 - SER3_RX */ + <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SMARC P140 - SER3_TX */ + }; + + /* SMARC SER1 */ + pinctrl_uart4: uart4grp { + fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SMARC P135 - SER1_RX */ + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SMARC P134 - SER1_TX */ + }; + + /* SMARC USB0_OTG_ID */ + pinctrl_usb0_id: usb0idgrp { + fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SMARC P64 - USB0_OTG_ID */ + }; + + /* SMARC USB0_EN_OC# */ + pinctrl_usb0_en_oc: usb0enocgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x04>; /* SMARC P62 - USB0_EN_OC# */ + }; + + /* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */ + pinctrl_usb1_en_oc: usb1enocgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04>; /* SMARC P71 - USB2_EN_OC# */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, /* WiFi_SDIO_CLK */ + <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, /* WiFi_SDIO_CMD */ + <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, /* WiFi_SDIO_DATA0 */ + <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, /* WiFi_SDIO_DATA1 */ + <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, /* WiFi_SDIO_DATA2 */ + <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; /* WiFi_SDIO_DATA3 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, /* WiFi_SDIO_CLK */ + <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, /* WiFi_SDIO_CMD */ + <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, /* WiFi_SDIO_DATA0 */ + <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, /* WiFi_SDIO_DATA1 */ + <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, /* WiFi_SDIO_DATA2 */ + <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; /* WiFi_SDIO_DATA3 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, /* WiFi_SDIO_CLK */ + <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, /* WiFi_SDIO_CMD */ + <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, /* WiFi_SDIO_DATA0 */ + <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, /* WiFi_SDIO_DATA1 */ + <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, /* WiFi_SDIO_DATA2 */ + <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; /* WiFi_SDIO_DATA3 */ + }; + + /* SMARC SDIO */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SMARC P36 - SDIO_CK */ + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SMARC P34 - SDIO_CMD */ + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SMARC P39 - SDIO_DO */ + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SMARC P40 - SDIO_D1 */ + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SMARC P41 - SDIO_D2 */ + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO 100MHz */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, /* SMARC P36 - SDIO_CK */ + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, /* SMARC P34 - SDIO_CMD */ + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, /* SMARC P39 - SDIO_DO */ + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, /* SMARC P40 - SDIO_D1 */ + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, /* SMARC P41 - SDIO_D2 */ + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO 200MHz */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, /* SMARC P36 - SDIO_CK */ + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, /* SMARC P34 - SDIO_CMD */ + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, /* SMARC P39 - SDIO_DO */ + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, /* SMARC P40 - SDIO_D1 */ + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, /* SMARC P41 - SDIO_D2 */ + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO_CD# */ + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SMARC P35 - SDIO_CD# */ + }; + + /* SMARC SDIO_CD# */ + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SMARC P35 - SDIO_CD# */ + }; + + /* SMARC SDIO_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* SMARC P37 - SDIO_PWR_EN */ + }; + + /* SMARC SDIO Sleep - Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, /* SMARC P36 - SDIO_CK */ + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, /* SMARC P34 - SDIO_CMD */ + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, /* SMARC P39 - SDIO_DO */ + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, /* SMARC P39 - SDIO_D1 */ + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, /* SMARC P39 - SDIO_D2 */ + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; /* SMARC P39 - SDIO_D3 */ + }; + + pinctrl_usdhc2_vsel: usdhc2vselgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x4>; /* PMIC_USDHC_VSELECT */ + }; + + /* SMARC SDIO_WP */ + pinctrl_usdhc2_wp: usdhc2wpgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x144>; /* SMARC P33 - SDIO_WP */ + }; + + /* On-module eMMC */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, /* eMMC_STROBE */ + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, /* eMMC_DATA5 */ + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, /* eMMC_DATA6 */ + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, /* eMMC_DATA7 */ + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, /* eMMC_DATA0 */ + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, /* eMMC_DATA1 */ + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, /* eMMC_DATA2 */ + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, /* eMMC_DATA3 */ + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, /* eMMC_DATA4 */ + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, /* eMMC_CLK */ + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; /* eMMC_CMD */ + }; + + /* On-module eMMC */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, /* eMMC_STROBE */ + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, /* eMMC_DATA5 */ + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, /* eMMC_DATA6 */ + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, /* eMMC_DATA7 */ + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, /* eMMC_DATA0 */ + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, /* eMMC_DATA1 */ + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, /* eMMC_DATA2 */ + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, /* eMMC_DATA3 */ + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, /* eMMC_DATA4 */ + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, /* eMMC_CLK */ + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; /* eMMC_CMD */ + }; + + /* On-module eMMC */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, /* eMMC_STROBE */ + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, /* eMMC_DATA5 */ + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, /* eMMC_DATA6 */ + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, /* eMMC_DATA7 */ + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, /* eMMC_DATA0 */ + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, /* eMMC_DATA1 */ + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, /* eMMC_DATA2 */ + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, /* eMMC_DATA3 */ + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, /* eMMC_DATA4 */ + <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, /* eMMC_CLK */ + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; /* eMMC_CMD */ + }; + + /* SoC Watchdog */ + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x4>; /* CTRL_SOC_WDOG */ + }; + + /* On-module Wi-Fi power enable */ + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x104>; /* CTRL_EN_WIFI */ + }; +}; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index c9a610ba483..ce6793b2d57 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -47,6 +47,20 @@ #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -65,6 +79,7 @@ nvmem-cell-names = "speed_grade"; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_1: cpu@1 { @@ -83,6 +98,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_2: cpu@2 { @@ -101,6 +117,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_3: cpu@3 { @@ -119,6 +136,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_L2: l2-cache0 { @@ -264,6 +282,7 @@ dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; + status = "disabled"; }; }; @@ -726,6 +745,8 @@ clk: clock-controller@30380000 { compatible = "fsl,imx8mp-ccm"; reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; @@ -786,6 +807,23 @@ reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; }; + pgc_mlmix: power-domain@4 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, + <800000000>, + <400000000>; + }; + pgc_audio: power-domain@5 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; @@ -793,10 +831,10 @@ <&clk IMX8MP_CLK_AUDIO_AXI>; assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; assigned-clock-rates = <400000000>, - <600000000>; + <800000000>; }; pgc_gpu2d: power-domain@6 { @@ -818,6 +856,12 @@ assigned-clock-rates = <800000000>, <400000000>; }; + pgc_vpumix: power-domain@8 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; + }; + pgc_gpu3d: power-domain@9 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_GPU3D>; @@ -833,60 +877,64 @@ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; - pgc_mipi_phy2: power-domain@16 { + pgc_vpu_g1: power-domain@11 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; }; - pgc_hsiomix: power-domain@17 { + pgc_vpu_g2: power-domain@12 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; - clocks = <&clk IMX8MP_CLK_HSIO_AXI>, - <&clk IMX8MP_CLK_HSIO_ROOT>; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; - pgc_ispdwp: power-domain@18 { + pgc_vpu_vc8000e: power-domain@13 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; - pgc_vpumix: power-domain@19 { + pgc_hdmimix: power-domain@14 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; - clocks = <&clk IMX8MP_CLK_VPU_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; }; - pgc_vpu_g1: power-domain@20 { + pgc_hdmi_phy: power-domain@15 { #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; }; - pgc_vpu_g2: power-domain@21 { + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; - clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; }; - pgc_vpu_vc8000e: power-domain@22 { + pgc_hsiomix: power-domain@17 { #power-domain-cells = <0>; - power-domains = <&pgc_vpumix>; - reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; - clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; }; - pgc_mlmix: power-domain@24 { + pgc_ispdwp: power-domain@18 { #power-domain-cells = <0>; - reg = <IMX8MP_POWER_DOMAIN_MLMIX>; - clocks = <&clk IMX8MP_CLK_ML_AXI>, - <&clk IMX8MP_CLK_ML_AHB>, - <&clk IMX8MP_CLK_NPU_ROOT>; + reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; }; }; }; @@ -1231,7 +1279,7 @@ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_DUMMY>, + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, <&clk IMX8MP_CLK_NAND_USDHC_BUS>, <&clk IMX8MP_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; @@ -1245,7 +1293,7 @@ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_DUMMY>, + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, <&clk IMX8MP_CLK_NAND_USDHC_BUS>, <&clk IMX8MP_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; @@ -1259,7 +1307,7 @@ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_DUMMY>, + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, <&clk IMX8MP_CLK_NAND_USDHC_BUS>, <&clk IMX8MP_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; @@ -1501,6 +1549,41 @@ status = "disabled"; }; + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + status = "disabled"; + }; + + xcvr: xcvr@30cc0000 { + compatible = "fsl,imx8mp-xcvr"; + reg = <0x30cc0000 0x800>, + <0x30cc0800 0x400>, + <0x30cc0c00 0x080>, + <0x30cc0e00 0x080>; + reg-names = "ram", "regs", "rxfifo", + "txfifo"; + interrupts = /* XCVR IRQ 0 */ + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR IRQ 1 */ + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + /* XCVR PHY - SPDIF wakeup IRQ */ + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; + dma-names = "rx", "tx"; + resets = <&audio_blk_ctrl 0>; + status = "disabled"; + }; }; sdma3: dma-controller@30e00000 { @@ -1529,17 +1612,22 @@ compatible = "fsl,imx8mp-audio-blk-ctrl"; reg = <0x30e20000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_SAI1>, <&clk IMX8MP_CLK_SAI2>, <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <361267200>; }; }; @@ -1604,6 +1692,50 @@ }; }; + isp_0: isp@32e10000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e10000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "isp", "aclk", "hclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + fsl,blk-ctrl = <&media_blk_ctrl 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + }; + + isp_1: isp@32e20000 { + compatible = "fsl,imx8mp-isp"; + reg = <0x32e20000 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "isp", "aclk", "hclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + fsl,blk-ctrl = <&media_blk_ctrl 1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + }; + }; + }; + dewarp: dwe@32e30000 { compatible = "nxp,imx8mp-dw100"; reg = <0x32e30000 0x10000>; @@ -1618,15 +1750,16 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <500000000>; + clock-frequency = <250000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <500000000>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, + <&clk IMX8MP_CLK_24M>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; @@ -1652,15 +1785,16 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e50000 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <266000000>; + clock-frequency = <250000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <266000000>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, + <&clk IMX8MP_CLK_24M>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; status = "disabled"; @@ -1709,6 +1843,13 @@ remote-endpoint = <&lcdif1_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; @@ -1791,24 +1932,33 @@ clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", "isp", "phy"; + /* + * The ISP maximum frequency is 400MHz in normal mode + * and 500MHz in overdrive mode. The 400MHz operating + * point hasn't been successfully tested yet, so set + * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. + */ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, <&clk IMX8MP_CLK_MEDIA_APB>, <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_VIDEO_PLL1_OUT>, - <&clk IMX8MP_VIDEO_PLL1_OUT>; + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>, <200000000>, - <0>, <0>, <1039500000>; + <0>, <0>, <500000000>, + <1039500000>; #power-domain-cells = <1>; lvds_bridge: bridge@5c { compatible = "fsl,imx8mp-ldb"; reg = <0x5c 0x4>, <0x128 0x4>; reg-names = "ldb", "lvds"; - clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; clock-names = "ldb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; @@ -1873,6 +2023,136 @@ #power-domain-cells = <1>; #clock-cells = <0>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x1000>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; + #power-domain-cells = <1>; + }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32fc6000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <8>; + clocks = <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint = <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <0>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie: pcie@33800000 { @@ -1915,8 +2195,11 @@ pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; - reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; - reg-names = "dbi", "addr_space"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; @@ -1950,9 +2233,9 @@ clock-names = "core", "shader", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>, <1000000000>; power-domains = <&pgc_gpu3d>; }; @@ -1965,8 +2248,8 @@ <&clk IMX8MP_CLK_GPU_AHB>; clock-names = "core", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>; power-domains = <&pgc_gpu2d>; }; @@ -2012,6 +2295,18 @@ interconnect-names = "g1", "g2", "vc8000e"; }; + npu: npu@38500000 { + compatible = "vivante,gc"; + reg = <0x38500000 0x200000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "bus", "reg"; + power-domains = <&pgc_mlmix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -2072,6 +2367,7 @@ phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; }; }; @@ -2114,6 +2410,7 @@ phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; }; }; diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index 52c9cafe992..c001e2c96e8 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -42,6 +42,10 @@ bootph-all; }; +&phy_gmii_sel { + bootph-all; +}; + &fss { bootph-all; }; @@ -86,16 +90,6 @@ &main_pktdma { bootph-all; - reg = <0x00 0x485c0000 0x00 0x100>, - <0x00 0x4a800000 0x00 0x20000>, - <0x00 0x4aa00000 0x00 0x20000>, - <0x00 0x4b800000 0x00 0x200000>, - <0x00 0x485e0000 0x00 0x10000>, - <0x00 0x484a0000 0x00 0x2000>, - <0x00 0x484c0000 0x00 0x2000>, - <0x00 0x48430000 0x00 0x1000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", - "cfg", "tchan", "rchan", "rflow"; }; &main_rgmii1_pins_default { diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi index 5a52f3d19c0..f922f4b4781 100644 --- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi @@ -66,7 +66,7 @@ }; &cpsw_port2 { - bootph-all; + status = "disabled"; }; &dmsc { diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi index 7dfbeb10c32..a70fc88317e 100644 --- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -100,6 +100,10 @@ bootph-all; }; +&sdhci0 { + bootph-all; +}; + &sdhci1 { bootph-all; }; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi deleted file mode 100644 index f86a23404e6..00000000000 --- a/arch/arm/dts/k3-am62a7.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Device Tree Source for AM62A7 SoC family in Quad core configuration - * - * TRM: https://www.ti.com/lit/zip/spruj16 - * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-am62a.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - - core2 { - cpu = <&cpu2>; - }; - - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - reg = <0x002>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - reg = <0x003>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; -}; diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi index 4a82d2fd222..2f119508e18 100644 --- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi @@ -1,10 +1,109 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#define SPL_BOARD_DTB "spl/dts/ti/k3-am69-sk.dtb" +#define BOARD_DESCRIPTION "k3-am69-sk" +#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 board" + #include "k3-j784s4-binman.dtsi" +#if defined(CONFIG_CPU_V7R) + +&binman { + tiboot3-am69-hs { + insert-template = <&tiboot3_j784s4_hs>; + filename = "tiboot3-j784s4-hs-evm.bin"; + }; + + tiboot3-am69-hs-fs { + insert-template = <&tiboot3_j784s4_hs_fs>; + filename = "tiboot3-j784s4-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + }; +}; + +&ti_fs_enc { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; +}; + +&sysfw_inner_cert { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; +}; + +&ti_fs_enc_fs { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin"; +}; + +&sysfw_inner_cert_fs { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin"; +}; + +#include "k3-binman-capsule-r5.dtsi" + +// Capsule update GUIDs in string form. See j784s4_evm.h +#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46" + +&capsule_tiboot3 { + efi-capsule { + image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR; + + blob { + filename = "tiboot3-j784s4-hs-fs-evm.bin"; + }; + }; +}; + +#else // CONFIG_ARM64 + +&binman { + ti-dm { + filename = "ti-dm.bin"; + + blob-ext { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + tispl { + insert-template = <&ti_spl>; + }; + + u-boot { + insert-template = <&u_boot>; + }; + + tispl-unsigned { + insert-template = <&ti_spl_unsigned>; + }; + + u-boot-unsigned { + insert-template = <&u_boot_unsigned>; + }; +}; + +#include "k3-binman-capsule.dtsi" + +// Capsule update GUIDs in string form. See j784s4_evm.h +#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e" +#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617" + +&capsule_tispl { + efi-capsule { + image-guid = AM69_SK_SPL_IMAGE_GUID_STR; + }; +}; + +&capsule_uboot { + efi-capsule { + image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR; + }; +}; + +#endif + / { memory@80000000 { bootph-all; @@ -23,25 +122,3 @@ bootph-pre-ram; }; -#ifdef CONFIG_TARGET_J784S4_A72_EVM - -#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb" -#define AM69_SK_DTB "u-boot.dtb" - -&spl_j784s4_evm_dtb { - filename = SPL_AM69_SK_DTB; -}; - -&j784s4_evm_dtb { - filename = AM69_SK_DTB; -}; - -&spl_j784s4_evm_dtb_unsigned { - filename = SPL_AM69_SK_DTB; -}; - -&j784s4_evm_dtb_unsigned { - filename = AM69_SK_DTB; -}; - -#endif diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index ef7d4594f69..423badd7cb5 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -7,46 +7,6 @@ #ifdef CONFIG_TARGET_J7200_R5_EVM -&bcfg_yaml { - config = "board-cfg_j7200.yaml"; -}; - -&rcfg_yaml { - config = "rm-cfg_j7200.yaml"; -}; - -&pcfg_yaml { - config = "pm-cfg_j7200.yaml"; -}; - -&scfg_yaml { - config = "sec-cfg_j7200.yaml"; -}; - -&bcfg_yaml_tifs { - config = "board-cfg_j7200.yaml"; -}; - -&rcfg_yaml_tifs { - config = "rm-cfg_j7200.yaml"; -}; - -&pcfg_yaml_tifs { - config = "pm-cfg_j7200.yaml"; -}; - -&scfg_yaml_tifs { - config = "sec-cfg_j7200.yaml"; -}; - -&rcfg_yaml_dm { - config = "rm-cfg_j7200.yaml"; -}; - -&pcfg_yaml_dm { - config = "pm-cfg_j7200.yaml"; -}; - &binman { tiboot3-j7200-hs-evm.bin { filename = "tiboot3-j7200-hs-evm.bin"; diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi new file mode 100644 index 00000000000..a64d19b05f3 --- /dev/null +++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi @@ -0,0 +1,8756 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0 + */ + +#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 11 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 3 + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0012 +#define DDRSS0_CTL_69_DATA 0x00CB0408 +#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x00003380 +#define DDRSS0_CTL_103_DATA 0x00003380 +#define DDRSS0_CTL_104_DATA 0x00003380 +#define DDRSS0_CTL_105_DATA 0x00003380 +#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000005A2 +#define DDRSS0_CTL_109_DATA 0x00081CC0 +#define DDRSS0_CTL_110_DATA 0x00081CC0 +#define DDRSS0_CTL_111_DATA 0x00081CC0 +#define DDRSS0_CTL_112_DATA 0x00081CC0 +#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x0000E325 +#define DDRSS0_CTL_116_DATA 0x00081CC0 +#define DDRSS0_CTL_117_DATA 0x00081CC0 +#define DDRSS0_CTL_118_DATA 0x00081CC0 +#define DDRSS0_CTL_119_DATA 0x00081CC0 +#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0x33003FF4 +#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_178_DATA 0x35000000 +#define DDRSS0_CTL_179_DATA 0x27270035 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00353500 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0x00000000 +#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x000004D4 +#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000C2B2 +#define DDRSS0_CTL_403_DATA 0x000288FC +#define DDRSS0_CTL_404_DATA 0x00000E15 +#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000C2B2 +#define DDRSS0_CTL_411_DATA 0x000288FC +#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000007 +#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x00000100 +#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x00010000 +#define DDRSS0_PI_162_DATA 0x00000000 +#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000064 +#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x48120C04 +#define DDRSS0_PI_169_DATA 0x00154812 +#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x15040000 +#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x32103200 +#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000301 +#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005B +#define DDRSS0_PI_217_DATA 0x09000301 +#define DDRSS0_PI_218_DATA 0x04010504 +#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x00019C16 +#define DDRSS0_PI_230_DATA 0x00001018 +#define DDRSS0_PI_231_DATA 0x000040E6 +#define DDRSS0_PI_232_DATA 0x000288FC +#define DDRSS0_PI_233_DATA 0x000040E6 +#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0012 +#define DDRSS1_CTL_69_DATA 0x00CB0408 +#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x00003380 +#define DDRSS1_CTL_103_DATA 0x00003380 +#define DDRSS1_CTL_104_DATA 0x00003380 +#define DDRSS1_CTL_105_DATA 0x00003380 +#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000005A2 +#define DDRSS1_CTL_109_DATA 0x00081CC0 +#define DDRSS1_CTL_110_DATA 0x00081CC0 +#define DDRSS1_CTL_111_DATA 0x00081CC0 +#define DDRSS1_CTL_112_DATA 0x00081CC0 +#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x0000E325 +#define DDRSS1_CTL_116_DATA 0x00081CC0 +#define DDRSS1_CTL_117_DATA 0x00081CC0 +#define DDRSS1_CTL_118_DATA 0x00081CC0 +#define DDRSS1_CTL_119_DATA 0x00081CC0 +#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0x33003FF4 +#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_178_DATA 0x35000000 +#define DDRSS1_CTL_179_DATA 0x27270035 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00353500 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0x00000000 +#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x000004D4 +#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000C2B2 +#define DDRSS1_CTL_403_DATA 0x000288FC +#define DDRSS1_CTL_404_DATA 0x00000E15 +#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000C2B2 +#define DDRSS1_CTL_411_DATA 0x000288FC +#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000007 +#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x00010000 +#define DDRSS1_PI_162_DATA 0x00000000 +#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000064 +#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x48120C04 +#define DDRSS1_PI_169_DATA 0x00154812 +#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x15040000 +#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x32103200 +#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000301 +#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005B +#define DDRSS1_PI_217_DATA 0x09000301 +#define DDRSS1_PI_218_DATA 0x04010504 +#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x00019C16 +#define DDRSS1_PI_230_DATA 0x00001018 +#define DDRSS1_PI_231_DATA 0x000040E6 +#define DDRSS1_PI_232_DATA 0x000288FC +#define DDRSS1_PI_233_DATA 0x000040E6 +#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + +#define DDRSS2_CTL_00_DATA 0x00000B00 +#define DDRSS2_CTL_01_DATA 0x00000000 +#define DDRSS2_CTL_02_DATA 0x00000000 +#define DDRSS2_CTL_03_DATA 0x00000000 +#define DDRSS2_CTL_04_DATA 0x00000000 +#define DDRSS2_CTL_05_DATA 0x00000000 +#define DDRSS2_CTL_06_DATA 0x00000000 +#define DDRSS2_CTL_07_DATA 0x00002AF8 +#define DDRSS2_CTL_08_DATA 0x0001ADAF +#define DDRSS2_CTL_09_DATA 0x00000005 +#define DDRSS2_CTL_10_DATA 0x0000006E +#define DDRSS2_CTL_11_DATA 0x000681C8 +#define DDRSS2_CTL_12_DATA 0x004111C9 +#define DDRSS2_CTL_13_DATA 0x00000005 +#define DDRSS2_CTL_14_DATA 0x000010A9 +#define DDRSS2_CTL_15_DATA 0x000681C8 +#define DDRSS2_CTL_16_DATA 0x004111C9 +#define DDRSS2_CTL_17_DATA 0x00000005 +#define DDRSS2_CTL_18_DATA 0x000010A9 +#define DDRSS2_CTL_19_DATA 0x01010000 +#define DDRSS2_CTL_20_DATA 0x02011001 +#define DDRSS2_CTL_21_DATA 0x02010000 +#define DDRSS2_CTL_22_DATA 0x00020100 +#define DDRSS2_CTL_23_DATA 0x0000000B +#define DDRSS2_CTL_24_DATA 0x0000001C +#define DDRSS2_CTL_25_DATA 0x00000000 +#define DDRSS2_CTL_26_DATA 0x00000000 +#define DDRSS2_CTL_27_DATA 0x03020200 +#define DDRSS2_CTL_28_DATA 0x00005656 +#define DDRSS2_CTL_29_DATA 0x00100000 +#define DDRSS2_CTL_30_DATA 0x00000000 +#define DDRSS2_CTL_31_DATA 0x00000000 +#define DDRSS2_CTL_32_DATA 0x00000000 +#define DDRSS2_CTL_33_DATA 0x00000000 +#define DDRSS2_CTL_34_DATA 0x040C0000 +#define DDRSS2_CTL_35_DATA 0x12481248 +#define DDRSS2_CTL_36_DATA 0x00050804 +#define DDRSS2_CTL_37_DATA 0x09040008 +#define DDRSS2_CTL_38_DATA 0x15000204 +#define DDRSS2_CTL_39_DATA 0x1760008B +#define DDRSS2_CTL_40_DATA 0x1500422B +#define DDRSS2_CTL_41_DATA 0x1760008B +#define DDRSS2_CTL_42_DATA 0x2000422B +#define DDRSS2_CTL_43_DATA 0x000A0A09 +#define DDRSS2_CTL_44_DATA 0x0400078A +#define DDRSS2_CTL_45_DATA 0x1E161104 +#define DDRSS2_CTL_46_DATA 0x10012458 +#define DDRSS2_CTL_47_DATA 0x1E161110 +#define DDRSS2_CTL_48_DATA 0x10012458 +#define DDRSS2_CTL_49_DATA 0x02030410 +#define DDRSS2_CTL_50_DATA 0x2C040500 +#define DDRSS2_CTL_51_DATA 0x08292C29 +#define DDRSS2_CTL_52_DATA 0x14000E0A +#define DDRSS2_CTL_53_DATA 0x04010A0A +#define DDRSS2_CTL_54_DATA 0x01010004 +#define DDRSS2_CTL_55_DATA 0x04545408 +#define DDRSS2_CTL_56_DATA 0x04313104 +#define DDRSS2_CTL_57_DATA 0x00003131 +#define DDRSS2_CTL_58_DATA 0x00010100 +#define DDRSS2_CTL_59_DATA 0x03010000 +#define DDRSS2_CTL_60_DATA 0x00001508 +#define DDRSS2_CTL_61_DATA 0x000000CE +#define DDRSS2_CTL_62_DATA 0x0000032B +#define DDRSS2_CTL_63_DATA 0x00002073 +#define DDRSS2_CTL_64_DATA 0x0000032B +#define DDRSS2_CTL_65_DATA 0x00002073 +#define DDRSS2_CTL_66_DATA 0x00000005 +#define DDRSS2_CTL_67_DATA 0x00050000 +#define DDRSS2_CTL_68_DATA 0x00CB0012 +#define DDRSS2_CTL_69_DATA 0x00CB0408 +#define DDRSS2_CTL_70_DATA 0x00400408 +#define DDRSS2_CTL_71_DATA 0x00120103 +#define DDRSS2_CTL_72_DATA 0x00100005 +#define DDRSS2_CTL_73_DATA 0x2F080010 +#define DDRSS2_CTL_74_DATA 0x0505012F +#define DDRSS2_CTL_75_DATA 0x0401030A +#define DDRSS2_CTL_76_DATA 0x041E100B +#define DDRSS2_CTL_77_DATA 0x100B0401 +#define DDRSS2_CTL_78_DATA 0x0001041E +#define DDRSS2_CTL_79_DATA 0x00160016 +#define DDRSS2_CTL_80_DATA 0x033B033B +#define DDRSS2_CTL_81_DATA 0x033B033B +#define DDRSS2_CTL_82_DATA 0x03050505 +#define DDRSS2_CTL_83_DATA 0x03010303 +#define DDRSS2_CTL_84_DATA 0x200B100B +#define DDRSS2_CTL_85_DATA 0x04041004 +#define DDRSS2_CTL_86_DATA 0x200B100B +#define DDRSS2_CTL_87_DATA 0x04041004 +#define DDRSS2_CTL_88_DATA 0x03010000 +#define DDRSS2_CTL_89_DATA 0x00010000 +#define DDRSS2_CTL_90_DATA 0x00000000 +#define DDRSS2_CTL_91_DATA 0x00000000 +#define DDRSS2_CTL_92_DATA 0x01000000 +#define DDRSS2_CTL_93_DATA 0x80104002 +#define DDRSS2_CTL_94_DATA 0x00000000 +#define DDRSS2_CTL_95_DATA 0x00040005 +#define DDRSS2_CTL_96_DATA 0x00000000 +#define DDRSS2_CTL_97_DATA 0x00050000 +#define DDRSS2_CTL_98_DATA 0x00000004 +#define DDRSS2_CTL_99_DATA 0x00000000 +#define DDRSS2_CTL_100_DATA 0x00040005 +#define DDRSS2_CTL_101_DATA 0x00000000 +#define DDRSS2_CTL_102_DATA 0x00003380 +#define DDRSS2_CTL_103_DATA 0x00003380 +#define DDRSS2_CTL_104_DATA 0x00003380 +#define DDRSS2_CTL_105_DATA 0x00003380 +#define DDRSS2_CTL_106_DATA 0x00003380 +#define DDRSS2_CTL_107_DATA 0x00000000 +#define DDRSS2_CTL_108_DATA 0x000005A2 +#define DDRSS2_CTL_109_DATA 0x00081CC0 +#define DDRSS2_CTL_110_DATA 0x00081CC0 +#define DDRSS2_CTL_111_DATA 0x00081CC0 +#define DDRSS2_CTL_112_DATA 0x00081CC0 +#define DDRSS2_CTL_113_DATA 0x00081CC0 +#define DDRSS2_CTL_114_DATA 0x00000000 +#define DDRSS2_CTL_115_DATA 0x0000E325 +#define DDRSS2_CTL_116_DATA 0x00081CC0 +#define DDRSS2_CTL_117_DATA 0x00081CC0 +#define DDRSS2_CTL_118_DATA 0x00081CC0 +#define DDRSS2_CTL_119_DATA 0x00081CC0 +#define DDRSS2_CTL_120_DATA 0x00081CC0 +#define DDRSS2_CTL_121_DATA 0x00000000 +#define DDRSS2_CTL_122_DATA 0x0000E325 +#define DDRSS2_CTL_123_DATA 0x00000000 +#define DDRSS2_CTL_124_DATA 0x00000000 +#define DDRSS2_CTL_125_DATA 0x00000000 +#define DDRSS2_CTL_126_DATA 0x00000000 +#define DDRSS2_CTL_127_DATA 0x00000000 +#define DDRSS2_CTL_128_DATA 0x00000000 +#define DDRSS2_CTL_129_DATA 0x00000000 +#define DDRSS2_CTL_130_DATA 0x00000000 +#define DDRSS2_CTL_131_DATA 0x0B030500 +#define DDRSS2_CTL_132_DATA 0x00040B04 +#define DDRSS2_CTL_133_DATA 0x0A090000 +#define DDRSS2_CTL_134_DATA 0x0A090701 +#define DDRSS2_CTL_135_DATA 0x0900000E +#define DDRSS2_CTL_136_DATA 0x0907010A +#define DDRSS2_CTL_137_DATA 0x00000E0A +#define DDRSS2_CTL_138_DATA 0x07010A09 +#define DDRSS2_CTL_139_DATA 0x000E0A09 +#define DDRSS2_CTL_140_DATA 0x07000401 +#define DDRSS2_CTL_141_DATA 0x00000000 +#define DDRSS2_CTL_142_DATA 0x00000000 +#define DDRSS2_CTL_143_DATA 0x00000000 +#define DDRSS2_CTL_144_DATA 0x00000000 +#define DDRSS2_CTL_145_DATA 0x00000000 +#define DDRSS2_CTL_146_DATA 0x00000000 +#define DDRSS2_CTL_147_DATA 0x00000000 +#define DDRSS2_CTL_148_DATA 0x08080000 +#define DDRSS2_CTL_149_DATA 0x01000000 +#define DDRSS2_CTL_150_DATA 0x800000C0 +#define DDRSS2_CTL_151_DATA 0x800000C0 +#define DDRSS2_CTL_152_DATA 0x800000C0 +#define DDRSS2_CTL_153_DATA 0x00000000 +#define DDRSS2_CTL_154_DATA 0x00001500 +#define DDRSS2_CTL_155_DATA 0x00000000 +#define DDRSS2_CTL_156_DATA 0x00000001 +#define DDRSS2_CTL_157_DATA 0x00000002 +#define DDRSS2_CTL_158_DATA 0x0000100E +#define DDRSS2_CTL_159_DATA 0x00000000 +#define DDRSS2_CTL_160_DATA 0x00000000 +#define DDRSS2_CTL_161_DATA 0x00000000 +#define DDRSS2_CTL_162_DATA 0x00000000 +#define DDRSS2_CTL_163_DATA 0x00000000 +#define DDRSS2_CTL_164_DATA 0x000B0000 +#define DDRSS2_CTL_165_DATA 0x000E0006 +#define DDRSS2_CTL_166_DATA 0x000E0404 +#define DDRSS2_CTL_167_DATA 0x00D601AB +#define DDRSS2_CTL_168_DATA 0x10100216 +#define DDRSS2_CTL_169_DATA 0x01AB0216 +#define DDRSS2_CTL_170_DATA 0x021600D6 +#define DDRSS2_CTL_171_DATA 0x02161010 +#define DDRSS2_CTL_172_DATA 0x00000000 +#define DDRSS2_CTL_173_DATA 0x00000000 +#define DDRSS2_CTL_174_DATA 0x00000000 +#define DDRSS2_CTL_175_DATA 0x3FF40084 +#define DDRSS2_CTL_176_DATA 0x33003FF4 +#define DDRSS2_CTL_177_DATA 0x00003333 +#define DDRSS2_CTL_178_DATA 0x35000000 +#define DDRSS2_CTL_179_DATA 0x27270035 +#define DDRSS2_CTL_180_DATA 0x0F0F0000 +#define DDRSS2_CTL_181_DATA 0x16000000 +#define DDRSS2_CTL_182_DATA 0x00841616 +#define DDRSS2_CTL_183_DATA 0x3FF43FF4 +#define DDRSS2_CTL_184_DATA 0x33333300 +#define DDRSS2_CTL_185_DATA 0x00000000 +#define DDRSS2_CTL_186_DATA 0x00353500 +#define DDRSS2_CTL_187_DATA 0x00002727 +#define DDRSS2_CTL_188_DATA 0x00000F0F +#define DDRSS2_CTL_189_DATA 0x16161600 +#define DDRSS2_CTL_190_DATA 0x00000020 +#define DDRSS2_CTL_191_DATA 0x00000000 +#define DDRSS2_CTL_192_DATA 0x00000001 +#define DDRSS2_CTL_193_DATA 0x00000000 +#define DDRSS2_CTL_194_DATA 0x01000000 +#define DDRSS2_CTL_195_DATA 0x00000001 +#define DDRSS2_CTL_196_DATA 0x00000000 +#define DDRSS2_CTL_197_DATA 0x00000000 +#define DDRSS2_CTL_198_DATA 0x00000000 +#define DDRSS2_CTL_199_DATA 0x00000000 +#define DDRSS2_CTL_200_DATA 0x00000000 +#define DDRSS2_CTL_201_DATA 0x00000000 +#define DDRSS2_CTL_202_DATA 0x00000000 +#define DDRSS2_CTL_203_DATA 0x00000000 +#define DDRSS2_CTL_204_DATA 0x00000000 +#define DDRSS2_CTL_205_DATA 0x00000000 +#define DDRSS2_CTL_206_DATA 0x02000000 +#define DDRSS2_CTL_207_DATA 0x01080101 +#define DDRSS2_CTL_208_DATA 0x00000000 +#define DDRSS2_CTL_209_DATA 0x00000000 +#define DDRSS2_CTL_210_DATA 0x00000000 +#define DDRSS2_CTL_211_DATA 0x00000000 +#define DDRSS2_CTL_212_DATA 0x00000000 +#define DDRSS2_CTL_213_DATA 0x00000000 +#define DDRSS2_CTL_214_DATA 0x00000000 +#define DDRSS2_CTL_215_DATA 0x00000000 +#define DDRSS2_CTL_216_DATA 0x00000000 +#define DDRSS2_CTL_217_DATA 0x00000000 +#define DDRSS2_CTL_218_DATA 0x00000000 +#define DDRSS2_CTL_219_DATA 0x00000000 +#define DDRSS2_CTL_220_DATA 0x00000000 +#define DDRSS2_CTL_221_DATA 0x00000000 +#define DDRSS2_CTL_222_DATA 0x00001000 +#define DDRSS2_CTL_223_DATA 0x006403E8 +#define DDRSS2_CTL_224_DATA 0x00000000 +#define DDRSS2_CTL_225_DATA 0x00000000 +#define DDRSS2_CTL_226_DATA 0x00000000 +#define DDRSS2_CTL_227_DATA 0x15110000 +#define DDRSS2_CTL_228_DATA 0x00040C18 +#define DDRSS2_CTL_229_DATA 0xF000C000 +#define DDRSS2_CTL_230_DATA 0x0000F000 +#define DDRSS2_CTL_231_DATA 0x00000000 +#define DDRSS2_CTL_232_DATA 0x00000000 +#define DDRSS2_CTL_233_DATA 0xC0000000 +#define DDRSS2_CTL_234_DATA 0xF000F000 +#define DDRSS2_CTL_235_DATA 0x00000000 +#define DDRSS2_CTL_236_DATA 0x00000000 +#define DDRSS2_CTL_237_DATA 0x00000000 +#define DDRSS2_CTL_238_DATA 0xF000C000 +#define DDRSS2_CTL_239_DATA 0x0000F000 +#define DDRSS2_CTL_240_DATA 0x00000000 +#define DDRSS2_CTL_241_DATA 0x00000000 +#define DDRSS2_CTL_242_DATA 0x00030000 +#define DDRSS2_CTL_243_DATA 0x00000000 +#define DDRSS2_CTL_244_DATA 0x00000000 +#define DDRSS2_CTL_245_DATA 0x00000000 +#define DDRSS2_CTL_246_DATA 0x00000000 +#define DDRSS2_CTL_247_DATA 0x00000000 +#define DDRSS2_CTL_248_DATA 0x00000000 +#define DDRSS2_CTL_249_DATA 0x00000000 +#define DDRSS2_CTL_250_DATA 0x00000000 +#define DDRSS2_CTL_251_DATA 0x00000000 +#define DDRSS2_CTL_252_DATA 0x00000000 +#define DDRSS2_CTL_253_DATA 0x00000000 +#define DDRSS2_CTL_254_DATA 0x00000000 +#define DDRSS2_CTL_255_DATA 0x00000000 +#define DDRSS2_CTL_256_DATA 0x00000000 +#define DDRSS2_CTL_257_DATA 0x01000200 +#define DDRSS2_CTL_258_DATA 0x00370040 +#define DDRSS2_CTL_259_DATA 0x00020008 +#define DDRSS2_CTL_260_DATA 0x00400100 +#define DDRSS2_CTL_261_DATA 0x00400855 +#define DDRSS2_CTL_262_DATA 0x01000200 +#define DDRSS2_CTL_263_DATA 0x08550040 +#define DDRSS2_CTL_264_DATA 0x00000040 +#define DDRSS2_CTL_265_DATA 0x006B0003 +#define DDRSS2_CTL_266_DATA 0x0100006B +#define DDRSS2_CTL_267_DATA 0x03030303 +#define DDRSS2_CTL_268_DATA 0x00000000 +#define DDRSS2_CTL_269_DATA 0x00000202 +#define DDRSS2_CTL_270_DATA 0x00001FFF +#define DDRSS2_CTL_271_DATA 0x3FFF2000 +#define DDRSS2_CTL_272_DATA 0x03FF0000 +#define DDRSS2_CTL_273_DATA 0x000103FF +#define DDRSS2_CTL_274_DATA 0x0FFF0B00 +#define DDRSS2_CTL_275_DATA 0x01010001 +#define DDRSS2_CTL_276_DATA 0x01010101 +#define DDRSS2_CTL_277_DATA 0x01180101 +#define DDRSS2_CTL_278_DATA 0x00030000 +#define DDRSS2_CTL_279_DATA 0x00000000 +#define DDRSS2_CTL_280_DATA 0x00000000 +#define DDRSS2_CTL_281_DATA 0x00000000 +#define DDRSS2_CTL_282_DATA 0x00000000 +#define DDRSS2_CTL_283_DATA 0x00000000 +#define DDRSS2_CTL_284_DATA 0x00000000 +#define DDRSS2_CTL_285_DATA 0x00000000 +#define DDRSS2_CTL_286_DATA 0x00040101 +#define DDRSS2_CTL_287_DATA 0x04010100 +#define DDRSS2_CTL_288_DATA 0x00000000 +#define DDRSS2_CTL_289_DATA 0x00000000 +#define DDRSS2_CTL_290_DATA 0x03030300 +#define DDRSS2_CTL_291_DATA 0x00000001 +#define DDRSS2_CTL_292_DATA 0x00000000 +#define DDRSS2_CTL_293_DATA 0x00000000 +#define DDRSS2_CTL_294_DATA 0x00000000 +#define DDRSS2_CTL_295_DATA 0x00000000 +#define DDRSS2_CTL_296_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0x00000000 +#define DDRSS2_CTL_298_DATA 0x00000000 +#define DDRSS2_CTL_299_DATA 0x00000000 +#define DDRSS2_CTL_300_DATA 0x00000000 +#define DDRSS2_CTL_301_DATA 0x00000000 +#define DDRSS2_CTL_302_DATA 0x00000000 +#define DDRSS2_CTL_303_DATA 0x00000000 +#define DDRSS2_CTL_304_DATA 0x00000000 +#define DDRSS2_CTL_305_DATA 0x00000000 +#define DDRSS2_CTL_306_DATA 0x00000000 +#define DDRSS2_CTL_307_DATA 0x00000000 +#define DDRSS2_CTL_308_DATA 0x00000000 +#define DDRSS2_CTL_309_DATA 0x00000000 +#define DDRSS2_CTL_310_DATA 0x00000000 +#define DDRSS2_CTL_311_DATA 0x00000000 +#define DDRSS2_CTL_312_DATA 0x00000000 +#define DDRSS2_CTL_313_DATA 0x01000000 +#define DDRSS2_CTL_314_DATA 0x00020201 +#define DDRSS2_CTL_315_DATA 0x01000101 +#define DDRSS2_CTL_316_DATA 0x01010001 +#define DDRSS2_CTL_317_DATA 0x00010101 +#define DDRSS2_CTL_318_DATA 0x050A0A03 +#define DDRSS2_CTL_319_DATA 0x10081F1F +#define DDRSS2_CTL_320_DATA 0x00090310 +#define DDRSS2_CTL_321_DATA 0x0B0C030F +#define DDRSS2_CTL_322_DATA 0x0B0C0306 +#define DDRSS2_CTL_323_DATA 0x0C090006 +#define DDRSS2_CTL_324_DATA 0x0100000C +#define DDRSS2_CTL_325_DATA 0x08040801 +#define DDRSS2_CTL_326_DATA 0x00000004 +#define DDRSS2_CTL_327_DATA 0x00000000 +#define DDRSS2_CTL_328_DATA 0x00010000 +#define DDRSS2_CTL_329_DATA 0x00280D00 +#define DDRSS2_CTL_330_DATA 0x00000001 +#define DDRSS2_CTL_331_DATA 0x00030001 +#define DDRSS2_CTL_332_DATA 0x00000000 +#define DDRSS2_CTL_333_DATA 0x00000000 +#define DDRSS2_CTL_334_DATA 0x00000000 +#define DDRSS2_CTL_335_DATA 0x00000000 +#define DDRSS2_CTL_336_DATA 0x00000000 +#define DDRSS2_CTL_337_DATA 0x00000000 +#define DDRSS2_CTL_338_DATA 0x00000000 +#define DDRSS2_CTL_339_DATA 0x00000000 +#define DDRSS2_CTL_340_DATA 0x01000000 +#define DDRSS2_CTL_341_DATA 0x00000001 +#define DDRSS2_CTL_342_DATA 0x00010100 +#define DDRSS2_CTL_343_DATA 0x03030000 +#define DDRSS2_CTL_344_DATA 0x00000000 +#define DDRSS2_CTL_345_DATA 0x00000000 +#define DDRSS2_CTL_346_DATA 0x00000000 +#define DDRSS2_CTL_347_DATA 0x00000000 +#define DDRSS2_CTL_348_DATA 0x00000000 +#define DDRSS2_CTL_349_DATA 0x00000000 +#define DDRSS2_CTL_350_DATA 0x00000000 +#define DDRSS2_CTL_351_DATA 0x00000000 +#define DDRSS2_CTL_352_DATA 0x00000000 +#define DDRSS2_CTL_353_DATA 0x00000000 +#define DDRSS2_CTL_354_DATA 0x00000000 +#define DDRSS2_CTL_355_DATA 0x00000000 +#define DDRSS2_CTL_356_DATA 0x00000000 +#define DDRSS2_CTL_357_DATA 0x00000000 +#define DDRSS2_CTL_358_DATA 0x00000000 +#define DDRSS2_CTL_359_DATA 0x00000000 +#define DDRSS2_CTL_360_DATA 0x000556AA +#define DDRSS2_CTL_361_DATA 0x000AAAAA +#define DDRSS2_CTL_362_DATA 0x000AA955 +#define DDRSS2_CTL_363_DATA 0x00055555 +#define DDRSS2_CTL_364_DATA 0x000B3133 +#define DDRSS2_CTL_365_DATA 0x0004CD33 +#define DDRSS2_CTL_366_DATA 0x0004CECC +#define DDRSS2_CTL_367_DATA 0x000B32CC +#define DDRSS2_CTL_368_DATA 0x00010300 +#define DDRSS2_CTL_369_DATA 0x03000100 +#define DDRSS2_CTL_370_DATA 0x00000000 +#define DDRSS2_CTL_371_DATA 0x00000000 +#define DDRSS2_CTL_372_DATA 0x00000000 +#define DDRSS2_CTL_373_DATA 0x00000000 +#define DDRSS2_CTL_374_DATA 0x00000000 +#define DDRSS2_CTL_375_DATA 0x00000000 +#define DDRSS2_CTL_376_DATA 0x00000000 +#define DDRSS2_CTL_377_DATA 0x00010000 +#define DDRSS2_CTL_378_DATA 0x00000404 +#define DDRSS2_CTL_379_DATA 0x00000000 +#define DDRSS2_CTL_380_DATA 0x00000000 +#define DDRSS2_CTL_381_DATA 0x00000000 +#define DDRSS2_CTL_382_DATA 0x00000000 +#define DDRSS2_CTL_383_DATA 0x00000000 +#define DDRSS2_CTL_384_DATA 0x00000000 +#define DDRSS2_CTL_385_DATA 0x00000000 +#define DDRSS2_CTL_386_DATA 0x00000000 +#define DDRSS2_CTL_387_DATA 0x3A3A1B00 +#define DDRSS2_CTL_388_DATA 0x000A0000 +#define DDRSS2_CTL_389_DATA 0x0000019C +#define DDRSS2_CTL_390_DATA 0x00000200 +#define DDRSS2_CTL_391_DATA 0x00000200 +#define DDRSS2_CTL_392_DATA 0x00000200 +#define DDRSS2_CTL_393_DATA 0x00000200 +#define DDRSS2_CTL_394_DATA 0x000004D4 +#define DDRSS2_CTL_395_DATA 0x00001018 +#define DDRSS2_CTL_396_DATA 0x00000204 +#define DDRSS2_CTL_397_DATA 0x000040E6 +#define DDRSS2_CTL_398_DATA 0x00000200 +#define DDRSS2_CTL_399_DATA 0x00000200 +#define DDRSS2_CTL_400_DATA 0x00000200 +#define DDRSS2_CTL_401_DATA 0x00000200 +#define DDRSS2_CTL_402_DATA 0x0000C2B2 +#define DDRSS2_CTL_403_DATA 0x000288FC +#define DDRSS2_CTL_404_DATA 0x00000E15 +#define DDRSS2_CTL_405_DATA 0x000040E6 +#define DDRSS2_CTL_406_DATA 0x00000200 +#define DDRSS2_CTL_407_DATA 0x00000200 +#define DDRSS2_CTL_408_DATA 0x00000200 +#define DDRSS2_CTL_409_DATA 0x00000200 +#define DDRSS2_CTL_410_DATA 0x0000C2B2 +#define DDRSS2_CTL_411_DATA 0x000288FC +#define DDRSS2_CTL_412_DATA 0x02020E15 +#define DDRSS2_CTL_413_DATA 0x03030202 +#define DDRSS2_CTL_414_DATA 0x00000022 +#define DDRSS2_CTL_415_DATA 0x00000000 +#define DDRSS2_CTL_416_DATA 0x00000000 +#define DDRSS2_CTL_417_DATA 0x00001403 +#define DDRSS2_CTL_418_DATA 0x000007D0 +#define DDRSS2_CTL_419_DATA 0x00000000 +#define DDRSS2_CTL_420_DATA 0x00000000 +#define DDRSS2_CTL_421_DATA 0x00030000 +#define DDRSS2_CTL_422_DATA 0x0007001F +#define DDRSS2_CTL_423_DATA 0x001B0033 +#define DDRSS2_CTL_424_DATA 0x001B0033 +#define DDRSS2_CTL_425_DATA 0x00000000 +#define DDRSS2_CTL_426_DATA 0x00000000 +#define DDRSS2_CTL_427_DATA 0x02000000 +#define DDRSS2_CTL_428_DATA 0x01000404 +#define DDRSS2_CTL_429_DATA 0x0B1E0B1E +#define DDRSS2_CTL_430_DATA 0x00000105 +#define DDRSS2_CTL_431_DATA 0x00010101 +#define DDRSS2_CTL_432_DATA 0x00010101 +#define DDRSS2_CTL_433_DATA 0x00010001 +#define DDRSS2_CTL_434_DATA 0x00000101 +#define DDRSS2_CTL_435_DATA 0x02000201 +#define DDRSS2_CTL_436_DATA 0x02010000 +#define DDRSS2_CTL_437_DATA 0x00000200 +#define DDRSS2_CTL_438_DATA 0x28060000 +#define DDRSS2_CTL_439_DATA 0x00000128 +#define DDRSS2_CTL_440_DATA 0xFFFFFFFF +#define DDRSS2_CTL_441_DATA 0xFFFFFFFF +#define DDRSS2_CTL_442_DATA 0x00000000 +#define DDRSS2_CTL_443_DATA 0x00000000 +#define DDRSS2_CTL_444_DATA 0x00000000 +#define DDRSS2_CTL_445_DATA 0x00000000 +#define DDRSS2_CTL_446_DATA 0x00000000 +#define DDRSS2_CTL_447_DATA 0x00000000 +#define DDRSS2_CTL_448_DATA 0x00000000 +#define DDRSS2_CTL_449_DATA 0x00000000 +#define DDRSS2_CTL_450_DATA 0x00000000 +#define DDRSS2_CTL_451_DATA 0x00000000 +#define DDRSS2_CTL_452_DATA 0x00000000 +#define DDRSS2_CTL_453_DATA 0x00000000 +#define DDRSS2_CTL_454_DATA 0x00000000 +#define DDRSS2_CTL_455_DATA 0x00000000 +#define DDRSS2_CTL_456_DATA 0x00000000 +#define DDRSS2_CTL_457_DATA 0x00000000 +#define DDRSS2_CTL_458_DATA 0x00000000 + +#define DDRSS2_PI_00_DATA 0x00000B00 +#define DDRSS2_PI_01_DATA 0x00000000 +#define DDRSS2_PI_02_DATA 0x00000000 +#define DDRSS2_PI_03_DATA 0x00000000 +#define DDRSS2_PI_04_DATA 0x00000000 +#define DDRSS2_PI_05_DATA 0x00000101 +#define DDRSS2_PI_06_DATA 0x00640000 +#define DDRSS2_PI_07_DATA 0x00000001 +#define DDRSS2_PI_08_DATA 0x00000000 +#define DDRSS2_PI_09_DATA 0x00000000 +#define DDRSS2_PI_10_DATA 0x00000000 +#define DDRSS2_PI_11_DATA 0x00000000 +#define DDRSS2_PI_12_DATA 0x00000007 +#define DDRSS2_PI_13_DATA 0x00010002 +#define DDRSS2_PI_14_DATA 0x0800000F +#define DDRSS2_PI_15_DATA 0x00000103 +#define DDRSS2_PI_16_DATA 0x00000005 +#define DDRSS2_PI_17_DATA 0x00000000 +#define DDRSS2_PI_18_DATA 0x00000000 +#define DDRSS2_PI_19_DATA 0x00000000 +#define DDRSS2_PI_20_DATA 0x00000000 +#define DDRSS2_PI_21_DATA 0x00000000 +#define DDRSS2_PI_22_DATA 0x00000000 +#define DDRSS2_PI_23_DATA 0x00000000 +#define DDRSS2_PI_24_DATA 0x00000000 +#define DDRSS2_PI_25_DATA 0x00000000 +#define DDRSS2_PI_26_DATA 0x00010100 +#define DDRSS2_PI_27_DATA 0x00280A00 +#define DDRSS2_PI_28_DATA 0x00000000 +#define DDRSS2_PI_29_DATA 0x0F000000 +#define DDRSS2_PI_30_DATA 0x00003200 +#define DDRSS2_PI_31_DATA 0x00000000 +#define DDRSS2_PI_32_DATA 0x00000000 +#define DDRSS2_PI_33_DATA 0x01010102 +#define DDRSS2_PI_34_DATA 0x00000000 +#define DDRSS2_PI_35_DATA 0x000000AA +#define DDRSS2_PI_36_DATA 0x00000055 +#define DDRSS2_PI_37_DATA 0x000000B5 +#define DDRSS2_PI_38_DATA 0x0000004A +#define DDRSS2_PI_39_DATA 0x00000056 +#define DDRSS2_PI_40_DATA 0x000000A9 +#define DDRSS2_PI_41_DATA 0x000000A9 +#define DDRSS2_PI_42_DATA 0x000000B5 +#define DDRSS2_PI_43_DATA 0x00000000 +#define DDRSS2_PI_44_DATA 0x00000000 +#define DDRSS2_PI_45_DATA 0x000F0F00 +#define DDRSS2_PI_46_DATA 0x0000001B +#define DDRSS2_PI_47_DATA 0x000007D0 +#define DDRSS2_PI_48_DATA 0x00000300 +#define DDRSS2_PI_49_DATA 0x00000000 +#define DDRSS2_PI_50_DATA 0x00000000 +#define DDRSS2_PI_51_DATA 0x01000000 +#define DDRSS2_PI_52_DATA 0x00010101 +#define DDRSS2_PI_53_DATA 0x00000000 +#define DDRSS2_PI_54_DATA 0x00030000 +#define DDRSS2_PI_55_DATA 0x0F000000 +#define DDRSS2_PI_56_DATA 0x00000017 +#define DDRSS2_PI_57_DATA 0x00000000 +#define DDRSS2_PI_58_DATA 0x00000000 +#define DDRSS2_PI_59_DATA 0x00000000 +#define DDRSS2_PI_60_DATA 0x0A0A140A +#define DDRSS2_PI_61_DATA 0x10020101 +#define DDRSS2_PI_62_DATA 0x00020805 +#define DDRSS2_PI_63_DATA 0x01000404 +#define DDRSS2_PI_64_DATA 0x00000000 +#define DDRSS2_PI_65_DATA 0x00000000 +#define DDRSS2_PI_66_DATA 0x00000100 +#define DDRSS2_PI_67_DATA 0x0001010F +#define DDRSS2_PI_68_DATA 0x00340000 +#define DDRSS2_PI_69_DATA 0x00000000 +#define DDRSS2_PI_70_DATA 0x00000000 +#define DDRSS2_PI_71_DATA 0x0000FFFF +#define DDRSS2_PI_72_DATA 0x00000000 +#define DDRSS2_PI_73_DATA 0x00080000 +#define DDRSS2_PI_74_DATA 0x02000200 +#define DDRSS2_PI_75_DATA 0x01000100 +#define DDRSS2_PI_76_DATA 0x01000000 +#define DDRSS2_PI_77_DATA 0x02000200 +#define DDRSS2_PI_78_DATA 0x00000200 +#define DDRSS2_PI_79_DATA 0x00000000 +#define DDRSS2_PI_80_DATA 0x00000000 +#define DDRSS2_PI_81_DATA 0x00000000 +#define DDRSS2_PI_82_DATA 0x00000000 +#define DDRSS2_PI_83_DATA 0x00000000 +#define DDRSS2_PI_84_DATA 0x00000000 +#define DDRSS2_PI_85_DATA 0x00000000 +#define DDRSS2_PI_86_DATA 0x00000000 +#define DDRSS2_PI_87_DATA 0x00000000 +#define DDRSS2_PI_88_DATA 0x00000000 +#define DDRSS2_PI_89_DATA 0x00000000 +#define DDRSS2_PI_90_DATA 0x00000000 +#define DDRSS2_PI_91_DATA 0x00000400 +#define DDRSS2_PI_92_DATA 0x02010000 +#define DDRSS2_PI_93_DATA 0x00080003 +#define DDRSS2_PI_94_DATA 0x00080000 +#define DDRSS2_PI_95_DATA 0x00000001 +#define DDRSS2_PI_96_DATA 0x00000000 +#define DDRSS2_PI_97_DATA 0x0000AA00 +#define DDRSS2_PI_98_DATA 0x00000000 +#define DDRSS2_PI_99_DATA 0x00000000 +#define DDRSS2_PI_100_DATA 0x00010000 +#define DDRSS2_PI_101_DATA 0x00000000 +#define DDRSS2_PI_102_DATA 0x00000000 +#define DDRSS2_PI_103_DATA 0x00000000 +#define DDRSS2_PI_104_DATA 0x00000000 +#define DDRSS2_PI_105_DATA 0x00000000 +#define DDRSS2_PI_106_DATA 0x00000000 +#define DDRSS2_PI_107_DATA 0x00000000 +#define DDRSS2_PI_108_DATA 0x00000000 +#define DDRSS2_PI_109_DATA 0x00000000 +#define DDRSS2_PI_110_DATA 0x00000000 +#define DDRSS2_PI_111_DATA 0x00000000 +#define DDRSS2_PI_112_DATA 0x00000000 +#define DDRSS2_PI_113_DATA 0x00000000 +#define DDRSS2_PI_114_DATA 0x00000000 +#define DDRSS2_PI_115_DATA 0x00000000 +#define DDRSS2_PI_116_DATA 0x00000000 +#define DDRSS2_PI_117_DATA 0x00000000 +#define DDRSS2_PI_118_DATA 0x00000000 +#define DDRSS2_PI_119_DATA 0x00000000 +#define DDRSS2_PI_120_DATA 0x00000000 +#define DDRSS2_PI_121_DATA 0x00000000 +#define DDRSS2_PI_122_DATA 0x00000000 +#define DDRSS2_PI_123_DATA 0x00000000 +#define DDRSS2_PI_124_DATA 0x00000000 +#define DDRSS2_PI_125_DATA 0x00000008 +#define DDRSS2_PI_126_DATA 0x00000000 +#define DDRSS2_PI_127_DATA 0x00000000 +#define DDRSS2_PI_128_DATA 0x00000000 +#define DDRSS2_PI_129_DATA 0x00000000 +#define DDRSS2_PI_130_DATA 0x00000000 +#define DDRSS2_PI_131_DATA 0x00000000 +#define DDRSS2_PI_132_DATA 0x00000000 +#define DDRSS2_PI_133_DATA 0x00000000 +#define DDRSS2_PI_134_DATA 0x00000002 +#define DDRSS2_PI_135_DATA 0x00000000 +#define DDRSS2_PI_136_DATA 0x00000000 +#define DDRSS2_PI_137_DATA 0x0000000A +#define DDRSS2_PI_138_DATA 0x00000019 +#define DDRSS2_PI_139_DATA 0x00000100 +#define DDRSS2_PI_140_DATA 0x00000000 +#define DDRSS2_PI_141_DATA 0x00000000 +#define DDRSS2_PI_142_DATA 0x00000000 +#define DDRSS2_PI_143_DATA 0x00000000 +#define DDRSS2_PI_144_DATA 0x01000000 +#define DDRSS2_PI_145_DATA 0x00010003 +#define DDRSS2_PI_146_DATA 0x02000101 +#define DDRSS2_PI_147_DATA 0x01030001 +#define DDRSS2_PI_148_DATA 0x00010400 +#define DDRSS2_PI_149_DATA 0x06000105 +#define DDRSS2_PI_150_DATA 0x01070001 +#define DDRSS2_PI_151_DATA 0x00000000 +#define DDRSS2_PI_152_DATA 0x00000000 +#define DDRSS2_PI_153_DATA 0x00000000 +#define DDRSS2_PI_154_DATA 0x00010001 +#define DDRSS2_PI_155_DATA 0x00000000 +#define DDRSS2_PI_156_DATA 0x00000000 +#define DDRSS2_PI_157_DATA 0x00000000 +#define DDRSS2_PI_158_DATA 0x00000000 +#define DDRSS2_PI_159_DATA 0x00000401 +#define DDRSS2_PI_160_DATA 0x00000000 +#define DDRSS2_PI_161_DATA 0x00010000 +#define DDRSS2_PI_162_DATA 0x00000000 +#define DDRSS2_PI_163_DATA 0x2B2B0200 +#define DDRSS2_PI_164_DATA 0x00000034 +#define DDRSS2_PI_165_DATA 0x00000064 +#define DDRSS2_PI_166_DATA 0x00020064 +#define DDRSS2_PI_167_DATA 0x02000200 +#define DDRSS2_PI_168_DATA 0x48120C04 +#define DDRSS2_PI_169_DATA 0x00154812 +#define DDRSS2_PI_170_DATA 0x000000CE +#define DDRSS2_PI_171_DATA 0x0000032B +#define DDRSS2_PI_172_DATA 0x00002073 +#define DDRSS2_PI_173_DATA 0x0000032B +#define DDRSS2_PI_174_DATA 0x04002073 +#define DDRSS2_PI_175_DATA 0x01010404 +#define DDRSS2_PI_176_DATA 0x00001501 +#define DDRSS2_PI_177_DATA 0x00150015 +#define DDRSS2_PI_178_DATA 0x01000100 +#define DDRSS2_PI_179_DATA 0x00000100 +#define DDRSS2_PI_180_DATA 0x00000000 +#define DDRSS2_PI_181_DATA 0x01010101 +#define DDRSS2_PI_182_DATA 0x00000101 +#define DDRSS2_PI_183_DATA 0x00000000 +#define DDRSS2_PI_184_DATA 0x00000000 +#define DDRSS2_PI_185_DATA 0x15040000 +#define DDRSS2_PI_186_DATA 0x0E0E0215 +#define DDRSS2_PI_187_DATA 0x00040402 +#define DDRSS2_PI_188_DATA 0x000D0035 +#define DDRSS2_PI_189_DATA 0x00218049 +#define DDRSS2_PI_190_DATA 0x00218049 +#define DDRSS2_PI_191_DATA 0x01010101 +#define DDRSS2_PI_192_DATA 0x0004000E +#define DDRSS2_PI_193_DATA 0x00040216 +#define DDRSS2_PI_194_DATA 0x01000216 +#define DDRSS2_PI_195_DATA 0x000F000F +#define DDRSS2_PI_196_DATA 0x02170100 +#define DDRSS2_PI_197_DATA 0x01000217 +#define DDRSS2_PI_198_DATA 0x02170217 +#define DDRSS2_PI_199_DATA 0x32103200 +#define DDRSS2_PI_200_DATA 0x01013210 +#define DDRSS2_PI_201_DATA 0x0A070601 +#define DDRSS2_PI_202_DATA 0x1F130A0D +#define DDRSS2_PI_203_DATA 0x1F130A14 +#define DDRSS2_PI_204_DATA 0x0000C014 +#define DDRSS2_PI_205_DATA 0x00C01000 +#define DDRSS2_PI_206_DATA 0x00C01000 +#define DDRSS2_PI_207_DATA 0x00021000 +#define DDRSS2_PI_208_DATA 0x0024000E +#define DDRSS2_PI_209_DATA 0x00240216 +#define DDRSS2_PI_210_DATA 0x00110216 +#define DDRSS2_PI_211_DATA 0x32000056 +#define DDRSS2_PI_212_DATA 0x00000301 +#define DDRSS2_PI_213_DATA 0x005B0036 +#define DDRSS2_PI_214_DATA 0x03013212 +#define DDRSS2_PI_215_DATA 0x00003600 +#define DDRSS2_PI_216_DATA 0x3212005B +#define DDRSS2_PI_217_DATA 0x09000301 +#define DDRSS2_PI_218_DATA 0x04010504 +#define DDRSS2_PI_219_DATA 0x040006C9 +#define DDRSS2_PI_220_DATA 0x0A032001 +#define DDRSS2_PI_221_DATA 0x2C31110A +#define DDRSS2_PI_222_DATA 0x00002918 +#define DDRSS2_PI_223_DATA 0x6001071C +#define DDRSS2_PI_224_DATA 0x1E202008 +#define DDRSS2_PI_225_DATA 0x2C311116 +#define DDRSS2_PI_226_DATA 0x00002918 +#define DDRSS2_PI_227_DATA 0x6001071C +#define DDRSS2_PI_228_DATA 0x1E202008 +#define DDRSS2_PI_229_DATA 0x00019C16 +#define DDRSS2_PI_230_DATA 0x00001018 +#define DDRSS2_PI_231_DATA 0x000040E6 +#define DDRSS2_PI_232_DATA 0x000288FC +#define DDRSS2_PI_233_DATA 0x000040E6 +#define DDRSS2_PI_234_DATA 0x000288FC +#define DDRSS2_PI_235_DATA 0x033B0016 +#define DDRSS2_PI_236_DATA 0x0303033B +#define DDRSS2_PI_237_DATA 0x002AF803 +#define DDRSS2_PI_238_DATA 0x0001ADAF +#define DDRSS2_PI_239_DATA 0x00000005 +#define DDRSS2_PI_240_DATA 0x0000006E +#define DDRSS2_PI_241_DATA 0x00000016 +#define DDRSS2_PI_242_DATA 0x000681C8 +#define DDRSS2_PI_243_DATA 0x0001ADAF +#define DDRSS2_PI_244_DATA 0x00000005 +#define DDRSS2_PI_245_DATA 0x000010A9 +#define DDRSS2_PI_246_DATA 0x0000033B +#define DDRSS2_PI_247_DATA 0x000681C8 +#define DDRSS2_PI_248_DATA 0x0001ADAF +#define DDRSS2_PI_249_DATA 0x00000005 +#define DDRSS2_PI_250_DATA 0x000010A9 +#define DDRSS2_PI_251_DATA 0x0100033B +#define DDRSS2_PI_252_DATA 0x00370040 +#define DDRSS2_PI_253_DATA 0x00010008 +#define DDRSS2_PI_254_DATA 0x08550040 +#define DDRSS2_PI_255_DATA 0x00010040 +#define DDRSS2_PI_256_DATA 0x08550040 +#define DDRSS2_PI_257_DATA 0x00000340 +#define DDRSS2_PI_258_DATA 0x006B006B +#define DDRSS2_PI_259_DATA 0x08040404 +#define DDRSS2_PI_260_DATA 0x00000055 +#define DDRSS2_PI_261_DATA 0x55083C5A +#define DDRSS2_PI_262_DATA 0x5A000000 +#define DDRSS2_PI_263_DATA 0x0055083C +#define DDRSS2_PI_264_DATA 0x3C5A0000 +#define DDRSS2_PI_265_DATA 0x00005508 +#define DDRSS2_PI_266_DATA 0x0C3C5A00 +#define DDRSS2_PI_267_DATA 0x080F0E0D +#define DDRSS2_PI_268_DATA 0x000B0A09 +#define DDRSS2_PI_269_DATA 0x00030201 +#define DDRSS2_PI_270_DATA 0x01000000 +#define DDRSS2_PI_271_DATA 0x04020201 +#define DDRSS2_PI_272_DATA 0x00080804 +#define DDRSS2_PI_273_DATA 0x00000000 +#define DDRSS2_PI_274_DATA 0x00000000 +#define DDRSS2_PI_275_DATA 0x00330084 +#define DDRSS2_PI_276_DATA 0x00160000 +#define DDRSS2_PI_277_DATA 0x35333FF4 +#define DDRSS2_PI_278_DATA 0x00160F27 +#define DDRSS2_PI_279_DATA 0x35333FF4 +#define DDRSS2_PI_280_DATA 0x00160F27 +#define DDRSS2_PI_281_DATA 0x00330084 +#define DDRSS2_PI_282_DATA 0x00160000 +#define DDRSS2_PI_283_DATA 0x35333FF4 +#define DDRSS2_PI_284_DATA 0x00160F27 +#define DDRSS2_PI_285_DATA 0x35333FF4 +#define DDRSS2_PI_286_DATA 0x00160F27 +#define DDRSS2_PI_287_DATA 0x00330084 +#define DDRSS2_PI_288_DATA 0x00160000 +#define DDRSS2_PI_289_DATA 0x35333FF4 +#define DDRSS2_PI_290_DATA 0x00160F27 +#define DDRSS2_PI_291_DATA 0x35333FF4 +#define DDRSS2_PI_292_DATA 0x00160F27 +#define DDRSS2_PI_293_DATA 0x00330084 +#define DDRSS2_PI_294_DATA 0x00160000 +#define DDRSS2_PI_295_DATA 0x35333FF4 +#define DDRSS2_PI_296_DATA 0x00160F27 +#define DDRSS2_PI_297_DATA 0x35333FF4 +#define DDRSS2_PI_298_DATA 0x00160F27 +#define DDRSS2_PI_299_DATA 0x00000000 + +#define DDRSS2_PHY_00_DATA 0x000004F0 +#define DDRSS2_PHY_01_DATA 0x00000000 +#define DDRSS2_PHY_02_DATA 0x00030200 +#define DDRSS2_PHY_03_DATA 0x00000000 +#define DDRSS2_PHY_04_DATA 0x00000000 +#define DDRSS2_PHY_05_DATA 0x01030000 +#define DDRSS2_PHY_06_DATA 0x00010000 +#define DDRSS2_PHY_07_DATA 0x01030004 +#define DDRSS2_PHY_08_DATA 0x01000000 +#define DDRSS2_PHY_09_DATA 0x00000000 +#define DDRSS2_PHY_10_DATA 0x00000000 +#define DDRSS2_PHY_11_DATA 0x01000001 +#define DDRSS2_PHY_12_DATA 0x00000100 +#define DDRSS2_PHY_13_DATA 0x000800C0 +#define DDRSS2_PHY_14_DATA 0x060100CC +#define DDRSS2_PHY_15_DATA 0x00030066 +#define DDRSS2_PHY_16_DATA 0x00000000 +#define DDRSS2_PHY_17_DATA 0x00000301 +#define DDRSS2_PHY_18_DATA 0x0000AAAA +#define DDRSS2_PHY_19_DATA 0x00005555 +#define DDRSS2_PHY_20_DATA 0x0000B5B5 +#define DDRSS2_PHY_21_DATA 0x00004A4A +#define DDRSS2_PHY_22_DATA 0x00005656 +#define DDRSS2_PHY_23_DATA 0x0000A9A9 +#define DDRSS2_PHY_24_DATA 0x0000A9A9 +#define DDRSS2_PHY_25_DATA 0x0000B5B5 +#define DDRSS2_PHY_26_DATA 0x00000000 +#define DDRSS2_PHY_27_DATA 0x00000000 +#define DDRSS2_PHY_28_DATA 0x2A000000 +#define DDRSS2_PHY_29_DATA 0x00000808 +#define DDRSS2_PHY_30_DATA 0x0F000000 +#define DDRSS2_PHY_31_DATA 0x00000F0F +#define DDRSS2_PHY_32_DATA 0x10400000 +#define DDRSS2_PHY_33_DATA 0x0C002006 +#define DDRSS2_PHY_34_DATA 0x00000000 +#define DDRSS2_PHY_35_DATA 0x00000000 +#define DDRSS2_PHY_36_DATA 0x55555555 +#define DDRSS2_PHY_37_DATA 0xAAAAAAAA +#define DDRSS2_PHY_38_DATA 0x55555555 +#define DDRSS2_PHY_39_DATA 0xAAAAAAAA +#define DDRSS2_PHY_40_DATA 0x00005555 +#define DDRSS2_PHY_41_DATA 0x01000100 +#define DDRSS2_PHY_42_DATA 0x00800180 +#define DDRSS2_PHY_43_DATA 0x00000001 +#define DDRSS2_PHY_44_DATA 0x00000000 +#define DDRSS2_PHY_45_DATA 0x00000000 +#define DDRSS2_PHY_46_DATA 0x00000000 +#define DDRSS2_PHY_47_DATA 0x00000000 +#define DDRSS2_PHY_48_DATA 0x00000000 +#define DDRSS2_PHY_49_DATA 0x00000000 +#define DDRSS2_PHY_50_DATA 0x00000000 +#define DDRSS2_PHY_51_DATA 0x00000000 +#define DDRSS2_PHY_52_DATA 0x00000000 +#define DDRSS2_PHY_53_DATA 0x00000000 +#define DDRSS2_PHY_54_DATA 0x00000000 +#define DDRSS2_PHY_55_DATA 0x00000000 +#define DDRSS2_PHY_56_DATA 0x00000000 +#define DDRSS2_PHY_57_DATA 0x00000000 +#define DDRSS2_PHY_58_DATA 0x00000000 +#define DDRSS2_PHY_59_DATA 0x00000000 +#define DDRSS2_PHY_60_DATA 0x00000000 +#define DDRSS2_PHY_61_DATA 0x00000000 +#define DDRSS2_PHY_62_DATA 0x00000000 +#define DDRSS2_PHY_63_DATA 0x00000000 +#define DDRSS2_PHY_64_DATA 0x00000000 +#define DDRSS2_PHY_65_DATA 0x00000000 +#define DDRSS2_PHY_66_DATA 0x00000104 +#define DDRSS2_PHY_67_DATA 0x00000120 +#define DDRSS2_PHY_68_DATA 0x00000000 +#define DDRSS2_PHY_69_DATA 0x00000000 +#define DDRSS2_PHY_70_DATA 0x00000000 +#define DDRSS2_PHY_71_DATA 0x00000000 +#define DDRSS2_PHY_72_DATA 0x00000000 +#define DDRSS2_PHY_73_DATA 0x00000000 +#define DDRSS2_PHY_74_DATA 0x00000000 +#define DDRSS2_PHY_75_DATA 0x00000001 +#define DDRSS2_PHY_76_DATA 0x07FF0000 +#define DDRSS2_PHY_77_DATA 0x0080081F +#define DDRSS2_PHY_78_DATA 0x00081020 +#define DDRSS2_PHY_79_DATA 0x04010000 +#define DDRSS2_PHY_80_DATA 0x00000000 +#define DDRSS2_PHY_81_DATA 0x00000000 +#define DDRSS2_PHY_82_DATA 0x00000000 +#define DDRSS2_PHY_83_DATA 0x00000100 +#define DDRSS2_PHY_84_DATA 0x01CC0C01 +#define DDRSS2_PHY_85_DATA 0x1003CC0C +#define DDRSS2_PHY_86_DATA 0x20000140 +#define DDRSS2_PHY_87_DATA 0x07FF0200 +#define DDRSS2_PHY_88_DATA 0x0000DD01 +#define DDRSS2_PHY_89_DATA 0x10100303 +#define DDRSS2_PHY_90_DATA 0x10101010 +#define DDRSS2_PHY_91_DATA 0x10101010 +#define DDRSS2_PHY_92_DATA 0x00021010 +#define DDRSS2_PHY_93_DATA 0x00100010 +#define DDRSS2_PHY_94_DATA 0x00100010 +#define DDRSS2_PHY_95_DATA 0x00100010 +#define DDRSS2_PHY_96_DATA 0x00100010 +#define DDRSS2_PHY_97_DATA 0x00050010 +#define DDRSS2_PHY_98_DATA 0x51517041 +#define DDRSS2_PHY_99_DATA 0x31C06001 +#define DDRSS2_PHY_100_DATA 0x07AB0340 +#define DDRSS2_PHY_101_DATA 0x00C0C001 +#define DDRSS2_PHY_102_DATA 0x0E0D0001 +#define DDRSS2_PHY_103_DATA 0x10001000 +#define DDRSS2_PHY_104_DATA 0x0C083E42 +#define DDRSS2_PHY_105_DATA 0x0F0C3701 +#define DDRSS2_PHY_106_DATA 0x01000140 +#define DDRSS2_PHY_107_DATA 0x0C000420 +#define DDRSS2_PHY_108_DATA 0x00000198 +#define DDRSS2_PHY_109_DATA 0x0A0000D0 +#define DDRSS2_PHY_110_DATA 0x00030200 +#define DDRSS2_PHY_111_DATA 0x02800000 +#define DDRSS2_PHY_112_DATA 0x80800000 +#define DDRSS2_PHY_113_DATA 0x000E2010 +#define DDRSS2_PHY_114_DATA 0x76543210 +#define DDRSS2_PHY_115_DATA 0x00000008 +#define DDRSS2_PHY_116_DATA 0x02800280 +#define DDRSS2_PHY_117_DATA 0x02800280 +#define DDRSS2_PHY_118_DATA 0x02800280 +#define DDRSS2_PHY_119_DATA 0x02800280 +#define DDRSS2_PHY_120_DATA 0x00000280 +#define DDRSS2_PHY_121_DATA 0x0000A000 +#define DDRSS2_PHY_122_DATA 0x00A000A0 +#define DDRSS2_PHY_123_DATA 0x00A000A0 +#define DDRSS2_PHY_124_DATA 0x00A000A0 +#define DDRSS2_PHY_125_DATA 0x00A000A0 +#define DDRSS2_PHY_126_DATA 0x00A000A0 +#define DDRSS2_PHY_127_DATA 0x00A000A0 +#define DDRSS2_PHY_128_DATA 0x00A000A0 +#define DDRSS2_PHY_129_DATA 0x00A000A0 +#define DDRSS2_PHY_130_DATA 0x01C200A0 +#define DDRSS2_PHY_131_DATA 0x01A00005 +#define DDRSS2_PHY_132_DATA 0x00000000 +#define DDRSS2_PHY_133_DATA 0x00000000 +#define DDRSS2_PHY_134_DATA 0x00080200 +#define DDRSS2_PHY_135_DATA 0x00000000 +#define DDRSS2_PHY_136_DATA 0x20202000 +#define DDRSS2_PHY_137_DATA 0x20202020 +#define DDRSS2_PHY_138_DATA 0xF0F02020 +#define DDRSS2_PHY_139_DATA 0x00000000 +#define DDRSS2_PHY_140_DATA 0x00000000 +#define DDRSS2_PHY_141_DATA 0x00000000 +#define DDRSS2_PHY_142_DATA 0x00000000 +#define DDRSS2_PHY_143_DATA 0x00000000 +#define DDRSS2_PHY_144_DATA 0x00000000 +#define DDRSS2_PHY_145_DATA 0x00000000 +#define DDRSS2_PHY_146_DATA 0x00000000 +#define DDRSS2_PHY_147_DATA 0x00000000 +#define DDRSS2_PHY_148_DATA 0x00000000 +#define DDRSS2_PHY_149_DATA 0x00000000 +#define DDRSS2_PHY_150_DATA 0x00000000 +#define DDRSS2_PHY_151_DATA 0x00000000 +#define DDRSS2_PHY_152_DATA 0x00000000 +#define DDRSS2_PHY_153_DATA 0x00000000 +#define DDRSS2_PHY_154_DATA 0x00000000 +#define DDRSS2_PHY_155_DATA 0x00000000 +#define DDRSS2_PHY_156_DATA 0x00000000 +#define DDRSS2_PHY_157_DATA 0x00000000 +#define DDRSS2_PHY_158_DATA 0x00000000 +#define DDRSS2_PHY_159_DATA 0x00000000 +#define DDRSS2_PHY_160_DATA 0x00000000 +#define DDRSS2_PHY_161_DATA 0x00000000 +#define DDRSS2_PHY_162_DATA 0x00000000 +#define DDRSS2_PHY_163_DATA 0x00000000 +#define DDRSS2_PHY_164_DATA 0x00000000 +#define DDRSS2_PHY_165_DATA 0x00000000 +#define DDRSS2_PHY_166_DATA 0x00000000 +#define DDRSS2_PHY_167_DATA 0x00000000 +#define DDRSS2_PHY_168_DATA 0x00000000 +#define DDRSS2_PHY_169_DATA 0x00000000 +#define DDRSS2_PHY_170_DATA 0x00000000 +#define DDRSS2_PHY_171_DATA 0x00000000 +#define DDRSS2_PHY_172_DATA 0x00000000 +#define DDRSS2_PHY_173_DATA 0x00000000 +#define DDRSS2_PHY_174_DATA 0x00000000 +#define DDRSS2_PHY_175_DATA 0x00000000 +#define DDRSS2_PHY_176_DATA 0x00000000 +#define DDRSS2_PHY_177_DATA 0x00000000 +#define DDRSS2_PHY_178_DATA 0x00000000 +#define DDRSS2_PHY_179_DATA 0x00000000 +#define DDRSS2_PHY_180_DATA 0x00000000 +#define DDRSS2_PHY_181_DATA 0x00000000 +#define DDRSS2_PHY_182_DATA 0x00000000 +#define DDRSS2_PHY_183_DATA 0x00000000 +#define DDRSS2_PHY_184_DATA 0x00000000 +#define DDRSS2_PHY_185_DATA 0x00000000 +#define DDRSS2_PHY_186_DATA 0x00000000 +#define DDRSS2_PHY_187_DATA 0x00000000 +#define DDRSS2_PHY_188_DATA 0x00000000 +#define DDRSS2_PHY_189_DATA 0x00000000 +#define DDRSS2_PHY_190_DATA 0x00000000 +#define DDRSS2_PHY_191_DATA 0x00000000 +#define DDRSS2_PHY_192_DATA 0x00000000 +#define DDRSS2_PHY_193_DATA 0x00000000 +#define DDRSS2_PHY_194_DATA 0x00000000 +#define DDRSS2_PHY_195_DATA 0x00000000 +#define DDRSS2_PHY_196_DATA 0x00000000 +#define DDRSS2_PHY_197_DATA 0x00000000 +#define DDRSS2_PHY_198_DATA 0x00000000 +#define DDRSS2_PHY_199_DATA 0x00000000 +#define DDRSS2_PHY_200_DATA 0x00000000 +#define DDRSS2_PHY_201_DATA 0x00000000 +#define DDRSS2_PHY_202_DATA 0x00000000 +#define DDRSS2_PHY_203_DATA 0x00000000 +#define DDRSS2_PHY_204_DATA 0x00000000 +#define DDRSS2_PHY_205_DATA 0x00000000 +#define DDRSS2_PHY_206_DATA 0x00000000 +#define DDRSS2_PHY_207_DATA 0x00000000 +#define DDRSS2_PHY_208_DATA 0x00000000 +#define DDRSS2_PHY_209_DATA 0x00000000 +#define DDRSS2_PHY_210_DATA 0x00000000 +#define DDRSS2_PHY_211_DATA 0x00000000 +#define DDRSS2_PHY_212_DATA 0x00000000 +#define DDRSS2_PHY_213_DATA 0x00000000 +#define DDRSS2_PHY_214_DATA 0x00000000 +#define DDRSS2_PHY_215_DATA 0x00000000 +#define DDRSS2_PHY_216_DATA 0x00000000 +#define DDRSS2_PHY_217_DATA 0x00000000 +#define DDRSS2_PHY_218_DATA 0x00000000 +#define DDRSS2_PHY_219_DATA 0x00000000 +#define DDRSS2_PHY_220_DATA 0x00000000 +#define DDRSS2_PHY_221_DATA 0x00000000 +#define DDRSS2_PHY_222_DATA 0x00000000 +#define DDRSS2_PHY_223_DATA 0x00000000 +#define DDRSS2_PHY_224_DATA 0x00000000 +#define DDRSS2_PHY_225_DATA 0x00000000 +#define DDRSS2_PHY_226_DATA 0x00000000 +#define DDRSS2_PHY_227_DATA 0x00000000 +#define DDRSS2_PHY_228_DATA 0x00000000 +#define DDRSS2_PHY_229_DATA 0x00000000 +#define DDRSS2_PHY_230_DATA 0x00000000 +#define DDRSS2_PHY_231_DATA 0x00000000 +#define DDRSS2_PHY_232_DATA 0x00000000 +#define DDRSS2_PHY_233_DATA 0x00000000 +#define DDRSS2_PHY_234_DATA 0x00000000 +#define DDRSS2_PHY_235_DATA 0x00000000 +#define DDRSS2_PHY_236_DATA 0x00000000 +#define DDRSS2_PHY_237_DATA 0x00000000 +#define DDRSS2_PHY_238_DATA 0x00000000 +#define DDRSS2_PHY_239_DATA 0x00000000 +#define DDRSS2_PHY_240_DATA 0x00000000 +#define DDRSS2_PHY_241_DATA 0x00000000 +#define DDRSS2_PHY_242_DATA 0x00000000 +#define DDRSS2_PHY_243_DATA 0x00000000 +#define DDRSS2_PHY_244_DATA 0x00000000 +#define DDRSS2_PHY_245_DATA 0x00000000 +#define DDRSS2_PHY_246_DATA 0x00000000 +#define DDRSS2_PHY_247_DATA 0x00000000 +#define DDRSS2_PHY_248_DATA 0x00000000 +#define DDRSS2_PHY_249_DATA 0x00000000 +#define DDRSS2_PHY_250_DATA 0x00000000 +#define DDRSS2_PHY_251_DATA 0x00000000 +#define DDRSS2_PHY_252_DATA 0x00000000 +#define DDRSS2_PHY_253_DATA 0x00000000 +#define DDRSS2_PHY_254_DATA 0x00000000 +#define DDRSS2_PHY_255_DATA 0x00000000 +#define DDRSS2_PHY_256_DATA 0x000004F0 +#define DDRSS2_PHY_257_DATA 0x00000000 +#define DDRSS2_PHY_258_DATA 0x00030200 +#define DDRSS2_PHY_259_DATA 0x00000000 +#define DDRSS2_PHY_260_DATA 0x00000000 +#define DDRSS2_PHY_261_DATA 0x01030000 +#define DDRSS2_PHY_262_DATA 0x00010000 +#define DDRSS2_PHY_263_DATA 0x01030004 +#define DDRSS2_PHY_264_DATA 0x01000000 +#define DDRSS2_PHY_265_DATA 0x00000000 +#define DDRSS2_PHY_266_DATA 0x00000000 +#define DDRSS2_PHY_267_DATA 0x01000001 +#define DDRSS2_PHY_268_DATA 0x00000100 +#define DDRSS2_PHY_269_DATA 0x000800C0 +#define DDRSS2_PHY_270_DATA 0x060100CC +#define DDRSS2_PHY_271_DATA 0x00030066 +#define DDRSS2_PHY_272_DATA 0x00000000 +#define DDRSS2_PHY_273_DATA 0x00000301 +#define DDRSS2_PHY_274_DATA 0x0000AAAA +#define DDRSS2_PHY_275_DATA 0x00005555 +#define DDRSS2_PHY_276_DATA 0x0000B5B5 +#define DDRSS2_PHY_277_DATA 0x00004A4A +#define DDRSS2_PHY_278_DATA 0x00005656 +#define DDRSS2_PHY_279_DATA 0x0000A9A9 +#define DDRSS2_PHY_280_DATA 0x0000A9A9 +#define DDRSS2_PHY_281_DATA 0x0000B5B5 +#define DDRSS2_PHY_282_DATA 0x00000000 +#define DDRSS2_PHY_283_DATA 0x00000000 +#define DDRSS2_PHY_284_DATA 0x2A000000 +#define DDRSS2_PHY_285_DATA 0x00000808 +#define DDRSS2_PHY_286_DATA 0x0F000000 +#define DDRSS2_PHY_287_DATA 0x00000F0F +#define DDRSS2_PHY_288_DATA 0x10400000 +#define DDRSS2_PHY_289_DATA 0x0C002006 +#define DDRSS2_PHY_290_DATA 0x00000000 +#define DDRSS2_PHY_291_DATA 0x00000000 +#define DDRSS2_PHY_292_DATA 0x55555555 +#define DDRSS2_PHY_293_DATA 0xAAAAAAAA +#define DDRSS2_PHY_294_DATA 0x55555555 +#define DDRSS2_PHY_295_DATA 0xAAAAAAAA +#define DDRSS2_PHY_296_DATA 0x00005555 +#define DDRSS2_PHY_297_DATA 0x01000100 +#define DDRSS2_PHY_298_DATA 0x00800180 +#define DDRSS2_PHY_299_DATA 0x00000000 +#define DDRSS2_PHY_300_DATA 0x00000000 +#define DDRSS2_PHY_301_DATA 0x00000000 +#define DDRSS2_PHY_302_DATA 0x00000000 +#define DDRSS2_PHY_303_DATA 0x00000000 +#define DDRSS2_PHY_304_DATA 0x00000000 +#define DDRSS2_PHY_305_DATA 0x00000000 +#define DDRSS2_PHY_306_DATA 0x00000000 +#define DDRSS2_PHY_307_DATA 0x00000000 +#define DDRSS2_PHY_308_DATA 0x00000000 +#define DDRSS2_PHY_309_DATA 0x00000000 +#define DDRSS2_PHY_310_DATA 0x00000000 +#define DDRSS2_PHY_311_DATA 0x00000000 +#define DDRSS2_PHY_312_DATA 0x00000000 +#define DDRSS2_PHY_313_DATA 0x00000000 +#define DDRSS2_PHY_314_DATA 0x00000000 +#define DDRSS2_PHY_315_DATA 0x00000000 +#define DDRSS2_PHY_316_DATA 0x00000000 +#define DDRSS2_PHY_317_DATA 0x00000000 +#define DDRSS2_PHY_318_DATA 0x00000000 +#define DDRSS2_PHY_319_DATA 0x00000000 +#define DDRSS2_PHY_320_DATA 0x00000000 +#define DDRSS2_PHY_321_DATA 0x00000000 +#define DDRSS2_PHY_322_DATA 0x00000104 +#define DDRSS2_PHY_323_DATA 0x00000120 +#define DDRSS2_PHY_324_DATA 0x00000000 +#define DDRSS2_PHY_325_DATA 0x00000000 +#define DDRSS2_PHY_326_DATA 0x00000000 +#define DDRSS2_PHY_327_DATA 0x00000000 +#define DDRSS2_PHY_328_DATA 0x00000000 +#define DDRSS2_PHY_329_DATA 0x00000000 +#define DDRSS2_PHY_330_DATA 0x00000000 +#define DDRSS2_PHY_331_DATA 0x00000001 +#define DDRSS2_PHY_332_DATA 0x07FF0000 +#define DDRSS2_PHY_333_DATA 0x0080081F +#define DDRSS2_PHY_334_DATA 0x00081020 +#define DDRSS2_PHY_335_DATA 0x04010000 +#define DDRSS2_PHY_336_DATA 0x00000000 +#define DDRSS2_PHY_337_DATA 0x00000000 +#define DDRSS2_PHY_338_DATA 0x00000000 +#define DDRSS2_PHY_339_DATA 0x00000100 +#define DDRSS2_PHY_340_DATA 0x01CC0C01 +#define DDRSS2_PHY_341_DATA 0x1003CC0C +#define DDRSS2_PHY_342_DATA 0x20000140 +#define DDRSS2_PHY_343_DATA 0x07FF0200 +#define DDRSS2_PHY_344_DATA 0x0000DD01 +#define DDRSS2_PHY_345_DATA 0x10100303 +#define DDRSS2_PHY_346_DATA 0x10101010 +#define DDRSS2_PHY_347_DATA 0x10101010 +#define DDRSS2_PHY_348_DATA 0x00021010 +#define DDRSS2_PHY_349_DATA 0x00100010 +#define DDRSS2_PHY_350_DATA 0x00100010 +#define DDRSS2_PHY_351_DATA 0x00100010 +#define DDRSS2_PHY_352_DATA 0x00100010 +#define DDRSS2_PHY_353_DATA 0x00050010 +#define DDRSS2_PHY_354_DATA 0x51517041 +#define DDRSS2_PHY_355_DATA 0x31C06001 +#define DDRSS2_PHY_356_DATA 0x07AB0340 +#define DDRSS2_PHY_357_DATA 0x00C0C001 +#define DDRSS2_PHY_358_DATA 0x0E0D0001 +#define DDRSS2_PHY_359_DATA 0x10001000 +#define DDRSS2_PHY_360_DATA 0x0C083E42 +#define DDRSS2_PHY_361_DATA 0x0F0C3701 +#define DDRSS2_PHY_362_DATA 0x01000140 +#define DDRSS2_PHY_363_DATA 0x0C000420 +#define DDRSS2_PHY_364_DATA 0x00000198 +#define DDRSS2_PHY_365_DATA 0x0A0000D0 +#define DDRSS2_PHY_366_DATA 0x00030200 +#define DDRSS2_PHY_367_DATA 0x02800000 +#define DDRSS2_PHY_368_DATA 0x80800000 +#define DDRSS2_PHY_369_DATA 0x000E2010 +#define DDRSS2_PHY_370_DATA 0x76543210 +#define DDRSS2_PHY_371_DATA 0x00000008 +#define DDRSS2_PHY_372_DATA 0x02800280 +#define DDRSS2_PHY_373_DATA 0x02800280 +#define DDRSS2_PHY_374_DATA 0x02800280 +#define DDRSS2_PHY_375_DATA 0x02800280 +#define DDRSS2_PHY_376_DATA 0x00000280 +#define DDRSS2_PHY_377_DATA 0x0000A000 +#define DDRSS2_PHY_378_DATA 0x00A000A0 +#define DDRSS2_PHY_379_DATA 0x00A000A0 +#define DDRSS2_PHY_380_DATA 0x00A000A0 +#define DDRSS2_PHY_381_DATA 0x00A000A0 +#define DDRSS2_PHY_382_DATA 0x00A000A0 +#define DDRSS2_PHY_383_DATA 0x00A000A0 +#define DDRSS2_PHY_384_DATA 0x00A000A0 +#define DDRSS2_PHY_385_DATA 0x00A000A0 +#define DDRSS2_PHY_386_DATA 0x01C200A0 +#define DDRSS2_PHY_387_DATA 0x01A00005 +#define DDRSS2_PHY_388_DATA 0x00000000 +#define DDRSS2_PHY_389_DATA 0x00000000 +#define DDRSS2_PHY_390_DATA 0x00080200 +#define DDRSS2_PHY_391_DATA 0x00000000 +#define DDRSS2_PHY_392_DATA 0x20202000 +#define DDRSS2_PHY_393_DATA 0x20202020 +#define DDRSS2_PHY_394_DATA 0xF0F02020 +#define DDRSS2_PHY_395_DATA 0x00000000 +#define DDRSS2_PHY_396_DATA 0x00000000 +#define DDRSS2_PHY_397_DATA 0x00000000 +#define DDRSS2_PHY_398_DATA 0x00000000 +#define DDRSS2_PHY_399_DATA 0x00000000 +#define DDRSS2_PHY_400_DATA 0x00000000 +#define DDRSS2_PHY_401_DATA 0x00000000 +#define DDRSS2_PHY_402_DATA 0x00000000 +#define DDRSS2_PHY_403_DATA 0x00000000 +#define DDRSS2_PHY_404_DATA 0x00000000 +#define DDRSS2_PHY_405_DATA 0x00000000 +#define DDRSS2_PHY_406_DATA 0x00000000 +#define DDRSS2_PHY_407_DATA 0x00000000 +#define DDRSS2_PHY_408_DATA 0x00000000 +#define DDRSS2_PHY_409_DATA 0x00000000 +#define DDRSS2_PHY_410_DATA 0x00000000 +#define DDRSS2_PHY_411_DATA 0x00000000 +#define DDRSS2_PHY_412_DATA 0x00000000 +#define DDRSS2_PHY_413_DATA 0x00000000 +#define DDRSS2_PHY_414_DATA 0x00000000 +#define DDRSS2_PHY_415_DATA 0x00000000 +#define DDRSS2_PHY_416_DATA 0x00000000 +#define DDRSS2_PHY_417_DATA 0x00000000 +#define DDRSS2_PHY_418_DATA 0x00000000 +#define DDRSS2_PHY_419_DATA 0x00000000 +#define DDRSS2_PHY_420_DATA 0x00000000 +#define DDRSS2_PHY_421_DATA 0x00000000 +#define DDRSS2_PHY_422_DATA 0x00000000 +#define DDRSS2_PHY_423_DATA 0x00000000 +#define DDRSS2_PHY_424_DATA 0x00000000 +#define DDRSS2_PHY_425_DATA 0x00000000 +#define DDRSS2_PHY_426_DATA 0x00000000 +#define DDRSS2_PHY_427_DATA 0x00000000 +#define DDRSS2_PHY_428_DATA 0x00000000 +#define DDRSS2_PHY_429_DATA 0x00000000 +#define DDRSS2_PHY_430_DATA 0x00000000 +#define DDRSS2_PHY_431_DATA 0x00000000 +#define DDRSS2_PHY_432_DATA 0x00000000 +#define DDRSS2_PHY_433_DATA 0x00000000 +#define DDRSS2_PHY_434_DATA 0x00000000 +#define DDRSS2_PHY_435_DATA 0x00000000 +#define DDRSS2_PHY_436_DATA 0x00000000 +#define DDRSS2_PHY_437_DATA 0x00000000 +#define DDRSS2_PHY_438_DATA 0x00000000 +#define DDRSS2_PHY_439_DATA 0x00000000 +#define DDRSS2_PHY_440_DATA 0x00000000 +#define DDRSS2_PHY_441_DATA 0x00000000 +#define DDRSS2_PHY_442_DATA 0x00000000 +#define DDRSS2_PHY_443_DATA 0x00000000 +#define DDRSS2_PHY_444_DATA 0x00000000 +#define DDRSS2_PHY_445_DATA 0x00000000 +#define DDRSS2_PHY_446_DATA 0x00000000 +#define DDRSS2_PHY_447_DATA 0x00000000 +#define DDRSS2_PHY_448_DATA 0x00000000 +#define DDRSS2_PHY_449_DATA 0x00000000 +#define DDRSS2_PHY_450_DATA 0x00000000 +#define DDRSS2_PHY_451_DATA 0x00000000 +#define DDRSS2_PHY_452_DATA 0x00000000 +#define DDRSS2_PHY_453_DATA 0x00000000 +#define DDRSS2_PHY_454_DATA 0x00000000 +#define DDRSS2_PHY_455_DATA 0x00000000 +#define DDRSS2_PHY_456_DATA 0x00000000 +#define DDRSS2_PHY_457_DATA 0x00000000 +#define DDRSS2_PHY_458_DATA 0x00000000 +#define DDRSS2_PHY_459_DATA 0x00000000 +#define DDRSS2_PHY_460_DATA 0x00000000 +#define DDRSS2_PHY_461_DATA 0x00000000 +#define DDRSS2_PHY_462_DATA 0x00000000 +#define DDRSS2_PHY_463_DATA 0x00000000 +#define DDRSS2_PHY_464_DATA 0x00000000 +#define DDRSS2_PHY_465_DATA 0x00000000 +#define DDRSS2_PHY_466_DATA 0x00000000 +#define DDRSS2_PHY_467_DATA 0x00000000 +#define DDRSS2_PHY_468_DATA 0x00000000 +#define DDRSS2_PHY_469_DATA 0x00000000 +#define DDRSS2_PHY_470_DATA 0x00000000 +#define DDRSS2_PHY_471_DATA 0x00000000 +#define DDRSS2_PHY_472_DATA 0x00000000 +#define DDRSS2_PHY_473_DATA 0x00000000 +#define DDRSS2_PHY_474_DATA 0x00000000 +#define DDRSS2_PHY_475_DATA 0x00000000 +#define DDRSS2_PHY_476_DATA 0x00000000 +#define DDRSS2_PHY_477_DATA 0x00000000 +#define DDRSS2_PHY_478_DATA 0x00000000 +#define DDRSS2_PHY_479_DATA 0x00000000 +#define DDRSS2_PHY_480_DATA 0x00000000 +#define DDRSS2_PHY_481_DATA 0x00000000 +#define DDRSS2_PHY_482_DATA 0x00000000 +#define DDRSS2_PHY_483_DATA 0x00000000 +#define DDRSS2_PHY_484_DATA 0x00000000 +#define DDRSS2_PHY_485_DATA 0x00000000 +#define DDRSS2_PHY_486_DATA 0x00000000 +#define DDRSS2_PHY_487_DATA 0x00000000 +#define DDRSS2_PHY_488_DATA 0x00000000 +#define DDRSS2_PHY_489_DATA 0x00000000 +#define DDRSS2_PHY_490_DATA 0x00000000 +#define DDRSS2_PHY_491_DATA 0x00000000 +#define DDRSS2_PHY_492_DATA 0x00000000 +#define DDRSS2_PHY_493_DATA 0x00000000 +#define DDRSS2_PHY_494_DATA 0x00000000 +#define DDRSS2_PHY_495_DATA 0x00000000 +#define DDRSS2_PHY_496_DATA 0x00000000 +#define DDRSS2_PHY_497_DATA 0x00000000 +#define DDRSS2_PHY_498_DATA 0x00000000 +#define DDRSS2_PHY_499_DATA 0x00000000 +#define DDRSS2_PHY_500_DATA 0x00000000 +#define DDRSS2_PHY_501_DATA 0x00000000 +#define DDRSS2_PHY_502_DATA 0x00000000 +#define DDRSS2_PHY_503_DATA 0x00000000 +#define DDRSS2_PHY_504_DATA 0x00000000 +#define DDRSS2_PHY_505_DATA 0x00000000 +#define DDRSS2_PHY_506_DATA 0x00000000 +#define DDRSS2_PHY_507_DATA 0x00000000 +#define DDRSS2_PHY_508_DATA 0x00000000 +#define DDRSS2_PHY_509_DATA 0x00000000 +#define DDRSS2_PHY_510_DATA 0x00000000 +#define DDRSS2_PHY_511_DATA 0x00000000 +#define DDRSS2_PHY_512_DATA 0x000004F0 +#define DDRSS2_PHY_513_DATA 0x00000000 +#define DDRSS2_PHY_514_DATA 0x00030200 +#define DDRSS2_PHY_515_DATA 0x00000000 +#define DDRSS2_PHY_516_DATA 0x00000000 +#define DDRSS2_PHY_517_DATA 0x01030000 +#define DDRSS2_PHY_518_DATA 0x00010000 +#define DDRSS2_PHY_519_DATA 0x01030004 +#define DDRSS2_PHY_520_DATA 0x01000000 +#define DDRSS2_PHY_521_DATA 0x00000000 +#define DDRSS2_PHY_522_DATA 0x00000000 +#define DDRSS2_PHY_523_DATA 0x01000001 +#define DDRSS2_PHY_524_DATA 0x00000100 +#define DDRSS2_PHY_525_DATA 0x000800C0 +#define DDRSS2_PHY_526_DATA 0x060100CC +#define DDRSS2_PHY_527_DATA 0x00030066 +#define DDRSS2_PHY_528_DATA 0x00000000 +#define DDRSS2_PHY_529_DATA 0x00000301 +#define DDRSS2_PHY_530_DATA 0x0000AAAA +#define DDRSS2_PHY_531_DATA 0x00005555 +#define DDRSS2_PHY_532_DATA 0x0000B5B5 +#define DDRSS2_PHY_533_DATA 0x00004A4A +#define DDRSS2_PHY_534_DATA 0x00005656 +#define DDRSS2_PHY_535_DATA 0x0000A9A9 +#define DDRSS2_PHY_536_DATA 0x0000A9A9 +#define DDRSS2_PHY_537_DATA 0x0000B5B5 +#define DDRSS2_PHY_538_DATA 0x00000000 +#define DDRSS2_PHY_539_DATA 0x00000000 +#define DDRSS2_PHY_540_DATA 0x2A000000 +#define DDRSS2_PHY_541_DATA 0x00000808 +#define DDRSS2_PHY_542_DATA 0x0F000000 +#define DDRSS2_PHY_543_DATA 0x00000F0F +#define DDRSS2_PHY_544_DATA 0x10400000 +#define DDRSS2_PHY_545_DATA 0x0C002006 +#define DDRSS2_PHY_546_DATA 0x00000000 +#define DDRSS2_PHY_547_DATA 0x00000000 +#define DDRSS2_PHY_548_DATA 0x55555555 +#define DDRSS2_PHY_549_DATA 0xAAAAAAAA +#define DDRSS2_PHY_550_DATA 0x55555555 +#define DDRSS2_PHY_551_DATA 0xAAAAAAAA +#define DDRSS2_PHY_552_DATA 0x00005555 +#define DDRSS2_PHY_553_DATA 0x01000100 +#define DDRSS2_PHY_554_DATA 0x00800180 +#define DDRSS2_PHY_555_DATA 0x00000001 +#define DDRSS2_PHY_556_DATA 0x00000000 +#define DDRSS2_PHY_557_DATA 0x00000000 +#define DDRSS2_PHY_558_DATA 0x00000000 +#define DDRSS2_PHY_559_DATA 0x00000000 +#define DDRSS2_PHY_560_DATA 0x00000000 +#define DDRSS2_PHY_561_DATA 0x00000000 +#define DDRSS2_PHY_562_DATA 0x00000000 +#define DDRSS2_PHY_563_DATA 0x00000000 +#define DDRSS2_PHY_564_DATA 0x00000000 +#define DDRSS2_PHY_565_DATA 0x00000000 +#define DDRSS2_PHY_566_DATA 0x00000000 +#define DDRSS2_PHY_567_DATA 0x00000000 +#define DDRSS2_PHY_568_DATA 0x00000000 +#define DDRSS2_PHY_569_DATA 0x00000000 +#define DDRSS2_PHY_570_DATA 0x00000000 +#define DDRSS2_PHY_571_DATA 0x00000000 +#define DDRSS2_PHY_572_DATA 0x00000000 +#define DDRSS2_PHY_573_DATA 0x00000000 +#define DDRSS2_PHY_574_DATA 0x00000000 +#define DDRSS2_PHY_575_DATA 0x00000000 +#define DDRSS2_PHY_576_DATA 0x00000000 +#define DDRSS2_PHY_577_DATA 0x00000000 +#define DDRSS2_PHY_578_DATA 0x00000104 +#define DDRSS2_PHY_579_DATA 0x00000120 +#define DDRSS2_PHY_580_DATA 0x00000000 +#define DDRSS2_PHY_581_DATA 0x00000000 +#define DDRSS2_PHY_582_DATA 0x00000000 +#define DDRSS2_PHY_583_DATA 0x00000000 +#define DDRSS2_PHY_584_DATA 0x00000000 +#define DDRSS2_PHY_585_DATA 0x00000000 +#define DDRSS2_PHY_586_DATA 0x00000000 +#define DDRSS2_PHY_587_DATA 0x00000001 +#define DDRSS2_PHY_588_DATA 0x07FF0000 +#define DDRSS2_PHY_589_DATA 0x0080081F +#define DDRSS2_PHY_590_DATA 0x00081020 +#define DDRSS2_PHY_591_DATA 0x04010000 +#define DDRSS2_PHY_592_DATA 0x00000000 +#define DDRSS2_PHY_593_DATA 0x00000000 +#define DDRSS2_PHY_594_DATA 0x00000000 +#define DDRSS2_PHY_595_DATA 0x00000100 +#define DDRSS2_PHY_596_DATA 0x01CC0C01 +#define DDRSS2_PHY_597_DATA 0x1003CC0C +#define DDRSS2_PHY_598_DATA 0x20000140 +#define DDRSS2_PHY_599_DATA 0x07FF0200 +#define DDRSS2_PHY_600_DATA 0x0000DD01 +#define DDRSS2_PHY_601_DATA 0x10100303 +#define DDRSS2_PHY_602_DATA 0x10101010 +#define DDRSS2_PHY_603_DATA 0x10101010 +#define DDRSS2_PHY_604_DATA 0x00021010 +#define DDRSS2_PHY_605_DATA 0x00100010 +#define DDRSS2_PHY_606_DATA 0x00100010 +#define DDRSS2_PHY_607_DATA 0x00100010 +#define DDRSS2_PHY_608_DATA 0x00100010 +#define DDRSS2_PHY_609_DATA 0x00050010 +#define DDRSS2_PHY_610_DATA 0x51517041 +#define DDRSS2_PHY_611_DATA 0x31C06001 +#define DDRSS2_PHY_612_DATA 0x07AB0340 +#define DDRSS2_PHY_613_DATA 0x00C0C001 +#define DDRSS2_PHY_614_DATA 0x0E0D0001 +#define DDRSS2_PHY_615_DATA 0x10001000 +#define DDRSS2_PHY_616_DATA 0x0C083E42 +#define DDRSS2_PHY_617_DATA 0x0F0C3701 +#define DDRSS2_PHY_618_DATA 0x01000140 +#define DDRSS2_PHY_619_DATA 0x0C000420 +#define DDRSS2_PHY_620_DATA 0x00000198 +#define DDRSS2_PHY_621_DATA 0x0A0000D0 +#define DDRSS2_PHY_622_DATA 0x00030200 +#define DDRSS2_PHY_623_DATA 0x02800000 +#define DDRSS2_PHY_624_DATA 0x80800000 +#define DDRSS2_PHY_625_DATA 0x000E2010 +#define DDRSS2_PHY_626_DATA 0x76543210 +#define DDRSS2_PHY_627_DATA 0x00000008 +#define DDRSS2_PHY_628_DATA 0x02800280 +#define DDRSS2_PHY_629_DATA 0x02800280 +#define DDRSS2_PHY_630_DATA 0x02800280 +#define DDRSS2_PHY_631_DATA 0x02800280 +#define DDRSS2_PHY_632_DATA 0x00000280 +#define DDRSS2_PHY_633_DATA 0x0000A000 +#define DDRSS2_PHY_634_DATA 0x00A000A0 +#define DDRSS2_PHY_635_DATA 0x00A000A0 +#define DDRSS2_PHY_636_DATA 0x00A000A0 +#define DDRSS2_PHY_637_DATA 0x00A000A0 +#define DDRSS2_PHY_638_DATA 0x00A000A0 +#define DDRSS2_PHY_639_DATA 0x00A000A0 +#define DDRSS2_PHY_640_DATA 0x00A000A0 +#define DDRSS2_PHY_641_DATA 0x00A000A0 +#define DDRSS2_PHY_642_DATA 0x01C200A0 +#define DDRSS2_PHY_643_DATA 0x01A00005 +#define DDRSS2_PHY_644_DATA 0x00000000 +#define DDRSS2_PHY_645_DATA 0x00000000 +#define DDRSS2_PHY_646_DATA 0x00080200 +#define DDRSS2_PHY_647_DATA 0x00000000 +#define DDRSS2_PHY_648_DATA 0x20202000 +#define DDRSS2_PHY_649_DATA 0x20202020 +#define DDRSS2_PHY_650_DATA 0xF0F02020 +#define DDRSS2_PHY_651_DATA 0x00000000 +#define DDRSS2_PHY_652_DATA 0x00000000 +#define DDRSS2_PHY_653_DATA 0x00000000 +#define DDRSS2_PHY_654_DATA 0x00000000 +#define DDRSS2_PHY_655_DATA 0x00000000 +#define DDRSS2_PHY_656_DATA 0x00000000 +#define DDRSS2_PHY_657_DATA 0x00000000 +#define DDRSS2_PHY_658_DATA 0x00000000 +#define DDRSS2_PHY_659_DATA 0x00000000 +#define DDRSS2_PHY_660_DATA 0x00000000 +#define DDRSS2_PHY_661_DATA 0x00000000 +#define DDRSS2_PHY_662_DATA 0x00000000 +#define DDRSS2_PHY_663_DATA 0x00000000 +#define DDRSS2_PHY_664_DATA 0x00000000 +#define DDRSS2_PHY_665_DATA 0x00000000 +#define DDRSS2_PHY_666_DATA 0x00000000 +#define DDRSS2_PHY_667_DATA 0x00000000 +#define DDRSS2_PHY_668_DATA 0x00000000 +#define DDRSS2_PHY_669_DATA 0x00000000 +#define DDRSS2_PHY_670_DATA 0x00000000 +#define DDRSS2_PHY_671_DATA 0x00000000 +#define DDRSS2_PHY_672_DATA 0x00000000 +#define DDRSS2_PHY_673_DATA 0x00000000 +#define DDRSS2_PHY_674_DATA 0x00000000 +#define DDRSS2_PHY_675_DATA 0x00000000 +#define DDRSS2_PHY_676_DATA 0x00000000 +#define DDRSS2_PHY_677_DATA 0x00000000 +#define DDRSS2_PHY_678_DATA 0x00000000 +#define DDRSS2_PHY_679_DATA 0x00000000 +#define DDRSS2_PHY_680_DATA 0x00000000 +#define DDRSS2_PHY_681_DATA 0x00000000 +#define DDRSS2_PHY_682_DATA 0x00000000 +#define DDRSS2_PHY_683_DATA 0x00000000 +#define DDRSS2_PHY_684_DATA 0x00000000 +#define DDRSS2_PHY_685_DATA 0x00000000 +#define DDRSS2_PHY_686_DATA 0x00000000 +#define DDRSS2_PHY_687_DATA 0x00000000 +#define DDRSS2_PHY_688_DATA 0x00000000 +#define DDRSS2_PHY_689_DATA 0x00000000 +#define DDRSS2_PHY_690_DATA 0x00000000 +#define DDRSS2_PHY_691_DATA 0x00000000 +#define DDRSS2_PHY_692_DATA 0x00000000 +#define DDRSS2_PHY_693_DATA 0x00000000 +#define DDRSS2_PHY_694_DATA 0x00000000 +#define DDRSS2_PHY_695_DATA 0x00000000 +#define DDRSS2_PHY_696_DATA 0x00000000 +#define DDRSS2_PHY_697_DATA 0x00000000 +#define DDRSS2_PHY_698_DATA 0x00000000 +#define DDRSS2_PHY_699_DATA 0x00000000 +#define DDRSS2_PHY_700_DATA 0x00000000 +#define DDRSS2_PHY_701_DATA 0x00000000 +#define DDRSS2_PHY_702_DATA 0x00000000 +#define DDRSS2_PHY_703_DATA 0x00000000 +#define DDRSS2_PHY_704_DATA 0x00000000 +#define DDRSS2_PHY_705_DATA 0x00000000 +#define DDRSS2_PHY_706_DATA 0x00000000 +#define DDRSS2_PHY_707_DATA 0x00000000 +#define DDRSS2_PHY_708_DATA 0x00000000 +#define DDRSS2_PHY_709_DATA 0x00000000 +#define DDRSS2_PHY_710_DATA 0x00000000 +#define DDRSS2_PHY_711_DATA 0x00000000 +#define DDRSS2_PHY_712_DATA 0x00000000 +#define DDRSS2_PHY_713_DATA 0x00000000 +#define DDRSS2_PHY_714_DATA 0x00000000 +#define DDRSS2_PHY_715_DATA 0x00000000 +#define DDRSS2_PHY_716_DATA 0x00000000 +#define DDRSS2_PHY_717_DATA 0x00000000 +#define DDRSS2_PHY_718_DATA 0x00000000 +#define DDRSS2_PHY_719_DATA 0x00000000 +#define DDRSS2_PHY_720_DATA 0x00000000 +#define DDRSS2_PHY_721_DATA 0x00000000 +#define DDRSS2_PHY_722_DATA 0x00000000 +#define DDRSS2_PHY_723_DATA 0x00000000 +#define DDRSS2_PHY_724_DATA 0x00000000 +#define DDRSS2_PHY_725_DATA 0x00000000 +#define DDRSS2_PHY_726_DATA 0x00000000 +#define DDRSS2_PHY_727_DATA 0x00000000 +#define DDRSS2_PHY_728_DATA 0x00000000 +#define DDRSS2_PHY_729_DATA 0x00000000 +#define DDRSS2_PHY_730_DATA 0x00000000 +#define DDRSS2_PHY_731_DATA 0x00000000 +#define DDRSS2_PHY_732_DATA 0x00000000 +#define DDRSS2_PHY_733_DATA 0x00000000 +#define DDRSS2_PHY_734_DATA 0x00000000 +#define DDRSS2_PHY_735_DATA 0x00000000 +#define DDRSS2_PHY_736_DATA 0x00000000 +#define DDRSS2_PHY_737_DATA 0x00000000 +#define DDRSS2_PHY_738_DATA 0x00000000 +#define DDRSS2_PHY_739_DATA 0x00000000 +#define DDRSS2_PHY_740_DATA 0x00000000 +#define DDRSS2_PHY_741_DATA 0x00000000 +#define DDRSS2_PHY_742_DATA 0x00000000 +#define DDRSS2_PHY_743_DATA 0x00000000 +#define DDRSS2_PHY_744_DATA 0x00000000 +#define DDRSS2_PHY_745_DATA 0x00000000 +#define DDRSS2_PHY_746_DATA 0x00000000 +#define DDRSS2_PHY_747_DATA 0x00000000 +#define DDRSS2_PHY_748_DATA 0x00000000 +#define DDRSS2_PHY_749_DATA 0x00000000 +#define DDRSS2_PHY_750_DATA 0x00000000 +#define DDRSS2_PHY_751_DATA 0x00000000 +#define DDRSS2_PHY_752_DATA 0x00000000 +#define DDRSS2_PHY_753_DATA 0x00000000 +#define DDRSS2_PHY_754_DATA 0x00000000 +#define DDRSS2_PHY_755_DATA 0x00000000 +#define DDRSS2_PHY_756_DATA 0x00000000 +#define DDRSS2_PHY_757_DATA 0x00000000 +#define DDRSS2_PHY_758_DATA 0x00000000 +#define DDRSS2_PHY_759_DATA 0x00000000 +#define DDRSS2_PHY_760_DATA 0x00000000 +#define DDRSS2_PHY_761_DATA 0x00000000 +#define DDRSS2_PHY_762_DATA 0x00000000 +#define DDRSS2_PHY_763_DATA 0x00000000 +#define DDRSS2_PHY_764_DATA 0x00000000 +#define DDRSS2_PHY_765_DATA 0x00000000 +#define DDRSS2_PHY_766_DATA 0x00000000 +#define DDRSS2_PHY_767_DATA 0x00000000 +#define DDRSS2_PHY_768_DATA 0x000004F0 +#define DDRSS2_PHY_769_DATA 0x00000000 +#define DDRSS2_PHY_770_DATA 0x00030200 +#define DDRSS2_PHY_771_DATA 0x00000000 +#define DDRSS2_PHY_772_DATA 0x00000000 +#define DDRSS2_PHY_773_DATA 0x01030000 +#define DDRSS2_PHY_774_DATA 0x00010000 +#define DDRSS2_PHY_775_DATA 0x01030004 +#define DDRSS2_PHY_776_DATA 0x01000000 +#define DDRSS2_PHY_777_DATA 0x00000000 +#define DDRSS2_PHY_778_DATA 0x00000000 +#define DDRSS2_PHY_779_DATA 0x01000001 +#define DDRSS2_PHY_780_DATA 0x00000100 +#define DDRSS2_PHY_781_DATA 0x000800C0 +#define DDRSS2_PHY_782_DATA 0x060100CC +#define DDRSS2_PHY_783_DATA 0x00030066 +#define DDRSS2_PHY_784_DATA 0x00000000 +#define DDRSS2_PHY_785_DATA 0x00000301 +#define DDRSS2_PHY_786_DATA 0x0000AAAA +#define DDRSS2_PHY_787_DATA 0x00005555 +#define DDRSS2_PHY_788_DATA 0x0000B5B5 +#define DDRSS2_PHY_789_DATA 0x00004A4A +#define DDRSS2_PHY_790_DATA 0x00005656 +#define DDRSS2_PHY_791_DATA 0x0000A9A9 +#define DDRSS2_PHY_792_DATA 0x0000A9A9 +#define DDRSS2_PHY_793_DATA 0x0000B5B5 +#define DDRSS2_PHY_794_DATA 0x00000000 +#define DDRSS2_PHY_795_DATA 0x00000000 +#define DDRSS2_PHY_796_DATA 0x2A000000 +#define DDRSS2_PHY_797_DATA 0x00000808 +#define DDRSS2_PHY_798_DATA 0x0F000000 +#define DDRSS2_PHY_799_DATA 0x00000F0F +#define DDRSS2_PHY_800_DATA 0x10400000 +#define DDRSS2_PHY_801_DATA 0x0C002006 +#define DDRSS2_PHY_802_DATA 0x00000000 +#define DDRSS2_PHY_803_DATA 0x00000000 +#define DDRSS2_PHY_804_DATA 0x55555555 +#define DDRSS2_PHY_805_DATA 0xAAAAAAAA +#define DDRSS2_PHY_806_DATA 0x55555555 +#define DDRSS2_PHY_807_DATA 0xAAAAAAAA +#define DDRSS2_PHY_808_DATA 0x00005555 +#define DDRSS2_PHY_809_DATA 0x01000100 +#define DDRSS2_PHY_810_DATA 0x00800180 +#define DDRSS2_PHY_811_DATA 0x00000000 +#define DDRSS2_PHY_812_DATA 0x00000000 +#define DDRSS2_PHY_813_DATA 0x00000000 +#define DDRSS2_PHY_814_DATA 0x00000000 +#define DDRSS2_PHY_815_DATA 0x00000000 +#define DDRSS2_PHY_816_DATA 0x00000000 +#define DDRSS2_PHY_817_DATA 0x00000000 +#define DDRSS2_PHY_818_DATA 0x00000000 +#define DDRSS2_PHY_819_DATA 0x00000000 +#define DDRSS2_PHY_820_DATA 0x00000000 +#define DDRSS2_PHY_821_DATA 0x00000000 +#define DDRSS2_PHY_822_DATA 0x00000000 +#define DDRSS2_PHY_823_DATA 0x00000000 +#define DDRSS2_PHY_824_DATA 0x00000000 +#define DDRSS2_PHY_825_DATA 0x00000000 +#define DDRSS2_PHY_826_DATA 0x00000000 +#define DDRSS2_PHY_827_DATA 0x00000000 +#define DDRSS2_PHY_828_DATA 0x00000000 +#define DDRSS2_PHY_829_DATA 0x00000000 +#define DDRSS2_PHY_830_DATA 0x00000000 +#define DDRSS2_PHY_831_DATA 0x00000000 +#define DDRSS2_PHY_832_DATA 0x00000000 +#define DDRSS2_PHY_833_DATA 0x00000000 +#define DDRSS2_PHY_834_DATA 0x00000104 +#define DDRSS2_PHY_835_DATA 0x00000120 +#define DDRSS2_PHY_836_DATA 0x00000000 +#define DDRSS2_PHY_837_DATA 0x00000000 +#define DDRSS2_PHY_838_DATA 0x00000000 +#define DDRSS2_PHY_839_DATA 0x00000000 +#define DDRSS2_PHY_840_DATA 0x00000000 +#define DDRSS2_PHY_841_DATA 0x00000000 +#define DDRSS2_PHY_842_DATA 0x00000000 +#define DDRSS2_PHY_843_DATA 0x00000001 +#define DDRSS2_PHY_844_DATA 0x07FF0000 +#define DDRSS2_PHY_845_DATA 0x0080081F +#define DDRSS2_PHY_846_DATA 0x00081020 +#define DDRSS2_PHY_847_DATA 0x04010000 +#define DDRSS2_PHY_848_DATA 0x00000000 +#define DDRSS2_PHY_849_DATA 0x00000000 +#define DDRSS2_PHY_850_DATA 0x00000000 +#define DDRSS2_PHY_851_DATA 0x00000100 +#define DDRSS2_PHY_852_DATA 0x01CC0C01 +#define DDRSS2_PHY_853_DATA 0x1003CC0C +#define DDRSS2_PHY_854_DATA 0x20000140 +#define DDRSS2_PHY_855_DATA 0x07FF0200 +#define DDRSS2_PHY_856_DATA 0x0000DD01 +#define DDRSS2_PHY_857_DATA 0x10100303 +#define DDRSS2_PHY_858_DATA 0x10101010 +#define DDRSS2_PHY_859_DATA 0x10101010 +#define DDRSS2_PHY_860_DATA 0x00021010 +#define DDRSS2_PHY_861_DATA 0x00100010 +#define DDRSS2_PHY_862_DATA 0x00100010 +#define DDRSS2_PHY_863_DATA 0x00100010 +#define DDRSS2_PHY_864_DATA 0x00100010 +#define DDRSS2_PHY_865_DATA 0x00050010 +#define DDRSS2_PHY_866_DATA 0x51517041 +#define DDRSS2_PHY_867_DATA 0x31C06001 +#define DDRSS2_PHY_868_DATA 0x07AB0340 +#define DDRSS2_PHY_869_DATA 0x00C0C001 +#define DDRSS2_PHY_870_DATA 0x0E0D0001 +#define DDRSS2_PHY_871_DATA 0x10001000 +#define DDRSS2_PHY_872_DATA 0x0C083E42 +#define DDRSS2_PHY_873_DATA 0x0F0C3701 +#define DDRSS2_PHY_874_DATA 0x01000140 +#define DDRSS2_PHY_875_DATA 0x0C000420 +#define DDRSS2_PHY_876_DATA 0x00000198 +#define DDRSS2_PHY_877_DATA 0x0A0000D0 +#define DDRSS2_PHY_878_DATA 0x00030200 +#define DDRSS2_PHY_879_DATA 0x02800000 +#define DDRSS2_PHY_880_DATA 0x80800000 +#define DDRSS2_PHY_881_DATA 0x000E2010 +#define DDRSS2_PHY_882_DATA 0x76543210 +#define DDRSS2_PHY_883_DATA 0x00000008 +#define DDRSS2_PHY_884_DATA 0x02800280 +#define DDRSS2_PHY_885_DATA 0x02800280 +#define DDRSS2_PHY_886_DATA 0x02800280 +#define DDRSS2_PHY_887_DATA 0x02800280 +#define DDRSS2_PHY_888_DATA 0x00000280 +#define DDRSS2_PHY_889_DATA 0x0000A000 +#define DDRSS2_PHY_890_DATA 0x00A000A0 +#define DDRSS2_PHY_891_DATA 0x00A000A0 +#define DDRSS2_PHY_892_DATA 0x00A000A0 +#define DDRSS2_PHY_893_DATA 0x00A000A0 +#define DDRSS2_PHY_894_DATA 0x00A000A0 +#define DDRSS2_PHY_895_DATA 0x00A000A0 +#define DDRSS2_PHY_896_DATA 0x00A000A0 +#define DDRSS2_PHY_897_DATA 0x00A000A0 +#define DDRSS2_PHY_898_DATA 0x01C200A0 +#define DDRSS2_PHY_899_DATA 0x01A00005 +#define DDRSS2_PHY_900_DATA 0x00000000 +#define DDRSS2_PHY_901_DATA 0x00000000 +#define DDRSS2_PHY_902_DATA 0x00080200 +#define DDRSS2_PHY_903_DATA 0x00000000 +#define DDRSS2_PHY_904_DATA 0x20202000 +#define DDRSS2_PHY_905_DATA 0x20202020 +#define DDRSS2_PHY_906_DATA 0xF0F02020 +#define DDRSS2_PHY_907_DATA 0x00000000 +#define DDRSS2_PHY_908_DATA 0x00000000 +#define DDRSS2_PHY_909_DATA 0x00000000 +#define DDRSS2_PHY_910_DATA 0x00000000 +#define DDRSS2_PHY_911_DATA 0x00000000 +#define DDRSS2_PHY_912_DATA 0x00000000 +#define DDRSS2_PHY_913_DATA 0x00000000 +#define DDRSS2_PHY_914_DATA 0x00000000 +#define DDRSS2_PHY_915_DATA 0x00000000 +#define DDRSS2_PHY_916_DATA 0x00000000 +#define DDRSS2_PHY_917_DATA 0x00000000 +#define DDRSS2_PHY_918_DATA 0x00000000 +#define DDRSS2_PHY_919_DATA 0x00000000 +#define DDRSS2_PHY_920_DATA 0x00000000 +#define DDRSS2_PHY_921_DATA 0x00000000 +#define DDRSS2_PHY_922_DATA 0x00000000 +#define DDRSS2_PHY_923_DATA 0x00000000 +#define DDRSS2_PHY_924_DATA 0x00000000 +#define DDRSS2_PHY_925_DATA 0x00000000 +#define DDRSS2_PHY_926_DATA 0x00000000 +#define DDRSS2_PHY_927_DATA 0x00000000 +#define DDRSS2_PHY_928_DATA 0x00000000 +#define DDRSS2_PHY_929_DATA 0x00000000 +#define DDRSS2_PHY_930_DATA 0x00000000 +#define DDRSS2_PHY_931_DATA 0x00000000 +#define DDRSS2_PHY_932_DATA 0x00000000 +#define DDRSS2_PHY_933_DATA 0x00000000 +#define DDRSS2_PHY_934_DATA 0x00000000 +#define DDRSS2_PHY_935_DATA 0x00000000 +#define DDRSS2_PHY_936_DATA 0x00000000 +#define DDRSS2_PHY_937_DATA 0x00000000 +#define DDRSS2_PHY_938_DATA 0x00000000 +#define DDRSS2_PHY_939_DATA 0x00000000 +#define DDRSS2_PHY_940_DATA 0x00000000 +#define DDRSS2_PHY_941_DATA 0x00000000 +#define DDRSS2_PHY_942_DATA 0x00000000 +#define DDRSS2_PHY_943_DATA 0x00000000 +#define DDRSS2_PHY_944_DATA 0x00000000 +#define DDRSS2_PHY_945_DATA 0x00000000 +#define DDRSS2_PHY_946_DATA 0x00000000 +#define DDRSS2_PHY_947_DATA 0x00000000 +#define DDRSS2_PHY_948_DATA 0x00000000 +#define DDRSS2_PHY_949_DATA 0x00000000 +#define DDRSS2_PHY_950_DATA 0x00000000 +#define DDRSS2_PHY_951_DATA 0x00000000 +#define DDRSS2_PHY_952_DATA 0x00000000 +#define DDRSS2_PHY_953_DATA 0x00000000 +#define DDRSS2_PHY_954_DATA 0x00000000 +#define DDRSS2_PHY_955_DATA 0x00000000 +#define DDRSS2_PHY_956_DATA 0x00000000 +#define DDRSS2_PHY_957_DATA 0x00000000 +#define DDRSS2_PHY_958_DATA 0x00000000 +#define DDRSS2_PHY_959_DATA 0x00000000 +#define DDRSS2_PHY_960_DATA 0x00000000 +#define DDRSS2_PHY_961_DATA 0x00000000 +#define DDRSS2_PHY_962_DATA 0x00000000 +#define DDRSS2_PHY_963_DATA 0x00000000 +#define DDRSS2_PHY_964_DATA 0x00000000 +#define DDRSS2_PHY_965_DATA 0x00000000 +#define DDRSS2_PHY_966_DATA 0x00000000 +#define DDRSS2_PHY_967_DATA 0x00000000 +#define DDRSS2_PHY_968_DATA 0x00000000 +#define DDRSS2_PHY_969_DATA 0x00000000 +#define DDRSS2_PHY_970_DATA 0x00000000 +#define DDRSS2_PHY_971_DATA 0x00000000 +#define DDRSS2_PHY_972_DATA 0x00000000 +#define DDRSS2_PHY_973_DATA 0x00000000 +#define DDRSS2_PHY_974_DATA 0x00000000 +#define DDRSS2_PHY_975_DATA 0x00000000 +#define DDRSS2_PHY_976_DATA 0x00000000 +#define DDRSS2_PHY_977_DATA 0x00000000 +#define DDRSS2_PHY_978_DATA 0x00000000 +#define DDRSS2_PHY_979_DATA 0x00000000 +#define DDRSS2_PHY_980_DATA 0x00000000 +#define DDRSS2_PHY_981_DATA 0x00000000 +#define DDRSS2_PHY_982_DATA 0x00000000 +#define DDRSS2_PHY_983_DATA 0x00000000 +#define DDRSS2_PHY_984_DATA 0x00000000 +#define DDRSS2_PHY_985_DATA 0x00000000 +#define DDRSS2_PHY_986_DATA 0x00000000 +#define DDRSS2_PHY_987_DATA 0x00000000 +#define DDRSS2_PHY_988_DATA 0x00000000 +#define DDRSS2_PHY_989_DATA 0x00000000 +#define DDRSS2_PHY_990_DATA 0x00000000 +#define DDRSS2_PHY_991_DATA 0x00000000 +#define DDRSS2_PHY_992_DATA 0x00000000 +#define DDRSS2_PHY_993_DATA 0x00000000 +#define DDRSS2_PHY_994_DATA 0x00000000 +#define DDRSS2_PHY_995_DATA 0x00000000 +#define DDRSS2_PHY_996_DATA 0x00000000 +#define DDRSS2_PHY_997_DATA 0x00000000 +#define DDRSS2_PHY_998_DATA 0x00000000 +#define DDRSS2_PHY_999_DATA 0x00000000 +#define DDRSS2_PHY_1000_DATA 0x00000000 +#define DDRSS2_PHY_1001_DATA 0x00000000 +#define DDRSS2_PHY_1002_DATA 0x00000000 +#define DDRSS2_PHY_1003_DATA 0x00000000 +#define DDRSS2_PHY_1004_DATA 0x00000000 +#define DDRSS2_PHY_1005_DATA 0x00000000 +#define DDRSS2_PHY_1006_DATA 0x00000000 +#define DDRSS2_PHY_1007_DATA 0x00000000 +#define DDRSS2_PHY_1008_DATA 0x00000000 +#define DDRSS2_PHY_1009_DATA 0x00000000 +#define DDRSS2_PHY_1010_DATA 0x00000000 +#define DDRSS2_PHY_1011_DATA 0x00000000 +#define DDRSS2_PHY_1012_DATA 0x00000000 +#define DDRSS2_PHY_1013_DATA 0x00000000 +#define DDRSS2_PHY_1014_DATA 0x00000000 +#define DDRSS2_PHY_1015_DATA 0x00000000 +#define DDRSS2_PHY_1016_DATA 0x00000000 +#define DDRSS2_PHY_1017_DATA 0x00000000 +#define DDRSS2_PHY_1018_DATA 0x00000000 +#define DDRSS2_PHY_1019_DATA 0x00000000 +#define DDRSS2_PHY_1020_DATA 0x00000000 +#define DDRSS2_PHY_1021_DATA 0x00000000 +#define DDRSS2_PHY_1022_DATA 0x00000000 +#define DDRSS2_PHY_1023_DATA 0x00000000 +#define DDRSS2_PHY_1024_DATA 0x00000000 +#define DDRSS2_PHY_1025_DATA 0x00000000 +#define DDRSS2_PHY_1026_DATA 0x00000000 +#define DDRSS2_PHY_1027_DATA 0x00000000 +#define DDRSS2_PHY_1028_DATA 0x00000000 +#define DDRSS2_PHY_1029_DATA 0x00000100 +#define DDRSS2_PHY_1030_DATA 0x00000200 +#define DDRSS2_PHY_1031_DATA 0x00000000 +#define DDRSS2_PHY_1032_DATA 0x00000000 +#define DDRSS2_PHY_1033_DATA 0x00000000 +#define DDRSS2_PHY_1034_DATA 0x00000000 +#define DDRSS2_PHY_1035_DATA 0x00400000 +#define DDRSS2_PHY_1036_DATA 0x00000080 +#define DDRSS2_PHY_1037_DATA 0x00DCBA98 +#define DDRSS2_PHY_1038_DATA 0x03000000 +#define DDRSS2_PHY_1039_DATA 0x00200000 +#define DDRSS2_PHY_1040_DATA 0x00000000 +#define DDRSS2_PHY_1041_DATA 0x00000000 +#define DDRSS2_PHY_1042_DATA 0x00000000 +#define DDRSS2_PHY_1043_DATA 0x00000000 +#define DDRSS2_PHY_1044_DATA 0x00000000 +#define DDRSS2_PHY_1045_DATA 0x0000002A +#define DDRSS2_PHY_1046_DATA 0x00000015 +#define DDRSS2_PHY_1047_DATA 0x00000015 +#define DDRSS2_PHY_1048_DATA 0x0000002A +#define DDRSS2_PHY_1049_DATA 0x00000033 +#define DDRSS2_PHY_1050_DATA 0x0000000C +#define DDRSS2_PHY_1051_DATA 0x0000000C +#define DDRSS2_PHY_1052_DATA 0x00000033 +#define DDRSS2_PHY_1053_DATA 0x00543210 +#define DDRSS2_PHY_1054_DATA 0x003F0000 +#define DDRSS2_PHY_1055_DATA 0x000F013F +#define DDRSS2_PHY_1056_DATA 0x20202003 +#define DDRSS2_PHY_1057_DATA 0x00202020 +#define DDRSS2_PHY_1058_DATA 0x20008008 +#define DDRSS2_PHY_1059_DATA 0x00000810 +#define DDRSS2_PHY_1060_DATA 0x00000F00 +#define DDRSS2_PHY_1061_DATA 0x00000000 +#define DDRSS2_PHY_1062_DATA 0x00000000 +#define DDRSS2_PHY_1063_DATA 0x00000000 +#define DDRSS2_PHY_1064_DATA 0x000305CC +#define DDRSS2_PHY_1065_DATA 0x00030000 +#define DDRSS2_PHY_1066_DATA 0x00000300 +#define DDRSS2_PHY_1067_DATA 0x00000300 +#define DDRSS2_PHY_1068_DATA 0x00000300 +#define DDRSS2_PHY_1069_DATA 0x00000300 +#define DDRSS2_PHY_1070_DATA 0x00000300 +#define DDRSS2_PHY_1071_DATA 0x42080010 +#define DDRSS2_PHY_1072_DATA 0x0000803E +#define DDRSS2_PHY_1073_DATA 0x00000001 +#define DDRSS2_PHY_1074_DATA 0x01000102 +#define DDRSS2_PHY_1075_DATA 0x00008000 +#define DDRSS2_PHY_1076_DATA 0x00000000 +#define DDRSS2_PHY_1077_DATA 0x00000000 +#define DDRSS2_PHY_1078_DATA 0x00000000 +#define DDRSS2_PHY_1079_DATA 0x00000000 +#define DDRSS2_PHY_1080_DATA 0x00000000 +#define DDRSS2_PHY_1081_DATA 0x00000000 +#define DDRSS2_PHY_1082_DATA 0x00000000 +#define DDRSS2_PHY_1083_DATA 0x00000000 +#define DDRSS2_PHY_1084_DATA 0x00000000 +#define DDRSS2_PHY_1085_DATA 0x00000000 +#define DDRSS2_PHY_1086_DATA 0x00000000 +#define DDRSS2_PHY_1087_DATA 0x00000000 +#define DDRSS2_PHY_1088_DATA 0x00000000 +#define DDRSS2_PHY_1089_DATA 0x00000000 +#define DDRSS2_PHY_1090_DATA 0x00000000 +#define DDRSS2_PHY_1091_DATA 0x00000000 +#define DDRSS2_PHY_1092_DATA 0x00000000 +#define DDRSS2_PHY_1093_DATA 0x00000000 +#define DDRSS2_PHY_1094_DATA 0x00000000 +#define DDRSS2_PHY_1095_DATA 0x00000000 +#define DDRSS2_PHY_1096_DATA 0x00000000 +#define DDRSS2_PHY_1097_DATA 0x00000000 +#define DDRSS2_PHY_1098_DATA 0x00000000 +#define DDRSS2_PHY_1099_DATA 0x00000000 +#define DDRSS2_PHY_1100_DATA 0x00000000 +#define DDRSS2_PHY_1101_DATA 0x00000000 +#define DDRSS2_PHY_1102_DATA 0x00000000 +#define DDRSS2_PHY_1103_DATA 0x00000000 +#define DDRSS2_PHY_1104_DATA 0x00000000 +#define DDRSS2_PHY_1105_DATA 0x00000000 +#define DDRSS2_PHY_1106_DATA 0x00000000 +#define DDRSS2_PHY_1107_DATA 0x00000000 +#define DDRSS2_PHY_1108_DATA 0x00000000 +#define DDRSS2_PHY_1109_DATA 0x00000000 +#define DDRSS2_PHY_1110_DATA 0x00000000 +#define DDRSS2_PHY_1111_DATA 0x00000000 +#define DDRSS2_PHY_1112_DATA 0x00000000 +#define DDRSS2_PHY_1113_DATA 0x00000000 +#define DDRSS2_PHY_1114_DATA 0x00000000 +#define DDRSS2_PHY_1115_DATA 0x00000000 +#define DDRSS2_PHY_1116_DATA 0x00000000 +#define DDRSS2_PHY_1117_DATA 0x00000000 +#define DDRSS2_PHY_1118_DATA 0x00000000 +#define DDRSS2_PHY_1119_DATA 0x00000000 +#define DDRSS2_PHY_1120_DATA 0x00000000 +#define DDRSS2_PHY_1121_DATA 0x00000000 +#define DDRSS2_PHY_1122_DATA 0x00000000 +#define DDRSS2_PHY_1123_DATA 0x00000000 +#define DDRSS2_PHY_1124_DATA 0x00000000 +#define DDRSS2_PHY_1125_DATA 0x00000000 +#define DDRSS2_PHY_1126_DATA 0x00000000 +#define DDRSS2_PHY_1127_DATA 0x00000000 +#define DDRSS2_PHY_1128_DATA 0x00000000 +#define DDRSS2_PHY_1129_DATA 0x00000000 +#define DDRSS2_PHY_1130_DATA 0x00000000 +#define DDRSS2_PHY_1131_DATA 0x00000000 +#define DDRSS2_PHY_1132_DATA 0x00000000 +#define DDRSS2_PHY_1133_DATA 0x00000000 +#define DDRSS2_PHY_1134_DATA 0x00000000 +#define DDRSS2_PHY_1135_DATA 0x00000000 +#define DDRSS2_PHY_1136_DATA 0x00000000 +#define DDRSS2_PHY_1137_DATA 0x00000000 +#define DDRSS2_PHY_1138_DATA 0x00000000 +#define DDRSS2_PHY_1139_DATA 0x00000000 +#define DDRSS2_PHY_1140_DATA 0x00000000 +#define DDRSS2_PHY_1141_DATA 0x00000000 +#define DDRSS2_PHY_1142_DATA 0x00000000 +#define DDRSS2_PHY_1143_DATA 0x00000000 +#define DDRSS2_PHY_1144_DATA 0x00000000 +#define DDRSS2_PHY_1145_DATA 0x00000000 +#define DDRSS2_PHY_1146_DATA 0x00000000 +#define DDRSS2_PHY_1147_DATA 0x00000000 +#define DDRSS2_PHY_1148_DATA 0x00000000 +#define DDRSS2_PHY_1149_DATA 0x00000000 +#define DDRSS2_PHY_1150_DATA 0x00000000 +#define DDRSS2_PHY_1151_DATA 0x00000000 +#define DDRSS2_PHY_1152_DATA 0x00000000 +#define DDRSS2_PHY_1153_DATA 0x00000000 +#define DDRSS2_PHY_1154_DATA 0x00000000 +#define DDRSS2_PHY_1155_DATA 0x00000000 +#define DDRSS2_PHY_1156_DATA 0x00000000 +#define DDRSS2_PHY_1157_DATA 0x00000000 +#define DDRSS2_PHY_1158_DATA 0x00000000 +#define DDRSS2_PHY_1159_DATA 0x00000000 +#define DDRSS2_PHY_1160_DATA 0x00000000 +#define DDRSS2_PHY_1161_DATA 0x00000000 +#define DDRSS2_PHY_1162_DATA 0x00000000 +#define DDRSS2_PHY_1163_DATA 0x00000000 +#define DDRSS2_PHY_1164_DATA 0x00000000 +#define DDRSS2_PHY_1165_DATA 0x00000000 +#define DDRSS2_PHY_1166_DATA 0x00000000 +#define DDRSS2_PHY_1167_DATA 0x00000000 +#define DDRSS2_PHY_1168_DATA 0x00000000 +#define DDRSS2_PHY_1169_DATA 0x00000000 +#define DDRSS2_PHY_1170_DATA 0x00000000 +#define DDRSS2_PHY_1171_DATA 0x00000000 +#define DDRSS2_PHY_1172_DATA 0x00000000 +#define DDRSS2_PHY_1173_DATA 0x00000000 +#define DDRSS2_PHY_1174_DATA 0x00000000 +#define DDRSS2_PHY_1175_DATA 0x00000000 +#define DDRSS2_PHY_1176_DATA 0x00000000 +#define DDRSS2_PHY_1177_DATA 0x00000000 +#define DDRSS2_PHY_1178_DATA 0x00000000 +#define DDRSS2_PHY_1179_DATA 0x00000000 +#define DDRSS2_PHY_1180_DATA 0x00000000 +#define DDRSS2_PHY_1181_DATA 0x00000000 +#define DDRSS2_PHY_1182_DATA 0x00000000 +#define DDRSS2_PHY_1183_DATA 0x00000000 +#define DDRSS2_PHY_1184_DATA 0x00000000 +#define DDRSS2_PHY_1185_DATA 0x00000000 +#define DDRSS2_PHY_1186_DATA 0x00000000 +#define DDRSS2_PHY_1187_DATA 0x00000000 +#define DDRSS2_PHY_1188_DATA 0x00000000 +#define DDRSS2_PHY_1189_DATA 0x00000000 +#define DDRSS2_PHY_1190_DATA 0x00000000 +#define DDRSS2_PHY_1191_DATA 0x00000000 +#define DDRSS2_PHY_1192_DATA 0x00000000 +#define DDRSS2_PHY_1193_DATA 0x00000000 +#define DDRSS2_PHY_1194_DATA 0x00000000 +#define DDRSS2_PHY_1195_DATA 0x00000000 +#define DDRSS2_PHY_1196_DATA 0x00000000 +#define DDRSS2_PHY_1197_DATA 0x00000000 +#define DDRSS2_PHY_1198_DATA 0x00000000 +#define DDRSS2_PHY_1199_DATA 0x00000000 +#define DDRSS2_PHY_1200_DATA 0x00000000 +#define DDRSS2_PHY_1201_DATA 0x00000000 +#define DDRSS2_PHY_1202_DATA 0x00000000 +#define DDRSS2_PHY_1203_DATA 0x00000000 +#define DDRSS2_PHY_1204_DATA 0x00000000 +#define DDRSS2_PHY_1205_DATA 0x00000000 +#define DDRSS2_PHY_1206_DATA 0x00000000 +#define DDRSS2_PHY_1207_DATA 0x00000000 +#define DDRSS2_PHY_1208_DATA 0x00000000 +#define DDRSS2_PHY_1209_DATA 0x00000000 +#define DDRSS2_PHY_1210_DATA 0x00000000 +#define DDRSS2_PHY_1211_DATA 0x00000000 +#define DDRSS2_PHY_1212_DATA 0x00000000 +#define DDRSS2_PHY_1213_DATA 0x00000000 +#define DDRSS2_PHY_1214_DATA 0x00000000 +#define DDRSS2_PHY_1215_DATA 0x00000000 +#define DDRSS2_PHY_1216_DATA 0x00000000 +#define DDRSS2_PHY_1217_DATA 0x00000000 +#define DDRSS2_PHY_1218_DATA 0x00000000 +#define DDRSS2_PHY_1219_DATA 0x00000000 +#define DDRSS2_PHY_1220_DATA 0x00000000 +#define DDRSS2_PHY_1221_DATA 0x00000000 +#define DDRSS2_PHY_1222_DATA 0x00000000 +#define DDRSS2_PHY_1223_DATA 0x00000000 +#define DDRSS2_PHY_1224_DATA 0x00000000 +#define DDRSS2_PHY_1225_DATA 0x00000000 +#define DDRSS2_PHY_1226_DATA 0x00000000 +#define DDRSS2_PHY_1227_DATA 0x00000000 +#define DDRSS2_PHY_1228_DATA 0x00000000 +#define DDRSS2_PHY_1229_DATA 0x00000000 +#define DDRSS2_PHY_1230_DATA 0x00000000 +#define DDRSS2_PHY_1231_DATA 0x00000000 +#define DDRSS2_PHY_1232_DATA 0x00000000 +#define DDRSS2_PHY_1233_DATA 0x00000000 +#define DDRSS2_PHY_1234_DATA 0x00000000 +#define DDRSS2_PHY_1235_DATA 0x00000000 +#define DDRSS2_PHY_1236_DATA 0x00000000 +#define DDRSS2_PHY_1237_DATA 0x00000000 +#define DDRSS2_PHY_1238_DATA 0x00000000 +#define DDRSS2_PHY_1239_DATA 0x00000000 +#define DDRSS2_PHY_1240_DATA 0x00000000 +#define DDRSS2_PHY_1241_DATA 0x00000000 +#define DDRSS2_PHY_1242_DATA 0x00000000 +#define DDRSS2_PHY_1243_DATA 0x00000000 +#define DDRSS2_PHY_1244_DATA 0x00000000 +#define DDRSS2_PHY_1245_DATA 0x00000000 +#define DDRSS2_PHY_1246_DATA 0x00000000 +#define DDRSS2_PHY_1247_DATA 0x00000000 +#define DDRSS2_PHY_1248_DATA 0x00000000 +#define DDRSS2_PHY_1249_DATA 0x00000000 +#define DDRSS2_PHY_1250_DATA 0x00000000 +#define DDRSS2_PHY_1251_DATA 0x00000000 +#define DDRSS2_PHY_1252_DATA 0x00000000 +#define DDRSS2_PHY_1253_DATA 0x00000000 +#define DDRSS2_PHY_1254_DATA 0x00000000 +#define DDRSS2_PHY_1255_DATA 0x00000000 +#define DDRSS2_PHY_1256_DATA 0x00000000 +#define DDRSS2_PHY_1257_DATA 0x00000000 +#define DDRSS2_PHY_1258_DATA 0x00000000 +#define DDRSS2_PHY_1259_DATA 0x00000000 +#define DDRSS2_PHY_1260_DATA 0x00000000 +#define DDRSS2_PHY_1261_DATA 0x00000000 +#define DDRSS2_PHY_1262_DATA 0x00000000 +#define DDRSS2_PHY_1263_DATA 0x00000000 +#define DDRSS2_PHY_1264_DATA 0x00000000 +#define DDRSS2_PHY_1265_DATA 0x00000000 +#define DDRSS2_PHY_1266_DATA 0x00000000 +#define DDRSS2_PHY_1267_DATA 0x00000000 +#define DDRSS2_PHY_1268_DATA 0x00000000 +#define DDRSS2_PHY_1269_DATA 0x00000000 +#define DDRSS2_PHY_1270_DATA 0x00000000 +#define DDRSS2_PHY_1271_DATA 0x00000000 +#define DDRSS2_PHY_1272_DATA 0x00000000 +#define DDRSS2_PHY_1273_DATA 0x00000000 +#define DDRSS2_PHY_1274_DATA 0x00000000 +#define DDRSS2_PHY_1275_DATA 0x00000000 +#define DDRSS2_PHY_1276_DATA 0x00000000 +#define DDRSS2_PHY_1277_DATA 0x00000000 +#define DDRSS2_PHY_1278_DATA 0x00000000 +#define DDRSS2_PHY_1279_DATA 0x00000000 +#define DDRSS2_PHY_1280_DATA 0x00000000 +#define DDRSS2_PHY_1281_DATA 0x00010100 +#define DDRSS2_PHY_1282_DATA 0x00000000 +#define DDRSS2_PHY_1283_DATA 0x00000000 +#define DDRSS2_PHY_1284_DATA 0x00050000 +#define DDRSS2_PHY_1285_DATA 0x04000000 +#define DDRSS2_PHY_1286_DATA 0x00000055 +#define DDRSS2_PHY_1287_DATA 0x00000000 +#define DDRSS2_PHY_1288_DATA 0x00000000 +#define DDRSS2_PHY_1289_DATA 0x00000000 +#define DDRSS2_PHY_1290_DATA 0x00000000 +#define DDRSS2_PHY_1291_DATA 0x00002001 +#define DDRSS2_PHY_1292_DATA 0x0000400F +#define DDRSS2_PHY_1293_DATA 0x50020028 +#define DDRSS2_PHY_1294_DATA 0x01010000 +#define DDRSS2_PHY_1295_DATA 0x80080001 +#define DDRSS2_PHY_1296_DATA 0x10200000 +#define DDRSS2_PHY_1297_DATA 0x00000008 +#define DDRSS2_PHY_1298_DATA 0x00000000 +#define DDRSS2_PHY_1299_DATA 0x01090E00 +#define DDRSS2_PHY_1300_DATA 0x00040101 +#define DDRSS2_PHY_1301_DATA 0x0000010F +#define DDRSS2_PHY_1302_DATA 0x00000000 +#define DDRSS2_PHY_1303_DATA 0x0000FFFF +#define DDRSS2_PHY_1304_DATA 0x00000000 +#define DDRSS2_PHY_1305_DATA 0x01010000 +#define DDRSS2_PHY_1306_DATA 0x01080402 +#define DDRSS2_PHY_1307_DATA 0x01200F02 +#define DDRSS2_PHY_1308_DATA 0x00194280 +#define DDRSS2_PHY_1309_DATA 0x00000004 +#define DDRSS2_PHY_1310_DATA 0x00042000 +#define DDRSS2_PHY_1311_DATA 0x00000000 +#define DDRSS2_PHY_1312_DATA 0x00000000 +#define DDRSS2_PHY_1313_DATA 0x00000000 +#define DDRSS2_PHY_1314_DATA 0x00000000 +#define DDRSS2_PHY_1315_DATA 0x00000000 +#define DDRSS2_PHY_1316_DATA 0x00000000 +#define DDRSS2_PHY_1317_DATA 0x01000000 +#define DDRSS2_PHY_1318_DATA 0x00000705 +#define DDRSS2_PHY_1319_DATA 0x00000054 +#define DDRSS2_PHY_1320_DATA 0x00030820 +#define DDRSS2_PHY_1321_DATA 0x00010820 +#define DDRSS2_PHY_1322_DATA 0x00010820 +#define DDRSS2_PHY_1323_DATA 0x00010820 +#define DDRSS2_PHY_1324_DATA 0x00010820 +#define DDRSS2_PHY_1325_DATA 0x00010820 +#define DDRSS2_PHY_1326_DATA 0x00010820 +#define DDRSS2_PHY_1327_DATA 0x00010820 +#define DDRSS2_PHY_1328_DATA 0x00010820 +#define DDRSS2_PHY_1329_DATA 0x00000000 +#define DDRSS2_PHY_1330_DATA 0x00000074 +#define DDRSS2_PHY_1331_DATA 0x00000400 +#define DDRSS2_PHY_1332_DATA 0x00000108 +#define DDRSS2_PHY_1333_DATA 0x00000000 +#define DDRSS2_PHY_1334_DATA 0x00000000 +#define DDRSS2_PHY_1335_DATA 0x00000000 +#define DDRSS2_PHY_1336_DATA 0x00000000 +#define DDRSS2_PHY_1337_DATA 0x00000000 +#define DDRSS2_PHY_1338_DATA 0x03000000 +#define DDRSS2_PHY_1339_DATA 0x00000000 +#define DDRSS2_PHY_1340_DATA 0x00000000 +#define DDRSS2_PHY_1341_DATA 0x00000000 +#define DDRSS2_PHY_1342_DATA 0x04102006 +#define DDRSS2_PHY_1343_DATA 0x00041020 +#define DDRSS2_PHY_1344_DATA 0x01C98C98 +#define DDRSS2_PHY_1345_DATA 0x3F400000 +#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS2_PHY_1347_DATA 0x0000001F +#define DDRSS2_PHY_1348_DATA 0x00000000 +#define DDRSS2_PHY_1349_DATA 0x00000000 +#define DDRSS2_PHY_1350_DATA 0x00000000 +#define DDRSS2_PHY_1351_DATA 0x00010000 +#define DDRSS2_PHY_1352_DATA 0x00000000 +#define DDRSS2_PHY_1353_DATA 0x00000000 +#define DDRSS2_PHY_1354_DATA 0x00000000 +#define DDRSS2_PHY_1355_DATA 0x00000000 +#define DDRSS2_PHY_1356_DATA 0x76543210 +#define DDRSS2_PHY_1357_DATA 0x00010198 +#define DDRSS2_PHY_1358_DATA 0x00000000 +#define DDRSS2_PHY_1359_DATA 0x00000000 +#define DDRSS2_PHY_1360_DATA 0x00000000 +#define DDRSS2_PHY_1361_DATA 0x00040700 +#define DDRSS2_PHY_1362_DATA 0x00000000 +#define DDRSS2_PHY_1363_DATA 0x00000000 +#define DDRSS2_PHY_1364_DATA 0x00000000 +#define DDRSS2_PHY_1365_DATA 0x00000000 +#define DDRSS2_PHY_1366_DATA 0x00000000 +#define DDRSS2_PHY_1367_DATA 0x00000002 +#define DDRSS2_PHY_1368_DATA 0x00000000 +#define DDRSS2_PHY_1369_DATA 0x00000000 +#define DDRSS2_PHY_1370_DATA 0x00000000 +#define DDRSS2_PHY_1371_DATA 0x00000000 +#define DDRSS2_PHY_1372_DATA 0x00000000 +#define DDRSS2_PHY_1373_DATA 0x00000000 +#define DDRSS2_PHY_1374_DATA 0x00080000 +#define DDRSS2_PHY_1375_DATA 0x000007FF +#define DDRSS2_PHY_1376_DATA 0x00000000 +#define DDRSS2_PHY_1377_DATA 0x00000000 +#define DDRSS2_PHY_1378_DATA 0x00000000 +#define DDRSS2_PHY_1379_DATA 0x00000000 +#define DDRSS2_PHY_1380_DATA 0x00000000 +#define DDRSS2_PHY_1381_DATA 0x00000000 +#define DDRSS2_PHY_1382_DATA 0x000FFFFF +#define DDRSS2_PHY_1383_DATA 0x000FFFFF +#define DDRSS2_PHY_1384_DATA 0x0000FFFF +#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS2_PHY_1386_DATA 0x030FFFFF +#define DDRSS2_PHY_1387_DATA 0x01FFFFFF +#define DDRSS2_PHY_1388_DATA 0x0000FFFF +#define DDRSS2_PHY_1389_DATA 0x00000000 +#define DDRSS2_PHY_1390_DATA 0x00000000 +#define DDRSS2_PHY_1391_DATA 0x00000000 +#define DDRSS2_PHY_1392_DATA 0x00000000 +#define DDRSS2_PHY_1393_DATA 0x0001F7C0 +#define DDRSS2_PHY_1394_DATA 0x00000003 +#define DDRSS2_PHY_1395_DATA 0x00000000 +#define DDRSS2_PHY_1396_DATA 0x00001142 +#define DDRSS2_PHY_1397_DATA 0x010207AB +#define DDRSS2_PHY_1398_DATA 0x01000080 +#define DDRSS2_PHY_1399_DATA 0x03900390 +#define DDRSS2_PHY_1400_DATA 0x03900390 +#define DDRSS2_PHY_1401_DATA 0x00000390 +#define DDRSS2_PHY_1402_DATA 0x00000390 +#define DDRSS2_PHY_1403_DATA 0x00000390 +#define DDRSS2_PHY_1404_DATA 0x00000390 +#define DDRSS2_PHY_1405_DATA 0x00000005 +#define DDRSS2_PHY_1406_DATA 0x01813FCC +#define DDRSS2_PHY_1407_DATA 0x000000CC +#define DDRSS2_PHY_1408_DATA 0x0C000DFF +#define DDRSS2_PHY_1409_DATA 0x30000DFF +#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1411_DATA 0x000100F0 +#define DDRSS2_PHY_1412_DATA 0x780DFFCC +#define DDRSS2_PHY_1413_DATA 0x00007E31 +#define DDRSS2_PHY_1414_DATA 0x000CBF11 +#define DDRSS2_PHY_1415_DATA 0x01990010 +#define DDRSS2_PHY_1416_DATA 0x000CBF11 +#define DDRSS2_PHY_1417_DATA 0x01990010 +#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1419_DATA 0x00EF00F0 +#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1421_DATA 0x01FF00F0 +#define DDRSS2_PHY_1422_DATA 0x20040006 + +#define DDRSS3_CTL_00_DATA 0x00000B00 +#define DDRSS3_CTL_01_DATA 0x00000000 +#define DDRSS3_CTL_02_DATA 0x00000000 +#define DDRSS3_CTL_03_DATA 0x00000000 +#define DDRSS3_CTL_04_DATA 0x00000000 +#define DDRSS3_CTL_05_DATA 0x00000000 +#define DDRSS3_CTL_06_DATA 0x00000000 +#define DDRSS3_CTL_07_DATA 0x00002AF8 +#define DDRSS3_CTL_08_DATA 0x0001ADAF +#define DDRSS3_CTL_09_DATA 0x00000005 +#define DDRSS3_CTL_10_DATA 0x0000006E +#define DDRSS3_CTL_11_DATA 0x000681C8 +#define DDRSS3_CTL_12_DATA 0x004111C9 +#define DDRSS3_CTL_13_DATA 0x00000005 +#define DDRSS3_CTL_14_DATA 0x000010A9 +#define DDRSS3_CTL_15_DATA 0x000681C8 +#define DDRSS3_CTL_16_DATA 0x004111C9 +#define DDRSS3_CTL_17_DATA 0x00000005 +#define DDRSS3_CTL_18_DATA 0x000010A9 +#define DDRSS3_CTL_19_DATA 0x01010000 +#define DDRSS3_CTL_20_DATA 0x02011001 +#define DDRSS3_CTL_21_DATA 0x02010000 +#define DDRSS3_CTL_22_DATA 0x00020100 +#define DDRSS3_CTL_23_DATA 0x0000000B +#define DDRSS3_CTL_24_DATA 0x0000001C +#define DDRSS3_CTL_25_DATA 0x00000000 +#define DDRSS3_CTL_26_DATA 0x00000000 +#define DDRSS3_CTL_27_DATA 0x03020200 +#define DDRSS3_CTL_28_DATA 0x00005656 +#define DDRSS3_CTL_29_DATA 0x00100000 +#define DDRSS3_CTL_30_DATA 0x00000000 +#define DDRSS3_CTL_31_DATA 0x00000000 +#define DDRSS3_CTL_32_DATA 0x00000000 +#define DDRSS3_CTL_33_DATA 0x00000000 +#define DDRSS3_CTL_34_DATA 0x040C0000 +#define DDRSS3_CTL_35_DATA 0x12481248 +#define DDRSS3_CTL_36_DATA 0x00050804 +#define DDRSS3_CTL_37_DATA 0x09040008 +#define DDRSS3_CTL_38_DATA 0x15000204 +#define DDRSS3_CTL_39_DATA 0x1760008B +#define DDRSS3_CTL_40_DATA 0x1500422B +#define DDRSS3_CTL_41_DATA 0x1760008B +#define DDRSS3_CTL_42_DATA 0x2000422B +#define DDRSS3_CTL_43_DATA 0x000A0A09 +#define DDRSS3_CTL_44_DATA 0x0400078A +#define DDRSS3_CTL_45_DATA 0x1E161104 +#define DDRSS3_CTL_46_DATA 0x10012458 +#define DDRSS3_CTL_47_DATA 0x1E161110 +#define DDRSS3_CTL_48_DATA 0x10012458 +#define DDRSS3_CTL_49_DATA 0x02030410 +#define DDRSS3_CTL_50_DATA 0x2C040500 +#define DDRSS3_CTL_51_DATA 0x08292C29 +#define DDRSS3_CTL_52_DATA 0x14000E0A +#define DDRSS3_CTL_53_DATA 0x04010A0A +#define DDRSS3_CTL_54_DATA 0x01010004 +#define DDRSS3_CTL_55_DATA 0x04545408 +#define DDRSS3_CTL_56_DATA 0x04313104 +#define DDRSS3_CTL_57_DATA 0x00003131 +#define DDRSS3_CTL_58_DATA 0x00010100 +#define DDRSS3_CTL_59_DATA 0x03010000 +#define DDRSS3_CTL_60_DATA 0x00001508 +#define DDRSS3_CTL_61_DATA 0x000000CE +#define DDRSS3_CTL_62_DATA 0x0000032B +#define DDRSS3_CTL_63_DATA 0x00002073 +#define DDRSS3_CTL_64_DATA 0x0000032B +#define DDRSS3_CTL_65_DATA 0x00002073 +#define DDRSS3_CTL_66_DATA 0x00000005 +#define DDRSS3_CTL_67_DATA 0x00050000 +#define DDRSS3_CTL_68_DATA 0x00CB0012 +#define DDRSS3_CTL_69_DATA 0x00CB0408 +#define DDRSS3_CTL_70_DATA 0x00400408 +#define DDRSS3_CTL_71_DATA 0x00120103 +#define DDRSS3_CTL_72_DATA 0x00100005 +#define DDRSS3_CTL_73_DATA 0x2F080010 +#define DDRSS3_CTL_74_DATA 0x0505012F +#define DDRSS3_CTL_75_DATA 0x0401030A +#define DDRSS3_CTL_76_DATA 0x041E100B +#define DDRSS3_CTL_77_DATA 0x100B0401 +#define DDRSS3_CTL_78_DATA 0x0001041E +#define DDRSS3_CTL_79_DATA 0x00160016 +#define DDRSS3_CTL_80_DATA 0x033B033B +#define DDRSS3_CTL_81_DATA 0x033B033B +#define DDRSS3_CTL_82_DATA 0x03050505 +#define DDRSS3_CTL_83_DATA 0x03010303 +#define DDRSS3_CTL_84_DATA 0x200B100B +#define DDRSS3_CTL_85_DATA 0x04041004 +#define DDRSS3_CTL_86_DATA 0x200B100B +#define DDRSS3_CTL_87_DATA 0x04041004 +#define DDRSS3_CTL_88_DATA 0x03010000 +#define DDRSS3_CTL_89_DATA 0x00010000 +#define DDRSS3_CTL_90_DATA 0x00000000 +#define DDRSS3_CTL_91_DATA 0x00000000 +#define DDRSS3_CTL_92_DATA 0x01000000 +#define DDRSS3_CTL_93_DATA 0x80104002 +#define DDRSS3_CTL_94_DATA 0x00000000 +#define DDRSS3_CTL_95_DATA 0x00040005 +#define DDRSS3_CTL_96_DATA 0x00000000 +#define DDRSS3_CTL_97_DATA 0x00050000 +#define DDRSS3_CTL_98_DATA 0x00000004 +#define DDRSS3_CTL_99_DATA 0x00000000 +#define DDRSS3_CTL_100_DATA 0x00040005 +#define DDRSS3_CTL_101_DATA 0x00000000 +#define DDRSS3_CTL_102_DATA 0x00003380 +#define DDRSS3_CTL_103_DATA 0x00003380 +#define DDRSS3_CTL_104_DATA 0x00003380 +#define DDRSS3_CTL_105_DATA 0x00003380 +#define DDRSS3_CTL_106_DATA 0x00003380 +#define DDRSS3_CTL_107_DATA 0x00000000 +#define DDRSS3_CTL_108_DATA 0x000005A2 +#define DDRSS3_CTL_109_DATA 0x00081CC0 +#define DDRSS3_CTL_110_DATA 0x00081CC0 +#define DDRSS3_CTL_111_DATA 0x00081CC0 +#define DDRSS3_CTL_112_DATA 0x00081CC0 +#define DDRSS3_CTL_113_DATA 0x00081CC0 +#define DDRSS3_CTL_114_DATA 0x00000000 +#define DDRSS3_CTL_115_DATA 0x0000E325 +#define DDRSS3_CTL_116_DATA 0x00081CC0 +#define DDRSS3_CTL_117_DATA 0x00081CC0 +#define DDRSS3_CTL_118_DATA 0x00081CC0 +#define DDRSS3_CTL_119_DATA 0x00081CC0 +#define DDRSS3_CTL_120_DATA 0x00081CC0 +#define DDRSS3_CTL_121_DATA 0x00000000 +#define DDRSS3_CTL_122_DATA 0x0000E325 +#define DDRSS3_CTL_123_DATA 0x00000000 +#define DDRSS3_CTL_124_DATA 0x00000000 +#define DDRSS3_CTL_125_DATA 0x00000000 +#define DDRSS3_CTL_126_DATA 0x00000000 +#define DDRSS3_CTL_127_DATA 0x00000000 +#define DDRSS3_CTL_128_DATA 0x00000000 +#define DDRSS3_CTL_129_DATA 0x00000000 +#define DDRSS3_CTL_130_DATA 0x00000000 +#define DDRSS3_CTL_131_DATA 0x0B030500 +#define DDRSS3_CTL_132_DATA 0x00040B04 +#define DDRSS3_CTL_133_DATA 0x0A090000 +#define DDRSS3_CTL_134_DATA 0x0A090701 +#define DDRSS3_CTL_135_DATA 0x0900000E +#define DDRSS3_CTL_136_DATA 0x0907010A +#define DDRSS3_CTL_137_DATA 0x00000E0A +#define DDRSS3_CTL_138_DATA 0x07010A09 +#define DDRSS3_CTL_139_DATA 0x000E0A09 +#define DDRSS3_CTL_140_DATA 0x07000401 +#define DDRSS3_CTL_141_DATA 0x00000000 +#define DDRSS3_CTL_142_DATA 0x00000000 +#define DDRSS3_CTL_143_DATA 0x00000000 +#define DDRSS3_CTL_144_DATA 0x00000000 +#define DDRSS3_CTL_145_DATA 0x00000000 +#define DDRSS3_CTL_146_DATA 0x00000000 +#define DDRSS3_CTL_147_DATA 0x00000000 +#define DDRSS3_CTL_148_DATA 0x08080000 +#define DDRSS3_CTL_149_DATA 0x01000000 +#define DDRSS3_CTL_150_DATA 0x800000C0 +#define DDRSS3_CTL_151_DATA 0x800000C0 +#define DDRSS3_CTL_152_DATA 0x800000C0 +#define DDRSS3_CTL_153_DATA 0x00000000 +#define DDRSS3_CTL_154_DATA 0x00001500 +#define DDRSS3_CTL_155_DATA 0x00000000 +#define DDRSS3_CTL_156_DATA 0x00000001 +#define DDRSS3_CTL_157_DATA 0x00000002 +#define DDRSS3_CTL_158_DATA 0x0000100E +#define DDRSS3_CTL_159_DATA 0x00000000 +#define DDRSS3_CTL_160_DATA 0x00000000 +#define DDRSS3_CTL_161_DATA 0x00000000 +#define DDRSS3_CTL_162_DATA 0x00000000 +#define DDRSS3_CTL_163_DATA 0x00000000 +#define DDRSS3_CTL_164_DATA 0x000B0000 +#define DDRSS3_CTL_165_DATA 0x000E0006 +#define DDRSS3_CTL_166_DATA 0x000E0404 +#define DDRSS3_CTL_167_DATA 0x00D601AB +#define DDRSS3_CTL_168_DATA 0x10100216 +#define DDRSS3_CTL_169_DATA 0x01AB0216 +#define DDRSS3_CTL_170_DATA 0x021600D6 +#define DDRSS3_CTL_171_DATA 0x02161010 +#define DDRSS3_CTL_172_DATA 0x00000000 +#define DDRSS3_CTL_173_DATA 0x00000000 +#define DDRSS3_CTL_174_DATA 0x00000000 +#define DDRSS3_CTL_175_DATA 0x3FF40084 +#define DDRSS3_CTL_176_DATA 0x33003FF4 +#define DDRSS3_CTL_177_DATA 0x00003333 +#define DDRSS3_CTL_178_DATA 0x35000000 +#define DDRSS3_CTL_179_DATA 0x27270035 +#define DDRSS3_CTL_180_DATA 0x0F0F0000 +#define DDRSS3_CTL_181_DATA 0x16000000 +#define DDRSS3_CTL_182_DATA 0x00841616 +#define DDRSS3_CTL_183_DATA 0x3FF43FF4 +#define DDRSS3_CTL_184_DATA 0x33333300 +#define DDRSS3_CTL_185_DATA 0x00000000 +#define DDRSS3_CTL_186_DATA 0x00353500 +#define DDRSS3_CTL_187_DATA 0x00002727 +#define DDRSS3_CTL_188_DATA 0x00000F0F +#define DDRSS3_CTL_189_DATA 0x16161600 +#define DDRSS3_CTL_190_DATA 0x00000020 +#define DDRSS3_CTL_191_DATA 0x00000000 +#define DDRSS3_CTL_192_DATA 0x00000001 +#define DDRSS3_CTL_193_DATA 0x00000000 +#define DDRSS3_CTL_194_DATA 0x01000000 +#define DDRSS3_CTL_195_DATA 0x00000001 +#define DDRSS3_CTL_196_DATA 0x00000000 +#define DDRSS3_CTL_197_DATA 0x00000000 +#define DDRSS3_CTL_198_DATA 0x00000000 +#define DDRSS3_CTL_199_DATA 0x00000000 +#define DDRSS3_CTL_200_DATA 0x00000000 +#define DDRSS3_CTL_201_DATA 0x00000000 +#define DDRSS3_CTL_202_DATA 0x00000000 +#define DDRSS3_CTL_203_DATA 0x00000000 +#define DDRSS3_CTL_204_DATA 0x00000000 +#define DDRSS3_CTL_205_DATA 0x00000000 +#define DDRSS3_CTL_206_DATA 0x02000000 +#define DDRSS3_CTL_207_DATA 0x01080101 +#define DDRSS3_CTL_208_DATA 0x00000000 +#define DDRSS3_CTL_209_DATA 0x00000000 +#define DDRSS3_CTL_210_DATA 0x00000000 +#define DDRSS3_CTL_211_DATA 0x00000000 +#define DDRSS3_CTL_212_DATA 0x00000000 +#define DDRSS3_CTL_213_DATA 0x00000000 +#define DDRSS3_CTL_214_DATA 0x00000000 +#define DDRSS3_CTL_215_DATA 0x00000000 +#define DDRSS3_CTL_216_DATA 0x00000000 +#define DDRSS3_CTL_217_DATA 0x00000000 +#define DDRSS3_CTL_218_DATA 0x00000000 +#define DDRSS3_CTL_219_DATA 0x00000000 +#define DDRSS3_CTL_220_DATA 0x00000000 +#define DDRSS3_CTL_221_DATA 0x00000000 +#define DDRSS3_CTL_222_DATA 0x00001000 +#define DDRSS3_CTL_223_DATA 0x006403E8 +#define DDRSS3_CTL_224_DATA 0x00000000 +#define DDRSS3_CTL_225_DATA 0x00000000 +#define DDRSS3_CTL_226_DATA 0x00000000 +#define DDRSS3_CTL_227_DATA 0x15110000 +#define DDRSS3_CTL_228_DATA 0x00040C18 +#define DDRSS3_CTL_229_DATA 0xF000C000 +#define DDRSS3_CTL_230_DATA 0x0000F000 +#define DDRSS3_CTL_231_DATA 0x00000000 +#define DDRSS3_CTL_232_DATA 0x00000000 +#define DDRSS3_CTL_233_DATA 0xC0000000 +#define DDRSS3_CTL_234_DATA 0xF000F000 +#define DDRSS3_CTL_235_DATA 0x00000000 +#define DDRSS3_CTL_236_DATA 0x00000000 +#define DDRSS3_CTL_237_DATA 0x00000000 +#define DDRSS3_CTL_238_DATA 0xF000C000 +#define DDRSS3_CTL_239_DATA 0x0000F000 +#define DDRSS3_CTL_240_DATA 0x00000000 +#define DDRSS3_CTL_241_DATA 0x00000000 +#define DDRSS3_CTL_242_DATA 0x00030000 +#define DDRSS3_CTL_243_DATA 0x00000000 +#define DDRSS3_CTL_244_DATA 0x00000000 +#define DDRSS3_CTL_245_DATA 0x00000000 +#define DDRSS3_CTL_246_DATA 0x00000000 +#define DDRSS3_CTL_247_DATA 0x00000000 +#define DDRSS3_CTL_248_DATA 0x00000000 +#define DDRSS3_CTL_249_DATA 0x00000000 +#define DDRSS3_CTL_250_DATA 0x00000000 +#define DDRSS3_CTL_251_DATA 0x00000000 +#define DDRSS3_CTL_252_DATA 0x00000000 +#define DDRSS3_CTL_253_DATA 0x00000000 +#define DDRSS3_CTL_254_DATA 0x00000000 +#define DDRSS3_CTL_255_DATA 0x00000000 +#define DDRSS3_CTL_256_DATA 0x00000000 +#define DDRSS3_CTL_257_DATA 0x01000200 +#define DDRSS3_CTL_258_DATA 0x00370040 +#define DDRSS3_CTL_259_DATA 0x00020008 +#define DDRSS3_CTL_260_DATA 0x00400100 +#define DDRSS3_CTL_261_DATA 0x00400855 +#define DDRSS3_CTL_262_DATA 0x01000200 +#define DDRSS3_CTL_263_DATA 0x08550040 +#define DDRSS3_CTL_264_DATA 0x00000040 +#define DDRSS3_CTL_265_DATA 0x006B0003 +#define DDRSS3_CTL_266_DATA 0x0100006B +#define DDRSS3_CTL_267_DATA 0x03030303 +#define DDRSS3_CTL_268_DATA 0x00000000 +#define DDRSS3_CTL_269_DATA 0x00000202 +#define DDRSS3_CTL_270_DATA 0x00001FFF +#define DDRSS3_CTL_271_DATA 0x3FFF2000 +#define DDRSS3_CTL_272_DATA 0x03FF0000 +#define DDRSS3_CTL_273_DATA 0x000103FF +#define DDRSS3_CTL_274_DATA 0x0FFF0B00 +#define DDRSS3_CTL_275_DATA 0x01010001 +#define DDRSS3_CTL_276_DATA 0x01010101 +#define DDRSS3_CTL_277_DATA 0x01180101 +#define DDRSS3_CTL_278_DATA 0x00030000 +#define DDRSS3_CTL_279_DATA 0x00000000 +#define DDRSS3_CTL_280_DATA 0x00000000 +#define DDRSS3_CTL_281_DATA 0x00000000 +#define DDRSS3_CTL_282_DATA 0x00000000 +#define DDRSS3_CTL_283_DATA 0x00000000 +#define DDRSS3_CTL_284_DATA 0x00000000 +#define DDRSS3_CTL_285_DATA 0x00000000 +#define DDRSS3_CTL_286_DATA 0x00040101 +#define DDRSS3_CTL_287_DATA 0x04010100 +#define DDRSS3_CTL_288_DATA 0x00000000 +#define DDRSS3_CTL_289_DATA 0x00000000 +#define DDRSS3_CTL_290_DATA 0x03030300 +#define DDRSS3_CTL_291_DATA 0x00000001 +#define DDRSS3_CTL_292_DATA 0x00000000 +#define DDRSS3_CTL_293_DATA 0x00000000 +#define DDRSS3_CTL_294_DATA 0x00000000 +#define DDRSS3_CTL_295_DATA 0x00000000 +#define DDRSS3_CTL_296_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0x00000000 +#define DDRSS3_CTL_298_DATA 0x00000000 +#define DDRSS3_CTL_299_DATA 0x00000000 +#define DDRSS3_CTL_300_DATA 0x00000000 +#define DDRSS3_CTL_301_DATA 0x00000000 +#define DDRSS3_CTL_302_DATA 0x00000000 +#define DDRSS3_CTL_303_DATA 0x00000000 +#define DDRSS3_CTL_304_DATA 0x00000000 +#define DDRSS3_CTL_305_DATA 0x00000000 +#define DDRSS3_CTL_306_DATA 0x00000000 +#define DDRSS3_CTL_307_DATA 0x00000000 +#define DDRSS3_CTL_308_DATA 0x00000000 +#define DDRSS3_CTL_309_DATA 0x00000000 +#define DDRSS3_CTL_310_DATA 0x00000000 +#define DDRSS3_CTL_311_DATA 0x00000000 +#define DDRSS3_CTL_312_DATA 0x00000000 +#define DDRSS3_CTL_313_DATA 0x01000000 +#define DDRSS3_CTL_314_DATA 0x00020201 +#define DDRSS3_CTL_315_DATA 0x01000101 +#define DDRSS3_CTL_316_DATA 0x01010001 +#define DDRSS3_CTL_317_DATA 0x00010101 +#define DDRSS3_CTL_318_DATA 0x050A0A03 +#define DDRSS3_CTL_319_DATA 0x10081F1F +#define DDRSS3_CTL_320_DATA 0x00090310 +#define DDRSS3_CTL_321_DATA 0x0B0C030F +#define DDRSS3_CTL_322_DATA 0x0B0C0306 +#define DDRSS3_CTL_323_DATA 0x0C090006 +#define DDRSS3_CTL_324_DATA 0x0100000C +#define DDRSS3_CTL_325_DATA 0x08040801 +#define DDRSS3_CTL_326_DATA 0x00000004 +#define DDRSS3_CTL_327_DATA 0x00000000 +#define DDRSS3_CTL_328_DATA 0x00010000 +#define DDRSS3_CTL_329_DATA 0x00280D00 +#define DDRSS3_CTL_330_DATA 0x00000001 +#define DDRSS3_CTL_331_DATA 0x00030001 +#define DDRSS3_CTL_332_DATA 0x00000000 +#define DDRSS3_CTL_333_DATA 0x00000000 +#define DDRSS3_CTL_334_DATA 0x00000000 +#define DDRSS3_CTL_335_DATA 0x00000000 +#define DDRSS3_CTL_336_DATA 0x00000000 +#define DDRSS3_CTL_337_DATA 0x00000000 +#define DDRSS3_CTL_338_DATA 0x00000000 +#define DDRSS3_CTL_339_DATA 0x00000000 +#define DDRSS3_CTL_340_DATA 0x01000000 +#define DDRSS3_CTL_341_DATA 0x00000001 +#define DDRSS3_CTL_342_DATA 0x00010100 +#define DDRSS3_CTL_343_DATA 0x03030000 +#define DDRSS3_CTL_344_DATA 0x00000000 +#define DDRSS3_CTL_345_DATA 0x00000000 +#define DDRSS3_CTL_346_DATA 0x00000000 +#define DDRSS3_CTL_347_DATA 0x00000000 +#define DDRSS3_CTL_348_DATA 0x00000000 +#define DDRSS3_CTL_349_DATA 0x00000000 +#define DDRSS3_CTL_350_DATA 0x00000000 +#define DDRSS3_CTL_351_DATA 0x00000000 +#define DDRSS3_CTL_352_DATA 0x00000000 +#define DDRSS3_CTL_353_DATA 0x00000000 +#define DDRSS3_CTL_354_DATA 0x00000000 +#define DDRSS3_CTL_355_DATA 0x00000000 +#define DDRSS3_CTL_356_DATA 0x00000000 +#define DDRSS3_CTL_357_DATA 0x00000000 +#define DDRSS3_CTL_358_DATA 0x00000000 +#define DDRSS3_CTL_359_DATA 0x00000000 +#define DDRSS3_CTL_360_DATA 0x000556AA +#define DDRSS3_CTL_361_DATA 0x000AAAAA +#define DDRSS3_CTL_362_DATA 0x000AA955 +#define DDRSS3_CTL_363_DATA 0x00055555 +#define DDRSS3_CTL_364_DATA 0x000B3133 +#define DDRSS3_CTL_365_DATA 0x0004CD33 +#define DDRSS3_CTL_366_DATA 0x0004CECC +#define DDRSS3_CTL_367_DATA 0x000B32CC +#define DDRSS3_CTL_368_DATA 0x00010300 +#define DDRSS3_CTL_369_DATA 0x03000100 +#define DDRSS3_CTL_370_DATA 0x00000000 +#define DDRSS3_CTL_371_DATA 0x00000000 +#define DDRSS3_CTL_372_DATA 0x00000000 +#define DDRSS3_CTL_373_DATA 0x00000000 +#define DDRSS3_CTL_374_DATA 0x00000000 +#define DDRSS3_CTL_375_DATA 0x00000000 +#define DDRSS3_CTL_376_DATA 0x00000000 +#define DDRSS3_CTL_377_DATA 0x00010000 +#define DDRSS3_CTL_378_DATA 0x00000404 +#define DDRSS3_CTL_379_DATA 0x00000000 +#define DDRSS3_CTL_380_DATA 0x00000000 +#define DDRSS3_CTL_381_DATA 0x00000000 +#define DDRSS3_CTL_382_DATA 0x00000000 +#define DDRSS3_CTL_383_DATA 0x00000000 +#define DDRSS3_CTL_384_DATA 0x00000000 +#define DDRSS3_CTL_385_DATA 0x00000000 +#define DDRSS3_CTL_386_DATA 0x00000000 +#define DDRSS3_CTL_387_DATA 0x3A3A1B00 +#define DDRSS3_CTL_388_DATA 0x000A0000 +#define DDRSS3_CTL_389_DATA 0x0000019C +#define DDRSS3_CTL_390_DATA 0x00000200 +#define DDRSS3_CTL_391_DATA 0x00000200 +#define DDRSS3_CTL_392_DATA 0x00000200 +#define DDRSS3_CTL_393_DATA 0x00000200 +#define DDRSS3_CTL_394_DATA 0x000004D4 +#define DDRSS3_CTL_395_DATA 0x00001018 +#define DDRSS3_CTL_396_DATA 0x00000204 +#define DDRSS3_CTL_397_DATA 0x000040E6 +#define DDRSS3_CTL_398_DATA 0x00000200 +#define DDRSS3_CTL_399_DATA 0x00000200 +#define DDRSS3_CTL_400_DATA 0x00000200 +#define DDRSS3_CTL_401_DATA 0x00000200 +#define DDRSS3_CTL_402_DATA 0x0000C2B2 +#define DDRSS3_CTL_403_DATA 0x000288FC +#define DDRSS3_CTL_404_DATA 0x00000E15 +#define DDRSS3_CTL_405_DATA 0x000040E6 +#define DDRSS3_CTL_406_DATA 0x00000200 +#define DDRSS3_CTL_407_DATA 0x00000200 +#define DDRSS3_CTL_408_DATA 0x00000200 +#define DDRSS3_CTL_409_DATA 0x00000200 +#define DDRSS3_CTL_410_DATA 0x0000C2B2 +#define DDRSS3_CTL_411_DATA 0x000288FC +#define DDRSS3_CTL_412_DATA 0x02020E15 +#define DDRSS3_CTL_413_DATA 0x03030202 +#define DDRSS3_CTL_414_DATA 0x00000022 +#define DDRSS3_CTL_415_DATA 0x00000000 +#define DDRSS3_CTL_416_DATA 0x00000000 +#define DDRSS3_CTL_417_DATA 0x00001403 +#define DDRSS3_CTL_418_DATA 0x000007D0 +#define DDRSS3_CTL_419_DATA 0x00000000 +#define DDRSS3_CTL_420_DATA 0x00000000 +#define DDRSS3_CTL_421_DATA 0x00030000 +#define DDRSS3_CTL_422_DATA 0x0007001F +#define DDRSS3_CTL_423_DATA 0x001B0033 +#define DDRSS3_CTL_424_DATA 0x001B0033 +#define DDRSS3_CTL_425_DATA 0x00000000 +#define DDRSS3_CTL_426_DATA 0x00000000 +#define DDRSS3_CTL_427_DATA 0x02000000 +#define DDRSS3_CTL_428_DATA 0x01000404 +#define DDRSS3_CTL_429_DATA 0x0B1E0B1E +#define DDRSS3_CTL_430_DATA 0x00000105 +#define DDRSS3_CTL_431_DATA 0x00010101 +#define DDRSS3_CTL_432_DATA 0x00010101 +#define DDRSS3_CTL_433_DATA 0x00010001 +#define DDRSS3_CTL_434_DATA 0x00000101 +#define DDRSS3_CTL_435_DATA 0x02000201 +#define DDRSS3_CTL_436_DATA 0x02010000 +#define DDRSS3_CTL_437_DATA 0x00000200 +#define DDRSS3_CTL_438_DATA 0x28060000 +#define DDRSS3_CTL_439_DATA 0x00000128 +#define DDRSS3_CTL_440_DATA 0xFFFFFFFF +#define DDRSS3_CTL_441_DATA 0xFFFFFFFF +#define DDRSS3_CTL_442_DATA 0x00000000 +#define DDRSS3_CTL_443_DATA 0x00000000 +#define DDRSS3_CTL_444_DATA 0x00000000 +#define DDRSS3_CTL_445_DATA 0x00000000 +#define DDRSS3_CTL_446_DATA 0x00000000 +#define DDRSS3_CTL_447_DATA 0x00000000 +#define DDRSS3_CTL_448_DATA 0x00000000 +#define DDRSS3_CTL_449_DATA 0x00000000 +#define DDRSS3_CTL_450_DATA 0x00000000 +#define DDRSS3_CTL_451_DATA 0x00000000 +#define DDRSS3_CTL_452_DATA 0x00000000 +#define DDRSS3_CTL_453_DATA 0x00000000 +#define DDRSS3_CTL_454_DATA 0x00000000 +#define DDRSS3_CTL_455_DATA 0x00000000 +#define DDRSS3_CTL_456_DATA 0x00000000 +#define DDRSS3_CTL_457_DATA 0x00000000 +#define DDRSS3_CTL_458_DATA 0x00000000 + +#define DDRSS3_PI_00_DATA 0x00000B00 +#define DDRSS3_PI_01_DATA 0x00000000 +#define DDRSS3_PI_02_DATA 0x00000000 +#define DDRSS3_PI_03_DATA 0x00000000 +#define DDRSS3_PI_04_DATA 0x00000000 +#define DDRSS3_PI_05_DATA 0x00000101 +#define DDRSS3_PI_06_DATA 0x00640000 +#define DDRSS3_PI_07_DATA 0x00000001 +#define DDRSS3_PI_08_DATA 0x00000000 +#define DDRSS3_PI_09_DATA 0x00000000 +#define DDRSS3_PI_10_DATA 0x00000000 +#define DDRSS3_PI_11_DATA 0x00000000 +#define DDRSS3_PI_12_DATA 0x00000007 +#define DDRSS3_PI_13_DATA 0x00010002 +#define DDRSS3_PI_14_DATA 0x0800000F +#define DDRSS3_PI_15_DATA 0x00000103 +#define DDRSS3_PI_16_DATA 0x00000005 +#define DDRSS3_PI_17_DATA 0x00000000 +#define DDRSS3_PI_18_DATA 0x00000000 +#define DDRSS3_PI_19_DATA 0x00000000 +#define DDRSS3_PI_20_DATA 0x00000000 +#define DDRSS3_PI_21_DATA 0x00000000 +#define DDRSS3_PI_22_DATA 0x00000000 +#define DDRSS3_PI_23_DATA 0x00000000 +#define DDRSS3_PI_24_DATA 0x00000000 +#define DDRSS3_PI_25_DATA 0x00000000 +#define DDRSS3_PI_26_DATA 0x00010100 +#define DDRSS3_PI_27_DATA 0x00280A00 +#define DDRSS3_PI_28_DATA 0x00000000 +#define DDRSS3_PI_29_DATA 0x0F000000 +#define DDRSS3_PI_30_DATA 0x00003200 +#define DDRSS3_PI_31_DATA 0x00000000 +#define DDRSS3_PI_32_DATA 0x00000000 +#define DDRSS3_PI_33_DATA 0x01010102 +#define DDRSS3_PI_34_DATA 0x00000000 +#define DDRSS3_PI_35_DATA 0x000000AA +#define DDRSS3_PI_36_DATA 0x00000055 +#define DDRSS3_PI_37_DATA 0x000000B5 +#define DDRSS3_PI_38_DATA 0x0000004A +#define DDRSS3_PI_39_DATA 0x00000056 +#define DDRSS3_PI_40_DATA 0x000000A9 +#define DDRSS3_PI_41_DATA 0x000000A9 +#define DDRSS3_PI_42_DATA 0x000000B5 +#define DDRSS3_PI_43_DATA 0x00000000 +#define DDRSS3_PI_44_DATA 0x00000000 +#define DDRSS3_PI_45_DATA 0x000F0F00 +#define DDRSS3_PI_46_DATA 0x0000001B +#define DDRSS3_PI_47_DATA 0x000007D0 +#define DDRSS3_PI_48_DATA 0x00000300 +#define DDRSS3_PI_49_DATA 0x00000000 +#define DDRSS3_PI_50_DATA 0x00000000 +#define DDRSS3_PI_51_DATA 0x01000000 +#define DDRSS3_PI_52_DATA 0x00010101 +#define DDRSS3_PI_53_DATA 0x00000000 +#define DDRSS3_PI_54_DATA 0x00030000 +#define DDRSS3_PI_55_DATA 0x0F000000 +#define DDRSS3_PI_56_DATA 0x00000017 +#define DDRSS3_PI_57_DATA 0x00000000 +#define DDRSS3_PI_58_DATA 0x00000000 +#define DDRSS3_PI_59_DATA 0x00000000 +#define DDRSS3_PI_60_DATA 0x0A0A140A +#define DDRSS3_PI_61_DATA 0x10020101 +#define DDRSS3_PI_62_DATA 0x00020805 +#define DDRSS3_PI_63_DATA 0x01000404 +#define DDRSS3_PI_64_DATA 0x00000000 +#define DDRSS3_PI_65_DATA 0x00000000 +#define DDRSS3_PI_66_DATA 0x00000100 +#define DDRSS3_PI_67_DATA 0x0001010F +#define DDRSS3_PI_68_DATA 0x00340000 +#define DDRSS3_PI_69_DATA 0x00000000 +#define DDRSS3_PI_70_DATA 0x00000000 +#define DDRSS3_PI_71_DATA 0x0000FFFF +#define DDRSS3_PI_72_DATA 0x00000000 +#define DDRSS3_PI_73_DATA 0x00080000 +#define DDRSS3_PI_74_DATA 0x02000200 +#define DDRSS3_PI_75_DATA 0x01000100 +#define DDRSS3_PI_76_DATA 0x01000000 +#define DDRSS3_PI_77_DATA 0x02000200 +#define DDRSS3_PI_78_DATA 0x00000200 +#define DDRSS3_PI_79_DATA 0x00000000 +#define DDRSS3_PI_80_DATA 0x00000000 +#define DDRSS3_PI_81_DATA 0x00000000 +#define DDRSS3_PI_82_DATA 0x00000000 +#define DDRSS3_PI_83_DATA 0x00000000 +#define DDRSS3_PI_84_DATA 0x00000000 +#define DDRSS3_PI_85_DATA 0x00000000 +#define DDRSS3_PI_86_DATA 0x00000000 +#define DDRSS3_PI_87_DATA 0x00000000 +#define DDRSS3_PI_88_DATA 0x00000000 +#define DDRSS3_PI_89_DATA 0x00000000 +#define DDRSS3_PI_90_DATA 0x00000000 +#define DDRSS3_PI_91_DATA 0x00000400 +#define DDRSS3_PI_92_DATA 0x02010000 +#define DDRSS3_PI_93_DATA 0x00080003 +#define DDRSS3_PI_94_DATA 0x00080000 +#define DDRSS3_PI_95_DATA 0x00000001 +#define DDRSS3_PI_96_DATA 0x00000000 +#define DDRSS3_PI_97_DATA 0x0000AA00 +#define DDRSS3_PI_98_DATA 0x00000000 +#define DDRSS3_PI_99_DATA 0x00000000 +#define DDRSS3_PI_100_DATA 0x00010000 +#define DDRSS3_PI_101_DATA 0x00000000 +#define DDRSS3_PI_102_DATA 0x00000000 +#define DDRSS3_PI_103_DATA 0x00000000 +#define DDRSS3_PI_104_DATA 0x00000000 +#define DDRSS3_PI_105_DATA 0x00000000 +#define DDRSS3_PI_106_DATA 0x00000000 +#define DDRSS3_PI_107_DATA 0x00000000 +#define DDRSS3_PI_108_DATA 0x00000000 +#define DDRSS3_PI_109_DATA 0x00000000 +#define DDRSS3_PI_110_DATA 0x00000000 +#define DDRSS3_PI_111_DATA 0x00000000 +#define DDRSS3_PI_112_DATA 0x00000000 +#define DDRSS3_PI_113_DATA 0x00000000 +#define DDRSS3_PI_114_DATA 0x00000000 +#define DDRSS3_PI_115_DATA 0x00000000 +#define DDRSS3_PI_116_DATA 0x00000000 +#define DDRSS3_PI_117_DATA 0x00000000 +#define DDRSS3_PI_118_DATA 0x00000000 +#define DDRSS3_PI_119_DATA 0x00000000 +#define DDRSS3_PI_120_DATA 0x00000000 +#define DDRSS3_PI_121_DATA 0x00000000 +#define DDRSS3_PI_122_DATA 0x00000000 +#define DDRSS3_PI_123_DATA 0x00000000 +#define DDRSS3_PI_124_DATA 0x00000000 +#define DDRSS3_PI_125_DATA 0x00000008 +#define DDRSS3_PI_126_DATA 0x00000000 +#define DDRSS3_PI_127_DATA 0x00000000 +#define DDRSS3_PI_128_DATA 0x00000000 +#define DDRSS3_PI_129_DATA 0x00000000 +#define DDRSS3_PI_130_DATA 0x00000000 +#define DDRSS3_PI_131_DATA 0x00000000 +#define DDRSS3_PI_132_DATA 0x00000000 +#define DDRSS3_PI_133_DATA 0x00000000 +#define DDRSS3_PI_134_DATA 0x00000002 +#define DDRSS3_PI_135_DATA 0x00000000 +#define DDRSS3_PI_136_DATA 0x00000000 +#define DDRSS3_PI_137_DATA 0x0000000A +#define DDRSS3_PI_138_DATA 0x00000019 +#define DDRSS3_PI_139_DATA 0x00000100 +#define DDRSS3_PI_140_DATA 0x00000000 +#define DDRSS3_PI_141_DATA 0x00000000 +#define DDRSS3_PI_142_DATA 0x00000000 +#define DDRSS3_PI_143_DATA 0x00000000 +#define DDRSS3_PI_144_DATA 0x01000000 +#define DDRSS3_PI_145_DATA 0x00010003 +#define DDRSS3_PI_146_DATA 0x02000101 +#define DDRSS3_PI_147_DATA 0x01030001 +#define DDRSS3_PI_148_DATA 0x00010400 +#define DDRSS3_PI_149_DATA 0x06000105 +#define DDRSS3_PI_150_DATA 0x01070001 +#define DDRSS3_PI_151_DATA 0x00000000 +#define DDRSS3_PI_152_DATA 0x00000000 +#define DDRSS3_PI_153_DATA 0x00000000 +#define DDRSS3_PI_154_DATA 0x00010001 +#define DDRSS3_PI_155_DATA 0x00000000 +#define DDRSS3_PI_156_DATA 0x00000000 +#define DDRSS3_PI_157_DATA 0x00000000 +#define DDRSS3_PI_158_DATA 0x00000000 +#define DDRSS3_PI_159_DATA 0x00000401 +#define DDRSS3_PI_160_DATA 0x00000000 +#define DDRSS3_PI_161_DATA 0x00010000 +#define DDRSS3_PI_162_DATA 0x00000000 +#define DDRSS3_PI_163_DATA 0x2B2B0200 +#define DDRSS3_PI_164_DATA 0x00000034 +#define DDRSS3_PI_165_DATA 0x00000064 +#define DDRSS3_PI_166_DATA 0x00020064 +#define DDRSS3_PI_167_DATA 0x02000200 +#define DDRSS3_PI_168_DATA 0x48120C04 +#define DDRSS3_PI_169_DATA 0x00154812 +#define DDRSS3_PI_170_DATA 0x000000CE +#define DDRSS3_PI_171_DATA 0x0000032B +#define DDRSS3_PI_172_DATA 0x00002073 +#define DDRSS3_PI_173_DATA 0x0000032B +#define DDRSS3_PI_174_DATA 0x04002073 +#define DDRSS3_PI_175_DATA 0x01010404 +#define DDRSS3_PI_176_DATA 0x00001501 +#define DDRSS3_PI_177_DATA 0x00150015 +#define DDRSS3_PI_178_DATA 0x01000100 +#define DDRSS3_PI_179_DATA 0x00000100 +#define DDRSS3_PI_180_DATA 0x00000000 +#define DDRSS3_PI_181_DATA 0x01010101 +#define DDRSS3_PI_182_DATA 0x00000101 +#define DDRSS3_PI_183_DATA 0x00000000 +#define DDRSS3_PI_184_DATA 0x00000000 +#define DDRSS3_PI_185_DATA 0x15040000 +#define DDRSS3_PI_186_DATA 0x0E0E0215 +#define DDRSS3_PI_187_DATA 0x00040402 +#define DDRSS3_PI_188_DATA 0x000D0035 +#define DDRSS3_PI_189_DATA 0x00218049 +#define DDRSS3_PI_190_DATA 0x00218049 +#define DDRSS3_PI_191_DATA 0x01010101 +#define DDRSS3_PI_192_DATA 0x0004000E +#define DDRSS3_PI_193_DATA 0x00040216 +#define DDRSS3_PI_194_DATA 0x01000216 +#define DDRSS3_PI_195_DATA 0x000F000F +#define DDRSS3_PI_196_DATA 0x02170100 +#define DDRSS3_PI_197_DATA 0x01000217 +#define DDRSS3_PI_198_DATA 0x02170217 +#define DDRSS3_PI_199_DATA 0x32103200 +#define DDRSS3_PI_200_DATA 0x01013210 +#define DDRSS3_PI_201_DATA 0x0A070601 +#define DDRSS3_PI_202_DATA 0x1F130A0D +#define DDRSS3_PI_203_DATA 0x1F130A14 +#define DDRSS3_PI_204_DATA 0x0000C014 +#define DDRSS3_PI_205_DATA 0x00C01000 +#define DDRSS3_PI_206_DATA 0x00C01000 +#define DDRSS3_PI_207_DATA 0x00021000 +#define DDRSS3_PI_208_DATA 0x0024000E +#define DDRSS3_PI_209_DATA 0x00240216 +#define DDRSS3_PI_210_DATA 0x00110216 +#define DDRSS3_PI_211_DATA 0x32000056 +#define DDRSS3_PI_212_DATA 0x00000301 +#define DDRSS3_PI_213_DATA 0x005B0036 +#define DDRSS3_PI_214_DATA 0x03013212 +#define DDRSS3_PI_215_DATA 0x00003600 +#define DDRSS3_PI_216_DATA 0x3212005B +#define DDRSS3_PI_217_DATA 0x09000301 +#define DDRSS3_PI_218_DATA 0x04010504 +#define DDRSS3_PI_219_DATA 0x040006C9 +#define DDRSS3_PI_220_DATA 0x0A032001 +#define DDRSS3_PI_221_DATA 0x2C31110A +#define DDRSS3_PI_222_DATA 0x00002918 +#define DDRSS3_PI_223_DATA 0x6001071C +#define DDRSS3_PI_224_DATA 0x1E202008 +#define DDRSS3_PI_225_DATA 0x2C311116 +#define DDRSS3_PI_226_DATA 0x00002918 +#define DDRSS3_PI_227_DATA 0x6001071C +#define DDRSS3_PI_228_DATA 0x1E202008 +#define DDRSS3_PI_229_DATA 0x00019C16 +#define DDRSS3_PI_230_DATA 0x00001018 +#define DDRSS3_PI_231_DATA 0x000040E6 +#define DDRSS3_PI_232_DATA 0x000288FC +#define DDRSS3_PI_233_DATA 0x000040E6 +#define DDRSS3_PI_234_DATA 0x000288FC +#define DDRSS3_PI_235_DATA 0x033B0016 +#define DDRSS3_PI_236_DATA 0x0303033B +#define DDRSS3_PI_237_DATA 0x002AF803 +#define DDRSS3_PI_238_DATA 0x0001ADAF +#define DDRSS3_PI_239_DATA 0x00000005 +#define DDRSS3_PI_240_DATA 0x0000006E +#define DDRSS3_PI_241_DATA 0x00000016 +#define DDRSS3_PI_242_DATA 0x000681C8 +#define DDRSS3_PI_243_DATA 0x0001ADAF +#define DDRSS3_PI_244_DATA 0x00000005 +#define DDRSS3_PI_245_DATA 0x000010A9 +#define DDRSS3_PI_246_DATA 0x0000033B +#define DDRSS3_PI_247_DATA 0x000681C8 +#define DDRSS3_PI_248_DATA 0x0001ADAF +#define DDRSS3_PI_249_DATA 0x00000005 +#define DDRSS3_PI_250_DATA 0x000010A9 +#define DDRSS3_PI_251_DATA 0x0100033B +#define DDRSS3_PI_252_DATA 0x00370040 +#define DDRSS3_PI_253_DATA 0x00010008 +#define DDRSS3_PI_254_DATA 0x08550040 +#define DDRSS3_PI_255_DATA 0x00010040 +#define DDRSS3_PI_256_DATA 0x08550040 +#define DDRSS3_PI_257_DATA 0x00000340 +#define DDRSS3_PI_258_DATA 0x006B006B +#define DDRSS3_PI_259_DATA 0x08040404 +#define DDRSS3_PI_260_DATA 0x00000055 +#define DDRSS3_PI_261_DATA 0x55083C5A +#define DDRSS3_PI_262_DATA 0x5A000000 +#define DDRSS3_PI_263_DATA 0x0055083C +#define DDRSS3_PI_264_DATA 0x3C5A0000 +#define DDRSS3_PI_265_DATA 0x00005508 +#define DDRSS3_PI_266_DATA 0x0C3C5A00 +#define DDRSS3_PI_267_DATA 0x080F0E0D +#define DDRSS3_PI_268_DATA 0x000B0A09 +#define DDRSS3_PI_269_DATA 0x00030201 +#define DDRSS3_PI_270_DATA 0x01000000 +#define DDRSS3_PI_271_DATA 0x04020201 +#define DDRSS3_PI_272_DATA 0x00080804 +#define DDRSS3_PI_273_DATA 0x00000000 +#define DDRSS3_PI_274_DATA 0x00000000 +#define DDRSS3_PI_275_DATA 0x00330084 +#define DDRSS3_PI_276_DATA 0x00160000 +#define DDRSS3_PI_277_DATA 0x35333FF4 +#define DDRSS3_PI_278_DATA 0x00160F27 +#define DDRSS3_PI_279_DATA 0x35333FF4 +#define DDRSS3_PI_280_DATA 0x00160F27 +#define DDRSS3_PI_281_DATA 0x00330084 +#define DDRSS3_PI_282_DATA 0x00160000 +#define DDRSS3_PI_283_DATA 0x35333FF4 +#define DDRSS3_PI_284_DATA 0x00160F27 +#define DDRSS3_PI_285_DATA 0x35333FF4 +#define DDRSS3_PI_286_DATA 0x00160F27 +#define DDRSS3_PI_287_DATA 0x00330084 +#define DDRSS3_PI_288_DATA 0x00160000 +#define DDRSS3_PI_289_DATA 0x35333FF4 +#define DDRSS3_PI_290_DATA 0x00160F27 +#define DDRSS3_PI_291_DATA 0x35333FF4 +#define DDRSS3_PI_292_DATA 0x00160F27 +#define DDRSS3_PI_293_DATA 0x00330084 +#define DDRSS3_PI_294_DATA 0x00160000 +#define DDRSS3_PI_295_DATA 0x35333FF4 +#define DDRSS3_PI_296_DATA 0x00160F27 +#define DDRSS3_PI_297_DATA 0x35333FF4 +#define DDRSS3_PI_298_DATA 0x00160F27 +#define DDRSS3_PI_299_DATA 0x00000000 + +#define DDRSS3_PHY_00_DATA 0x000004F0 +#define DDRSS3_PHY_01_DATA 0x00000000 +#define DDRSS3_PHY_02_DATA 0x00030200 +#define DDRSS3_PHY_03_DATA 0x00000000 +#define DDRSS3_PHY_04_DATA 0x00000000 +#define DDRSS3_PHY_05_DATA 0x01030000 +#define DDRSS3_PHY_06_DATA 0x00010000 +#define DDRSS3_PHY_07_DATA 0x01030004 +#define DDRSS3_PHY_08_DATA 0x01000000 +#define DDRSS3_PHY_09_DATA 0x00000000 +#define DDRSS3_PHY_10_DATA 0x00000000 +#define DDRSS3_PHY_11_DATA 0x01000001 +#define DDRSS3_PHY_12_DATA 0x00000100 +#define DDRSS3_PHY_13_DATA 0x000800C0 +#define DDRSS3_PHY_14_DATA 0x060100CC +#define DDRSS3_PHY_15_DATA 0x00030066 +#define DDRSS3_PHY_16_DATA 0x00000000 +#define DDRSS3_PHY_17_DATA 0x00000301 +#define DDRSS3_PHY_18_DATA 0x0000AAAA +#define DDRSS3_PHY_19_DATA 0x00005555 +#define DDRSS3_PHY_20_DATA 0x0000B5B5 +#define DDRSS3_PHY_21_DATA 0x00004A4A +#define DDRSS3_PHY_22_DATA 0x00005656 +#define DDRSS3_PHY_23_DATA 0x0000A9A9 +#define DDRSS3_PHY_24_DATA 0x0000A9A9 +#define DDRSS3_PHY_25_DATA 0x0000B5B5 +#define DDRSS3_PHY_26_DATA 0x00000000 +#define DDRSS3_PHY_27_DATA 0x00000000 +#define DDRSS3_PHY_28_DATA 0x2A000000 +#define DDRSS3_PHY_29_DATA 0x00000808 +#define DDRSS3_PHY_30_DATA 0x0F000000 +#define DDRSS3_PHY_31_DATA 0x00000F0F +#define DDRSS3_PHY_32_DATA 0x10400000 +#define DDRSS3_PHY_33_DATA 0x0C002006 +#define DDRSS3_PHY_34_DATA 0x00000000 +#define DDRSS3_PHY_35_DATA 0x00000000 +#define DDRSS3_PHY_36_DATA 0x55555555 +#define DDRSS3_PHY_37_DATA 0xAAAAAAAA +#define DDRSS3_PHY_38_DATA 0x55555555 +#define DDRSS3_PHY_39_DATA 0xAAAAAAAA +#define DDRSS3_PHY_40_DATA 0x00005555 +#define DDRSS3_PHY_41_DATA 0x01000100 +#define DDRSS3_PHY_42_DATA 0x00800180 +#define DDRSS3_PHY_43_DATA 0x00000001 +#define DDRSS3_PHY_44_DATA 0x00000000 +#define DDRSS3_PHY_45_DATA 0x00000000 +#define DDRSS3_PHY_46_DATA 0x00000000 +#define DDRSS3_PHY_47_DATA 0x00000000 +#define DDRSS3_PHY_48_DATA 0x00000000 +#define DDRSS3_PHY_49_DATA 0x00000000 +#define DDRSS3_PHY_50_DATA 0x00000000 +#define DDRSS3_PHY_51_DATA 0x00000000 +#define DDRSS3_PHY_52_DATA 0x00000000 +#define DDRSS3_PHY_53_DATA 0x00000000 +#define DDRSS3_PHY_54_DATA 0x00000000 +#define DDRSS3_PHY_55_DATA 0x00000000 +#define DDRSS3_PHY_56_DATA 0x00000000 +#define DDRSS3_PHY_57_DATA 0x00000000 +#define DDRSS3_PHY_58_DATA 0x00000000 +#define DDRSS3_PHY_59_DATA 0x00000000 +#define DDRSS3_PHY_60_DATA 0x00000000 +#define DDRSS3_PHY_61_DATA 0x00000000 +#define DDRSS3_PHY_62_DATA 0x00000000 +#define DDRSS3_PHY_63_DATA 0x00000000 +#define DDRSS3_PHY_64_DATA 0x00000000 +#define DDRSS3_PHY_65_DATA 0x00000000 +#define DDRSS3_PHY_66_DATA 0x00000104 +#define DDRSS3_PHY_67_DATA 0x00000120 +#define DDRSS3_PHY_68_DATA 0x00000000 +#define DDRSS3_PHY_69_DATA 0x00000000 +#define DDRSS3_PHY_70_DATA 0x00000000 +#define DDRSS3_PHY_71_DATA 0x00000000 +#define DDRSS3_PHY_72_DATA 0x00000000 +#define DDRSS3_PHY_73_DATA 0x00000000 +#define DDRSS3_PHY_74_DATA 0x00000000 +#define DDRSS3_PHY_75_DATA 0x00000001 +#define DDRSS3_PHY_76_DATA 0x07FF0000 +#define DDRSS3_PHY_77_DATA 0x0080081F +#define DDRSS3_PHY_78_DATA 0x00081020 +#define DDRSS3_PHY_79_DATA 0x04010000 +#define DDRSS3_PHY_80_DATA 0x00000000 +#define DDRSS3_PHY_81_DATA 0x00000000 +#define DDRSS3_PHY_82_DATA 0x00000000 +#define DDRSS3_PHY_83_DATA 0x00000100 +#define DDRSS3_PHY_84_DATA 0x01CC0C01 +#define DDRSS3_PHY_85_DATA 0x1003CC0C +#define DDRSS3_PHY_86_DATA 0x20000140 +#define DDRSS3_PHY_87_DATA 0x07FF0200 +#define DDRSS3_PHY_88_DATA 0x0000DD01 +#define DDRSS3_PHY_89_DATA 0x10100303 +#define DDRSS3_PHY_90_DATA 0x10101010 +#define DDRSS3_PHY_91_DATA 0x10101010 +#define DDRSS3_PHY_92_DATA 0x00021010 +#define DDRSS3_PHY_93_DATA 0x00100010 +#define DDRSS3_PHY_94_DATA 0x00100010 +#define DDRSS3_PHY_95_DATA 0x00100010 +#define DDRSS3_PHY_96_DATA 0x00100010 +#define DDRSS3_PHY_97_DATA 0x00050010 +#define DDRSS3_PHY_98_DATA 0x51517041 +#define DDRSS3_PHY_99_DATA 0x31C06001 +#define DDRSS3_PHY_100_DATA 0x07AB0340 +#define DDRSS3_PHY_101_DATA 0x00C0C001 +#define DDRSS3_PHY_102_DATA 0x0E0D0001 +#define DDRSS3_PHY_103_DATA 0x10001000 +#define DDRSS3_PHY_104_DATA 0x0C083E42 +#define DDRSS3_PHY_105_DATA 0x0F0C3701 +#define DDRSS3_PHY_106_DATA 0x01000140 +#define DDRSS3_PHY_107_DATA 0x0C000420 +#define DDRSS3_PHY_108_DATA 0x00000198 +#define DDRSS3_PHY_109_DATA 0x0A0000D0 +#define DDRSS3_PHY_110_DATA 0x00030200 +#define DDRSS3_PHY_111_DATA 0x02800000 +#define DDRSS3_PHY_112_DATA 0x80800000 +#define DDRSS3_PHY_113_DATA 0x000E2010 +#define DDRSS3_PHY_114_DATA 0x76543210 +#define DDRSS3_PHY_115_DATA 0x00000008 +#define DDRSS3_PHY_116_DATA 0x02800280 +#define DDRSS3_PHY_117_DATA 0x02800280 +#define DDRSS3_PHY_118_DATA 0x02800280 +#define DDRSS3_PHY_119_DATA 0x02800280 +#define DDRSS3_PHY_120_DATA 0x00000280 +#define DDRSS3_PHY_121_DATA 0x0000A000 +#define DDRSS3_PHY_122_DATA 0x00A000A0 +#define DDRSS3_PHY_123_DATA 0x00A000A0 +#define DDRSS3_PHY_124_DATA 0x00A000A0 +#define DDRSS3_PHY_125_DATA 0x00A000A0 +#define DDRSS3_PHY_126_DATA 0x00A000A0 +#define DDRSS3_PHY_127_DATA 0x00A000A0 +#define DDRSS3_PHY_128_DATA 0x00A000A0 +#define DDRSS3_PHY_129_DATA 0x00A000A0 +#define DDRSS3_PHY_130_DATA 0x01C200A0 +#define DDRSS3_PHY_131_DATA 0x01A00005 +#define DDRSS3_PHY_132_DATA 0x00000000 +#define DDRSS3_PHY_133_DATA 0x00000000 +#define DDRSS3_PHY_134_DATA 0x00080200 +#define DDRSS3_PHY_135_DATA 0x00000000 +#define DDRSS3_PHY_136_DATA 0x20202000 +#define DDRSS3_PHY_137_DATA 0x20202020 +#define DDRSS3_PHY_138_DATA 0xF0F02020 +#define DDRSS3_PHY_139_DATA 0x00000000 +#define DDRSS3_PHY_140_DATA 0x00000000 +#define DDRSS3_PHY_141_DATA 0x00000000 +#define DDRSS3_PHY_142_DATA 0x00000000 +#define DDRSS3_PHY_143_DATA 0x00000000 +#define DDRSS3_PHY_144_DATA 0x00000000 +#define DDRSS3_PHY_145_DATA 0x00000000 +#define DDRSS3_PHY_146_DATA 0x00000000 +#define DDRSS3_PHY_147_DATA 0x00000000 +#define DDRSS3_PHY_148_DATA 0x00000000 +#define DDRSS3_PHY_149_DATA 0x00000000 +#define DDRSS3_PHY_150_DATA 0x00000000 +#define DDRSS3_PHY_151_DATA 0x00000000 +#define DDRSS3_PHY_152_DATA 0x00000000 +#define DDRSS3_PHY_153_DATA 0x00000000 +#define DDRSS3_PHY_154_DATA 0x00000000 +#define DDRSS3_PHY_155_DATA 0x00000000 +#define DDRSS3_PHY_156_DATA 0x00000000 +#define DDRSS3_PHY_157_DATA 0x00000000 +#define DDRSS3_PHY_158_DATA 0x00000000 +#define DDRSS3_PHY_159_DATA 0x00000000 +#define DDRSS3_PHY_160_DATA 0x00000000 +#define DDRSS3_PHY_161_DATA 0x00000000 +#define DDRSS3_PHY_162_DATA 0x00000000 +#define DDRSS3_PHY_163_DATA 0x00000000 +#define DDRSS3_PHY_164_DATA 0x00000000 +#define DDRSS3_PHY_165_DATA 0x00000000 +#define DDRSS3_PHY_166_DATA 0x00000000 +#define DDRSS3_PHY_167_DATA 0x00000000 +#define DDRSS3_PHY_168_DATA 0x00000000 +#define DDRSS3_PHY_169_DATA 0x00000000 +#define DDRSS3_PHY_170_DATA 0x00000000 +#define DDRSS3_PHY_171_DATA 0x00000000 +#define DDRSS3_PHY_172_DATA 0x00000000 +#define DDRSS3_PHY_173_DATA 0x00000000 +#define DDRSS3_PHY_174_DATA 0x00000000 +#define DDRSS3_PHY_175_DATA 0x00000000 +#define DDRSS3_PHY_176_DATA 0x00000000 +#define DDRSS3_PHY_177_DATA 0x00000000 +#define DDRSS3_PHY_178_DATA 0x00000000 +#define DDRSS3_PHY_179_DATA 0x00000000 +#define DDRSS3_PHY_180_DATA 0x00000000 +#define DDRSS3_PHY_181_DATA 0x00000000 +#define DDRSS3_PHY_182_DATA 0x00000000 +#define DDRSS3_PHY_183_DATA 0x00000000 +#define DDRSS3_PHY_184_DATA 0x00000000 +#define DDRSS3_PHY_185_DATA 0x00000000 +#define DDRSS3_PHY_186_DATA 0x00000000 +#define DDRSS3_PHY_187_DATA 0x00000000 +#define DDRSS3_PHY_188_DATA 0x00000000 +#define DDRSS3_PHY_189_DATA 0x00000000 +#define DDRSS3_PHY_190_DATA 0x00000000 +#define DDRSS3_PHY_191_DATA 0x00000000 +#define DDRSS3_PHY_192_DATA 0x00000000 +#define DDRSS3_PHY_193_DATA 0x00000000 +#define DDRSS3_PHY_194_DATA 0x00000000 +#define DDRSS3_PHY_195_DATA 0x00000000 +#define DDRSS3_PHY_196_DATA 0x00000000 +#define DDRSS3_PHY_197_DATA 0x00000000 +#define DDRSS3_PHY_198_DATA 0x00000000 +#define DDRSS3_PHY_199_DATA 0x00000000 +#define DDRSS3_PHY_200_DATA 0x00000000 +#define DDRSS3_PHY_201_DATA 0x00000000 +#define DDRSS3_PHY_202_DATA 0x00000000 +#define DDRSS3_PHY_203_DATA 0x00000000 +#define DDRSS3_PHY_204_DATA 0x00000000 +#define DDRSS3_PHY_205_DATA 0x00000000 +#define DDRSS3_PHY_206_DATA 0x00000000 +#define DDRSS3_PHY_207_DATA 0x00000000 +#define DDRSS3_PHY_208_DATA 0x00000000 +#define DDRSS3_PHY_209_DATA 0x00000000 +#define DDRSS3_PHY_210_DATA 0x00000000 +#define DDRSS3_PHY_211_DATA 0x00000000 +#define DDRSS3_PHY_212_DATA 0x00000000 +#define DDRSS3_PHY_213_DATA 0x00000000 +#define DDRSS3_PHY_214_DATA 0x00000000 +#define DDRSS3_PHY_215_DATA 0x00000000 +#define DDRSS3_PHY_216_DATA 0x00000000 +#define DDRSS3_PHY_217_DATA 0x00000000 +#define DDRSS3_PHY_218_DATA 0x00000000 +#define DDRSS3_PHY_219_DATA 0x00000000 +#define DDRSS3_PHY_220_DATA 0x00000000 +#define DDRSS3_PHY_221_DATA 0x00000000 +#define DDRSS3_PHY_222_DATA 0x00000000 +#define DDRSS3_PHY_223_DATA 0x00000000 +#define DDRSS3_PHY_224_DATA 0x00000000 +#define DDRSS3_PHY_225_DATA 0x00000000 +#define DDRSS3_PHY_226_DATA 0x00000000 +#define DDRSS3_PHY_227_DATA 0x00000000 +#define DDRSS3_PHY_228_DATA 0x00000000 +#define DDRSS3_PHY_229_DATA 0x00000000 +#define DDRSS3_PHY_230_DATA 0x00000000 +#define DDRSS3_PHY_231_DATA 0x00000000 +#define DDRSS3_PHY_232_DATA 0x00000000 +#define DDRSS3_PHY_233_DATA 0x00000000 +#define DDRSS3_PHY_234_DATA 0x00000000 +#define DDRSS3_PHY_235_DATA 0x00000000 +#define DDRSS3_PHY_236_DATA 0x00000000 +#define DDRSS3_PHY_237_DATA 0x00000000 +#define DDRSS3_PHY_238_DATA 0x00000000 +#define DDRSS3_PHY_239_DATA 0x00000000 +#define DDRSS3_PHY_240_DATA 0x00000000 +#define DDRSS3_PHY_241_DATA 0x00000000 +#define DDRSS3_PHY_242_DATA 0x00000000 +#define DDRSS3_PHY_243_DATA 0x00000000 +#define DDRSS3_PHY_244_DATA 0x00000000 +#define DDRSS3_PHY_245_DATA 0x00000000 +#define DDRSS3_PHY_246_DATA 0x00000000 +#define DDRSS3_PHY_247_DATA 0x00000000 +#define DDRSS3_PHY_248_DATA 0x00000000 +#define DDRSS3_PHY_249_DATA 0x00000000 +#define DDRSS3_PHY_250_DATA 0x00000000 +#define DDRSS3_PHY_251_DATA 0x00000000 +#define DDRSS3_PHY_252_DATA 0x00000000 +#define DDRSS3_PHY_253_DATA 0x00000000 +#define DDRSS3_PHY_254_DATA 0x00000000 +#define DDRSS3_PHY_255_DATA 0x00000000 +#define DDRSS3_PHY_256_DATA 0x000004F0 +#define DDRSS3_PHY_257_DATA 0x00000000 +#define DDRSS3_PHY_258_DATA 0x00030200 +#define DDRSS3_PHY_259_DATA 0x00000000 +#define DDRSS3_PHY_260_DATA 0x00000000 +#define DDRSS3_PHY_261_DATA 0x01030000 +#define DDRSS3_PHY_262_DATA 0x00010000 +#define DDRSS3_PHY_263_DATA 0x01030004 +#define DDRSS3_PHY_264_DATA 0x01000000 +#define DDRSS3_PHY_265_DATA 0x00000000 +#define DDRSS3_PHY_266_DATA 0x00000000 +#define DDRSS3_PHY_267_DATA 0x01000001 +#define DDRSS3_PHY_268_DATA 0x00000100 +#define DDRSS3_PHY_269_DATA 0x000800C0 +#define DDRSS3_PHY_270_DATA 0x060100CC +#define DDRSS3_PHY_271_DATA 0x00030066 +#define DDRSS3_PHY_272_DATA 0x00000000 +#define DDRSS3_PHY_273_DATA 0x00000301 +#define DDRSS3_PHY_274_DATA 0x0000AAAA +#define DDRSS3_PHY_275_DATA 0x00005555 +#define DDRSS3_PHY_276_DATA 0x0000B5B5 +#define DDRSS3_PHY_277_DATA 0x00004A4A +#define DDRSS3_PHY_278_DATA 0x00005656 +#define DDRSS3_PHY_279_DATA 0x0000A9A9 +#define DDRSS3_PHY_280_DATA 0x0000A9A9 +#define DDRSS3_PHY_281_DATA 0x0000B5B5 +#define DDRSS3_PHY_282_DATA 0x00000000 +#define DDRSS3_PHY_283_DATA 0x00000000 +#define DDRSS3_PHY_284_DATA 0x2A000000 +#define DDRSS3_PHY_285_DATA 0x00000808 +#define DDRSS3_PHY_286_DATA 0x0F000000 +#define DDRSS3_PHY_287_DATA 0x00000F0F +#define DDRSS3_PHY_288_DATA 0x10400000 +#define DDRSS3_PHY_289_DATA 0x0C002006 +#define DDRSS3_PHY_290_DATA 0x00000000 +#define DDRSS3_PHY_291_DATA 0x00000000 +#define DDRSS3_PHY_292_DATA 0x55555555 +#define DDRSS3_PHY_293_DATA 0xAAAAAAAA +#define DDRSS3_PHY_294_DATA 0x55555555 +#define DDRSS3_PHY_295_DATA 0xAAAAAAAA +#define DDRSS3_PHY_296_DATA 0x00005555 +#define DDRSS3_PHY_297_DATA 0x01000100 +#define DDRSS3_PHY_298_DATA 0x00800180 +#define DDRSS3_PHY_299_DATA 0x00000000 +#define DDRSS3_PHY_300_DATA 0x00000000 +#define DDRSS3_PHY_301_DATA 0x00000000 +#define DDRSS3_PHY_302_DATA 0x00000000 +#define DDRSS3_PHY_303_DATA 0x00000000 +#define DDRSS3_PHY_304_DATA 0x00000000 +#define DDRSS3_PHY_305_DATA 0x00000000 +#define DDRSS3_PHY_306_DATA 0x00000000 +#define DDRSS3_PHY_307_DATA 0x00000000 +#define DDRSS3_PHY_308_DATA 0x00000000 +#define DDRSS3_PHY_309_DATA 0x00000000 +#define DDRSS3_PHY_310_DATA 0x00000000 +#define DDRSS3_PHY_311_DATA 0x00000000 +#define DDRSS3_PHY_312_DATA 0x00000000 +#define DDRSS3_PHY_313_DATA 0x00000000 +#define DDRSS3_PHY_314_DATA 0x00000000 +#define DDRSS3_PHY_315_DATA 0x00000000 +#define DDRSS3_PHY_316_DATA 0x00000000 +#define DDRSS3_PHY_317_DATA 0x00000000 +#define DDRSS3_PHY_318_DATA 0x00000000 +#define DDRSS3_PHY_319_DATA 0x00000000 +#define DDRSS3_PHY_320_DATA 0x00000000 +#define DDRSS3_PHY_321_DATA 0x00000000 +#define DDRSS3_PHY_322_DATA 0x00000104 +#define DDRSS3_PHY_323_DATA 0x00000120 +#define DDRSS3_PHY_324_DATA 0x00000000 +#define DDRSS3_PHY_325_DATA 0x00000000 +#define DDRSS3_PHY_326_DATA 0x00000000 +#define DDRSS3_PHY_327_DATA 0x00000000 +#define DDRSS3_PHY_328_DATA 0x00000000 +#define DDRSS3_PHY_329_DATA 0x00000000 +#define DDRSS3_PHY_330_DATA 0x00000000 +#define DDRSS3_PHY_331_DATA 0x00000001 +#define DDRSS3_PHY_332_DATA 0x07FF0000 +#define DDRSS3_PHY_333_DATA 0x0080081F +#define DDRSS3_PHY_334_DATA 0x00081020 +#define DDRSS3_PHY_335_DATA 0x04010000 +#define DDRSS3_PHY_336_DATA 0x00000000 +#define DDRSS3_PHY_337_DATA 0x00000000 +#define DDRSS3_PHY_338_DATA 0x00000000 +#define DDRSS3_PHY_339_DATA 0x00000100 +#define DDRSS3_PHY_340_DATA 0x01CC0C01 +#define DDRSS3_PHY_341_DATA 0x1003CC0C +#define DDRSS3_PHY_342_DATA 0x20000140 +#define DDRSS3_PHY_343_DATA 0x07FF0200 +#define DDRSS3_PHY_344_DATA 0x0000DD01 +#define DDRSS3_PHY_345_DATA 0x10100303 +#define DDRSS3_PHY_346_DATA 0x10101010 +#define DDRSS3_PHY_347_DATA 0x10101010 +#define DDRSS3_PHY_348_DATA 0x00021010 +#define DDRSS3_PHY_349_DATA 0x00100010 +#define DDRSS3_PHY_350_DATA 0x00100010 +#define DDRSS3_PHY_351_DATA 0x00100010 +#define DDRSS3_PHY_352_DATA 0x00100010 +#define DDRSS3_PHY_353_DATA 0x00050010 +#define DDRSS3_PHY_354_DATA 0x51517041 +#define DDRSS3_PHY_355_DATA 0x31C06001 +#define DDRSS3_PHY_356_DATA 0x07AB0340 +#define DDRSS3_PHY_357_DATA 0x00C0C001 +#define DDRSS3_PHY_358_DATA 0x0E0D0001 +#define DDRSS3_PHY_359_DATA 0x10001000 +#define DDRSS3_PHY_360_DATA 0x0C083E42 +#define DDRSS3_PHY_361_DATA 0x0F0C3701 +#define DDRSS3_PHY_362_DATA 0x01000140 +#define DDRSS3_PHY_363_DATA 0x0C000420 +#define DDRSS3_PHY_364_DATA 0x00000198 +#define DDRSS3_PHY_365_DATA 0x0A0000D0 +#define DDRSS3_PHY_366_DATA 0x00030200 +#define DDRSS3_PHY_367_DATA 0x02800000 +#define DDRSS3_PHY_368_DATA 0x80800000 +#define DDRSS3_PHY_369_DATA 0x000E2010 +#define DDRSS3_PHY_370_DATA 0x76543210 +#define DDRSS3_PHY_371_DATA 0x00000008 +#define DDRSS3_PHY_372_DATA 0x02800280 +#define DDRSS3_PHY_373_DATA 0x02800280 +#define DDRSS3_PHY_374_DATA 0x02800280 +#define DDRSS3_PHY_375_DATA 0x02800280 +#define DDRSS3_PHY_376_DATA 0x00000280 +#define DDRSS3_PHY_377_DATA 0x0000A000 +#define DDRSS3_PHY_378_DATA 0x00A000A0 +#define DDRSS3_PHY_379_DATA 0x00A000A0 +#define DDRSS3_PHY_380_DATA 0x00A000A0 +#define DDRSS3_PHY_381_DATA 0x00A000A0 +#define DDRSS3_PHY_382_DATA 0x00A000A0 +#define DDRSS3_PHY_383_DATA 0x00A000A0 +#define DDRSS3_PHY_384_DATA 0x00A000A0 +#define DDRSS3_PHY_385_DATA 0x00A000A0 +#define DDRSS3_PHY_386_DATA 0x01C200A0 +#define DDRSS3_PHY_387_DATA 0x01A00005 +#define DDRSS3_PHY_388_DATA 0x00000000 +#define DDRSS3_PHY_389_DATA 0x00000000 +#define DDRSS3_PHY_390_DATA 0x00080200 +#define DDRSS3_PHY_391_DATA 0x00000000 +#define DDRSS3_PHY_392_DATA 0x20202000 +#define DDRSS3_PHY_393_DATA 0x20202020 +#define DDRSS3_PHY_394_DATA 0xF0F02020 +#define DDRSS3_PHY_395_DATA 0x00000000 +#define DDRSS3_PHY_396_DATA 0x00000000 +#define DDRSS3_PHY_397_DATA 0x00000000 +#define DDRSS3_PHY_398_DATA 0x00000000 +#define DDRSS3_PHY_399_DATA 0x00000000 +#define DDRSS3_PHY_400_DATA 0x00000000 +#define DDRSS3_PHY_401_DATA 0x00000000 +#define DDRSS3_PHY_402_DATA 0x00000000 +#define DDRSS3_PHY_403_DATA 0x00000000 +#define DDRSS3_PHY_404_DATA 0x00000000 +#define DDRSS3_PHY_405_DATA 0x00000000 +#define DDRSS3_PHY_406_DATA 0x00000000 +#define DDRSS3_PHY_407_DATA 0x00000000 +#define DDRSS3_PHY_408_DATA 0x00000000 +#define DDRSS3_PHY_409_DATA 0x00000000 +#define DDRSS3_PHY_410_DATA 0x00000000 +#define DDRSS3_PHY_411_DATA 0x00000000 +#define DDRSS3_PHY_412_DATA 0x00000000 +#define DDRSS3_PHY_413_DATA 0x00000000 +#define DDRSS3_PHY_414_DATA 0x00000000 +#define DDRSS3_PHY_415_DATA 0x00000000 +#define DDRSS3_PHY_416_DATA 0x00000000 +#define DDRSS3_PHY_417_DATA 0x00000000 +#define DDRSS3_PHY_418_DATA 0x00000000 +#define DDRSS3_PHY_419_DATA 0x00000000 +#define DDRSS3_PHY_420_DATA 0x00000000 +#define DDRSS3_PHY_421_DATA 0x00000000 +#define DDRSS3_PHY_422_DATA 0x00000000 +#define DDRSS3_PHY_423_DATA 0x00000000 +#define DDRSS3_PHY_424_DATA 0x00000000 +#define DDRSS3_PHY_425_DATA 0x00000000 +#define DDRSS3_PHY_426_DATA 0x00000000 +#define DDRSS3_PHY_427_DATA 0x00000000 +#define DDRSS3_PHY_428_DATA 0x00000000 +#define DDRSS3_PHY_429_DATA 0x00000000 +#define DDRSS3_PHY_430_DATA 0x00000000 +#define DDRSS3_PHY_431_DATA 0x00000000 +#define DDRSS3_PHY_432_DATA 0x00000000 +#define DDRSS3_PHY_433_DATA 0x00000000 +#define DDRSS3_PHY_434_DATA 0x00000000 +#define DDRSS3_PHY_435_DATA 0x00000000 +#define DDRSS3_PHY_436_DATA 0x00000000 +#define DDRSS3_PHY_437_DATA 0x00000000 +#define DDRSS3_PHY_438_DATA 0x00000000 +#define DDRSS3_PHY_439_DATA 0x00000000 +#define DDRSS3_PHY_440_DATA 0x00000000 +#define DDRSS3_PHY_441_DATA 0x00000000 +#define DDRSS3_PHY_442_DATA 0x00000000 +#define DDRSS3_PHY_443_DATA 0x00000000 +#define DDRSS3_PHY_444_DATA 0x00000000 +#define DDRSS3_PHY_445_DATA 0x00000000 +#define DDRSS3_PHY_446_DATA 0x00000000 +#define DDRSS3_PHY_447_DATA 0x00000000 +#define DDRSS3_PHY_448_DATA 0x00000000 +#define DDRSS3_PHY_449_DATA 0x00000000 +#define DDRSS3_PHY_450_DATA 0x00000000 +#define DDRSS3_PHY_451_DATA 0x00000000 +#define DDRSS3_PHY_452_DATA 0x00000000 +#define DDRSS3_PHY_453_DATA 0x00000000 +#define DDRSS3_PHY_454_DATA 0x00000000 +#define DDRSS3_PHY_455_DATA 0x00000000 +#define DDRSS3_PHY_456_DATA 0x00000000 +#define DDRSS3_PHY_457_DATA 0x00000000 +#define DDRSS3_PHY_458_DATA 0x00000000 +#define DDRSS3_PHY_459_DATA 0x00000000 +#define DDRSS3_PHY_460_DATA 0x00000000 +#define DDRSS3_PHY_461_DATA 0x00000000 +#define DDRSS3_PHY_462_DATA 0x00000000 +#define DDRSS3_PHY_463_DATA 0x00000000 +#define DDRSS3_PHY_464_DATA 0x00000000 +#define DDRSS3_PHY_465_DATA 0x00000000 +#define DDRSS3_PHY_466_DATA 0x00000000 +#define DDRSS3_PHY_467_DATA 0x00000000 +#define DDRSS3_PHY_468_DATA 0x00000000 +#define DDRSS3_PHY_469_DATA 0x00000000 +#define DDRSS3_PHY_470_DATA 0x00000000 +#define DDRSS3_PHY_471_DATA 0x00000000 +#define DDRSS3_PHY_472_DATA 0x00000000 +#define DDRSS3_PHY_473_DATA 0x00000000 +#define DDRSS3_PHY_474_DATA 0x00000000 +#define DDRSS3_PHY_475_DATA 0x00000000 +#define DDRSS3_PHY_476_DATA 0x00000000 +#define DDRSS3_PHY_477_DATA 0x00000000 +#define DDRSS3_PHY_478_DATA 0x00000000 +#define DDRSS3_PHY_479_DATA 0x00000000 +#define DDRSS3_PHY_480_DATA 0x00000000 +#define DDRSS3_PHY_481_DATA 0x00000000 +#define DDRSS3_PHY_482_DATA 0x00000000 +#define DDRSS3_PHY_483_DATA 0x00000000 +#define DDRSS3_PHY_484_DATA 0x00000000 +#define DDRSS3_PHY_485_DATA 0x00000000 +#define DDRSS3_PHY_486_DATA 0x00000000 +#define DDRSS3_PHY_487_DATA 0x00000000 +#define DDRSS3_PHY_488_DATA 0x00000000 +#define DDRSS3_PHY_489_DATA 0x00000000 +#define DDRSS3_PHY_490_DATA 0x00000000 +#define DDRSS3_PHY_491_DATA 0x00000000 +#define DDRSS3_PHY_492_DATA 0x00000000 +#define DDRSS3_PHY_493_DATA 0x00000000 +#define DDRSS3_PHY_494_DATA 0x00000000 +#define DDRSS3_PHY_495_DATA 0x00000000 +#define DDRSS3_PHY_496_DATA 0x00000000 +#define DDRSS3_PHY_497_DATA 0x00000000 +#define DDRSS3_PHY_498_DATA 0x00000000 +#define DDRSS3_PHY_499_DATA 0x00000000 +#define DDRSS3_PHY_500_DATA 0x00000000 +#define DDRSS3_PHY_501_DATA 0x00000000 +#define DDRSS3_PHY_502_DATA 0x00000000 +#define DDRSS3_PHY_503_DATA 0x00000000 +#define DDRSS3_PHY_504_DATA 0x00000000 +#define DDRSS3_PHY_505_DATA 0x00000000 +#define DDRSS3_PHY_506_DATA 0x00000000 +#define DDRSS3_PHY_507_DATA 0x00000000 +#define DDRSS3_PHY_508_DATA 0x00000000 +#define DDRSS3_PHY_509_DATA 0x00000000 +#define DDRSS3_PHY_510_DATA 0x00000000 +#define DDRSS3_PHY_511_DATA 0x00000000 +#define DDRSS3_PHY_512_DATA 0x000004F0 +#define DDRSS3_PHY_513_DATA 0x00000000 +#define DDRSS3_PHY_514_DATA 0x00030200 +#define DDRSS3_PHY_515_DATA 0x00000000 +#define DDRSS3_PHY_516_DATA 0x00000000 +#define DDRSS3_PHY_517_DATA 0x01030000 +#define DDRSS3_PHY_518_DATA 0x00010000 +#define DDRSS3_PHY_519_DATA 0x01030004 +#define DDRSS3_PHY_520_DATA 0x01000000 +#define DDRSS3_PHY_521_DATA 0x00000000 +#define DDRSS3_PHY_522_DATA 0x00000000 +#define DDRSS3_PHY_523_DATA 0x01000001 +#define DDRSS3_PHY_524_DATA 0x00000100 +#define DDRSS3_PHY_525_DATA 0x000800C0 +#define DDRSS3_PHY_526_DATA 0x060100CC +#define DDRSS3_PHY_527_DATA 0x00030066 +#define DDRSS3_PHY_528_DATA 0x00000000 +#define DDRSS3_PHY_529_DATA 0x00000301 +#define DDRSS3_PHY_530_DATA 0x0000AAAA +#define DDRSS3_PHY_531_DATA 0x00005555 +#define DDRSS3_PHY_532_DATA 0x0000B5B5 +#define DDRSS3_PHY_533_DATA 0x00004A4A +#define DDRSS3_PHY_534_DATA 0x00005656 +#define DDRSS3_PHY_535_DATA 0x0000A9A9 +#define DDRSS3_PHY_536_DATA 0x0000A9A9 +#define DDRSS3_PHY_537_DATA 0x0000B5B5 +#define DDRSS3_PHY_538_DATA 0x00000000 +#define DDRSS3_PHY_539_DATA 0x00000000 +#define DDRSS3_PHY_540_DATA 0x2A000000 +#define DDRSS3_PHY_541_DATA 0x00000808 +#define DDRSS3_PHY_542_DATA 0x0F000000 +#define DDRSS3_PHY_543_DATA 0x00000F0F +#define DDRSS3_PHY_544_DATA 0x10400000 +#define DDRSS3_PHY_545_DATA 0x0C002006 +#define DDRSS3_PHY_546_DATA 0x00000000 +#define DDRSS3_PHY_547_DATA 0x00000000 +#define DDRSS3_PHY_548_DATA 0x55555555 +#define DDRSS3_PHY_549_DATA 0xAAAAAAAA +#define DDRSS3_PHY_550_DATA 0x55555555 +#define DDRSS3_PHY_551_DATA 0xAAAAAAAA +#define DDRSS3_PHY_552_DATA 0x00005555 +#define DDRSS3_PHY_553_DATA 0x01000100 +#define DDRSS3_PHY_554_DATA 0x00800180 +#define DDRSS3_PHY_555_DATA 0x00000001 +#define DDRSS3_PHY_556_DATA 0x00000000 +#define DDRSS3_PHY_557_DATA 0x00000000 +#define DDRSS3_PHY_558_DATA 0x00000000 +#define DDRSS3_PHY_559_DATA 0x00000000 +#define DDRSS3_PHY_560_DATA 0x00000000 +#define DDRSS3_PHY_561_DATA 0x00000000 +#define DDRSS3_PHY_562_DATA 0x00000000 +#define DDRSS3_PHY_563_DATA 0x00000000 +#define DDRSS3_PHY_564_DATA 0x00000000 +#define DDRSS3_PHY_565_DATA 0x00000000 +#define DDRSS3_PHY_566_DATA 0x00000000 +#define DDRSS3_PHY_567_DATA 0x00000000 +#define DDRSS3_PHY_568_DATA 0x00000000 +#define DDRSS3_PHY_569_DATA 0x00000000 +#define DDRSS3_PHY_570_DATA 0x00000000 +#define DDRSS3_PHY_571_DATA 0x00000000 +#define DDRSS3_PHY_572_DATA 0x00000000 +#define DDRSS3_PHY_573_DATA 0x00000000 +#define DDRSS3_PHY_574_DATA 0x00000000 +#define DDRSS3_PHY_575_DATA 0x00000000 +#define DDRSS3_PHY_576_DATA 0x00000000 +#define DDRSS3_PHY_577_DATA 0x00000000 +#define DDRSS3_PHY_578_DATA 0x00000104 +#define DDRSS3_PHY_579_DATA 0x00000120 +#define DDRSS3_PHY_580_DATA 0x00000000 +#define DDRSS3_PHY_581_DATA 0x00000000 +#define DDRSS3_PHY_582_DATA 0x00000000 +#define DDRSS3_PHY_583_DATA 0x00000000 +#define DDRSS3_PHY_584_DATA 0x00000000 +#define DDRSS3_PHY_585_DATA 0x00000000 +#define DDRSS3_PHY_586_DATA 0x00000000 +#define DDRSS3_PHY_587_DATA 0x00000001 +#define DDRSS3_PHY_588_DATA 0x07FF0000 +#define DDRSS3_PHY_589_DATA 0x0080081F +#define DDRSS3_PHY_590_DATA 0x00081020 +#define DDRSS3_PHY_591_DATA 0x04010000 +#define DDRSS3_PHY_592_DATA 0x00000000 +#define DDRSS3_PHY_593_DATA 0x00000000 +#define DDRSS3_PHY_594_DATA 0x00000000 +#define DDRSS3_PHY_595_DATA 0x00000100 +#define DDRSS3_PHY_596_DATA 0x01CC0C01 +#define DDRSS3_PHY_597_DATA 0x1003CC0C +#define DDRSS3_PHY_598_DATA 0x20000140 +#define DDRSS3_PHY_599_DATA 0x07FF0200 +#define DDRSS3_PHY_600_DATA 0x0000DD01 +#define DDRSS3_PHY_601_DATA 0x10100303 +#define DDRSS3_PHY_602_DATA 0x10101010 +#define DDRSS3_PHY_603_DATA 0x10101010 +#define DDRSS3_PHY_604_DATA 0x00021010 +#define DDRSS3_PHY_605_DATA 0x00100010 +#define DDRSS3_PHY_606_DATA 0x00100010 +#define DDRSS3_PHY_607_DATA 0x00100010 +#define DDRSS3_PHY_608_DATA 0x00100010 +#define DDRSS3_PHY_609_DATA 0x00050010 +#define DDRSS3_PHY_610_DATA 0x51517041 +#define DDRSS3_PHY_611_DATA 0x31C06001 +#define DDRSS3_PHY_612_DATA 0x07AB0340 +#define DDRSS3_PHY_613_DATA 0x00C0C001 +#define DDRSS3_PHY_614_DATA 0x0E0D0001 +#define DDRSS3_PHY_615_DATA 0x10001000 +#define DDRSS3_PHY_616_DATA 0x0C083E42 +#define DDRSS3_PHY_617_DATA 0x0F0C3701 +#define DDRSS3_PHY_618_DATA 0x01000140 +#define DDRSS3_PHY_619_DATA 0x0C000420 +#define DDRSS3_PHY_620_DATA 0x00000198 +#define DDRSS3_PHY_621_DATA 0x0A0000D0 +#define DDRSS3_PHY_622_DATA 0x00030200 +#define DDRSS3_PHY_623_DATA 0x02800000 +#define DDRSS3_PHY_624_DATA 0x80800000 +#define DDRSS3_PHY_625_DATA 0x000E2010 +#define DDRSS3_PHY_626_DATA 0x76543210 +#define DDRSS3_PHY_627_DATA 0x00000008 +#define DDRSS3_PHY_628_DATA 0x02800280 +#define DDRSS3_PHY_629_DATA 0x02800280 +#define DDRSS3_PHY_630_DATA 0x02800280 +#define DDRSS3_PHY_631_DATA 0x02800280 +#define DDRSS3_PHY_632_DATA 0x00000280 +#define DDRSS3_PHY_633_DATA 0x0000A000 +#define DDRSS3_PHY_634_DATA 0x00A000A0 +#define DDRSS3_PHY_635_DATA 0x00A000A0 +#define DDRSS3_PHY_636_DATA 0x00A000A0 +#define DDRSS3_PHY_637_DATA 0x00A000A0 +#define DDRSS3_PHY_638_DATA 0x00A000A0 +#define DDRSS3_PHY_639_DATA 0x00A000A0 +#define DDRSS3_PHY_640_DATA 0x00A000A0 +#define DDRSS3_PHY_641_DATA 0x00A000A0 +#define DDRSS3_PHY_642_DATA 0x01C200A0 +#define DDRSS3_PHY_643_DATA 0x01A00005 +#define DDRSS3_PHY_644_DATA 0x00000000 +#define DDRSS3_PHY_645_DATA 0x00000000 +#define DDRSS3_PHY_646_DATA 0x00080200 +#define DDRSS3_PHY_647_DATA 0x00000000 +#define DDRSS3_PHY_648_DATA 0x20202000 +#define DDRSS3_PHY_649_DATA 0x20202020 +#define DDRSS3_PHY_650_DATA 0xF0F02020 +#define DDRSS3_PHY_651_DATA 0x00000000 +#define DDRSS3_PHY_652_DATA 0x00000000 +#define DDRSS3_PHY_653_DATA 0x00000000 +#define DDRSS3_PHY_654_DATA 0x00000000 +#define DDRSS3_PHY_655_DATA 0x00000000 +#define DDRSS3_PHY_656_DATA 0x00000000 +#define DDRSS3_PHY_657_DATA 0x00000000 +#define DDRSS3_PHY_658_DATA 0x00000000 +#define DDRSS3_PHY_659_DATA 0x00000000 +#define DDRSS3_PHY_660_DATA 0x00000000 +#define DDRSS3_PHY_661_DATA 0x00000000 +#define DDRSS3_PHY_662_DATA 0x00000000 +#define DDRSS3_PHY_663_DATA 0x00000000 +#define DDRSS3_PHY_664_DATA 0x00000000 +#define DDRSS3_PHY_665_DATA 0x00000000 +#define DDRSS3_PHY_666_DATA 0x00000000 +#define DDRSS3_PHY_667_DATA 0x00000000 +#define DDRSS3_PHY_668_DATA 0x00000000 +#define DDRSS3_PHY_669_DATA 0x00000000 +#define DDRSS3_PHY_670_DATA 0x00000000 +#define DDRSS3_PHY_671_DATA 0x00000000 +#define DDRSS3_PHY_672_DATA 0x00000000 +#define DDRSS3_PHY_673_DATA 0x00000000 +#define DDRSS3_PHY_674_DATA 0x00000000 +#define DDRSS3_PHY_675_DATA 0x00000000 +#define DDRSS3_PHY_676_DATA 0x00000000 +#define DDRSS3_PHY_677_DATA 0x00000000 +#define DDRSS3_PHY_678_DATA 0x00000000 +#define DDRSS3_PHY_679_DATA 0x00000000 +#define DDRSS3_PHY_680_DATA 0x00000000 +#define DDRSS3_PHY_681_DATA 0x00000000 +#define DDRSS3_PHY_682_DATA 0x00000000 +#define DDRSS3_PHY_683_DATA 0x00000000 +#define DDRSS3_PHY_684_DATA 0x00000000 +#define DDRSS3_PHY_685_DATA 0x00000000 +#define DDRSS3_PHY_686_DATA 0x00000000 +#define DDRSS3_PHY_687_DATA 0x00000000 +#define DDRSS3_PHY_688_DATA 0x00000000 +#define DDRSS3_PHY_689_DATA 0x00000000 +#define DDRSS3_PHY_690_DATA 0x00000000 +#define DDRSS3_PHY_691_DATA 0x00000000 +#define DDRSS3_PHY_692_DATA 0x00000000 +#define DDRSS3_PHY_693_DATA 0x00000000 +#define DDRSS3_PHY_694_DATA 0x00000000 +#define DDRSS3_PHY_695_DATA 0x00000000 +#define DDRSS3_PHY_696_DATA 0x00000000 +#define DDRSS3_PHY_697_DATA 0x00000000 +#define DDRSS3_PHY_698_DATA 0x00000000 +#define DDRSS3_PHY_699_DATA 0x00000000 +#define DDRSS3_PHY_700_DATA 0x00000000 +#define DDRSS3_PHY_701_DATA 0x00000000 +#define DDRSS3_PHY_702_DATA 0x00000000 +#define DDRSS3_PHY_703_DATA 0x00000000 +#define DDRSS3_PHY_704_DATA 0x00000000 +#define DDRSS3_PHY_705_DATA 0x00000000 +#define DDRSS3_PHY_706_DATA 0x00000000 +#define DDRSS3_PHY_707_DATA 0x00000000 +#define DDRSS3_PHY_708_DATA 0x00000000 +#define DDRSS3_PHY_709_DATA 0x00000000 +#define DDRSS3_PHY_710_DATA 0x00000000 +#define DDRSS3_PHY_711_DATA 0x00000000 +#define DDRSS3_PHY_712_DATA 0x00000000 +#define DDRSS3_PHY_713_DATA 0x00000000 +#define DDRSS3_PHY_714_DATA 0x00000000 +#define DDRSS3_PHY_715_DATA 0x00000000 +#define DDRSS3_PHY_716_DATA 0x00000000 +#define DDRSS3_PHY_717_DATA 0x00000000 +#define DDRSS3_PHY_718_DATA 0x00000000 +#define DDRSS3_PHY_719_DATA 0x00000000 +#define DDRSS3_PHY_720_DATA 0x00000000 +#define DDRSS3_PHY_721_DATA 0x00000000 +#define DDRSS3_PHY_722_DATA 0x00000000 +#define DDRSS3_PHY_723_DATA 0x00000000 +#define DDRSS3_PHY_724_DATA 0x00000000 +#define DDRSS3_PHY_725_DATA 0x00000000 +#define DDRSS3_PHY_726_DATA 0x00000000 +#define DDRSS3_PHY_727_DATA 0x00000000 +#define DDRSS3_PHY_728_DATA 0x00000000 +#define DDRSS3_PHY_729_DATA 0x00000000 +#define DDRSS3_PHY_730_DATA 0x00000000 +#define DDRSS3_PHY_731_DATA 0x00000000 +#define DDRSS3_PHY_732_DATA 0x00000000 +#define DDRSS3_PHY_733_DATA 0x00000000 +#define DDRSS3_PHY_734_DATA 0x00000000 +#define DDRSS3_PHY_735_DATA 0x00000000 +#define DDRSS3_PHY_736_DATA 0x00000000 +#define DDRSS3_PHY_737_DATA 0x00000000 +#define DDRSS3_PHY_738_DATA 0x00000000 +#define DDRSS3_PHY_739_DATA 0x00000000 +#define DDRSS3_PHY_740_DATA 0x00000000 +#define DDRSS3_PHY_741_DATA 0x00000000 +#define DDRSS3_PHY_742_DATA 0x00000000 +#define DDRSS3_PHY_743_DATA 0x00000000 +#define DDRSS3_PHY_744_DATA 0x00000000 +#define DDRSS3_PHY_745_DATA 0x00000000 +#define DDRSS3_PHY_746_DATA 0x00000000 +#define DDRSS3_PHY_747_DATA 0x00000000 +#define DDRSS3_PHY_748_DATA 0x00000000 +#define DDRSS3_PHY_749_DATA 0x00000000 +#define DDRSS3_PHY_750_DATA 0x00000000 +#define DDRSS3_PHY_751_DATA 0x00000000 +#define DDRSS3_PHY_752_DATA 0x00000000 +#define DDRSS3_PHY_753_DATA 0x00000000 +#define DDRSS3_PHY_754_DATA 0x00000000 +#define DDRSS3_PHY_755_DATA 0x00000000 +#define DDRSS3_PHY_756_DATA 0x00000000 +#define DDRSS3_PHY_757_DATA 0x00000000 +#define DDRSS3_PHY_758_DATA 0x00000000 +#define DDRSS3_PHY_759_DATA 0x00000000 +#define DDRSS3_PHY_760_DATA 0x00000000 +#define DDRSS3_PHY_761_DATA 0x00000000 +#define DDRSS3_PHY_762_DATA 0x00000000 +#define DDRSS3_PHY_763_DATA 0x00000000 +#define DDRSS3_PHY_764_DATA 0x00000000 +#define DDRSS3_PHY_765_DATA 0x00000000 +#define DDRSS3_PHY_766_DATA 0x00000000 +#define DDRSS3_PHY_767_DATA 0x00000000 +#define DDRSS3_PHY_768_DATA 0x000004F0 +#define DDRSS3_PHY_769_DATA 0x00000000 +#define DDRSS3_PHY_770_DATA 0x00030200 +#define DDRSS3_PHY_771_DATA 0x00000000 +#define DDRSS3_PHY_772_DATA 0x00000000 +#define DDRSS3_PHY_773_DATA 0x01030000 +#define DDRSS3_PHY_774_DATA 0x00010000 +#define DDRSS3_PHY_775_DATA 0x01030004 +#define DDRSS3_PHY_776_DATA 0x01000000 +#define DDRSS3_PHY_777_DATA 0x00000000 +#define DDRSS3_PHY_778_DATA 0x00000000 +#define DDRSS3_PHY_779_DATA 0x01000001 +#define DDRSS3_PHY_780_DATA 0x00000100 +#define DDRSS3_PHY_781_DATA 0x000800C0 +#define DDRSS3_PHY_782_DATA 0x060100CC +#define DDRSS3_PHY_783_DATA 0x00030066 +#define DDRSS3_PHY_784_DATA 0x00000000 +#define DDRSS3_PHY_785_DATA 0x00000301 +#define DDRSS3_PHY_786_DATA 0x0000AAAA +#define DDRSS3_PHY_787_DATA 0x00005555 +#define DDRSS3_PHY_788_DATA 0x0000B5B5 +#define DDRSS3_PHY_789_DATA 0x00004A4A +#define DDRSS3_PHY_790_DATA 0x00005656 +#define DDRSS3_PHY_791_DATA 0x0000A9A9 +#define DDRSS3_PHY_792_DATA 0x0000A9A9 +#define DDRSS3_PHY_793_DATA 0x0000B5B5 +#define DDRSS3_PHY_794_DATA 0x00000000 +#define DDRSS3_PHY_795_DATA 0x00000000 +#define DDRSS3_PHY_796_DATA 0x2A000000 +#define DDRSS3_PHY_797_DATA 0x00000808 +#define DDRSS3_PHY_798_DATA 0x0F000000 +#define DDRSS3_PHY_799_DATA 0x00000F0F +#define DDRSS3_PHY_800_DATA 0x10400000 +#define DDRSS3_PHY_801_DATA 0x0C002006 +#define DDRSS3_PHY_802_DATA 0x00000000 +#define DDRSS3_PHY_803_DATA 0x00000000 +#define DDRSS3_PHY_804_DATA 0x55555555 +#define DDRSS3_PHY_805_DATA 0xAAAAAAAA +#define DDRSS3_PHY_806_DATA 0x55555555 +#define DDRSS3_PHY_807_DATA 0xAAAAAAAA +#define DDRSS3_PHY_808_DATA 0x00005555 +#define DDRSS3_PHY_809_DATA 0x01000100 +#define DDRSS3_PHY_810_DATA 0x00800180 +#define DDRSS3_PHY_811_DATA 0x00000000 +#define DDRSS3_PHY_812_DATA 0x00000000 +#define DDRSS3_PHY_813_DATA 0x00000000 +#define DDRSS3_PHY_814_DATA 0x00000000 +#define DDRSS3_PHY_815_DATA 0x00000000 +#define DDRSS3_PHY_816_DATA 0x00000000 +#define DDRSS3_PHY_817_DATA 0x00000000 +#define DDRSS3_PHY_818_DATA 0x00000000 +#define DDRSS3_PHY_819_DATA 0x00000000 +#define DDRSS3_PHY_820_DATA 0x00000000 +#define DDRSS3_PHY_821_DATA 0x00000000 +#define DDRSS3_PHY_822_DATA 0x00000000 +#define DDRSS3_PHY_823_DATA 0x00000000 +#define DDRSS3_PHY_824_DATA 0x00000000 +#define DDRSS3_PHY_825_DATA 0x00000000 +#define DDRSS3_PHY_826_DATA 0x00000000 +#define DDRSS3_PHY_827_DATA 0x00000000 +#define DDRSS3_PHY_828_DATA 0x00000000 +#define DDRSS3_PHY_829_DATA 0x00000000 +#define DDRSS3_PHY_830_DATA 0x00000000 +#define DDRSS3_PHY_831_DATA 0x00000000 +#define DDRSS3_PHY_832_DATA 0x00000000 +#define DDRSS3_PHY_833_DATA 0x00000000 +#define DDRSS3_PHY_834_DATA 0x00000104 +#define DDRSS3_PHY_835_DATA 0x00000120 +#define DDRSS3_PHY_836_DATA 0x00000000 +#define DDRSS3_PHY_837_DATA 0x00000000 +#define DDRSS3_PHY_838_DATA 0x00000000 +#define DDRSS3_PHY_839_DATA 0x00000000 +#define DDRSS3_PHY_840_DATA 0x00000000 +#define DDRSS3_PHY_841_DATA 0x00000000 +#define DDRSS3_PHY_842_DATA 0x00000000 +#define DDRSS3_PHY_843_DATA 0x00000001 +#define DDRSS3_PHY_844_DATA 0x07FF0000 +#define DDRSS3_PHY_845_DATA 0x0080081F +#define DDRSS3_PHY_846_DATA 0x00081020 +#define DDRSS3_PHY_847_DATA 0x04010000 +#define DDRSS3_PHY_848_DATA 0x00000000 +#define DDRSS3_PHY_849_DATA 0x00000000 +#define DDRSS3_PHY_850_DATA 0x00000000 +#define DDRSS3_PHY_851_DATA 0x00000100 +#define DDRSS3_PHY_852_DATA 0x01CC0C01 +#define DDRSS3_PHY_853_DATA 0x1003CC0C +#define DDRSS3_PHY_854_DATA 0x20000140 +#define DDRSS3_PHY_855_DATA 0x07FF0200 +#define DDRSS3_PHY_856_DATA 0x0000DD01 +#define DDRSS3_PHY_857_DATA 0x10100303 +#define DDRSS3_PHY_858_DATA 0x10101010 +#define DDRSS3_PHY_859_DATA 0x10101010 +#define DDRSS3_PHY_860_DATA 0x00021010 +#define DDRSS3_PHY_861_DATA 0x00100010 +#define DDRSS3_PHY_862_DATA 0x00100010 +#define DDRSS3_PHY_863_DATA 0x00100010 +#define DDRSS3_PHY_864_DATA 0x00100010 +#define DDRSS3_PHY_865_DATA 0x00050010 +#define DDRSS3_PHY_866_DATA 0x51517041 +#define DDRSS3_PHY_867_DATA 0x31C06001 +#define DDRSS3_PHY_868_DATA 0x07AB0340 +#define DDRSS3_PHY_869_DATA 0x00C0C001 +#define DDRSS3_PHY_870_DATA 0x0E0D0001 +#define DDRSS3_PHY_871_DATA 0x10001000 +#define DDRSS3_PHY_872_DATA 0x0C083E42 +#define DDRSS3_PHY_873_DATA 0x0F0C3701 +#define DDRSS3_PHY_874_DATA 0x01000140 +#define DDRSS3_PHY_875_DATA 0x0C000420 +#define DDRSS3_PHY_876_DATA 0x00000198 +#define DDRSS3_PHY_877_DATA 0x0A0000D0 +#define DDRSS3_PHY_878_DATA 0x00030200 +#define DDRSS3_PHY_879_DATA 0x02800000 +#define DDRSS3_PHY_880_DATA 0x80800000 +#define DDRSS3_PHY_881_DATA 0x000E2010 +#define DDRSS3_PHY_882_DATA 0x76543210 +#define DDRSS3_PHY_883_DATA 0x00000008 +#define DDRSS3_PHY_884_DATA 0x02800280 +#define DDRSS3_PHY_885_DATA 0x02800280 +#define DDRSS3_PHY_886_DATA 0x02800280 +#define DDRSS3_PHY_887_DATA 0x02800280 +#define DDRSS3_PHY_888_DATA 0x00000280 +#define DDRSS3_PHY_889_DATA 0x0000A000 +#define DDRSS3_PHY_890_DATA 0x00A000A0 +#define DDRSS3_PHY_891_DATA 0x00A000A0 +#define DDRSS3_PHY_892_DATA 0x00A000A0 +#define DDRSS3_PHY_893_DATA 0x00A000A0 +#define DDRSS3_PHY_894_DATA 0x00A000A0 +#define DDRSS3_PHY_895_DATA 0x00A000A0 +#define DDRSS3_PHY_896_DATA 0x00A000A0 +#define DDRSS3_PHY_897_DATA 0x00A000A0 +#define DDRSS3_PHY_898_DATA 0x01C200A0 +#define DDRSS3_PHY_899_DATA 0x01A00005 +#define DDRSS3_PHY_900_DATA 0x00000000 +#define DDRSS3_PHY_901_DATA 0x00000000 +#define DDRSS3_PHY_902_DATA 0x00080200 +#define DDRSS3_PHY_903_DATA 0x00000000 +#define DDRSS3_PHY_904_DATA 0x20202000 +#define DDRSS3_PHY_905_DATA 0x20202020 +#define DDRSS3_PHY_906_DATA 0xF0F02020 +#define DDRSS3_PHY_907_DATA 0x00000000 +#define DDRSS3_PHY_908_DATA 0x00000000 +#define DDRSS3_PHY_909_DATA 0x00000000 +#define DDRSS3_PHY_910_DATA 0x00000000 +#define DDRSS3_PHY_911_DATA 0x00000000 +#define DDRSS3_PHY_912_DATA 0x00000000 +#define DDRSS3_PHY_913_DATA 0x00000000 +#define DDRSS3_PHY_914_DATA 0x00000000 +#define DDRSS3_PHY_915_DATA 0x00000000 +#define DDRSS3_PHY_916_DATA 0x00000000 +#define DDRSS3_PHY_917_DATA 0x00000000 +#define DDRSS3_PHY_918_DATA 0x00000000 +#define DDRSS3_PHY_919_DATA 0x00000000 +#define DDRSS3_PHY_920_DATA 0x00000000 +#define DDRSS3_PHY_921_DATA 0x00000000 +#define DDRSS3_PHY_922_DATA 0x00000000 +#define DDRSS3_PHY_923_DATA 0x00000000 +#define DDRSS3_PHY_924_DATA 0x00000000 +#define DDRSS3_PHY_925_DATA 0x00000000 +#define DDRSS3_PHY_926_DATA 0x00000000 +#define DDRSS3_PHY_927_DATA 0x00000000 +#define DDRSS3_PHY_928_DATA 0x00000000 +#define DDRSS3_PHY_929_DATA 0x00000000 +#define DDRSS3_PHY_930_DATA 0x00000000 +#define DDRSS3_PHY_931_DATA 0x00000000 +#define DDRSS3_PHY_932_DATA 0x00000000 +#define DDRSS3_PHY_933_DATA 0x00000000 +#define DDRSS3_PHY_934_DATA 0x00000000 +#define DDRSS3_PHY_935_DATA 0x00000000 +#define DDRSS3_PHY_936_DATA 0x00000000 +#define DDRSS3_PHY_937_DATA 0x00000000 +#define DDRSS3_PHY_938_DATA 0x00000000 +#define DDRSS3_PHY_939_DATA 0x00000000 +#define DDRSS3_PHY_940_DATA 0x00000000 +#define DDRSS3_PHY_941_DATA 0x00000000 +#define DDRSS3_PHY_942_DATA 0x00000000 +#define DDRSS3_PHY_943_DATA 0x00000000 +#define DDRSS3_PHY_944_DATA 0x00000000 +#define DDRSS3_PHY_945_DATA 0x00000000 +#define DDRSS3_PHY_946_DATA 0x00000000 +#define DDRSS3_PHY_947_DATA 0x00000000 +#define DDRSS3_PHY_948_DATA 0x00000000 +#define DDRSS3_PHY_949_DATA 0x00000000 +#define DDRSS3_PHY_950_DATA 0x00000000 +#define DDRSS3_PHY_951_DATA 0x00000000 +#define DDRSS3_PHY_952_DATA 0x00000000 +#define DDRSS3_PHY_953_DATA 0x00000000 +#define DDRSS3_PHY_954_DATA 0x00000000 +#define DDRSS3_PHY_955_DATA 0x00000000 +#define DDRSS3_PHY_956_DATA 0x00000000 +#define DDRSS3_PHY_957_DATA 0x00000000 +#define DDRSS3_PHY_958_DATA 0x00000000 +#define DDRSS3_PHY_959_DATA 0x00000000 +#define DDRSS3_PHY_960_DATA 0x00000000 +#define DDRSS3_PHY_961_DATA 0x00000000 +#define DDRSS3_PHY_962_DATA 0x00000000 +#define DDRSS3_PHY_963_DATA 0x00000000 +#define DDRSS3_PHY_964_DATA 0x00000000 +#define DDRSS3_PHY_965_DATA 0x00000000 +#define DDRSS3_PHY_966_DATA 0x00000000 +#define DDRSS3_PHY_967_DATA 0x00000000 +#define DDRSS3_PHY_968_DATA 0x00000000 +#define DDRSS3_PHY_969_DATA 0x00000000 +#define DDRSS3_PHY_970_DATA 0x00000000 +#define DDRSS3_PHY_971_DATA 0x00000000 +#define DDRSS3_PHY_972_DATA 0x00000000 +#define DDRSS3_PHY_973_DATA 0x00000000 +#define DDRSS3_PHY_974_DATA 0x00000000 +#define DDRSS3_PHY_975_DATA 0x00000000 +#define DDRSS3_PHY_976_DATA 0x00000000 +#define DDRSS3_PHY_977_DATA 0x00000000 +#define DDRSS3_PHY_978_DATA 0x00000000 +#define DDRSS3_PHY_979_DATA 0x00000000 +#define DDRSS3_PHY_980_DATA 0x00000000 +#define DDRSS3_PHY_981_DATA 0x00000000 +#define DDRSS3_PHY_982_DATA 0x00000000 +#define DDRSS3_PHY_983_DATA 0x00000000 +#define DDRSS3_PHY_984_DATA 0x00000000 +#define DDRSS3_PHY_985_DATA 0x00000000 +#define DDRSS3_PHY_986_DATA 0x00000000 +#define DDRSS3_PHY_987_DATA 0x00000000 +#define DDRSS3_PHY_988_DATA 0x00000000 +#define DDRSS3_PHY_989_DATA 0x00000000 +#define DDRSS3_PHY_990_DATA 0x00000000 +#define DDRSS3_PHY_991_DATA 0x00000000 +#define DDRSS3_PHY_992_DATA 0x00000000 +#define DDRSS3_PHY_993_DATA 0x00000000 +#define DDRSS3_PHY_994_DATA 0x00000000 +#define DDRSS3_PHY_995_DATA 0x00000000 +#define DDRSS3_PHY_996_DATA 0x00000000 +#define DDRSS3_PHY_997_DATA 0x00000000 +#define DDRSS3_PHY_998_DATA 0x00000000 +#define DDRSS3_PHY_999_DATA 0x00000000 +#define DDRSS3_PHY_1000_DATA 0x00000000 +#define DDRSS3_PHY_1001_DATA 0x00000000 +#define DDRSS3_PHY_1002_DATA 0x00000000 +#define DDRSS3_PHY_1003_DATA 0x00000000 +#define DDRSS3_PHY_1004_DATA 0x00000000 +#define DDRSS3_PHY_1005_DATA 0x00000000 +#define DDRSS3_PHY_1006_DATA 0x00000000 +#define DDRSS3_PHY_1007_DATA 0x00000000 +#define DDRSS3_PHY_1008_DATA 0x00000000 +#define DDRSS3_PHY_1009_DATA 0x00000000 +#define DDRSS3_PHY_1010_DATA 0x00000000 +#define DDRSS3_PHY_1011_DATA 0x00000000 +#define DDRSS3_PHY_1012_DATA 0x00000000 +#define DDRSS3_PHY_1013_DATA 0x00000000 +#define DDRSS3_PHY_1014_DATA 0x00000000 +#define DDRSS3_PHY_1015_DATA 0x00000000 +#define DDRSS3_PHY_1016_DATA 0x00000000 +#define DDRSS3_PHY_1017_DATA 0x00000000 +#define DDRSS3_PHY_1018_DATA 0x00000000 +#define DDRSS3_PHY_1019_DATA 0x00000000 +#define DDRSS3_PHY_1020_DATA 0x00000000 +#define DDRSS3_PHY_1021_DATA 0x00000000 +#define DDRSS3_PHY_1022_DATA 0x00000000 +#define DDRSS3_PHY_1023_DATA 0x00000000 +#define DDRSS3_PHY_1024_DATA 0x00000000 +#define DDRSS3_PHY_1025_DATA 0x00000000 +#define DDRSS3_PHY_1026_DATA 0x00000000 +#define DDRSS3_PHY_1027_DATA 0x00000000 +#define DDRSS3_PHY_1028_DATA 0x00000000 +#define DDRSS3_PHY_1029_DATA 0x00000100 +#define DDRSS3_PHY_1030_DATA 0x00000200 +#define DDRSS3_PHY_1031_DATA 0x00000000 +#define DDRSS3_PHY_1032_DATA 0x00000000 +#define DDRSS3_PHY_1033_DATA 0x00000000 +#define DDRSS3_PHY_1034_DATA 0x00000000 +#define DDRSS3_PHY_1035_DATA 0x00400000 +#define DDRSS3_PHY_1036_DATA 0x00000080 +#define DDRSS3_PHY_1037_DATA 0x00DCBA98 +#define DDRSS3_PHY_1038_DATA 0x03000000 +#define DDRSS3_PHY_1039_DATA 0x00200000 +#define DDRSS3_PHY_1040_DATA 0x00000000 +#define DDRSS3_PHY_1041_DATA 0x00000000 +#define DDRSS3_PHY_1042_DATA 0x00000000 +#define DDRSS3_PHY_1043_DATA 0x00000000 +#define DDRSS3_PHY_1044_DATA 0x00000000 +#define DDRSS3_PHY_1045_DATA 0x0000002A +#define DDRSS3_PHY_1046_DATA 0x00000015 +#define DDRSS3_PHY_1047_DATA 0x00000015 +#define DDRSS3_PHY_1048_DATA 0x0000002A +#define DDRSS3_PHY_1049_DATA 0x00000033 +#define DDRSS3_PHY_1050_DATA 0x0000000C +#define DDRSS3_PHY_1051_DATA 0x0000000C +#define DDRSS3_PHY_1052_DATA 0x00000033 +#define DDRSS3_PHY_1053_DATA 0x00543210 +#define DDRSS3_PHY_1054_DATA 0x003F0000 +#define DDRSS3_PHY_1055_DATA 0x000F013F +#define DDRSS3_PHY_1056_DATA 0x20202003 +#define DDRSS3_PHY_1057_DATA 0x00202020 +#define DDRSS3_PHY_1058_DATA 0x20008008 +#define DDRSS3_PHY_1059_DATA 0x00000810 +#define DDRSS3_PHY_1060_DATA 0x00000F00 +#define DDRSS3_PHY_1061_DATA 0x00000000 +#define DDRSS3_PHY_1062_DATA 0x00000000 +#define DDRSS3_PHY_1063_DATA 0x00000000 +#define DDRSS3_PHY_1064_DATA 0x000305CC +#define DDRSS3_PHY_1065_DATA 0x00030000 +#define DDRSS3_PHY_1066_DATA 0x00000300 +#define DDRSS3_PHY_1067_DATA 0x00000300 +#define DDRSS3_PHY_1068_DATA 0x00000300 +#define DDRSS3_PHY_1069_DATA 0x00000300 +#define DDRSS3_PHY_1070_DATA 0x00000300 +#define DDRSS3_PHY_1071_DATA 0x42080010 +#define DDRSS3_PHY_1072_DATA 0x0000803E +#define DDRSS3_PHY_1073_DATA 0x00000001 +#define DDRSS3_PHY_1074_DATA 0x01000102 +#define DDRSS3_PHY_1075_DATA 0x00008000 +#define DDRSS3_PHY_1076_DATA 0x00000000 +#define DDRSS3_PHY_1077_DATA 0x00000000 +#define DDRSS3_PHY_1078_DATA 0x00000000 +#define DDRSS3_PHY_1079_DATA 0x00000000 +#define DDRSS3_PHY_1080_DATA 0x00000000 +#define DDRSS3_PHY_1081_DATA 0x00000000 +#define DDRSS3_PHY_1082_DATA 0x00000000 +#define DDRSS3_PHY_1083_DATA 0x00000000 +#define DDRSS3_PHY_1084_DATA 0x00000000 +#define DDRSS3_PHY_1085_DATA 0x00000000 +#define DDRSS3_PHY_1086_DATA 0x00000000 +#define DDRSS3_PHY_1087_DATA 0x00000000 +#define DDRSS3_PHY_1088_DATA 0x00000000 +#define DDRSS3_PHY_1089_DATA 0x00000000 +#define DDRSS3_PHY_1090_DATA 0x00000000 +#define DDRSS3_PHY_1091_DATA 0x00000000 +#define DDRSS3_PHY_1092_DATA 0x00000000 +#define DDRSS3_PHY_1093_DATA 0x00000000 +#define DDRSS3_PHY_1094_DATA 0x00000000 +#define DDRSS3_PHY_1095_DATA 0x00000000 +#define DDRSS3_PHY_1096_DATA 0x00000000 +#define DDRSS3_PHY_1097_DATA 0x00000000 +#define DDRSS3_PHY_1098_DATA 0x00000000 +#define DDRSS3_PHY_1099_DATA 0x00000000 +#define DDRSS3_PHY_1100_DATA 0x00000000 +#define DDRSS3_PHY_1101_DATA 0x00000000 +#define DDRSS3_PHY_1102_DATA 0x00000000 +#define DDRSS3_PHY_1103_DATA 0x00000000 +#define DDRSS3_PHY_1104_DATA 0x00000000 +#define DDRSS3_PHY_1105_DATA 0x00000000 +#define DDRSS3_PHY_1106_DATA 0x00000000 +#define DDRSS3_PHY_1107_DATA 0x00000000 +#define DDRSS3_PHY_1108_DATA 0x00000000 +#define DDRSS3_PHY_1109_DATA 0x00000000 +#define DDRSS3_PHY_1110_DATA 0x00000000 +#define DDRSS3_PHY_1111_DATA 0x00000000 +#define DDRSS3_PHY_1112_DATA 0x00000000 +#define DDRSS3_PHY_1113_DATA 0x00000000 +#define DDRSS3_PHY_1114_DATA 0x00000000 +#define DDRSS3_PHY_1115_DATA 0x00000000 +#define DDRSS3_PHY_1116_DATA 0x00000000 +#define DDRSS3_PHY_1117_DATA 0x00000000 +#define DDRSS3_PHY_1118_DATA 0x00000000 +#define DDRSS3_PHY_1119_DATA 0x00000000 +#define DDRSS3_PHY_1120_DATA 0x00000000 +#define DDRSS3_PHY_1121_DATA 0x00000000 +#define DDRSS3_PHY_1122_DATA 0x00000000 +#define DDRSS3_PHY_1123_DATA 0x00000000 +#define DDRSS3_PHY_1124_DATA 0x00000000 +#define DDRSS3_PHY_1125_DATA 0x00000000 +#define DDRSS3_PHY_1126_DATA 0x00000000 +#define DDRSS3_PHY_1127_DATA 0x00000000 +#define DDRSS3_PHY_1128_DATA 0x00000000 +#define DDRSS3_PHY_1129_DATA 0x00000000 +#define DDRSS3_PHY_1130_DATA 0x00000000 +#define DDRSS3_PHY_1131_DATA 0x00000000 +#define DDRSS3_PHY_1132_DATA 0x00000000 +#define DDRSS3_PHY_1133_DATA 0x00000000 +#define DDRSS3_PHY_1134_DATA 0x00000000 +#define DDRSS3_PHY_1135_DATA 0x00000000 +#define DDRSS3_PHY_1136_DATA 0x00000000 +#define DDRSS3_PHY_1137_DATA 0x00000000 +#define DDRSS3_PHY_1138_DATA 0x00000000 +#define DDRSS3_PHY_1139_DATA 0x00000000 +#define DDRSS3_PHY_1140_DATA 0x00000000 +#define DDRSS3_PHY_1141_DATA 0x00000000 +#define DDRSS3_PHY_1142_DATA 0x00000000 +#define DDRSS3_PHY_1143_DATA 0x00000000 +#define DDRSS3_PHY_1144_DATA 0x00000000 +#define DDRSS3_PHY_1145_DATA 0x00000000 +#define DDRSS3_PHY_1146_DATA 0x00000000 +#define DDRSS3_PHY_1147_DATA 0x00000000 +#define DDRSS3_PHY_1148_DATA 0x00000000 +#define DDRSS3_PHY_1149_DATA 0x00000000 +#define DDRSS3_PHY_1150_DATA 0x00000000 +#define DDRSS3_PHY_1151_DATA 0x00000000 +#define DDRSS3_PHY_1152_DATA 0x00000000 +#define DDRSS3_PHY_1153_DATA 0x00000000 +#define DDRSS3_PHY_1154_DATA 0x00000000 +#define DDRSS3_PHY_1155_DATA 0x00000000 +#define DDRSS3_PHY_1156_DATA 0x00000000 +#define DDRSS3_PHY_1157_DATA 0x00000000 +#define DDRSS3_PHY_1158_DATA 0x00000000 +#define DDRSS3_PHY_1159_DATA 0x00000000 +#define DDRSS3_PHY_1160_DATA 0x00000000 +#define DDRSS3_PHY_1161_DATA 0x00000000 +#define DDRSS3_PHY_1162_DATA 0x00000000 +#define DDRSS3_PHY_1163_DATA 0x00000000 +#define DDRSS3_PHY_1164_DATA 0x00000000 +#define DDRSS3_PHY_1165_DATA 0x00000000 +#define DDRSS3_PHY_1166_DATA 0x00000000 +#define DDRSS3_PHY_1167_DATA 0x00000000 +#define DDRSS3_PHY_1168_DATA 0x00000000 +#define DDRSS3_PHY_1169_DATA 0x00000000 +#define DDRSS3_PHY_1170_DATA 0x00000000 +#define DDRSS3_PHY_1171_DATA 0x00000000 +#define DDRSS3_PHY_1172_DATA 0x00000000 +#define DDRSS3_PHY_1173_DATA 0x00000000 +#define DDRSS3_PHY_1174_DATA 0x00000000 +#define DDRSS3_PHY_1175_DATA 0x00000000 +#define DDRSS3_PHY_1176_DATA 0x00000000 +#define DDRSS3_PHY_1177_DATA 0x00000000 +#define DDRSS3_PHY_1178_DATA 0x00000000 +#define DDRSS3_PHY_1179_DATA 0x00000000 +#define DDRSS3_PHY_1180_DATA 0x00000000 +#define DDRSS3_PHY_1181_DATA 0x00000000 +#define DDRSS3_PHY_1182_DATA 0x00000000 +#define DDRSS3_PHY_1183_DATA 0x00000000 +#define DDRSS3_PHY_1184_DATA 0x00000000 +#define DDRSS3_PHY_1185_DATA 0x00000000 +#define DDRSS3_PHY_1186_DATA 0x00000000 +#define DDRSS3_PHY_1187_DATA 0x00000000 +#define DDRSS3_PHY_1188_DATA 0x00000000 +#define DDRSS3_PHY_1189_DATA 0x00000000 +#define DDRSS3_PHY_1190_DATA 0x00000000 +#define DDRSS3_PHY_1191_DATA 0x00000000 +#define DDRSS3_PHY_1192_DATA 0x00000000 +#define DDRSS3_PHY_1193_DATA 0x00000000 +#define DDRSS3_PHY_1194_DATA 0x00000000 +#define DDRSS3_PHY_1195_DATA 0x00000000 +#define DDRSS3_PHY_1196_DATA 0x00000000 +#define DDRSS3_PHY_1197_DATA 0x00000000 +#define DDRSS3_PHY_1198_DATA 0x00000000 +#define DDRSS3_PHY_1199_DATA 0x00000000 +#define DDRSS3_PHY_1200_DATA 0x00000000 +#define DDRSS3_PHY_1201_DATA 0x00000000 +#define DDRSS3_PHY_1202_DATA 0x00000000 +#define DDRSS3_PHY_1203_DATA 0x00000000 +#define DDRSS3_PHY_1204_DATA 0x00000000 +#define DDRSS3_PHY_1205_DATA 0x00000000 +#define DDRSS3_PHY_1206_DATA 0x00000000 +#define DDRSS3_PHY_1207_DATA 0x00000000 +#define DDRSS3_PHY_1208_DATA 0x00000000 +#define DDRSS3_PHY_1209_DATA 0x00000000 +#define DDRSS3_PHY_1210_DATA 0x00000000 +#define DDRSS3_PHY_1211_DATA 0x00000000 +#define DDRSS3_PHY_1212_DATA 0x00000000 +#define DDRSS3_PHY_1213_DATA 0x00000000 +#define DDRSS3_PHY_1214_DATA 0x00000000 +#define DDRSS3_PHY_1215_DATA 0x00000000 +#define DDRSS3_PHY_1216_DATA 0x00000000 +#define DDRSS3_PHY_1217_DATA 0x00000000 +#define DDRSS3_PHY_1218_DATA 0x00000000 +#define DDRSS3_PHY_1219_DATA 0x00000000 +#define DDRSS3_PHY_1220_DATA 0x00000000 +#define DDRSS3_PHY_1221_DATA 0x00000000 +#define DDRSS3_PHY_1222_DATA 0x00000000 +#define DDRSS3_PHY_1223_DATA 0x00000000 +#define DDRSS3_PHY_1224_DATA 0x00000000 +#define DDRSS3_PHY_1225_DATA 0x00000000 +#define DDRSS3_PHY_1226_DATA 0x00000000 +#define DDRSS3_PHY_1227_DATA 0x00000000 +#define DDRSS3_PHY_1228_DATA 0x00000000 +#define DDRSS3_PHY_1229_DATA 0x00000000 +#define DDRSS3_PHY_1230_DATA 0x00000000 +#define DDRSS3_PHY_1231_DATA 0x00000000 +#define DDRSS3_PHY_1232_DATA 0x00000000 +#define DDRSS3_PHY_1233_DATA 0x00000000 +#define DDRSS3_PHY_1234_DATA 0x00000000 +#define DDRSS3_PHY_1235_DATA 0x00000000 +#define DDRSS3_PHY_1236_DATA 0x00000000 +#define DDRSS3_PHY_1237_DATA 0x00000000 +#define DDRSS3_PHY_1238_DATA 0x00000000 +#define DDRSS3_PHY_1239_DATA 0x00000000 +#define DDRSS3_PHY_1240_DATA 0x00000000 +#define DDRSS3_PHY_1241_DATA 0x00000000 +#define DDRSS3_PHY_1242_DATA 0x00000000 +#define DDRSS3_PHY_1243_DATA 0x00000000 +#define DDRSS3_PHY_1244_DATA 0x00000000 +#define DDRSS3_PHY_1245_DATA 0x00000000 +#define DDRSS3_PHY_1246_DATA 0x00000000 +#define DDRSS3_PHY_1247_DATA 0x00000000 +#define DDRSS3_PHY_1248_DATA 0x00000000 +#define DDRSS3_PHY_1249_DATA 0x00000000 +#define DDRSS3_PHY_1250_DATA 0x00000000 +#define DDRSS3_PHY_1251_DATA 0x00000000 +#define DDRSS3_PHY_1252_DATA 0x00000000 +#define DDRSS3_PHY_1253_DATA 0x00000000 +#define DDRSS3_PHY_1254_DATA 0x00000000 +#define DDRSS3_PHY_1255_DATA 0x00000000 +#define DDRSS3_PHY_1256_DATA 0x00000000 +#define DDRSS3_PHY_1257_DATA 0x00000000 +#define DDRSS3_PHY_1258_DATA 0x00000000 +#define DDRSS3_PHY_1259_DATA 0x00000000 +#define DDRSS3_PHY_1260_DATA 0x00000000 +#define DDRSS3_PHY_1261_DATA 0x00000000 +#define DDRSS3_PHY_1262_DATA 0x00000000 +#define DDRSS3_PHY_1263_DATA 0x00000000 +#define DDRSS3_PHY_1264_DATA 0x00000000 +#define DDRSS3_PHY_1265_DATA 0x00000000 +#define DDRSS3_PHY_1266_DATA 0x00000000 +#define DDRSS3_PHY_1267_DATA 0x00000000 +#define DDRSS3_PHY_1268_DATA 0x00000000 +#define DDRSS3_PHY_1269_DATA 0x00000000 +#define DDRSS3_PHY_1270_DATA 0x00000000 +#define DDRSS3_PHY_1271_DATA 0x00000000 +#define DDRSS3_PHY_1272_DATA 0x00000000 +#define DDRSS3_PHY_1273_DATA 0x00000000 +#define DDRSS3_PHY_1274_DATA 0x00000000 +#define DDRSS3_PHY_1275_DATA 0x00000000 +#define DDRSS3_PHY_1276_DATA 0x00000000 +#define DDRSS3_PHY_1277_DATA 0x00000000 +#define DDRSS3_PHY_1278_DATA 0x00000000 +#define DDRSS3_PHY_1279_DATA 0x00000000 +#define DDRSS3_PHY_1280_DATA 0x00000000 +#define DDRSS3_PHY_1281_DATA 0x00010100 +#define DDRSS3_PHY_1282_DATA 0x00000000 +#define DDRSS3_PHY_1283_DATA 0x00000000 +#define DDRSS3_PHY_1284_DATA 0x00050000 +#define DDRSS3_PHY_1285_DATA 0x04000000 +#define DDRSS3_PHY_1286_DATA 0x00000055 +#define DDRSS3_PHY_1287_DATA 0x00000000 +#define DDRSS3_PHY_1288_DATA 0x00000000 +#define DDRSS3_PHY_1289_DATA 0x00000000 +#define DDRSS3_PHY_1290_DATA 0x00000000 +#define DDRSS3_PHY_1291_DATA 0x00002001 +#define DDRSS3_PHY_1292_DATA 0x0000400F +#define DDRSS3_PHY_1293_DATA 0x50020028 +#define DDRSS3_PHY_1294_DATA 0x01010000 +#define DDRSS3_PHY_1295_DATA 0x80080001 +#define DDRSS3_PHY_1296_DATA 0x10200000 +#define DDRSS3_PHY_1297_DATA 0x00000008 +#define DDRSS3_PHY_1298_DATA 0x00000000 +#define DDRSS3_PHY_1299_DATA 0x01090E00 +#define DDRSS3_PHY_1300_DATA 0x00040101 +#define DDRSS3_PHY_1301_DATA 0x0000010F +#define DDRSS3_PHY_1302_DATA 0x00000000 +#define DDRSS3_PHY_1303_DATA 0x0000FFFF +#define DDRSS3_PHY_1304_DATA 0x00000000 +#define DDRSS3_PHY_1305_DATA 0x01010000 +#define DDRSS3_PHY_1306_DATA 0x01080402 +#define DDRSS3_PHY_1307_DATA 0x01200F02 +#define DDRSS3_PHY_1308_DATA 0x00194280 +#define DDRSS3_PHY_1309_DATA 0x00000004 +#define DDRSS3_PHY_1310_DATA 0x00042000 +#define DDRSS3_PHY_1311_DATA 0x00000000 +#define DDRSS3_PHY_1312_DATA 0x00000000 +#define DDRSS3_PHY_1313_DATA 0x00000000 +#define DDRSS3_PHY_1314_DATA 0x00000000 +#define DDRSS3_PHY_1315_DATA 0x00000000 +#define DDRSS3_PHY_1316_DATA 0x00000000 +#define DDRSS3_PHY_1317_DATA 0x01000000 +#define DDRSS3_PHY_1318_DATA 0x00000705 +#define DDRSS3_PHY_1319_DATA 0x00000054 +#define DDRSS3_PHY_1320_DATA 0x00030820 +#define DDRSS3_PHY_1321_DATA 0x00010820 +#define DDRSS3_PHY_1322_DATA 0x00010820 +#define DDRSS3_PHY_1323_DATA 0x00010820 +#define DDRSS3_PHY_1324_DATA 0x00010820 +#define DDRSS3_PHY_1325_DATA 0x00010820 +#define DDRSS3_PHY_1326_DATA 0x00010820 +#define DDRSS3_PHY_1327_DATA 0x00010820 +#define DDRSS3_PHY_1328_DATA 0x00010820 +#define DDRSS3_PHY_1329_DATA 0x00000000 +#define DDRSS3_PHY_1330_DATA 0x00000074 +#define DDRSS3_PHY_1331_DATA 0x00000400 +#define DDRSS3_PHY_1332_DATA 0x00000108 +#define DDRSS3_PHY_1333_DATA 0x00000000 +#define DDRSS3_PHY_1334_DATA 0x00000000 +#define DDRSS3_PHY_1335_DATA 0x00000000 +#define DDRSS3_PHY_1336_DATA 0x00000000 +#define DDRSS3_PHY_1337_DATA 0x00000000 +#define DDRSS3_PHY_1338_DATA 0x03000000 +#define DDRSS3_PHY_1339_DATA 0x00000000 +#define DDRSS3_PHY_1340_DATA 0x00000000 +#define DDRSS3_PHY_1341_DATA 0x00000000 +#define DDRSS3_PHY_1342_DATA 0x04102006 +#define DDRSS3_PHY_1343_DATA 0x00041020 +#define DDRSS3_PHY_1344_DATA 0x01C98C98 +#define DDRSS3_PHY_1345_DATA 0x3F400000 +#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS3_PHY_1347_DATA 0x0000001F +#define DDRSS3_PHY_1348_DATA 0x00000000 +#define DDRSS3_PHY_1349_DATA 0x00000000 +#define DDRSS3_PHY_1350_DATA 0x00000000 +#define DDRSS3_PHY_1351_DATA 0x00010000 +#define DDRSS3_PHY_1352_DATA 0x00000000 +#define DDRSS3_PHY_1353_DATA 0x00000000 +#define DDRSS3_PHY_1354_DATA 0x00000000 +#define DDRSS3_PHY_1355_DATA 0x00000000 +#define DDRSS3_PHY_1356_DATA 0x76543210 +#define DDRSS3_PHY_1357_DATA 0x00010198 +#define DDRSS3_PHY_1358_DATA 0x00000000 +#define DDRSS3_PHY_1359_DATA 0x00000000 +#define DDRSS3_PHY_1360_DATA 0x00000000 +#define DDRSS3_PHY_1361_DATA 0x00040700 +#define DDRSS3_PHY_1362_DATA 0x00000000 +#define DDRSS3_PHY_1363_DATA 0x00000000 +#define DDRSS3_PHY_1364_DATA 0x00000000 +#define DDRSS3_PHY_1365_DATA 0x00000000 +#define DDRSS3_PHY_1366_DATA 0x00000000 +#define DDRSS3_PHY_1367_DATA 0x00000002 +#define DDRSS3_PHY_1368_DATA 0x00000000 +#define DDRSS3_PHY_1369_DATA 0x00000000 +#define DDRSS3_PHY_1370_DATA 0x00000000 +#define DDRSS3_PHY_1371_DATA 0x00000000 +#define DDRSS3_PHY_1372_DATA 0x00000000 +#define DDRSS3_PHY_1373_DATA 0x00000000 +#define DDRSS3_PHY_1374_DATA 0x00080000 +#define DDRSS3_PHY_1375_DATA 0x000007FF +#define DDRSS3_PHY_1376_DATA 0x00000000 +#define DDRSS3_PHY_1377_DATA 0x00000000 +#define DDRSS3_PHY_1378_DATA 0x00000000 +#define DDRSS3_PHY_1379_DATA 0x00000000 +#define DDRSS3_PHY_1380_DATA 0x00000000 +#define DDRSS3_PHY_1381_DATA 0x00000000 +#define DDRSS3_PHY_1382_DATA 0x000FFFFF +#define DDRSS3_PHY_1383_DATA 0x000FFFFF +#define DDRSS3_PHY_1384_DATA 0x0000FFFF +#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS3_PHY_1386_DATA 0x030FFFFF +#define DDRSS3_PHY_1387_DATA 0x01FFFFFF +#define DDRSS3_PHY_1388_DATA 0x0000FFFF +#define DDRSS3_PHY_1389_DATA 0x00000000 +#define DDRSS3_PHY_1390_DATA 0x00000000 +#define DDRSS3_PHY_1391_DATA 0x00000000 +#define DDRSS3_PHY_1392_DATA 0x00000000 +#define DDRSS3_PHY_1393_DATA 0x0001F7C0 +#define DDRSS3_PHY_1394_DATA 0x00000003 +#define DDRSS3_PHY_1395_DATA 0x00000000 +#define DDRSS3_PHY_1396_DATA 0x00001142 +#define DDRSS3_PHY_1397_DATA 0x010207AB +#define DDRSS3_PHY_1398_DATA 0x01000080 +#define DDRSS3_PHY_1399_DATA 0x03900390 +#define DDRSS3_PHY_1400_DATA 0x03900390 +#define DDRSS3_PHY_1401_DATA 0x00000390 +#define DDRSS3_PHY_1402_DATA 0x00000390 +#define DDRSS3_PHY_1403_DATA 0x00000390 +#define DDRSS3_PHY_1404_DATA 0x00000390 +#define DDRSS3_PHY_1405_DATA 0x00000005 +#define DDRSS3_PHY_1406_DATA 0x01813FCC +#define DDRSS3_PHY_1407_DATA 0x000000CC +#define DDRSS3_PHY_1408_DATA 0x0C000DFF +#define DDRSS3_PHY_1409_DATA 0x30000DFF +#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1411_DATA 0x000100F0 +#define DDRSS3_PHY_1412_DATA 0x780DFFCC +#define DDRSS3_PHY_1413_DATA 0x00007E31 +#define DDRSS3_PHY_1414_DATA 0x000CBF11 +#define DDRSS3_PHY_1415_DATA 0x01990010 +#define DDRSS3_PHY_1416_DATA 0x000CBF11 +#define DDRSS3_PHY_1417_DATA 0x01990010 +#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1419_DATA 0x00EF00F0 +#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1421_DATA 0x01FF00F0 +#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi new file mode 100644 index 00000000000..ede5d6e58f5 --- /dev/null +++ b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define SPL_BOARD_DTB "spl/dts/ti/k3-j742s2-evm.dtb" +#define BOARD_DESCRIPTION "k3-j742s2-evm" +#define UBOOT_BOARD_DESCRIPTION "U-Boot for J742S2 board" + +#include "k3-j784s4-binman.dtsi" + +#if !defined(CONFIG_ARM64) + +&binman { + tiboot3-j742s2-hs-fs { + insert-template = <&tiboot3_j784s4_hs_fs>; + filename = "tiboot3-j742s2-hs-fs-evm.bin"; + symlink = "tiboot3.bin"; + }; + + tiboot3-j742s2-hs { + insert-template = <&tiboot3_j784s4_hs>; + filename = "tiboot3-j742s2-hs-evm.bin"; + }; +}; + +&ti_fs_enc_fs { + filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-enc.bin"; +}; + +&sysfw_inner_cert_fs { + filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-cert.bin"; +}; + +&ti_fs_enc { + filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-enc.bin"; +}; + +&sysfw_inner_cert { + filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-cert.bin"; +}; + +#else // CONFIG_ARM64 + +&binman { + ti-dm { + filename = "ti-dm.bin"; + + blob-ext { + filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + tispl { + insert-template = <&ti_spl>; + }; + + u-boot { + insert-template = <&u_boot>; + }; + + tispl-unsigned { + insert-template = <&ti_spl_unsigned>; + }; + + u-boot-unsigned { + insert-template = <&u_boot_unsigned>; + }; +}; + +#endif diff --git a/arch/arm/dts/k3-j742s2-r5-evm.dts b/arch/arm/dts/k3-j742s2-r5-evm.dts new file mode 100644 index 00000000000..6dde13c4e75 --- /dev/null +++ b/arch/arm/dts/k3-j742s2-r5-evm.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ +/dts-v1/; + +#include "k3-j742s2-evm.dts" +#include "k3-j742s2-ddr-evm-lp4-4266.dtsi" +#include "k3-j784s4-j742s2-ddr.dtsi" +#include "k3-j742s2-evm-u-boot.dtsi" +#include "k3-j784s4-r5.dtsi" + +&tps659413 { + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index 85bdd1f5b6c..0553825b383 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -5,16 +5,15 @@ #include "k3-binman.dtsi" -#ifdef CONFIG_TARGET_J784S4_R5_EVM +#if defined(CONFIG_CPU_V7R) &rcfg_yaml_tifs { config = "tifs-rm-cfg.yaml"; }; &binman { - tiboot3-j784s4-hs-evm.bin { - filename = "tiboot3-j784s4-hs-evm.bin"; - + tiboot3_j784s4_hs: template-9 { + section { ti-secure-rom { content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, <&combined_dm_cfg>, <&sysfw_inner_cert>; @@ -39,7 +38,6 @@ }; ti_fs_enc: ti-fs-enc.bin { - filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; type = "blob-ext"; optional; }; @@ -50,7 +48,6 @@ }; sysfw_inner_cert: sysfw-inner-cert { - filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; type = "blob-ext"; optional; }; @@ -59,13 +56,13 @@ filename = "combined-dm-cfg.bin"; type = "blob-ext"; }; + }; }; }; &binman { - tiboot3-j784s4-hs-fs-evm.bin { - filename = "tiboot3-j784s4-hs-fs-evm.bin"; - + tiboot3_j784s4_hs_fs: template-10 { + section { ti-secure-rom { content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; @@ -90,7 +87,6 @@ }; ti_fs_enc_fs: ti-fs-enc.bin { - filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin"; type = "blob-ext"; optional; }; @@ -101,7 +97,6 @@ }; sysfw_inner_cert_fs: sysfw-inner-cert { - filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin"; type = "blob-ext"; optional; }; @@ -110,14 +105,13 @@ filename = "combined-dm-cfg.bin"; type = "blob-ext"; }; + }; }; }; &binman { - tiboot3-j784s4-gp-evm.bin { - filename = "tiboot3-j784s4-gp-evm.bin"; - symlink = "tiboot3.bin"; - + tiboot3_j784s4_gp: template-11 { + section { ti-secure-rom { content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; @@ -140,7 +134,6 @@ }; ti_fs_gp: ti-fs-gp.bin { - filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin"; type = "blob-ext"; optional; }; @@ -154,43 +147,14 @@ filename = "combined-dm-cfg.bin"; type = "blob-ext"; }; - - }; -}; - -#include "k3-binman-capsule-r5.dtsi" - -// Capsule update GUIDs in string form. See j784s4_evm.h -#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46" - -&capsule_tiboot3 { - efi-capsule { - image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR; - - blob { - filename = "tiboot3-j784s4-hs-fs-evm.bin"; }; }; }; -#endif - -#ifdef CONFIG_TARGET_J784S4_A72_EVM - -#define SPL_J784S4_EVM_DTB "spl/dts/ti/k3-j784s4-evm.dtb" -#define J784S4_EVM_DTB "u-boot.dtb" +#else &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - - ti-spl { + ti_spl: template-12 { insert-template = <&ti_spl_template>; fit { @@ -207,19 +171,20 @@ }; fdt-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; type = "flat_dt"; arch = "arm"; compression = "none"; ti-secure { - content = <&spl_j784s4_evm_dtb>; + content = <&spl_board_dtb>; keyfile = "custMpk.pem"; }; - spl_j784s4_evm_dtb: blob-ext { - filename = SPL_J784S4_EVM_DTB; + spl_board_dtb: blob-ext { + filename = SPL_BOARD_DTB; }; + }; }; @@ -227,7 +192,7 @@ default = "conf-0"; conf-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; firmware = "atf"; loadables = "tee", "dm", "spl"; fdt = "fdt-0"; @@ -238,17 +203,17 @@ }; &binman { - u-boot { + u_boot: template-13 { insert-template = <&u_boot_template>; fit { images { uboot { - description = "U-Boot for J784S4 board"; + description = UBOOT_BOARD_DESCRIPTION; }; fdt-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; type = "flat_dt"; arch = "arm"; compression = "none"; @@ -259,7 +224,7 @@ }; j784s4_evm_dtb: blob-ext { - filename = J784S4_EVM_DTB; + filename = "u-boot.dtb"; }; hash { @@ -272,7 +237,7 @@ default = "conf-0"; conf-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; firmware = "uboot"; loadables = "uboot"; fdt = "fdt-0"; @@ -283,7 +248,7 @@ }; &binman { - ti-spl_unsigned { + ti_spl_unsigned: template-14 { insert-template = <&ti_spl_unsigned_template>; fit { @@ -295,13 +260,13 @@ }; fdt-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; type = "flat_dt"; arch = "arm"; compression = "none"; spl_j784s4_evm_dtb_unsigned: blob { - filename = SPL_J784S4_EVM_DTB; + filename = SPL_BOARD_DTB; }; }; }; @@ -310,7 +275,7 @@ default = "conf-0"; conf-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; firmware = "atf"; loadables = "tee", "dm", "spl"; fdt = "fdt-0"; @@ -321,23 +286,23 @@ }; &binman { - u-boot_unsigned { + u_boot_unsigned: template-15 { insert-template = <&u_boot_unsigned_template>; fit { images { uboot { - description = "U-Boot for J784S4 board"; + description = UBOOT_BOARD_DESCRIPTION; }; fdt-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; type = "flat_dt"; arch = "arm"; compression = "none"; j784s4_evm_dtb_unsigned: blob { - filename = J784S4_EVM_DTB; + filename = "u-boot.dtb"; }; hash { @@ -350,7 +315,7 @@ default = "conf-0"; conf-0 { - description = "k3-j784s4-evm"; + description = BOARD_DESCRIPTION; firmware = "uboot"; loadables = "uboot"; fdt = "fdt-0"; @@ -359,23 +324,4 @@ }; }; }; - -#include "k3-binman-capsule.dtsi" - -// Capsule update GUIDs in string form. See j784s4_evm.h -#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e" -#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617" - -&capsule_tispl { - efi-capsule { - image-guid = AM69_SK_SPL_IMAGE_GUID_STR; - }; -}; - -&capsule_uboot { - efi-capsule { - image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR; - }; -}; - #endif diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi index fc74c539331..47ed3f05eb2 100644 --- a/arch/arm/dts/k3-j784s4-ddr.dtsi +++ b/arch/arm/dts/k3-j784s4-ddr.dtsi @@ -3,8864 +3,4424 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ -&main_navss { - ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr - <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg - <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg - <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg - <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg - <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0 - <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1 - <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2 - <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3 - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; +#include "k3-j784s4-j742s2-ddr.dtsi" - msmc0: msmc { - compatible = "ti,j721s2-msmc"; - intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>; - intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>; - ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>; - emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>; - emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>; - #address-cells = <2>; - #size-cells = <2>; +&msmc0 { + memorycontroller2: memorycontroller@29d0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029d0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029c0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; + power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>, + <&k3_pds 133 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 193 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <2>; bootph-pre-ram; - memorycontroller0: memorycontroller@2990000 { - compatible = "ti,j721s2-ddrss"; - reg = <0x0 0x02990000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>, - <0x0 0x02980000 0x0 0x200>; - reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; - power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>, - <&k3_pds 131 TI_SCI_PD_SHARED>; - clocks = <&k3_clks 191 1>, <&k3_clks 78 2>; - ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; - ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; - ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; - ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; - instance = <0>; + ti,ctl-data = < + DDRSS2_CTL_00_DATA + DDRSS2_CTL_01_DATA + DDRSS2_CTL_02_DATA + DDRSS2_CTL_03_DATA + DDRSS2_CTL_04_DATA + DDRSS2_CTL_05_DATA + DDRSS2_CTL_06_DATA + DDRSS2_CTL_07_DATA + DDRSS2_CTL_08_DATA + DDRSS2_CTL_09_DATA + DDRSS2_CTL_10_DATA + DDRSS2_CTL_11_DATA + DDRSS2_CTL_12_DATA + DDRSS2_CTL_13_DATA + DDRSS2_CTL_14_DATA + DDRSS2_CTL_15_DATA + DDRSS2_CTL_16_DATA + DDRSS2_CTL_17_DATA + DDRSS2_CTL_18_DATA + DDRSS2_CTL_19_DATA + DDRSS2_CTL_20_DATA + DDRSS2_CTL_21_DATA + DDRSS2_CTL_22_DATA + DDRSS2_CTL_23_DATA + DDRSS2_CTL_24_DATA + DDRSS2_CTL_25_DATA + DDRSS2_CTL_26_DATA + DDRSS2_CTL_27_DATA + DDRSS2_CTL_28_DATA + DDRSS2_CTL_29_DATA + DDRSS2_CTL_30_DATA + DDRSS2_CTL_31_DATA + DDRSS2_CTL_32_DATA + DDRSS2_CTL_33_DATA + DDRSS2_CTL_34_DATA + DDRSS2_CTL_35_DATA + DDRSS2_CTL_36_DATA + DDRSS2_CTL_37_DATA + DDRSS2_CTL_38_DATA + DDRSS2_CTL_39_DATA + DDRSS2_CTL_40_DATA + DDRSS2_CTL_41_DATA + DDRSS2_CTL_42_DATA + DDRSS2_CTL_43_DATA + DDRSS2_CTL_44_DATA + DDRSS2_CTL_45_DATA + DDRSS2_CTL_46_DATA + DDRSS2_CTL_47_DATA + DDRSS2_CTL_48_DATA + DDRSS2_CTL_49_DATA + DDRSS2_CTL_50_DATA + DDRSS2_CTL_51_DATA + DDRSS2_CTL_52_DATA + DDRSS2_CTL_53_DATA + DDRSS2_CTL_54_DATA + DDRSS2_CTL_55_DATA + DDRSS2_CTL_56_DATA + DDRSS2_CTL_57_DATA + DDRSS2_CTL_58_DATA + DDRSS2_CTL_59_DATA + DDRSS2_CTL_60_DATA + DDRSS2_CTL_61_DATA + DDRSS2_CTL_62_DATA + DDRSS2_CTL_63_DATA + DDRSS2_CTL_64_DATA + DDRSS2_CTL_65_DATA + DDRSS2_CTL_66_DATA + DDRSS2_CTL_67_DATA + DDRSS2_CTL_68_DATA + DDRSS2_CTL_69_DATA + DDRSS2_CTL_70_DATA + DDRSS2_CTL_71_DATA + DDRSS2_CTL_72_DATA + DDRSS2_CTL_73_DATA + DDRSS2_CTL_74_DATA + DDRSS2_CTL_75_DATA + DDRSS2_CTL_76_DATA + DDRSS2_CTL_77_DATA + DDRSS2_CTL_78_DATA + DDRSS2_CTL_79_DATA + DDRSS2_CTL_80_DATA + DDRSS2_CTL_81_DATA + DDRSS2_CTL_82_DATA + DDRSS2_CTL_83_DATA + DDRSS2_CTL_84_DATA + DDRSS2_CTL_85_DATA + DDRSS2_CTL_86_DATA + DDRSS2_CTL_87_DATA + DDRSS2_CTL_88_DATA + DDRSS2_CTL_89_DATA + DDRSS2_CTL_90_DATA + DDRSS2_CTL_91_DATA + DDRSS2_CTL_92_DATA + DDRSS2_CTL_93_DATA + DDRSS2_CTL_94_DATA + DDRSS2_CTL_95_DATA + DDRSS2_CTL_96_DATA + DDRSS2_CTL_97_DATA + DDRSS2_CTL_98_DATA + DDRSS2_CTL_99_DATA + DDRSS2_CTL_100_DATA + DDRSS2_CTL_101_DATA + DDRSS2_CTL_102_DATA + DDRSS2_CTL_103_DATA + DDRSS2_CTL_104_DATA + DDRSS2_CTL_105_DATA + DDRSS2_CTL_106_DATA + DDRSS2_CTL_107_DATA + DDRSS2_CTL_108_DATA + DDRSS2_CTL_109_DATA + DDRSS2_CTL_110_DATA + DDRSS2_CTL_111_DATA + DDRSS2_CTL_112_DATA + DDRSS2_CTL_113_DATA + DDRSS2_CTL_114_DATA + DDRSS2_CTL_115_DATA + DDRSS2_CTL_116_DATA + DDRSS2_CTL_117_DATA + DDRSS2_CTL_118_DATA + DDRSS2_CTL_119_DATA + DDRSS2_CTL_120_DATA + DDRSS2_CTL_121_DATA + DDRSS2_CTL_122_DATA + DDRSS2_CTL_123_DATA + DDRSS2_CTL_124_DATA + DDRSS2_CTL_125_DATA + DDRSS2_CTL_126_DATA + DDRSS2_CTL_127_DATA + DDRSS2_CTL_128_DATA + DDRSS2_CTL_129_DATA + DDRSS2_CTL_130_DATA + DDRSS2_CTL_131_DATA + DDRSS2_CTL_132_DATA + DDRSS2_CTL_133_DATA + DDRSS2_CTL_134_DATA + DDRSS2_CTL_135_DATA + DDRSS2_CTL_136_DATA + DDRSS2_CTL_137_DATA + DDRSS2_CTL_138_DATA + DDRSS2_CTL_139_DATA + DDRSS2_CTL_140_DATA + DDRSS2_CTL_141_DATA + DDRSS2_CTL_142_DATA + DDRSS2_CTL_143_DATA + DDRSS2_CTL_144_DATA + DDRSS2_CTL_145_DATA + DDRSS2_CTL_146_DATA + DDRSS2_CTL_147_DATA + DDRSS2_CTL_148_DATA + DDRSS2_CTL_149_DATA + DDRSS2_CTL_150_DATA + DDRSS2_CTL_151_DATA + DDRSS2_CTL_152_DATA + DDRSS2_CTL_153_DATA + DDRSS2_CTL_154_DATA + DDRSS2_CTL_155_DATA + DDRSS2_CTL_156_DATA + DDRSS2_CTL_157_DATA + DDRSS2_CTL_158_DATA + DDRSS2_CTL_159_DATA + DDRSS2_CTL_160_DATA + DDRSS2_CTL_161_DATA + DDRSS2_CTL_162_DATA + DDRSS2_CTL_163_DATA + DDRSS2_CTL_164_DATA + DDRSS2_CTL_165_DATA + DDRSS2_CTL_166_DATA + DDRSS2_CTL_167_DATA + DDRSS2_CTL_168_DATA + DDRSS2_CTL_169_DATA + DDRSS2_CTL_170_DATA + DDRSS2_CTL_171_DATA + DDRSS2_CTL_172_DATA + DDRSS2_CTL_173_DATA + DDRSS2_CTL_174_DATA + DDRSS2_CTL_175_DATA + DDRSS2_CTL_176_DATA + DDRSS2_CTL_177_DATA + DDRSS2_CTL_178_DATA + DDRSS2_CTL_179_DATA + DDRSS2_CTL_180_DATA + DDRSS2_CTL_181_DATA + DDRSS2_CTL_182_DATA + DDRSS2_CTL_183_DATA + DDRSS2_CTL_184_DATA + DDRSS2_CTL_185_DATA + DDRSS2_CTL_186_DATA + DDRSS2_CTL_187_DATA + DDRSS2_CTL_188_DATA + DDRSS2_CTL_189_DATA + DDRSS2_CTL_190_DATA + DDRSS2_CTL_191_DATA + DDRSS2_CTL_192_DATA + DDRSS2_CTL_193_DATA + DDRSS2_CTL_194_DATA + DDRSS2_CTL_195_DATA + DDRSS2_CTL_196_DATA + DDRSS2_CTL_197_DATA + DDRSS2_CTL_198_DATA + DDRSS2_CTL_199_DATA + DDRSS2_CTL_200_DATA + DDRSS2_CTL_201_DATA + DDRSS2_CTL_202_DATA + DDRSS2_CTL_203_DATA + DDRSS2_CTL_204_DATA + DDRSS2_CTL_205_DATA + DDRSS2_CTL_206_DATA + DDRSS2_CTL_207_DATA + DDRSS2_CTL_208_DATA + DDRSS2_CTL_209_DATA + DDRSS2_CTL_210_DATA + DDRSS2_CTL_211_DATA + DDRSS2_CTL_212_DATA + DDRSS2_CTL_213_DATA + DDRSS2_CTL_214_DATA + DDRSS2_CTL_215_DATA + DDRSS2_CTL_216_DATA + DDRSS2_CTL_217_DATA + DDRSS2_CTL_218_DATA + DDRSS2_CTL_219_DATA + DDRSS2_CTL_220_DATA + DDRSS2_CTL_221_DATA + DDRSS2_CTL_222_DATA + DDRSS2_CTL_223_DATA + DDRSS2_CTL_224_DATA + DDRSS2_CTL_225_DATA + DDRSS2_CTL_226_DATA + DDRSS2_CTL_227_DATA + DDRSS2_CTL_228_DATA + DDRSS2_CTL_229_DATA + DDRSS2_CTL_230_DATA + DDRSS2_CTL_231_DATA + DDRSS2_CTL_232_DATA + DDRSS2_CTL_233_DATA + DDRSS2_CTL_234_DATA + DDRSS2_CTL_235_DATA + DDRSS2_CTL_236_DATA + DDRSS2_CTL_237_DATA + DDRSS2_CTL_238_DATA + DDRSS2_CTL_239_DATA + DDRSS2_CTL_240_DATA + DDRSS2_CTL_241_DATA + DDRSS2_CTL_242_DATA + DDRSS2_CTL_243_DATA + DDRSS2_CTL_244_DATA + DDRSS2_CTL_245_DATA + DDRSS2_CTL_246_DATA + DDRSS2_CTL_247_DATA + DDRSS2_CTL_248_DATA + DDRSS2_CTL_249_DATA + DDRSS2_CTL_250_DATA + DDRSS2_CTL_251_DATA + DDRSS2_CTL_252_DATA + DDRSS2_CTL_253_DATA + DDRSS2_CTL_254_DATA + DDRSS2_CTL_255_DATA + DDRSS2_CTL_256_DATA + DDRSS2_CTL_257_DATA + DDRSS2_CTL_258_DATA + DDRSS2_CTL_259_DATA + DDRSS2_CTL_260_DATA + DDRSS2_CTL_261_DATA + DDRSS2_CTL_262_DATA + DDRSS2_CTL_263_DATA + DDRSS2_CTL_264_DATA + DDRSS2_CTL_265_DATA + DDRSS2_CTL_266_DATA + DDRSS2_CTL_267_DATA + DDRSS2_CTL_268_DATA + DDRSS2_CTL_269_DATA + DDRSS2_CTL_270_DATA + DDRSS2_CTL_271_DATA + DDRSS2_CTL_272_DATA + DDRSS2_CTL_273_DATA + DDRSS2_CTL_274_DATA + DDRSS2_CTL_275_DATA + DDRSS2_CTL_276_DATA + DDRSS2_CTL_277_DATA + DDRSS2_CTL_278_DATA + DDRSS2_CTL_279_DATA + DDRSS2_CTL_280_DATA + DDRSS2_CTL_281_DATA + DDRSS2_CTL_282_DATA + DDRSS2_CTL_283_DATA + DDRSS2_CTL_284_DATA + DDRSS2_CTL_285_DATA + DDRSS2_CTL_286_DATA + DDRSS2_CTL_287_DATA + DDRSS2_CTL_288_DATA + DDRSS2_CTL_289_DATA + DDRSS2_CTL_290_DATA + DDRSS2_CTL_291_DATA + DDRSS2_CTL_292_DATA + DDRSS2_CTL_293_DATA + DDRSS2_CTL_294_DATA + DDRSS2_CTL_295_DATA + DDRSS2_CTL_296_DATA + DDRSS2_CTL_297_DATA + DDRSS2_CTL_298_DATA + DDRSS2_CTL_299_DATA + DDRSS2_CTL_300_DATA + DDRSS2_CTL_301_DATA + DDRSS2_CTL_302_DATA + DDRSS2_CTL_303_DATA + DDRSS2_CTL_304_DATA + DDRSS2_CTL_305_DATA + DDRSS2_CTL_306_DATA + DDRSS2_CTL_307_DATA + DDRSS2_CTL_308_DATA + DDRSS2_CTL_309_DATA + DDRSS2_CTL_310_DATA + DDRSS2_CTL_311_DATA + DDRSS2_CTL_312_DATA + DDRSS2_CTL_313_DATA + DDRSS2_CTL_314_DATA + DDRSS2_CTL_315_DATA + DDRSS2_CTL_316_DATA + DDRSS2_CTL_317_DATA + DDRSS2_CTL_318_DATA + DDRSS2_CTL_319_DATA + DDRSS2_CTL_320_DATA + DDRSS2_CTL_321_DATA + DDRSS2_CTL_322_DATA + DDRSS2_CTL_323_DATA + DDRSS2_CTL_324_DATA + DDRSS2_CTL_325_DATA + DDRSS2_CTL_326_DATA + DDRSS2_CTL_327_DATA + DDRSS2_CTL_328_DATA + DDRSS2_CTL_329_DATA + DDRSS2_CTL_330_DATA + DDRSS2_CTL_331_DATA + DDRSS2_CTL_332_DATA + DDRSS2_CTL_333_DATA + DDRSS2_CTL_334_DATA + DDRSS2_CTL_335_DATA + DDRSS2_CTL_336_DATA + DDRSS2_CTL_337_DATA + DDRSS2_CTL_338_DATA + DDRSS2_CTL_339_DATA + DDRSS2_CTL_340_DATA + DDRSS2_CTL_341_DATA + DDRSS2_CTL_342_DATA + DDRSS2_CTL_343_DATA + DDRSS2_CTL_344_DATA + DDRSS2_CTL_345_DATA + DDRSS2_CTL_346_DATA + DDRSS2_CTL_347_DATA + DDRSS2_CTL_348_DATA + DDRSS2_CTL_349_DATA + DDRSS2_CTL_350_DATA + DDRSS2_CTL_351_DATA + DDRSS2_CTL_352_DATA + DDRSS2_CTL_353_DATA + DDRSS2_CTL_354_DATA + DDRSS2_CTL_355_DATA + DDRSS2_CTL_356_DATA + DDRSS2_CTL_357_DATA + DDRSS2_CTL_358_DATA + DDRSS2_CTL_359_DATA + DDRSS2_CTL_360_DATA + DDRSS2_CTL_361_DATA + DDRSS2_CTL_362_DATA + DDRSS2_CTL_363_DATA + DDRSS2_CTL_364_DATA + DDRSS2_CTL_365_DATA + DDRSS2_CTL_366_DATA + DDRSS2_CTL_367_DATA + DDRSS2_CTL_368_DATA + DDRSS2_CTL_369_DATA + DDRSS2_CTL_370_DATA + DDRSS2_CTL_371_DATA + DDRSS2_CTL_372_DATA + DDRSS2_CTL_373_DATA + DDRSS2_CTL_374_DATA + DDRSS2_CTL_375_DATA + DDRSS2_CTL_376_DATA + DDRSS2_CTL_377_DATA + DDRSS2_CTL_378_DATA + DDRSS2_CTL_379_DATA + DDRSS2_CTL_380_DATA + DDRSS2_CTL_381_DATA + DDRSS2_CTL_382_DATA + DDRSS2_CTL_383_DATA + DDRSS2_CTL_384_DATA + DDRSS2_CTL_385_DATA + DDRSS2_CTL_386_DATA + DDRSS2_CTL_387_DATA + DDRSS2_CTL_388_DATA + DDRSS2_CTL_389_DATA + DDRSS2_CTL_390_DATA + DDRSS2_CTL_391_DATA + DDRSS2_CTL_392_DATA + DDRSS2_CTL_393_DATA + DDRSS2_CTL_394_DATA + DDRSS2_CTL_395_DATA + DDRSS2_CTL_396_DATA + DDRSS2_CTL_397_DATA + DDRSS2_CTL_398_DATA + DDRSS2_CTL_399_DATA + DDRSS2_CTL_400_DATA + DDRSS2_CTL_401_DATA + DDRSS2_CTL_402_DATA + DDRSS2_CTL_403_DATA + DDRSS2_CTL_404_DATA + DDRSS2_CTL_405_DATA + DDRSS2_CTL_406_DATA + DDRSS2_CTL_407_DATA + DDRSS2_CTL_408_DATA + DDRSS2_CTL_409_DATA + DDRSS2_CTL_410_DATA + DDRSS2_CTL_411_DATA + DDRSS2_CTL_412_DATA + DDRSS2_CTL_413_DATA + DDRSS2_CTL_414_DATA + DDRSS2_CTL_415_DATA + DDRSS2_CTL_416_DATA + DDRSS2_CTL_417_DATA + DDRSS2_CTL_418_DATA + DDRSS2_CTL_419_DATA + DDRSS2_CTL_420_DATA + DDRSS2_CTL_421_DATA + DDRSS2_CTL_422_DATA + DDRSS2_CTL_423_DATA + DDRSS2_CTL_424_DATA + DDRSS2_CTL_425_DATA + DDRSS2_CTL_426_DATA + DDRSS2_CTL_427_DATA + DDRSS2_CTL_428_DATA + DDRSS2_CTL_429_DATA + DDRSS2_CTL_430_DATA + DDRSS2_CTL_431_DATA + DDRSS2_CTL_432_DATA + DDRSS2_CTL_433_DATA + DDRSS2_CTL_434_DATA + DDRSS2_CTL_435_DATA + DDRSS2_CTL_436_DATA + DDRSS2_CTL_437_DATA + DDRSS2_CTL_438_DATA + DDRSS2_CTL_439_DATA + DDRSS2_CTL_440_DATA + DDRSS2_CTL_441_DATA + DDRSS2_CTL_442_DATA + DDRSS2_CTL_443_DATA + DDRSS2_CTL_444_DATA + DDRSS2_CTL_445_DATA + DDRSS2_CTL_446_DATA + DDRSS2_CTL_447_DATA + DDRSS2_CTL_448_DATA + DDRSS2_CTL_449_DATA + DDRSS2_CTL_450_DATA + DDRSS2_CTL_451_DATA + DDRSS2_CTL_452_DATA + DDRSS2_CTL_453_DATA + DDRSS2_CTL_454_DATA + DDRSS2_CTL_455_DATA + DDRSS2_CTL_456_DATA + DDRSS2_CTL_457_DATA + DDRSS2_CTL_458_DATA + >; - bootph-pre-ram; + ti,pi-data = < + DDRSS2_PI_00_DATA + DDRSS2_PI_01_DATA + DDRSS2_PI_02_DATA + DDRSS2_PI_03_DATA + DDRSS2_PI_04_DATA + DDRSS2_PI_05_DATA + DDRSS2_PI_06_DATA + DDRSS2_PI_07_DATA + DDRSS2_PI_08_DATA + DDRSS2_PI_09_DATA + DDRSS2_PI_10_DATA + DDRSS2_PI_11_DATA + DDRSS2_PI_12_DATA + DDRSS2_PI_13_DATA + DDRSS2_PI_14_DATA + DDRSS2_PI_15_DATA + DDRSS2_PI_16_DATA + DDRSS2_PI_17_DATA + DDRSS2_PI_18_DATA + DDRSS2_PI_19_DATA + DDRSS2_PI_20_DATA + DDRSS2_PI_21_DATA + DDRSS2_PI_22_DATA + DDRSS2_PI_23_DATA + DDRSS2_PI_24_DATA + DDRSS2_PI_25_DATA + DDRSS2_PI_26_DATA + DDRSS2_PI_27_DATA + DDRSS2_PI_28_DATA + DDRSS2_PI_29_DATA + DDRSS2_PI_30_DATA + DDRSS2_PI_31_DATA + DDRSS2_PI_32_DATA + DDRSS2_PI_33_DATA + DDRSS2_PI_34_DATA + DDRSS2_PI_35_DATA + DDRSS2_PI_36_DATA + DDRSS2_PI_37_DATA + DDRSS2_PI_38_DATA + DDRSS2_PI_39_DATA + DDRSS2_PI_40_DATA + DDRSS2_PI_41_DATA + DDRSS2_PI_42_DATA + DDRSS2_PI_43_DATA + DDRSS2_PI_44_DATA + DDRSS2_PI_45_DATA + DDRSS2_PI_46_DATA + DDRSS2_PI_47_DATA + DDRSS2_PI_48_DATA + DDRSS2_PI_49_DATA + DDRSS2_PI_50_DATA + DDRSS2_PI_51_DATA + DDRSS2_PI_52_DATA + DDRSS2_PI_53_DATA + DDRSS2_PI_54_DATA + DDRSS2_PI_55_DATA + DDRSS2_PI_56_DATA + DDRSS2_PI_57_DATA + DDRSS2_PI_58_DATA + DDRSS2_PI_59_DATA + DDRSS2_PI_60_DATA + DDRSS2_PI_61_DATA + DDRSS2_PI_62_DATA + DDRSS2_PI_63_DATA + DDRSS2_PI_64_DATA + DDRSS2_PI_65_DATA + DDRSS2_PI_66_DATA + DDRSS2_PI_67_DATA + DDRSS2_PI_68_DATA + DDRSS2_PI_69_DATA + DDRSS2_PI_70_DATA + DDRSS2_PI_71_DATA + DDRSS2_PI_72_DATA + DDRSS2_PI_73_DATA + DDRSS2_PI_74_DATA + DDRSS2_PI_75_DATA + DDRSS2_PI_76_DATA + DDRSS2_PI_77_DATA + DDRSS2_PI_78_DATA + DDRSS2_PI_79_DATA + DDRSS2_PI_80_DATA + DDRSS2_PI_81_DATA + DDRSS2_PI_82_DATA + DDRSS2_PI_83_DATA + DDRSS2_PI_84_DATA + DDRSS2_PI_85_DATA + DDRSS2_PI_86_DATA + DDRSS2_PI_87_DATA + DDRSS2_PI_88_DATA + DDRSS2_PI_89_DATA + DDRSS2_PI_90_DATA + DDRSS2_PI_91_DATA + DDRSS2_PI_92_DATA + DDRSS2_PI_93_DATA + DDRSS2_PI_94_DATA + DDRSS2_PI_95_DATA + DDRSS2_PI_96_DATA + DDRSS2_PI_97_DATA + DDRSS2_PI_98_DATA + DDRSS2_PI_99_DATA + DDRSS2_PI_100_DATA + DDRSS2_PI_101_DATA + DDRSS2_PI_102_DATA + DDRSS2_PI_103_DATA + DDRSS2_PI_104_DATA + DDRSS2_PI_105_DATA + DDRSS2_PI_106_DATA + DDRSS2_PI_107_DATA + DDRSS2_PI_108_DATA + DDRSS2_PI_109_DATA + DDRSS2_PI_110_DATA + DDRSS2_PI_111_DATA + DDRSS2_PI_112_DATA + DDRSS2_PI_113_DATA + DDRSS2_PI_114_DATA + DDRSS2_PI_115_DATA + DDRSS2_PI_116_DATA + DDRSS2_PI_117_DATA + DDRSS2_PI_118_DATA + DDRSS2_PI_119_DATA + DDRSS2_PI_120_DATA + DDRSS2_PI_121_DATA + DDRSS2_PI_122_DATA + DDRSS2_PI_123_DATA + DDRSS2_PI_124_DATA + DDRSS2_PI_125_DATA + DDRSS2_PI_126_DATA + DDRSS2_PI_127_DATA + DDRSS2_PI_128_DATA + DDRSS2_PI_129_DATA + DDRSS2_PI_130_DATA + DDRSS2_PI_131_DATA + DDRSS2_PI_132_DATA + DDRSS2_PI_133_DATA + DDRSS2_PI_134_DATA + DDRSS2_PI_135_DATA + DDRSS2_PI_136_DATA + DDRSS2_PI_137_DATA + DDRSS2_PI_138_DATA + DDRSS2_PI_139_DATA + DDRSS2_PI_140_DATA + DDRSS2_PI_141_DATA + DDRSS2_PI_142_DATA + DDRSS2_PI_143_DATA + DDRSS2_PI_144_DATA + DDRSS2_PI_145_DATA + DDRSS2_PI_146_DATA + DDRSS2_PI_147_DATA + DDRSS2_PI_148_DATA + DDRSS2_PI_149_DATA + DDRSS2_PI_150_DATA + DDRSS2_PI_151_DATA + DDRSS2_PI_152_DATA + DDRSS2_PI_153_DATA + DDRSS2_PI_154_DATA + DDRSS2_PI_155_DATA + DDRSS2_PI_156_DATA + DDRSS2_PI_157_DATA + DDRSS2_PI_158_DATA + DDRSS2_PI_159_DATA + DDRSS2_PI_160_DATA + DDRSS2_PI_161_DATA + DDRSS2_PI_162_DATA + DDRSS2_PI_163_DATA + DDRSS2_PI_164_DATA + DDRSS2_PI_165_DATA + DDRSS2_PI_166_DATA + DDRSS2_PI_167_DATA + DDRSS2_PI_168_DATA + DDRSS2_PI_169_DATA + DDRSS2_PI_170_DATA + DDRSS2_PI_171_DATA + DDRSS2_PI_172_DATA + DDRSS2_PI_173_DATA + DDRSS2_PI_174_DATA + DDRSS2_PI_175_DATA + DDRSS2_PI_176_DATA + DDRSS2_PI_177_DATA + DDRSS2_PI_178_DATA + DDRSS2_PI_179_DATA + DDRSS2_PI_180_DATA + DDRSS2_PI_181_DATA + DDRSS2_PI_182_DATA + DDRSS2_PI_183_DATA + DDRSS2_PI_184_DATA + DDRSS2_PI_185_DATA + DDRSS2_PI_186_DATA + DDRSS2_PI_187_DATA + DDRSS2_PI_188_DATA + DDRSS2_PI_189_DATA + DDRSS2_PI_190_DATA + DDRSS2_PI_191_DATA + DDRSS2_PI_192_DATA + DDRSS2_PI_193_DATA + DDRSS2_PI_194_DATA + DDRSS2_PI_195_DATA + DDRSS2_PI_196_DATA + DDRSS2_PI_197_DATA + DDRSS2_PI_198_DATA + DDRSS2_PI_199_DATA + DDRSS2_PI_200_DATA + DDRSS2_PI_201_DATA + DDRSS2_PI_202_DATA + DDRSS2_PI_203_DATA + DDRSS2_PI_204_DATA + DDRSS2_PI_205_DATA + DDRSS2_PI_206_DATA + DDRSS2_PI_207_DATA + DDRSS2_PI_208_DATA + DDRSS2_PI_209_DATA + DDRSS2_PI_210_DATA + DDRSS2_PI_211_DATA + DDRSS2_PI_212_DATA + DDRSS2_PI_213_DATA + DDRSS2_PI_214_DATA + DDRSS2_PI_215_DATA + DDRSS2_PI_216_DATA + DDRSS2_PI_217_DATA + DDRSS2_PI_218_DATA + DDRSS2_PI_219_DATA + DDRSS2_PI_220_DATA + DDRSS2_PI_221_DATA + DDRSS2_PI_222_DATA + DDRSS2_PI_223_DATA + DDRSS2_PI_224_DATA + DDRSS2_PI_225_DATA + DDRSS2_PI_226_DATA + DDRSS2_PI_227_DATA + DDRSS2_PI_228_DATA + DDRSS2_PI_229_DATA + DDRSS2_PI_230_DATA + DDRSS2_PI_231_DATA + DDRSS2_PI_232_DATA + DDRSS2_PI_233_DATA + DDRSS2_PI_234_DATA + DDRSS2_PI_235_DATA + DDRSS2_PI_236_DATA + DDRSS2_PI_237_DATA + DDRSS2_PI_238_DATA + DDRSS2_PI_239_DATA + DDRSS2_PI_240_DATA + DDRSS2_PI_241_DATA + DDRSS2_PI_242_DATA + DDRSS2_PI_243_DATA + DDRSS2_PI_244_DATA + DDRSS2_PI_245_DATA + DDRSS2_PI_246_DATA + DDRSS2_PI_247_DATA + DDRSS2_PI_248_DATA + DDRSS2_PI_249_DATA + DDRSS2_PI_250_DATA + DDRSS2_PI_251_DATA + DDRSS2_PI_252_DATA + DDRSS2_PI_253_DATA + DDRSS2_PI_254_DATA + DDRSS2_PI_255_DATA + DDRSS2_PI_256_DATA + DDRSS2_PI_257_DATA + DDRSS2_PI_258_DATA + DDRSS2_PI_259_DATA + DDRSS2_PI_260_DATA + DDRSS2_PI_261_DATA + DDRSS2_PI_262_DATA + DDRSS2_PI_263_DATA + DDRSS2_PI_264_DATA + DDRSS2_PI_265_DATA + DDRSS2_PI_266_DATA + DDRSS2_PI_267_DATA + DDRSS2_PI_268_DATA + DDRSS2_PI_269_DATA + DDRSS2_PI_270_DATA + DDRSS2_PI_271_DATA + DDRSS2_PI_272_DATA + DDRSS2_PI_273_DATA + DDRSS2_PI_274_DATA + DDRSS2_PI_275_DATA + DDRSS2_PI_276_DATA + DDRSS2_PI_277_DATA + DDRSS2_PI_278_DATA + DDRSS2_PI_279_DATA + DDRSS2_PI_280_DATA + DDRSS2_PI_281_DATA + DDRSS2_PI_282_DATA + DDRSS2_PI_283_DATA + DDRSS2_PI_284_DATA + DDRSS2_PI_285_DATA + DDRSS2_PI_286_DATA + DDRSS2_PI_287_DATA + DDRSS2_PI_288_DATA + DDRSS2_PI_289_DATA + DDRSS2_PI_290_DATA + DDRSS2_PI_291_DATA + DDRSS2_PI_292_DATA + DDRSS2_PI_293_DATA + DDRSS2_PI_294_DATA + DDRSS2_PI_295_DATA + DDRSS2_PI_296_DATA + DDRSS2_PI_297_DATA + DDRSS2_PI_298_DATA + DDRSS2_PI_299_DATA + >; - ti,ctl-data = < - DDRSS0_CTL_00_DATA - DDRSS0_CTL_01_DATA - DDRSS0_CTL_02_DATA - DDRSS0_CTL_03_DATA - DDRSS0_CTL_04_DATA - DDRSS0_CTL_05_DATA - DDRSS0_CTL_06_DATA - DDRSS0_CTL_07_DATA - DDRSS0_CTL_08_DATA - DDRSS0_CTL_09_DATA - DDRSS0_CTL_10_DATA - DDRSS0_CTL_11_DATA - DDRSS0_CTL_12_DATA - DDRSS0_CTL_13_DATA - DDRSS0_CTL_14_DATA - DDRSS0_CTL_15_DATA - DDRSS0_CTL_16_DATA - DDRSS0_CTL_17_DATA - DDRSS0_CTL_18_DATA - DDRSS0_CTL_19_DATA - DDRSS0_CTL_20_DATA - DDRSS0_CTL_21_DATA - DDRSS0_CTL_22_DATA - DDRSS0_CTL_23_DATA - DDRSS0_CTL_24_DATA - DDRSS0_CTL_25_DATA - DDRSS0_CTL_26_DATA - DDRSS0_CTL_27_DATA - DDRSS0_CTL_28_DATA - DDRSS0_CTL_29_DATA - DDRSS0_CTL_30_DATA - DDRSS0_CTL_31_DATA - DDRSS0_CTL_32_DATA - DDRSS0_CTL_33_DATA - DDRSS0_CTL_34_DATA - DDRSS0_CTL_35_DATA - DDRSS0_CTL_36_DATA - DDRSS0_CTL_37_DATA - DDRSS0_CTL_38_DATA - DDRSS0_CTL_39_DATA - DDRSS0_CTL_40_DATA - DDRSS0_CTL_41_DATA - DDRSS0_CTL_42_DATA - DDRSS0_CTL_43_DATA - DDRSS0_CTL_44_DATA - DDRSS0_CTL_45_DATA - DDRSS0_CTL_46_DATA - DDRSS0_CTL_47_DATA - DDRSS0_CTL_48_DATA - DDRSS0_CTL_49_DATA - DDRSS0_CTL_50_DATA - DDRSS0_CTL_51_DATA - DDRSS0_CTL_52_DATA - DDRSS0_CTL_53_DATA - DDRSS0_CTL_54_DATA - DDRSS0_CTL_55_DATA - DDRSS0_CTL_56_DATA - DDRSS0_CTL_57_DATA - DDRSS0_CTL_58_DATA - DDRSS0_CTL_59_DATA - DDRSS0_CTL_60_DATA - DDRSS0_CTL_61_DATA - DDRSS0_CTL_62_DATA - DDRSS0_CTL_63_DATA - DDRSS0_CTL_64_DATA - DDRSS0_CTL_65_DATA - DDRSS0_CTL_66_DATA - DDRSS0_CTL_67_DATA - DDRSS0_CTL_68_DATA - DDRSS0_CTL_69_DATA - DDRSS0_CTL_70_DATA - DDRSS0_CTL_71_DATA - DDRSS0_CTL_72_DATA - DDRSS0_CTL_73_DATA - DDRSS0_CTL_74_DATA - DDRSS0_CTL_75_DATA - DDRSS0_CTL_76_DATA - DDRSS0_CTL_77_DATA - DDRSS0_CTL_78_DATA - DDRSS0_CTL_79_DATA - DDRSS0_CTL_80_DATA - DDRSS0_CTL_81_DATA - DDRSS0_CTL_82_DATA - DDRSS0_CTL_83_DATA - DDRSS0_CTL_84_DATA - DDRSS0_CTL_85_DATA - DDRSS0_CTL_86_DATA - DDRSS0_CTL_87_DATA - DDRSS0_CTL_88_DATA - DDRSS0_CTL_89_DATA - DDRSS0_CTL_90_DATA - DDRSS0_CTL_91_DATA - DDRSS0_CTL_92_DATA - DDRSS0_CTL_93_DATA - DDRSS0_CTL_94_DATA - DDRSS0_CTL_95_DATA - DDRSS0_CTL_96_DATA - DDRSS0_CTL_97_DATA - DDRSS0_CTL_98_DATA - DDRSS0_CTL_99_DATA - DDRSS0_CTL_100_DATA - DDRSS0_CTL_101_DATA - DDRSS0_CTL_102_DATA - DDRSS0_CTL_103_DATA - DDRSS0_CTL_104_DATA - DDRSS0_CTL_105_DATA - DDRSS0_CTL_106_DATA - DDRSS0_CTL_107_DATA - DDRSS0_CTL_108_DATA - DDRSS0_CTL_109_DATA - DDRSS0_CTL_110_DATA - DDRSS0_CTL_111_DATA - DDRSS0_CTL_112_DATA - DDRSS0_CTL_113_DATA - DDRSS0_CTL_114_DATA - DDRSS0_CTL_115_DATA - DDRSS0_CTL_116_DATA - DDRSS0_CTL_117_DATA - DDRSS0_CTL_118_DATA - DDRSS0_CTL_119_DATA - DDRSS0_CTL_120_DATA - DDRSS0_CTL_121_DATA - DDRSS0_CTL_122_DATA - DDRSS0_CTL_123_DATA - DDRSS0_CTL_124_DATA - DDRSS0_CTL_125_DATA - DDRSS0_CTL_126_DATA - DDRSS0_CTL_127_DATA - DDRSS0_CTL_128_DATA - DDRSS0_CTL_129_DATA - DDRSS0_CTL_130_DATA - DDRSS0_CTL_131_DATA - DDRSS0_CTL_132_DATA - DDRSS0_CTL_133_DATA - DDRSS0_CTL_134_DATA - DDRSS0_CTL_135_DATA - DDRSS0_CTL_136_DATA - DDRSS0_CTL_137_DATA - DDRSS0_CTL_138_DATA - DDRSS0_CTL_139_DATA - DDRSS0_CTL_140_DATA - DDRSS0_CTL_141_DATA - DDRSS0_CTL_142_DATA - DDRSS0_CTL_143_DATA - DDRSS0_CTL_144_DATA - DDRSS0_CTL_145_DATA - DDRSS0_CTL_146_DATA - DDRSS0_CTL_147_DATA - DDRSS0_CTL_148_DATA - DDRSS0_CTL_149_DATA - DDRSS0_CTL_150_DATA - DDRSS0_CTL_151_DATA - DDRSS0_CTL_152_DATA - DDRSS0_CTL_153_DATA - DDRSS0_CTL_154_DATA - DDRSS0_CTL_155_DATA - DDRSS0_CTL_156_DATA - DDRSS0_CTL_157_DATA - DDRSS0_CTL_158_DATA - DDRSS0_CTL_159_DATA - DDRSS0_CTL_160_DATA - DDRSS0_CTL_161_DATA - DDRSS0_CTL_162_DATA - DDRSS0_CTL_163_DATA - DDRSS0_CTL_164_DATA - DDRSS0_CTL_165_DATA - DDRSS0_CTL_166_DATA - DDRSS0_CTL_167_DATA - DDRSS0_CTL_168_DATA - DDRSS0_CTL_169_DATA - DDRSS0_CTL_170_DATA - DDRSS0_CTL_171_DATA - DDRSS0_CTL_172_DATA - DDRSS0_CTL_173_DATA - DDRSS0_CTL_174_DATA - DDRSS0_CTL_175_DATA - DDRSS0_CTL_176_DATA - DDRSS0_CTL_177_DATA - DDRSS0_CTL_178_DATA - DDRSS0_CTL_179_DATA - DDRSS0_CTL_180_DATA - DDRSS0_CTL_181_DATA - DDRSS0_CTL_182_DATA - DDRSS0_CTL_183_DATA - DDRSS0_CTL_184_DATA - DDRSS0_CTL_185_DATA - DDRSS0_CTL_186_DATA - DDRSS0_CTL_187_DATA - DDRSS0_CTL_188_DATA - DDRSS0_CTL_189_DATA - DDRSS0_CTL_190_DATA - DDRSS0_CTL_191_DATA - DDRSS0_CTL_192_DATA - DDRSS0_CTL_193_DATA - DDRSS0_CTL_194_DATA - DDRSS0_CTL_195_DATA - DDRSS0_CTL_196_DATA - DDRSS0_CTL_197_DATA - DDRSS0_CTL_198_DATA - DDRSS0_CTL_199_DATA - DDRSS0_CTL_200_DATA - DDRSS0_CTL_201_DATA - DDRSS0_CTL_202_DATA - DDRSS0_CTL_203_DATA - DDRSS0_CTL_204_DATA - DDRSS0_CTL_205_DATA - DDRSS0_CTL_206_DATA - DDRSS0_CTL_207_DATA - DDRSS0_CTL_208_DATA - DDRSS0_CTL_209_DATA - DDRSS0_CTL_210_DATA - DDRSS0_CTL_211_DATA - DDRSS0_CTL_212_DATA - DDRSS0_CTL_213_DATA - DDRSS0_CTL_214_DATA - DDRSS0_CTL_215_DATA - DDRSS0_CTL_216_DATA - DDRSS0_CTL_217_DATA - DDRSS0_CTL_218_DATA - DDRSS0_CTL_219_DATA - DDRSS0_CTL_220_DATA - DDRSS0_CTL_221_DATA - DDRSS0_CTL_222_DATA - DDRSS0_CTL_223_DATA - DDRSS0_CTL_224_DATA - DDRSS0_CTL_225_DATA - DDRSS0_CTL_226_DATA - DDRSS0_CTL_227_DATA - DDRSS0_CTL_228_DATA - DDRSS0_CTL_229_DATA - DDRSS0_CTL_230_DATA - DDRSS0_CTL_231_DATA - DDRSS0_CTL_232_DATA - DDRSS0_CTL_233_DATA - DDRSS0_CTL_234_DATA - DDRSS0_CTL_235_DATA - DDRSS0_CTL_236_DATA - DDRSS0_CTL_237_DATA - DDRSS0_CTL_238_DATA - DDRSS0_CTL_239_DATA - DDRSS0_CTL_240_DATA - DDRSS0_CTL_241_DATA - DDRSS0_CTL_242_DATA - DDRSS0_CTL_243_DATA - DDRSS0_CTL_244_DATA - DDRSS0_CTL_245_DATA - DDRSS0_CTL_246_DATA - DDRSS0_CTL_247_DATA - DDRSS0_CTL_248_DATA - DDRSS0_CTL_249_DATA - DDRSS0_CTL_250_DATA - DDRSS0_CTL_251_DATA - DDRSS0_CTL_252_DATA - DDRSS0_CTL_253_DATA - DDRSS0_CTL_254_DATA - DDRSS0_CTL_255_DATA - DDRSS0_CTL_256_DATA - DDRSS0_CTL_257_DATA - DDRSS0_CTL_258_DATA - DDRSS0_CTL_259_DATA - DDRSS0_CTL_260_DATA - DDRSS0_CTL_261_DATA - DDRSS0_CTL_262_DATA - DDRSS0_CTL_263_DATA - DDRSS0_CTL_264_DATA - DDRSS0_CTL_265_DATA - DDRSS0_CTL_266_DATA - DDRSS0_CTL_267_DATA - DDRSS0_CTL_268_DATA - DDRSS0_CTL_269_DATA - DDRSS0_CTL_270_DATA - DDRSS0_CTL_271_DATA - DDRSS0_CTL_272_DATA - DDRSS0_CTL_273_DATA - DDRSS0_CTL_274_DATA - DDRSS0_CTL_275_DATA - DDRSS0_CTL_276_DATA - DDRSS0_CTL_277_DATA - DDRSS0_CTL_278_DATA - DDRSS0_CTL_279_DATA - DDRSS0_CTL_280_DATA - DDRSS0_CTL_281_DATA - DDRSS0_CTL_282_DATA - DDRSS0_CTL_283_DATA - DDRSS0_CTL_284_DATA - DDRSS0_CTL_285_DATA - DDRSS0_CTL_286_DATA - DDRSS0_CTL_287_DATA - DDRSS0_CTL_288_DATA - DDRSS0_CTL_289_DATA - DDRSS0_CTL_290_DATA - DDRSS0_CTL_291_DATA - DDRSS0_CTL_292_DATA - DDRSS0_CTL_293_DATA - DDRSS0_CTL_294_DATA - DDRSS0_CTL_295_DATA - DDRSS0_CTL_296_DATA - DDRSS0_CTL_297_DATA - DDRSS0_CTL_298_DATA - DDRSS0_CTL_299_DATA - DDRSS0_CTL_300_DATA - DDRSS0_CTL_301_DATA - DDRSS0_CTL_302_DATA - DDRSS0_CTL_303_DATA - DDRSS0_CTL_304_DATA - DDRSS0_CTL_305_DATA - DDRSS0_CTL_306_DATA - DDRSS0_CTL_307_DATA - DDRSS0_CTL_308_DATA - DDRSS0_CTL_309_DATA - DDRSS0_CTL_310_DATA - DDRSS0_CTL_311_DATA - DDRSS0_CTL_312_DATA - DDRSS0_CTL_313_DATA - DDRSS0_CTL_314_DATA - DDRSS0_CTL_315_DATA - DDRSS0_CTL_316_DATA - DDRSS0_CTL_317_DATA - DDRSS0_CTL_318_DATA - DDRSS0_CTL_319_DATA - DDRSS0_CTL_320_DATA - DDRSS0_CTL_321_DATA - DDRSS0_CTL_322_DATA - DDRSS0_CTL_323_DATA - DDRSS0_CTL_324_DATA - DDRSS0_CTL_325_DATA - DDRSS0_CTL_326_DATA - DDRSS0_CTL_327_DATA - DDRSS0_CTL_328_DATA - DDRSS0_CTL_329_DATA - DDRSS0_CTL_330_DATA - DDRSS0_CTL_331_DATA - DDRSS0_CTL_332_DATA - DDRSS0_CTL_333_DATA - DDRSS0_CTL_334_DATA - DDRSS0_CTL_335_DATA - DDRSS0_CTL_336_DATA - DDRSS0_CTL_337_DATA - DDRSS0_CTL_338_DATA - DDRSS0_CTL_339_DATA - DDRSS0_CTL_340_DATA - DDRSS0_CTL_341_DATA - DDRSS0_CTL_342_DATA - DDRSS0_CTL_343_DATA - DDRSS0_CTL_344_DATA - DDRSS0_CTL_345_DATA - DDRSS0_CTL_346_DATA - DDRSS0_CTL_347_DATA - DDRSS0_CTL_348_DATA - DDRSS0_CTL_349_DATA - DDRSS0_CTL_350_DATA - DDRSS0_CTL_351_DATA - DDRSS0_CTL_352_DATA - DDRSS0_CTL_353_DATA - DDRSS0_CTL_354_DATA - DDRSS0_CTL_355_DATA - DDRSS0_CTL_356_DATA - DDRSS0_CTL_357_DATA - DDRSS0_CTL_358_DATA - DDRSS0_CTL_359_DATA - DDRSS0_CTL_360_DATA - DDRSS0_CTL_361_DATA - DDRSS0_CTL_362_DATA - DDRSS0_CTL_363_DATA - DDRSS0_CTL_364_DATA - DDRSS0_CTL_365_DATA - DDRSS0_CTL_366_DATA - DDRSS0_CTL_367_DATA - DDRSS0_CTL_368_DATA - DDRSS0_CTL_369_DATA - DDRSS0_CTL_370_DATA - DDRSS0_CTL_371_DATA - DDRSS0_CTL_372_DATA - DDRSS0_CTL_373_DATA - DDRSS0_CTL_374_DATA - DDRSS0_CTL_375_DATA - DDRSS0_CTL_376_DATA - DDRSS0_CTL_377_DATA - DDRSS0_CTL_378_DATA - DDRSS0_CTL_379_DATA - DDRSS0_CTL_380_DATA - DDRSS0_CTL_381_DATA - DDRSS0_CTL_382_DATA - DDRSS0_CTL_383_DATA - DDRSS0_CTL_384_DATA - DDRSS0_CTL_385_DATA - DDRSS0_CTL_386_DATA - DDRSS0_CTL_387_DATA - DDRSS0_CTL_388_DATA - DDRSS0_CTL_389_DATA - DDRSS0_CTL_390_DATA - DDRSS0_CTL_391_DATA - DDRSS0_CTL_392_DATA - DDRSS0_CTL_393_DATA - DDRSS0_CTL_394_DATA - DDRSS0_CTL_395_DATA - DDRSS0_CTL_396_DATA - DDRSS0_CTL_397_DATA - DDRSS0_CTL_398_DATA - DDRSS0_CTL_399_DATA - DDRSS0_CTL_400_DATA - DDRSS0_CTL_401_DATA - DDRSS0_CTL_402_DATA - DDRSS0_CTL_403_DATA - DDRSS0_CTL_404_DATA - DDRSS0_CTL_405_DATA - DDRSS0_CTL_406_DATA - DDRSS0_CTL_407_DATA - DDRSS0_CTL_408_DATA - DDRSS0_CTL_409_DATA - DDRSS0_CTL_410_DATA - DDRSS0_CTL_411_DATA - DDRSS0_CTL_412_DATA - DDRSS0_CTL_413_DATA - DDRSS0_CTL_414_DATA - DDRSS0_CTL_415_DATA - DDRSS0_CTL_416_DATA - DDRSS0_CTL_417_DATA - DDRSS0_CTL_418_DATA - DDRSS0_CTL_419_DATA - DDRSS0_CTL_420_DATA - DDRSS0_CTL_421_DATA - DDRSS0_CTL_422_DATA - DDRSS0_CTL_423_DATA - DDRSS0_CTL_424_DATA - DDRSS0_CTL_425_DATA - DDRSS0_CTL_426_DATA - DDRSS0_CTL_427_DATA - DDRSS0_CTL_428_DATA - DDRSS0_CTL_429_DATA - DDRSS0_CTL_430_DATA - DDRSS0_CTL_431_DATA - DDRSS0_CTL_432_DATA - DDRSS0_CTL_433_DATA - DDRSS0_CTL_434_DATA - DDRSS0_CTL_435_DATA - DDRSS0_CTL_436_DATA - DDRSS0_CTL_437_DATA - DDRSS0_CTL_438_DATA - DDRSS0_CTL_439_DATA - DDRSS0_CTL_440_DATA - DDRSS0_CTL_441_DATA - DDRSS0_CTL_442_DATA - DDRSS0_CTL_443_DATA - DDRSS0_CTL_444_DATA - DDRSS0_CTL_445_DATA - DDRSS0_CTL_446_DATA - DDRSS0_CTL_447_DATA - DDRSS0_CTL_448_DATA - DDRSS0_CTL_449_DATA - DDRSS0_CTL_450_DATA - DDRSS0_CTL_451_DATA - DDRSS0_CTL_452_DATA - DDRSS0_CTL_453_DATA - DDRSS0_CTL_454_DATA - DDRSS0_CTL_455_DATA - DDRSS0_CTL_456_DATA - DDRSS0_CTL_457_DATA - DDRSS0_CTL_458_DATA - >; - - ti,pi-data = < - DDRSS0_PI_00_DATA - DDRSS0_PI_01_DATA - DDRSS0_PI_02_DATA - DDRSS0_PI_03_DATA - DDRSS0_PI_04_DATA - DDRSS0_PI_05_DATA - DDRSS0_PI_06_DATA - DDRSS0_PI_07_DATA - DDRSS0_PI_08_DATA - DDRSS0_PI_09_DATA - DDRSS0_PI_10_DATA - DDRSS0_PI_11_DATA - DDRSS0_PI_12_DATA - DDRSS0_PI_13_DATA - DDRSS0_PI_14_DATA - DDRSS0_PI_15_DATA - DDRSS0_PI_16_DATA - DDRSS0_PI_17_DATA - DDRSS0_PI_18_DATA - DDRSS0_PI_19_DATA - DDRSS0_PI_20_DATA - DDRSS0_PI_21_DATA - DDRSS0_PI_22_DATA - DDRSS0_PI_23_DATA - DDRSS0_PI_24_DATA - DDRSS0_PI_25_DATA - DDRSS0_PI_26_DATA - DDRSS0_PI_27_DATA - DDRSS0_PI_28_DATA - DDRSS0_PI_29_DATA - DDRSS0_PI_30_DATA - DDRSS0_PI_31_DATA - DDRSS0_PI_32_DATA - DDRSS0_PI_33_DATA - DDRSS0_PI_34_DATA - DDRSS0_PI_35_DATA - DDRSS0_PI_36_DATA - DDRSS0_PI_37_DATA - DDRSS0_PI_38_DATA - DDRSS0_PI_39_DATA - DDRSS0_PI_40_DATA - DDRSS0_PI_41_DATA - DDRSS0_PI_42_DATA - DDRSS0_PI_43_DATA - DDRSS0_PI_44_DATA - DDRSS0_PI_45_DATA - DDRSS0_PI_46_DATA - DDRSS0_PI_47_DATA - DDRSS0_PI_48_DATA - DDRSS0_PI_49_DATA - DDRSS0_PI_50_DATA - DDRSS0_PI_51_DATA - DDRSS0_PI_52_DATA - DDRSS0_PI_53_DATA - DDRSS0_PI_54_DATA - DDRSS0_PI_55_DATA - DDRSS0_PI_56_DATA - DDRSS0_PI_57_DATA - DDRSS0_PI_58_DATA - DDRSS0_PI_59_DATA - DDRSS0_PI_60_DATA - DDRSS0_PI_61_DATA - DDRSS0_PI_62_DATA - DDRSS0_PI_63_DATA - DDRSS0_PI_64_DATA - DDRSS0_PI_65_DATA - DDRSS0_PI_66_DATA - DDRSS0_PI_67_DATA - DDRSS0_PI_68_DATA - DDRSS0_PI_69_DATA - DDRSS0_PI_70_DATA - DDRSS0_PI_71_DATA - DDRSS0_PI_72_DATA - DDRSS0_PI_73_DATA - DDRSS0_PI_74_DATA - DDRSS0_PI_75_DATA - DDRSS0_PI_76_DATA - DDRSS0_PI_77_DATA - DDRSS0_PI_78_DATA - DDRSS0_PI_79_DATA - DDRSS0_PI_80_DATA - DDRSS0_PI_81_DATA - DDRSS0_PI_82_DATA - DDRSS0_PI_83_DATA - DDRSS0_PI_84_DATA - DDRSS0_PI_85_DATA - DDRSS0_PI_86_DATA - DDRSS0_PI_87_DATA - DDRSS0_PI_88_DATA - DDRSS0_PI_89_DATA - DDRSS0_PI_90_DATA - DDRSS0_PI_91_DATA - DDRSS0_PI_92_DATA - DDRSS0_PI_93_DATA - DDRSS0_PI_94_DATA - DDRSS0_PI_95_DATA - DDRSS0_PI_96_DATA - DDRSS0_PI_97_DATA - DDRSS0_PI_98_DATA - DDRSS0_PI_99_DATA - DDRSS0_PI_100_DATA - DDRSS0_PI_101_DATA - DDRSS0_PI_102_DATA - DDRSS0_PI_103_DATA - DDRSS0_PI_104_DATA - DDRSS0_PI_105_DATA - DDRSS0_PI_106_DATA - DDRSS0_PI_107_DATA - DDRSS0_PI_108_DATA - DDRSS0_PI_109_DATA - DDRSS0_PI_110_DATA - DDRSS0_PI_111_DATA - DDRSS0_PI_112_DATA - DDRSS0_PI_113_DATA - DDRSS0_PI_114_DATA - DDRSS0_PI_115_DATA - DDRSS0_PI_116_DATA - DDRSS0_PI_117_DATA - DDRSS0_PI_118_DATA - DDRSS0_PI_119_DATA - DDRSS0_PI_120_DATA - DDRSS0_PI_121_DATA - DDRSS0_PI_122_DATA - DDRSS0_PI_123_DATA - DDRSS0_PI_124_DATA - DDRSS0_PI_125_DATA - DDRSS0_PI_126_DATA - DDRSS0_PI_127_DATA - DDRSS0_PI_128_DATA - DDRSS0_PI_129_DATA - DDRSS0_PI_130_DATA - DDRSS0_PI_131_DATA - DDRSS0_PI_132_DATA - DDRSS0_PI_133_DATA - DDRSS0_PI_134_DATA - DDRSS0_PI_135_DATA - DDRSS0_PI_136_DATA - DDRSS0_PI_137_DATA - DDRSS0_PI_138_DATA - DDRSS0_PI_139_DATA - DDRSS0_PI_140_DATA - DDRSS0_PI_141_DATA - DDRSS0_PI_142_DATA - DDRSS0_PI_143_DATA - DDRSS0_PI_144_DATA - DDRSS0_PI_145_DATA - DDRSS0_PI_146_DATA - DDRSS0_PI_147_DATA - DDRSS0_PI_148_DATA - DDRSS0_PI_149_DATA - DDRSS0_PI_150_DATA - DDRSS0_PI_151_DATA - DDRSS0_PI_152_DATA - DDRSS0_PI_153_DATA - DDRSS0_PI_154_DATA - DDRSS0_PI_155_DATA - DDRSS0_PI_156_DATA - DDRSS0_PI_157_DATA - DDRSS0_PI_158_DATA - DDRSS0_PI_159_DATA - DDRSS0_PI_160_DATA - DDRSS0_PI_161_DATA - DDRSS0_PI_162_DATA - DDRSS0_PI_163_DATA - DDRSS0_PI_164_DATA - DDRSS0_PI_165_DATA - DDRSS0_PI_166_DATA - DDRSS0_PI_167_DATA - DDRSS0_PI_168_DATA - DDRSS0_PI_169_DATA - DDRSS0_PI_170_DATA - DDRSS0_PI_171_DATA - DDRSS0_PI_172_DATA - DDRSS0_PI_173_DATA - DDRSS0_PI_174_DATA - DDRSS0_PI_175_DATA - DDRSS0_PI_176_DATA - DDRSS0_PI_177_DATA - DDRSS0_PI_178_DATA - DDRSS0_PI_179_DATA - DDRSS0_PI_180_DATA - DDRSS0_PI_181_DATA - DDRSS0_PI_182_DATA - DDRSS0_PI_183_DATA - DDRSS0_PI_184_DATA - DDRSS0_PI_185_DATA - DDRSS0_PI_186_DATA - DDRSS0_PI_187_DATA - DDRSS0_PI_188_DATA - DDRSS0_PI_189_DATA - DDRSS0_PI_190_DATA - DDRSS0_PI_191_DATA - DDRSS0_PI_192_DATA - DDRSS0_PI_193_DATA - DDRSS0_PI_194_DATA - DDRSS0_PI_195_DATA - DDRSS0_PI_196_DATA - DDRSS0_PI_197_DATA - DDRSS0_PI_198_DATA - DDRSS0_PI_199_DATA - DDRSS0_PI_200_DATA - DDRSS0_PI_201_DATA - DDRSS0_PI_202_DATA - DDRSS0_PI_203_DATA - DDRSS0_PI_204_DATA - DDRSS0_PI_205_DATA - DDRSS0_PI_206_DATA - DDRSS0_PI_207_DATA - DDRSS0_PI_208_DATA - DDRSS0_PI_209_DATA - DDRSS0_PI_210_DATA - DDRSS0_PI_211_DATA - DDRSS0_PI_212_DATA - DDRSS0_PI_213_DATA - DDRSS0_PI_214_DATA - DDRSS0_PI_215_DATA - DDRSS0_PI_216_DATA - DDRSS0_PI_217_DATA - DDRSS0_PI_218_DATA - DDRSS0_PI_219_DATA - DDRSS0_PI_220_DATA - DDRSS0_PI_221_DATA - DDRSS0_PI_222_DATA - DDRSS0_PI_223_DATA - DDRSS0_PI_224_DATA - DDRSS0_PI_225_DATA - DDRSS0_PI_226_DATA - DDRSS0_PI_227_DATA - DDRSS0_PI_228_DATA - DDRSS0_PI_229_DATA - DDRSS0_PI_230_DATA - DDRSS0_PI_231_DATA - DDRSS0_PI_232_DATA - DDRSS0_PI_233_DATA - DDRSS0_PI_234_DATA - DDRSS0_PI_235_DATA - DDRSS0_PI_236_DATA - DDRSS0_PI_237_DATA - DDRSS0_PI_238_DATA - DDRSS0_PI_239_DATA - DDRSS0_PI_240_DATA - DDRSS0_PI_241_DATA - DDRSS0_PI_242_DATA - DDRSS0_PI_243_DATA - DDRSS0_PI_244_DATA - DDRSS0_PI_245_DATA - DDRSS0_PI_246_DATA - DDRSS0_PI_247_DATA - DDRSS0_PI_248_DATA - DDRSS0_PI_249_DATA - DDRSS0_PI_250_DATA - DDRSS0_PI_251_DATA - DDRSS0_PI_252_DATA - DDRSS0_PI_253_DATA - DDRSS0_PI_254_DATA - DDRSS0_PI_255_DATA - DDRSS0_PI_256_DATA - DDRSS0_PI_257_DATA - DDRSS0_PI_258_DATA - DDRSS0_PI_259_DATA - DDRSS0_PI_260_DATA - DDRSS0_PI_261_DATA - DDRSS0_PI_262_DATA - DDRSS0_PI_263_DATA - DDRSS0_PI_264_DATA - DDRSS0_PI_265_DATA - DDRSS0_PI_266_DATA - DDRSS0_PI_267_DATA - DDRSS0_PI_268_DATA - DDRSS0_PI_269_DATA - DDRSS0_PI_270_DATA - DDRSS0_PI_271_DATA - DDRSS0_PI_272_DATA - DDRSS0_PI_273_DATA - DDRSS0_PI_274_DATA - DDRSS0_PI_275_DATA - DDRSS0_PI_276_DATA - DDRSS0_PI_277_DATA - DDRSS0_PI_278_DATA - DDRSS0_PI_279_DATA - DDRSS0_PI_280_DATA - DDRSS0_PI_281_DATA - DDRSS0_PI_282_DATA - DDRSS0_PI_283_DATA - DDRSS0_PI_284_DATA - DDRSS0_PI_285_DATA - DDRSS0_PI_286_DATA - DDRSS0_PI_287_DATA - DDRSS0_PI_288_DATA - DDRSS0_PI_289_DATA - DDRSS0_PI_290_DATA - DDRSS0_PI_291_DATA - DDRSS0_PI_292_DATA - DDRSS0_PI_293_DATA - DDRSS0_PI_294_DATA - DDRSS0_PI_295_DATA - DDRSS0_PI_296_DATA - DDRSS0_PI_297_DATA - DDRSS0_PI_298_DATA - DDRSS0_PI_299_DATA - >; - - ti,phy-data = < - DDRSS0_PHY_00_DATA - DDRSS0_PHY_01_DATA - DDRSS0_PHY_02_DATA - DDRSS0_PHY_03_DATA - DDRSS0_PHY_04_DATA - DDRSS0_PHY_05_DATA - DDRSS0_PHY_06_DATA - DDRSS0_PHY_07_DATA - DDRSS0_PHY_08_DATA - DDRSS0_PHY_09_DATA - DDRSS0_PHY_10_DATA - DDRSS0_PHY_11_DATA - DDRSS0_PHY_12_DATA - DDRSS0_PHY_13_DATA - DDRSS0_PHY_14_DATA - DDRSS0_PHY_15_DATA - DDRSS0_PHY_16_DATA - DDRSS0_PHY_17_DATA - DDRSS0_PHY_18_DATA - DDRSS0_PHY_19_DATA - DDRSS0_PHY_20_DATA - DDRSS0_PHY_21_DATA - DDRSS0_PHY_22_DATA - DDRSS0_PHY_23_DATA - DDRSS0_PHY_24_DATA - DDRSS0_PHY_25_DATA - DDRSS0_PHY_26_DATA - DDRSS0_PHY_27_DATA - DDRSS0_PHY_28_DATA - DDRSS0_PHY_29_DATA - DDRSS0_PHY_30_DATA - DDRSS0_PHY_31_DATA - DDRSS0_PHY_32_DATA - DDRSS0_PHY_33_DATA - DDRSS0_PHY_34_DATA - DDRSS0_PHY_35_DATA - DDRSS0_PHY_36_DATA - DDRSS0_PHY_37_DATA - DDRSS0_PHY_38_DATA - DDRSS0_PHY_39_DATA - DDRSS0_PHY_40_DATA - DDRSS0_PHY_41_DATA - DDRSS0_PHY_42_DATA - DDRSS0_PHY_43_DATA - DDRSS0_PHY_44_DATA - DDRSS0_PHY_45_DATA - DDRSS0_PHY_46_DATA - DDRSS0_PHY_47_DATA - DDRSS0_PHY_48_DATA - DDRSS0_PHY_49_DATA - DDRSS0_PHY_50_DATA - DDRSS0_PHY_51_DATA - DDRSS0_PHY_52_DATA - DDRSS0_PHY_53_DATA - DDRSS0_PHY_54_DATA - DDRSS0_PHY_55_DATA - DDRSS0_PHY_56_DATA - DDRSS0_PHY_57_DATA - DDRSS0_PHY_58_DATA - DDRSS0_PHY_59_DATA - DDRSS0_PHY_60_DATA - DDRSS0_PHY_61_DATA - DDRSS0_PHY_62_DATA - DDRSS0_PHY_63_DATA - DDRSS0_PHY_64_DATA - DDRSS0_PHY_65_DATA - DDRSS0_PHY_66_DATA - DDRSS0_PHY_67_DATA - DDRSS0_PHY_68_DATA - DDRSS0_PHY_69_DATA - DDRSS0_PHY_70_DATA - DDRSS0_PHY_71_DATA - DDRSS0_PHY_72_DATA - DDRSS0_PHY_73_DATA - DDRSS0_PHY_74_DATA - DDRSS0_PHY_75_DATA - DDRSS0_PHY_76_DATA - DDRSS0_PHY_77_DATA - DDRSS0_PHY_78_DATA - DDRSS0_PHY_79_DATA - DDRSS0_PHY_80_DATA - DDRSS0_PHY_81_DATA - DDRSS0_PHY_82_DATA - DDRSS0_PHY_83_DATA - DDRSS0_PHY_84_DATA - DDRSS0_PHY_85_DATA - DDRSS0_PHY_86_DATA - DDRSS0_PHY_87_DATA - DDRSS0_PHY_88_DATA - DDRSS0_PHY_89_DATA - DDRSS0_PHY_90_DATA - DDRSS0_PHY_91_DATA - DDRSS0_PHY_92_DATA - DDRSS0_PHY_93_DATA - DDRSS0_PHY_94_DATA - DDRSS0_PHY_95_DATA - DDRSS0_PHY_96_DATA - DDRSS0_PHY_97_DATA - DDRSS0_PHY_98_DATA - DDRSS0_PHY_99_DATA - DDRSS0_PHY_100_DATA - DDRSS0_PHY_101_DATA - DDRSS0_PHY_102_DATA - DDRSS0_PHY_103_DATA - DDRSS0_PHY_104_DATA - DDRSS0_PHY_105_DATA - DDRSS0_PHY_106_DATA - DDRSS0_PHY_107_DATA - DDRSS0_PHY_108_DATA - DDRSS0_PHY_109_DATA - DDRSS0_PHY_110_DATA - DDRSS0_PHY_111_DATA - DDRSS0_PHY_112_DATA - DDRSS0_PHY_113_DATA - DDRSS0_PHY_114_DATA - DDRSS0_PHY_115_DATA - DDRSS0_PHY_116_DATA - DDRSS0_PHY_117_DATA - DDRSS0_PHY_118_DATA - DDRSS0_PHY_119_DATA - DDRSS0_PHY_120_DATA - DDRSS0_PHY_121_DATA - DDRSS0_PHY_122_DATA - DDRSS0_PHY_123_DATA - DDRSS0_PHY_124_DATA - DDRSS0_PHY_125_DATA - DDRSS0_PHY_126_DATA - DDRSS0_PHY_127_DATA - DDRSS0_PHY_128_DATA - DDRSS0_PHY_129_DATA - DDRSS0_PHY_130_DATA - DDRSS0_PHY_131_DATA - DDRSS0_PHY_132_DATA - DDRSS0_PHY_133_DATA - DDRSS0_PHY_134_DATA - DDRSS0_PHY_135_DATA - DDRSS0_PHY_136_DATA - DDRSS0_PHY_137_DATA - DDRSS0_PHY_138_DATA - DDRSS0_PHY_139_DATA - DDRSS0_PHY_140_DATA - DDRSS0_PHY_141_DATA - DDRSS0_PHY_142_DATA - DDRSS0_PHY_143_DATA - DDRSS0_PHY_144_DATA - DDRSS0_PHY_145_DATA - DDRSS0_PHY_146_DATA - DDRSS0_PHY_147_DATA - DDRSS0_PHY_148_DATA - DDRSS0_PHY_149_DATA - DDRSS0_PHY_150_DATA - DDRSS0_PHY_151_DATA - DDRSS0_PHY_152_DATA - DDRSS0_PHY_153_DATA - DDRSS0_PHY_154_DATA - DDRSS0_PHY_155_DATA - DDRSS0_PHY_156_DATA - DDRSS0_PHY_157_DATA - DDRSS0_PHY_158_DATA - DDRSS0_PHY_159_DATA - DDRSS0_PHY_160_DATA - DDRSS0_PHY_161_DATA - DDRSS0_PHY_162_DATA - DDRSS0_PHY_163_DATA - DDRSS0_PHY_164_DATA - DDRSS0_PHY_165_DATA - DDRSS0_PHY_166_DATA - DDRSS0_PHY_167_DATA - DDRSS0_PHY_168_DATA - DDRSS0_PHY_169_DATA - DDRSS0_PHY_170_DATA - DDRSS0_PHY_171_DATA - DDRSS0_PHY_172_DATA - DDRSS0_PHY_173_DATA - DDRSS0_PHY_174_DATA - DDRSS0_PHY_175_DATA - DDRSS0_PHY_176_DATA - DDRSS0_PHY_177_DATA - DDRSS0_PHY_178_DATA - DDRSS0_PHY_179_DATA - DDRSS0_PHY_180_DATA - DDRSS0_PHY_181_DATA - DDRSS0_PHY_182_DATA - DDRSS0_PHY_183_DATA - DDRSS0_PHY_184_DATA - DDRSS0_PHY_185_DATA - DDRSS0_PHY_186_DATA - DDRSS0_PHY_187_DATA - DDRSS0_PHY_188_DATA - DDRSS0_PHY_189_DATA - DDRSS0_PHY_190_DATA - DDRSS0_PHY_191_DATA - DDRSS0_PHY_192_DATA - DDRSS0_PHY_193_DATA - DDRSS0_PHY_194_DATA - DDRSS0_PHY_195_DATA - DDRSS0_PHY_196_DATA - DDRSS0_PHY_197_DATA - DDRSS0_PHY_198_DATA - DDRSS0_PHY_199_DATA - DDRSS0_PHY_200_DATA - DDRSS0_PHY_201_DATA - DDRSS0_PHY_202_DATA - DDRSS0_PHY_203_DATA - DDRSS0_PHY_204_DATA - DDRSS0_PHY_205_DATA - DDRSS0_PHY_206_DATA - DDRSS0_PHY_207_DATA - DDRSS0_PHY_208_DATA - DDRSS0_PHY_209_DATA - DDRSS0_PHY_210_DATA - DDRSS0_PHY_211_DATA - DDRSS0_PHY_212_DATA - DDRSS0_PHY_213_DATA - DDRSS0_PHY_214_DATA - DDRSS0_PHY_215_DATA - DDRSS0_PHY_216_DATA - DDRSS0_PHY_217_DATA - DDRSS0_PHY_218_DATA - DDRSS0_PHY_219_DATA - DDRSS0_PHY_220_DATA - DDRSS0_PHY_221_DATA - DDRSS0_PHY_222_DATA - DDRSS0_PHY_223_DATA - DDRSS0_PHY_224_DATA - DDRSS0_PHY_225_DATA - DDRSS0_PHY_226_DATA - DDRSS0_PHY_227_DATA - DDRSS0_PHY_228_DATA - DDRSS0_PHY_229_DATA - DDRSS0_PHY_230_DATA - DDRSS0_PHY_231_DATA - DDRSS0_PHY_232_DATA - DDRSS0_PHY_233_DATA - DDRSS0_PHY_234_DATA - DDRSS0_PHY_235_DATA - DDRSS0_PHY_236_DATA - DDRSS0_PHY_237_DATA - DDRSS0_PHY_238_DATA - DDRSS0_PHY_239_DATA - DDRSS0_PHY_240_DATA - DDRSS0_PHY_241_DATA - DDRSS0_PHY_242_DATA - DDRSS0_PHY_243_DATA - DDRSS0_PHY_244_DATA - DDRSS0_PHY_245_DATA - DDRSS0_PHY_246_DATA - DDRSS0_PHY_247_DATA - DDRSS0_PHY_248_DATA - DDRSS0_PHY_249_DATA - DDRSS0_PHY_250_DATA - DDRSS0_PHY_251_DATA - DDRSS0_PHY_252_DATA - DDRSS0_PHY_253_DATA - DDRSS0_PHY_254_DATA - DDRSS0_PHY_255_DATA - DDRSS0_PHY_256_DATA - DDRSS0_PHY_257_DATA - DDRSS0_PHY_258_DATA - DDRSS0_PHY_259_DATA - DDRSS0_PHY_260_DATA - DDRSS0_PHY_261_DATA - DDRSS0_PHY_262_DATA - DDRSS0_PHY_263_DATA - DDRSS0_PHY_264_DATA - DDRSS0_PHY_265_DATA - DDRSS0_PHY_266_DATA - DDRSS0_PHY_267_DATA - DDRSS0_PHY_268_DATA - DDRSS0_PHY_269_DATA - DDRSS0_PHY_270_DATA - DDRSS0_PHY_271_DATA - DDRSS0_PHY_272_DATA - DDRSS0_PHY_273_DATA - DDRSS0_PHY_274_DATA - DDRSS0_PHY_275_DATA - DDRSS0_PHY_276_DATA - DDRSS0_PHY_277_DATA - DDRSS0_PHY_278_DATA - DDRSS0_PHY_279_DATA - DDRSS0_PHY_280_DATA - DDRSS0_PHY_281_DATA - DDRSS0_PHY_282_DATA - DDRSS0_PHY_283_DATA - DDRSS0_PHY_284_DATA - DDRSS0_PHY_285_DATA - DDRSS0_PHY_286_DATA - DDRSS0_PHY_287_DATA - DDRSS0_PHY_288_DATA - DDRSS0_PHY_289_DATA - DDRSS0_PHY_290_DATA - DDRSS0_PHY_291_DATA - DDRSS0_PHY_292_DATA - DDRSS0_PHY_293_DATA - DDRSS0_PHY_294_DATA - DDRSS0_PHY_295_DATA - DDRSS0_PHY_296_DATA - DDRSS0_PHY_297_DATA - DDRSS0_PHY_298_DATA - DDRSS0_PHY_299_DATA - DDRSS0_PHY_300_DATA - DDRSS0_PHY_301_DATA - DDRSS0_PHY_302_DATA - DDRSS0_PHY_303_DATA - DDRSS0_PHY_304_DATA - DDRSS0_PHY_305_DATA - DDRSS0_PHY_306_DATA - DDRSS0_PHY_307_DATA - DDRSS0_PHY_308_DATA - DDRSS0_PHY_309_DATA - DDRSS0_PHY_310_DATA - DDRSS0_PHY_311_DATA - DDRSS0_PHY_312_DATA - DDRSS0_PHY_313_DATA - DDRSS0_PHY_314_DATA - DDRSS0_PHY_315_DATA - DDRSS0_PHY_316_DATA - DDRSS0_PHY_317_DATA - DDRSS0_PHY_318_DATA - DDRSS0_PHY_319_DATA - DDRSS0_PHY_320_DATA - DDRSS0_PHY_321_DATA - DDRSS0_PHY_322_DATA - DDRSS0_PHY_323_DATA - DDRSS0_PHY_324_DATA - DDRSS0_PHY_325_DATA - DDRSS0_PHY_326_DATA - DDRSS0_PHY_327_DATA - DDRSS0_PHY_328_DATA - DDRSS0_PHY_329_DATA - DDRSS0_PHY_330_DATA - DDRSS0_PHY_331_DATA - DDRSS0_PHY_332_DATA - DDRSS0_PHY_333_DATA - DDRSS0_PHY_334_DATA - DDRSS0_PHY_335_DATA - DDRSS0_PHY_336_DATA - DDRSS0_PHY_337_DATA - DDRSS0_PHY_338_DATA - DDRSS0_PHY_339_DATA - DDRSS0_PHY_340_DATA - DDRSS0_PHY_341_DATA - DDRSS0_PHY_342_DATA - DDRSS0_PHY_343_DATA - DDRSS0_PHY_344_DATA - DDRSS0_PHY_345_DATA - DDRSS0_PHY_346_DATA - DDRSS0_PHY_347_DATA - DDRSS0_PHY_348_DATA - DDRSS0_PHY_349_DATA - DDRSS0_PHY_350_DATA - DDRSS0_PHY_351_DATA - DDRSS0_PHY_352_DATA - DDRSS0_PHY_353_DATA - DDRSS0_PHY_354_DATA - DDRSS0_PHY_355_DATA - DDRSS0_PHY_356_DATA - DDRSS0_PHY_357_DATA - DDRSS0_PHY_358_DATA - DDRSS0_PHY_359_DATA - DDRSS0_PHY_360_DATA - DDRSS0_PHY_361_DATA - DDRSS0_PHY_362_DATA - DDRSS0_PHY_363_DATA - DDRSS0_PHY_364_DATA - DDRSS0_PHY_365_DATA - DDRSS0_PHY_366_DATA - DDRSS0_PHY_367_DATA - DDRSS0_PHY_368_DATA - DDRSS0_PHY_369_DATA - DDRSS0_PHY_370_DATA - DDRSS0_PHY_371_DATA - DDRSS0_PHY_372_DATA - DDRSS0_PHY_373_DATA - DDRSS0_PHY_374_DATA - DDRSS0_PHY_375_DATA - DDRSS0_PHY_376_DATA - DDRSS0_PHY_377_DATA - DDRSS0_PHY_378_DATA - DDRSS0_PHY_379_DATA - DDRSS0_PHY_380_DATA - DDRSS0_PHY_381_DATA - DDRSS0_PHY_382_DATA - DDRSS0_PHY_383_DATA - DDRSS0_PHY_384_DATA - DDRSS0_PHY_385_DATA - DDRSS0_PHY_386_DATA - DDRSS0_PHY_387_DATA - DDRSS0_PHY_388_DATA - DDRSS0_PHY_389_DATA - DDRSS0_PHY_390_DATA - DDRSS0_PHY_391_DATA - DDRSS0_PHY_392_DATA - DDRSS0_PHY_393_DATA - DDRSS0_PHY_394_DATA - DDRSS0_PHY_395_DATA - DDRSS0_PHY_396_DATA - DDRSS0_PHY_397_DATA - DDRSS0_PHY_398_DATA - DDRSS0_PHY_399_DATA - DDRSS0_PHY_400_DATA - DDRSS0_PHY_401_DATA - DDRSS0_PHY_402_DATA - DDRSS0_PHY_403_DATA - DDRSS0_PHY_404_DATA - DDRSS0_PHY_405_DATA - DDRSS0_PHY_406_DATA - DDRSS0_PHY_407_DATA - DDRSS0_PHY_408_DATA - DDRSS0_PHY_409_DATA - DDRSS0_PHY_410_DATA - DDRSS0_PHY_411_DATA - DDRSS0_PHY_412_DATA - DDRSS0_PHY_413_DATA - DDRSS0_PHY_414_DATA - DDRSS0_PHY_415_DATA - DDRSS0_PHY_416_DATA - DDRSS0_PHY_417_DATA - DDRSS0_PHY_418_DATA - DDRSS0_PHY_419_DATA - DDRSS0_PHY_420_DATA - DDRSS0_PHY_421_DATA - DDRSS0_PHY_422_DATA - DDRSS0_PHY_423_DATA - DDRSS0_PHY_424_DATA - DDRSS0_PHY_425_DATA - DDRSS0_PHY_426_DATA - DDRSS0_PHY_427_DATA - DDRSS0_PHY_428_DATA - DDRSS0_PHY_429_DATA - DDRSS0_PHY_430_DATA - DDRSS0_PHY_431_DATA - DDRSS0_PHY_432_DATA - DDRSS0_PHY_433_DATA - DDRSS0_PHY_434_DATA - DDRSS0_PHY_435_DATA - DDRSS0_PHY_436_DATA - DDRSS0_PHY_437_DATA - DDRSS0_PHY_438_DATA - DDRSS0_PHY_439_DATA - DDRSS0_PHY_440_DATA - DDRSS0_PHY_441_DATA - DDRSS0_PHY_442_DATA - DDRSS0_PHY_443_DATA - DDRSS0_PHY_444_DATA - DDRSS0_PHY_445_DATA - DDRSS0_PHY_446_DATA - DDRSS0_PHY_447_DATA - DDRSS0_PHY_448_DATA - DDRSS0_PHY_449_DATA - DDRSS0_PHY_450_DATA - DDRSS0_PHY_451_DATA - DDRSS0_PHY_452_DATA - DDRSS0_PHY_453_DATA - DDRSS0_PHY_454_DATA - DDRSS0_PHY_455_DATA - DDRSS0_PHY_456_DATA - DDRSS0_PHY_457_DATA - DDRSS0_PHY_458_DATA - DDRSS0_PHY_459_DATA - DDRSS0_PHY_460_DATA - DDRSS0_PHY_461_DATA - DDRSS0_PHY_462_DATA - DDRSS0_PHY_463_DATA - DDRSS0_PHY_464_DATA - DDRSS0_PHY_465_DATA - DDRSS0_PHY_466_DATA - DDRSS0_PHY_467_DATA - DDRSS0_PHY_468_DATA - DDRSS0_PHY_469_DATA - DDRSS0_PHY_470_DATA - DDRSS0_PHY_471_DATA - DDRSS0_PHY_472_DATA - DDRSS0_PHY_473_DATA - DDRSS0_PHY_474_DATA - DDRSS0_PHY_475_DATA - DDRSS0_PHY_476_DATA - DDRSS0_PHY_477_DATA - DDRSS0_PHY_478_DATA - DDRSS0_PHY_479_DATA - DDRSS0_PHY_480_DATA - DDRSS0_PHY_481_DATA - DDRSS0_PHY_482_DATA - DDRSS0_PHY_483_DATA - DDRSS0_PHY_484_DATA - DDRSS0_PHY_485_DATA - DDRSS0_PHY_486_DATA - DDRSS0_PHY_487_DATA - DDRSS0_PHY_488_DATA - DDRSS0_PHY_489_DATA - DDRSS0_PHY_490_DATA - DDRSS0_PHY_491_DATA - DDRSS0_PHY_492_DATA - DDRSS0_PHY_493_DATA - DDRSS0_PHY_494_DATA - DDRSS0_PHY_495_DATA - DDRSS0_PHY_496_DATA - DDRSS0_PHY_497_DATA - DDRSS0_PHY_498_DATA - DDRSS0_PHY_499_DATA - DDRSS0_PHY_500_DATA - DDRSS0_PHY_501_DATA - DDRSS0_PHY_502_DATA - DDRSS0_PHY_503_DATA - DDRSS0_PHY_504_DATA - DDRSS0_PHY_505_DATA - DDRSS0_PHY_506_DATA - DDRSS0_PHY_507_DATA - DDRSS0_PHY_508_DATA - DDRSS0_PHY_509_DATA - DDRSS0_PHY_510_DATA - DDRSS0_PHY_511_DATA - DDRSS0_PHY_512_DATA - DDRSS0_PHY_513_DATA - DDRSS0_PHY_514_DATA - DDRSS0_PHY_515_DATA - DDRSS0_PHY_516_DATA - DDRSS0_PHY_517_DATA - DDRSS0_PHY_518_DATA - DDRSS0_PHY_519_DATA - DDRSS0_PHY_520_DATA - DDRSS0_PHY_521_DATA - DDRSS0_PHY_522_DATA - DDRSS0_PHY_523_DATA - DDRSS0_PHY_524_DATA - DDRSS0_PHY_525_DATA - DDRSS0_PHY_526_DATA - DDRSS0_PHY_527_DATA - DDRSS0_PHY_528_DATA - DDRSS0_PHY_529_DATA - DDRSS0_PHY_530_DATA - DDRSS0_PHY_531_DATA - DDRSS0_PHY_532_DATA - DDRSS0_PHY_533_DATA - DDRSS0_PHY_534_DATA - DDRSS0_PHY_535_DATA - DDRSS0_PHY_536_DATA - DDRSS0_PHY_537_DATA - DDRSS0_PHY_538_DATA - DDRSS0_PHY_539_DATA - DDRSS0_PHY_540_DATA - DDRSS0_PHY_541_DATA - DDRSS0_PHY_542_DATA - DDRSS0_PHY_543_DATA - DDRSS0_PHY_544_DATA - DDRSS0_PHY_545_DATA - DDRSS0_PHY_546_DATA - DDRSS0_PHY_547_DATA - DDRSS0_PHY_548_DATA - DDRSS0_PHY_549_DATA - DDRSS0_PHY_550_DATA - DDRSS0_PHY_551_DATA - DDRSS0_PHY_552_DATA - DDRSS0_PHY_553_DATA - DDRSS0_PHY_554_DATA - DDRSS0_PHY_555_DATA - DDRSS0_PHY_556_DATA - DDRSS0_PHY_557_DATA - DDRSS0_PHY_558_DATA - DDRSS0_PHY_559_DATA - DDRSS0_PHY_560_DATA - DDRSS0_PHY_561_DATA - DDRSS0_PHY_562_DATA - DDRSS0_PHY_563_DATA - DDRSS0_PHY_564_DATA - DDRSS0_PHY_565_DATA - DDRSS0_PHY_566_DATA - DDRSS0_PHY_567_DATA - DDRSS0_PHY_568_DATA - DDRSS0_PHY_569_DATA - DDRSS0_PHY_570_DATA - DDRSS0_PHY_571_DATA - DDRSS0_PHY_572_DATA - DDRSS0_PHY_573_DATA - DDRSS0_PHY_574_DATA - DDRSS0_PHY_575_DATA - DDRSS0_PHY_576_DATA - DDRSS0_PHY_577_DATA - DDRSS0_PHY_578_DATA - DDRSS0_PHY_579_DATA - DDRSS0_PHY_580_DATA - DDRSS0_PHY_581_DATA - DDRSS0_PHY_582_DATA - DDRSS0_PHY_583_DATA - DDRSS0_PHY_584_DATA - DDRSS0_PHY_585_DATA - DDRSS0_PHY_586_DATA - DDRSS0_PHY_587_DATA - DDRSS0_PHY_588_DATA - DDRSS0_PHY_589_DATA - DDRSS0_PHY_590_DATA - DDRSS0_PHY_591_DATA - DDRSS0_PHY_592_DATA - DDRSS0_PHY_593_DATA - DDRSS0_PHY_594_DATA - DDRSS0_PHY_595_DATA - DDRSS0_PHY_596_DATA - DDRSS0_PHY_597_DATA - DDRSS0_PHY_598_DATA - DDRSS0_PHY_599_DATA - DDRSS0_PHY_600_DATA - DDRSS0_PHY_601_DATA - DDRSS0_PHY_602_DATA - DDRSS0_PHY_603_DATA - DDRSS0_PHY_604_DATA - DDRSS0_PHY_605_DATA - DDRSS0_PHY_606_DATA - DDRSS0_PHY_607_DATA - DDRSS0_PHY_608_DATA - DDRSS0_PHY_609_DATA - DDRSS0_PHY_610_DATA - DDRSS0_PHY_611_DATA - DDRSS0_PHY_612_DATA - DDRSS0_PHY_613_DATA - DDRSS0_PHY_614_DATA - DDRSS0_PHY_615_DATA - DDRSS0_PHY_616_DATA - DDRSS0_PHY_617_DATA - DDRSS0_PHY_618_DATA - DDRSS0_PHY_619_DATA - DDRSS0_PHY_620_DATA - DDRSS0_PHY_621_DATA - DDRSS0_PHY_622_DATA - DDRSS0_PHY_623_DATA - DDRSS0_PHY_624_DATA - DDRSS0_PHY_625_DATA - DDRSS0_PHY_626_DATA - DDRSS0_PHY_627_DATA - DDRSS0_PHY_628_DATA - DDRSS0_PHY_629_DATA - DDRSS0_PHY_630_DATA - DDRSS0_PHY_631_DATA - DDRSS0_PHY_632_DATA - DDRSS0_PHY_633_DATA - DDRSS0_PHY_634_DATA - DDRSS0_PHY_635_DATA - DDRSS0_PHY_636_DATA - DDRSS0_PHY_637_DATA - DDRSS0_PHY_638_DATA - DDRSS0_PHY_639_DATA - DDRSS0_PHY_640_DATA - DDRSS0_PHY_641_DATA - DDRSS0_PHY_642_DATA - DDRSS0_PHY_643_DATA - DDRSS0_PHY_644_DATA - DDRSS0_PHY_645_DATA - DDRSS0_PHY_646_DATA - DDRSS0_PHY_647_DATA - DDRSS0_PHY_648_DATA - DDRSS0_PHY_649_DATA - DDRSS0_PHY_650_DATA - DDRSS0_PHY_651_DATA - DDRSS0_PHY_652_DATA - DDRSS0_PHY_653_DATA - DDRSS0_PHY_654_DATA - DDRSS0_PHY_655_DATA - DDRSS0_PHY_656_DATA - DDRSS0_PHY_657_DATA - DDRSS0_PHY_658_DATA - DDRSS0_PHY_659_DATA - DDRSS0_PHY_660_DATA - DDRSS0_PHY_661_DATA - DDRSS0_PHY_662_DATA - DDRSS0_PHY_663_DATA - DDRSS0_PHY_664_DATA - DDRSS0_PHY_665_DATA - DDRSS0_PHY_666_DATA - DDRSS0_PHY_667_DATA - DDRSS0_PHY_668_DATA - DDRSS0_PHY_669_DATA - DDRSS0_PHY_670_DATA - DDRSS0_PHY_671_DATA - DDRSS0_PHY_672_DATA - DDRSS0_PHY_673_DATA - DDRSS0_PHY_674_DATA - DDRSS0_PHY_675_DATA - DDRSS0_PHY_676_DATA - DDRSS0_PHY_677_DATA - DDRSS0_PHY_678_DATA - DDRSS0_PHY_679_DATA - DDRSS0_PHY_680_DATA - DDRSS0_PHY_681_DATA - DDRSS0_PHY_682_DATA - DDRSS0_PHY_683_DATA - DDRSS0_PHY_684_DATA - DDRSS0_PHY_685_DATA - DDRSS0_PHY_686_DATA - DDRSS0_PHY_687_DATA - DDRSS0_PHY_688_DATA - DDRSS0_PHY_689_DATA - DDRSS0_PHY_690_DATA - DDRSS0_PHY_691_DATA - DDRSS0_PHY_692_DATA - DDRSS0_PHY_693_DATA - DDRSS0_PHY_694_DATA - DDRSS0_PHY_695_DATA - DDRSS0_PHY_696_DATA - DDRSS0_PHY_697_DATA - DDRSS0_PHY_698_DATA - DDRSS0_PHY_699_DATA - DDRSS0_PHY_700_DATA - DDRSS0_PHY_701_DATA - DDRSS0_PHY_702_DATA - DDRSS0_PHY_703_DATA - DDRSS0_PHY_704_DATA - DDRSS0_PHY_705_DATA - DDRSS0_PHY_706_DATA - DDRSS0_PHY_707_DATA - DDRSS0_PHY_708_DATA - DDRSS0_PHY_709_DATA - DDRSS0_PHY_710_DATA - DDRSS0_PHY_711_DATA - DDRSS0_PHY_712_DATA - DDRSS0_PHY_713_DATA - DDRSS0_PHY_714_DATA - DDRSS0_PHY_715_DATA - DDRSS0_PHY_716_DATA - DDRSS0_PHY_717_DATA - DDRSS0_PHY_718_DATA - DDRSS0_PHY_719_DATA - DDRSS0_PHY_720_DATA - DDRSS0_PHY_721_DATA - DDRSS0_PHY_722_DATA - DDRSS0_PHY_723_DATA - DDRSS0_PHY_724_DATA - DDRSS0_PHY_725_DATA - DDRSS0_PHY_726_DATA - DDRSS0_PHY_727_DATA - DDRSS0_PHY_728_DATA - DDRSS0_PHY_729_DATA - DDRSS0_PHY_730_DATA - DDRSS0_PHY_731_DATA - DDRSS0_PHY_732_DATA - DDRSS0_PHY_733_DATA - DDRSS0_PHY_734_DATA - DDRSS0_PHY_735_DATA - DDRSS0_PHY_736_DATA - DDRSS0_PHY_737_DATA - DDRSS0_PHY_738_DATA - DDRSS0_PHY_739_DATA - DDRSS0_PHY_740_DATA - DDRSS0_PHY_741_DATA - DDRSS0_PHY_742_DATA - DDRSS0_PHY_743_DATA - DDRSS0_PHY_744_DATA - DDRSS0_PHY_745_DATA - DDRSS0_PHY_746_DATA - DDRSS0_PHY_747_DATA - DDRSS0_PHY_748_DATA - DDRSS0_PHY_749_DATA - DDRSS0_PHY_750_DATA - DDRSS0_PHY_751_DATA - DDRSS0_PHY_752_DATA - DDRSS0_PHY_753_DATA - DDRSS0_PHY_754_DATA - DDRSS0_PHY_755_DATA - DDRSS0_PHY_756_DATA - DDRSS0_PHY_757_DATA - DDRSS0_PHY_758_DATA - DDRSS0_PHY_759_DATA - DDRSS0_PHY_760_DATA - DDRSS0_PHY_761_DATA - DDRSS0_PHY_762_DATA - DDRSS0_PHY_763_DATA - DDRSS0_PHY_764_DATA - DDRSS0_PHY_765_DATA - DDRSS0_PHY_766_DATA - DDRSS0_PHY_767_DATA - DDRSS0_PHY_768_DATA - DDRSS0_PHY_769_DATA - DDRSS0_PHY_770_DATA - DDRSS0_PHY_771_DATA - DDRSS0_PHY_772_DATA - DDRSS0_PHY_773_DATA - DDRSS0_PHY_774_DATA - DDRSS0_PHY_775_DATA - DDRSS0_PHY_776_DATA - DDRSS0_PHY_777_DATA - DDRSS0_PHY_778_DATA - DDRSS0_PHY_779_DATA - DDRSS0_PHY_780_DATA - DDRSS0_PHY_781_DATA - DDRSS0_PHY_782_DATA - DDRSS0_PHY_783_DATA - DDRSS0_PHY_784_DATA - DDRSS0_PHY_785_DATA - DDRSS0_PHY_786_DATA - DDRSS0_PHY_787_DATA - DDRSS0_PHY_788_DATA - DDRSS0_PHY_789_DATA - DDRSS0_PHY_790_DATA - DDRSS0_PHY_791_DATA - DDRSS0_PHY_792_DATA - DDRSS0_PHY_793_DATA - DDRSS0_PHY_794_DATA - DDRSS0_PHY_795_DATA - DDRSS0_PHY_796_DATA - DDRSS0_PHY_797_DATA - DDRSS0_PHY_798_DATA - DDRSS0_PHY_799_DATA - DDRSS0_PHY_800_DATA - DDRSS0_PHY_801_DATA - DDRSS0_PHY_802_DATA - DDRSS0_PHY_803_DATA - DDRSS0_PHY_804_DATA - DDRSS0_PHY_805_DATA - DDRSS0_PHY_806_DATA - DDRSS0_PHY_807_DATA - DDRSS0_PHY_808_DATA - DDRSS0_PHY_809_DATA - DDRSS0_PHY_810_DATA - DDRSS0_PHY_811_DATA - DDRSS0_PHY_812_DATA - DDRSS0_PHY_813_DATA - DDRSS0_PHY_814_DATA - DDRSS0_PHY_815_DATA - DDRSS0_PHY_816_DATA - DDRSS0_PHY_817_DATA - DDRSS0_PHY_818_DATA - DDRSS0_PHY_819_DATA - DDRSS0_PHY_820_DATA - DDRSS0_PHY_821_DATA - DDRSS0_PHY_822_DATA - DDRSS0_PHY_823_DATA - DDRSS0_PHY_824_DATA - DDRSS0_PHY_825_DATA - DDRSS0_PHY_826_DATA - DDRSS0_PHY_827_DATA - DDRSS0_PHY_828_DATA - DDRSS0_PHY_829_DATA - DDRSS0_PHY_830_DATA - DDRSS0_PHY_831_DATA - DDRSS0_PHY_832_DATA - DDRSS0_PHY_833_DATA - DDRSS0_PHY_834_DATA - DDRSS0_PHY_835_DATA - DDRSS0_PHY_836_DATA - DDRSS0_PHY_837_DATA - DDRSS0_PHY_838_DATA - DDRSS0_PHY_839_DATA - DDRSS0_PHY_840_DATA - DDRSS0_PHY_841_DATA - DDRSS0_PHY_842_DATA - DDRSS0_PHY_843_DATA - DDRSS0_PHY_844_DATA - DDRSS0_PHY_845_DATA - DDRSS0_PHY_846_DATA - DDRSS0_PHY_847_DATA - DDRSS0_PHY_848_DATA - DDRSS0_PHY_849_DATA - DDRSS0_PHY_850_DATA - DDRSS0_PHY_851_DATA - DDRSS0_PHY_852_DATA - DDRSS0_PHY_853_DATA - DDRSS0_PHY_854_DATA - DDRSS0_PHY_855_DATA - DDRSS0_PHY_856_DATA - DDRSS0_PHY_857_DATA - DDRSS0_PHY_858_DATA - DDRSS0_PHY_859_DATA - DDRSS0_PHY_860_DATA - DDRSS0_PHY_861_DATA - DDRSS0_PHY_862_DATA - DDRSS0_PHY_863_DATA - DDRSS0_PHY_864_DATA - DDRSS0_PHY_865_DATA - DDRSS0_PHY_866_DATA - DDRSS0_PHY_867_DATA - DDRSS0_PHY_868_DATA - DDRSS0_PHY_869_DATA - DDRSS0_PHY_870_DATA - DDRSS0_PHY_871_DATA - DDRSS0_PHY_872_DATA - DDRSS0_PHY_873_DATA - DDRSS0_PHY_874_DATA - DDRSS0_PHY_875_DATA - DDRSS0_PHY_876_DATA - DDRSS0_PHY_877_DATA - DDRSS0_PHY_878_DATA - DDRSS0_PHY_879_DATA - DDRSS0_PHY_880_DATA - DDRSS0_PHY_881_DATA - DDRSS0_PHY_882_DATA - DDRSS0_PHY_883_DATA - DDRSS0_PHY_884_DATA - DDRSS0_PHY_885_DATA - DDRSS0_PHY_886_DATA - DDRSS0_PHY_887_DATA - DDRSS0_PHY_888_DATA - DDRSS0_PHY_889_DATA - DDRSS0_PHY_890_DATA - DDRSS0_PHY_891_DATA - DDRSS0_PHY_892_DATA - DDRSS0_PHY_893_DATA - DDRSS0_PHY_894_DATA - DDRSS0_PHY_895_DATA - DDRSS0_PHY_896_DATA - DDRSS0_PHY_897_DATA - DDRSS0_PHY_898_DATA - DDRSS0_PHY_899_DATA - DDRSS0_PHY_900_DATA - DDRSS0_PHY_901_DATA - DDRSS0_PHY_902_DATA - DDRSS0_PHY_903_DATA - DDRSS0_PHY_904_DATA - DDRSS0_PHY_905_DATA - DDRSS0_PHY_906_DATA - DDRSS0_PHY_907_DATA - DDRSS0_PHY_908_DATA - DDRSS0_PHY_909_DATA - DDRSS0_PHY_910_DATA - DDRSS0_PHY_911_DATA - DDRSS0_PHY_912_DATA - DDRSS0_PHY_913_DATA - DDRSS0_PHY_914_DATA - DDRSS0_PHY_915_DATA - DDRSS0_PHY_916_DATA - DDRSS0_PHY_917_DATA - DDRSS0_PHY_918_DATA - DDRSS0_PHY_919_DATA - DDRSS0_PHY_920_DATA - DDRSS0_PHY_921_DATA - DDRSS0_PHY_922_DATA - DDRSS0_PHY_923_DATA - DDRSS0_PHY_924_DATA - DDRSS0_PHY_925_DATA - DDRSS0_PHY_926_DATA - DDRSS0_PHY_927_DATA - DDRSS0_PHY_928_DATA - DDRSS0_PHY_929_DATA - DDRSS0_PHY_930_DATA - DDRSS0_PHY_931_DATA - DDRSS0_PHY_932_DATA - DDRSS0_PHY_933_DATA - DDRSS0_PHY_934_DATA - DDRSS0_PHY_935_DATA - DDRSS0_PHY_936_DATA - DDRSS0_PHY_937_DATA - DDRSS0_PHY_938_DATA - DDRSS0_PHY_939_DATA - DDRSS0_PHY_940_DATA - DDRSS0_PHY_941_DATA - DDRSS0_PHY_942_DATA - DDRSS0_PHY_943_DATA - DDRSS0_PHY_944_DATA - DDRSS0_PHY_945_DATA - DDRSS0_PHY_946_DATA - DDRSS0_PHY_947_DATA - DDRSS0_PHY_948_DATA - DDRSS0_PHY_949_DATA - DDRSS0_PHY_950_DATA - DDRSS0_PHY_951_DATA - DDRSS0_PHY_952_DATA - DDRSS0_PHY_953_DATA - DDRSS0_PHY_954_DATA - DDRSS0_PHY_955_DATA - DDRSS0_PHY_956_DATA - DDRSS0_PHY_957_DATA - DDRSS0_PHY_958_DATA - DDRSS0_PHY_959_DATA - DDRSS0_PHY_960_DATA - DDRSS0_PHY_961_DATA - DDRSS0_PHY_962_DATA - DDRSS0_PHY_963_DATA - DDRSS0_PHY_964_DATA - DDRSS0_PHY_965_DATA - DDRSS0_PHY_966_DATA - DDRSS0_PHY_967_DATA - DDRSS0_PHY_968_DATA - DDRSS0_PHY_969_DATA - DDRSS0_PHY_970_DATA - DDRSS0_PHY_971_DATA - DDRSS0_PHY_972_DATA - DDRSS0_PHY_973_DATA - DDRSS0_PHY_974_DATA - DDRSS0_PHY_975_DATA - DDRSS0_PHY_976_DATA - DDRSS0_PHY_977_DATA - DDRSS0_PHY_978_DATA - DDRSS0_PHY_979_DATA - DDRSS0_PHY_980_DATA - DDRSS0_PHY_981_DATA - DDRSS0_PHY_982_DATA - DDRSS0_PHY_983_DATA - DDRSS0_PHY_984_DATA - DDRSS0_PHY_985_DATA - DDRSS0_PHY_986_DATA - DDRSS0_PHY_987_DATA - DDRSS0_PHY_988_DATA - DDRSS0_PHY_989_DATA - DDRSS0_PHY_990_DATA - DDRSS0_PHY_991_DATA - DDRSS0_PHY_992_DATA - DDRSS0_PHY_993_DATA - DDRSS0_PHY_994_DATA - DDRSS0_PHY_995_DATA - DDRSS0_PHY_996_DATA - DDRSS0_PHY_997_DATA - DDRSS0_PHY_998_DATA - DDRSS0_PHY_999_DATA - DDRSS0_PHY_1000_DATA - DDRSS0_PHY_1001_DATA - DDRSS0_PHY_1002_DATA - DDRSS0_PHY_1003_DATA - DDRSS0_PHY_1004_DATA - DDRSS0_PHY_1005_DATA - DDRSS0_PHY_1006_DATA - DDRSS0_PHY_1007_DATA - DDRSS0_PHY_1008_DATA - DDRSS0_PHY_1009_DATA - DDRSS0_PHY_1010_DATA - DDRSS0_PHY_1011_DATA - DDRSS0_PHY_1012_DATA - DDRSS0_PHY_1013_DATA - DDRSS0_PHY_1014_DATA - DDRSS0_PHY_1015_DATA - DDRSS0_PHY_1016_DATA - DDRSS0_PHY_1017_DATA - DDRSS0_PHY_1018_DATA - DDRSS0_PHY_1019_DATA - DDRSS0_PHY_1020_DATA - DDRSS0_PHY_1021_DATA - DDRSS0_PHY_1022_DATA - DDRSS0_PHY_1023_DATA - DDRSS0_PHY_1024_DATA - DDRSS0_PHY_1025_DATA - DDRSS0_PHY_1026_DATA - DDRSS0_PHY_1027_DATA - DDRSS0_PHY_1028_DATA - DDRSS0_PHY_1029_DATA - DDRSS0_PHY_1030_DATA - DDRSS0_PHY_1031_DATA - DDRSS0_PHY_1032_DATA - DDRSS0_PHY_1033_DATA - DDRSS0_PHY_1034_DATA - DDRSS0_PHY_1035_DATA - DDRSS0_PHY_1036_DATA - DDRSS0_PHY_1037_DATA - DDRSS0_PHY_1038_DATA - DDRSS0_PHY_1039_DATA - DDRSS0_PHY_1040_DATA - DDRSS0_PHY_1041_DATA - DDRSS0_PHY_1042_DATA - DDRSS0_PHY_1043_DATA - DDRSS0_PHY_1044_DATA - DDRSS0_PHY_1045_DATA - DDRSS0_PHY_1046_DATA - DDRSS0_PHY_1047_DATA - DDRSS0_PHY_1048_DATA - DDRSS0_PHY_1049_DATA - DDRSS0_PHY_1050_DATA - DDRSS0_PHY_1051_DATA - DDRSS0_PHY_1052_DATA - DDRSS0_PHY_1053_DATA - DDRSS0_PHY_1054_DATA - DDRSS0_PHY_1055_DATA - DDRSS0_PHY_1056_DATA - DDRSS0_PHY_1057_DATA - DDRSS0_PHY_1058_DATA - DDRSS0_PHY_1059_DATA - DDRSS0_PHY_1060_DATA - DDRSS0_PHY_1061_DATA - DDRSS0_PHY_1062_DATA - DDRSS0_PHY_1063_DATA - DDRSS0_PHY_1064_DATA - DDRSS0_PHY_1065_DATA - DDRSS0_PHY_1066_DATA - DDRSS0_PHY_1067_DATA - DDRSS0_PHY_1068_DATA - DDRSS0_PHY_1069_DATA - DDRSS0_PHY_1070_DATA - DDRSS0_PHY_1071_DATA - DDRSS0_PHY_1072_DATA - DDRSS0_PHY_1073_DATA - DDRSS0_PHY_1074_DATA - DDRSS0_PHY_1075_DATA - DDRSS0_PHY_1076_DATA - DDRSS0_PHY_1077_DATA - DDRSS0_PHY_1078_DATA - DDRSS0_PHY_1079_DATA - DDRSS0_PHY_1080_DATA - DDRSS0_PHY_1081_DATA - DDRSS0_PHY_1082_DATA - DDRSS0_PHY_1083_DATA - DDRSS0_PHY_1084_DATA - DDRSS0_PHY_1085_DATA - DDRSS0_PHY_1086_DATA - DDRSS0_PHY_1087_DATA - DDRSS0_PHY_1088_DATA - DDRSS0_PHY_1089_DATA - DDRSS0_PHY_1090_DATA - DDRSS0_PHY_1091_DATA - DDRSS0_PHY_1092_DATA - DDRSS0_PHY_1093_DATA - DDRSS0_PHY_1094_DATA - DDRSS0_PHY_1095_DATA - DDRSS0_PHY_1096_DATA - DDRSS0_PHY_1097_DATA - DDRSS0_PHY_1098_DATA - DDRSS0_PHY_1099_DATA - DDRSS0_PHY_1100_DATA - DDRSS0_PHY_1101_DATA - DDRSS0_PHY_1102_DATA - DDRSS0_PHY_1103_DATA - DDRSS0_PHY_1104_DATA - DDRSS0_PHY_1105_DATA - DDRSS0_PHY_1106_DATA - DDRSS0_PHY_1107_DATA - DDRSS0_PHY_1108_DATA - DDRSS0_PHY_1109_DATA - DDRSS0_PHY_1110_DATA - DDRSS0_PHY_1111_DATA - DDRSS0_PHY_1112_DATA - DDRSS0_PHY_1113_DATA - DDRSS0_PHY_1114_DATA - DDRSS0_PHY_1115_DATA - DDRSS0_PHY_1116_DATA - DDRSS0_PHY_1117_DATA - DDRSS0_PHY_1118_DATA - DDRSS0_PHY_1119_DATA - DDRSS0_PHY_1120_DATA - DDRSS0_PHY_1121_DATA - DDRSS0_PHY_1122_DATA - DDRSS0_PHY_1123_DATA - DDRSS0_PHY_1124_DATA - DDRSS0_PHY_1125_DATA - DDRSS0_PHY_1126_DATA - DDRSS0_PHY_1127_DATA - DDRSS0_PHY_1128_DATA - DDRSS0_PHY_1129_DATA - DDRSS0_PHY_1130_DATA - DDRSS0_PHY_1131_DATA - DDRSS0_PHY_1132_DATA - DDRSS0_PHY_1133_DATA - DDRSS0_PHY_1134_DATA - DDRSS0_PHY_1135_DATA - DDRSS0_PHY_1136_DATA - DDRSS0_PHY_1137_DATA - DDRSS0_PHY_1138_DATA - DDRSS0_PHY_1139_DATA - DDRSS0_PHY_1140_DATA - DDRSS0_PHY_1141_DATA - DDRSS0_PHY_1142_DATA - DDRSS0_PHY_1143_DATA - DDRSS0_PHY_1144_DATA - DDRSS0_PHY_1145_DATA - DDRSS0_PHY_1146_DATA - DDRSS0_PHY_1147_DATA - DDRSS0_PHY_1148_DATA - DDRSS0_PHY_1149_DATA - DDRSS0_PHY_1150_DATA - DDRSS0_PHY_1151_DATA - DDRSS0_PHY_1152_DATA - DDRSS0_PHY_1153_DATA - DDRSS0_PHY_1154_DATA - DDRSS0_PHY_1155_DATA - DDRSS0_PHY_1156_DATA - DDRSS0_PHY_1157_DATA - DDRSS0_PHY_1158_DATA - DDRSS0_PHY_1159_DATA - DDRSS0_PHY_1160_DATA - DDRSS0_PHY_1161_DATA - DDRSS0_PHY_1162_DATA - DDRSS0_PHY_1163_DATA - DDRSS0_PHY_1164_DATA - DDRSS0_PHY_1165_DATA - DDRSS0_PHY_1166_DATA - DDRSS0_PHY_1167_DATA - DDRSS0_PHY_1168_DATA - DDRSS0_PHY_1169_DATA - DDRSS0_PHY_1170_DATA - DDRSS0_PHY_1171_DATA - DDRSS0_PHY_1172_DATA - DDRSS0_PHY_1173_DATA - DDRSS0_PHY_1174_DATA - DDRSS0_PHY_1175_DATA - DDRSS0_PHY_1176_DATA - DDRSS0_PHY_1177_DATA - DDRSS0_PHY_1178_DATA - DDRSS0_PHY_1179_DATA - DDRSS0_PHY_1180_DATA - DDRSS0_PHY_1181_DATA - DDRSS0_PHY_1182_DATA - DDRSS0_PHY_1183_DATA - DDRSS0_PHY_1184_DATA - DDRSS0_PHY_1185_DATA - DDRSS0_PHY_1186_DATA - DDRSS0_PHY_1187_DATA - DDRSS0_PHY_1188_DATA - DDRSS0_PHY_1189_DATA - DDRSS0_PHY_1190_DATA - DDRSS0_PHY_1191_DATA - DDRSS0_PHY_1192_DATA - DDRSS0_PHY_1193_DATA - DDRSS0_PHY_1194_DATA - DDRSS0_PHY_1195_DATA - DDRSS0_PHY_1196_DATA - DDRSS0_PHY_1197_DATA - DDRSS0_PHY_1198_DATA - DDRSS0_PHY_1199_DATA - DDRSS0_PHY_1200_DATA - DDRSS0_PHY_1201_DATA - DDRSS0_PHY_1202_DATA - DDRSS0_PHY_1203_DATA - DDRSS0_PHY_1204_DATA - DDRSS0_PHY_1205_DATA - DDRSS0_PHY_1206_DATA - DDRSS0_PHY_1207_DATA - DDRSS0_PHY_1208_DATA - DDRSS0_PHY_1209_DATA - DDRSS0_PHY_1210_DATA - DDRSS0_PHY_1211_DATA - DDRSS0_PHY_1212_DATA - DDRSS0_PHY_1213_DATA - DDRSS0_PHY_1214_DATA - DDRSS0_PHY_1215_DATA - DDRSS0_PHY_1216_DATA - DDRSS0_PHY_1217_DATA - DDRSS0_PHY_1218_DATA - DDRSS0_PHY_1219_DATA - DDRSS0_PHY_1220_DATA - DDRSS0_PHY_1221_DATA - DDRSS0_PHY_1222_DATA - DDRSS0_PHY_1223_DATA - DDRSS0_PHY_1224_DATA - DDRSS0_PHY_1225_DATA - DDRSS0_PHY_1226_DATA - DDRSS0_PHY_1227_DATA - DDRSS0_PHY_1228_DATA - DDRSS0_PHY_1229_DATA - DDRSS0_PHY_1230_DATA - DDRSS0_PHY_1231_DATA - DDRSS0_PHY_1232_DATA - DDRSS0_PHY_1233_DATA - DDRSS0_PHY_1234_DATA - DDRSS0_PHY_1235_DATA - DDRSS0_PHY_1236_DATA - DDRSS0_PHY_1237_DATA - DDRSS0_PHY_1238_DATA - DDRSS0_PHY_1239_DATA - DDRSS0_PHY_1240_DATA - DDRSS0_PHY_1241_DATA - DDRSS0_PHY_1242_DATA - DDRSS0_PHY_1243_DATA - DDRSS0_PHY_1244_DATA - DDRSS0_PHY_1245_DATA - DDRSS0_PHY_1246_DATA - DDRSS0_PHY_1247_DATA - DDRSS0_PHY_1248_DATA - DDRSS0_PHY_1249_DATA - DDRSS0_PHY_1250_DATA - DDRSS0_PHY_1251_DATA - DDRSS0_PHY_1252_DATA - DDRSS0_PHY_1253_DATA - DDRSS0_PHY_1254_DATA - DDRSS0_PHY_1255_DATA - DDRSS0_PHY_1256_DATA - DDRSS0_PHY_1257_DATA - DDRSS0_PHY_1258_DATA - DDRSS0_PHY_1259_DATA - DDRSS0_PHY_1260_DATA - DDRSS0_PHY_1261_DATA - DDRSS0_PHY_1262_DATA - DDRSS0_PHY_1263_DATA - DDRSS0_PHY_1264_DATA - DDRSS0_PHY_1265_DATA - DDRSS0_PHY_1266_DATA - DDRSS0_PHY_1267_DATA - DDRSS0_PHY_1268_DATA - DDRSS0_PHY_1269_DATA - DDRSS0_PHY_1270_DATA - DDRSS0_PHY_1271_DATA - DDRSS0_PHY_1272_DATA - DDRSS0_PHY_1273_DATA - DDRSS0_PHY_1274_DATA - DDRSS0_PHY_1275_DATA - DDRSS0_PHY_1276_DATA - DDRSS0_PHY_1277_DATA - DDRSS0_PHY_1278_DATA - DDRSS0_PHY_1279_DATA - DDRSS0_PHY_1280_DATA - DDRSS0_PHY_1281_DATA - DDRSS0_PHY_1282_DATA - DDRSS0_PHY_1283_DATA - DDRSS0_PHY_1284_DATA - DDRSS0_PHY_1285_DATA - DDRSS0_PHY_1286_DATA - DDRSS0_PHY_1287_DATA - DDRSS0_PHY_1288_DATA - DDRSS0_PHY_1289_DATA - DDRSS0_PHY_1290_DATA - DDRSS0_PHY_1291_DATA - DDRSS0_PHY_1292_DATA - DDRSS0_PHY_1293_DATA - DDRSS0_PHY_1294_DATA - DDRSS0_PHY_1295_DATA - DDRSS0_PHY_1296_DATA - DDRSS0_PHY_1297_DATA - DDRSS0_PHY_1298_DATA - DDRSS0_PHY_1299_DATA - DDRSS0_PHY_1300_DATA - DDRSS0_PHY_1301_DATA - DDRSS0_PHY_1302_DATA - DDRSS0_PHY_1303_DATA - DDRSS0_PHY_1304_DATA - DDRSS0_PHY_1305_DATA - DDRSS0_PHY_1306_DATA - DDRSS0_PHY_1307_DATA - DDRSS0_PHY_1308_DATA - DDRSS0_PHY_1309_DATA - DDRSS0_PHY_1310_DATA - DDRSS0_PHY_1311_DATA - DDRSS0_PHY_1312_DATA - DDRSS0_PHY_1313_DATA - DDRSS0_PHY_1314_DATA - DDRSS0_PHY_1315_DATA - DDRSS0_PHY_1316_DATA - DDRSS0_PHY_1317_DATA - DDRSS0_PHY_1318_DATA - DDRSS0_PHY_1319_DATA - DDRSS0_PHY_1320_DATA - DDRSS0_PHY_1321_DATA - DDRSS0_PHY_1322_DATA - DDRSS0_PHY_1323_DATA - DDRSS0_PHY_1324_DATA - DDRSS0_PHY_1325_DATA - DDRSS0_PHY_1326_DATA - DDRSS0_PHY_1327_DATA - DDRSS0_PHY_1328_DATA - DDRSS0_PHY_1329_DATA - DDRSS0_PHY_1330_DATA - DDRSS0_PHY_1331_DATA - DDRSS0_PHY_1332_DATA - DDRSS0_PHY_1333_DATA - DDRSS0_PHY_1334_DATA - DDRSS0_PHY_1335_DATA - DDRSS0_PHY_1336_DATA - DDRSS0_PHY_1337_DATA - DDRSS0_PHY_1338_DATA - DDRSS0_PHY_1339_DATA - DDRSS0_PHY_1340_DATA - DDRSS0_PHY_1341_DATA - DDRSS0_PHY_1342_DATA - DDRSS0_PHY_1343_DATA - DDRSS0_PHY_1344_DATA - DDRSS0_PHY_1345_DATA - DDRSS0_PHY_1346_DATA - DDRSS0_PHY_1347_DATA - DDRSS0_PHY_1348_DATA - DDRSS0_PHY_1349_DATA - DDRSS0_PHY_1350_DATA - DDRSS0_PHY_1351_DATA - DDRSS0_PHY_1352_DATA - DDRSS0_PHY_1353_DATA - DDRSS0_PHY_1354_DATA - DDRSS0_PHY_1355_DATA - DDRSS0_PHY_1356_DATA - DDRSS0_PHY_1357_DATA - DDRSS0_PHY_1358_DATA - DDRSS0_PHY_1359_DATA - DDRSS0_PHY_1360_DATA - DDRSS0_PHY_1361_DATA - DDRSS0_PHY_1362_DATA - DDRSS0_PHY_1363_DATA - DDRSS0_PHY_1364_DATA - DDRSS0_PHY_1365_DATA - DDRSS0_PHY_1366_DATA - DDRSS0_PHY_1367_DATA - DDRSS0_PHY_1368_DATA - DDRSS0_PHY_1369_DATA - DDRSS0_PHY_1370_DATA - DDRSS0_PHY_1371_DATA - DDRSS0_PHY_1372_DATA - DDRSS0_PHY_1373_DATA - DDRSS0_PHY_1374_DATA - DDRSS0_PHY_1375_DATA - DDRSS0_PHY_1376_DATA - DDRSS0_PHY_1377_DATA - DDRSS0_PHY_1378_DATA - DDRSS0_PHY_1379_DATA - DDRSS0_PHY_1380_DATA - DDRSS0_PHY_1381_DATA - DDRSS0_PHY_1382_DATA - DDRSS0_PHY_1383_DATA - DDRSS0_PHY_1384_DATA - DDRSS0_PHY_1385_DATA - DDRSS0_PHY_1386_DATA - DDRSS0_PHY_1387_DATA - DDRSS0_PHY_1388_DATA - DDRSS0_PHY_1389_DATA - DDRSS0_PHY_1390_DATA - DDRSS0_PHY_1391_DATA - DDRSS0_PHY_1392_DATA - DDRSS0_PHY_1393_DATA - DDRSS0_PHY_1394_DATA - DDRSS0_PHY_1395_DATA - DDRSS0_PHY_1396_DATA - DDRSS0_PHY_1397_DATA - DDRSS0_PHY_1398_DATA - DDRSS0_PHY_1399_DATA - DDRSS0_PHY_1400_DATA - DDRSS0_PHY_1401_DATA - DDRSS0_PHY_1402_DATA - DDRSS0_PHY_1403_DATA - DDRSS0_PHY_1404_DATA - DDRSS0_PHY_1405_DATA - DDRSS0_PHY_1406_DATA - DDRSS0_PHY_1407_DATA - DDRSS0_PHY_1408_DATA - DDRSS0_PHY_1409_DATA - DDRSS0_PHY_1410_DATA - DDRSS0_PHY_1411_DATA - DDRSS0_PHY_1412_DATA - DDRSS0_PHY_1413_DATA - DDRSS0_PHY_1414_DATA - DDRSS0_PHY_1415_DATA - DDRSS0_PHY_1416_DATA - DDRSS0_PHY_1417_DATA - DDRSS0_PHY_1418_DATA - DDRSS0_PHY_1419_DATA - DDRSS0_PHY_1420_DATA - DDRSS0_PHY_1421_DATA - DDRSS0_PHY_1422_DATA - >; - }; - - memorycontroller1: memorycontroller@29b0000 { - compatible = "ti,j721s2-ddrss"; - reg = <0x0 0x029b0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>, - <0x0 0x029a0000 0x0 0x200>; - reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; - power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>, - <&k3_pds 132 TI_SCI_PD_SHARED>; - clocks = <&k3_clks 192 1>, <&k3_clks 78 2>; - ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; - ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; - ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; - ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; - instance = <1>; - - bootph-pre-ram; - - ti,ctl-data = < - DDRSS1_CTL_00_DATA - DDRSS1_CTL_01_DATA - DDRSS1_CTL_02_DATA - DDRSS1_CTL_03_DATA - DDRSS1_CTL_04_DATA - DDRSS1_CTL_05_DATA - DDRSS1_CTL_06_DATA - DDRSS1_CTL_07_DATA - DDRSS1_CTL_08_DATA - DDRSS1_CTL_09_DATA - DDRSS1_CTL_10_DATA - DDRSS1_CTL_11_DATA - DDRSS1_CTL_12_DATA - DDRSS1_CTL_13_DATA - DDRSS1_CTL_14_DATA - DDRSS1_CTL_15_DATA - DDRSS1_CTL_16_DATA - DDRSS1_CTL_17_DATA - DDRSS1_CTL_18_DATA - DDRSS1_CTL_19_DATA - DDRSS1_CTL_20_DATA - DDRSS1_CTL_21_DATA - DDRSS1_CTL_22_DATA - DDRSS1_CTL_23_DATA - DDRSS1_CTL_24_DATA - DDRSS1_CTL_25_DATA - DDRSS1_CTL_26_DATA - DDRSS1_CTL_27_DATA - DDRSS1_CTL_28_DATA - DDRSS1_CTL_29_DATA - DDRSS1_CTL_30_DATA - DDRSS1_CTL_31_DATA - DDRSS1_CTL_32_DATA - DDRSS1_CTL_33_DATA - DDRSS1_CTL_34_DATA - DDRSS1_CTL_35_DATA - DDRSS1_CTL_36_DATA - DDRSS1_CTL_37_DATA - DDRSS1_CTL_38_DATA - DDRSS1_CTL_39_DATA - DDRSS1_CTL_40_DATA - DDRSS1_CTL_41_DATA - DDRSS1_CTL_42_DATA - DDRSS1_CTL_43_DATA - DDRSS1_CTL_44_DATA - DDRSS1_CTL_45_DATA - DDRSS1_CTL_46_DATA - DDRSS1_CTL_47_DATA - DDRSS1_CTL_48_DATA - DDRSS1_CTL_49_DATA - DDRSS1_CTL_50_DATA - DDRSS1_CTL_51_DATA - DDRSS1_CTL_52_DATA - DDRSS1_CTL_53_DATA - DDRSS1_CTL_54_DATA - DDRSS1_CTL_55_DATA - DDRSS1_CTL_56_DATA - DDRSS1_CTL_57_DATA - DDRSS1_CTL_58_DATA - DDRSS1_CTL_59_DATA - DDRSS1_CTL_60_DATA - DDRSS1_CTL_61_DATA - DDRSS1_CTL_62_DATA - DDRSS1_CTL_63_DATA - DDRSS1_CTL_64_DATA - DDRSS1_CTL_65_DATA - DDRSS1_CTL_66_DATA - DDRSS1_CTL_67_DATA - DDRSS1_CTL_68_DATA - DDRSS1_CTL_69_DATA - DDRSS1_CTL_70_DATA - DDRSS1_CTL_71_DATA - DDRSS1_CTL_72_DATA - DDRSS1_CTL_73_DATA - DDRSS1_CTL_74_DATA - DDRSS1_CTL_75_DATA - DDRSS1_CTL_76_DATA - DDRSS1_CTL_77_DATA - DDRSS1_CTL_78_DATA - DDRSS1_CTL_79_DATA - DDRSS1_CTL_80_DATA - DDRSS1_CTL_81_DATA - DDRSS1_CTL_82_DATA - DDRSS1_CTL_83_DATA - DDRSS1_CTL_84_DATA - DDRSS1_CTL_85_DATA - DDRSS1_CTL_86_DATA - DDRSS1_CTL_87_DATA - DDRSS1_CTL_88_DATA - DDRSS1_CTL_89_DATA - DDRSS1_CTL_90_DATA - DDRSS1_CTL_91_DATA - DDRSS1_CTL_92_DATA - DDRSS1_CTL_93_DATA - DDRSS1_CTL_94_DATA - DDRSS1_CTL_95_DATA - DDRSS1_CTL_96_DATA - DDRSS1_CTL_97_DATA - DDRSS1_CTL_98_DATA - DDRSS1_CTL_99_DATA - DDRSS1_CTL_100_DATA - DDRSS1_CTL_101_DATA - DDRSS1_CTL_102_DATA - DDRSS1_CTL_103_DATA - DDRSS1_CTL_104_DATA - DDRSS1_CTL_105_DATA - DDRSS1_CTL_106_DATA - DDRSS1_CTL_107_DATA - DDRSS1_CTL_108_DATA - DDRSS1_CTL_109_DATA - DDRSS1_CTL_110_DATA - DDRSS1_CTL_111_DATA - DDRSS1_CTL_112_DATA - DDRSS1_CTL_113_DATA - DDRSS1_CTL_114_DATA - DDRSS1_CTL_115_DATA - DDRSS1_CTL_116_DATA - DDRSS1_CTL_117_DATA - DDRSS1_CTL_118_DATA - DDRSS1_CTL_119_DATA - DDRSS1_CTL_120_DATA - DDRSS1_CTL_121_DATA - DDRSS1_CTL_122_DATA - DDRSS1_CTL_123_DATA - DDRSS1_CTL_124_DATA - DDRSS1_CTL_125_DATA - DDRSS1_CTL_126_DATA - DDRSS1_CTL_127_DATA - DDRSS1_CTL_128_DATA - DDRSS1_CTL_129_DATA - DDRSS1_CTL_130_DATA - DDRSS1_CTL_131_DATA - DDRSS1_CTL_132_DATA - DDRSS1_CTL_133_DATA - DDRSS1_CTL_134_DATA - DDRSS1_CTL_135_DATA - DDRSS1_CTL_136_DATA - DDRSS1_CTL_137_DATA - DDRSS1_CTL_138_DATA - DDRSS1_CTL_139_DATA - DDRSS1_CTL_140_DATA - DDRSS1_CTL_141_DATA - DDRSS1_CTL_142_DATA - DDRSS1_CTL_143_DATA - DDRSS1_CTL_144_DATA - DDRSS1_CTL_145_DATA - DDRSS1_CTL_146_DATA - DDRSS1_CTL_147_DATA - DDRSS1_CTL_148_DATA - DDRSS1_CTL_149_DATA - DDRSS1_CTL_150_DATA - DDRSS1_CTL_151_DATA - DDRSS1_CTL_152_DATA - DDRSS1_CTL_153_DATA - DDRSS1_CTL_154_DATA - DDRSS1_CTL_155_DATA - DDRSS1_CTL_156_DATA - DDRSS1_CTL_157_DATA - DDRSS1_CTL_158_DATA - DDRSS1_CTL_159_DATA - DDRSS1_CTL_160_DATA - DDRSS1_CTL_161_DATA - DDRSS1_CTL_162_DATA - DDRSS1_CTL_163_DATA - DDRSS1_CTL_164_DATA - DDRSS1_CTL_165_DATA - DDRSS1_CTL_166_DATA - DDRSS1_CTL_167_DATA - DDRSS1_CTL_168_DATA - DDRSS1_CTL_169_DATA - DDRSS1_CTL_170_DATA - DDRSS1_CTL_171_DATA - DDRSS1_CTL_172_DATA - DDRSS1_CTL_173_DATA - DDRSS1_CTL_174_DATA - DDRSS1_CTL_175_DATA - DDRSS1_CTL_176_DATA - DDRSS1_CTL_177_DATA - DDRSS1_CTL_178_DATA - DDRSS1_CTL_179_DATA - DDRSS1_CTL_180_DATA - DDRSS1_CTL_181_DATA - DDRSS1_CTL_182_DATA - DDRSS1_CTL_183_DATA - DDRSS1_CTL_184_DATA - DDRSS1_CTL_185_DATA - DDRSS1_CTL_186_DATA - DDRSS1_CTL_187_DATA - DDRSS1_CTL_188_DATA - DDRSS1_CTL_189_DATA - DDRSS1_CTL_190_DATA - DDRSS1_CTL_191_DATA - DDRSS1_CTL_192_DATA - DDRSS1_CTL_193_DATA - DDRSS1_CTL_194_DATA - DDRSS1_CTL_195_DATA - DDRSS1_CTL_196_DATA - DDRSS1_CTL_197_DATA - DDRSS1_CTL_198_DATA - DDRSS1_CTL_199_DATA - DDRSS1_CTL_200_DATA - DDRSS1_CTL_201_DATA - DDRSS1_CTL_202_DATA - DDRSS1_CTL_203_DATA - DDRSS1_CTL_204_DATA - DDRSS1_CTL_205_DATA - DDRSS1_CTL_206_DATA - DDRSS1_CTL_207_DATA - DDRSS1_CTL_208_DATA - DDRSS1_CTL_209_DATA - DDRSS1_CTL_210_DATA - DDRSS1_CTL_211_DATA - DDRSS1_CTL_212_DATA - DDRSS1_CTL_213_DATA - DDRSS1_CTL_214_DATA - DDRSS1_CTL_215_DATA - DDRSS1_CTL_216_DATA - DDRSS1_CTL_217_DATA - DDRSS1_CTL_218_DATA - DDRSS1_CTL_219_DATA - DDRSS1_CTL_220_DATA - DDRSS1_CTL_221_DATA - DDRSS1_CTL_222_DATA - DDRSS1_CTL_223_DATA - DDRSS1_CTL_224_DATA - DDRSS1_CTL_225_DATA - DDRSS1_CTL_226_DATA - DDRSS1_CTL_227_DATA - DDRSS1_CTL_228_DATA - DDRSS1_CTL_229_DATA - DDRSS1_CTL_230_DATA - DDRSS1_CTL_231_DATA - DDRSS1_CTL_232_DATA - DDRSS1_CTL_233_DATA - DDRSS1_CTL_234_DATA - DDRSS1_CTL_235_DATA - DDRSS1_CTL_236_DATA - DDRSS1_CTL_237_DATA - DDRSS1_CTL_238_DATA - DDRSS1_CTL_239_DATA - DDRSS1_CTL_240_DATA - DDRSS1_CTL_241_DATA - DDRSS1_CTL_242_DATA - DDRSS1_CTL_243_DATA - DDRSS1_CTL_244_DATA - DDRSS1_CTL_245_DATA - DDRSS1_CTL_246_DATA - DDRSS1_CTL_247_DATA - DDRSS1_CTL_248_DATA - DDRSS1_CTL_249_DATA - DDRSS1_CTL_250_DATA - DDRSS1_CTL_251_DATA - DDRSS1_CTL_252_DATA - DDRSS1_CTL_253_DATA - DDRSS1_CTL_254_DATA - DDRSS1_CTL_255_DATA - DDRSS1_CTL_256_DATA - DDRSS1_CTL_257_DATA - DDRSS1_CTL_258_DATA - DDRSS1_CTL_259_DATA - DDRSS1_CTL_260_DATA - DDRSS1_CTL_261_DATA - DDRSS1_CTL_262_DATA - DDRSS1_CTL_263_DATA - DDRSS1_CTL_264_DATA - DDRSS1_CTL_265_DATA - DDRSS1_CTL_266_DATA - DDRSS1_CTL_267_DATA - DDRSS1_CTL_268_DATA - DDRSS1_CTL_269_DATA - DDRSS1_CTL_270_DATA - DDRSS1_CTL_271_DATA - DDRSS1_CTL_272_DATA - DDRSS1_CTL_273_DATA - DDRSS1_CTL_274_DATA - DDRSS1_CTL_275_DATA - DDRSS1_CTL_276_DATA - DDRSS1_CTL_277_DATA - DDRSS1_CTL_278_DATA - DDRSS1_CTL_279_DATA - DDRSS1_CTL_280_DATA - DDRSS1_CTL_281_DATA - DDRSS1_CTL_282_DATA - DDRSS1_CTL_283_DATA - DDRSS1_CTL_284_DATA - DDRSS1_CTL_285_DATA - DDRSS1_CTL_286_DATA - DDRSS1_CTL_287_DATA - DDRSS1_CTL_288_DATA - DDRSS1_CTL_289_DATA - DDRSS1_CTL_290_DATA - DDRSS1_CTL_291_DATA - DDRSS1_CTL_292_DATA - DDRSS1_CTL_293_DATA - DDRSS1_CTL_294_DATA - DDRSS1_CTL_295_DATA - DDRSS1_CTL_296_DATA - DDRSS1_CTL_297_DATA - DDRSS1_CTL_298_DATA - DDRSS1_CTL_299_DATA - DDRSS1_CTL_300_DATA - DDRSS1_CTL_301_DATA - DDRSS1_CTL_302_DATA - DDRSS1_CTL_303_DATA - DDRSS1_CTL_304_DATA - DDRSS1_CTL_305_DATA - DDRSS1_CTL_306_DATA - DDRSS1_CTL_307_DATA - DDRSS1_CTL_308_DATA - DDRSS1_CTL_309_DATA - DDRSS1_CTL_310_DATA - DDRSS1_CTL_311_DATA - DDRSS1_CTL_312_DATA - DDRSS1_CTL_313_DATA - DDRSS1_CTL_314_DATA - DDRSS1_CTL_315_DATA - DDRSS1_CTL_316_DATA - DDRSS1_CTL_317_DATA - DDRSS1_CTL_318_DATA - DDRSS1_CTL_319_DATA - DDRSS1_CTL_320_DATA - DDRSS1_CTL_321_DATA - DDRSS1_CTL_322_DATA - DDRSS1_CTL_323_DATA - DDRSS1_CTL_324_DATA - DDRSS1_CTL_325_DATA - DDRSS1_CTL_326_DATA - DDRSS1_CTL_327_DATA - DDRSS1_CTL_328_DATA - DDRSS1_CTL_329_DATA - DDRSS1_CTL_330_DATA - DDRSS1_CTL_331_DATA - DDRSS1_CTL_332_DATA - DDRSS1_CTL_333_DATA - DDRSS1_CTL_334_DATA - DDRSS1_CTL_335_DATA - DDRSS1_CTL_336_DATA - DDRSS1_CTL_337_DATA - DDRSS1_CTL_338_DATA - DDRSS1_CTL_339_DATA - DDRSS1_CTL_340_DATA - DDRSS1_CTL_341_DATA - DDRSS1_CTL_342_DATA - DDRSS1_CTL_343_DATA - DDRSS1_CTL_344_DATA - DDRSS1_CTL_345_DATA - DDRSS1_CTL_346_DATA - DDRSS1_CTL_347_DATA - DDRSS1_CTL_348_DATA - DDRSS1_CTL_349_DATA - DDRSS1_CTL_350_DATA - DDRSS1_CTL_351_DATA - DDRSS1_CTL_352_DATA - DDRSS1_CTL_353_DATA - DDRSS1_CTL_354_DATA - DDRSS1_CTL_355_DATA - DDRSS1_CTL_356_DATA - DDRSS1_CTL_357_DATA - DDRSS1_CTL_358_DATA - DDRSS1_CTL_359_DATA - DDRSS1_CTL_360_DATA - DDRSS1_CTL_361_DATA - DDRSS1_CTL_362_DATA - DDRSS1_CTL_363_DATA - DDRSS1_CTL_364_DATA - DDRSS1_CTL_365_DATA - DDRSS1_CTL_366_DATA - DDRSS1_CTL_367_DATA - DDRSS1_CTL_368_DATA - DDRSS1_CTL_369_DATA - DDRSS1_CTL_370_DATA - DDRSS1_CTL_371_DATA - DDRSS1_CTL_372_DATA - DDRSS1_CTL_373_DATA - DDRSS1_CTL_374_DATA - DDRSS1_CTL_375_DATA - DDRSS1_CTL_376_DATA - DDRSS1_CTL_377_DATA - DDRSS1_CTL_378_DATA - DDRSS1_CTL_379_DATA - DDRSS1_CTL_380_DATA - DDRSS1_CTL_381_DATA - DDRSS1_CTL_382_DATA - DDRSS1_CTL_383_DATA - DDRSS1_CTL_384_DATA - DDRSS1_CTL_385_DATA - DDRSS1_CTL_386_DATA - DDRSS1_CTL_387_DATA - DDRSS1_CTL_388_DATA - DDRSS1_CTL_389_DATA - DDRSS1_CTL_390_DATA - DDRSS1_CTL_391_DATA - DDRSS1_CTL_392_DATA - DDRSS1_CTL_393_DATA - DDRSS1_CTL_394_DATA - DDRSS1_CTL_395_DATA - DDRSS1_CTL_396_DATA - DDRSS1_CTL_397_DATA - DDRSS1_CTL_398_DATA - DDRSS1_CTL_399_DATA - DDRSS1_CTL_400_DATA - DDRSS1_CTL_401_DATA - DDRSS1_CTL_402_DATA - DDRSS1_CTL_403_DATA - DDRSS1_CTL_404_DATA - DDRSS1_CTL_405_DATA - DDRSS1_CTL_406_DATA - DDRSS1_CTL_407_DATA - DDRSS1_CTL_408_DATA - DDRSS1_CTL_409_DATA - DDRSS1_CTL_410_DATA - DDRSS1_CTL_411_DATA - DDRSS1_CTL_412_DATA - DDRSS1_CTL_413_DATA - DDRSS1_CTL_414_DATA - DDRSS1_CTL_415_DATA - DDRSS1_CTL_416_DATA - DDRSS1_CTL_417_DATA - DDRSS1_CTL_418_DATA - DDRSS1_CTL_419_DATA - DDRSS1_CTL_420_DATA - DDRSS1_CTL_421_DATA - DDRSS1_CTL_422_DATA - DDRSS1_CTL_423_DATA - DDRSS1_CTL_424_DATA - DDRSS1_CTL_425_DATA - DDRSS1_CTL_426_DATA - DDRSS1_CTL_427_DATA - DDRSS1_CTL_428_DATA - DDRSS1_CTL_429_DATA - DDRSS1_CTL_430_DATA - DDRSS1_CTL_431_DATA - DDRSS1_CTL_432_DATA - DDRSS1_CTL_433_DATA - DDRSS1_CTL_434_DATA - DDRSS1_CTL_435_DATA - DDRSS1_CTL_436_DATA - DDRSS1_CTL_437_DATA - DDRSS1_CTL_438_DATA - DDRSS1_CTL_439_DATA - DDRSS1_CTL_440_DATA - DDRSS1_CTL_441_DATA - DDRSS1_CTL_442_DATA - DDRSS1_CTL_443_DATA - DDRSS1_CTL_444_DATA - DDRSS1_CTL_445_DATA - DDRSS1_CTL_446_DATA - DDRSS1_CTL_447_DATA - DDRSS1_CTL_448_DATA - DDRSS1_CTL_449_DATA - DDRSS1_CTL_450_DATA - DDRSS1_CTL_451_DATA - DDRSS1_CTL_452_DATA - DDRSS1_CTL_453_DATA - DDRSS1_CTL_454_DATA - DDRSS1_CTL_455_DATA - DDRSS1_CTL_456_DATA - DDRSS1_CTL_457_DATA - DDRSS1_CTL_458_DATA - >; - - ti,pi-data = < - DDRSS1_PI_00_DATA - DDRSS1_PI_01_DATA - DDRSS1_PI_02_DATA - DDRSS1_PI_03_DATA - DDRSS1_PI_04_DATA - DDRSS1_PI_05_DATA - DDRSS1_PI_06_DATA - DDRSS1_PI_07_DATA - DDRSS1_PI_08_DATA - DDRSS1_PI_09_DATA - DDRSS1_PI_10_DATA - DDRSS1_PI_11_DATA - DDRSS1_PI_12_DATA - DDRSS1_PI_13_DATA - DDRSS1_PI_14_DATA - DDRSS1_PI_15_DATA - DDRSS1_PI_16_DATA - DDRSS1_PI_17_DATA - DDRSS1_PI_18_DATA - DDRSS1_PI_19_DATA - DDRSS1_PI_20_DATA - DDRSS1_PI_21_DATA - DDRSS1_PI_22_DATA - DDRSS1_PI_23_DATA - DDRSS1_PI_24_DATA - DDRSS1_PI_25_DATA - DDRSS1_PI_26_DATA - DDRSS1_PI_27_DATA - DDRSS1_PI_28_DATA - DDRSS1_PI_29_DATA - DDRSS1_PI_30_DATA - DDRSS1_PI_31_DATA - DDRSS1_PI_32_DATA - DDRSS1_PI_33_DATA - DDRSS1_PI_34_DATA - DDRSS1_PI_35_DATA - DDRSS1_PI_36_DATA - DDRSS1_PI_37_DATA - DDRSS1_PI_38_DATA - DDRSS1_PI_39_DATA - DDRSS1_PI_40_DATA - DDRSS1_PI_41_DATA - DDRSS1_PI_42_DATA - DDRSS1_PI_43_DATA - DDRSS1_PI_44_DATA - DDRSS1_PI_45_DATA - DDRSS1_PI_46_DATA - DDRSS1_PI_47_DATA - DDRSS1_PI_48_DATA - DDRSS1_PI_49_DATA - DDRSS1_PI_50_DATA - DDRSS1_PI_51_DATA - DDRSS1_PI_52_DATA - DDRSS1_PI_53_DATA - DDRSS1_PI_54_DATA - DDRSS1_PI_55_DATA - DDRSS1_PI_56_DATA - DDRSS1_PI_57_DATA - DDRSS1_PI_58_DATA - DDRSS1_PI_59_DATA - DDRSS1_PI_60_DATA - DDRSS1_PI_61_DATA - DDRSS1_PI_62_DATA - DDRSS1_PI_63_DATA - DDRSS1_PI_64_DATA - DDRSS1_PI_65_DATA - DDRSS1_PI_66_DATA - DDRSS1_PI_67_DATA - DDRSS1_PI_68_DATA - DDRSS1_PI_69_DATA - DDRSS1_PI_70_DATA - DDRSS1_PI_71_DATA - DDRSS1_PI_72_DATA - DDRSS1_PI_73_DATA - DDRSS1_PI_74_DATA - DDRSS1_PI_75_DATA - DDRSS1_PI_76_DATA - DDRSS1_PI_77_DATA - DDRSS1_PI_78_DATA - DDRSS1_PI_79_DATA - DDRSS1_PI_80_DATA - DDRSS1_PI_81_DATA - DDRSS1_PI_82_DATA - DDRSS1_PI_83_DATA - DDRSS1_PI_84_DATA - DDRSS1_PI_85_DATA - DDRSS1_PI_86_DATA - DDRSS1_PI_87_DATA - DDRSS1_PI_88_DATA - DDRSS1_PI_89_DATA - DDRSS1_PI_90_DATA - DDRSS1_PI_91_DATA - DDRSS1_PI_92_DATA - DDRSS1_PI_93_DATA - DDRSS1_PI_94_DATA - DDRSS1_PI_95_DATA - DDRSS1_PI_96_DATA - DDRSS1_PI_97_DATA - DDRSS1_PI_98_DATA - DDRSS1_PI_99_DATA - DDRSS1_PI_100_DATA - DDRSS1_PI_101_DATA - DDRSS1_PI_102_DATA - DDRSS1_PI_103_DATA - DDRSS1_PI_104_DATA - DDRSS1_PI_105_DATA - DDRSS1_PI_106_DATA - DDRSS1_PI_107_DATA - DDRSS1_PI_108_DATA - DDRSS1_PI_109_DATA - DDRSS1_PI_110_DATA - DDRSS1_PI_111_DATA - DDRSS1_PI_112_DATA - DDRSS1_PI_113_DATA - DDRSS1_PI_114_DATA - DDRSS1_PI_115_DATA - DDRSS1_PI_116_DATA - DDRSS1_PI_117_DATA - DDRSS1_PI_118_DATA - DDRSS1_PI_119_DATA - DDRSS1_PI_120_DATA - DDRSS1_PI_121_DATA - DDRSS1_PI_122_DATA - DDRSS1_PI_123_DATA - DDRSS1_PI_124_DATA - DDRSS1_PI_125_DATA - DDRSS1_PI_126_DATA - DDRSS1_PI_127_DATA - DDRSS1_PI_128_DATA - DDRSS1_PI_129_DATA - DDRSS1_PI_130_DATA - DDRSS1_PI_131_DATA - DDRSS1_PI_132_DATA - DDRSS1_PI_133_DATA - DDRSS1_PI_134_DATA - DDRSS1_PI_135_DATA - DDRSS1_PI_136_DATA - DDRSS1_PI_137_DATA - DDRSS1_PI_138_DATA - DDRSS1_PI_139_DATA - DDRSS1_PI_140_DATA - DDRSS1_PI_141_DATA - DDRSS1_PI_142_DATA - DDRSS1_PI_143_DATA - DDRSS1_PI_144_DATA - DDRSS1_PI_145_DATA - DDRSS1_PI_146_DATA - DDRSS1_PI_147_DATA - DDRSS1_PI_148_DATA - DDRSS1_PI_149_DATA - DDRSS1_PI_150_DATA - DDRSS1_PI_151_DATA - DDRSS1_PI_152_DATA - DDRSS1_PI_153_DATA - DDRSS1_PI_154_DATA - DDRSS1_PI_155_DATA - DDRSS1_PI_156_DATA - DDRSS1_PI_157_DATA - DDRSS1_PI_158_DATA - DDRSS1_PI_159_DATA - DDRSS1_PI_160_DATA - DDRSS1_PI_161_DATA - DDRSS1_PI_162_DATA - DDRSS1_PI_163_DATA - DDRSS1_PI_164_DATA - DDRSS1_PI_165_DATA - DDRSS1_PI_166_DATA - DDRSS1_PI_167_DATA - DDRSS1_PI_168_DATA - DDRSS1_PI_169_DATA - DDRSS1_PI_170_DATA - DDRSS1_PI_171_DATA - DDRSS1_PI_172_DATA - DDRSS1_PI_173_DATA - DDRSS1_PI_174_DATA - DDRSS1_PI_175_DATA - DDRSS1_PI_176_DATA - DDRSS1_PI_177_DATA - DDRSS1_PI_178_DATA - DDRSS1_PI_179_DATA - DDRSS1_PI_180_DATA - DDRSS1_PI_181_DATA - DDRSS1_PI_182_DATA - DDRSS1_PI_183_DATA - DDRSS1_PI_184_DATA - DDRSS1_PI_185_DATA - DDRSS1_PI_186_DATA - DDRSS1_PI_187_DATA - DDRSS1_PI_188_DATA - DDRSS1_PI_189_DATA - DDRSS1_PI_190_DATA - DDRSS1_PI_191_DATA - DDRSS1_PI_192_DATA - DDRSS1_PI_193_DATA - DDRSS1_PI_194_DATA - DDRSS1_PI_195_DATA - DDRSS1_PI_196_DATA - DDRSS1_PI_197_DATA - DDRSS1_PI_198_DATA - DDRSS1_PI_199_DATA - DDRSS1_PI_200_DATA - DDRSS1_PI_201_DATA - DDRSS1_PI_202_DATA - DDRSS1_PI_203_DATA - DDRSS1_PI_204_DATA - DDRSS1_PI_205_DATA - DDRSS1_PI_206_DATA - DDRSS1_PI_207_DATA - DDRSS1_PI_208_DATA - DDRSS1_PI_209_DATA - DDRSS1_PI_210_DATA - DDRSS1_PI_211_DATA - DDRSS1_PI_212_DATA - DDRSS1_PI_213_DATA - DDRSS1_PI_214_DATA - DDRSS1_PI_215_DATA - DDRSS1_PI_216_DATA - DDRSS1_PI_217_DATA - DDRSS1_PI_218_DATA - DDRSS1_PI_219_DATA - DDRSS1_PI_220_DATA - DDRSS1_PI_221_DATA - DDRSS1_PI_222_DATA - DDRSS1_PI_223_DATA - DDRSS1_PI_224_DATA - DDRSS1_PI_225_DATA - DDRSS1_PI_226_DATA - DDRSS1_PI_227_DATA - DDRSS1_PI_228_DATA - DDRSS1_PI_229_DATA - DDRSS1_PI_230_DATA - DDRSS1_PI_231_DATA - DDRSS1_PI_232_DATA - DDRSS1_PI_233_DATA - DDRSS1_PI_234_DATA - DDRSS1_PI_235_DATA - DDRSS1_PI_236_DATA - DDRSS1_PI_237_DATA - DDRSS1_PI_238_DATA - DDRSS1_PI_239_DATA - DDRSS1_PI_240_DATA - DDRSS1_PI_241_DATA - DDRSS1_PI_242_DATA - DDRSS1_PI_243_DATA - DDRSS1_PI_244_DATA - DDRSS1_PI_245_DATA - DDRSS1_PI_246_DATA - DDRSS1_PI_247_DATA - DDRSS1_PI_248_DATA - DDRSS1_PI_249_DATA - DDRSS1_PI_250_DATA - DDRSS1_PI_251_DATA - DDRSS1_PI_252_DATA - DDRSS1_PI_253_DATA - DDRSS1_PI_254_DATA - DDRSS1_PI_255_DATA - DDRSS1_PI_256_DATA - DDRSS1_PI_257_DATA - DDRSS1_PI_258_DATA - DDRSS1_PI_259_DATA - DDRSS1_PI_260_DATA - DDRSS1_PI_261_DATA - DDRSS1_PI_262_DATA - DDRSS1_PI_263_DATA - DDRSS1_PI_264_DATA - DDRSS1_PI_265_DATA - DDRSS1_PI_266_DATA - DDRSS1_PI_267_DATA - DDRSS1_PI_268_DATA - DDRSS1_PI_269_DATA - DDRSS1_PI_270_DATA - DDRSS1_PI_271_DATA - DDRSS1_PI_272_DATA - DDRSS1_PI_273_DATA - DDRSS1_PI_274_DATA - DDRSS1_PI_275_DATA - DDRSS1_PI_276_DATA - DDRSS1_PI_277_DATA - DDRSS1_PI_278_DATA - DDRSS1_PI_279_DATA - DDRSS1_PI_280_DATA - DDRSS1_PI_281_DATA - DDRSS1_PI_282_DATA - DDRSS1_PI_283_DATA - DDRSS1_PI_284_DATA - DDRSS1_PI_285_DATA - DDRSS1_PI_286_DATA - DDRSS1_PI_287_DATA - DDRSS1_PI_288_DATA - DDRSS1_PI_289_DATA - DDRSS1_PI_290_DATA - DDRSS1_PI_291_DATA - DDRSS1_PI_292_DATA - DDRSS1_PI_293_DATA - DDRSS1_PI_294_DATA - DDRSS1_PI_295_DATA - DDRSS1_PI_296_DATA - DDRSS1_PI_297_DATA - DDRSS1_PI_298_DATA - DDRSS1_PI_299_DATA - >; - - ti,phy-data = < - DDRSS1_PHY_00_DATA - DDRSS1_PHY_01_DATA - DDRSS1_PHY_02_DATA - DDRSS1_PHY_03_DATA - DDRSS1_PHY_04_DATA - DDRSS1_PHY_05_DATA - DDRSS1_PHY_06_DATA - DDRSS1_PHY_07_DATA - DDRSS1_PHY_08_DATA - DDRSS1_PHY_09_DATA - DDRSS1_PHY_10_DATA - DDRSS1_PHY_11_DATA - DDRSS1_PHY_12_DATA - DDRSS1_PHY_13_DATA - DDRSS1_PHY_14_DATA - DDRSS1_PHY_15_DATA - DDRSS1_PHY_16_DATA - DDRSS1_PHY_17_DATA - DDRSS1_PHY_18_DATA - DDRSS1_PHY_19_DATA - DDRSS1_PHY_20_DATA - DDRSS1_PHY_21_DATA - DDRSS1_PHY_22_DATA - DDRSS1_PHY_23_DATA - DDRSS1_PHY_24_DATA - DDRSS1_PHY_25_DATA - DDRSS1_PHY_26_DATA - DDRSS1_PHY_27_DATA - DDRSS1_PHY_28_DATA - DDRSS1_PHY_29_DATA - DDRSS1_PHY_30_DATA - DDRSS1_PHY_31_DATA - DDRSS1_PHY_32_DATA - DDRSS1_PHY_33_DATA - DDRSS1_PHY_34_DATA - DDRSS1_PHY_35_DATA - DDRSS1_PHY_36_DATA - DDRSS1_PHY_37_DATA - DDRSS1_PHY_38_DATA - DDRSS1_PHY_39_DATA - DDRSS1_PHY_40_DATA - DDRSS1_PHY_41_DATA - DDRSS1_PHY_42_DATA - DDRSS1_PHY_43_DATA - DDRSS1_PHY_44_DATA - DDRSS1_PHY_45_DATA - DDRSS1_PHY_46_DATA - DDRSS1_PHY_47_DATA - DDRSS1_PHY_48_DATA - DDRSS1_PHY_49_DATA - DDRSS1_PHY_50_DATA - DDRSS1_PHY_51_DATA - DDRSS1_PHY_52_DATA - DDRSS1_PHY_53_DATA - DDRSS1_PHY_54_DATA - DDRSS1_PHY_55_DATA - DDRSS1_PHY_56_DATA - DDRSS1_PHY_57_DATA - DDRSS1_PHY_58_DATA - DDRSS1_PHY_59_DATA - DDRSS1_PHY_60_DATA - DDRSS1_PHY_61_DATA - DDRSS1_PHY_62_DATA - DDRSS1_PHY_63_DATA - DDRSS1_PHY_64_DATA - DDRSS1_PHY_65_DATA - DDRSS1_PHY_66_DATA - DDRSS1_PHY_67_DATA - DDRSS1_PHY_68_DATA - DDRSS1_PHY_69_DATA - DDRSS1_PHY_70_DATA - DDRSS1_PHY_71_DATA - DDRSS1_PHY_72_DATA - DDRSS1_PHY_73_DATA - DDRSS1_PHY_74_DATA - DDRSS1_PHY_75_DATA - DDRSS1_PHY_76_DATA - DDRSS1_PHY_77_DATA - DDRSS1_PHY_78_DATA - DDRSS1_PHY_79_DATA - DDRSS1_PHY_80_DATA - DDRSS1_PHY_81_DATA - DDRSS1_PHY_82_DATA - DDRSS1_PHY_83_DATA - DDRSS1_PHY_84_DATA - DDRSS1_PHY_85_DATA - DDRSS1_PHY_86_DATA - DDRSS1_PHY_87_DATA - DDRSS1_PHY_88_DATA - DDRSS1_PHY_89_DATA - DDRSS1_PHY_90_DATA - DDRSS1_PHY_91_DATA - DDRSS1_PHY_92_DATA - DDRSS1_PHY_93_DATA - DDRSS1_PHY_94_DATA - DDRSS1_PHY_95_DATA - DDRSS1_PHY_96_DATA - DDRSS1_PHY_97_DATA - DDRSS1_PHY_98_DATA - DDRSS1_PHY_99_DATA - DDRSS1_PHY_100_DATA - DDRSS1_PHY_101_DATA - DDRSS1_PHY_102_DATA - DDRSS1_PHY_103_DATA - DDRSS1_PHY_104_DATA - DDRSS1_PHY_105_DATA - DDRSS1_PHY_106_DATA - DDRSS1_PHY_107_DATA - DDRSS1_PHY_108_DATA - DDRSS1_PHY_109_DATA - DDRSS1_PHY_110_DATA - DDRSS1_PHY_111_DATA - DDRSS1_PHY_112_DATA - DDRSS1_PHY_113_DATA - DDRSS1_PHY_114_DATA - DDRSS1_PHY_115_DATA - DDRSS1_PHY_116_DATA - DDRSS1_PHY_117_DATA - DDRSS1_PHY_118_DATA - DDRSS1_PHY_119_DATA - DDRSS1_PHY_120_DATA - DDRSS1_PHY_121_DATA - DDRSS1_PHY_122_DATA - DDRSS1_PHY_123_DATA - DDRSS1_PHY_124_DATA - DDRSS1_PHY_125_DATA - DDRSS1_PHY_126_DATA - DDRSS1_PHY_127_DATA - DDRSS1_PHY_128_DATA - DDRSS1_PHY_129_DATA - DDRSS1_PHY_130_DATA - DDRSS1_PHY_131_DATA - DDRSS1_PHY_132_DATA - DDRSS1_PHY_133_DATA - DDRSS1_PHY_134_DATA - DDRSS1_PHY_135_DATA - DDRSS1_PHY_136_DATA - DDRSS1_PHY_137_DATA - DDRSS1_PHY_138_DATA - DDRSS1_PHY_139_DATA - DDRSS1_PHY_140_DATA - DDRSS1_PHY_141_DATA - DDRSS1_PHY_142_DATA - DDRSS1_PHY_143_DATA - DDRSS1_PHY_144_DATA - DDRSS1_PHY_145_DATA - DDRSS1_PHY_146_DATA - DDRSS1_PHY_147_DATA - DDRSS1_PHY_148_DATA - DDRSS1_PHY_149_DATA - DDRSS1_PHY_150_DATA - DDRSS1_PHY_151_DATA - DDRSS1_PHY_152_DATA - DDRSS1_PHY_153_DATA - DDRSS1_PHY_154_DATA - DDRSS1_PHY_155_DATA - DDRSS1_PHY_156_DATA - DDRSS1_PHY_157_DATA - DDRSS1_PHY_158_DATA - DDRSS1_PHY_159_DATA - DDRSS1_PHY_160_DATA - DDRSS1_PHY_161_DATA - DDRSS1_PHY_162_DATA - DDRSS1_PHY_163_DATA - DDRSS1_PHY_164_DATA - DDRSS1_PHY_165_DATA - DDRSS1_PHY_166_DATA - DDRSS1_PHY_167_DATA - DDRSS1_PHY_168_DATA - DDRSS1_PHY_169_DATA - DDRSS1_PHY_170_DATA - DDRSS1_PHY_171_DATA - DDRSS1_PHY_172_DATA - DDRSS1_PHY_173_DATA - DDRSS1_PHY_174_DATA - DDRSS1_PHY_175_DATA - DDRSS1_PHY_176_DATA - DDRSS1_PHY_177_DATA - DDRSS1_PHY_178_DATA - DDRSS1_PHY_179_DATA - DDRSS1_PHY_180_DATA - DDRSS1_PHY_181_DATA - DDRSS1_PHY_182_DATA - DDRSS1_PHY_183_DATA - DDRSS1_PHY_184_DATA - DDRSS1_PHY_185_DATA - DDRSS1_PHY_186_DATA - DDRSS1_PHY_187_DATA - DDRSS1_PHY_188_DATA - DDRSS1_PHY_189_DATA - DDRSS1_PHY_190_DATA - DDRSS1_PHY_191_DATA - DDRSS1_PHY_192_DATA - DDRSS1_PHY_193_DATA - DDRSS1_PHY_194_DATA - DDRSS1_PHY_195_DATA - DDRSS1_PHY_196_DATA - DDRSS1_PHY_197_DATA - DDRSS1_PHY_198_DATA - DDRSS1_PHY_199_DATA - DDRSS1_PHY_200_DATA - DDRSS1_PHY_201_DATA - DDRSS1_PHY_202_DATA - DDRSS1_PHY_203_DATA - DDRSS1_PHY_204_DATA - DDRSS1_PHY_205_DATA - DDRSS1_PHY_206_DATA - DDRSS1_PHY_207_DATA - DDRSS1_PHY_208_DATA - DDRSS1_PHY_209_DATA - DDRSS1_PHY_210_DATA - DDRSS1_PHY_211_DATA - DDRSS1_PHY_212_DATA - DDRSS1_PHY_213_DATA - DDRSS1_PHY_214_DATA - DDRSS1_PHY_215_DATA - DDRSS1_PHY_216_DATA - DDRSS1_PHY_217_DATA - DDRSS1_PHY_218_DATA - DDRSS1_PHY_219_DATA - DDRSS1_PHY_220_DATA - DDRSS1_PHY_221_DATA - DDRSS1_PHY_222_DATA - DDRSS1_PHY_223_DATA - DDRSS1_PHY_224_DATA - DDRSS1_PHY_225_DATA - DDRSS1_PHY_226_DATA - DDRSS1_PHY_227_DATA - DDRSS1_PHY_228_DATA - DDRSS1_PHY_229_DATA - DDRSS1_PHY_230_DATA - DDRSS1_PHY_231_DATA - DDRSS1_PHY_232_DATA - DDRSS1_PHY_233_DATA - DDRSS1_PHY_234_DATA - DDRSS1_PHY_235_DATA - DDRSS1_PHY_236_DATA - DDRSS1_PHY_237_DATA - DDRSS1_PHY_238_DATA - DDRSS1_PHY_239_DATA - DDRSS1_PHY_240_DATA - DDRSS1_PHY_241_DATA - DDRSS1_PHY_242_DATA - DDRSS1_PHY_243_DATA - DDRSS1_PHY_244_DATA - DDRSS1_PHY_245_DATA - DDRSS1_PHY_246_DATA - DDRSS1_PHY_247_DATA - DDRSS1_PHY_248_DATA - DDRSS1_PHY_249_DATA - DDRSS1_PHY_250_DATA - DDRSS1_PHY_251_DATA - DDRSS1_PHY_252_DATA - DDRSS1_PHY_253_DATA - DDRSS1_PHY_254_DATA - DDRSS1_PHY_255_DATA - DDRSS1_PHY_256_DATA - DDRSS1_PHY_257_DATA - DDRSS1_PHY_258_DATA - DDRSS1_PHY_259_DATA - DDRSS1_PHY_260_DATA - DDRSS1_PHY_261_DATA - DDRSS1_PHY_262_DATA - DDRSS1_PHY_263_DATA - DDRSS1_PHY_264_DATA - DDRSS1_PHY_265_DATA - DDRSS1_PHY_266_DATA - DDRSS1_PHY_267_DATA - DDRSS1_PHY_268_DATA - DDRSS1_PHY_269_DATA - DDRSS1_PHY_270_DATA - DDRSS1_PHY_271_DATA - DDRSS1_PHY_272_DATA - DDRSS1_PHY_273_DATA - DDRSS1_PHY_274_DATA - DDRSS1_PHY_275_DATA - DDRSS1_PHY_276_DATA - DDRSS1_PHY_277_DATA - DDRSS1_PHY_278_DATA - DDRSS1_PHY_279_DATA - DDRSS1_PHY_280_DATA - DDRSS1_PHY_281_DATA - DDRSS1_PHY_282_DATA - DDRSS1_PHY_283_DATA - DDRSS1_PHY_284_DATA - DDRSS1_PHY_285_DATA - DDRSS1_PHY_286_DATA - DDRSS1_PHY_287_DATA - DDRSS1_PHY_288_DATA - DDRSS1_PHY_289_DATA - DDRSS1_PHY_290_DATA - DDRSS1_PHY_291_DATA - DDRSS1_PHY_292_DATA - DDRSS1_PHY_293_DATA - DDRSS1_PHY_294_DATA - DDRSS1_PHY_295_DATA - DDRSS1_PHY_296_DATA - DDRSS1_PHY_297_DATA - DDRSS1_PHY_298_DATA - DDRSS1_PHY_299_DATA - DDRSS1_PHY_300_DATA - DDRSS1_PHY_301_DATA - DDRSS1_PHY_302_DATA - DDRSS1_PHY_303_DATA - DDRSS1_PHY_304_DATA - DDRSS1_PHY_305_DATA - DDRSS1_PHY_306_DATA - DDRSS1_PHY_307_DATA - DDRSS1_PHY_308_DATA - DDRSS1_PHY_309_DATA - DDRSS1_PHY_310_DATA - DDRSS1_PHY_311_DATA - DDRSS1_PHY_312_DATA - DDRSS1_PHY_313_DATA - DDRSS1_PHY_314_DATA - DDRSS1_PHY_315_DATA - DDRSS1_PHY_316_DATA - DDRSS1_PHY_317_DATA - DDRSS1_PHY_318_DATA - DDRSS1_PHY_319_DATA - DDRSS1_PHY_320_DATA - DDRSS1_PHY_321_DATA - DDRSS1_PHY_322_DATA - DDRSS1_PHY_323_DATA - DDRSS1_PHY_324_DATA - DDRSS1_PHY_325_DATA - DDRSS1_PHY_326_DATA - DDRSS1_PHY_327_DATA - DDRSS1_PHY_328_DATA - DDRSS1_PHY_329_DATA - DDRSS1_PHY_330_DATA - DDRSS1_PHY_331_DATA - DDRSS1_PHY_332_DATA - DDRSS1_PHY_333_DATA - DDRSS1_PHY_334_DATA - DDRSS1_PHY_335_DATA - DDRSS1_PHY_336_DATA - DDRSS1_PHY_337_DATA - DDRSS1_PHY_338_DATA - DDRSS1_PHY_339_DATA - DDRSS1_PHY_340_DATA - DDRSS1_PHY_341_DATA - DDRSS1_PHY_342_DATA - DDRSS1_PHY_343_DATA - DDRSS1_PHY_344_DATA - DDRSS1_PHY_345_DATA - DDRSS1_PHY_346_DATA - DDRSS1_PHY_347_DATA - DDRSS1_PHY_348_DATA - DDRSS1_PHY_349_DATA - DDRSS1_PHY_350_DATA - DDRSS1_PHY_351_DATA - DDRSS1_PHY_352_DATA - DDRSS1_PHY_353_DATA - DDRSS1_PHY_354_DATA - DDRSS1_PHY_355_DATA - DDRSS1_PHY_356_DATA - DDRSS1_PHY_357_DATA - DDRSS1_PHY_358_DATA - DDRSS1_PHY_359_DATA - DDRSS1_PHY_360_DATA - DDRSS1_PHY_361_DATA - DDRSS1_PHY_362_DATA - DDRSS1_PHY_363_DATA - DDRSS1_PHY_364_DATA - DDRSS1_PHY_365_DATA - DDRSS1_PHY_366_DATA - DDRSS1_PHY_367_DATA - DDRSS1_PHY_368_DATA - DDRSS1_PHY_369_DATA - DDRSS1_PHY_370_DATA - DDRSS1_PHY_371_DATA - DDRSS1_PHY_372_DATA - DDRSS1_PHY_373_DATA - DDRSS1_PHY_374_DATA - DDRSS1_PHY_375_DATA - DDRSS1_PHY_376_DATA - DDRSS1_PHY_377_DATA - DDRSS1_PHY_378_DATA - DDRSS1_PHY_379_DATA - DDRSS1_PHY_380_DATA - DDRSS1_PHY_381_DATA - DDRSS1_PHY_382_DATA - DDRSS1_PHY_383_DATA - DDRSS1_PHY_384_DATA - DDRSS1_PHY_385_DATA - DDRSS1_PHY_386_DATA - DDRSS1_PHY_387_DATA - DDRSS1_PHY_388_DATA - DDRSS1_PHY_389_DATA - DDRSS1_PHY_390_DATA - DDRSS1_PHY_391_DATA - DDRSS1_PHY_392_DATA - DDRSS1_PHY_393_DATA - DDRSS1_PHY_394_DATA - DDRSS1_PHY_395_DATA - DDRSS1_PHY_396_DATA - DDRSS1_PHY_397_DATA - DDRSS1_PHY_398_DATA - DDRSS1_PHY_399_DATA - DDRSS1_PHY_400_DATA - DDRSS1_PHY_401_DATA - DDRSS1_PHY_402_DATA - DDRSS1_PHY_403_DATA - DDRSS1_PHY_404_DATA - DDRSS1_PHY_405_DATA - DDRSS1_PHY_406_DATA - DDRSS1_PHY_407_DATA - DDRSS1_PHY_408_DATA - DDRSS1_PHY_409_DATA - DDRSS1_PHY_410_DATA - DDRSS1_PHY_411_DATA - DDRSS1_PHY_412_DATA - DDRSS1_PHY_413_DATA - DDRSS1_PHY_414_DATA - DDRSS1_PHY_415_DATA - DDRSS1_PHY_416_DATA - DDRSS1_PHY_417_DATA - DDRSS1_PHY_418_DATA - DDRSS1_PHY_419_DATA - DDRSS1_PHY_420_DATA - DDRSS1_PHY_421_DATA - DDRSS1_PHY_422_DATA - DDRSS1_PHY_423_DATA - DDRSS1_PHY_424_DATA - DDRSS1_PHY_425_DATA - DDRSS1_PHY_426_DATA - DDRSS1_PHY_427_DATA - DDRSS1_PHY_428_DATA - DDRSS1_PHY_429_DATA - DDRSS1_PHY_430_DATA - DDRSS1_PHY_431_DATA - DDRSS1_PHY_432_DATA - DDRSS1_PHY_433_DATA - DDRSS1_PHY_434_DATA - DDRSS1_PHY_435_DATA - DDRSS1_PHY_436_DATA - DDRSS1_PHY_437_DATA - DDRSS1_PHY_438_DATA - DDRSS1_PHY_439_DATA - DDRSS1_PHY_440_DATA - DDRSS1_PHY_441_DATA - DDRSS1_PHY_442_DATA - DDRSS1_PHY_443_DATA - DDRSS1_PHY_444_DATA - DDRSS1_PHY_445_DATA - DDRSS1_PHY_446_DATA - DDRSS1_PHY_447_DATA - DDRSS1_PHY_448_DATA - DDRSS1_PHY_449_DATA - DDRSS1_PHY_450_DATA - DDRSS1_PHY_451_DATA - DDRSS1_PHY_452_DATA - DDRSS1_PHY_453_DATA - DDRSS1_PHY_454_DATA - DDRSS1_PHY_455_DATA - DDRSS1_PHY_456_DATA - DDRSS1_PHY_457_DATA - DDRSS1_PHY_458_DATA - DDRSS1_PHY_459_DATA - DDRSS1_PHY_460_DATA - DDRSS1_PHY_461_DATA - DDRSS1_PHY_462_DATA - DDRSS1_PHY_463_DATA - DDRSS1_PHY_464_DATA - DDRSS1_PHY_465_DATA - DDRSS1_PHY_466_DATA - DDRSS1_PHY_467_DATA - DDRSS1_PHY_468_DATA - DDRSS1_PHY_469_DATA - DDRSS1_PHY_470_DATA - DDRSS1_PHY_471_DATA - DDRSS1_PHY_472_DATA - DDRSS1_PHY_473_DATA - DDRSS1_PHY_474_DATA - DDRSS1_PHY_475_DATA - DDRSS1_PHY_476_DATA - DDRSS1_PHY_477_DATA - DDRSS1_PHY_478_DATA - DDRSS1_PHY_479_DATA - DDRSS1_PHY_480_DATA - DDRSS1_PHY_481_DATA - DDRSS1_PHY_482_DATA - DDRSS1_PHY_483_DATA - DDRSS1_PHY_484_DATA - DDRSS1_PHY_485_DATA - DDRSS1_PHY_486_DATA - DDRSS1_PHY_487_DATA - DDRSS1_PHY_488_DATA - DDRSS1_PHY_489_DATA - DDRSS1_PHY_490_DATA - DDRSS1_PHY_491_DATA - DDRSS1_PHY_492_DATA - DDRSS1_PHY_493_DATA - DDRSS1_PHY_494_DATA - DDRSS1_PHY_495_DATA - DDRSS1_PHY_496_DATA - DDRSS1_PHY_497_DATA - DDRSS1_PHY_498_DATA - DDRSS1_PHY_499_DATA - DDRSS1_PHY_500_DATA - DDRSS1_PHY_501_DATA - DDRSS1_PHY_502_DATA - DDRSS1_PHY_503_DATA - DDRSS1_PHY_504_DATA - DDRSS1_PHY_505_DATA - DDRSS1_PHY_506_DATA - DDRSS1_PHY_507_DATA - DDRSS1_PHY_508_DATA - DDRSS1_PHY_509_DATA - DDRSS1_PHY_510_DATA - DDRSS1_PHY_511_DATA - DDRSS1_PHY_512_DATA - DDRSS1_PHY_513_DATA - DDRSS1_PHY_514_DATA - DDRSS1_PHY_515_DATA - DDRSS1_PHY_516_DATA - DDRSS1_PHY_517_DATA - DDRSS1_PHY_518_DATA - DDRSS1_PHY_519_DATA - DDRSS1_PHY_520_DATA - DDRSS1_PHY_521_DATA - DDRSS1_PHY_522_DATA - DDRSS1_PHY_523_DATA - DDRSS1_PHY_524_DATA - DDRSS1_PHY_525_DATA - DDRSS1_PHY_526_DATA - DDRSS1_PHY_527_DATA - DDRSS1_PHY_528_DATA - DDRSS1_PHY_529_DATA - DDRSS1_PHY_530_DATA - DDRSS1_PHY_531_DATA - DDRSS1_PHY_532_DATA - DDRSS1_PHY_533_DATA - DDRSS1_PHY_534_DATA - DDRSS1_PHY_535_DATA - DDRSS1_PHY_536_DATA - DDRSS1_PHY_537_DATA - DDRSS1_PHY_538_DATA - DDRSS1_PHY_539_DATA - DDRSS1_PHY_540_DATA - DDRSS1_PHY_541_DATA - DDRSS1_PHY_542_DATA - DDRSS1_PHY_543_DATA - DDRSS1_PHY_544_DATA - DDRSS1_PHY_545_DATA - DDRSS1_PHY_546_DATA - DDRSS1_PHY_547_DATA - DDRSS1_PHY_548_DATA - DDRSS1_PHY_549_DATA - DDRSS1_PHY_550_DATA - DDRSS1_PHY_551_DATA - DDRSS1_PHY_552_DATA - DDRSS1_PHY_553_DATA - DDRSS1_PHY_554_DATA - DDRSS1_PHY_555_DATA - DDRSS1_PHY_556_DATA - DDRSS1_PHY_557_DATA - DDRSS1_PHY_558_DATA - DDRSS1_PHY_559_DATA - DDRSS1_PHY_560_DATA - DDRSS1_PHY_561_DATA - DDRSS1_PHY_562_DATA - DDRSS1_PHY_563_DATA - DDRSS1_PHY_564_DATA - DDRSS1_PHY_565_DATA - DDRSS1_PHY_566_DATA - DDRSS1_PHY_567_DATA - DDRSS1_PHY_568_DATA - DDRSS1_PHY_569_DATA - DDRSS1_PHY_570_DATA - DDRSS1_PHY_571_DATA - DDRSS1_PHY_572_DATA - DDRSS1_PHY_573_DATA - DDRSS1_PHY_574_DATA - DDRSS1_PHY_575_DATA - DDRSS1_PHY_576_DATA - DDRSS1_PHY_577_DATA - DDRSS1_PHY_578_DATA - DDRSS1_PHY_579_DATA - DDRSS1_PHY_580_DATA - DDRSS1_PHY_581_DATA - DDRSS1_PHY_582_DATA - DDRSS1_PHY_583_DATA - DDRSS1_PHY_584_DATA - DDRSS1_PHY_585_DATA - DDRSS1_PHY_586_DATA - DDRSS1_PHY_587_DATA - DDRSS1_PHY_588_DATA - DDRSS1_PHY_589_DATA - DDRSS1_PHY_590_DATA - DDRSS1_PHY_591_DATA - DDRSS1_PHY_592_DATA - DDRSS1_PHY_593_DATA - DDRSS1_PHY_594_DATA - DDRSS1_PHY_595_DATA - DDRSS1_PHY_596_DATA - DDRSS1_PHY_597_DATA - DDRSS1_PHY_598_DATA - DDRSS1_PHY_599_DATA - DDRSS1_PHY_600_DATA - DDRSS1_PHY_601_DATA - DDRSS1_PHY_602_DATA - DDRSS1_PHY_603_DATA - DDRSS1_PHY_604_DATA - DDRSS1_PHY_605_DATA - DDRSS1_PHY_606_DATA - DDRSS1_PHY_607_DATA - DDRSS1_PHY_608_DATA - DDRSS1_PHY_609_DATA - DDRSS1_PHY_610_DATA - DDRSS1_PHY_611_DATA - DDRSS1_PHY_612_DATA - DDRSS1_PHY_613_DATA - DDRSS1_PHY_614_DATA - DDRSS1_PHY_615_DATA - DDRSS1_PHY_616_DATA - DDRSS1_PHY_617_DATA - DDRSS1_PHY_618_DATA - DDRSS1_PHY_619_DATA - DDRSS1_PHY_620_DATA - DDRSS1_PHY_621_DATA - DDRSS1_PHY_622_DATA - DDRSS1_PHY_623_DATA - DDRSS1_PHY_624_DATA - DDRSS1_PHY_625_DATA - DDRSS1_PHY_626_DATA - DDRSS1_PHY_627_DATA - DDRSS1_PHY_628_DATA - DDRSS1_PHY_629_DATA - DDRSS1_PHY_630_DATA - DDRSS1_PHY_631_DATA - DDRSS1_PHY_632_DATA - DDRSS1_PHY_633_DATA - DDRSS1_PHY_634_DATA - DDRSS1_PHY_635_DATA - DDRSS1_PHY_636_DATA - DDRSS1_PHY_637_DATA - DDRSS1_PHY_638_DATA - DDRSS1_PHY_639_DATA - DDRSS1_PHY_640_DATA - DDRSS1_PHY_641_DATA - DDRSS1_PHY_642_DATA - DDRSS1_PHY_643_DATA - DDRSS1_PHY_644_DATA - DDRSS1_PHY_645_DATA - DDRSS1_PHY_646_DATA - DDRSS1_PHY_647_DATA - DDRSS1_PHY_648_DATA - DDRSS1_PHY_649_DATA - DDRSS1_PHY_650_DATA - DDRSS1_PHY_651_DATA - DDRSS1_PHY_652_DATA - DDRSS1_PHY_653_DATA - DDRSS1_PHY_654_DATA - DDRSS1_PHY_655_DATA - DDRSS1_PHY_656_DATA - DDRSS1_PHY_657_DATA - DDRSS1_PHY_658_DATA - DDRSS1_PHY_659_DATA - DDRSS1_PHY_660_DATA - DDRSS1_PHY_661_DATA - DDRSS1_PHY_662_DATA - DDRSS1_PHY_663_DATA - DDRSS1_PHY_664_DATA - DDRSS1_PHY_665_DATA - DDRSS1_PHY_666_DATA - DDRSS1_PHY_667_DATA - DDRSS1_PHY_668_DATA - DDRSS1_PHY_669_DATA - DDRSS1_PHY_670_DATA - DDRSS1_PHY_671_DATA - DDRSS1_PHY_672_DATA - DDRSS1_PHY_673_DATA - DDRSS1_PHY_674_DATA - DDRSS1_PHY_675_DATA - DDRSS1_PHY_676_DATA - DDRSS1_PHY_677_DATA - DDRSS1_PHY_678_DATA - DDRSS1_PHY_679_DATA - DDRSS1_PHY_680_DATA - DDRSS1_PHY_681_DATA - DDRSS1_PHY_682_DATA - DDRSS1_PHY_683_DATA - DDRSS1_PHY_684_DATA - DDRSS1_PHY_685_DATA - DDRSS1_PHY_686_DATA - DDRSS1_PHY_687_DATA - DDRSS1_PHY_688_DATA - DDRSS1_PHY_689_DATA - DDRSS1_PHY_690_DATA - DDRSS1_PHY_691_DATA - DDRSS1_PHY_692_DATA - DDRSS1_PHY_693_DATA - DDRSS1_PHY_694_DATA - DDRSS1_PHY_695_DATA - DDRSS1_PHY_696_DATA - DDRSS1_PHY_697_DATA - DDRSS1_PHY_698_DATA - DDRSS1_PHY_699_DATA - DDRSS1_PHY_700_DATA - DDRSS1_PHY_701_DATA - DDRSS1_PHY_702_DATA - DDRSS1_PHY_703_DATA - DDRSS1_PHY_704_DATA - DDRSS1_PHY_705_DATA - DDRSS1_PHY_706_DATA - DDRSS1_PHY_707_DATA - DDRSS1_PHY_708_DATA - DDRSS1_PHY_709_DATA - DDRSS1_PHY_710_DATA - DDRSS1_PHY_711_DATA - DDRSS1_PHY_712_DATA - DDRSS1_PHY_713_DATA - DDRSS1_PHY_714_DATA - DDRSS1_PHY_715_DATA - DDRSS1_PHY_716_DATA - DDRSS1_PHY_717_DATA - DDRSS1_PHY_718_DATA - DDRSS1_PHY_719_DATA - DDRSS1_PHY_720_DATA - DDRSS1_PHY_721_DATA - DDRSS1_PHY_722_DATA - DDRSS1_PHY_723_DATA - DDRSS1_PHY_724_DATA - DDRSS1_PHY_725_DATA - DDRSS1_PHY_726_DATA - DDRSS1_PHY_727_DATA - DDRSS1_PHY_728_DATA - DDRSS1_PHY_729_DATA - DDRSS1_PHY_730_DATA - DDRSS1_PHY_731_DATA - DDRSS1_PHY_732_DATA - DDRSS1_PHY_733_DATA - DDRSS1_PHY_734_DATA - DDRSS1_PHY_735_DATA - DDRSS1_PHY_736_DATA - DDRSS1_PHY_737_DATA - DDRSS1_PHY_738_DATA - DDRSS1_PHY_739_DATA - DDRSS1_PHY_740_DATA - DDRSS1_PHY_741_DATA - DDRSS1_PHY_742_DATA - DDRSS1_PHY_743_DATA - DDRSS1_PHY_744_DATA - DDRSS1_PHY_745_DATA - DDRSS1_PHY_746_DATA - DDRSS1_PHY_747_DATA - DDRSS1_PHY_748_DATA - DDRSS1_PHY_749_DATA - DDRSS1_PHY_750_DATA - DDRSS1_PHY_751_DATA - DDRSS1_PHY_752_DATA - DDRSS1_PHY_753_DATA - DDRSS1_PHY_754_DATA - DDRSS1_PHY_755_DATA - DDRSS1_PHY_756_DATA - DDRSS1_PHY_757_DATA - DDRSS1_PHY_758_DATA - DDRSS1_PHY_759_DATA - DDRSS1_PHY_760_DATA - DDRSS1_PHY_761_DATA - DDRSS1_PHY_762_DATA - DDRSS1_PHY_763_DATA - DDRSS1_PHY_764_DATA - DDRSS1_PHY_765_DATA - DDRSS1_PHY_766_DATA - DDRSS1_PHY_767_DATA - DDRSS1_PHY_768_DATA - DDRSS1_PHY_769_DATA - DDRSS1_PHY_770_DATA - DDRSS1_PHY_771_DATA - DDRSS1_PHY_772_DATA - DDRSS1_PHY_773_DATA - DDRSS1_PHY_774_DATA - DDRSS1_PHY_775_DATA - DDRSS1_PHY_776_DATA - DDRSS1_PHY_777_DATA - DDRSS1_PHY_778_DATA - DDRSS1_PHY_779_DATA - DDRSS1_PHY_780_DATA - DDRSS1_PHY_781_DATA - DDRSS1_PHY_782_DATA - DDRSS1_PHY_783_DATA - DDRSS1_PHY_784_DATA - DDRSS1_PHY_785_DATA - DDRSS1_PHY_786_DATA - DDRSS1_PHY_787_DATA - DDRSS1_PHY_788_DATA - DDRSS1_PHY_789_DATA - DDRSS1_PHY_790_DATA - DDRSS1_PHY_791_DATA - DDRSS1_PHY_792_DATA - DDRSS1_PHY_793_DATA - DDRSS1_PHY_794_DATA - DDRSS1_PHY_795_DATA - DDRSS1_PHY_796_DATA - DDRSS1_PHY_797_DATA - DDRSS1_PHY_798_DATA - DDRSS1_PHY_799_DATA - DDRSS1_PHY_800_DATA - DDRSS1_PHY_801_DATA - DDRSS1_PHY_802_DATA - DDRSS1_PHY_803_DATA - DDRSS1_PHY_804_DATA - DDRSS1_PHY_805_DATA - DDRSS1_PHY_806_DATA - DDRSS1_PHY_807_DATA - DDRSS1_PHY_808_DATA - DDRSS1_PHY_809_DATA - DDRSS1_PHY_810_DATA - DDRSS1_PHY_811_DATA - DDRSS1_PHY_812_DATA - DDRSS1_PHY_813_DATA - DDRSS1_PHY_814_DATA - DDRSS1_PHY_815_DATA - DDRSS1_PHY_816_DATA - DDRSS1_PHY_817_DATA - DDRSS1_PHY_818_DATA - DDRSS1_PHY_819_DATA - DDRSS1_PHY_820_DATA - DDRSS1_PHY_821_DATA - DDRSS1_PHY_822_DATA - DDRSS1_PHY_823_DATA - DDRSS1_PHY_824_DATA - DDRSS1_PHY_825_DATA - DDRSS1_PHY_826_DATA - DDRSS1_PHY_827_DATA - DDRSS1_PHY_828_DATA - DDRSS1_PHY_829_DATA - DDRSS1_PHY_830_DATA - DDRSS1_PHY_831_DATA - DDRSS1_PHY_832_DATA - DDRSS1_PHY_833_DATA - DDRSS1_PHY_834_DATA - DDRSS1_PHY_835_DATA - DDRSS1_PHY_836_DATA - DDRSS1_PHY_837_DATA - DDRSS1_PHY_838_DATA - DDRSS1_PHY_839_DATA - DDRSS1_PHY_840_DATA - DDRSS1_PHY_841_DATA - DDRSS1_PHY_842_DATA - DDRSS1_PHY_843_DATA - DDRSS1_PHY_844_DATA - DDRSS1_PHY_845_DATA - DDRSS1_PHY_846_DATA - DDRSS1_PHY_847_DATA - DDRSS1_PHY_848_DATA - DDRSS1_PHY_849_DATA - DDRSS1_PHY_850_DATA - DDRSS1_PHY_851_DATA - DDRSS1_PHY_852_DATA - DDRSS1_PHY_853_DATA - DDRSS1_PHY_854_DATA - DDRSS1_PHY_855_DATA - DDRSS1_PHY_856_DATA - DDRSS1_PHY_857_DATA - DDRSS1_PHY_858_DATA - DDRSS1_PHY_859_DATA - DDRSS1_PHY_860_DATA - DDRSS1_PHY_861_DATA - DDRSS1_PHY_862_DATA - DDRSS1_PHY_863_DATA - DDRSS1_PHY_864_DATA - DDRSS1_PHY_865_DATA - DDRSS1_PHY_866_DATA - DDRSS1_PHY_867_DATA - DDRSS1_PHY_868_DATA - DDRSS1_PHY_869_DATA - DDRSS1_PHY_870_DATA - DDRSS1_PHY_871_DATA - DDRSS1_PHY_872_DATA - DDRSS1_PHY_873_DATA - DDRSS1_PHY_874_DATA - DDRSS1_PHY_875_DATA - DDRSS1_PHY_876_DATA - DDRSS1_PHY_877_DATA - DDRSS1_PHY_878_DATA - DDRSS1_PHY_879_DATA - DDRSS1_PHY_880_DATA - DDRSS1_PHY_881_DATA - DDRSS1_PHY_882_DATA - DDRSS1_PHY_883_DATA - DDRSS1_PHY_884_DATA - DDRSS1_PHY_885_DATA - DDRSS1_PHY_886_DATA - DDRSS1_PHY_887_DATA - DDRSS1_PHY_888_DATA - DDRSS1_PHY_889_DATA - DDRSS1_PHY_890_DATA - DDRSS1_PHY_891_DATA - DDRSS1_PHY_892_DATA - DDRSS1_PHY_893_DATA - DDRSS1_PHY_894_DATA - DDRSS1_PHY_895_DATA - DDRSS1_PHY_896_DATA - DDRSS1_PHY_897_DATA - DDRSS1_PHY_898_DATA - DDRSS1_PHY_899_DATA - DDRSS1_PHY_900_DATA - DDRSS1_PHY_901_DATA - DDRSS1_PHY_902_DATA - DDRSS1_PHY_903_DATA - DDRSS1_PHY_904_DATA - DDRSS1_PHY_905_DATA - DDRSS1_PHY_906_DATA - DDRSS1_PHY_907_DATA - DDRSS1_PHY_908_DATA - DDRSS1_PHY_909_DATA - DDRSS1_PHY_910_DATA - DDRSS1_PHY_911_DATA - DDRSS1_PHY_912_DATA - DDRSS1_PHY_913_DATA - DDRSS1_PHY_914_DATA - DDRSS1_PHY_915_DATA - DDRSS1_PHY_916_DATA - DDRSS1_PHY_917_DATA - DDRSS1_PHY_918_DATA - DDRSS1_PHY_919_DATA - DDRSS1_PHY_920_DATA - DDRSS1_PHY_921_DATA - DDRSS1_PHY_922_DATA - DDRSS1_PHY_923_DATA - DDRSS1_PHY_924_DATA - DDRSS1_PHY_925_DATA - DDRSS1_PHY_926_DATA - DDRSS1_PHY_927_DATA - DDRSS1_PHY_928_DATA - DDRSS1_PHY_929_DATA - DDRSS1_PHY_930_DATA - DDRSS1_PHY_931_DATA - DDRSS1_PHY_932_DATA - DDRSS1_PHY_933_DATA - DDRSS1_PHY_934_DATA - DDRSS1_PHY_935_DATA - DDRSS1_PHY_936_DATA - DDRSS1_PHY_937_DATA - DDRSS1_PHY_938_DATA - DDRSS1_PHY_939_DATA - DDRSS1_PHY_940_DATA - DDRSS1_PHY_941_DATA - DDRSS1_PHY_942_DATA - DDRSS1_PHY_943_DATA - DDRSS1_PHY_944_DATA - DDRSS1_PHY_945_DATA - DDRSS1_PHY_946_DATA - DDRSS1_PHY_947_DATA - DDRSS1_PHY_948_DATA - DDRSS1_PHY_949_DATA - DDRSS1_PHY_950_DATA - DDRSS1_PHY_951_DATA - DDRSS1_PHY_952_DATA - DDRSS1_PHY_953_DATA - DDRSS1_PHY_954_DATA - DDRSS1_PHY_955_DATA - DDRSS1_PHY_956_DATA - DDRSS1_PHY_957_DATA - DDRSS1_PHY_958_DATA - DDRSS1_PHY_959_DATA - DDRSS1_PHY_960_DATA - DDRSS1_PHY_961_DATA - DDRSS1_PHY_962_DATA - DDRSS1_PHY_963_DATA - DDRSS1_PHY_964_DATA - DDRSS1_PHY_965_DATA - DDRSS1_PHY_966_DATA - DDRSS1_PHY_967_DATA - DDRSS1_PHY_968_DATA - DDRSS1_PHY_969_DATA - DDRSS1_PHY_970_DATA - DDRSS1_PHY_971_DATA - DDRSS1_PHY_972_DATA - DDRSS1_PHY_973_DATA - DDRSS1_PHY_974_DATA - DDRSS1_PHY_975_DATA - DDRSS1_PHY_976_DATA - DDRSS1_PHY_977_DATA - DDRSS1_PHY_978_DATA - DDRSS1_PHY_979_DATA - DDRSS1_PHY_980_DATA - DDRSS1_PHY_981_DATA - DDRSS1_PHY_982_DATA - DDRSS1_PHY_983_DATA - DDRSS1_PHY_984_DATA - DDRSS1_PHY_985_DATA - DDRSS1_PHY_986_DATA - DDRSS1_PHY_987_DATA - DDRSS1_PHY_988_DATA - DDRSS1_PHY_989_DATA - DDRSS1_PHY_990_DATA - DDRSS1_PHY_991_DATA - DDRSS1_PHY_992_DATA - DDRSS1_PHY_993_DATA - DDRSS1_PHY_994_DATA - DDRSS1_PHY_995_DATA - DDRSS1_PHY_996_DATA - DDRSS1_PHY_997_DATA - DDRSS1_PHY_998_DATA - DDRSS1_PHY_999_DATA - DDRSS1_PHY_1000_DATA - DDRSS1_PHY_1001_DATA - DDRSS1_PHY_1002_DATA - DDRSS1_PHY_1003_DATA - DDRSS1_PHY_1004_DATA - DDRSS1_PHY_1005_DATA - DDRSS1_PHY_1006_DATA - DDRSS1_PHY_1007_DATA - DDRSS1_PHY_1008_DATA - DDRSS1_PHY_1009_DATA - DDRSS1_PHY_1010_DATA - DDRSS1_PHY_1011_DATA - DDRSS1_PHY_1012_DATA - DDRSS1_PHY_1013_DATA - DDRSS1_PHY_1014_DATA - DDRSS1_PHY_1015_DATA - DDRSS1_PHY_1016_DATA - DDRSS1_PHY_1017_DATA - DDRSS1_PHY_1018_DATA - DDRSS1_PHY_1019_DATA - DDRSS1_PHY_1020_DATA - DDRSS1_PHY_1021_DATA - DDRSS1_PHY_1022_DATA - DDRSS1_PHY_1023_DATA - DDRSS1_PHY_1024_DATA - DDRSS1_PHY_1025_DATA - DDRSS1_PHY_1026_DATA - DDRSS1_PHY_1027_DATA - DDRSS1_PHY_1028_DATA - DDRSS1_PHY_1029_DATA - DDRSS1_PHY_1030_DATA - DDRSS1_PHY_1031_DATA - DDRSS1_PHY_1032_DATA - DDRSS1_PHY_1033_DATA - DDRSS1_PHY_1034_DATA - DDRSS1_PHY_1035_DATA - DDRSS1_PHY_1036_DATA - DDRSS1_PHY_1037_DATA - DDRSS1_PHY_1038_DATA - DDRSS1_PHY_1039_DATA - DDRSS1_PHY_1040_DATA - DDRSS1_PHY_1041_DATA - DDRSS1_PHY_1042_DATA - DDRSS1_PHY_1043_DATA - DDRSS1_PHY_1044_DATA - DDRSS1_PHY_1045_DATA - DDRSS1_PHY_1046_DATA - DDRSS1_PHY_1047_DATA - DDRSS1_PHY_1048_DATA - DDRSS1_PHY_1049_DATA - DDRSS1_PHY_1050_DATA - DDRSS1_PHY_1051_DATA - DDRSS1_PHY_1052_DATA - DDRSS1_PHY_1053_DATA - DDRSS1_PHY_1054_DATA - DDRSS1_PHY_1055_DATA - DDRSS1_PHY_1056_DATA - DDRSS1_PHY_1057_DATA - DDRSS1_PHY_1058_DATA - DDRSS1_PHY_1059_DATA - DDRSS1_PHY_1060_DATA - DDRSS1_PHY_1061_DATA - DDRSS1_PHY_1062_DATA - DDRSS1_PHY_1063_DATA - DDRSS1_PHY_1064_DATA - DDRSS1_PHY_1065_DATA - DDRSS1_PHY_1066_DATA - DDRSS1_PHY_1067_DATA - DDRSS1_PHY_1068_DATA - DDRSS1_PHY_1069_DATA - DDRSS1_PHY_1070_DATA - DDRSS1_PHY_1071_DATA - DDRSS1_PHY_1072_DATA - DDRSS1_PHY_1073_DATA - DDRSS1_PHY_1074_DATA - DDRSS1_PHY_1075_DATA - DDRSS1_PHY_1076_DATA - DDRSS1_PHY_1077_DATA - DDRSS1_PHY_1078_DATA - DDRSS1_PHY_1079_DATA - DDRSS1_PHY_1080_DATA - DDRSS1_PHY_1081_DATA - DDRSS1_PHY_1082_DATA - DDRSS1_PHY_1083_DATA - DDRSS1_PHY_1084_DATA - DDRSS1_PHY_1085_DATA - DDRSS1_PHY_1086_DATA - DDRSS1_PHY_1087_DATA - DDRSS1_PHY_1088_DATA - DDRSS1_PHY_1089_DATA - DDRSS1_PHY_1090_DATA - DDRSS1_PHY_1091_DATA - DDRSS1_PHY_1092_DATA - DDRSS1_PHY_1093_DATA - DDRSS1_PHY_1094_DATA - DDRSS1_PHY_1095_DATA - DDRSS1_PHY_1096_DATA - DDRSS1_PHY_1097_DATA - DDRSS1_PHY_1098_DATA - DDRSS1_PHY_1099_DATA - DDRSS1_PHY_1100_DATA - DDRSS1_PHY_1101_DATA - DDRSS1_PHY_1102_DATA - DDRSS1_PHY_1103_DATA - DDRSS1_PHY_1104_DATA - DDRSS1_PHY_1105_DATA - DDRSS1_PHY_1106_DATA - DDRSS1_PHY_1107_DATA - DDRSS1_PHY_1108_DATA - DDRSS1_PHY_1109_DATA - DDRSS1_PHY_1110_DATA - DDRSS1_PHY_1111_DATA - DDRSS1_PHY_1112_DATA - DDRSS1_PHY_1113_DATA - DDRSS1_PHY_1114_DATA - DDRSS1_PHY_1115_DATA - DDRSS1_PHY_1116_DATA - DDRSS1_PHY_1117_DATA - DDRSS1_PHY_1118_DATA - DDRSS1_PHY_1119_DATA - DDRSS1_PHY_1120_DATA - DDRSS1_PHY_1121_DATA - DDRSS1_PHY_1122_DATA - DDRSS1_PHY_1123_DATA - DDRSS1_PHY_1124_DATA - DDRSS1_PHY_1125_DATA - DDRSS1_PHY_1126_DATA - DDRSS1_PHY_1127_DATA - DDRSS1_PHY_1128_DATA - DDRSS1_PHY_1129_DATA - DDRSS1_PHY_1130_DATA - DDRSS1_PHY_1131_DATA - DDRSS1_PHY_1132_DATA - DDRSS1_PHY_1133_DATA - DDRSS1_PHY_1134_DATA - DDRSS1_PHY_1135_DATA - DDRSS1_PHY_1136_DATA - DDRSS1_PHY_1137_DATA - DDRSS1_PHY_1138_DATA - DDRSS1_PHY_1139_DATA - DDRSS1_PHY_1140_DATA - DDRSS1_PHY_1141_DATA - DDRSS1_PHY_1142_DATA - DDRSS1_PHY_1143_DATA - DDRSS1_PHY_1144_DATA - DDRSS1_PHY_1145_DATA - DDRSS1_PHY_1146_DATA - DDRSS1_PHY_1147_DATA - DDRSS1_PHY_1148_DATA - DDRSS1_PHY_1149_DATA - DDRSS1_PHY_1150_DATA - DDRSS1_PHY_1151_DATA - DDRSS1_PHY_1152_DATA - DDRSS1_PHY_1153_DATA - DDRSS1_PHY_1154_DATA - DDRSS1_PHY_1155_DATA - DDRSS1_PHY_1156_DATA - DDRSS1_PHY_1157_DATA - DDRSS1_PHY_1158_DATA - DDRSS1_PHY_1159_DATA - DDRSS1_PHY_1160_DATA - DDRSS1_PHY_1161_DATA - DDRSS1_PHY_1162_DATA - DDRSS1_PHY_1163_DATA - DDRSS1_PHY_1164_DATA - DDRSS1_PHY_1165_DATA - DDRSS1_PHY_1166_DATA - DDRSS1_PHY_1167_DATA - DDRSS1_PHY_1168_DATA - DDRSS1_PHY_1169_DATA - DDRSS1_PHY_1170_DATA - DDRSS1_PHY_1171_DATA - DDRSS1_PHY_1172_DATA - DDRSS1_PHY_1173_DATA - DDRSS1_PHY_1174_DATA - DDRSS1_PHY_1175_DATA - DDRSS1_PHY_1176_DATA - DDRSS1_PHY_1177_DATA - DDRSS1_PHY_1178_DATA - DDRSS1_PHY_1179_DATA - DDRSS1_PHY_1180_DATA - DDRSS1_PHY_1181_DATA - DDRSS1_PHY_1182_DATA - DDRSS1_PHY_1183_DATA - DDRSS1_PHY_1184_DATA - DDRSS1_PHY_1185_DATA - DDRSS1_PHY_1186_DATA - DDRSS1_PHY_1187_DATA - DDRSS1_PHY_1188_DATA - DDRSS1_PHY_1189_DATA - DDRSS1_PHY_1190_DATA - DDRSS1_PHY_1191_DATA - DDRSS1_PHY_1192_DATA - DDRSS1_PHY_1193_DATA - DDRSS1_PHY_1194_DATA - DDRSS1_PHY_1195_DATA - DDRSS1_PHY_1196_DATA - DDRSS1_PHY_1197_DATA - DDRSS1_PHY_1198_DATA - DDRSS1_PHY_1199_DATA - DDRSS1_PHY_1200_DATA - DDRSS1_PHY_1201_DATA - DDRSS1_PHY_1202_DATA - DDRSS1_PHY_1203_DATA - DDRSS1_PHY_1204_DATA - DDRSS1_PHY_1205_DATA - DDRSS1_PHY_1206_DATA - DDRSS1_PHY_1207_DATA - DDRSS1_PHY_1208_DATA - DDRSS1_PHY_1209_DATA - DDRSS1_PHY_1210_DATA - DDRSS1_PHY_1211_DATA - DDRSS1_PHY_1212_DATA - DDRSS1_PHY_1213_DATA - DDRSS1_PHY_1214_DATA - DDRSS1_PHY_1215_DATA - DDRSS1_PHY_1216_DATA - DDRSS1_PHY_1217_DATA - DDRSS1_PHY_1218_DATA - DDRSS1_PHY_1219_DATA - DDRSS1_PHY_1220_DATA - DDRSS1_PHY_1221_DATA - DDRSS1_PHY_1222_DATA - DDRSS1_PHY_1223_DATA - DDRSS1_PHY_1224_DATA - DDRSS1_PHY_1225_DATA - DDRSS1_PHY_1226_DATA - DDRSS1_PHY_1227_DATA - DDRSS1_PHY_1228_DATA - DDRSS1_PHY_1229_DATA - DDRSS1_PHY_1230_DATA - DDRSS1_PHY_1231_DATA - DDRSS1_PHY_1232_DATA - DDRSS1_PHY_1233_DATA - DDRSS1_PHY_1234_DATA - DDRSS1_PHY_1235_DATA - DDRSS1_PHY_1236_DATA - DDRSS1_PHY_1237_DATA - DDRSS1_PHY_1238_DATA - DDRSS1_PHY_1239_DATA - DDRSS1_PHY_1240_DATA - DDRSS1_PHY_1241_DATA - DDRSS1_PHY_1242_DATA - DDRSS1_PHY_1243_DATA - DDRSS1_PHY_1244_DATA - DDRSS1_PHY_1245_DATA - DDRSS1_PHY_1246_DATA - DDRSS1_PHY_1247_DATA - DDRSS1_PHY_1248_DATA - DDRSS1_PHY_1249_DATA - DDRSS1_PHY_1250_DATA - DDRSS1_PHY_1251_DATA - DDRSS1_PHY_1252_DATA - DDRSS1_PHY_1253_DATA - DDRSS1_PHY_1254_DATA - DDRSS1_PHY_1255_DATA - DDRSS1_PHY_1256_DATA - DDRSS1_PHY_1257_DATA - DDRSS1_PHY_1258_DATA - DDRSS1_PHY_1259_DATA - DDRSS1_PHY_1260_DATA - DDRSS1_PHY_1261_DATA - DDRSS1_PHY_1262_DATA - DDRSS1_PHY_1263_DATA - DDRSS1_PHY_1264_DATA - DDRSS1_PHY_1265_DATA - DDRSS1_PHY_1266_DATA - DDRSS1_PHY_1267_DATA - DDRSS1_PHY_1268_DATA - DDRSS1_PHY_1269_DATA - DDRSS1_PHY_1270_DATA - DDRSS1_PHY_1271_DATA - DDRSS1_PHY_1272_DATA - DDRSS1_PHY_1273_DATA - DDRSS1_PHY_1274_DATA - DDRSS1_PHY_1275_DATA - DDRSS1_PHY_1276_DATA - DDRSS1_PHY_1277_DATA - DDRSS1_PHY_1278_DATA - DDRSS1_PHY_1279_DATA - DDRSS1_PHY_1280_DATA - DDRSS1_PHY_1281_DATA - DDRSS1_PHY_1282_DATA - DDRSS1_PHY_1283_DATA - DDRSS1_PHY_1284_DATA - DDRSS1_PHY_1285_DATA - DDRSS1_PHY_1286_DATA - DDRSS1_PHY_1287_DATA - DDRSS1_PHY_1288_DATA - DDRSS1_PHY_1289_DATA - DDRSS1_PHY_1290_DATA - DDRSS1_PHY_1291_DATA - DDRSS1_PHY_1292_DATA - DDRSS1_PHY_1293_DATA - DDRSS1_PHY_1294_DATA - DDRSS1_PHY_1295_DATA - DDRSS1_PHY_1296_DATA - DDRSS1_PHY_1297_DATA - DDRSS1_PHY_1298_DATA - DDRSS1_PHY_1299_DATA - DDRSS1_PHY_1300_DATA - DDRSS1_PHY_1301_DATA - DDRSS1_PHY_1302_DATA - DDRSS1_PHY_1303_DATA - DDRSS1_PHY_1304_DATA - DDRSS1_PHY_1305_DATA - DDRSS1_PHY_1306_DATA - DDRSS1_PHY_1307_DATA - DDRSS1_PHY_1308_DATA - DDRSS1_PHY_1309_DATA - DDRSS1_PHY_1310_DATA - DDRSS1_PHY_1311_DATA - DDRSS1_PHY_1312_DATA - DDRSS1_PHY_1313_DATA - DDRSS1_PHY_1314_DATA - DDRSS1_PHY_1315_DATA - DDRSS1_PHY_1316_DATA - DDRSS1_PHY_1317_DATA - DDRSS1_PHY_1318_DATA - DDRSS1_PHY_1319_DATA - DDRSS1_PHY_1320_DATA - DDRSS1_PHY_1321_DATA - DDRSS1_PHY_1322_DATA - DDRSS1_PHY_1323_DATA - DDRSS1_PHY_1324_DATA - DDRSS1_PHY_1325_DATA - DDRSS1_PHY_1326_DATA - DDRSS1_PHY_1327_DATA - DDRSS1_PHY_1328_DATA - DDRSS1_PHY_1329_DATA - DDRSS1_PHY_1330_DATA - DDRSS1_PHY_1331_DATA - DDRSS1_PHY_1332_DATA - DDRSS1_PHY_1333_DATA - DDRSS1_PHY_1334_DATA - DDRSS1_PHY_1335_DATA - DDRSS1_PHY_1336_DATA - DDRSS1_PHY_1337_DATA - DDRSS1_PHY_1338_DATA - DDRSS1_PHY_1339_DATA - DDRSS1_PHY_1340_DATA - DDRSS1_PHY_1341_DATA - DDRSS1_PHY_1342_DATA - DDRSS1_PHY_1343_DATA - DDRSS1_PHY_1344_DATA - DDRSS1_PHY_1345_DATA - DDRSS1_PHY_1346_DATA - DDRSS1_PHY_1347_DATA - DDRSS1_PHY_1348_DATA - DDRSS1_PHY_1349_DATA - DDRSS1_PHY_1350_DATA - DDRSS1_PHY_1351_DATA - DDRSS1_PHY_1352_DATA - DDRSS1_PHY_1353_DATA - DDRSS1_PHY_1354_DATA - DDRSS1_PHY_1355_DATA - DDRSS1_PHY_1356_DATA - DDRSS1_PHY_1357_DATA - DDRSS1_PHY_1358_DATA - DDRSS1_PHY_1359_DATA - DDRSS1_PHY_1360_DATA - DDRSS1_PHY_1361_DATA - DDRSS1_PHY_1362_DATA - DDRSS1_PHY_1363_DATA - DDRSS1_PHY_1364_DATA - DDRSS1_PHY_1365_DATA - DDRSS1_PHY_1366_DATA - DDRSS1_PHY_1367_DATA - DDRSS1_PHY_1368_DATA - DDRSS1_PHY_1369_DATA - DDRSS1_PHY_1370_DATA - DDRSS1_PHY_1371_DATA - DDRSS1_PHY_1372_DATA - DDRSS1_PHY_1373_DATA - DDRSS1_PHY_1374_DATA - DDRSS1_PHY_1375_DATA - DDRSS1_PHY_1376_DATA - DDRSS1_PHY_1377_DATA - DDRSS1_PHY_1378_DATA - DDRSS1_PHY_1379_DATA - DDRSS1_PHY_1380_DATA - DDRSS1_PHY_1381_DATA - DDRSS1_PHY_1382_DATA - DDRSS1_PHY_1383_DATA - DDRSS1_PHY_1384_DATA - DDRSS1_PHY_1385_DATA - DDRSS1_PHY_1386_DATA - DDRSS1_PHY_1387_DATA - DDRSS1_PHY_1388_DATA - DDRSS1_PHY_1389_DATA - DDRSS1_PHY_1390_DATA - DDRSS1_PHY_1391_DATA - DDRSS1_PHY_1392_DATA - DDRSS1_PHY_1393_DATA - DDRSS1_PHY_1394_DATA - DDRSS1_PHY_1395_DATA - DDRSS1_PHY_1396_DATA - DDRSS1_PHY_1397_DATA - DDRSS1_PHY_1398_DATA - DDRSS1_PHY_1399_DATA - DDRSS1_PHY_1400_DATA - DDRSS1_PHY_1401_DATA - DDRSS1_PHY_1402_DATA - DDRSS1_PHY_1403_DATA - DDRSS1_PHY_1404_DATA - DDRSS1_PHY_1405_DATA - DDRSS1_PHY_1406_DATA - DDRSS1_PHY_1407_DATA - DDRSS1_PHY_1408_DATA - DDRSS1_PHY_1409_DATA - DDRSS1_PHY_1410_DATA - DDRSS1_PHY_1411_DATA - DDRSS1_PHY_1412_DATA - DDRSS1_PHY_1413_DATA - DDRSS1_PHY_1414_DATA - DDRSS1_PHY_1415_DATA - DDRSS1_PHY_1416_DATA - DDRSS1_PHY_1417_DATA - DDRSS1_PHY_1418_DATA - DDRSS1_PHY_1419_DATA - DDRSS1_PHY_1420_DATA - DDRSS1_PHY_1421_DATA - DDRSS1_PHY_1422_DATA - >; - }; - - memorycontroller2: memorycontroller@29d0000 { - compatible = "ti,j721s2-ddrss"; - reg = <0x0 0x029d0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>, - <0x0 0x029c0000 0x0 0x200>; - reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; - power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>, - <&k3_pds 133 TI_SCI_PD_SHARED>; - clocks = <&k3_clks 193 1>, <&k3_clks 78 2>; - ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; - ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; - ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; - ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; - instance = <2>; - - bootph-pre-ram; - - ti,ctl-data = < - DDRSS2_CTL_00_DATA - DDRSS2_CTL_01_DATA - DDRSS2_CTL_02_DATA - DDRSS2_CTL_03_DATA - DDRSS2_CTL_04_DATA - DDRSS2_CTL_05_DATA - DDRSS2_CTL_06_DATA - DDRSS2_CTL_07_DATA - DDRSS2_CTL_08_DATA - DDRSS2_CTL_09_DATA - DDRSS2_CTL_10_DATA - DDRSS2_CTL_11_DATA - DDRSS2_CTL_12_DATA - DDRSS2_CTL_13_DATA - DDRSS2_CTL_14_DATA - DDRSS2_CTL_15_DATA - DDRSS2_CTL_16_DATA - DDRSS2_CTL_17_DATA - DDRSS2_CTL_18_DATA - DDRSS2_CTL_19_DATA - DDRSS2_CTL_20_DATA - DDRSS2_CTL_21_DATA - DDRSS2_CTL_22_DATA - DDRSS2_CTL_23_DATA - DDRSS2_CTL_24_DATA - DDRSS2_CTL_25_DATA - DDRSS2_CTL_26_DATA - DDRSS2_CTL_27_DATA - DDRSS2_CTL_28_DATA - DDRSS2_CTL_29_DATA - DDRSS2_CTL_30_DATA - DDRSS2_CTL_31_DATA - DDRSS2_CTL_32_DATA - DDRSS2_CTL_33_DATA - DDRSS2_CTL_34_DATA - DDRSS2_CTL_35_DATA - DDRSS2_CTL_36_DATA - DDRSS2_CTL_37_DATA - DDRSS2_CTL_38_DATA - DDRSS2_CTL_39_DATA - DDRSS2_CTL_40_DATA - DDRSS2_CTL_41_DATA - DDRSS2_CTL_42_DATA - DDRSS2_CTL_43_DATA - DDRSS2_CTL_44_DATA - DDRSS2_CTL_45_DATA - DDRSS2_CTL_46_DATA - DDRSS2_CTL_47_DATA - DDRSS2_CTL_48_DATA - DDRSS2_CTL_49_DATA - DDRSS2_CTL_50_DATA - DDRSS2_CTL_51_DATA - DDRSS2_CTL_52_DATA - DDRSS2_CTL_53_DATA - DDRSS2_CTL_54_DATA - DDRSS2_CTL_55_DATA - DDRSS2_CTL_56_DATA - DDRSS2_CTL_57_DATA - DDRSS2_CTL_58_DATA - DDRSS2_CTL_59_DATA - DDRSS2_CTL_60_DATA - DDRSS2_CTL_61_DATA - DDRSS2_CTL_62_DATA - DDRSS2_CTL_63_DATA - DDRSS2_CTL_64_DATA - DDRSS2_CTL_65_DATA - DDRSS2_CTL_66_DATA - DDRSS2_CTL_67_DATA - DDRSS2_CTL_68_DATA - DDRSS2_CTL_69_DATA - DDRSS2_CTL_70_DATA - DDRSS2_CTL_71_DATA - DDRSS2_CTL_72_DATA - DDRSS2_CTL_73_DATA - DDRSS2_CTL_74_DATA - DDRSS2_CTL_75_DATA - DDRSS2_CTL_76_DATA - DDRSS2_CTL_77_DATA - DDRSS2_CTL_78_DATA - DDRSS2_CTL_79_DATA - DDRSS2_CTL_80_DATA - DDRSS2_CTL_81_DATA - DDRSS2_CTL_82_DATA - DDRSS2_CTL_83_DATA - DDRSS2_CTL_84_DATA - DDRSS2_CTL_85_DATA - DDRSS2_CTL_86_DATA - DDRSS2_CTL_87_DATA - DDRSS2_CTL_88_DATA - DDRSS2_CTL_89_DATA - DDRSS2_CTL_90_DATA - DDRSS2_CTL_91_DATA - DDRSS2_CTL_92_DATA - DDRSS2_CTL_93_DATA - DDRSS2_CTL_94_DATA - DDRSS2_CTL_95_DATA - DDRSS2_CTL_96_DATA - DDRSS2_CTL_97_DATA - DDRSS2_CTL_98_DATA - DDRSS2_CTL_99_DATA - DDRSS2_CTL_100_DATA - DDRSS2_CTL_101_DATA - DDRSS2_CTL_102_DATA - DDRSS2_CTL_103_DATA - DDRSS2_CTL_104_DATA - DDRSS2_CTL_105_DATA - DDRSS2_CTL_106_DATA - DDRSS2_CTL_107_DATA - DDRSS2_CTL_108_DATA - DDRSS2_CTL_109_DATA - DDRSS2_CTL_110_DATA - DDRSS2_CTL_111_DATA - DDRSS2_CTL_112_DATA - DDRSS2_CTL_113_DATA - DDRSS2_CTL_114_DATA - DDRSS2_CTL_115_DATA - DDRSS2_CTL_116_DATA - DDRSS2_CTL_117_DATA - DDRSS2_CTL_118_DATA - DDRSS2_CTL_119_DATA - DDRSS2_CTL_120_DATA - DDRSS2_CTL_121_DATA - DDRSS2_CTL_122_DATA - DDRSS2_CTL_123_DATA - DDRSS2_CTL_124_DATA - DDRSS2_CTL_125_DATA - DDRSS2_CTL_126_DATA - DDRSS2_CTL_127_DATA - DDRSS2_CTL_128_DATA - DDRSS2_CTL_129_DATA - DDRSS2_CTL_130_DATA - DDRSS2_CTL_131_DATA - DDRSS2_CTL_132_DATA - DDRSS2_CTL_133_DATA - DDRSS2_CTL_134_DATA - DDRSS2_CTL_135_DATA - DDRSS2_CTL_136_DATA - DDRSS2_CTL_137_DATA - DDRSS2_CTL_138_DATA - DDRSS2_CTL_139_DATA - DDRSS2_CTL_140_DATA - DDRSS2_CTL_141_DATA - DDRSS2_CTL_142_DATA - DDRSS2_CTL_143_DATA - DDRSS2_CTL_144_DATA - DDRSS2_CTL_145_DATA - DDRSS2_CTL_146_DATA - DDRSS2_CTL_147_DATA - DDRSS2_CTL_148_DATA - DDRSS2_CTL_149_DATA - DDRSS2_CTL_150_DATA - DDRSS2_CTL_151_DATA - DDRSS2_CTL_152_DATA - DDRSS2_CTL_153_DATA - DDRSS2_CTL_154_DATA - DDRSS2_CTL_155_DATA - DDRSS2_CTL_156_DATA - DDRSS2_CTL_157_DATA - DDRSS2_CTL_158_DATA - DDRSS2_CTL_159_DATA - DDRSS2_CTL_160_DATA - DDRSS2_CTL_161_DATA - DDRSS2_CTL_162_DATA - DDRSS2_CTL_163_DATA - DDRSS2_CTL_164_DATA - DDRSS2_CTL_165_DATA - DDRSS2_CTL_166_DATA - DDRSS2_CTL_167_DATA - DDRSS2_CTL_168_DATA - DDRSS2_CTL_169_DATA - DDRSS2_CTL_170_DATA - DDRSS2_CTL_171_DATA - DDRSS2_CTL_172_DATA - DDRSS2_CTL_173_DATA - DDRSS2_CTL_174_DATA - DDRSS2_CTL_175_DATA - DDRSS2_CTL_176_DATA - DDRSS2_CTL_177_DATA - DDRSS2_CTL_178_DATA - DDRSS2_CTL_179_DATA - DDRSS2_CTL_180_DATA - DDRSS2_CTL_181_DATA - DDRSS2_CTL_182_DATA - DDRSS2_CTL_183_DATA - DDRSS2_CTL_184_DATA - DDRSS2_CTL_185_DATA - DDRSS2_CTL_186_DATA - DDRSS2_CTL_187_DATA - DDRSS2_CTL_188_DATA - DDRSS2_CTL_189_DATA - DDRSS2_CTL_190_DATA - DDRSS2_CTL_191_DATA - DDRSS2_CTL_192_DATA - DDRSS2_CTL_193_DATA - DDRSS2_CTL_194_DATA - DDRSS2_CTL_195_DATA - DDRSS2_CTL_196_DATA - DDRSS2_CTL_197_DATA - DDRSS2_CTL_198_DATA - DDRSS2_CTL_199_DATA - DDRSS2_CTL_200_DATA - DDRSS2_CTL_201_DATA - DDRSS2_CTL_202_DATA - DDRSS2_CTL_203_DATA - DDRSS2_CTL_204_DATA - DDRSS2_CTL_205_DATA - DDRSS2_CTL_206_DATA - DDRSS2_CTL_207_DATA - DDRSS2_CTL_208_DATA - DDRSS2_CTL_209_DATA - DDRSS2_CTL_210_DATA - DDRSS2_CTL_211_DATA - DDRSS2_CTL_212_DATA - DDRSS2_CTL_213_DATA - DDRSS2_CTL_214_DATA - DDRSS2_CTL_215_DATA - DDRSS2_CTL_216_DATA - DDRSS2_CTL_217_DATA - DDRSS2_CTL_218_DATA - DDRSS2_CTL_219_DATA - DDRSS2_CTL_220_DATA - DDRSS2_CTL_221_DATA - DDRSS2_CTL_222_DATA - DDRSS2_CTL_223_DATA - DDRSS2_CTL_224_DATA - DDRSS2_CTL_225_DATA - DDRSS2_CTL_226_DATA - DDRSS2_CTL_227_DATA - DDRSS2_CTL_228_DATA - DDRSS2_CTL_229_DATA - DDRSS2_CTL_230_DATA - DDRSS2_CTL_231_DATA - DDRSS2_CTL_232_DATA - DDRSS2_CTL_233_DATA - DDRSS2_CTL_234_DATA - DDRSS2_CTL_235_DATA - DDRSS2_CTL_236_DATA - DDRSS2_CTL_237_DATA - DDRSS2_CTL_238_DATA - DDRSS2_CTL_239_DATA - DDRSS2_CTL_240_DATA - DDRSS2_CTL_241_DATA - DDRSS2_CTL_242_DATA - DDRSS2_CTL_243_DATA - DDRSS2_CTL_244_DATA - DDRSS2_CTL_245_DATA - DDRSS2_CTL_246_DATA - DDRSS2_CTL_247_DATA - DDRSS2_CTL_248_DATA - DDRSS2_CTL_249_DATA - DDRSS2_CTL_250_DATA - DDRSS2_CTL_251_DATA - DDRSS2_CTL_252_DATA - DDRSS2_CTL_253_DATA - DDRSS2_CTL_254_DATA - DDRSS2_CTL_255_DATA - DDRSS2_CTL_256_DATA - DDRSS2_CTL_257_DATA - DDRSS2_CTL_258_DATA - DDRSS2_CTL_259_DATA - DDRSS2_CTL_260_DATA - DDRSS2_CTL_261_DATA - DDRSS2_CTL_262_DATA - DDRSS2_CTL_263_DATA - DDRSS2_CTL_264_DATA - DDRSS2_CTL_265_DATA - DDRSS2_CTL_266_DATA - DDRSS2_CTL_267_DATA - DDRSS2_CTL_268_DATA - DDRSS2_CTL_269_DATA - DDRSS2_CTL_270_DATA - DDRSS2_CTL_271_DATA - DDRSS2_CTL_272_DATA - DDRSS2_CTL_273_DATA - DDRSS2_CTL_274_DATA - DDRSS2_CTL_275_DATA - DDRSS2_CTL_276_DATA - DDRSS2_CTL_277_DATA - DDRSS2_CTL_278_DATA - DDRSS2_CTL_279_DATA - DDRSS2_CTL_280_DATA - DDRSS2_CTL_281_DATA - DDRSS2_CTL_282_DATA - DDRSS2_CTL_283_DATA - DDRSS2_CTL_284_DATA - DDRSS2_CTL_285_DATA - DDRSS2_CTL_286_DATA - DDRSS2_CTL_287_DATA - DDRSS2_CTL_288_DATA - DDRSS2_CTL_289_DATA - DDRSS2_CTL_290_DATA - DDRSS2_CTL_291_DATA - DDRSS2_CTL_292_DATA - DDRSS2_CTL_293_DATA - DDRSS2_CTL_294_DATA - DDRSS2_CTL_295_DATA - DDRSS2_CTL_296_DATA - DDRSS2_CTL_297_DATA - DDRSS2_CTL_298_DATA - DDRSS2_CTL_299_DATA - DDRSS2_CTL_300_DATA - DDRSS2_CTL_301_DATA - DDRSS2_CTL_302_DATA - DDRSS2_CTL_303_DATA - DDRSS2_CTL_304_DATA - DDRSS2_CTL_305_DATA - DDRSS2_CTL_306_DATA - DDRSS2_CTL_307_DATA - DDRSS2_CTL_308_DATA - DDRSS2_CTL_309_DATA - DDRSS2_CTL_310_DATA - DDRSS2_CTL_311_DATA - DDRSS2_CTL_312_DATA - DDRSS2_CTL_313_DATA - DDRSS2_CTL_314_DATA - DDRSS2_CTL_315_DATA - DDRSS2_CTL_316_DATA - DDRSS2_CTL_317_DATA - DDRSS2_CTL_318_DATA - DDRSS2_CTL_319_DATA - DDRSS2_CTL_320_DATA - DDRSS2_CTL_321_DATA - DDRSS2_CTL_322_DATA - DDRSS2_CTL_323_DATA - DDRSS2_CTL_324_DATA - DDRSS2_CTL_325_DATA - DDRSS2_CTL_326_DATA - DDRSS2_CTL_327_DATA - DDRSS2_CTL_328_DATA - DDRSS2_CTL_329_DATA - DDRSS2_CTL_330_DATA - DDRSS2_CTL_331_DATA - DDRSS2_CTL_332_DATA - DDRSS2_CTL_333_DATA - DDRSS2_CTL_334_DATA - DDRSS2_CTL_335_DATA - DDRSS2_CTL_336_DATA - DDRSS2_CTL_337_DATA - DDRSS2_CTL_338_DATA - DDRSS2_CTL_339_DATA - DDRSS2_CTL_340_DATA - DDRSS2_CTL_341_DATA - DDRSS2_CTL_342_DATA - DDRSS2_CTL_343_DATA - DDRSS2_CTL_344_DATA - DDRSS2_CTL_345_DATA - DDRSS2_CTL_346_DATA - DDRSS2_CTL_347_DATA - DDRSS2_CTL_348_DATA - DDRSS2_CTL_349_DATA - DDRSS2_CTL_350_DATA - DDRSS2_CTL_351_DATA - DDRSS2_CTL_352_DATA - DDRSS2_CTL_353_DATA - DDRSS2_CTL_354_DATA - DDRSS2_CTL_355_DATA - DDRSS2_CTL_356_DATA - DDRSS2_CTL_357_DATA - DDRSS2_CTL_358_DATA - DDRSS2_CTL_359_DATA - DDRSS2_CTL_360_DATA - DDRSS2_CTL_361_DATA - DDRSS2_CTL_362_DATA - DDRSS2_CTL_363_DATA - DDRSS2_CTL_364_DATA - DDRSS2_CTL_365_DATA - DDRSS2_CTL_366_DATA - DDRSS2_CTL_367_DATA - DDRSS2_CTL_368_DATA - DDRSS2_CTL_369_DATA - DDRSS2_CTL_370_DATA - DDRSS2_CTL_371_DATA - DDRSS2_CTL_372_DATA - DDRSS2_CTL_373_DATA - DDRSS2_CTL_374_DATA - DDRSS2_CTL_375_DATA - DDRSS2_CTL_376_DATA - DDRSS2_CTL_377_DATA - DDRSS2_CTL_378_DATA - DDRSS2_CTL_379_DATA - DDRSS2_CTL_380_DATA - DDRSS2_CTL_381_DATA - DDRSS2_CTL_382_DATA - DDRSS2_CTL_383_DATA - DDRSS2_CTL_384_DATA - DDRSS2_CTL_385_DATA - DDRSS2_CTL_386_DATA - DDRSS2_CTL_387_DATA - DDRSS2_CTL_388_DATA - DDRSS2_CTL_389_DATA - DDRSS2_CTL_390_DATA - DDRSS2_CTL_391_DATA - DDRSS2_CTL_392_DATA - DDRSS2_CTL_393_DATA - DDRSS2_CTL_394_DATA - DDRSS2_CTL_395_DATA - DDRSS2_CTL_396_DATA - DDRSS2_CTL_397_DATA - DDRSS2_CTL_398_DATA - DDRSS2_CTL_399_DATA - DDRSS2_CTL_400_DATA - DDRSS2_CTL_401_DATA - DDRSS2_CTL_402_DATA - DDRSS2_CTL_403_DATA - DDRSS2_CTL_404_DATA - DDRSS2_CTL_405_DATA - DDRSS2_CTL_406_DATA - DDRSS2_CTL_407_DATA - DDRSS2_CTL_408_DATA - DDRSS2_CTL_409_DATA - DDRSS2_CTL_410_DATA - DDRSS2_CTL_411_DATA - DDRSS2_CTL_412_DATA - DDRSS2_CTL_413_DATA - DDRSS2_CTL_414_DATA - DDRSS2_CTL_415_DATA - DDRSS2_CTL_416_DATA - DDRSS2_CTL_417_DATA - DDRSS2_CTL_418_DATA - DDRSS2_CTL_419_DATA - DDRSS2_CTL_420_DATA - DDRSS2_CTL_421_DATA - DDRSS2_CTL_422_DATA - DDRSS2_CTL_423_DATA - DDRSS2_CTL_424_DATA - DDRSS2_CTL_425_DATA - DDRSS2_CTL_426_DATA - DDRSS2_CTL_427_DATA - DDRSS2_CTL_428_DATA - DDRSS2_CTL_429_DATA - DDRSS2_CTL_430_DATA - DDRSS2_CTL_431_DATA - DDRSS2_CTL_432_DATA - DDRSS2_CTL_433_DATA - DDRSS2_CTL_434_DATA - DDRSS2_CTL_435_DATA - DDRSS2_CTL_436_DATA - DDRSS2_CTL_437_DATA - DDRSS2_CTL_438_DATA - DDRSS2_CTL_439_DATA - DDRSS2_CTL_440_DATA - DDRSS2_CTL_441_DATA - DDRSS2_CTL_442_DATA - DDRSS2_CTL_443_DATA - DDRSS2_CTL_444_DATA - DDRSS2_CTL_445_DATA - DDRSS2_CTL_446_DATA - DDRSS2_CTL_447_DATA - DDRSS2_CTL_448_DATA - DDRSS2_CTL_449_DATA - DDRSS2_CTL_450_DATA - DDRSS2_CTL_451_DATA - DDRSS2_CTL_452_DATA - DDRSS2_CTL_453_DATA - DDRSS2_CTL_454_DATA - DDRSS2_CTL_455_DATA - DDRSS2_CTL_456_DATA - DDRSS2_CTL_457_DATA - DDRSS2_CTL_458_DATA - >; - - ti,pi-data = < - DDRSS2_PI_00_DATA - DDRSS2_PI_01_DATA - DDRSS2_PI_02_DATA - DDRSS2_PI_03_DATA - DDRSS2_PI_04_DATA - DDRSS2_PI_05_DATA - DDRSS2_PI_06_DATA - DDRSS2_PI_07_DATA - DDRSS2_PI_08_DATA - DDRSS2_PI_09_DATA - DDRSS2_PI_10_DATA - DDRSS2_PI_11_DATA - DDRSS2_PI_12_DATA - DDRSS2_PI_13_DATA - DDRSS2_PI_14_DATA - DDRSS2_PI_15_DATA - DDRSS2_PI_16_DATA - DDRSS2_PI_17_DATA - DDRSS2_PI_18_DATA - DDRSS2_PI_19_DATA - DDRSS2_PI_20_DATA - DDRSS2_PI_21_DATA - DDRSS2_PI_22_DATA - DDRSS2_PI_23_DATA - DDRSS2_PI_24_DATA - DDRSS2_PI_25_DATA - DDRSS2_PI_26_DATA - DDRSS2_PI_27_DATA - DDRSS2_PI_28_DATA - DDRSS2_PI_29_DATA - DDRSS2_PI_30_DATA - DDRSS2_PI_31_DATA - DDRSS2_PI_32_DATA - DDRSS2_PI_33_DATA - DDRSS2_PI_34_DATA - DDRSS2_PI_35_DATA - DDRSS2_PI_36_DATA - DDRSS2_PI_37_DATA - DDRSS2_PI_38_DATA - DDRSS2_PI_39_DATA - DDRSS2_PI_40_DATA - DDRSS2_PI_41_DATA - DDRSS2_PI_42_DATA - DDRSS2_PI_43_DATA - DDRSS2_PI_44_DATA - DDRSS2_PI_45_DATA - DDRSS2_PI_46_DATA - DDRSS2_PI_47_DATA - DDRSS2_PI_48_DATA - DDRSS2_PI_49_DATA - DDRSS2_PI_50_DATA - DDRSS2_PI_51_DATA - DDRSS2_PI_52_DATA - DDRSS2_PI_53_DATA - DDRSS2_PI_54_DATA - DDRSS2_PI_55_DATA - DDRSS2_PI_56_DATA - DDRSS2_PI_57_DATA - DDRSS2_PI_58_DATA - DDRSS2_PI_59_DATA - DDRSS2_PI_60_DATA - DDRSS2_PI_61_DATA - DDRSS2_PI_62_DATA - DDRSS2_PI_63_DATA - DDRSS2_PI_64_DATA - DDRSS2_PI_65_DATA - DDRSS2_PI_66_DATA - DDRSS2_PI_67_DATA - DDRSS2_PI_68_DATA - DDRSS2_PI_69_DATA - DDRSS2_PI_70_DATA - DDRSS2_PI_71_DATA - DDRSS2_PI_72_DATA - DDRSS2_PI_73_DATA - DDRSS2_PI_74_DATA - DDRSS2_PI_75_DATA - DDRSS2_PI_76_DATA - DDRSS2_PI_77_DATA - DDRSS2_PI_78_DATA - DDRSS2_PI_79_DATA - DDRSS2_PI_80_DATA - DDRSS2_PI_81_DATA - DDRSS2_PI_82_DATA - DDRSS2_PI_83_DATA - DDRSS2_PI_84_DATA - DDRSS2_PI_85_DATA - DDRSS2_PI_86_DATA - DDRSS2_PI_87_DATA - DDRSS2_PI_88_DATA - DDRSS2_PI_89_DATA - DDRSS2_PI_90_DATA - DDRSS2_PI_91_DATA - DDRSS2_PI_92_DATA - DDRSS2_PI_93_DATA - DDRSS2_PI_94_DATA - DDRSS2_PI_95_DATA - DDRSS2_PI_96_DATA - DDRSS2_PI_97_DATA - DDRSS2_PI_98_DATA - DDRSS2_PI_99_DATA - DDRSS2_PI_100_DATA - DDRSS2_PI_101_DATA - DDRSS2_PI_102_DATA - DDRSS2_PI_103_DATA - DDRSS2_PI_104_DATA - DDRSS2_PI_105_DATA - DDRSS2_PI_106_DATA - DDRSS2_PI_107_DATA - DDRSS2_PI_108_DATA - DDRSS2_PI_109_DATA - DDRSS2_PI_110_DATA - DDRSS2_PI_111_DATA - DDRSS2_PI_112_DATA - DDRSS2_PI_113_DATA - DDRSS2_PI_114_DATA - DDRSS2_PI_115_DATA - DDRSS2_PI_116_DATA - DDRSS2_PI_117_DATA - DDRSS2_PI_118_DATA - DDRSS2_PI_119_DATA - DDRSS2_PI_120_DATA - DDRSS2_PI_121_DATA - DDRSS2_PI_122_DATA - DDRSS2_PI_123_DATA - DDRSS2_PI_124_DATA - DDRSS2_PI_125_DATA - DDRSS2_PI_126_DATA - DDRSS2_PI_127_DATA - DDRSS2_PI_128_DATA - DDRSS2_PI_129_DATA - DDRSS2_PI_130_DATA - DDRSS2_PI_131_DATA - DDRSS2_PI_132_DATA - DDRSS2_PI_133_DATA - DDRSS2_PI_134_DATA - DDRSS2_PI_135_DATA - DDRSS2_PI_136_DATA - DDRSS2_PI_137_DATA - DDRSS2_PI_138_DATA - DDRSS2_PI_139_DATA - DDRSS2_PI_140_DATA - DDRSS2_PI_141_DATA - DDRSS2_PI_142_DATA - DDRSS2_PI_143_DATA - DDRSS2_PI_144_DATA - DDRSS2_PI_145_DATA - DDRSS2_PI_146_DATA - DDRSS2_PI_147_DATA - DDRSS2_PI_148_DATA - DDRSS2_PI_149_DATA - DDRSS2_PI_150_DATA - DDRSS2_PI_151_DATA - DDRSS2_PI_152_DATA - DDRSS2_PI_153_DATA - DDRSS2_PI_154_DATA - DDRSS2_PI_155_DATA - DDRSS2_PI_156_DATA - DDRSS2_PI_157_DATA - DDRSS2_PI_158_DATA - DDRSS2_PI_159_DATA - DDRSS2_PI_160_DATA - DDRSS2_PI_161_DATA - DDRSS2_PI_162_DATA - DDRSS2_PI_163_DATA - DDRSS2_PI_164_DATA - DDRSS2_PI_165_DATA - DDRSS2_PI_166_DATA - DDRSS2_PI_167_DATA - DDRSS2_PI_168_DATA - DDRSS2_PI_169_DATA - DDRSS2_PI_170_DATA - DDRSS2_PI_171_DATA - DDRSS2_PI_172_DATA - DDRSS2_PI_173_DATA - DDRSS2_PI_174_DATA - DDRSS2_PI_175_DATA - DDRSS2_PI_176_DATA - DDRSS2_PI_177_DATA - DDRSS2_PI_178_DATA - DDRSS2_PI_179_DATA - DDRSS2_PI_180_DATA - DDRSS2_PI_181_DATA - DDRSS2_PI_182_DATA - DDRSS2_PI_183_DATA - DDRSS2_PI_184_DATA - DDRSS2_PI_185_DATA - DDRSS2_PI_186_DATA - DDRSS2_PI_187_DATA - DDRSS2_PI_188_DATA - DDRSS2_PI_189_DATA - DDRSS2_PI_190_DATA - DDRSS2_PI_191_DATA - DDRSS2_PI_192_DATA - DDRSS2_PI_193_DATA - DDRSS2_PI_194_DATA - DDRSS2_PI_195_DATA - DDRSS2_PI_196_DATA - DDRSS2_PI_197_DATA - DDRSS2_PI_198_DATA - DDRSS2_PI_199_DATA - DDRSS2_PI_200_DATA - DDRSS2_PI_201_DATA - DDRSS2_PI_202_DATA - DDRSS2_PI_203_DATA - DDRSS2_PI_204_DATA - DDRSS2_PI_205_DATA - DDRSS2_PI_206_DATA - DDRSS2_PI_207_DATA - DDRSS2_PI_208_DATA - DDRSS2_PI_209_DATA - DDRSS2_PI_210_DATA - DDRSS2_PI_211_DATA - DDRSS2_PI_212_DATA - DDRSS2_PI_213_DATA - DDRSS2_PI_214_DATA - DDRSS2_PI_215_DATA - DDRSS2_PI_216_DATA - DDRSS2_PI_217_DATA - DDRSS2_PI_218_DATA - DDRSS2_PI_219_DATA - DDRSS2_PI_220_DATA - DDRSS2_PI_221_DATA - DDRSS2_PI_222_DATA - DDRSS2_PI_223_DATA - DDRSS2_PI_224_DATA - DDRSS2_PI_225_DATA - DDRSS2_PI_226_DATA - DDRSS2_PI_227_DATA - DDRSS2_PI_228_DATA - DDRSS2_PI_229_DATA - DDRSS2_PI_230_DATA - DDRSS2_PI_231_DATA - DDRSS2_PI_232_DATA - DDRSS2_PI_233_DATA - DDRSS2_PI_234_DATA - DDRSS2_PI_235_DATA - DDRSS2_PI_236_DATA - DDRSS2_PI_237_DATA - DDRSS2_PI_238_DATA - DDRSS2_PI_239_DATA - DDRSS2_PI_240_DATA - DDRSS2_PI_241_DATA - DDRSS2_PI_242_DATA - DDRSS2_PI_243_DATA - DDRSS2_PI_244_DATA - DDRSS2_PI_245_DATA - DDRSS2_PI_246_DATA - DDRSS2_PI_247_DATA - DDRSS2_PI_248_DATA - DDRSS2_PI_249_DATA - DDRSS2_PI_250_DATA - DDRSS2_PI_251_DATA - DDRSS2_PI_252_DATA - DDRSS2_PI_253_DATA - DDRSS2_PI_254_DATA - DDRSS2_PI_255_DATA - DDRSS2_PI_256_DATA - DDRSS2_PI_257_DATA - DDRSS2_PI_258_DATA - DDRSS2_PI_259_DATA - DDRSS2_PI_260_DATA - DDRSS2_PI_261_DATA - DDRSS2_PI_262_DATA - DDRSS2_PI_263_DATA - DDRSS2_PI_264_DATA - DDRSS2_PI_265_DATA - DDRSS2_PI_266_DATA - DDRSS2_PI_267_DATA - DDRSS2_PI_268_DATA - DDRSS2_PI_269_DATA - DDRSS2_PI_270_DATA - DDRSS2_PI_271_DATA - DDRSS2_PI_272_DATA - DDRSS2_PI_273_DATA - DDRSS2_PI_274_DATA - DDRSS2_PI_275_DATA - DDRSS2_PI_276_DATA - DDRSS2_PI_277_DATA - DDRSS2_PI_278_DATA - DDRSS2_PI_279_DATA - DDRSS2_PI_280_DATA - DDRSS2_PI_281_DATA - DDRSS2_PI_282_DATA - DDRSS2_PI_283_DATA - DDRSS2_PI_284_DATA - DDRSS2_PI_285_DATA - DDRSS2_PI_286_DATA - DDRSS2_PI_287_DATA - DDRSS2_PI_288_DATA - DDRSS2_PI_289_DATA - DDRSS2_PI_290_DATA - DDRSS2_PI_291_DATA - DDRSS2_PI_292_DATA - DDRSS2_PI_293_DATA - DDRSS2_PI_294_DATA - DDRSS2_PI_295_DATA - DDRSS2_PI_296_DATA - DDRSS2_PI_297_DATA - DDRSS2_PI_298_DATA - DDRSS2_PI_299_DATA - >; - - ti,phy-data = < - DDRSS2_PHY_00_DATA - DDRSS2_PHY_01_DATA - DDRSS2_PHY_02_DATA - DDRSS2_PHY_03_DATA - DDRSS2_PHY_04_DATA - DDRSS2_PHY_05_DATA - DDRSS2_PHY_06_DATA - DDRSS2_PHY_07_DATA - DDRSS2_PHY_08_DATA - DDRSS2_PHY_09_DATA - DDRSS2_PHY_10_DATA - DDRSS2_PHY_11_DATA - DDRSS2_PHY_12_DATA - DDRSS2_PHY_13_DATA - DDRSS2_PHY_14_DATA - DDRSS2_PHY_15_DATA - DDRSS2_PHY_16_DATA - DDRSS2_PHY_17_DATA - DDRSS2_PHY_18_DATA - DDRSS2_PHY_19_DATA - DDRSS2_PHY_20_DATA - DDRSS2_PHY_21_DATA - DDRSS2_PHY_22_DATA - DDRSS2_PHY_23_DATA - DDRSS2_PHY_24_DATA - DDRSS2_PHY_25_DATA - DDRSS2_PHY_26_DATA - DDRSS2_PHY_27_DATA - DDRSS2_PHY_28_DATA - DDRSS2_PHY_29_DATA - DDRSS2_PHY_30_DATA - DDRSS2_PHY_31_DATA - DDRSS2_PHY_32_DATA - DDRSS2_PHY_33_DATA - DDRSS2_PHY_34_DATA - DDRSS2_PHY_35_DATA - DDRSS2_PHY_36_DATA - DDRSS2_PHY_37_DATA - DDRSS2_PHY_38_DATA - DDRSS2_PHY_39_DATA - DDRSS2_PHY_40_DATA - DDRSS2_PHY_41_DATA - DDRSS2_PHY_42_DATA - DDRSS2_PHY_43_DATA - DDRSS2_PHY_44_DATA - DDRSS2_PHY_45_DATA - DDRSS2_PHY_46_DATA - DDRSS2_PHY_47_DATA - DDRSS2_PHY_48_DATA - DDRSS2_PHY_49_DATA - DDRSS2_PHY_50_DATA - DDRSS2_PHY_51_DATA - DDRSS2_PHY_52_DATA - DDRSS2_PHY_53_DATA - DDRSS2_PHY_54_DATA - DDRSS2_PHY_55_DATA - DDRSS2_PHY_56_DATA - DDRSS2_PHY_57_DATA - DDRSS2_PHY_58_DATA - DDRSS2_PHY_59_DATA - DDRSS2_PHY_60_DATA - DDRSS2_PHY_61_DATA - DDRSS2_PHY_62_DATA - DDRSS2_PHY_63_DATA - DDRSS2_PHY_64_DATA - DDRSS2_PHY_65_DATA - DDRSS2_PHY_66_DATA - DDRSS2_PHY_67_DATA - DDRSS2_PHY_68_DATA - DDRSS2_PHY_69_DATA - DDRSS2_PHY_70_DATA - DDRSS2_PHY_71_DATA - DDRSS2_PHY_72_DATA - DDRSS2_PHY_73_DATA - DDRSS2_PHY_74_DATA - DDRSS2_PHY_75_DATA - DDRSS2_PHY_76_DATA - DDRSS2_PHY_77_DATA - DDRSS2_PHY_78_DATA - DDRSS2_PHY_79_DATA - DDRSS2_PHY_80_DATA - DDRSS2_PHY_81_DATA - DDRSS2_PHY_82_DATA - DDRSS2_PHY_83_DATA - DDRSS2_PHY_84_DATA - DDRSS2_PHY_85_DATA - DDRSS2_PHY_86_DATA - DDRSS2_PHY_87_DATA - DDRSS2_PHY_88_DATA - DDRSS2_PHY_89_DATA - DDRSS2_PHY_90_DATA - DDRSS2_PHY_91_DATA - DDRSS2_PHY_92_DATA - DDRSS2_PHY_93_DATA - DDRSS2_PHY_94_DATA - DDRSS2_PHY_95_DATA - DDRSS2_PHY_96_DATA - DDRSS2_PHY_97_DATA - DDRSS2_PHY_98_DATA - DDRSS2_PHY_99_DATA - DDRSS2_PHY_100_DATA - DDRSS2_PHY_101_DATA - DDRSS2_PHY_102_DATA - DDRSS2_PHY_103_DATA - DDRSS2_PHY_104_DATA - DDRSS2_PHY_105_DATA - DDRSS2_PHY_106_DATA - DDRSS2_PHY_107_DATA - DDRSS2_PHY_108_DATA - DDRSS2_PHY_109_DATA - DDRSS2_PHY_110_DATA - DDRSS2_PHY_111_DATA - DDRSS2_PHY_112_DATA - DDRSS2_PHY_113_DATA - DDRSS2_PHY_114_DATA - DDRSS2_PHY_115_DATA - DDRSS2_PHY_116_DATA - DDRSS2_PHY_117_DATA - DDRSS2_PHY_118_DATA - DDRSS2_PHY_119_DATA - DDRSS2_PHY_120_DATA - DDRSS2_PHY_121_DATA - DDRSS2_PHY_122_DATA - DDRSS2_PHY_123_DATA - DDRSS2_PHY_124_DATA - DDRSS2_PHY_125_DATA - DDRSS2_PHY_126_DATA - DDRSS2_PHY_127_DATA - DDRSS2_PHY_128_DATA - DDRSS2_PHY_129_DATA - DDRSS2_PHY_130_DATA - DDRSS2_PHY_131_DATA - DDRSS2_PHY_132_DATA - DDRSS2_PHY_133_DATA - DDRSS2_PHY_134_DATA - DDRSS2_PHY_135_DATA - DDRSS2_PHY_136_DATA - DDRSS2_PHY_137_DATA - DDRSS2_PHY_138_DATA - DDRSS2_PHY_139_DATA - DDRSS2_PHY_140_DATA - DDRSS2_PHY_141_DATA - DDRSS2_PHY_142_DATA - DDRSS2_PHY_143_DATA - DDRSS2_PHY_144_DATA - DDRSS2_PHY_145_DATA - DDRSS2_PHY_146_DATA - DDRSS2_PHY_147_DATA - DDRSS2_PHY_148_DATA - DDRSS2_PHY_149_DATA - DDRSS2_PHY_150_DATA - DDRSS2_PHY_151_DATA - DDRSS2_PHY_152_DATA - DDRSS2_PHY_153_DATA - DDRSS2_PHY_154_DATA - DDRSS2_PHY_155_DATA - DDRSS2_PHY_156_DATA - DDRSS2_PHY_157_DATA - DDRSS2_PHY_158_DATA - DDRSS2_PHY_159_DATA - DDRSS2_PHY_160_DATA - DDRSS2_PHY_161_DATA - DDRSS2_PHY_162_DATA - DDRSS2_PHY_163_DATA - DDRSS2_PHY_164_DATA - DDRSS2_PHY_165_DATA - DDRSS2_PHY_166_DATA - DDRSS2_PHY_167_DATA - DDRSS2_PHY_168_DATA - DDRSS2_PHY_169_DATA - DDRSS2_PHY_170_DATA - DDRSS2_PHY_171_DATA - DDRSS2_PHY_172_DATA - DDRSS2_PHY_173_DATA - DDRSS2_PHY_174_DATA - DDRSS2_PHY_175_DATA - DDRSS2_PHY_176_DATA - DDRSS2_PHY_177_DATA - DDRSS2_PHY_178_DATA - DDRSS2_PHY_179_DATA - DDRSS2_PHY_180_DATA - DDRSS2_PHY_181_DATA - DDRSS2_PHY_182_DATA - DDRSS2_PHY_183_DATA - DDRSS2_PHY_184_DATA - DDRSS2_PHY_185_DATA - DDRSS2_PHY_186_DATA - DDRSS2_PHY_187_DATA - DDRSS2_PHY_188_DATA - DDRSS2_PHY_189_DATA - DDRSS2_PHY_190_DATA - DDRSS2_PHY_191_DATA - DDRSS2_PHY_192_DATA - DDRSS2_PHY_193_DATA - DDRSS2_PHY_194_DATA - DDRSS2_PHY_195_DATA - DDRSS2_PHY_196_DATA - DDRSS2_PHY_197_DATA - DDRSS2_PHY_198_DATA - DDRSS2_PHY_199_DATA - DDRSS2_PHY_200_DATA - DDRSS2_PHY_201_DATA - DDRSS2_PHY_202_DATA - DDRSS2_PHY_203_DATA - DDRSS2_PHY_204_DATA - DDRSS2_PHY_205_DATA - DDRSS2_PHY_206_DATA - DDRSS2_PHY_207_DATA - DDRSS2_PHY_208_DATA - DDRSS2_PHY_209_DATA - DDRSS2_PHY_210_DATA - DDRSS2_PHY_211_DATA - DDRSS2_PHY_212_DATA - DDRSS2_PHY_213_DATA - DDRSS2_PHY_214_DATA - DDRSS2_PHY_215_DATA - DDRSS2_PHY_216_DATA - DDRSS2_PHY_217_DATA - DDRSS2_PHY_218_DATA - DDRSS2_PHY_219_DATA - DDRSS2_PHY_220_DATA - DDRSS2_PHY_221_DATA - DDRSS2_PHY_222_DATA - DDRSS2_PHY_223_DATA - DDRSS2_PHY_224_DATA - DDRSS2_PHY_225_DATA - DDRSS2_PHY_226_DATA - DDRSS2_PHY_227_DATA - DDRSS2_PHY_228_DATA - DDRSS2_PHY_229_DATA - DDRSS2_PHY_230_DATA - DDRSS2_PHY_231_DATA - DDRSS2_PHY_232_DATA - DDRSS2_PHY_233_DATA - DDRSS2_PHY_234_DATA - DDRSS2_PHY_235_DATA - DDRSS2_PHY_236_DATA - DDRSS2_PHY_237_DATA - DDRSS2_PHY_238_DATA - DDRSS2_PHY_239_DATA - DDRSS2_PHY_240_DATA - DDRSS2_PHY_241_DATA - DDRSS2_PHY_242_DATA - DDRSS2_PHY_243_DATA - DDRSS2_PHY_244_DATA - DDRSS2_PHY_245_DATA - DDRSS2_PHY_246_DATA - DDRSS2_PHY_247_DATA - DDRSS2_PHY_248_DATA - DDRSS2_PHY_249_DATA - DDRSS2_PHY_250_DATA - DDRSS2_PHY_251_DATA - DDRSS2_PHY_252_DATA - DDRSS2_PHY_253_DATA - DDRSS2_PHY_254_DATA - DDRSS2_PHY_255_DATA - DDRSS2_PHY_256_DATA - DDRSS2_PHY_257_DATA - DDRSS2_PHY_258_DATA - DDRSS2_PHY_259_DATA - DDRSS2_PHY_260_DATA - DDRSS2_PHY_261_DATA - DDRSS2_PHY_262_DATA - DDRSS2_PHY_263_DATA - DDRSS2_PHY_264_DATA - DDRSS2_PHY_265_DATA - DDRSS2_PHY_266_DATA - DDRSS2_PHY_267_DATA - DDRSS2_PHY_268_DATA - DDRSS2_PHY_269_DATA - DDRSS2_PHY_270_DATA - DDRSS2_PHY_271_DATA - DDRSS2_PHY_272_DATA - DDRSS2_PHY_273_DATA - DDRSS2_PHY_274_DATA - DDRSS2_PHY_275_DATA - DDRSS2_PHY_276_DATA - DDRSS2_PHY_277_DATA - DDRSS2_PHY_278_DATA - DDRSS2_PHY_279_DATA - DDRSS2_PHY_280_DATA - DDRSS2_PHY_281_DATA - DDRSS2_PHY_282_DATA - DDRSS2_PHY_283_DATA - DDRSS2_PHY_284_DATA - DDRSS2_PHY_285_DATA - DDRSS2_PHY_286_DATA - DDRSS2_PHY_287_DATA - DDRSS2_PHY_288_DATA - DDRSS2_PHY_289_DATA - DDRSS2_PHY_290_DATA - DDRSS2_PHY_291_DATA - DDRSS2_PHY_292_DATA - DDRSS2_PHY_293_DATA - DDRSS2_PHY_294_DATA - DDRSS2_PHY_295_DATA - DDRSS2_PHY_296_DATA - DDRSS2_PHY_297_DATA - DDRSS2_PHY_298_DATA - DDRSS2_PHY_299_DATA - DDRSS2_PHY_300_DATA - DDRSS2_PHY_301_DATA - DDRSS2_PHY_302_DATA - DDRSS2_PHY_303_DATA - DDRSS2_PHY_304_DATA - DDRSS2_PHY_305_DATA - DDRSS2_PHY_306_DATA - DDRSS2_PHY_307_DATA - DDRSS2_PHY_308_DATA - DDRSS2_PHY_309_DATA - DDRSS2_PHY_310_DATA - DDRSS2_PHY_311_DATA - DDRSS2_PHY_312_DATA - DDRSS2_PHY_313_DATA - DDRSS2_PHY_314_DATA - DDRSS2_PHY_315_DATA - DDRSS2_PHY_316_DATA - DDRSS2_PHY_317_DATA - DDRSS2_PHY_318_DATA - DDRSS2_PHY_319_DATA - DDRSS2_PHY_320_DATA - DDRSS2_PHY_321_DATA - DDRSS2_PHY_322_DATA - DDRSS2_PHY_323_DATA - DDRSS2_PHY_324_DATA - DDRSS2_PHY_325_DATA - DDRSS2_PHY_326_DATA - DDRSS2_PHY_327_DATA - DDRSS2_PHY_328_DATA - DDRSS2_PHY_329_DATA - DDRSS2_PHY_330_DATA - DDRSS2_PHY_331_DATA - DDRSS2_PHY_332_DATA - DDRSS2_PHY_333_DATA - DDRSS2_PHY_334_DATA - DDRSS2_PHY_335_DATA - DDRSS2_PHY_336_DATA - DDRSS2_PHY_337_DATA - DDRSS2_PHY_338_DATA - DDRSS2_PHY_339_DATA - DDRSS2_PHY_340_DATA - DDRSS2_PHY_341_DATA - DDRSS2_PHY_342_DATA - DDRSS2_PHY_343_DATA - DDRSS2_PHY_344_DATA - DDRSS2_PHY_345_DATA - DDRSS2_PHY_346_DATA - DDRSS2_PHY_347_DATA - DDRSS2_PHY_348_DATA - DDRSS2_PHY_349_DATA - DDRSS2_PHY_350_DATA - DDRSS2_PHY_351_DATA - DDRSS2_PHY_352_DATA - DDRSS2_PHY_353_DATA - DDRSS2_PHY_354_DATA - DDRSS2_PHY_355_DATA - DDRSS2_PHY_356_DATA - DDRSS2_PHY_357_DATA - DDRSS2_PHY_358_DATA - DDRSS2_PHY_359_DATA - DDRSS2_PHY_360_DATA - DDRSS2_PHY_361_DATA - DDRSS2_PHY_362_DATA - DDRSS2_PHY_363_DATA - DDRSS2_PHY_364_DATA - DDRSS2_PHY_365_DATA - DDRSS2_PHY_366_DATA - DDRSS2_PHY_367_DATA - DDRSS2_PHY_368_DATA - DDRSS2_PHY_369_DATA - DDRSS2_PHY_370_DATA - DDRSS2_PHY_371_DATA - DDRSS2_PHY_372_DATA - DDRSS2_PHY_373_DATA - DDRSS2_PHY_374_DATA - DDRSS2_PHY_375_DATA - DDRSS2_PHY_376_DATA - DDRSS2_PHY_377_DATA - DDRSS2_PHY_378_DATA - DDRSS2_PHY_379_DATA - DDRSS2_PHY_380_DATA - DDRSS2_PHY_381_DATA - DDRSS2_PHY_382_DATA - DDRSS2_PHY_383_DATA - DDRSS2_PHY_384_DATA - DDRSS2_PHY_385_DATA - DDRSS2_PHY_386_DATA - DDRSS2_PHY_387_DATA - DDRSS2_PHY_388_DATA - DDRSS2_PHY_389_DATA - DDRSS2_PHY_390_DATA - DDRSS2_PHY_391_DATA - DDRSS2_PHY_392_DATA - DDRSS2_PHY_393_DATA - DDRSS2_PHY_394_DATA - DDRSS2_PHY_395_DATA - DDRSS2_PHY_396_DATA - DDRSS2_PHY_397_DATA - DDRSS2_PHY_398_DATA - DDRSS2_PHY_399_DATA - DDRSS2_PHY_400_DATA - DDRSS2_PHY_401_DATA - DDRSS2_PHY_402_DATA - DDRSS2_PHY_403_DATA - DDRSS2_PHY_404_DATA - DDRSS2_PHY_405_DATA - DDRSS2_PHY_406_DATA - DDRSS2_PHY_407_DATA - DDRSS2_PHY_408_DATA - DDRSS2_PHY_409_DATA - DDRSS2_PHY_410_DATA - DDRSS2_PHY_411_DATA - DDRSS2_PHY_412_DATA - DDRSS2_PHY_413_DATA - DDRSS2_PHY_414_DATA - DDRSS2_PHY_415_DATA - DDRSS2_PHY_416_DATA - DDRSS2_PHY_417_DATA - DDRSS2_PHY_418_DATA - DDRSS2_PHY_419_DATA - DDRSS2_PHY_420_DATA - DDRSS2_PHY_421_DATA - DDRSS2_PHY_422_DATA - DDRSS2_PHY_423_DATA - DDRSS2_PHY_424_DATA - DDRSS2_PHY_425_DATA - DDRSS2_PHY_426_DATA - DDRSS2_PHY_427_DATA - DDRSS2_PHY_428_DATA - DDRSS2_PHY_429_DATA - DDRSS2_PHY_430_DATA - DDRSS2_PHY_431_DATA - DDRSS2_PHY_432_DATA - DDRSS2_PHY_433_DATA - DDRSS2_PHY_434_DATA - DDRSS2_PHY_435_DATA - DDRSS2_PHY_436_DATA - DDRSS2_PHY_437_DATA - DDRSS2_PHY_438_DATA - DDRSS2_PHY_439_DATA - DDRSS2_PHY_440_DATA - DDRSS2_PHY_441_DATA - DDRSS2_PHY_442_DATA - DDRSS2_PHY_443_DATA - DDRSS2_PHY_444_DATA - DDRSS2_PHY_445_DATA - DDRSS2_PHY_446_DATA - DDRSS2_PHY_447_DATA - DDRSS2_PHY_448_DATA - DDRSS2_PHY_449_DATA - DDRSS2_PHY_450_DATA - DDRSS2_PHY_451_DATA - DDRSS2_PHY_452_DATA - DDRSS2_PHY_453_DATA - DDRSS2_PHY_454_DATA - DDRSS2_PHY_455_DATA - DDRSS2_PHY_456_DATA - DDRSS2_PHY_457_DATA - DDRSS2_PHY_458_DATA - DDRSS2_PHY_459_DATA - DDRSS2_PHY_460_DATA - DDRSS2_PHY_461_DATA - DDRSS2_PHY_462_DATA - DDRSS2_PHY_463_DATA - DDRSS2_PHY_464_DATA - DDRSS2_PHY_465_DATA - DDRSS2_PHY_466_DATA - DDRSS2_PHY_467_DATA - DDRSS2_PHY_468_DATA - DDRSS2_PHY_469_DATA - DDRSS2_PHY_470_DATA - DDRSS2_PHY_471_DATA - DDRSS2_PHY_472_DATA - DDRSS2_PHY_473_DATA - DDRSS2_PHY_474_DATA - DDRSS2_PHY_475_DATA - DDRSS2_PHY_476_DATA - DDRSS2_PHY_477_DATA - DDRSS2_PHY_478_DATA - DDRSS2_PHY_479_DATA - DDRSS2_PHY_480_DATA - DDRSS2_PHY_481_DATA - DDRSS2_PHY_482_DATA - DDRSS2_PHY_483_DATA - DDRSS2_PHY_484_DATA - DDRSS2_PHY_485_DATA - DDRSS2_PHY_486_DATA - DDRSS2_PHY_487_DATA - DDRSS2_PHY_488_DATA - DDRSS2_PHY_489_DATA - DDRSS2_PHY_490_DATA - DDRSS2_PHY_491_DATA - DDRSS2_PHY_492_DATA - DDRSS2_PHY_493_DATA - DDRSS2_PHY_494_DATA - DDRSS2_PHY_495_DATA - DDRSS2_PHY_496_DATA - DDRSS2_PHY_497_DATA - DDRSS2_PHY_498_DATA - DDRSS2_PHY_499_DATA - DDRSS2_PHY_500_DATA - DDRSS2_PHY_501_DATA - DDRSS2_PHY_502_DATA - DDRSS2_PHY_503_DATA - DDRSS2_PHY_504_DATA - DDRSS2_PHY_505_DATA - DDRSS2_PHY_506_DATA - DDRSS2_PHY_507_DATA - DDRSS2_PHY_508_DATA - DDRSS2_PHY_509_DATA - DDRSS2_PHY_510_DATA - DDRSS2_PHY_511_DATA - DDRSS2_PHY_512_DATA - DDRSS2_PHY_513_DATA - DDRSS2_PHY_514_DATA - DDRSS2_PHY_515_DATA - DDRSS2_PHY_516_DATA - DDRSS2_PHY_517_DATA - DDRSS2_PHY_518_DATA - DDRSS2_PHY_519_DATA - DDRSS2_PHY_520_DATA - DDRSS2_PHY_521_DATA - DDRSS2_PHY_522_DATA - DDRSS2_PHY_523_DATA - DDRSS2_PHY_524_DATA - DDRSS2_PHY_525_DATA - DDRSS2_PHY_526_DATA - DDRSS2_PHY_527_DATA - DDRSS2_PHY_528_DATA - DDRSS2_PHY_529_DATA - DDRSS2_PHY_530_DATA - DDRSS2_PHY_531_DATA - DDRSS2_PHY_532_DATA - DDRSS2_PHY_533_DATA - DDRSS2_PHY_534_DATA - DDRSS2_PHY_535_DATA - DDRSS2_PHY_536_DATA - DDRSS2_PHY_537_DATA - DDRSS2_PHY_538_DATA - DDRSS2_PHY_539_DATA - DDRSS2_PHY_540_DATA - DDRSS2_PHY_541_DATA - DDRSS2_PHY_542_DATA - DDRSS2_PHY_543_DATA - DDRSS2_PHY_544_DATA - DDRSS2_PHY_545_DATA - DDRSS2_PHY_546_DATA - DDRSS2_PHY_547_DATA - DDRSS2_PHY_548_DATA - DDRSS2_PHY_549_DATA - DDRSS2_PHY_550_DATA - DDRSS2_PHY_551_DATA - DDRSS2_PHY_552_DATA - DDRSS2_PHY_553_DATA - DDRSS2_PHY_554_DATA - DDRSS2_PHY_555_DATA - DDRSS2_PHY_556_DATA - DDRSS2_PHY_557_DATA - DDRSS2_PHY_558_DATA - DDRSS2_PHY_559_DATA - DDRSS2_PHY_560_DATA - DDRSS2_PHY_561_DATA - DDRSS2_PHY_562_DATA - DDRSS2_PHY_563_DATA - DDRSS2_PHY_564_DATA - DDRSS2_PHY_565_DATA - DDRSS2_PHY_566_DATA - DDRSS2_PHY_567_DATA - DDRSS2_PHY_568_DATA - DDRSS2_PHY_569_DATA - DDRSS2_PHY_570_DATA - DDRSS2_PHY_571_DATA - DDRSS2_PHY_572_DATA - DDRSS2_PHY_573_DATA - DDRSS2_PHY_574_DATA - DDRSS2_PHY_575_DATA - DDRSS2_PHY_576_DATA - DDRSS2_PHY_577_DATA - DDRSS2_PHY_578_DATA - DDRSS2_PHY_579_DATA - DDRSS2_PHY_580_DATA - DDRSS2_PHY_581_DATA - DDRSS2_PHY_582_DATA - DDRSS2_PHY_583_DATA - DDRSS2_PHY_584_DATA - DDRSS2_PHY_585_DATA - DDRSS2_PHY_586_DATA - DDRSS2_PHY_587_DATA - DDRSS2_PHY_588_DATA - DDRSS2_PHY_589_DATA - DDRSS2_PHY_590_DATA - DDRSS2_PHY_591_DATA - DDRSS2_PHY_592_DATA - DDRSS2_PHY_593_DATA - DDRSS2_PHY_594_DATA - DDRSS2_PHY_595_DATA - DDRSS2_PHY_596_DATA - DDRSS2_PHY_597_DATA - DDRSS2_PHY_598_DATA - DDRSS2_PHY_599_DATA - DDRSS2_PHY_600_DATA - DDRSS2_PHY_601_DATA - DDRSS2_PHY_602_DATA - DDRSS2_PHY_603_DATA - DDRSS2_PHY_604_DATA - DDRSS2_PHY_605_DATA - DDRSS2_PHY_606_DATA - DDRSS2_PHY_607_DATA - DDRSS2_PHY_608_DATA - DDRSS2_PHY_609_DATA - DDRSS2_PHY_610_DATA - DDRSS2_PHY_611_DATA - DDRSS2_PHY_612_DATA - DDRSS2_PHY_613_DATA - DDRSS2_PHY_614_DATA - DDRSS2_PHY_615_DATA - DDRSS2_PHY_616_DATA - DDRSS2_PHY_617_DATA - DDRSS2_PHY_618_DATA - DDRSS2_PHY_619_DATA - DDRSS2_PHY_620_DATA - DDRSS2_PHY_621_DATA - DDRSS2_PHY_622_DATA - DDRSS2_PHY_623_DATA - DDRSS2_PHY_624_DATA - DDRSS2_PHY_625_DATA - DDRSS2_PHY_626_DATA - DDRSS2_PHY_627_DATA - DDRSS2_PHY_628_DATA - DDRSS2_PHY_629_DATA - DDRSS2_PHY_630_DATA - DDRSS2_PHY_631_DATA - DDRSS2_PHY_632_DATA - DDRSS2_PHY_633_DATA - DDRSS2_PHY_634_DATA - DDRSS2_PHY_635_DATA - DDRSS2_PHY_636_DATA - DDRSS2_PHY_637_DATA - DDRSS2_PHY_638_DATA - DDRSS2_PHY_639_DATA - DDRSS2_PHY_640_DATA - DDRSS2_PHY_641_DATA - DDRSS2_PHY_642_DATA - DDRSS2_PHY_643_DATA - DDRSS2_PHY_644_DATA - DDRSS2_PHY_645_DATA - DDRSS2_PHY_646_DATA - DDRSS2_PHY_647_DATA - DDRSS2_PHY_648_DATA - DDRSS2_PHY_649_DATA - DDRSS2_PHY_650_DATA - DDRSS2_PHY_651_DATA - DDRSS2_PHY_652_DATA - DDRSS2_PHY_653_DATA - DDRSS2_PHY_654_DATA - DDRSS2_PHY_655_DATA - DDRSS2_PHY_656_DATA - DDRSS2_PHY_657_DATA - DDRSS2_PHY_658_DATA - DDRSS2_PHY_659_DATA - DDRSS2_PHY_660_DATA - DDRSS2_PHY_661_DATA - DDRSS2_PHY_662_DATA - DDRSS2_PHY_663_DATA - DDRSS2_PHY_664_DATA - DDRSS2_PHY_665_DATA - DDRSS2_PHY_666_DATA - DDRSS2_PHY_667_DATA - DDRSS2_PHY_668_DATA - DDRSS2_PHY_669_DATA - DDRSS2_PHY_670_DATA - DDRSS2_PHY_671_DATA - DDRSS2_PHY_672_DATA - DDRSS2_PHY_673_DATA - DDRSS2_PHY_674_DATA - DDRSS2_PHY_675_DATA - DDRSS2_PHY_676_DATA - DDRSS2_PHY_677_DATA - DDRSS2_PHY_678_DATA - DDRSS2_PHY_679_DATA - DDRSS2_PHY_680_DATA - DDRSS2_PHY_681_DATA - DDRSS2_PHY_682_DATA - DDRSS2_PHY_683_DATA - DDRSS2_PHY_684_DATA - DDRSS2_PHY_685_DATA - DDRSS2_PHY_686_DATA - DDRSS2_PHY_687_DATA - DDRSS2_PHY_688_DATA - DDRSS2_PHY_689_DATA - DDRSS2_PHY_690_DATA - DDRSS2_PHY_691_DATA - DDRSS2_PHY_692_DATA - DDRSS2_PHY_693_DATA - DDRSS2_PHY_694_DATA - DDRSS2_PHY_695_DATA - DDRSS2_PHY_696_DATA - DDRSS2_PHY_697_DATA - DDRSS2_PHY_698_DATA - DDRSS2_PHY_699_DATA - DDRSS2_PHY_700_DATA - DDRSS2_PHY_701_DATA - DDRSS2_PHY_702_DATA - DDRSS2_PHY_703_DATA - DDRSS2_PHY_704_DATA - DDRSS2_PHY_705_DATA - DDRSS2_PHY_706_DATA - DDRSS2_PHY_707_DATA - DDRSS2_PHY_708_DATA - DDRSS2_PHY_709_DATA - DDRSS2_PHY_710_DATA - DDRSS2_PHY_711_DATA - DDRSS2_PHY_712_DATA - DDRSS2_PHY_713_DATA - DDRSS2_PHY_714_DATA - DDRSS2_PHY_715_DATA - DDRSS2_PHY_716_DATA - DDRSS2_PHY_717_DATA - DDRSS2_PHY_718_DATA - DDRSS2_PHY_719_DATA - DDRSS2_PHY_720_DATA - DDRSS2_PHY_721_DATA - DDRSS2_PHY_722_DATA - DDRSS2_PHY_723_DATA - DDRSS2_PHY_724_DATA - DDRSS2_PHY_725_DATA - DDRSS2_PHY_726_DATA - DDRSS2_PHY_727_DATA - DDRSS2_PHY_728_DATA - DDRSS2_PHY_729_DATA - DDRSS2_PHY_730_DATA - DDRSS2_PHY_731_DATA - DDRSS2_PHY_732_DATA - DDRSS2_PHY_733_DATA - DDRSS2_PHY_734_DATA - DDRSS2_PHY_735_DATA - DDRSS2_PHY_736_DATA - DDRSS2_PHY_737_DATA - DDRSS2_PHY_738_DATA - DDRSS2_PHY_739_DATA - DDRSS2_PHY_740_DATA - DDRSS2_PHY_741_DATA - DDRSS2_PHY_742_DATA - DDRSS2_PHY_743_DATA - DDRSS2_PHY_744_DATA - DDRSS2_PHY_745_DATA - DDRSS2_PHY_746_DATA - DDRSS2_PHY_747_DATA - DDRSS2_PHY_748_DATA - DDRSS2_PHY_749_DATA - DDRSS2_PHY_750_DATA - DDRSS2_PHY_751_DATA - DDRSS2_PHY_752_DATA - DDRSS2_PHY_753_DATA - DDRSS2_PHY_754_DATA - DDRSS2_PHY_755_DATA - DDRSS2_PHY_756_DATA - DDRSS2_PHY_757_DATA - DDRSS2_PHY_758_DATA - DDRSS2_PHY_759_DATA - DDRSS2_PHY_760_DATA - DDRSS2_PHY_761_DATA - DDRSS2_PHY_762_DATA - DDRSS2_PHY_763_DATA - DDRSS2_PHY_764_DATA - DDRSS2_PHY_765_DATA - DDRSS2_PHY_766_DATA - DDRSS2_PHY_767_DATA - DDRSS2_PHY_768_DATA - DDRSS2_PHY_769_DATA - DDRSS2_PHY_770_DATA - DDRSS2_PHY_771_DATA - DDRSS2_PHY_772_DATA - DDRSS2_PHY_773_DATA - DDRSS2_PHY_774_DATA - DDRSS2_PHY_775_DATA - DDRSS2_PHY_776_DATA - DDRSS2_PHY_777_DATA - DDRSS2_PHY_778_DATA - DDRSS2_PHY_779_DATA - DDRSS2_PHY_780_DATA - DDRSS2_PHY_781_DATA - DDRSS2_PHY_782_DATA - DDRSS2_PHY_783_DATA - DDRSS2_PHY_784_DATA - DDRSS2_PHY_785_DATA - DDRSS2_PHY_786_DATA - DDRSS2_PHY_787_DATA - DDRSS2_PHY_788_DATA - DDRSS2_PHY_789_DATA - DDRSS2_PHY_790_DATA - DDRSS2_PHY_791_DATA - DDRSS2_PHY_792_DATA - DDRSS2_PHY_793_DATA - DDRSS2_PHY_794_DATA - DDRSS2_PHY_795_DATA - DDRSS2_PHY_796_DATA - DDRSS2_PHY_797_DATA - DDRSS2_PHY_798_DATA - DDRSS2_PHY_799_DATA - DDRSS2_PHY_800_DATA - DDRSS2_PHY_801_DATA - DDRSS2_PHY_802_DATA - DDRSS2_PHY_803_DATA - DDRSS2_PHY_804_DATA - DDRSS2_PHY_805_DATA - DDRSS2_PHY_806_DATA - DDRSS2_PHY_807_DATA - DDRSS2_PHY_808_DATA - DDRSS2_PHY_809_DATA - DDRSS2_PHY_810_DATA - DDRSS2_PHY_811_DATA - DDRSS2_PHY_812_DATA - DDRSS2_PHY_813_DATA - DDRSS2_PHY_814_DATA - DDRSS2_PHY_815_DATA - DDRSS2_PHY_816_DATA - DDRSS2_PHY_817_DATA - DDRSS2_PHY_818_DATA - DDRSS2_PHY_819_DATA - DDRSS2_PHY_820_DATA - DDRSS2_PHY_821_DATA - DDRSS2_PHY_822_DATA - DDRSS2_PHY_823_DATA - DDRSS2_PHY_824_DATA - DDRSS2_PHY_825_DATA - DDRSS2_PHY_826_DATA - DDRSS2_PHY_827_DATA - DDRSS2_PHY_828_DATA - DDRSS2_PHY_829_DATA - DDRSS2_PHY_830_DATA - DDRSS2_PHY_831_DATA - DDRSS2_PHY_832_DATA - DDRSS2_PHY_833_DATA - DDRSS2_PHY_834_DATA - DDRSS2_PHY_835_DATA - DDRSS2_PHY_836_DATA - DDRSS2_PHY_837_DATA - DDRSS2_PHY_838_DATA - DDRSS2_PHY_839_DATA - DDRSS2_PHY_840_DATA - DDRSS2_PHY_841_DATA - DDRSS2_PHY_842_DATA - DDRSS2_PHY_843_DATA - DDRSS2_PHY_844_DATA - DDRSS2_PHY_845_DATA - DDRSS2_PHY_846_DATA - DDRSS2_PHY_847_DATA - DDRSS2_PHY_848_DATA - DDRSS2_PHY_849_DATA - DDRSS2_PHY_850_DATA - DDRSS2_PHY_851_DATA - DDRSS2_PHY_852_DATA - DDRSS2_PHY_853_DATA - DDRSS2_PHY_854_DATA - DDRSS2_PHY_855_DATA - DDRSS2_PHY_856_DATA - DDRSS2_PHY_857_DATA - DDRSS2_PHY_858_DATA - DDRSS2_PHY_859_DATA - DDRSS2_PHY_860_DATA - DDRSS2_PHY_861_DATA - DDRSS2_PHY_862_DATA - DDRSS2_PHY_863_DATA - DDRSS2_PHY_864_DATA - DDRSS2_PHY_865_DATA - DDRSS2_PHY_866_DATA - DDRSS2_PHY_867_DATA - DDRSS2_PHY_868_DATA - DDRSS2_PHY_869_DATA - DDRSS2_PHY_870_DATA - DDRSS2_PHY_871_DATA - DDRSS2_PHY_872_DATA - DDRSS2_PHY_873_DATA - DDRSS2_PHY_874_DATA - DDRSS2_PHY_875_DATA - DDRSS2_PHY_876_DATA - DDRSS2_PHY_877_DATA - DDRSS2_PHY_878_DATA - DDRSS2_PHY_879_DATA - DDRSS2_PHY_880_DATA - DDRSS2_PHY_881_DATA - DDRSS2_PHY_882_DATA - DDRSS2_PHY_883_DATA - DDRSS2_PHY_884_DATA - DDRSS2_PHY_885_DATA - DDRSS2_PHY_886_DATA - DDRSS2_PHY_887_DATA - DDRSS2_PHY_888_DATA - DDRSS2_PHY_889_DATA - DDRSS2_PHY_890_DATA - DDRSS2_PHY_891_DATA - DDRSS2_PHY_892_DATA - DDRSS2_PHY_893_DATA - DDRSS2_PHY_894_DATA - DDRSS2_PHY_895_DATA - DDRSS2_PHY_896_DATA - DDRSS2_PHY_897_DATA - DDRSS2_PHY_898_DATA - DDRSS2_PHY_899_DATA - DDRSS2_PHY_900_DATA - DDRSS2_PHY_901_DATA - DDRSS2_PHY_902_DATA - DDRSS2_PHY_903_DATA - DDRSS2_PHY_904_DATA - DDRSS2_PHY_905_DATA - DDRSS2_PHY_906_DATA - DDRSS2_PHY_907_DATA - DDRSS2_PHY_908_DATA - DDRSS2_PHY_909_DATA - DDRSS2_PHY_910_DATA - DDRSS2_PHY_911_DATA - DDRSS2_PHY_912_DATA - DDRSS2_PHY_913_DATA - DDRSS2_PHY_914_DATA - DDRSS2_PHY_915_DATA - DDRSS2_PHY_916_DATA - DDRSS2_PHY_917_DATA - DDRSS2_PHY_918_DATA - DDRSS2_PHY_919_DATA - DDRSS2_PHY_920_DATA - DDRSS2_PHY_921_DATA - DDRSS2_PHY_922_DATA - DDRSS2_PHY_923_DATA - DDRSS2_PHY_924_DATA - DDRSS2_PHY_925_DATA - DDRSS2_PHY_926_DATA - DDRSS2_PHY_927_DATA - DDRSS2_PHY_928_DATA - DDRSS2_PHY_929_DATA - DDRSS2_PHY_930_DATA - DDRSS2_PHY_931_DATA - DDRSS2_PHY_932_DATA - DDRSS2_PHY_933_DATA - DDRSS2_PHY_934_DATA - DDRSS2_PHY_935_DATA - DDRSS2_PHY_936_DATA - DDRSS2_PHY_937_DATA - DDRSS2_PHY_938_DATA - DDRSS2_PHY_939_DATA - DDRSS2_PHY_940_DATA - DDRSS2_PHY_941_DATA - DDRSS2_PHY_942_DATA - DDRSS2_PHY_943_DATA - DDRSS2_PHY_944_DATA - DDRSS2_PHY_945_DATA - DDRSS2_PHY_946_DATA - DDRSS2_PHY_947_DATA - DDRSS2_PHY_948_DATA - DDRSS2_PHY_949_DATA - DDRSS2_PHY_950_DATA - DDRSS2_PHY_951_DATA - DDRSS2_PHY_952_DATA - DDRSS2_PHY_953_DATA - DDRSS2_PHY_954_DATA - DDRSS2_PHY_955_DATA - DDRSS2_PHY_956_DATA - DDRSS2_PHY_957_DATA - DDRSS2_PHY_958_DATA - DDRSS2_PHY_959_DATA - DDRSS2_PHY_960_DATA - DDRSS2_PHY_961_DATA - DDRSS2_PHY_962_DATA - DDRSS2_PHY_963_DATA - DDRSS2_PHY_964_DATA - DDRSS2_PHY_965_DATA - DDRSS2_PHY_966_DATA - DDRSS2_PHY_967_DATA - DDRSS2_PHY_968_DATA - DDRSS2_PHY_969_DATA - DDRSS2_PHY_970_DATA - DDRSS2_PHY_971_DATA - DDRSS2_PHY_972_DATA - DDRSS2_PHY_973_DATA - DDRSS2_PHY_974_DATA - DDRSS2_PHY_975_DATA - DDRSS2_PHY_976_DATA - DDRSS2_PHY_977_DATA - DDRSS2_PHY_978_DATA - DDRSS2_PHY_979_DATA - DDRSS2_PHY_980_DATA - DDRSS2_PHY_981_DATA - DDRSS2_PHY_982_DATA - DDRSS2_PHY_983_DATA - DDRSS2_PHY_984_DATA - DDRSS2_PHY_985_DATA - DDRSS2_PHY_986_DATA - DDRSS2_PHY_987_DATA - DDRSS2_PHY_988_DATA - DDRSS2_PHY_989_DATA - DDRSS2_PHY_990_DATA - DDRSS2_PHY_991_DATA - DDRSS2_PHY_992_DATA - DDRSS2_PHY_993_DATA - DDRSS2_PHY_994_DATA - DDRSS2_PHY_995_DATA - DDRSS2_PHY_996_DATA - DDRSS2_PHY_997_DATA - DDRSS2_PHY_998_DATA - DDRSS2_PHY_999_DATA - DDRSS2_PHY_1000_DATA - DDRSS2_PHY_1001_DATA - DDRSS2_PHY_1002_DATA - DDRSS2_PHY_1003_DATA - DDRSS2_PHY_1004_DATA - DDRSS2_PHY_1005_DATA - DDRSS2_PHY_1006_DATA - DDRSS2_PHY_1007_DATA - DDRSS2_PHY_1008_DATA - DDRSS2_PHY_1009_DATA - DDRSS2_PHY_1010_DATA - DDRSS2_PHY_1011_DATA - DDRSS2_PHY_1012_DATA - DDRSS2_PHY_1013_DATA - DDRSS2_PHY_1014_DATA - DDRSS2_PHY_1015_DATA - DDRSS2_PHY_1016_DATA - DDRSS2_PHY_1017_DATA - DDRSS2_PHY_1018_DATA - DDRSS2_PHY_1019_DATA - DDRSS2_PHY_1020_DATA - DDRSS2_PHY_1021_DATA - DDRSS2_PHY_1022_DATA - DDRSS2_PHY_1023_DATA - DDRSS2_PHY_1024_DATA - DDRSS2_PHY_1025_DATA - DDRSS2_PHY_1026_DATA - DDRSS2_PHY_1027_DATA - DDRSS2_PHY_1028_DATA - DDRSS2_PHY_1029_DATA - DDRSS2_PHY_1030_DATA - DDRSS2_PHY_1031_DATA - DDRSS2_PHY_1032_DATA - DDRSS2_PHY_1033_DATA - DDRSS2_PHY_1034_DATA - DDRSS2_PHY_1035_DATA - DDRSS2_PHY_1036_DATA - DDRSS2_PHY_1037_DATA - DDRSS2_PHY_1038_DATA - DDRSS2_PHY_1039_DATA - DDRSS2_PHY_1040_DATA - DDRSS2_PHY_1041_DATA - DDRSS2_PHY_1042_DATA - DDRSS2_PHY_1043_DATA - DDRSS2_PHY_1044_DATA - DDRSS2_PHY_1045_DATA - DDRSS2_PHY_1046_DATA - DDRSS2_PHY_1047_DATA - DDRSS2_PHY_1048_DATA - DDRSS2_PHY_1049_DATA - DDRSS2_PHY_1050_DATA - DDRSS2_PHY_1051_DATA - DDRSS2_PHY_1052_DATA - DDRSS2_PHY_1053_DATA - DDRSS2_PHY_1054_DATA - DDRSS2_PHY_1055_DATA - DDRSS2_PHY_1056_DATA - DDRSS2_PHY_1057_DATA - DDRSS2_PHY_1058_DATA - DDRSS2_PHY_1059_DATA - DDRSS2_PHY_1060_DATA - DDRSS2_PHY_1061_DATA - DDRSS2_PHY_1062_DATA - DDRSS2_PHY_1063_DATA - DDRSS2_PHY_1064_DATA - DDRSS2_PHY_1065_DATA - DDRSS2_PHY_1066_DATA - DDRSS2_PHY_1067_DATA - DDRSS2_PHY_1068_DATA - DDRSS2_PHY_1069_DATA - DDRSS2_PHY_1070_DATA - DDRSS2_PHY_1071_DATA - DDRSS2_PHY_1072_DATA - DDRSS2_PHY_1073_DATA - DDRSS2_PHY_1074_DATA - DDRSS2_PHY_1075_DATA - DDRSS2_PHY_1076_DATA - DDRSS2_PHY_1077_DATA - DDRSS2_PHY_1078_DATA - DDRSS2_PHY_1079_DATA - DDRSS2_PHY_1080_DATA - DDRSS2_PHY_1081_DATA - DDRSS2_PHY_1082_DATA - DDRSS2_PHY_1083_DATA - DDRSS2_PHY_1084_DATA - DDRSS2_PHY_1085_DATA - DDRSS2_PHY_1086_DATA - DDRSS2_PHY_1087_DATA - DDRSS2_PHY_1088_DATA - DDRSS2_PHY_1089_DATA - DDRSS2_PHY_1090_DATA - DDRSS2_PHY_1091_DATA - DDRSS2_PHY_1092_DATA - DDRSS2_PHY_1093_DATA - DDRSS2_PHY_1094_DATA - DDRSS2_PHY_1095_DATA - DDRSS2_PHY_1096_DATA - DDRSS2_PHY_1097_DATA - DDRSS2_PHY_1098_DATA - DDRSS2_PHY_1099_DATA - DDRSS2_PHY_1100_DATA - DDRSS2_PHY_1101_DATA - DDRSS2_PHY_1102_DATA - DDRSS2_PHY_1103_DATA - DDRSS2_PHY_1104_DATA - DDRSS2_PHY_1105_DATA - DDRSS2_PHY_1106_DATA - DDRSS2_PHY_1107_DATA - DDRSS2_PHY_1108_DATA - DDRSS2_PHY_1109_DATA - DDRSS2_PHY_1110_DATA - DDRSS2_PHY_1111_DATA - DDRSS2_PHY_1112_DATA - DDRSS2_PHY_1113_DATA - DDRSS2_PHY_1114_DATA - DDRSS2_PHY_1115_DATA - DDRSS2_PHY_1116_DATA - DDRSS2_PHY_1117_DATA - DDRSS2_PHY_1118_DATA - DDRSS2_PHY_1119_DATA - DDRSS2_PHY_1120_DATA - DDRSS2_PHY_1121_DATA - DDRSS2_PHY_1122_DATA - DDRSS2_PHY_1123_DATA - DDRSS2_PHY_1124_DATA - DDRSS2_PHY_1125_DATA - DDRSS2_PHY_1126_DATA - DDRSS2_PHY_1127_DATA - DDRSS2_PHY_1128_DATA - DDRSS2_PHY_1129_DATA - DDRSS2_PHY_1130_DATA - DDRSS2_PHY_1131_DATA - DDRSS2_PHY_1132_DATA - DDRSS2_PHY_1133_DATA - DDRSS2_PHY_1134_DATA - DDRSS2_PHY_1135_DATA - DDRSS2_PHY_1136_DATA - DDRSS2_PHY_1137_DATA - DDRSS2_PHY_1138_DATA - DDRSS2_PHY_1139_DATA - DDRSS2_PHY_1140_DATA - DDRSS2_PHY_1141_DATA - DDRSS2_PHY_1142_DATA - DDRSS2_PHY_1143_DATA - DDRSS2_PHY_1144_DATA - DDRSS2_PHY_1145_DATA - DDRSS2_PHY_1146_DATA - DDRSS2_PHY_1147_DATA - DDRSS2_PHY_1148_DATA - DDRSS2_PHY_1149_DATA - DDRSS2_PHY_1150_DATA - DDRSS2_PHY_1151_DATA - DDRSS2_PHY_1152_DATA - DDRSS2_PHY_1153_DATA - DDRSS2_PHY_1154_DATA - DDRSS2_PHY_1155_DATA - DDRSS2_PHY_1156_DATA - DDRSS2_PHY_1157_DATA - DDRSS2_PHY_1158_DATA - DDRSS2_PHY_1159_DATA - DDRSS2_PHY_1160_DATA - DDRSS2_PHY_1161_DATA - DDRSS2_PHY_1162_DATA - DDRSS2_PHY_1163_DATA - DDRSS2_PHY_1164_DATA - DDRSS2_PHY_1165_DATA - DDRSS2_PHY_1166_DATA - DDRSS2_PHY_1167_DATA - DDRSS2_PHY_1168_DATA - DDRSS2_PHY_1169_DATA - DDRSS2_PHY_1170_DATA - DDRSS2_PHY_1171_DATA - DDRSS2_PHY_1172_DATA - DDRSS2_PHY_1173_DATA - DDRSS2_PHY_1174_DATA - DDRSS2_PHY_1175_DATA - DDRSS2_PHY_1176_DATA - DDRSS2_PHY_1177_DATA - DDRSS2_PHY_1178_DATA - DDRSS2_PHY_1179_DATA - DDRSS2_PHY_1180_DATA - DDRSS2_PHY_1181_DATA - DDRSS2_PHY_1182_DATA - DDRSS2_PHY_1183_DATA - DDRSS2_PHY_1184_DATA - DDRSS2_PHY_1185_DATA - DDRSS2_PHY_1186_DATA - DDRSS2_PHY_1187_DATA - DDRSS2_PHY_1188_DATA - DDRSS2_PHY_1189_DATA - DDRSS2_PHY_1190_DATA - DDRSS2_PHY_1191_DATA - DDRSS2_PHY_1192_DATA - DDRSS2_PHY_1193_DATA - DDRSS2_PHY_1194_DATA - DDRSS2_PHY_1195_DATA - DDRSS2_PHY_1196_DATA - DDRSS2_PHY_1197_DATA - DDRSS2_PHY_1198_DATA - DDRSS2_PHY_1199_DATA - DDRSS2_PHY_1200_DATA - DDRSS2_PHY_1201_DATA - DDRSS2_PHY_1202_DATA - DDRSS2_PHY_1203_DATA - DDRSS2_PHY_1204_DATA - DDRSS2_PHY_1205_DATA - DDRSS2_PHY_1206_DATA - DDRSS2_PHY_1207_DATA - DDRSS2_PHY_1208_DATA - DDRSS2_PHY_1209_DATA - DDRSS2_PHY_1210_DATA - DDRSS2_PHY_1211_DATA - DDRSS2_PHY_1212_DATA - DDRSS2_PHY_1213_DATA - DDRSS2_PHY_1214_DATA - DDRSS2_PHY_1215_DATA - DDRSS2_PHY_1216_DATA - DDRSS2_PHY_1217_DATA - DDRSS2_PHY_1218_DATA - DDRSS2_PHY_1219_DATA - DDRSS2_PHY_1220_DATA - DDRSS2_PHY_1221_DATA - DDRSS2_PHY_1222_DATA - DDRSS2_PHY_1223_DATA - DDRSS2_PHY_1224_DATA - DDRSS2_PHY_1225_DATA - DDRSS2_PHY_1226_DATA - DDRSS2_PHY_1227_DATA - DDRSS2_PHY_1228_DATA - DDRSS2_PHY_1229_DATA - DDRSS2_PHY_1230_DATA - DDRSS2_PHY_1231_DATA - DDRSS2_PHY_1232_DATA - DDRSS2_PHY_1233_DATA - DDRSS2_PHY_1234_DATA - DDRSS2_PHY_1235_DATA - DDRSS2_PHY_1236_DATA - DDRSS2_PHY_1237_DATA - DDRSS2_PHY_1238_DATA - DDRSS2_PHY_1239_DATA - DDRSS2_PHY_1240_DATA - DDRSS2_PHY_1241_DATA - DDRSS2_PHY_1242_DATA - DDRSS2_PHY_1243_DATA - DDRSS2_PHY_1244_DATA - DDRSS2_PHY_1245_DATA - DDRSS2_PHY_1246_DATA - DDRSS2_PHY_1247_DATA - DDRSS2_PHY_1248_DATA - DDRSS2_PHY_1249_DATA - DDRSS2_PHY_1250_DATA - DDRSS2_PHY_1251_DATA - DDRSS2_PHY_1252_DATA - DDRSS2_PHY_1253_DATA - DDRSS2_PHY_1254_DATA - DDRSS2_PHY_1255_DATA - DDRSS2_PHY_1256_DATA - DDRSS2_PHY_1257_DATA - DDRSS2_PHY_1258_DATA - DDRSS2_PHY_1259_DATA - DDRSS2_PHY_1260_DATA - DDRSS2_PHY_1261_DATA - DDRSS2_PHY_1262_DATA - DDRSS2_PHY_1263_DATA - DDRSS2_PHY_1264_DATA - DDRSS2_PHY_1265_DATA - DDRSS2_PHY_1266_DATA - DDRSS2_PHY_1267_DATA - DDRSS2_PHY_1268_DATA - DDRSS2_PHY_1269_DATA - DDRSS2_PHY_1270_DATA - DDRSS2_PHY_1271_DATA - DDRSS2_PHY_1272_DATA - DDRSS2_PHY_1273_DATA - DDRSS2_PHY_1274_DATA - DDRSS2_PHY_1275_DATA - DDRSS2_PHY_1276_DATA - DDRSS2_PHY_1277_DATA - DDRSS2_PHY_1278_DATA - DDRSS2_PHY_1279_DATA - DDRSS2_PHY_1280_DATA - DDRSS2_PHY_1281_DATA - DDRSS2_PHY_1282_DATA - DDRSS2_PHY_1283_DATA - DDRSS2_PHY_1284_DATA - DDRSS2_PHY_1285_DATA - DDRSS2_PHY_1286_DATA - DDRSS2_PHY_1287_DATA - DDRSS2_PHY_1288_DATA - DDRSS2_PHY_1289_DATA - DDRSS2_PHY_1290_DATA - DDRSS2_PHY_1291_DATA - DDRSS2_PHY_1292_DATA - DDRSS2_PHY_1293_DATA - DDRSS2_PHY_1294_DATA - DDRSS2_PHY_1295_DATA - DDRSS2_PHY_1296_DATA - DDRSS2_PHY_1297_DATA - DDRSS2_PHY_1298_DATA - DDRSS2_PHY_1299_DATA - DDRSS2_PHY_1300_DATA - DDRSS2_PHY_1301_DATA - DDRSS2_PHY_1302_DATA - DDRSS2_PHY_1303_DATA - DDRSS2_PHY_1304_DATA - DDRSS2_PHY_1305_DATA - DDRSS2_PHY_1306_DATA - DDRSS2_PHY_1307_DATA - DDRSS2_PHY_1308_DATA - DDRSS2_PHY_1309_DATA - DDRSS2_PHY_1310_DATA - DDRSS2_PHY_1311_DATA - DDRSS2_PHY_1312_DATA - DDRSS2_PHY_1313_DATA - DDRSS2_PHY_1314_DATA - DDRSS2_PHY_1315_DATA - DDRSS2_PHY_1316_DATA - DDRSS2_PHY_1317_DATA - DDRSS2_PHY_1318_DATA - DDRSS2_PHY_1319_DATA - DDRSS2_PHY_1320_DATA - DDRSS2_PHY_1321_DATA - DDRSS2_PHY_1322_DATA - DDRSS2_PHY_1323_DATA - DDRSS2_PHY_1324_DATA - DDRSS2_PHY_1325_DATA - DDRSS2_PHY_1326_DATA - DDRSS2_PHY_1327_DATA - DDRSS2_PHY_1328_DATA - DDRSS2_PHY_1329_DATA - DDRSS2_PHY_1330_DATA - DDRSS2_PHY_1331_DATA - DDRSS2_PHY_1332_DATA - DDRSS2_PHY_1333_DATA - DDRSS2_PHY_1334_DATA - DDRSS2_PHY_1335_DATA - DDRSS2_PHY_1336_DATA - DDRSS2_PHY_1337_DATA - DDRSS2_PHY_1338_DATA - DDRSS2_PHY_1339_DATA - DDRSS2_PHY_1340_DATA - DDRSS2_PHY_1341_DATA - DDRSS2_PHY_1342_DATA - DDRSS2_PHY_1343_DATA - DDRSS2_PHY_1344_DATA - DDRSS2_PHY_1345_DATA - DDRSS2_PHY_1346_DATA - DDRSS2_PHY_1347_DATA - DDRSS2_PHY_1348_DATA - DDRSS2_PHY_1349_DATA - DDRSS2_PHY_1350_DATA - DDRSS2_PHY_1351_DATA - DDRSS2_PHY_1352_DATA - DDRSS2_PHY_1353_DATA - DDRSS2_PHY_1354_DATA - DDRSS2_PHY_1355_DATA - DDRSS2_PHY_1356_DATA - DDRSS2_PHY_1357_DATA - DDRSS2_PHY_1358_DATA - DDRSS2_PHY_1359_DATA - DDRSS2_PHY_1360_DATA - DDRSS2_PHY_1361_DATA - DDRSS2_PHY_1362_DATA - DDRSS2_PHY_1363_DATA - DDRSS2_PHY_1364_DATA - DDRSS2_PHY_1365_DATA - DDRSS2_PHY_1366_DATA - DDRSS2_PHY_1367_DATA - DDRSS2_PHY_1368_DATA - DDRSS2_PHY_1369_DATA - DDRSS2_PHY_1370_DATA - DDRSS2_PHY_1371_DATA - DDRSS2_PHY_1372_DATA - DDRSS2_PHY_1373_DATA - DDRSS2_PHY_1374_DATA - DDRSS2_PHY_1375_DATA - DDRSS2_PHY_1376_DATA - DDRSS2_PHY_1377_DATA - DDRSS2_PHY_1378_DATA - DDRSS2_PHY_1379_DATA - DDRSS2_PHY_1380_DATA - DDRSS2_PHY_1381_DATA - DDRSS2_PHY_1382_DATA - DDRSS2_PHY_1383_DATA - DDRSS2_PHY_1384_DATA - DDRSS2_PHY_1385_DATA - DDRSS2_PHY_1386_DATA - DDRSS2_PHY_1387_DATA - DDRSS2_PHY_1388_DATA - DDRSS2_PHY_1389_DATA - DDRSS2_PHY_1390_DATA - DDRSS2_PHY_1391_DATA - DDRSS2_PHY_1392_DATA - DDRSS2_PHY_1393_DATA - DDRSS2_PHY_1394_DATA - DDRSS2_PHY_1395_DATA - DDRSS2_PHY_1396_DATA - DDRSS2_PHY_1397_DATA - DDRSS2_PHY_1398_DATA - DDRSS2_PHY_1399_DATA - DDRSS2_PHY_1400_DATA - DDRSS2_PHY_1401_DATA - DDRSS2_PHY_1402_DATA - DDRSS2_PHY_1403_DATA - DDRSS2_PHY_1404_DATA - DDRSS2_PHY_1405_DATA - DDRSS2_PHY_1406_DATA - DDRSS2_PHY_1407_DATA - DDRSS2_PHY_1408_DATA - DDRSS2_PHY_1409_DATA - DDRSS2_PHY_1410_DATA - DDRSS2_PHY_1411_DATA - DDRSS2_PHY_1412_DATA - DDRSS2_PHY_1413_DATA - DDRSS2_PHY_1414_DATA - DDRSS2_PHY_1415_DATA - DDRSS2_PHY_1416_DATA - DDRSS2_PHY_1417_DATA - DDRSS2_PHY_1418_DATA - DDRSS2_PHY_1419_DATA - DDRSS2_PHY_1420_DATA - DDRSS2_PHY_1421_DATA - DDRSS2_PHY_1422_DATA - >; - }; + ti,phy-data = < + DDRSS2_PHY_00_DATA + DDRSS2_PHY_01_DATA + DDRSS2_PHY_02_DATA + DDRSS2_PHY_03_DATA + DDRSS2_PHY_04_DATA + DDRSS2_PHY_05_DATA + DDRSS2_PHY_06_DATA + DDRSS2_PHY_07_DATA + DDRSS2_PHY_08_DATA + DDRSS2_PHY_09_DATA + DDRSS2_PHY_10_DATA + DDRSS2_PHY_11_DATA + DDRSS2_PHY_12_DATA + DDRSS2_PHY_13_DATA + DDRSS2_PHY_14_DATA + DDRSS2_PHY_15_DATA + DDRSS2_PHY_16_DATA + DDRSS2_PHY_17_DATA + DDRSS2_PHY_18_DATA + DDRSS2_PHY_19_DATA + DDRSS2_PHY_20_DATA + DDRSS2_PHY_21_DATA + DDRSS2_PHY_22_DATA + DDRSS2_PHY_23_DATA + DDRSS2_PHY_24_DATA + DDRSS2_PHY_25_DATA + DDRSS2_PHY_26_DATA + DDRSS2_PHY_27_DATA + DDRSS2_PHY_28_DATA + DDRSS2_PHY_29_DATA + DDRSS2_PHY_30_DATA + DDRSS2_PHY_31_DATA + DDRSS2_PHY_32_DATA + DDRSS2_PHY_33_DATA + DDRSS2_PHY_34_DATA + DDRSS2_PHY_35_DATA + DDRSS2_PHY_36_DATA + DDRSS2_PHY_37_DATA + DDRSS2_PHY_38_DATA + DDRSS2_PHY_39_DATA + DDRSS2_PHY_40_DATA + DDRSS2_PHY_41_DATA + DDRSS2_PHY_42_DATA + DDRSS2_PHY_43_DATA + DDRSS2_PHY_44_DATA + DDRSS2_PHY_45_DATA + DDRSS2_PHY_46_DATA + DDRSS2_PHY_47_DATA + DDRSS2_PHY_48_DATA + DDRSS2_PHY_49_DATA + DDRSS2_PHY_50_DATA + DDRSS2_PHY_51_DATA + DDRSS2_PHY_52_DATA + DDRSS2_PHY_53_DATA + DDRSS2_PHY_54_DATA + DDRSS2_PHY_55_DATA + DDRSS2_PHY_56_DATA + DDRSS2_PHY_57_DATA + DDRSS2_PHY_58_DATA + DDRSS2_PHY_59_DATA + DDRSS2_PHY_60_DATA + DDRSS2_PHY_61_DATA + DDRSS2_PHY_62_DATA + DDRSS2_PHY_63_DATA + DDRSS2_PHY_64_DATA + DDRSS2_PHY_65_DATA + DDRSS2_PHY_66_DATA + DDRSS2_PHY_67_DATA + DDRSS2_PHY_68_DATA + DDRSS2_PHY_69_DATA + DDRSS2_PHY_70_DATA + DDRSS2_PHY_71_DATA + DDRSS2_PHY_72_DATA + DDRSS2_PHY_73_DATA + DDRSS2_PHY_74_DATA + DDRSS2_PHY_75_DATA + DDRSS2_PHY_76_DATA + DDRSS2_PHY_77_DATA + DDRSS2_PHY_78_DATA + DDRSS2_PHY_79_DATA + DDRSS2_PHY_80_DATA + DDRSS2_PHY_81_DATA + DDRSS2_PHY_82_DATA + DDRSS2_PHY_83_DATA + DDRSS2_PHY_84_DATA + DDRSS2_PHY_85_DATA + DDRSS2_PHY_86_DATA + DDRSS2_PHY_87_DATA + DDRSS2_PHY_88_DATA + DDRSS2_PHY_89_DATA + DDRSS2_PHY_90_DATA + DDRSS2_PHY_91_DATA + DDRSS2_PHY_92_DATA + DDRSS2_PHY_93_DATA + DDRSS2_PHY_94_DATA + DDRSS2_PHY_95_DATA + DDRSS2_PHY_96_DATA + DDRSS2_PHY_97_DATA + DDRSS2_PHY_98_DATA + DDRSS2_PHY_99_DATA + DDRSS2_PHY_100_DATA + DDRSS2_PHY_101_DATA + DDRSS2_PHY_102_DATA + DDRSS2_PHY_103_DATA + DDRSS2_PHY_104_DATA + DDRSS2_PHY_105_DATA + DDRSS2_PHY_106_DATA + DDRSS2_PHY_107_DATA + DDRSS2_PHY_108_DATA + DDRSS2_PHY_109_DATA + DDRSS2_PHY_110_DATA + DDRSS2_PHY_111_DATA + DDRSS2_PHY_112_DATA + DDRSS2_PHY_113_DATA + DDRSS2_PHY_114_DATA + DDRSS2_PHY_115_DATA + DDRSS2_PHY_116_DATA + DDRSS2_PHY_117_DATA + DDRSS2_PHY_118_DATA + DDRSS2_PHY_119_DATA + DDRSS2_PHY_120_DATA + DDRSS2_PHY_121_DATA + DDRSS2_PHY_122_DATA + DDRSS2_PHY_123_DATA + DDRSS2_PHY_124_DATA + DDRSS2_PHY_125_DATA + DDRSS2_PHY_126_DATA + DDRSS2_PHY_127_DATA + DDRSS2_PHY_128_DATA + DDRSS2_PHY_129_DATA + DDRSS2_PHY_130_DATA + DDRSS2_PHY_131_DATA + DDRSS2_PHY_132_DATA + DDRSS2_PHY_133_DATA + DDRSS2_PHY_134_DATA + DDRSS2_PHY_135_DATA + DDRSS2_PHY_136_DATA + DDRSS2_PHY_137_DATA + DDRSS2_PHY_138_DATA + DDRSS2_PHY_139_DATA + DDRSS2_PHY_140_DATA + DDRSS2_PHY_141_DATA + DDRSS2_PHY_142_DATA + DDRSS2_PHY_143_DATA + DDRSS2_PHY_144_DATA + DDRSS2_PHY_145_DATA + DDRSS2_PHY_146_DATA + DDRSS2_PHY_147_DATA + DDRSS2_PHY_148_DATA + DDRSS2_PHY_149_DATA + DDRSS2_PHY_150_DATA + DDRSS2_PHY_151_DATA + DDRSS2_PHY_152_DATA + DDRSS2_PHY_153_DATA + DDRSS2_PHY_154_DATA + DDRSS2_PHY_155_DATA + DDRSS2_PHY_156_DATA + DDRSS2_PHY_157_DATA + DDRSS2_PHY_158_DATA + DDRSS2_PHY_159_DATA + DDRSS2_PHY_160_DATA + DDRSS2_PHY_161_DATA + DDRSS2_PHY_162_DATA + DDRSS2_PHY_163_DATA + DDRSS2_PHY_164_DATA + DDRSS2_PHY_165_DATA + DDRSS2_PHY_166_DATA + DDRSS2_PHY_167_DATA + DDRSS2_PHY_168_DATA + DDRSS2_PHY_169_DATA + DDRSS2_PHY_170_DATA + DDRSS2_PHY_171_DATA + DDRSS2_PHY_172_DATA + DDRSS2_PHY_173_DATA + DDRSS2_PHY_174_DATA + DDRSS2_PHY_175_DATA + DDRSS2_PHY_176_DATA + DDRSS2_PHY_177_DATA + DDRSS2_PHY_178_DATA + DDRSS2_PHY_179_DATA + DDRSS2_PHY_180_DATA + DDRSS2_PHY_181_DATA + DDRSS2_PHY_182_DATA + DDRSS2_PHY_183_DATA + DDRSS2_PHY_184_DATA + DDRSS2_PHY_185_DATA + DDRSS2_PHY_186_DATA + DDRSS2_PHY_187_DATA + DDRSS2_PHY_188_DATA + DDRSS2_PHY_189_DATA + DDRSS2_PHY_190_DATA + DDRSS2_PHY_191_DATA + DDRSS2_PHY_192_DATA + DDRSS2_PHY_193_DATA + DDRSS2_PHY_194_DATA + DDRSS2_PHY_195_DATA + DDRSS2_PHY_196_DATA + DDRSS2_PHY_197_DATA + DDRSS2_PHY_198_DATA + DDRSS2_PHY_199_DATA + DDRSS2_PHY_200_DATA + DDRSS2_PHY_201_DATA + DDRSS2_PHY_202_DATA + DDRSS2_PHY_203_DATA + DDRSS2_PHY_204_DATA + DDRSS2_PHY_205_DATA + DDRSS2_PHY_206_DATA + DDRSS2_PHY_207_DATA + DDRSS2_PHY_208_DATA + DDRSS2_PHY_209_DATA + DDRSS2_PHY_210_DATA + DDRSS2_PHY_211_DATA + DDRSS2_PHY_212_DATA + DDRSS2_PHY_213_DATA + DDRSS2_PHY_214_DATA + DDRSS2_PHY_215_DATA + DDRSS2_PHY_216_DATA + DDRSS2_PHY_217_DATA + DDRSS2_PHY_218_DATA + DDRSS2_PHY_219_DATA + DDRSS2_PHY_220_DATA + DDRSS2_PHY_221_DATA + DDRSS2_PHY_222_DATA + DDRSS2_PHY_223_DATA + DDRSS2_PHY_224_DATA + DDRSS2_PHY_225_DATA + DDRSS2_PHY_226_DATA + DDRSS2_PHY_227_DATA + DDRSS2_PHY_228_DATA + DDRSS2_PHY_229_DATA + DDRSS2_PHY_230_DATA + DDRSS2_PHY_231_DATA + DDRSS2_PHY_232_DATA + DDRSS2_PHY_233_DATA + DDRSS2_PHY_234_DATA + DDRSS2_PHY_235_DATA + DDRSS2_PHY_236_DATA + DDRSS2_PHY_237_DATA + DDRSS2_PHY_238_DATA + DDRSS2_PHY_239_DATA + DDRSS2_PHY_240_DATA + DDRSS2_PHY_241_DATA + DDRSS2_PHY_242_DATA + DDRSS2_PHY_243_DATA + DDRSS2_PHY_244_DATA + DDRSS2_PHY_245_DATA + DDRSS2_PHY_246_DATA + DDRSS2_PHY_247_DATA + DDRSS2_PHY_248_DATA + DDRSS2_PHY_249_DATA + DDRSS2_PHY_250_DATA + DDRSS2_PHY_251_DATA + DDRSS2_PHY_252_DATA + DDRSS2_PHY_253_DATA + DDRSS2_PHY_254_DATA + DDRSS2_PHY_255_DATA + DDRSS2_PHY_256_DATA + DDRSS2_PHY_257_DATA + DDRSS2_PHY_258_DATA + DDRSS2_PHY_259_DATA + DDRSS2_PHY_260_DATA + DDRSS2_PHY_261_DATA + DDRSS2_PHY_262_DATA + DDRSS2_PHY_263_DATA + DDRSS2_PHY_264_DATA + DDRSS2_PHY_265_DATA + DDRSS2_PHY_266_DATA + DDRSS2_PHY_267_DATA + DDRSS2_PHY_268_DATA + DDRSS2_PHY_269_DATA + DDRSS2_PHY_270_DATA + DDRSS2_PHY_271_DATA + DDRSS2_PHY_272_DATA + DDRSS2_PHY_273_DATA + DDRSS2_PHY_274_DATA + DDRSS2_PHY_275_DATA + DDRSS2_PHY_276_DATA + DDRSS2_PHY_277_DATA + DDRSS2_PHY_278_DATA + DDRSS2_PHY_279_DATA + DDRSS2_PHY_280_DATA + DDRSS2_PHY_281_DATA + DDRSS2_PHY_282_DATA + DDRSS2_PHY_283_DATA + DDRSS2_PHY_284_DATA + DDRSS2_PHY_285_DATA + DDRSS2_PHY_286_DATA + DDRSS2_PHY_287_DATA + DDRSS2_PHY_288_DATA + DDRSS2_PHY_289_DATA + DDRSS2_PHY_290_DATA + DDRSS2_PHY_291_DATA + DDRSS2_PHY_292_DATA + DDRSS2_PHY_293_DATA + DDRSS2_PHY_294_DATA + DDRSS2_PHY_295_DATA + DDRSS2_PHY_296_DATA + DDRSS2_PHY_297_DATA + DDRSS2_PHY_298_DATA + DDRSS2_PHY_299_DATA + DDRSS2_PHY_300_DATA + DDRSS2_PHY_301_DATA + DDRSS2_PHY_302_DATA + DDRSS2_PHY_303_DATA + DDRSS2_PHY_304_DATA + DDRSS2_PHY_305_DATA + DDRSS2_PHY_306_DATA + DDRSS2_PHY_307_DATA + DDRSS2_PHY_308_DATA + DDRSS2_PHY_309_DATA + DDRSS2_PHY_310_DATA + DDRSS2_PHY_311_DATA + DDRSS2_PHY_312_DATA + DDRSS2_PHY_313_DATA + DDRSS2_PHY_314_DATA + DDRSS2_PHY_315_DATA + DDRSS2_PHY_316_DATA + DDRSS2_PHY_317_DATA + DDRSS2_PHY_318_DATA + DDRSS2_PHY_319_DATA + DDRSS2_PHY_320_DATA + DDRSS2_PHY_321_DATA + DDRSS2_PHY_322_DATA + DDRSS2_PHY_323_DATA + DDRSS2_PHY_324_DATA + DDRSS2_PHY_325_DATA + DDRSS2_PHY_326_DATA + DDRSS2_PHY_327_DATA + DDRSS2_PHY_328_DATA + DDRSS2_PHY_329_DATA + DDRSS2_PHY_330_DATA + DDRSS2_PHY_331_DATA + DDRSS2_PHY_332_DATA + DDRSS2_PHY_333_DATA + DDRSS2_PHY_334_DATA + DDRSS2_PHY_335_DATA + DDRSS2_PHY_336_DATA + DDRSS2_PHY_337_DATA + DDRSS2_PHY_338_DATA + DDRSS2_PHY_339_DATA + DDRSS2_PHY_340_DATA + DDRSS2_PHY_341_DATA + DDRSS2_PHY_342_DATA + DDRSS2_PHY_343_DATA + DDRSS2_PHY_344_DATA + DDRSS2_PHY_345_DATA + DDRSS2_PHY_346_DATA + DDRSS2_PHY_347_DATA + DDRSS2_PHY_348_DATA + DDRSS2_PHY_349_DATA + DDRSS2_PHY_350_DATA + DDRSS2_PHY_351_DATA + DDRSS2_PHY_352_DATA + DDRSS2_PHY_353_DATA + DDRSS2_PHY_354_DATA + DDRSS2_PHY_355_DATA + DDRSS2_PHY_356_DATA + DDRSS2_PHY_357_DATA + DDRSS2_PHY_358_DATA + DDRSS2_PHY_359_DATA + DDRSS2_PHY_360_DATA + DDRSS2_PHY_361_DATA + DDRSS2_PHY_362_DATA + DDRSS2_PHY_363_DATA + DDRSS2_PHY_364_DATA + DDRSS2_PHY_365_DATA + DDRSS2_PHY_366_DATA + DDRSS2_PHY_367_DATA + DDRSS2_PHY_368_DATA + DDRSS2_PHY_369_DATA + DDRSS2_PHY_370_DATA + DDRSS2_PHY_371_DATA + DDRSS2_PHY_372_DATA + DDRSS2_PHY_373_DATA + DDRSS2_PHY_374_DATA + DDRSS2_PHY_375_DATA + DDRSS2_PHY_376_DATA + DDRSS2_PHY_377_DATA + DDRSS2_PHY_378_DATA + DDRSS2_PHY_379_DATA + DDRSS2_PHY_380_DATA + DDRSS2_PHY_381_DATA + DDRSS2_PHY_382_DATA + DDRSS2_PHY_383_DATA + DDRSS2_PHY_384_DATA + DDRSS2_PHY_385_DATA + DDRSS2_PHY_386_DATA + DDRSS2_PHY_387_DATA + DDRSS2_PHY_388_DATA + DDRSS2_PHY_389_DATA + DDRSS2_PHY_390_DATA + DDRSS2_PHY_391_DATA + DDRSS2_PHY_392_DATA + DDRSS2_PHY_393_DATA + DDRSS2_PHY_394_DATA + DDRSS2_PHY_395_DATA + DDRSS2_PHY_396_DATA + DDRSS2_PHY_397_DATA + DDRSS2_PHY_398_DATA + DDRSS2_PHY_399_DATA + DDRSS2_PHY_400_DATA + DDRSS2_PHY_401_DATA + DDRSS2_PHY_402_DATA + DDRSS2_PHY_403_DATA + DDRSS2_PHY_404_DATA + DDRSS2_PHY_405_DATA + DDRSS2_PHY_406_DATA + DDRSS2_PHY_407_DATA + DDRSS2_PHY_408_DATA + DDRSS2_PHY_409_DATA + DDRSS2_PHY_410_DATA + DDRSS2_PHY_411_DATA + DDRSS2_PHY_412_DATA + DDRSS2_PHY_413_DATA + DDRSS2_PHY_414_DATA + DDRSS2_PHY_415_DATA + DDRSS2_PHY_416_DATA + DDRSS2_PHY_417_DATA + DDRSS2_PHY_418_DATA + DDRSS2_PHY_419_DATA + DDRSS2_PHY_420_DATA + DDRSS2_PHY_421_DATA + DDRSS2_PHY_422_DATA + DDRSS2_PHY_423_DATA + DDRSS2_PHY_424_DATA + DDRSS2_PHY_425_DATA + DDRSS2_PHY_426_DATA + DDRSS2_PHY_427_DATA + DDRSS2_PHY_428_DATA + DDRSS2_PHY_429_DATA + DDRSS2_PHY_430_DATA + DDRSS2_PHY_431_DATA + DDRSS2_PHY_432_DATA + DDRSS2_PHY_433_DATA + DDRSS2_PHY_434_DATA + DDRSS2_PHY_435_DATA + DDRSS2_PHY_436_DATA + DDRSS2_PHY_437_DATA + DDRSS2_PHY_438_DATA + DDRSS2_PHY_439_DATA + DDRSS2_PHY_440_DATA + DDRSS2_PHY_441_DATA + DDRSS2_PHY_442_DATA + DDRSS2_PHY_443_DATA + DDRSS2_PHY_444_DATA + DDRSS2_PHY_445_DATA + DDRSS2_PHY_446_DATA + DDRSS2_PHY_447_DATA + DDRSS2_PHY_448_DATA + DDRSS2_PHY_449_DATA + DDRSS2_PHY_450_DATA + DDRSS2_PHY_451_DATA + DDRSS2_PHY_452_DATA + DDRSS2_PHY_453_DATA + DDRSS2_PHY_454_DATA + DDRSS2_PHY_455_DATA + DDRSS2_PHY_456_DATA + DDRSS2_PHY_457_DATA + DDRSS2_PHY_458_DATA + DDRSS2_PHY_459_DATA + DDRSS2_PHY_460_DATA + DDRSS2_PHY_461_DATA + DDRSS2_PHY_462_DATA + DDRSS2_PHY_463_DATA + DDRSS2_PHY_464_DATA + DDRSS2_PHY_465_DATA + DDRSS2_PHY_466_DATA + DDRSS2_PHY_467_DATA + DDRSS2_PHY_468_DATA + DDRSS2_PHY_469_DATA + DDRSS2_PHY_470_DATA + DDRSS2_PHY_471_DATA + DDRSS2_PHY_472_DATA + DDRSS2_PHY_473_DATA + DDRSS2_PHY_474_DATA + DDRSS2_PHY_475_DATA + DDRSS2_PHY_476_DATA + DDRSS2_PHY_477_DATA + DDRSS2_PHY_478_DATA + DDRSS2_PHY_479_DATA + DDRSS2_PHY_480_DATA + DDRSS2_PHY_481_DATA + DDRSS2_PHY_482_DATA + DDRSS2_PHY_483_DATA + DDRSS2_PHY_484_DATA + DDRSS2_PHY_485_DATA + DDRSS2_PHY_486_DATA + DDRSS2_PHY_487_DATA + DDRSS2_PHY_488_DATA + DDRSS2_PHY_489_DATA + DDRSS2_PHY_490_DATA + DDRSS2_PHY_491_DATA + DDRSS2_PHY_492_DATA + DDRSS2_PHY_493_DATA + DDRSS2_PHY_494_DATA + DDRSS2_PHY_495_DATA + DDRSS2_PHY_496_DATA + DDRSS2_PHY_497_DATA + DDRSS2_PHY_498_DATA + DDRSS2_PHY_499_DATA + DDRSS2_PHY_500_DATA + DDRSS2_PHY_501_DATA + DDRSS2_PHY_502_DATA + DDRSS2_PHY_503_DATA + DDRSS2_PHY_504_DATA + DDRSS2_PHY_505_DATA + DDRSS2_PHY_506_DATA + DDRSS2_PHY_507_DATA + DDRSS2_PHY_508_DATA + DDRSS2_PHY_509_DATA + DDRSS2_PHY_510_DATA + DDRSS2_PHY_511_DATA + DDRSS2_PHY_512_DATA + DDRSS2_PHY_513_DATA + DDRSS2_PHY_514_DATA + DDRSS2_PHY_515_DATA + DDRSS2_PHY_516_DATA + DDRSS2_PHY_517_DATA + DDRSS2_PHY_518_DATA + DDRSS2_PHY_519_DATA + DDRSS2_PHY_520_DATA + DDRSS2_PHY_521_DATA + DDRSS2_PHY_522_DATA + DDRSS2_PHY_523_DATA + DDRSS2_PHY_524_DATA + DDRSS2_PHY_525_DATA + DDRSS2_PHY_526_DATA + DDRSS2_PHY_527_DATA + DDRSS2_PHY_528_DATA + DDRSS2_PHY_529_DATA + DDRSS2_PHY_530_DATA + DDRSS2_PHY_531_DATA + DDRSS2_PHY_532_DATA + DDRSS2_PHY_533_DATA + DDRSS2_PHY_534_DATA + DDRSS2_PHY_535_DATA + DDRSS2_PHY_536_DATA + DDRSS2_PHY_537_DATA + DDRSS2_PHY_538_DATA + DDRSS2_PHY_539_DATA + DDRSS2_PHY_540_DATA + DDRSS2_PHY_541_DATA + DDRSS2_PHY_542_DATA + DDRSS2_PHY_543_DATA + DDRSS2_PHY_544_DATA + DDRSS2_PHY_545_DATA + DDRSS2_PHY_546_DATA + DDRSS2_PHY_547_DATA + DDRSS2_PHY_548_DATA + DDRSS2_PHY_549_DATA + DDRSS2_PHY_550_DATA + DDRSS2_PHY_551_DATA + DDRSS2_PHY_552_DATA + DDRSS2_PHY_553_DATA + DDRSS2_PHY_554_DATA + DDRSS2_PHY_555_DATA + DDRSS2_PHY_556_DATA + DDRSS2_PHY_557_DATA + DDRSS2_PHY_558_DATA + DDRSS2_PHY_559_DATA + DDRSS2_PHY_560_DATA + DDRSS2_PHY_561_DATA + DDRSS2_PHY_562_DATA + DDRSS2_PHY_563_DATA + DDRSS2_PHY_564_DATA + DDRSS2_PHY_565_DATA + DDRSS2_PHY_566_DATA + DDRSS2_PHY_567_DATA + DDRSS2_PHY_568_DATA + DDRSS2_PHY_569_DATA + DDRSS2_PHY_570_DATA + DDRSS2_PHY_571_DATA + DDRSS2_PHY_572_DATA + DDRSS2_PHY_573_DATA + DDRSS2_PHY_574_DATA + DDRSS2_PHY_575_DATA + DDRSS2_PHY_576_DATA + DDRSS2_PHY_577_DATA + DDRSS2_PHY_578_DATA + DDRSS2_PHY_579_DATA + DDRSS2_PHY_580_DATA + DDRSS2_PHY_581_DATA + DDRSS2_PHY_582_DATA + DDRSS2_PHY_583_DATA + DDRSS2_PHY_584_DATA + DDRSS2_PHY_585_DATA + DDRSS2_PHY_586_DATA + DDRSS2_PHY_587_DATA + DDRSS2_PHY_588_DATA + DDRSS2_PHY_589_DATA + DDRSS2_PHY_590_DATA + DDRSS2_PHY_591_DATA + DDRSS2_PHY_592_DATA + DDRSS2_PHY_593_DATA + DDRSS2_PHY_594_DATA + DDRSS2_PHY_595_DATA + DDRSS2_PHY_596_DATA + DDRSS2_PHY_597_DATA + DDRSS2_PHY_598_DATA + DDRSS2_PHY_599_DATA + DDRSS2_PHY_600_DATA + DDRSS2_PHY_601_DATA + DDRSS2_PHY_602_DATA + DDRSS2_PHY_603_DATA + DDRSS2_PHY_604_DATA + DDRSS2_PHY_605_DATA + DDRSS2_PHY_606_DATA + DDRSS2_PHY_607_DATA + DDRSS2_PHY_608_DATA + DDRSS2_PHY_609_DATA + DDRSS2_PHY_610_DATA + DDRSS2_PHY_611_DATA + DDRSS2_PHY_612_DATA + DDRSS2_PHY_613_DATA + DDRSS2_PHY_614_DATA + DDRSS2_PHY_615_DATA + DDRSS2_PHY_616_DATA + DDRSS2_PHY_617_DATA + DDRSS2_PHY_618_DATA + DDRSS2_PHY_619_DATA + DDRSS2_PHY_620_DATA + DDRSS2_PHY_621_DATA + DDRSS2_PHY_622_DATA + DDRSS2_PHY_623_DATA + DDRSS2_PHY_624_DATA + DDRSS2_PHY_625_DATA + DDRSS2_PHY_626_DATA + DDRSS2_PHY_627_DATA + DDRSS2_PHY_628_DATA + DDRSS2_PHY_629_DATA + DDRSS2_PHY_630_DATA + DDRSS2_PHY_631_DATA + DDRSS2_PHY_632_DATA + DDRSS2_PHY_633_DATA + DDRSS2_PHY_634_DATA + DDRSS2_PHY_635_DATA + DDRSS2_PHY_636_DATA + DDRSS2_PHY_637_DATA + DDRSS2_PHY_638_DATA + DDRSS2_PHY_639_DATA + DDRSS2_PHY_640_DATA + DDRSS2_PHY_641_DATA + DDRSS2_PHY_642_DATA + DDRSS2_PHY_643_DATA + DDRSS2_PHY_644_DATA + DDRSS2_PHY_645_DATA + DDRSS2_PHY_646_DATA + DDRSS2_PHY_647_DATA + DDRSS2_PHY_648_DATA + DDRSS2_PHY_649_DATA + DDRSS2_PHY_650_DATA + DDRSS2_PHY_651_DATA + DDRSS2_PHY_652_DATA + DDRSS2_PHY_653_DATA + DDRSS2_PHY_654_DATA + DDRSS2_PHY_655_DATA + DDRSS2_PHY_656_DATA + DDRSS2_PHY_657_DATA + DDRSS2_PHY_658_DATA + DDRSS2_PHY_659_DATA + DDRSS2_PHY_660_DATA + DDRSS2_PHY_661_DATA + DDRSS2_PHY_662_DATA + DDRSS2_PHY_663_DATA + DDRSS2_PHY_664_DATA + DDRSS2_PHY_665_DATA + DDRSS2_PHY_666_DATA + DDRSS2_PHY_667_DATA + DDRSS2_PHY_668_DATA + DDRSS2_PHY_669_DATA + DDRSS2_PHY_670_DATA + DDRSS2_PHY_671_DATA + DDRSS2_PHY_672_DATA + DDRSS2_PHY_673_DATA + DDRSS2_PHY_674_DATA + DDRSS2_PHY_675_DATA + DDRSS2_PHY_676_DATA + DDRSS2_PHY_677_DATA + DDRSS2_PHY_678_DATA + DDRSS2_PHY_679_DATA + DDRSS2_PHY_680_DATA + DDRSS2_PHY_681_DATA + DDRSS2_PHY_682_DATA + DDRSS2_PHY_683_DATA + DDRSS2_PHY_684_DATA + DDRSS2_PHY_685_DATA + DDRSS2_PHY_686_DATA + DDRSS2_PHY_687_DATA + DDRSS2_PHY_688_DATA + DDRSS2_PHY_689_DATA + DDRSS2_PHY_690_DATA + DDRSS2_PHY_691_DATA + DDRSS2_PHY_692_DATA + DDRSS2_PHY_693_DATA + DDRSS2_PHY_694_DATA + DDRSS2_PHY_695_DATA + DDRSS2_PHY_696_DATA + DDRSS2_PHY_697_DATA + DDRSS2_PHY_698_DATA + DDRSS2_PHY_699_DATA + DDRSS2_PHY_700_DATA + DDRSS2_PHY_701_DATA + DDRSS2_PHY_702_DATA + DDRSS2_PHY_703_DATA + DDRSS2_PHY_704_DATA + DDRSS2_PHY_705_DATA + DDRSS2_PHY_706_DATA + DDRSS2_PHY_707_DATA + DDRSS2_PHY_708_DATA + DDRSS2_PHY_709_DATA + DDRSS2_PHY_710_DATA + DDRSS2_PHY_711_DATA + DDRSS2_PHY_712_DATA + DDRSS2_PHY_713_DATA + DDRSS2_PHY_714_DATA + DDRSS2_PHY_715_DATA + DDRSS2_PHY_716_DATA + DDRSS2_PHY_717_DATA + DDRSS2_PHY_718_DATA + DDRSS2_PHY_719_DATA + DDRSS2_PHY_720_DATA + DDRSS2_PHY_721_DATA + DDRSS2_PHY_722_DATA + DDRSS2_PHY_723_DATA + DDRSS2_PHY_724_DATA + DDRSS2_PHY_725_DATA + DDRSS2_PHY_726_DATA + DDRSS2_PHY_727_DATA + DDRSS2_PHY_728_DATA + DDRSS2_PHY_729_DATA + DDRSS2_PHY_730_DATA + DDRSS2_PHY_731_DATA + DDRSS2_PHY_732_DATA + DDRSS2_PHY_733_DATA + DDRSS2_PHY_734_DATA + DDRSS2_PHY_735_DATA + DDRSS2_PHY_736_DATA + DDRSS2_PHY_737_DATA + DDRSS2_PHY_738_DATA + DDRSS2_PHY_739_DATA + DDRSS2_PHY_740_DATA + DDRSS2_PHY_741_DATA + DDRSS2_PHY_742_DATA + DDRSS2_PHY_743_DATA + DDRSS2_PHY_744_DATA + DDRSS2_PHY_745_DATA + DDRSS2_PHY_746_DATA + DDRSS2_PHY_747_DATA + DDRSS2_PHY_748_DATA + DDRSS2_PHY_749_DATA + DDRSS2_PHY_750_DATA + DDRSS2_PHY_751_DATA + DDRSS2_PHY_752_DATA + DDRSS2_PHY_753_DATA + DDRSS2_PHY_754_DATA + DDRSS2_PHY_755_DATA + DDRSS2_PHY_756_DATA + DDRSS2_PHY_757_DATA + DDRSS2_PHY_758_DATA + DDRSS2_PHY_759_DATA + DDRSS2_PHY_760_DATA + DDRSS2_PHY_761_DATA + DDRSS2_PHY_762_DATA + DDRSS2_PHY_763_DATA + DDRSS2_PHY_764_DATA + DDRSS2_PHY_765_DATA + DDRSS2_PHY_766_DATA + DDRSS2_PHY_767_DATA + DDRSS2_PHY_768_DATA + DDRSS2_PHY_769_DATA + DDRSS2_PHY_770_DATA + DDRSS2_PHY_771_DATA + DDRSS2_PHY_772_DATA + DDRSS2_PHY_773_DATA + DDRSS2_PHY_774_DATA + DDRSS2_PHY_775_DATA + DDRSS2_PHY_776_DATA + DDRSS2_PHY_777_DATA + DDRSS2_PHY_778_DATA + DDRSS2_PHY_779_DATA + DDRSS2_PHY_780_DATA + DDRSS2_PHY_781_DATA + DDRSS2_PHY_782_DATA + DDRSS2_PHY_783_DATA + DDRSS2_PHY_784_DATA + DDRSS2_PHY_785_DATA + DDRSS2_PHY_786_DATA + DDRSS2_PHY_787_DATA + DDRSS2_PHY_788_DATA + DDRSS2_PHY_789_DATA + DDRSS2_PHY_790_DATA + DDRSS2_PHY_791_DATA + DDRSS2_PHY_792_DATA + DDRSS2_PHY_793_DATA + DDRSS2_PHY_794_DATA + DDRSS2_PHY_795_DATA + DDRSS2_PHY_796_DATA + DDRSS2_PHY_797_DATA + DDRSS2_PHY_798_DATA + DDRSS2_PHY_799_DATA + DDRSS2_PHY_800_DATA + DDRSS2_PHY_801_DATA + DDRSS2_PHY_802_DATA + DDRSS2_PHY_803_DATA + DDRSS2_PHY_804_DATA + DDRSS2_PHY_805_DATA + DDRSS2_PHY_806_DATA + DDRSS2_PHY_807_DATA + DDRSS2_PHY_808_DATA + DDRSS2_PHY_809_DATA + DDRSS2_PHY_810_DATA + DDRSS2_PHY_811_DATA + DDRSS2_PHY_812_DATA + DDRSS2_PHY_813_DATA + DDRSS2_PHY_814_DATA + DDRSS2_PHY_815_DATA + DDRSS2_PHY_816_DATA + DDRSS2_PHY_817_DATA + DDRSS2_PHY_818_DATA + DDRSS2_PHY_819_DATA + DDRSS2_PHY_820_DATA + DDRSS2_PHY_821_DATA + DDRSS2_PHY_822_DATA + DDRSS2_PHY_823_DATA + DDRSS2_PHY_824_DATA + DDRSS2_PHY_825_DATA + DDRSS2_PHY_826_DATA + DDRSS2_PHY_827_DATA + DDRSS2_PHY_828_DATA + DDRSS2_PHY_829_DATA + DDRSS2_PHY_830_DATA + DDRSS2_PHY_831_DATA + DDRSS2_PHY_832_DATA + DDRSS2_PHY_833_DATA + DDRSS2_PHY_834_DATA + DDRSS2_PHY_835_DATA + DDRSS2_PHY_836_DATA + DDRSS2_PHY_837_DATA + DDRSS2_PHY_838_DATA + DDRSS2_PHY_839_DATA + DDRSS2_PHY_840_DATA + DDRSS2_PHY_841_DATA + DDRSS2_PHY_842_DATA + DDRSS2_PHY_843_DATA + DDRSS2_PHY_844_DATA + DDRSS2_PHY_845_DATA + DDRSS2_PHY_846_DATA + DDRSS2_PHY_847_DATA + DDRSS2_PHY_848_DATA + DDRSS2_PHY_849_DATA + DDRSS2_PHY_850_DATA + DDRSS2_PHY_851_DATA + DDRSS2_PHY_852_DATA + DDRSS2_PHY_853_DATA + DDRSS2_PHY_854_DATA + DDRSS2_PHY_855_DATA + DDRSS2_PHY_856_DATA + DDRSS2_PHY_857_DATA + DDRSS2_PHY_858_DATA + DDRSS2_PHY_859_DATA + DDRSS2_PHY_860_DATA + DDRSS2_PHY_861_DATA + DDRSS2_PHY_862_DATA + DDRSS2_PHY_863_DATA + DDRSS2_PHY_864_DATA + DDRSS2_PHY_865_DATA + DDRSS2_PHY_866_DATA + DDRSS2_PHY_867_DATA + DDRSS2_PHY_868_DATA + DDRSS2_PHY_869_DATA + DDRSS2_PHY_870_DATA + DDRSS2_PHY_871_DATA + DDRSS2_PHY_872_DATA + DDRSS2_PHY_873_DATA + DDRSS2_PHY_874_DATA + DDRSS2_PHY_875_DATA + DDRSS2_PHY_876_DATA + DDRSS2_PHY_877_DATA + DDRSS2_PHY_878_DATA + DDRSS2_PHY_879_DATA + DDRSS2_PHY_880_DATA + DDRSS2_PHY_881_DATA + DDRSS2_PHY_882_DATA + DDRSS2_PHY_883_DATA + DDRSS2_PHY_884_DATA + DDRSS2_PHY_885_DATA + DDRSS2_PHY_886_DATA + DDRSS2_PHY_887_DATA + DDRSS2_PHY_888_DATA + DDRSS2_PHY_889_DATA + DDRSS2_PHY_890_DATA + DDRSS2_PHY_891_DATA + DDRSS2_PHY_892_DATA + DDRSS2_PHY_893_DATA + DDRSS2_PHY_894_DATA + DDRSS2_PHY_895_DATA + DDRSS2_PHY_896_DATA + DDRSS2_PHY_897_DATA + DDRSS2_PHY_898_DATA + DDRSS2_PHY_899_DATA + DDRSS2_PHY_900_DATA + DDRSS2_PHY_901_DATA + DDRSS2_PHY_902_DATA + DDRSS2_PHY_903_DATA + DDRSS2_PHY_904_DATA + DDRSS2_PHY_905_DATA + DDRSS2_PHY_906_DATA + DDRSS2_PHY_907_DATA + DDRSS2_PHY_908_DATA + DDRSS2_PHY_909_DATA + DDRSS2_PHY_910_DATA + DDRSS2_PHY_911_DATA + DDRSS2_PHY_912_DATA + DDRSS2_PHY_913_DATA + DDRSS2_PHY_914_DATA + DDRSS2_PHY_915_DATA + DDRSS2_PHY_916_DATA + DDRSS2_PHY_917_DATA + DDRSS2_PHY_918_DATA + DDRSS2_PHY_919_DATA + DDRSS2_PHY_920_DATA + DDRSS2_PHY_921_DATA + DDRSS2_PHY_922_DATA + DDRSS2_PHY_923_DATA + DDRSS2_PHY_924_DATA + DDRSS2_PHY_925_DATA + DDRSS2_PHY_926_DATA + DDRSS2_PHY_927_DATA + DDRSS2_PHY_928_DATA + DDRSS2_PHY_929_DATA + DDRSS2_PHY_930_DATA + DDRSS2_PHY_931_DATA + DDRSS2_PHY_932_DATA + DDRSS2_PHY_933_DATA + DDRSS2_PHY_934_DATA + DDRSS2_PHY_935_DATA + DDRSS2_PHY_936_DATA + DDRSS2_PHY_937_DATA + DDRSS2_PHY_938_DATA + DDRSS2_PHY_939_DATA + DDRSS2_PHY_940_DATA + DDRSS2_PHY_941_DATA + DDRSS2_PHY_942_DATA + DDRSS2_PHY_943_DATA + DDRSS2_PHY_944_DATA + DDRSS2_PHY_945_DATA + DDRSS2_PHY_946_DATA + DDRSS2_PHY_947_DATA + DDRSS2_PHY_948_DATA + DDRSS2_PHY_949_DATA + DDRSS2_PHY_950_DATA + DDRSS2_PHY_951_DATA + DDRSS2_PHY_952_DATA + DDRSS2_PHY_953_DATA + DDRSS2_PHY_954_DATA + DDRSS2_PHY_955_DATA + DDRSS2_PHY_956_DATA + DDRSS2_PHY_957_DATA + DDRSS2_PHY_958_DATA + DDRSS2_PHY_959_DATA + DDRSS2_PHY_960_DATA + DDRSS2_PHY_961_DATA + DDRSS2_PHY_962_DATA + DDRSS2_PHY_963_DATA + DDRSS2_PHY_964_DATA + DDRSS2_PHY_965_DATA + DDRSS2_PHY_966_DATA + DDRSS2_PHY_967_DATA + DDRSS2_PHY_968_DATA + DDRSS2_PHY_969_DATA + DDRSS2_PHY_970_DATA + DDRSS2_PHY_971_DATA + DDRSS2_PHY_972_DATA + DDRSS2_PHY_973_DATA + DDRSS2_PHY_974_DATA + DDRSS2_PHY_975_DATA + DDRSS2_PHY_976_DATA + DDRSS2_PHY_977_DATA + DDRSS2_PHY_978_DATA + DDRSS2_PHY_979_DATA + DDRSS2_PHY_980_DATA + DDRSS2_PHY_981_DATA + DDRSS2_PHY_982_DATA + DDRSS2_PHY_983_DATA + DDRSS2_PHY_984_DATA + DDRSS2_PHY_985_DATA + DDRSS2_PHY_986_DATA + DDRSS2_PHY_987_DATA + DDRSS2_PHY_988_DATA + DDRSS2_PHY_989_DATA + DDRSS2_PHY_990_DATA + DDRSS2_PHY_991_DATA + DDRSS2_PHY_992_DATA + DDRSS2_PHY_993_DATA + DDRSS2_PHY_994_DATA + DDRSS2_PHY_995_DATA + DDRSS2_PHY_996_DATA + DDRSS2_PHY_997_DATA + DDRSS2_PHY_998_DATA + DDRSS2_PHY_999_DATA + DDRSS2_PHY_1000_DATA + DDRSS2_PHY_1001_DATA + DDRSS2_PHY_1002_DATA + DDRSS2_PHY_1003_DATA + DDRSS2_PHY_1004_DATA + DDRSS2_PHY_1005_DATA + DDRSS2_PHY_1006_DATA + DDRSS2_PHY_1007_DATA + DDRSS2_PHY_1008_DATA + DDRSS2_PHY_1009_DATA + DDRSS2_PHY_1010_DATA + DDRSS2_PHY_1011_DATA + DDRSS2_PHY_1012_DATA + DDRSS2_PHY_1013_DATA + DDRSS2_PHY_1014_DATA + DDRSS2_PHY_1015_DATA + DDRSS2_PHY_1016_DATA + DDRSS2_PHY_1017_DATA + DDRSS2_PHY_1018_DATA + DDRSS2_PHY_1019_DATA + DDRSS2_PHY_1020_DATA + DDRSS2_PHY_1021_DATA + DDRSS2_PHY_1022_DATA + DDRSS2_PHY_1023_DATA + DDRSS2_PHY_1024_DATA + DDRSS2_PHY_1025_DATA + DDRSS2_PHY_1026_DATA + DDRSS2_PHY_1027_DATA + DDRSS2_PHY_1028_DATA + DDRSS2_PHY_1029_DATA + DDRSS2_PHY_1030_DATA + DDRSS2_PHY_1031_DATA + DDRSS2_PHY_1032_DATA + DDRSS2_PHY_1033_DATA + DDRSS2_PHY_1034_DATA + DDRSS2_PHY_1035_DATA + DDRSS2_PHY_1036_DATA + DDRSS2_PHY_1037_DATA + DDRSS2_PHY_1038_DATA + DDRSS2_PHY_1039_DATA + DDRSS2_PHY_1040_DATA + DDRSS2_PHY_1041_DATA + DDRSS2_PHY_1042_DATA + DDRSS2_PHY_1043_DATA + DDRSS2_PHY_1044_DATA + DDRSS2_PHY_1045_DATA + DDRSS2_PHY_1046_DATA + DDRSS2_PHY_1047_DATA + DDRSS2_PHY_1048_DATA + DDRSS2_PHY_1049_DATA + DDRSS2_PHY_1050_DATA + DDRSS2_PHY_1051_DATA + DDRSS2_PHY_1052_DATA + DDRSS2_PHY_1053_DATA + DDRSS2_PHY_1054_DATA + DDRSS2_PHY_1055_DATA + DDRSS2_PHY_1056_DATA + DDRSS2_PHY_1057_DATA + DDRSS2_PHY_1058_DATA + DDRSS2_PHY_1059_DATA + DDRSS2_PHY_1060_DATA + DDRSS2_PHY_1061_DATA + DDRSS2_PHY_1062_DATA + DDRSS2_PHY_1063_DATA + DDRSS2_PHY_1064_DATA + DDRSS2_PHY_1065_DATA + DDRSS2_PHY_1066_DATA + DDRSS2_PHY_1067_DATA + DDRSS2_PHY_1068_DATA + DDRSS2_PHY_1069_DATA + DDRSS2_PHY_1070_DATA + DDRSS2_PHY_1071_DATA + DDRSS2_PHY_1072_DATA + DDRSS2_PHY_1073_DATA + DDRSS2_PHY_1074_DATA + DDRSS2_PHY_1075_DATA + DDRSS2_PHY_1076_DATA + DDRSS2_PHY_1077_DATA + DDRSS2_PHY_1078_DATA + DDRSS2_PHY_1079_DATA + DDRSS2_PHY_1080_DATA + DDRSS2_PHY_1081_DATA + DDRSS2_PHY_1082_DATA + DDRSS2_PHY_1083_DATA + DDRSS2_PHY_1084_DATA + DDRSS2_PHY_1085_DATA + DDRSS2_PHY_1086_DATA + DDRSS2_PHY_1087_DATA + DDRSS2_PHY_1088_DATA + DDRSS2_PHY_1089_DATA + DDRSS2_PHY_1090_DATA + DDRSS2_PHY_1091_DATA + DDRSS2_PHY_1092_DATA + DDRSS2_PHY_1093_DATA + DDRSS2_PHY_1094_DATA + DDRSS2_PHY_1095_DATA + DDRSS2_PHY_1096_DATA + DDRSS2_PHY_1097_DATA + DDRSS2_PHY_1098_DATA + DDRSS2_PHY_1099_DATA + DDRSS2_PHY_1100_DATA + DDRSS2_PHY_1101_DATA + DDRSS2_PHY_1102_DATA + DDRSS2_PHY_1103_DATA + DDRSS2_PHY_1104_DATA + DDRSS2_PHY_1105_DATA + DDRSS2_PHY_1106_DATA + DDRSS2_PHY_1107_DATA + DDRSS2_PHY_1108_DATA + DDRSS2_PHY_1109_DATA + DDRSS2_PHY_1110_DATA + DDRSS2_PHY_1111_DATA + DDRSS2_PHY_1112_DATA + DDRSS2_PHY_1113_DATA + DDRSS2_PHY_1114_DATA + DDRSS2_PHY_1115_DATA + DDRSS2_PHY_1116_DATA + DDRSS2_PHY_1117_DATA + DDRSS2_PHY_1118_DATA + DDRSS2_PHY_1119_DATA + DDRSS2_PHY_1120_DATA + DDRSS2_PHY_1121_DATA + DDRSS2_PHY_1122_DATA + DDRSS2_PHY_1123_DATA + DDRSS2_PHY_1124_DATA + DDRSS2_PHY_1125_DATA + DDRSS2_PHY_1126_DATA + DDRSS2_PHY_1127_DATA + DDRSS2_PHY_1128_DATA + DDRSS2_PHY_1129_DATA + DDRSS2_PHY_1130_DATA + DDRSS2_PHY_1131_DATA + DDRSS2_PHY_1132_DATA + DDRSS2_PHY_1133_DATA + DDRSS2_PHY_1134_DATA + DDRSS2_PHY_1135_DATA + DDRSS2_PHY_1136_DATA + DDRSS2_PHY_1137_DATA + DDRSS2_PHY_1138_DATA + DDRSS2_PHY_1139_DATA + DDRSS2_PHY_1140_DATA + DDRSS2_PHY_1141_DATA + DDRSS2_PHY_1142_DATA + DDRSS2_PHY_1143_DATA + DDRSS2_PHY_1144_DATA + DDRSS2_PHY_1145_DATA + DDRSS2_PHY_1146_DATA + DDRSS2_PHY_1147_DATA + DDRSS2_PHY_1148_DATA + DDRSS2_PHY_1149_DATA + DDRSS2_PHY_1150_DATA + DDRSS2_PHY_1151_DATA + DDRSS2_PHY_1152_DATA + DDRSS2_PHY_1153_DATA + DDRSS2_PHY_1154_DATA + DDRSS2_PHY_1155_DATA + DDRSS2_PHY_1156_DATA + DDRSS2_PHY_1157_DATA + DDRSS2_PHY_1158_DATA + DDRSS2_PHY_1159_DATA + DDRSS2_PHY_1160_DATA + DDRSS2_PHY_1161_DATA + DDRSS2_PHY_1162_DATA + DDRSS2_PHY_1163_DATA + DDRSS2_PHY_1164_DATA + DDRSS2_PHY_1165_DATA + DDRSS2_PHY_1166_DATA + DDRSS2_PHY_1167_DATA + DDRSS2_PHY_1168_DATA + DDRSS2_PHY_1169_DATA + DDRSS2_PHY_1170_DATA + DDRSS2_PHY_1171_DATA + DDRSS2_PHY_1172_DATA + DDRSS2_PHY_1173_DATA + DDRSS2_PHY_1174_DATA + DDRSS2_PHY_1175_DATA + DDRSS2_PHY_1176_DATA + DDRSS2_PHY_1177_DATA + DDRSS2_PHY_1178_DATA + DDRSS2_PHY_1179_DATA + DDRSS2_PHY_1180_DATA + DDRSS2_PHY_1181_DATA + DDRSS2_PHY_1182_DATA + DDRSS2_PHY_1183_DATA + DDRSS2_PHY_1184_DATA + DDRSS2_PHY_1185_DATA + DDRSS2_PHY_1186_DATA + DDRSS2_PHY_1187_DATA + DDRSS2_PHY_1188_DATA + DDRSS2_PHY_1189_DATA + DDRSS2_PHY_1190_DATA + DDRSS2_PHY_1191_DATA + DDRSS2_PHY_1192_DATA + DDRSS2_PHY_1193_DATA + DDRSS2_PHY_1194_DATA + DDRSS2_PHY_1195_DATA + DDRSS2_PHY_1196_DATA + DDRSS2_PHY_1197_DATA + DDRSS2_PHY_1198_DATA + DDRSS2_PHY_1199_DATA + DDRSS2_PHY_1200_DATA + DDRSS2_PHY_1201_DATA + DDRSS2_PHY_1202_DATA + DDRSS2_PHY_1203_DATA + DDRSS2_PHY_1204_DATA + DDRSS2_PHY_1205_DATA + DDRSS2_PHY_1206_DATA + DDRSS2_PHY_1207_DATA + DDRSS2_PHY_1208_DATA + DDRSS2_PHY_1209_DATA + DDRSS2_PHY_1210_DATA + DDRSS2_PHY_1211_DATA + DDRSS2_PHY_1212_DATA + DDRSS2_PHY_1213_DATA + DDRSS2_PHY_1214_DATA + DDRSS2_PHY_1215_DATA + DDRSS2_PHY_1216_DATA + DDRSS2_PHY_1217_DATA + DDRSS2_PHY_1218_DATA + DDRSS2_PHY_1219_DATA + DDRSS2_PHY_1220_DATA + DDRSS2_PHY_1221_DATA + DDRSS2_PHY_1222_DATA + DDRSS2_PHY_1223_DATA + DDRSS2_PHY_1224_DATA + DDRSS2_PHY_1225_DATA + DDRSS2_PHY_1226_DATA + DDRSS2_PHY_1227_DATA + DDRSS2_PHY_1228_DATA + DDRSS2_PHY_1229_DATA + DDRSS2_PHY_1230_DATA + DDRSS2_PHY_1231_DATA + DDRSS2_PHY_1232_DATA + DDRSS2_PHY_1233_DATA + DDRSS2_PHY_1234_DATA + DDRSS2_PHY_1235_DATA + DDRSS2_PHY_1236_DATA + DDRSS2_PHY_1237_DATA + DDRSS2_PHY_1238_DATA + DDRSS2_PHY_1239_DATA + DDRSS2_PHY_1240_DATA + DDRSS2_PHY_1241_DATA + DDRSS2_PHY_1242_DATA + DDRSS2_PHY_1243_DATA + DDRSS2_PHY_1244_DATA + DDRSS2_PHY_1245_DATA + DDRSS2_PHY_1246_DATA + DDRSS2_PHY_1247_DATA + DDRSS2_PHY_1248_DATA + DDRSS2_PHY_1249_DATA + DDRSS2_PHY_1250_DATA + DDRSS2_PHY_1251_DATA + DDRSS2_PHY_1252_DATA + DDRSS2_PHY_1253_DATA + DDRSS2_PHY_1254_DATA + DDRSS2_PHY_1255_DATA + DDRSS2_PHY_1256_DATA + DDRSS2_PHY_1257_DATA + DDRSS2_PHY_1258_DATA + DDRSS2_PHY_1259_DATA + DDRSS2_PHY_1260_DATA + DDRSS2_PHY_1261_DATA + DDRSS2_PHY_1262_DATA + DDRSS2_PHY_1263_DATA + DDRSS2_PHY_1264_DATA + DDRSS2_PHY_1265_DATA + DDRSS2_PHY_1266_DATA + DDRSS2_PHY_1267_DATA + DDRSS2_PHY_1268_DATA + DDRSS2_PHY_1269_DATA + DDRSS2_PHY_1270_DATA + DDRSS2_PHY_1271_DATA + DDRSS2_PHY_1272_DATA + DDRSS2_PHY_1273_DATA + DDRSS2_PHY_1274_DATA + DDRSS2_PHY_1275_DATA + DDRSS2_PHY_1276_DATA + DDRSS2_PHY_1277_DATA + DDRSS2_PHY_1278_DATA + DDRSS2_PHY_1279_DATA + DDRSS2_PHY_1280_DATA + DDRSS2_PHY_1281_DATA + DDRSS2_PHY_1282_DATA + DDRSS2_PHY_1283_DATA + DDRSS2_PHY_1284_DATA + DDRSS2_PHY_1285_DATA + DDRSS2_PHY_1286_DATA + DDRSS2_PHY_1287_DATA + DDRSS2_PHY_1288_DATA + DDRSS2_PHY_1289_DATA + DDRSS2_PHY_1290_DATA + DDRSS2_PHY_1291_DATA + DDRSS2_PHY_1292_DATA + DDRSS2_PHY_1293_DATA + DDRSS2_PHY_1294_DATA + DDRSS2_PHY_1295_DATA + DDRSS2_PHY_1296_DATA + DDRSS2_PHY_1297_DATA + DDRSS2_PHY_1298_DATA + DDRSS2_PHY_1299_DATA + DDRSS2_PHY_1300_DATA + DDRSS2_PHY_1301_DATA + DDRSS2_PHY_1302_DATA + DDRSS2_PHY_1303_DATA + DDRSS2_PHY_1304_DATA + DDRSS2_PHY_1305_DATA + DDRSS2_PHY_1306_DATA + DDRSS2_PHY_1307_DATA + DDRSS2_PHY_1308_DATA + DDRSS2_PHY_1309_DATA + DDRSS2_PHY_1310_DATA + DDRSS2_PHY_1311_DATA + DDRSS2_PHY_1312_DATA + DDRSS2_PHY_1313_DATA + DDRSS2_PHY_1314_DATA + DDRSS2_PHY_1315_DATA + DDRSS2_PHY_1316_DATA + DDRSS2_PHY_1317_DATA + DDRSS2_PHY_1318_DATA + DDRSS2_PHY_1319_DATA + DDRSS2_PHY_1320_DATA + DDRSS2_PHY_1321_DATA + DDRSS2_PHY_1322_DATA + DDRSS2_PHY_1323_DATA + DDRSS2_PHY_1324_DATA + DDRSS2_PHY_1325_DATA + DDRSS2_PHY_1326_DATA + DDRSS2_PHY_1327_DATA + DDRSS2_PHY_1328_DATA + DDRSS2_PHY_1329_DATA + DDRSS2_PHY_1330_DATA + DDRSS2_PHY_1331_DATA + DDRSS2_PHY_1332_DATA + DDRSS2_PHY_1333_DATA + DDRSS2_PHY_1334_DATA + DDRSS2_PHY_1335_DATA + DDRSS2_PHY_1336_DATA + DDRSS2_PHY_1337_DATA + DDRSS2_PHY_1338_DATA + DDRSS2_PHY_1339_DATA + DDRSS2_PHY_1340_DATA + DDRSS2_PHY_1341_DATA + DDRSS2_PHY_1342_DATA + DDRSS2_PHY_1343_DATA + DDRSS2_PHY_1344_DATA + DDRSS2_PHY_1345_DATA + DDRSS2_PHY_1346_DATA + DDRSS2_PHY_1347_DATA + DDRSS2_PHY_1348_DATA + DDRSS2_PHY_1349_DATA + DDRSS2_PHY_1350_DATA + DDRSS2_PHY_1351_DATA + DDRSS2_PHY_1352_DATA + DDRSS2_PHY_1353_DATA + DDRSS2_PHY_1354_DATA + DDRSS2_PHY_1355_DATA + DDRSS2_PHY_1356_DATA + DDRSS2_PHY_1357_DATA + DDRSS2_PHY_1358_DATA + DDRSS2_PHY_1359_DATA + DDRSS2_PHY_1360_DATA + DDRSS2_PHY_1361_DATA + DDRSS2_PHY_1362_DATA + DDRSS2_PHY_1363_DATA + DDRSS2_PHY_1364_DATA + DDRSS2_PHY_1365_DATA + DDRSS2_PHY_1366_DATA + DDRSS2_PHY_1367_DATA + DDRSS2_PHY_1368_DATA + DDRSS2_PHY_1369_DATA + DDRSS2_PHY_1370_DATA + DDRSS2_PHY_1371_DATA + DDRSS2_PHY_1372_DATA + DDRSS2_PHY_1373_DATA + DDRSS2_PHY_1374_DATA + DDRSS2_PHY_1375_DATA + DDRSS2_PHY_1376_DATA + DDRSS2_PHY_1377_DATA + DDRSS2_PHY_1378_DATA + DDRSS2_PHY_1379_DATA + DDRSS2_PHY_1380_DATA + DDRSS2_PHY_1381_DATA + DDRSS2_PHY_1382_DATA + DDRSS2_PHY_1383_DATA + DDRSS2_PHY_1384_DATA + DDRSS2_PHY_1385_DATA + DDRSS2_PHY_1386_DATA + DDRSS2_PHY_1387_DATA + DDRSS2_PHY_1388_DATA + DDRSS2_PHY_1389_DATA + DDRSS2_PHY_1390_DATA + DDRSS2_PHY_1391_DATA + DDRSS2_PHY_1392_DATA + DDRSS2_PHY_1393_DATA + DDRSS2_PHY_1394_DATA + DDRSS2_PHY_1395_DATA + DDRSS2_PHY_1396_DATA + DDRSS2_PHY_1397_DATA + DDRSS2_PHY_1398_DATA + DDRSS2_PHY_1399_DATA + DDRSS2_PHY_1400_DATA + DDRSS2_PHY_1401_DATA + DDRSS2_PHY_1402_DATA + DDRSS2_PHY_1403_DATA + DDRSS2_PHY_1404_DATA + DDRSS2_PHY_1405_DATA + DDRSS2_PHY_1406_DATA + DDRSS2_PHY_1407_DATA + DDRSS2_PHY_1408_DATA + DDRSS2_PHY_1409_DATA + DDRSS2_PHY_1410_DATA + DDRSS2_PHY_1411_DATA + DDRSS2_PHY_1412_DATA + DDRSS2_PHY_1413_DATA + DDRSS2_PHY_1414_DATA + DDRSS2_PHY_1415_DATA + DDRSS2_PHY_1416_DATA + DDRSS2_PHY_1417_DATA + DDRSS2_PHY_1418_DATA + DDRSS2_PHY_1419_DATA + DDRSS2_PHY_1420_DATA + DDRSS2_PHY_1421_DATA + DDRSS2_PHY_1422_DATA + >; + }; - memorycontroller3: memorycontroller@29f0000 { - compatible = "ti,j721s2-ddrss"; - reg = <0x0 0x029f0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>, - <0x0 0x29e0000 0x0 0x200>; - reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; - power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>, - <&k3_pds 139 TI_SCI_PD_SHARED>; - clocks = <&k3_clks 194 1>, <&k3_clks 78 2>; - ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; - ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; - ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; - ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; - instance = <3>; + memorycontroller3: memorycontroller@29f0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029f0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>, + <0x0 0x29e0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; + power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>, + <&k3_pds 139 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 194 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <3>; - bootph-pre-ram; + bootph-pre-ram; - ti,ctl-data = < - DDRSS3_CTL_00_DATA - DDRSS3_CTL_01_DATA - DDRSS3_CTL_02_DATA - DDRSS3_CTL_03_DATA - DDRSS3_CTL_04_DATA - DDRSS3_CTL_05_DATA - DDRSS3_CTL_06_DATA - DDRSS3_CTL_07_DATA - DDRSS3_CTL_08_DATA - DDRSS3_CTL_09_DATA - DDRSS3_CTL_10_DATA - DDRSS3_CTL_11_DATA - DDRSS3_CTL_12_DATA - DDRSS3_CTL_13_DATA - DDRSS3_CTL_14_DATA - DDRSS3_CTL_15_DATA - DDRSS3_CTL_16_DATA - DDRSS3_CTL_17_DATA - DDRSS3_CTL_18_DATA - DDRSS3_CTL_19_DATA - DDRSS3_CTL_20_DATA - DDRSS3_CTL_21_DATA - DDRSS3_CTL_22_DATA - DDRSS3_CTL_23_DATA - DDRSS3_CTL_24_DATA - DDRSS3_CTL_25_DATA - DDRSS3_CTL_26_DATA - DDRSS3_CTL_27_DATA - DDRSS3_CTL_28_DATA - DDRSS3_CTL_29_DATA - DDRSS3_CTL_30_DATA - DDRSS3_CTL_31_DATA - DDRSS3_CTL_32_DATA - DDRSS3_CTL_33_DATA - DDRSS3_CTL_34_DATA - DDRSS3_CTL_35_DATA - DDRSS3_CTL_36_DATA - DDRSS3_CTL_37_DATA - DDRSS3_CTL_38_DATA - DDRSS3_CTL_39_DATA - DDRSS3_CTL_40_DATA - DDRSS3_CTL_41_DATA - DDRSS3_CTL_42_DATA - DDRSS3_CTL_43_DATA - DDRSS3_CTL_44_DATA - DDRSS3_CTL_45_DATA - DDRSS3_CTL_46_DATA - DDRSS3_CTL_47_DATA - DDRSS3_CTL_48_DATA - DDRSS3_CTL_49_DATA - DDRSS3_CTL_50_DATA - DDRSS3_CTL_51_DATA - DDRSS3_CTL_52_DATA - DDRSS3_CTL_53_DATA - DDRSS3_CTL_54_DATA - DDRSS3_CTL_55_DATA - DDRSS3_CTL_56_DATA - DDRSS3_CTL_57_DATA - DDRSS3_CTL_58_DATA - DDRSS3_CTL_59_DATA - DDRSS3_CTL_60_DATA - DDRSS3_CTL_61_DATA - DDRSS3_CTL_62_DATA - DDRSS3_CTL_63_DATA - DDRSS3_CTL_64_DATA - DDRSS3_CTL_65_DATA - DDRSS3_CTL_66_DATA - DDRSS3_CTL_67_DATA - DDRSS3_CTL_68_DATA - DDRSS3_CTL_69_DATA - DDRSS3_CTL_70_DATA - DDRSS3_CTL_71_DATA - DDRSS3_CTL_72_DATA - DDRSS3_CTL_73_DATA - DDRSS3_CTL_74_DATA - DDRSS3_CTL_75_DATA - DDRSS3_CTL_76_DATA - DDRSS3_CTL_77_DATA - DDRSS3_CTL_78_DATA - DDRSS3_CTL_79_DATA - DDRSS3_CTL_80_DATA - DDRSS3_CTL_81_DATA - DDRSS3_CTL_82_DATA - DDRSS3_CTL_83_DATA - DDRSS3_CTL_84_DATA - DDRSS3_CTL_85_DATA - DDRSS3_CTL_86_DATA - DDRSS3_CTL_87_DATA - DDRSS3_CTL_88_DATA - DDRSS3_CTL_89_DATA - DDRSS3_CTL_90_DATA - DDRSS3_CTL_91_DATA - DDRSS3_CTL_92_DATA - DDRSS3_CTL_93_DATA - DDRSS3_CTL_94_DATA - DDRSS3_CTL_95_DATA - DDRSS3_CTL_96_DATA - DDRSS3_CTL_97_DATA - DDRSS3_CTL_98_DATA - DDRSS3_CTL_99_DATA - DDRSS3_CTL_100_DATA - DDRSS3_CTL_101_DATA - DDRSS3_CTL_102_DATA - DDRSS3_CTL_103_DATA - DDRSS3_CTL_104_DATA - DDRSS3_CTL_105_DATA - DDRSS3_CTL_106_DATA - DDRSS3_CTL_107_DATA - DDRSS3_CTL_108_DATA - DDRSS3_CTL_109_DATA - DDRSS3_CTL_110_DATA - DDRSS3_CTL_111_DATA - DDRSS3_CTL_112_DATA - DDRSS3_CTL_113_DATA - DDRSS3_CTL_114_DATA - DDRSS3_CTL_115_DATA - DDRSS3_CTL_116_DATA - DDRSS3_CTL_117_DATA - DDRSS3_CTL_118_DATA - DDRSS3_CTL_119_DATA - DDRSS3_CTL_120_DATA - DDRSS3_CTL_121_DATA - DDRSS3_CTL_122_DATA - DDRSS3_CTL_123_DATA - DDRSS3_CTL_124_DATA - DDRSS3_CTL_125_DATA - DDRSS3_CTL_126_DATA - DDRSS3_CTL_127_DATA - DDRSS3_CTL_128_DATA - DDRSS3_CTL_129_DATA - DDRSS3_CTL_130_DATA - DDRSS3_CTL_131_DATA - DDRSS3_CTL_132_DATA - DDRSS3_CTL_133_DATA - DDRSS3_CTL_134_DATA - DDRSS3_CTL_135_DATA - DDRSS3_CTL_136_DATA - DDRSS3_CTL_137_DATA - DDRSS3_CTL_138_DATA - DDRSS3_CTL_139_DATA - DDRSS3_CTL_140_DATA - DDRSS3_CTL_141_DATA - DDRSS3_CTL_142_DATA - DDRSS3_CTL_143_DATA - DDRSS3_CTL_144_DATA - DDRSS3_CTL_145_DATA - DDRSS3_CTL_146_DATA - DDRSS3_CTL_147_DATA - DDRSS3_CTL_148_DATA - DDRSS3_CTL_149_DATA - DDRSS3_CTL_150_DATA - DDRSS3_CTL_151_DATA - DDRSS3_CTL_152_DATA - DDRSS3_CTL_153_DATA - DDRSS3_CTL_154_DATA - DDRSS3_CTL_155_DATA - DDRSS3_CTL_156_DATA - DDRSS3_CTL_157_DATA - DDRSS3_CTL_158_DATA - DDRSS3_CTL_159_DATA - DDRSS3_CTL_160_DATA - DDRSS3_CTL_161_DATA - DDRSS3_CTL_162_DATA - DDRSS3_CTL_163_DATA - DDRSS3_CTL_164_DATA - DDRSS3_CTL_165_DATA - DDRSS3_CTL_166_DATA - DDRSS3_CTL_167_DATA - DDRSS3_CTL_168_DATA - DDRSS3_CTL_169_DATA - DDRSS3_CTL_170_DATA - DDRSS3_CTL_171_DATA - DDRSS3_CTL_172_DATA - DDRSS3_CTL_173_DATA - DDRSS3_CTL_174_DATA - DDRSS3_CTL_175_DATA - DDRSS3_CTL_176_DATA - DDRSS3_CTL_177_DATA - DDRSS3_CTL_178_DATA - DDRSS3_CTL_179_DATA - DDRSS3_CTL_180_DATA - DDRSS3_CTL_181_DATA - DDRSS3_CTL_182_DATA - DDRSS3_CTL_183_DATA - DDRSS3_CTL_184_DATA - DDRSS3_CTL_185_DATA - DDRSS3_CTL_186_DATA - DDRSS3_CTL_187_DATA - DDRSS3_CTL_188_DATA - DDRSS3_CTL_189_DATA - DDRSS3_CTL_190_DATA - DDRSS3_CTL_191_DATA - DDRSS3_CTL_192_DATA - DDRSS3_CTL_193_DATA - DDRSS3_CTL_194_DATA - DDRSS3_CTL_195_DATA - DDRSS3_CTL_196_DATA - DDRSS3_CTL_197_DATA - DDRSS3_CTL_198_DATA - DDRSS3_CTL_199_DATA - DDRSS3_CTL_200_DATA - DDRSS3_CTL_201_DATA - DDRSS3_CTL_202_DATA - DDRSS3_CTL_203_DATA - DDRSS3_CTL_204_DATA - DDRSS3_CTL_205_DATA - DDRSS3_CTL_206_DATA - DDRSS3_CTL_207_DATA - DDRSS3_CTL_208_DATA - DDRSS3_CTL_209_DATA - DDRSS3_CTL_210_DATA - DDRSS3_CTL_211_DATA - DDRSS3_CTL_212_DATA - DDRSS3_CTL_213_DATA - DDRSS3_CTL_214_DATA - DDRSS3_CTL_215_DATA - DDRSS3_CTL_216_DATA - DDRSS3_CTL_217_DATA - DDRSS3_CTL_218_DATA - DDRSS3_CTL_219_DATA - DDRSS3_CTL_220_DATA - DDRSS3_CTL_221_DATA - DDRSS3_CTL_222_DATA - DDRSS3_CTL_223_DATA - DDRSS3_CTL_224_DATA - DDRSS3_CTL_225_DATA - DDRSS3_CTL_226_DATA - DDRSS3_CTL_227_DATA - DDRSS3_CTL_228_DATA - DDRSS3_CTL_229_DATA - DDRSS3_CTL_230_DATA - DDRSS3_CTL_231_DATA - DDRSS3_CTL_232_DATA - DDRSS3_CTL_233_DATA - DDRSS3_CTL_234_DATA - DDRSS3_CTL_235_DATA - DDRSS3_CTL_236_DATA - DDRSS3_CTL_237_DATA - DDRSS3_CTL_238_DATA - DDRSS3_CTL_239_DATA - DDRSS3_CTL_240_DATA - DDRSS3_CTL_241_DATA - DDRSS3_CTL_242_DATA - DDRSS3_CTL_243_DATA - DDRSS3_CTL_244_DATA - DDRSS3_CTL_245_DATA - DDRSS3_CTL_246_DATA - DDRSS3_CTL_247_DATA - DDRSS3_CTL_248_DATA - DDRSS3_CTL_249_DATA - DDRSS3_CTL_250_DATA - DDRSS3_CTL_251_DATA - DDRSS3_CTL_252_DATA - DDRSS3_CTL_253_DATA - DDRSS3_CTL_254_DATA - DDRSS3_CTL_255_DATA - DDRSS3_CTL_256_DATA - DDRSS3_CTL_257_DATA - DDRSS3_CTL_258_DATA - DDRSS3_CTL_259_DATA - DDRSS3_CTL_260_DATA - DDRSS3_CTL_261_DATA - DDRSS3_CTL_262_DATA - DDRSS3_CTL_263_DATA - DDRSS3_CTL_264_DATA - DDRSS3_CTL_265_DATA - DDRSS3_CTL_266_DATA - DDRSS3_CTL_267_DATA - DDRSS3_CTL_268_DATA - DDRSS3_CTL_269_DATA - DDRSS3_CTL_270_DATA - DDRSS3_CTL_271_DATA - DDRSS3_CTL_272_DATA - DDRSS3_CTL_273_DATA - DDRSS3_CTL_274_DATA - DDRSS3_CTL_275_DATA - DDRSS3_CTL_276_DATA - DDRSS3_CTL_277_DATA - DDRSS3_CTL_278_DATA - DDRSS3_CTL_279_DATA - DDRSS3_CTL_280_DATA - DDRSS3_CTL_281_DATA - DDRSS3_CTL_282_DATA - DDRSS3_CTL_283_DATA - DDRSS3_CTL_284_DATA - DDRSS3_CTL_285_DATA - DDRSS3_CTL_286_DATA - DDRSS3_CTL_287_DATA - DDRSS3_CTL_288_DATA - DDRSS3_CTL_289_DATA - DDRSS3_CTL_290_DATA - DDRSS3_CTL_291_DATA - DDRSS3_CTL_292_DATA - DDRSS3_CTL_293_DATA - DDRSS3_CTL_294_DATA - DDRSS3_CTL_295_DATA - DDRSS3_CTL_296_DATA - DDRSS3_CTL_297_DATA - DDRSS3_CTL_298_DATA - DDRSS3_CTL_299_DATA - DDRSS3_CTL_300_DATA - DDRSS3_CTL_301_DATA - DDRSS3_CTL_302_DATA - DDRSS3_CTL_303_DATA - DDRSS3_CTL_304_DATA - DDRSS3_CTL_305_DATA - DDRSS3_CTL_306_DATA - DDRSS3_CTL_307_DATA - DDRSS3_CTL_308_DATA - DDRSS3_CTL_309_DATA - DDRSS3_CTL_310_DATA - DDRSS3_CTL_311_DATA - DDRSS3_CTL_312_DATA - DDRSS3_CTL_313_DATA - DDRSS3_CTL_314_DATA - DDRSS3_CTL_315_DATA - DDRSS3_CTL_316_DATA - DDRSS3_CTL_317_DATA - DDRSS3_CTL_318_DATA - DDRSS3_CTL_319_DATA - DDRSS3_CTL_320_DATA - DDRSS3_CTL_321_DATA - DDRSS3_CTL_322_DATA - DDRSS3_CTL_323_DATA - DDRSS3_CTL_324_DATA - DDRSS3_CTL_325_DATA - DDRSS3_CTL_326_DATA - DDRSS3_CTL_327_DATA - DDRSS3_CTL_328_DATA - DDRSS3_CTL_329_DATA - DDRSS3_CTL_330_DATA - DDRSS3_CTL_331_DATA - DDRSS3_CTL_332_DATA - DDRSS3_CTL_333_DATA - DDRSS3_CTL_334_DATA - DDRSS3_CTL_335_DATA - DDRSS3_CTL_336_DATA - DDRSS3_CTL_337_DATA - DDRSS3_CTL_338_DATA - DDRSS3_CTL_339_DATA - DDRSS3_CTL_340_DATA - DDRSS3_CTL_341_DATA - DDRSS3_CTL_342_DATA - DDRSS3_CTL_343_DATA - DDRSS3_CTL_344_DATA - DDRSS3_CTL_345_DATA - DDRSS3_CTL_346_DATA - DDRSS3_CTL_347_DATA - DDRSS3_CTL_348_DATA - DDRSS3_CTL_349_DATA - DDRSS3_CTL_350_DATA - DDRSS3_CTL_351_DATA - DDRSS3_CTL_352_DATA - DDRSS3_CTL_353_DATA - DDRSS3_CTL_354_DATA - DDRSS3_CTL_355_DATA - DDRSS3_CTL_356_DATA - DDRSS3_CTL_357_DATA - DDRSS3_CTL_358_DATA - DDRSS3_CTL_359_DATA - DDRSS3_CTL_360_DATA - DDRSS3_CTL_361_DATA - DDRSS3_CTL_362_DATA - DDRSS3_CTL_363_DATA - DDRSS3_CTL_364_DATA - DDRSS3_CTL_365_DATA - DDRSS3_CTL_366_DATA - DDRSS3_CTL_367_DATA - DDRSS3_CTL_368_DATA - DDRSS3_CTL_369_DATA - DDRSS3_CTL_370_DATA - DDRSS3_CTL_371_DATA - DDRSS3_CTL_372_DATA - DDRSS3_CTL_373_DATA - DDRSS3_CTL_374_DATA - DDRSS3_CTL_375_DATA - DDRSS3_CTL_376_DATA - DDRSS3_CTL_377_DATA - DDRSS3_CTL_378_DATA - DDRSS3_CTL_379_DATA - DDRSS3_CTL_380_DATA - DDRSS3_CTL_381_DATA - DDRSS3_CTL_382_DATA - DDRSS3_CTL_383_DATA - DDRSS3_CTL_384_DATA - DDRSS3_CTL_385_DATA - DDRSS3_CTL_386_DATA - DDRSS3_CTL_387_DATA - DDRSS3_CTL_388_DATA - DDRSS3_CTL_389_DATA - DDRSS3_CTL_390_DATA - DDRSS3_CTL_391_DATA - DDRSS3_CTL_392_DATA - DDRSS3_CTL_393_DATA - DDRSS3_CTL_394_DATA - DDRSS3_CTL_395_DATA - DDRSS3_CTL_396_DATA - DDRSS3_CTL_397_DATA - DDRSS3_CTL_398_DATA - DDRSS3_CTL_399_DATA - DDRSS3_CTL_400_DATA - DDRSS3_CTL_401_DATA - DDRSS3_CTL_402_DATA - DDRSS3_CTL_403_DATA - DDRSS3_CTL_404_DATA - DDRSS3_CTL_405_DATA - DDRSS3_CTL_406_DATA - DDRSS3_CTL_407_DATA - DDRSS3_CTL_408_DATA - DDRSS3_CTL_409_DATA - DDRSS3_CTL_410_DATA - DDRSS3_CTL_411_DATA - DDRSS3_CTL_412_DATA - DDRSS3_CTL_413_DATA - DDRSS3_CTL_414_DATA - DDRSS3_CTL_415_DATA - DDRSS3_CTL_416_DATA - DDRSS3_CTL_417_DATA - DDRSS3_CTL_418_DATA - DDRSS3_CTL_419_DATA - DDRSS3_CTL_420_DATA - DDRSS3_CTL_421_DATA - DDRSS3_CTL_422_DATA - DDRSS3_CTL_423_DATA - DDRSS3_CTL_424_DATA - DDRSS3_CTL_425_DATA - DDRSS3_CTL_426_DATA - DDRSS3_CTL_427_DATA - DDRSS3_CTL_428_DATA - DDRSS3_CTL_429_DATA - DDRSS3_CTL_430_DATA - DDRSS3_CTL_431_DATA - DDRSS3_CTL_432_DATA - DDRSS3_CTL_433_DATA - DDRSS3_CTL_434_DATA - DDRSS3_CTL_435_DATA - DDRSS3_CTL_436_DATA - DDRSS3_CTL_437_DATA - DDRSS3_CTL_438_DATA - DDRSS3_CTL_439_DATA - DDRSS3_CTL_440_DATA - DDRSS3_CTL_441_DATA - DDRSS3_CTL_442_DATA - DDRSS3_CTL_443_DATA - DDRSS3_CTL_444_DATA - DDRSS3_CTL_445_DATA - DDRSS3_CTL_446_DATA - DDRSS3_CTL_447_DATA - DDRSS3_CTL_448_DATA - DDRSS3_CTL_449_DATA - DDRSS3_CTL_450_DATA - DDRSS3_CTL_451_DATA - DDRSS3_CTL_452_DATA - DDRSS3_CTL_453_DATA - DDRSS3_CTL_454_DATA - DDRSS3_CTL_455_DATA - DDRSS3_CTL_456_DATA - DDRSS3_CTL_457_DATA - DDRSS3_CTL_458_DATA - >; + ti,ctl-data = < + DDRSS3_CTL_00_DATA + DDRSS3_CTL_01_DATA + DDRSS3_CTL_02_DATA + DDRSS3_CTL_03_DATA + DDRSS3_CTL_04_DATA + DDRSS3_CTL_05_DATA + DDRSS3_CTL_06_DATA + DDRSS3_CTL_07_DATA + DDRSS3_CTL_08_DATA + DDRSS3_CTL_09_DATA + DDRSS3_CTL_10_DATA + DDRSS3_CTL_11_DATA + DDRSS3_CTL_12_DATA + DDRSS3_CTL_13_DATA + DDRSS3_CTL_14_DATA + DDRSS3_CTL_15_DATA + DDRSS3_CTL_16_DATA + DDRSS3_CTL_17_DATA + DDRSS3_CTL_18_DATA + DDRSS3_CTL_19_DATA + DDRSS3_CTL_20_DATA + DDRSS3_CTL_21_DATA + DDRSS3_CTL_22_DATA + DDRSS3_CTL_23_DATA + DDRSS3_CTL_24_DATA + DDRSS3_CTL_25_DATA + DDRSS3_CTL_26_DATA + DDRSS3_CTL_27_DATA + DDRSS3_CTL_28_DATA + DDRSS3_CTL_29_DATA + DDRSS3_CTL_30_DATA + DDRSS3_CTL_31_DATA + DDRSS3_CTL_32_DATA + DDRSS3_CTL_33_DATA + DDRSS3_CTL_34_DATA + DDRSS3_CTL_35_DATA + DDRSS3_CTL_36_DATA + DDRSS3_CTL_37_DATA + DDRSS3_CTL_38_DATA + DDRSS3_CTL_39_DATA + DDRSS3_CTL_40_DATA + DDRSS3_CTL_41_DATA + DDRSS3_CTL_42_DATA + DDRSS3_CTL_43_DATA + DDRSS3_CTL_44_DATA + DDRSS3_CTL_45_DATA + DDRSS3_CTL_46_DATA + DDRSS3_CTL_47_DATA + DDRSS3_CTL_48_DATA + DDRSS3_CTL_49_DATA + DDRSS3_CTL_50_DATA + DDRSS3_CTL_51_DATA + DDRSS3_CTL_52_DATA + DDRSS3_CTL_53_DATA + DDRSS3_CTL_54_DATA + DDRSS3_CTL_55_DATA + DDRSS3_CTL_56_DATA + DDRSS3_CTL_57_DATA + DDRSS3_CTL_58_DATA + DDRSS3_CTL_59_DATA + DDRSS3_CTL_60_DATA + DDRSS3_CTL_61_DATA + DDRSS3_CTL_62_DATA + DDRSS3_CTL_63_DATA + DDRSS3_CTL_64_DATA + DDRSS3_CTL_65_DATA + DDRSS3_CTL_66_DATA + DDRSS3_CTL_67_DATA + DDRSS3_CTL_68_DATA + DDRSS3_CTL_69_DATA + DDRSS3_CTL_70_DATA + DDRSS3_CTL_71_DATA + DDRSS3_CTL_72_DATA + DDRSS3_CTL_73_DATA + DDRSS3_CTL_74_DATA + DDRSS3_CTL_75_DATA + DDRSS3_CTL_76_DATA + DDRSS3_CTL_77_DATA + DDRSS3_CTL_78_DATA + DDRSS3_CTL_79_DATA + DDRSS3_CTL_80_DATA + DDRSS3_CTL_81_DATA + DDRSS3_CTL_82_DATA + DDRSS3_CTL_83_DATA + DDRSS3_CTL_84_DATA + DDRSS3_CTL_85_DATA + DDRSS3_CTL_86_DATA + DDRSS3_CTL_87_DATA + DDRSS3_CTL_88_DATA + DDRSS3_CTL_89_DATA + DDRSS3_CTL_90_DATA + DDRSS3_CTL_91_DATA + DDRSS3_CTL_92_DATA + DDRSS3_CTL_93_DATA + DDRSS3_CTL_94_DATA + DDRSS3_CTL_95_DATA + DDRSS3_CTL_96_DATA + DDRSS3_CTL_97_DATA + DDRSS3_CTL_98_DATA + DDRSS3_CTL_99_DATA + DDRSS3_CTL_100_DATA + DDRSS3_CTL_101_DATA + DDRSS3_CTL_102_DATA + DDRSS3_CTL_103_DATA + DDRSS3_CTL_104_DATA + DDRSS3_CTL_105_DATA + DDRSS3_CTL_106_DATA + DDRSS3_CTL_107_DATA + DDRSS3_CTL_108_DATA + DDRSS3_CTL_109_DATA + DDRSS3_CTL_110_DATA + DDRSS3_CTL_111_DATA + DDRSS3_CTL_112_DATA + DDRSS3_CTL_113_DATA + DDRSS3_CTL_114_DATA + DDRSS3_CTL_115_DATA + DDRSS3_CTL_116_DATA + DDRSS3_CTL_117_DATA + DDRSS3_CTL_118_DATA + DDRSS3_CTL_119_DATA + DDRSS3_CTL_120_DATA + DDRSS3_CTL_121_DATA + DDRSS3_CTL_122_DATA + DDRSS3_CTL_123_DATA + DDRSS3_CTL_124_DATA + DDRSS3_CTL_125_DATA + DDRSS3_CTL_126_DATA + DDRSS3_CTL_127_DATA + DDRSS3_CTL_128_DATA + DDRSS3_CTL_129_DATA + DDRSS3_CTL_130_DATA + DDRSS3_CTL_131_DATA + DDRSS3_CTL_132_DATA + DDRSS3_CTL_133_DATA + DDRSS3_CTL_134_DATA + DDRSS3_CTL_135_DATA + DDRSS3_CTL_136_DATA + DDRSS3_CTL_137_DATA + DDRSS3_CTL_138_DATA + DDRSS3_CTL_139_DATA + DDRSS3_CTL_140_DATA + DDRSS3_CTL_141_DATA + DDRSS3_CTL_142_DATA + DDRSS3_CTL_143_DATA + DDRSS3_CTL_144_DATA + DDRSS3_CTL_145_DATA + DDRSS3_CTL_146_DATA + DDRSS3_CTL_147_DATA + DDRSS3_CTL_148_DATA + DDRSS3_CTL_149_DATA + DDRSS3_CTL_150_DATA + DDRSS3_CTL_151_DATA + DDRSS3_CTL_152_DATA + DDRSS3_CTL_153_DATA + DDRSS3_CTL_154_DATA + DDRSS3_CTL_155_DATA + DDRSS3_CTL_156_DATA + DDRSS3_CTL_157_DATA + DDRSS3_CTL_158_DATA + DDRSS3_CTL_159_DATA + DDRSS3_CTL_160_DATA + DDRSS3_CTL_161_DATA + DDRSS3_CTL_162_DATA + DDRSS3_CTL_163_DATA + DDRSS3_CTL_164_DATA + DDRSS3_CTL_165_DATA + DDRSS3_CTL_166_DATA + DDRSS3_CTL_167_DATA + DDRSS3_CTL_168_DATA + DDRSS3_CTL_169_DATA + DDRSS3_CTL_170_DATA + DDRSS3_CTL_171_DATA + DDRSS3_CTL_172_DATA + DDRSS3_CTL_173_DATA + DDRSS3_CTL_174_DATA + DDRSS3_CTL_175_DATA + DDRSS3_CTL_176_DATA + DDRSS3_CTL_177_DATA + DDRSS3_CTL_178_DATA + DDRSS3_CTL_179_DATA + DDRSS3_CTL_180_DATA + DDRSS3_CTL_181_DATA + DDRSS3_CTL_182_DATA + DDRSS3_CTL_183_DATA + DDRSS3_CTL_184_DATA + DDRSS3_CTL_185_DATA + DDRSS3_CTL_186_DATA + DDRSS3_CTL_187_DATA + DDRSS3_CTL_188_DATA + DDRSS3_CTL_189_DATA + DDRSS3_CTL_190_DATA + DDRSS3_CTL_191_DATA + DDRSS3_CTL_192_DATA + DDRSS3_CTL_193_DATA + DDRSS3_CTL_194_DATA + DDRSS3_CTL_195_DATA + DDRSS3_CTL_196_DATA + DDRSS3_CTL_197_DATA + DDRSS3_CTL_198_DATA + DDRSS3_CTL_199_DATA + DDRSS3_CTL_200_DATA + DDRSS3_CTL_201_DATA + DDRSS3_CTL_202_DATA + DDRSS3_CTL_203_DATA + DDRSS3_CTL_204_DATA + DDRSS3_CTL_205_DATA + DDRSS3_CTL_206_DATA + DDRSS3_CTL_207_DATA + DDRSS3_CTL_208_DATA + DDRSS3_CTL_209_DATA + DDRSS3_CTL_210_DATA + DDRSS3_CTL_211_DATA + DDRSS3_CTL_212_DATA + DDRSS3_CTL_213_DATA + DDRSS3_CTL_214_DATA + DDRSS3_CTL_215_DATA + DDRSS3_CTL_216_DATA + DDRSS3_CTL_217_DATA + DDRSS3_CTL_218_DATA + DDRSS3_CTL_219_DATA + DDRSS3_CTL_220_DATA + DDRSS3_CTL_221_DATA + DDRSS3_CTL_222_DATA + DDRSS3_CTL_223_DATA + DDRSS3_CTL_224_DATA + DDRSS3_CTL_225_DATA + DDRSS3_CTL_226_DATA + DDRSS3_CTL_227_DATA + DDRSS3_CTL_228_DATA + DDRSS3_CTL_229_DATA + DDRSS3_CTL_230_DATA + DDRSS3_CTL_231_DATA + DDRSS3_CTL_232_DATA + DDRSS3_CTL_233_DATA + DDRSS3_CTL_234_DATA + DDRSS3_CTL_235_DATA + DDRSS3_CTL_236_DATA + DDRSS3_CTL_237_DATA + DDRSS3_CTL_238_DATA + DDRSS3_CTL_239_DATA + DDRSS3_CTL_240_DATA + DDRSS3_CTL_241_DATA + DDRSS3_CTL_242_DATA + DDRSS3_CTL_243_DATA + DDRSS3_CTL_244_DATA + DDRSS3_CTL_245_DATA + DDRSS3_CTL_246_DATA + DDRSS3_CTL_247_DATA + DDRSS3_CTL_248_DATA + DDRSS3_CTL_249_DATA + DDRSS3_CTL_250_DATA + DDRSS3_CTL_251_DATA + DDRSS3_CTL_252_DATA + DDRSS3_CTL_253_DATA + DDRSS3_CTL_254_DATA + DDRSS3_CTL_255_DATA + DDRSS3_CTL_256_DATA + DDRSS3_CTL_257_DATA + DDRSS3_CTL_258_DATA + DDRSS3_CTL_259_DATA + DDRSS3_CTL_260_DATA + DDRSS3_CTL_261_DATA + DDRSS3_CTL_262_DATA + DDRSS3_CTL_263_DATA + DDRSS3_CTL_264_DATA + DDRSS3_CTL_265_DATA + DDRSS3_CTL_266_DATA + DDRSS3_CTL_267_DATA + DDRSS3_CTL_268_DATA + DDRSS3_CTL_269_DATA + DDRSS3_CTL_270_DATA + DDRSS3_CTL_271_DATA + DDRSS3_CTL_272_DATA + DDRSS3_CTL_273_DATA + DDRSS3_CTL_274_DATA + DDRSS3_CTL_275_DATA + DDRSS3_CTL_276_DATA + DDRSS3_CTL_277_DATA + DDRSS3_CTL_278_DATA + DDRSS3_CTL_279_DATA + DDRSS3_CTL_280_DATA + DDRSS3_CTL_281_DATA + DDRSS3_CTL_282_DATA + DDRSS3_CTL_283_DATA + DDRSS3_CTL_284_DATA + DDRSS3_CTL_285_DATA + DDRSS3_CTL_286_DATA + DDRSS3_CTL_287_DATA + DDRSS3_CTL_288_DATA + DDRSS3_CTL_289_DATA + DDRSS3_CTL_290_DATA + DDRSS3_CTL_291_DATA + DDRSS3_CTL_292_DATA + DDRSS3_CTL_293_DATA + DDRSS3_CTL_294_DATA + DDRSS3_CTL_295_DATA + DDRSS3_CTL_296_DATA + DDRSS3_CTL_297_DATA + DDRSS3_CTL_298_DATA + DDRSS3_CTL_299_DATA + DDRSS3_CTL_300_DATA + DDRSS3_CTL_301_DATA + DDRSS3_CTL_302_DATA + DDRSS3_CTL_303_DATA + DDRSS3_CTL_304_DATA + DDRSS3_CTL_305_DATA + DDRSS3_CTL_306_DATA + DDRSS3_CTL_307_DATA + DDRSS3_CTL_308_DATA + DDRSS3_CTL_309_DATA + DDRSS3_CTL_310_DATA + DDRSS3_CTL_311_DATA + DDRSS3_CTL_312_DATA + DDRSS3_CTL_313_DATA + DDRSS3_CTL_314_DATA + DDRSS3_CTL_315_DATA + DDRSS3_CTL_316_DATA + DDRSS3_CTL_317_DATA + DDRSS3_CTL_318_DATA + DDRSS3_CTL_319_DATA + DDRSS3_CTL_320_DATA + DDRSS3_CTL_321_DATA + DDRSS3_CTL_322_DATA + DDRSS3_CTL_323_DATA + DDRSS3_CTL_324_DATA + DDRSS3_CTL_325_DATA + DDRSS3_CTL_326_DATA + DDRSS3_CTL_327_DATA + DDRSS3_CTL_328_DATA + DDRSS3_CTL_329_DATA + DDRSS3_CTL_330_DATA + DDRSS3_CTL_331_DATA + DDRSS3_CTL_332_DATA + DDRSS3_CTL_333_DATA + DDRSS3_CTL_334_DATA + DDRSS3_CTL_335_DATA + DDRSS3_CTL_336_DATA + DDRSS3_CTL_337_DATA + DDRSS3_CTL_338_DATA + DDRSS3_CTL_339_DATA + DDRSS3_CTL_340_DATA + DDRSS3_CTL_341_DATA + DDRSS3_CTL_342_DATA + DDRSS3_CTL_343_DATA + DDRSS3_CTL_344_DATA + DDRSS3_CTL_345_DATA + DDRSS3_CTL_346_DATA + DDRSS3_CTL_347_DATA + DDRSS3_CTL_348_DATA + DDRSS3_CTL_349_DATA + DDRSS3_CTL_350_DATA + DDRSS3_CTL_351_DATA + DDRSS3_CTL_352_DATA + DDRSS3_CTL_353_DATA + DDRSS3_CTL_354_DATA + DDRSS3_CTL_355_DATA + DDRSS3_CTL_356_DATA + DDRSS3_CTL_357_DATA + DDRSS3_CTL_358_DATA + DDRSS3_CTL_359_DATA + DDRSS3_CTL_360_DATA + DDRSS3_CTL_361_DATA + DDRSS3_CTL_362_DATA + DDRSS3_CTL_363_DATA + DDRSS3_CTL_364_DATA + DDRSS3_CTL_365_DATA + DDRSS3_CTL_366_DATA + DDRSS3_CTL_367_DATA + DDRSS3_CTL_368_DATA + DDRSS3_CTL_369_DATA + DDRSS3_CTL_370_DATA + DDRSS3_CTL_371_DATA + DDRSS3_CTL_372_DATA + DDRSS3_CTL_373_DATA + DDRSS3_CTL_374_DATA + DDRSS3_CTL_375_DATA + DDRSS3_CTL_376_DATA + DDRSS3_CTL_377_DATA + DDRSS3_CTL_378_DATA + DDRSS3_CTL_379_DATA + DDRSS3_CTL_380_DATA + DDRSS3_CTL_381_DATA + DDRSS3_CTL_382_DATA + DDRSS3_CTL_383_DATA + DDRSS3_CTL_384_DATA + DDRSS3_CTL_385_DATA + DDRSS3_CTL_386_DATA + DDRSS3_CTL_387_DATA + DDRSS3_CTL_388_DATA + DDRSS3_CTL_389_DATA + DDRSS3_CTL_390_DATA + DDRSS3_CTL_391_DATA + DDRSS3_CTL_392_DATA + DDRSS3_CTL_393_DATA + DDRSS3_CTL_394_DATA + DDRSS3_CTL_395_DATA + DDRSS3_CTL_396_DATA + DDRSS3_CTL_397_DATA + DDRSS3_CTL_398_DATA + DDRSS3_CTL_399_DATA + DDRSS3_CTL_400_DATA + DDRSS3_CTL_401_DATA + DDRSS3_CTL_402_DATA + DDRSS3_CTL_403_DATA + DDRSS3_CTL_404_DATA + DDRSS3_CTL_405_DATA + DDRSS3_CTL_406_DATA + DDRSS3_CTL_407_DATA + DDRSS3_CTL_408_DATA + DDRSS3_CTL_409_DATA + DDRSS3_CTL_410_DATA + DDRSS3_CTL_411_DATA + DDRSS3_CTL_412_DATA + DDRSS3_CTL_413_DATA + DDRSS3_CTL_414_DATA + DDRSS3_CTL_415_DATA + DDRSS3_CTL_416_DATA + DDRSS3_CTL_417_DATA + DDRSS3_CTL_418_DATA + DDRSS3_CTL_419_DATA + DDRSS3_CTL_420_DATA + DDRSS3_CTL_421_DATA + DDRSS3_CTL_422_DATA + DDRSS3_CTL_423_DATA + DDRSS3_CTL_424_DATA + DDRSS3_CTL_425_DATA + DDRSS3_CTL_426_DATA + DDRSS3_CTL_427_DATA + DDRSS3_CTL_428_DATA + DDRSS3_CTL_429_DATA + DDRSS3_CTL_430_DATA + DDRSS3_CTL_431_DATA + DDRSS3_CTL_432_DATA + DDRSS3_CTL_433_DATA + DDRSS3_CTL_434_DATA + DDRSS3_CTL_435_DATA + DDRSS3_CTL_436_DATA + DDRSS3_CTL_437_DATA + DDRSS3_CTL_438_DATA + DDRSS3_CTL_439_DATA + DDRSS3_CTL_440_DATA + DDRSS3_CTL_441_DATA + DDRSS3_CTL_442_DATA + DDRSS3_CTL_443_DATA + DDRSS3_CTL_444_DATA + DDRSS3_CTL_445_DATA + DDRSS3_CTL_446_DATA + DDRSS3_CTL_447_DATA + DDRSS3_CTL_448_DATA + DDRSS3_CTL_449_DATA + DDRSS3_CTL_450_DATA + DDRSS3_CTL_451_DATA + DDRSS3_CTL_452_DATA + DDRSS3_CTL_453_DATA + DDRSS3_CTL_454_DATA + DDRSS3_CTL_455_DATA + DDRSS3_CTL_456_DATA + DDRSS3_CTL_457_DATA + DDRSS3_CTL_458_DATA + >; - ti,pi-data = < - DDRSS3_PI_00_DATA - DDRSS3_PI_01_DATA - DDRSS3_PI_02_DATA - DDRSS3_PI_03_DATA - DDRSS3_PI_04_DATA - DDRSS3_PI_05_DATA - DDRSS3_PI_06_DATA - DDRSS3_PI_07_DATA - DDRSS3_PI_08_DATA - DDRSS3_PI_09_DATA - DDRSS3_PI_10_DATA - DDRSS3_PI_11_DATA - DDRSS3_PI_12_DATA - DDRSS3_PI_13_DATA - DDRSS3_PI_14_DATA - DDRSS3_PI_15_DATA - DDRSS3_PI_16_DATA - DDRSS3_PI_17_DATA - DDRSS3_PI_18_DATA - DDRSS3_PI_19_DATA - DDRSS3_PI_20_DATA - DDRSS3_PI_21_DATA - DDRSS3_PI_22_DATA - DDRSS3_PI_23_DATA - DDRSS3_PI_24_DATA - DDRSS3_PI_25_DATA - DDRSS3_PI_26_DATA - DDRSS3_PI_27_DATA - DDRSS3_PI_28_DATA - DDRSS3_PI_29_DATA - DDRSS3_PI_30_DATA - DDRSS3_PI_31_DATA - DDRSS3_PI_32_DATA - DDRSS3_PI_33_DATA - DDRSS3_PI_34_DATA - DDRSS3_PI_35_DATA - DDRSS3_PI_36_DATA - DDRSS3_PI_37_DATA - DDRSS3_PI_38_DATA - DDRSS3_PI_39_DATA - DDRSS3_PI_40_DATA - DDRSS3_PI_41_DATA - DDRSS3_PI_42_DATA - DDRSS3_PI_43_DATA - DDRSS3_PI_44_DATA - DDRSS3_PI_45_DATA - DDRSS3_PI_46_DATA - DDRSS3_PI_47_DATA - DDRSS3_PI_48_DATA - DDRSS3_PI_49_DATA - DDRSS3_PI_50_DATA - DDRSS3_PI_51_DATA - DDRSS3_PI_52_DATA - DDRSS3_PI_53_DATA - DDRSS3_PI_54_DATA - DDRSS3_PI_55_DATA - DDRSS3_PI_56_DATA - DDRSS3_PI_57_DATA - DDRSS3_PI_58_DATA - DDRSS3_PI_59_DATA - DDRSS3_PI_60_DATA - DDRSS3_PI_61_DATA - DDRSS3_PI_62_DATA - DDRSS3_PI_63_DATA - DDRSS3_PI_64_DATA - DDRSS3_PI_65_DATA - DDRSS3_PI_66_DATA - DDRSS3_PI_67_DATA - DDRSS3_PI_68_DATA - DDRSS3_PI_69_DATA - DDRSS3_PI_70_DATA - DDRSS3_PI_71_DATA - DDRSS3_PI_72_DATA - DDRSS3_PI_73_DATA - DDRSS3_PI_74_DATA - DDRSS3_PI_75_DATA - DDRSS3_PI_76_DATA - DDRSS3_PI_77_DATA - DDRSS3_PI_78_DATA - DDRSS3_PI_79_DATA - DDRSS3_PI_80_DATA - DDRSS3_PI_81_DATA - DDRSS3_PI_82_DATA - DDRSS3_PI_83_DATA - DDRSS3_PI_84_DATA - DDRSS3_PI_85_DATA - DDRSS3_PI_86_DATA - DDRSS3_PI_87_DATA - DDRSS3_PI_88_DATA - DDRSS3_PI_89_DATA - DDRSS3_PI_90_DATA - DDRSS3_PI_91_DATA - DDRSS3_PI_92_DATA - DDRSS3_PI_93_DATA - DDRSS3_PI_94_DATA - DDRSS3_PI_95_DATA - DDRSS3_PI_96_DATA - DDRSS3_PI_97_DATA - DDRSS3_PI_98_DATA - DDRSS3_PI_99_DATA - DDRSS3_PI_100_DATA - DDRSS3_PI_101_DATA - DDRSS3_PI_102_DATA - DDRSS3_PI_103_DATA - DDRSS3_PI_104_DATA - DDRSS3_PI_105_DATA - DDRSS3_PI_106_DATA - DDRSS3_PI_107_DATA - DDRSS3_PI_108_DATA - DDRSS3_PI_109_DATA - DDRSS3_PI_110_DATA - DDRSS3_PI_111_DATA - DDRSS3_PI_112_DATA - DDRSS3_PI_113_DATA - DDRSS3_PI_114_DATA - DDRSS3_PI_115_DATA - DDRSS3_PI_116_DATA - DDRSS3_PI_117_DATA - DDRSS3_PI_118_DATA - DDRSS3_PI_119_DATA - DDRSS3_PI_120_DATA - DDRSS3_PI_121_DATA - DDRSS3_PI_122_DATA - DDRSS3_PI_123_DATA - DDRSS3_PI_124_DATA - DDRSS3_PI_125_DATA - DDRSS3_PI_126_DATA - DDRSS3_PI_127_DATA - DDRSS3_PI_128_DATA - DDRSS3_PI_129_DATA - DDRSS3_PI_130_DATA - DDRSS3_PI_131_DATA - DDRSS3_PI_132_DATA - DDRSS3_PI_133_DATA - DDRSS3_PI_134_DATA - DDRSS3_PI_135_DATA - DDRSS3_PI_136_DATA - DDRSS3_PI_137_DATA - DDRSS3_PI_138_DATA - DDRSS3_PI_139_DATA - DDRSS3_PI_140_DATA - DDRSS3_PI_141_DATA - DDRSS3_PI_142_DATA - DDRSS3_PI_143_DATA - DDRSS3_PI_144_DATA - DDRSS3_PI_145_DATA - DDRSS3_PI_146_DATA - DDRSS3_PI_147_DATA - DDRSS3_PI_148_DATA - DDRSS3_PI_149_DATA - DDRSS3_PI_150_DATA - DDRSS3_PI_151_DATA - DDRSS3_PI_152_DATA - DDRSS3_PI_153_DATA - DDRSS3_PI_154_DATA - DDRSS3_PI_155_DATA - DDRSS3_PI_156_DATA - DDRSS3_PI_157_DATA - DDRSS3_PI_158_DATA - DDRSS3_PI_159_DATA - DDRSS3_PI_160_DATA - DDRSS3_PI_161_DATA - DDRSS3_PI_162_DATA - DDRSS3_PI_163_DATA - DDRSS3_PI_164_DATA - DDRSS3_PI_165_DATA - DDRSS3_PI_166_DATA - DDRSS3_PI_167_DATA - DDRSS3_PI_168_DATA - DDRSS3_PI_169_DATA - DDRSS3_PI_170_DATA - DDRSS3_PI_171_DATA - DDRSS3_PI_172_DATA - DDRSS3_PI_173_DATA - DDRSS3_PI_174_DATA - DDRSS3_PI_175_DATA - DDRSS3_PI_176_DATA - DDRSS3_PI_177_DATA - DDRSS3_PI_178_DATA - DDRSS3_PI_179_DATA - DDRSS3_PI_180_DATA - DDRSS3_PI_181_DATA - DDRSS3_PI_182_DATA - DDRSS3_PI_183_DATA - DDRSS3_PI_184_DATA - DDRSS3_PI_185_DATA - DDRSS3_PI_186_DATA - DDRSS3_PI_187_DATA - DDRSS3_PI_188_DATA - DDRSS3_PI_189_DATA - DDRSS3_PI_190_DATA - DDRSS3_PI_191_DATA - DDRSS3_PI_192_DATA - DDRSS3_PI_193_DATA - DDRSS3_PI_194_DATA - DDRSS3_PI_195_DATA - DDRSS3_PI_196_DATA - DDRSS3_PI_197_DATA - DDRSS3_PI_198_DATA - DDRSS3_PI_199_DATA - DDRSS3_PI_200_DATA - DDRSS3_PI_201_DATA - DDRSS3_PI_202_DATA - DDRSS3_PI_203_DATA - DDRSS3_PI_204_DATA - DDRSS3_PI_205_DATA - DDRSS3_PI_206_DATA - DDRSS3_PI_207_DATA - DDRSS3_PI_208_DATA - DDRSS3_PI_209_DATA - DDRSS3_PI_210_DATA - DDRSS3_PI_211_DATA - DDRSS3_PI_212_DATA - DDRSS3_PI_213_DATA - DDRSS3_PI_214_DATA - DDRSS3_PI_215_DATA - DDRSS3_PI_216_DATA - DDRSS3_PI_217_DATA - DDRSS3_PI_218_DATA - DDRSS3_PI_219_DATA - DDRSS3_PI_220_DATA - DDRSS3_PI_221_DATA - DDRSS3_PI_222_DATA - DDRSS3_PI_223_DATA - DDRSS3_PI_224_DATA - DDRSS3_PI_225_DATA - DDRSS3_PI_226_DATA - DDRSS3_PI_227_DATA - DDRSS3_PI_228_DATA - DDRSS3_PI_229_DATA - DDRSS3_PI_230_DATA - DDRSS3_PI_231_DATA - DDRSS3_PI_232_DATA - DDRSS3_PI_233_DATA - DDRSS3_PI_234_DATA - DDRSS3_PI_235_DATA - DDRSS3_PI_236_DATA - DDRSS3_PI_237_DATA - DDRSS3_PI_238_DATA - DDRSS3_PI_239_DATA - DDRSS3_PI_240_DATA - DDRSS3_PI_241_DATA - DDRSS3_PI_242_DATA - DDRSS3_PI_243_DATA - DDRSS3_PI_244_DATA - DDRSS3_PI_245_DATA - DDRSS3_PI_246_DATA - DDRSS3_PI_247_DATA - DDRSS3_PI_248_DATA - DDRSS3_PI_249_DATA - DDRSS3_PI_250_DATA - DDRSS3_PI_251_DATA - DDRSS3_PI_252_DATA - DDRSS3_PI_253_DATA - DDRSS3_PI_254_DATA - DDRSS3_PI_255_DATA - DDRSS3_PI_256_DATA - DDRSS3_PI_257_DATA - DDRSS3_PI_258_DATA - DDRSS3_PI_259_DATA - DDRSS3_PI_260_DATA - DDRSS3_PI_261_DATA - DDRSS3_PI_262_DATA - DDRSS3_PI_263_DATA - DDRSS3_PI_264_DATA - DDRSS3_PI_265_DATA - DDRSS3_PI_266_DATA - DDRSS3_PI_267_DATA - DDRSS3_PI_268_DATA - DDRSS3_PI_269_DATA - DDRSS3_PI_270_DATA - DDRSS3_PI_271_DATA - DDRSS3_PI_272_DATA - DDRSS3_PI_273_DATA - DDRSS3_PI_274_DATA - DDRSS3_PI_275_DATA - DDRSS3_PI_276_DATA - DDRSS3_PI_277_DATA - DDRSS3_PI_278_DATA - DDRSS3_PI_279_DATA - DDRSS3_PI_280_DATA - DDRSS3_PI_281_DATA - DDRSS3_PI_282_DATA - DDRSS3_PI_283_DATA - DDRSS3_PI_284_DATA - DDRSS3_PI_285_DATA - DDRSS3_PI_286_DATA - DDRSS3_PI_287_DATA - DDRSS3_PI_288_DATA - DDRSS3_PI_289_DATA - DDRSS3_PI_290_DATA - DDRSS3_PI_291_DATA - DDRSS3_PI_292_DATA - DDRSS3_PI_293_DATA - DDRSS3_PI_294_DATA - DDRSS3_PI_295_DATA - DDRSS3_PI_296_DATA - DDRSS3_PI_297_DATA - DDRSS3_PI_298_DATA - DDRSS3_PI_299_DATA - >; + ti,pi-data = < + DDRSS3_PI_00_DATA + DDRSS3_PI_01_DATA + DDRSS3_PI_02_DATA + DDRSS3_PI_03_DATA + DDRSS3_PI_04_DATA + DDRSS3_PI_05_DATA + DDRSS3_PI_06_DATA + DDRSS3_PI_07_DATA + DDRSS3_PI_08_DATA + DDRSS3_PI_09_DATA + DDRSS3_PI_10_DATA + DDRSS3_PI_11_DATA + DDRSS3_PI_12_DATA + DDRSS3_PI_13_DATA + DDRSS3_PI_14_DATA + DDRSS3_PI_15_DATA + DDRSS3_PI_16_DATA + DDRSS3_PI_17_DATA + DDRSS3_PI_18_DATA + DDRSS3_PI_19_DATA + DDRSS3_PI_20_DATA + DDRSS3_PI_21_DATA + DDRSS3_PI_22_DATA + DDRSS3_PI_23_DATA + DDRSS3_PI_24_DATA + DDRSS3_PI_25_DATA + DDRSS3_PI_26_DATA + DDRSS3_PI_27_DATA + DDRSS3_PI_28_DATA + DDRSS3_PI_29_DATA + DDRSS3_PI_30_DATA + DDRSS3_PI_31_DATA + DDRSS3_PI_32_DATA + DDRSS3_PI_33_DATA + DDRSS3_PI_34_DATA + DDRSS3_PI_35_DATA + DDRSS3_PI_36_DATA + DDRSS3_PI_37_DATA + DDRSS3_PI_38_DATA + DDRSS3_PI_39_DATA + DDRSS3_PI_40_DATA + DDRSS3_PI_41_DATA + DDRSS3_PI_42_DATA + DDRSS3_PI_43_DATA + DDRSS3_PI_44_DATA + DDRSS3_PI_45_DATA + DDRSS3_PI_46_DATA + DDRSS3_PI_47_DATA + DDRSS3_PI_48_DATA + DDRSS3_PI_49_DATA + DDRSS3_PI_50_DATA + DDRSS3_PI_51_DATA + DDRSS3_PI_52_DATA + DDRSS3_PI_53_DATA + DDRSS3_PI_54_DATA + DDRSS3_PI_55_DATA + DDRSS3_PI_56_DATA + DDRSS3_PI_57_DATA + DDRSS3_PI_58_DATA + DDRSS3_PI_59_DATA + DDRSS3_PI_60_DATA + DDRSS3_PI_61_DATA + DDRSS3_PI_62_DATA + DDRSS3_PI_63_DATA + DDRSS3_PI_64_DATA + DDRSS3_PI_65_DATA + DDRSS3_PI_66_DATA + DDRSS3_PI_67_DATA + DDRSS3_PI_68_DATA + DDRSS3_PI_69_DATA + DDRSS3_PI_70_DATA + DDRSS3_PI_71_DATA + DDRSS3_PI_72_DATA + DDRSS3_PI_73_DATA + DDRSS3_PI_74_DATA + DDRSS3_PI_75_DATA + DDRSS3_PI_76_DATA + DDRSS3_PI_77_DATA + DDRSS3_PI_78_DATA + DDRSS3_PI_79_DATA + DDRSS3_PI_80_DATA + DDRSS3_PI_81_DATA + DDRSS3_PI_82_DATA + DDRSS3_PI_83_DATA + DDRSS3_PI_84_DATA + DDRSS3_PI_85_DATA + DDRSS3_PI_86_DATA + DDRSS3_PI_87_DATA + DDRSS3_PI_88_DATA + DDRSS3_PI_89_DATA + DDRSS3_PI_90_DATA + DDRSS3_PI_91_DATA + DDRSS3_PI_92_DATA + DDRSS3_PI_93_DATA + DDRSS3_PI_94_DATA + DDRSS3_PI_95_DATA + DDRSS3_PI_96_DATA + DDRSS3_PI_97_DATA + DDRSS3_PI_98_DATA + DDRSS3_PI_99_DATA + DDRSS3_PI_100_DATA + DDRSS3_PI_101_DATA + DDRSS3_PI_102_DATA + DDRSS3_PI_103_DATA + DDRSS3_PI_104_DATA + DDRSS3_PI_105_DATA + DDRSS3_PI_106_DATA + DDRSS3_PI_107_DATA + DDRSS3_PI_108_DATA + DDRSS3_PI_109_DATA + DDRSS3_PI_110_DATA + DDRSS3_PI_111_DATA + DDRSS3_PI_112_DATA + DDRSS3_PI_113_DATA + DDRSS3_PI_114_DATA + DDRSS3_PI_115_DATA + DDRSS3_PI_116_DATA + DDRSS3_PI_117_DATA + DDRSS3_PI_118_DATA + DDRSS3_PI_119_DATA + DDRSS3_PI_120_DATA + DDRSS3_PI_121_DATA + DDRSS3_PI_122_DATA + DDRSS3_PI_123_DATA + DDRSS3_PI_124_DATA + DDRSS3_PI_125_DATA + DDRSS3_PI_126_DATA + DDRSS3_PI_127_DATA + DDRSS3_PI_128_DATA + DDRSS3_PI_129_DATA + DDRSS3_PI_130_DATA + DDRSS3_PI_131_DATA + DDRSS3_PI_132_DATA + DDRSS3_PI_133_DATA + DDRSS3_PI_134_DATA + DDRSS3_PI_135_DATA + DDRSS3_PI_136_DATA + DDRSS3_PI_137_DATA + DDRSS3_PI_138_DATA + DDRSS3_PI_139_DATA + DDRSS3_PI_140_DATA + DDRSS3_PI_141_DATA + DDRSS3_PI_142_DATA + DDRSS3_PI_143_DATA + DDRSS3_PI_144_DATA + DDRSS3_PI_145_DATA + DDRSS3_PI_146_DATA + DDRSS3_PI_147_DATA + DDRSS3_PI_148_DATA + DDRSS3_PI_149_DATA + DDRSS3_PI_150_DATA + DDRSS3_PI_151_DATA + DDRSS3_PI_152_DATA + DDRSS3_PI_153_DATA + DDRSS3_PI_154_DATA + DDRSS3_PI_155_DATA + DDRSS3_PI_156_DATA + DDRSS3_PI_157_DATA + DDRSS3_PI_158_DATA + DDRSS3_PI_159_DATA + DDRSS3_PI_160_DATA + DDRSS3_PI_161_DATA + DDRSS3_PI_162_DATA + DDRSS3_PI_163_DATA + DDRSS3_PI_164_DATA + DDRSS3_PI_165_DATA + DDRSS3_PI_166_DATA + DDRSS3_PI_167_DATA + DDRSS3_PI_168_DATA + DDRSS3_PI_169_DATA + DDRSS3_PI_170_DATA + DDRSS3_PI_171_DATA + DDRSS3_PI_172_DATA + DDRSS3_PI_173_DATA + DDRSS3_PI_174_DATA + DDRSS3_PI_175_DATA + DDRSS3_PI_176_DATA + DDRSS3_PI_177_DATA + DDRSS3_PI_178_DATA + DDRSS3_PI_179_DATA + DDRSS3_PI_180_DATA + DDRSS3_PI_181_DATA + DDRSS3_PI_182_DATA + DDRSS3_PI_183_DATA + DDRSS3_PI_184_DATA + DDRSS3_PI_185_DATA + DDRSS3_PI_186_DATA + DDRSS3_PI_187_DATA + DDRSS3_PI_188_DATA + DDRSS3_PI_189_DATA + DDRSS3_PI_190_DATA + DDRSS3_PI_191_DATA + DDRSS3_PI_192_DATA + DDRSS3_PI_193_DATA + DDRSS3_PI_194_DATA + DDRSS3_PI_195_DATA + DDRSS3_PI_196_DATA + DDRSS3_PI_197_DATA + DDRSS3_PI_198_DATA + DDRSS3_PI_199_DATA + DDRSS3_PI_200_DATA + DDRSS3_PI_201_DATA + DDRSS3_PI_202_DATA + DDRSS3_PI_203_DATA + DDRSS3_PI_204_DATA + DDRSS3_PI_205_DATA + DDRSS3_PI_206_DATA + DDRSS3_PI_207_DATA + DDRSS3_PI_208_DATA + DDRSS3_PI_209_DATA + DDRSS3_PI_210_DATA + DDRSS3_PI_211_DATA + DDRSS3_PI_212_DATA + DDRSS3_PI_213_DATA + DDRSS3_PI_214_DATA + DDRSS3_PI_215_DATA + DDRSS3_PI_216_DATA + DDRSS3_PI_217_DATA + DDRSS3_PI_218_DATA + DDRSS3_PI_219_DATA + DDRSS3_PI_220_DATA + DDRSS3_PI_221_DATA + DDRSS3_PI_222_DATA + DDRSS3_PI_223_DATA + DDRSS3_PI_224_DATA + DDRSS3_PI_225_DATA + DDRSS3_PI_226_DATA + DDRSS3_PI_227_DATA + DDRSS3_PI_228_DATA + DDRSS3_PI_229_DATA + DDRSS3_PI_230_DATA + DDRSS3_PI_231_DATA + DDRSS3_PI_232_DATA + DDRSS3_PI_233_DATA + DDRSS3_PI_234_DATA + DDRSS3_PI_235_DATA + DDRSS3_PI_236_DATA + DDRSS3_PI_237_DATA + DDRSS3_PI_238_DATA + DDRSS3_PI_239_DATA + DDRSS3_PI_240_DATA + DDRSS3_PI_241_DATA + DDRSS3_PI_242_DATA + DDRSS3_PI_243_DATA + DDRSS3_PI_244_DATA + DDRSS3_PI_245_DATA + DDRSS3_PI_246_DATA + DDRSS3_PI_247_DATA + DDRSS3_PI_248_DATA + DDRSS3_PI_249_DATA + DDRSS3_PI_250_DATA + DDRSS3_PI_251_DATA + DDRSS3_PI_252_DATA + DDRSS3_PI_253_DATA + DDRSS3_PI_254_DATA + DDRSS3_PI_255_DATA + DDRSS3_PI_256_DATA + DDRSS3_PI_257_DATA + DDRSS3_PI_258_DATA + DDRSS3_PI_259_DATA + DDRSS3_PI_260_DATA + DDRSS3_PI_261_DATA + DDRSS3_PI_262_DATA + DDRSS3_PI_263_DATA + DDRSS3_PI_264_DATA + DDRSS3_PI_265_DATA + DDRSS3_PI_266_DATA + DDRSS3_PI_267_DATA + DDRSS3_PI_268_DATA + DDRSS3_PI_269_DATA + DDRSS3_PI_270_DATA + DDRSS3_PI_271_DATA + DDRSS3_PI_272_DATA + DDRSS3_PI_273_DATA + DDRSS3_PI_274_DATA + DDRSS3_PI_275_DATA + DDRSS3_PI_276_DATA + DDRSS3_PI_277_DATA + DDRSS3_PI_278_DATA + DDRSS3_PI_279_DATA + DDRSS3_PI_280_DATA + DDRSS3_PI_281_DATA + DDRSS3_PI_282_DATA + DDRSS3_PI_283_DATA + DDRSS3_PI_284_DATA + DDRSS3_PI_285_DATA + DDRSS3_PI_286_DATA + DDRSS3_PI_287_DATA + DDRSS3_PI_288_DATA + DDRSS3_PI_289_DATA + DDRSS3_PI_290_DATA + DDRSS3_PI_291_DATA + DDRSS3_PI_292_DATA + DDRSS3_PI_293_DATA + DDRSS3_PI_294_DATA + DDRSS3_PI_295_DATA + DDRSS3_PI_296_DATA + DDRSS3_PI_297_DATA + DDRSS3_PI_298_DATA + DDRSS3_PI_299_DATA + >; - ti,phy-data = < - DDRSS3_PHY_00_DATA - DDRSS3_PHY_01_DATA - DDRSS3_PHY_02_DATA - DDRSS3_PHY_03_DATA - DDRSS3_PHY_04_DATA - DDRSS3_PHY_05_DATA - DDRSS3_PHY_06_DATA - DDRSS3_PHY_07_DATA - DDRSS3_PHY_08_DATA - DDRSS3_PHY_09_DATA - DDRSS3_PHY_10_DATA - DDRSS3_PHY_11_DATA - DDRSS3_PHY_12_DATA - DDRSS3_PHY_13_DATA - DDRSS3_PHY_14_DATA - DDRSS3_PHY_15_DATA - DDRSS3_PHY_16_DATA - DDRSS3_PHY_17_DATA - DDRSS3_PHY_18_DATA - DDRSS3_PHY_19_DATA - DDRSS3_PHY_20_DATA - DDRSS3_PHY_21_DATA - DDRSS3_PHY_22_DATA - DDRSS3_PHY_23_DATA - DDRSS3_PHY_24_DATA - DDRSS3_PHY_25_DATA - DDRSS3_PHY_26_DATA - DDRSS3_PHY_27_DATA - DDRSS3_PHY_28_DATA - DDRSS3_PHY_29_DATA - DDRSS3_PHY_30_DATA - DDRSS3_PHY_31_DATA - DDRSS3_PHY_32_DATA - DDRSS3_PHY_33_DATA - DDRSS3_PHY_34_DATA - DDRSS3_PHY_35_DATA - DDRSS3_PHY_36_DATA - DDRSS3_PHY_37_DATA - DDRSS3_PHY_38_DATA - DDRSS3_PHY_39_DATA - DDRSS3_PHY_40_DATA - DDRSS3_PHY_41_DATA - DDRSS3_PHY_42_DATA - DDRSS3_PHY_43_DATA - DDRSS3_PHY_44_DATA - DDRSS3_PHY_45_DATA - DDRSS3_PHY_46_DATA - DDRSS3_PHY_47_DATA - DDRSS3_PHY_48_DATA - DDRSS3_PHY_49_DATA - DDRSS3_PHY_50_DATA - DDRSS3_PHY_51_DATA - DDRSS3_PHY_52_DATA - DDRSS3_PHY_53_DATA - DDRSS3_PHY_54_DATA - DDRSS3_PHY_55_DATA - DDRSS3_PHY_56_DATA - DDRSS3_PHY_57_DATA - DDRSS3_PHY_58_DATA - DDRSS3_PHY_59_DATA - DDRSS3_PHY_60_DATA - DDRSS3_PHY_61_DATA - DDRSS3_PHY_62_DATA - DDRSS3_PHY_63_DATA - DDRSS3_PHY_64_DATA - DDRSS3_PHY_65_DATA - DDRSS3_PHY_66_DATA - DDRSS3_PHY_67_DATA - DDRSS3_PHY_68_DATA - DDRSS3_PHY_69_DATA - DDRSS3_PHY_70_DATA - DDRSS3_PHY_71_DATA - DDRSS3_PHY_72_DATA - DDRSS3_PHY_73_DATA - DDRSS3_PHY_74_DATA - DDRSS3_PHY_75_DATA - DDRSS3_PHY_76_DATA - DDRSS3_PHY_77_DATA - DDRSS3_PHY_78_DATA - DDRSS3_PHY_79_DATA - DDRSS3_PHY_80_DATA - DDRSS3_PHY_81_DATA - DDRSS3_PHY_82_DATA - DDRSS3_PHY_83_DATA - DDRSS3_PHY_84_DATA - DDRSS3_PHY_85_DATA - DDRSS3_PHY_86_DATA - DDRSS3_PHY_87_DATA - DDRSS3_PHY_88_DATA - DDRSS3_PHY_89_DATA - DDRSS3_PHY_90_DATA - DDRSS3_PHY_91_DATA - DDRSS3_PHY_92_DATA - DDRSS3_PHY_93_DATA - DDRSS3_PHY_94_DATA - DDRSS3_PHY_95_DATA - DDRSS3_PHY_96_DATA - DDRSS3_PHY_97_DATA - DDRSS3_PHY_98_DATA - DDRSS3_PHY_99_DATA - DDRSS3_PHY_100_DATA - DDRSS3_PHY_101_DATA - DDRSS3_PHY_102_DATA - DDRSS3_PHY_103_DATA - DDRSS3_PHY_104_DATA - DDRSS3_PHY_105_DATA - DDRSS3_PHY_106_DATA - DDRSS3_PHY_107_DATA - DDRSS3_PHY_108_DATA - DDRSS3_PHY_109_DATA - DDRSS3_PHY_110_DATA - DDRSS3_PHY_111_DATA - DDRSS3_PHY_112_DATA - DDRSS3_PHY_113_DATA - DDRSS3_PHY_114_DATA - DDRSS3_PHY_115_DATA - DDRSS3_PHY_116_DATA - DDRSS3_PHY_117_DATA - DDRSS3_PHY_118_DATA - DDRSS3_PHY_119_DATA - DDRSS3_PHY_120_DATA - DDRSS3_PHY_121_DATA - DDRSS3_PHY_122_DATA - DDRSS3_PHY_123_DATA - DDRSS3_PHY_124_DATA - DDRSS3_PHY_125_DATA - DDRSS3_PHY_126_DATA - DDRSS3_PHY_127_DATA - DDRSS3_PHY_128_DATA - DDRSS3_PHY_129_DATA - DDRSS3_PHY_130_DATA - DDRSS3_PHY_131_DATA - DDRSS3_PHY_132_DATA - DDRSS3_PHY_133_DATA - DDRSS3_PHY_134_DATA - DDRSS3_PHY_135_DATA - DDRSS3_PHY_136_DATA - DDRSS3_PHY_137_DATA - DDRSS3_PHY_138_DATA - DDRSS3_PHY_139_DATA - DDRSS3_PHY_140_DATA - DDRSS3_PHY_141_DATA - DDRSS3_PHY_142_DATA - DDRSS3_PHY_143_DATA - DDRSS3_PHY_144_DATA - DDRSS3_PHY_145_DATA - DDRSS3_PHY_146_DATA - DDRSS3_PHY_147_DATA - DDRSS3_PHY_148_DATA - DDRSS3_PHY_149_DATA - DDRSS3_PHY_150_DATA - DDRSS3_PHY_151_DATA - DDRSS3_PHY_152_DATA - DDRSS3_PHY_153_DATA - DDRSS3_PHY_154_DATA - DDRSS3_PHY_155_DATA - DDRSS3_PHY_156_DATA - DDRSS3_PHY_157_DATA - DDRSS3_PHY_158_DATA - DDRSS3_PHY_159_DATA - DDRSS3_PHY_160_DATA - DDRSS3_PHY_161_DATA - DDRSS3_PHY_162_DATA - DDRSS3_PHY_163_DATA - DDRSS3_PHY_164_DATA - DDRSS3_PHY_165_DATA - DDRSS3_PHY_166_DATA - DDRSS3_PHY_167_DATA - DDRSS3_PHY_168_DATA - DDRSS3_PHY_169_DATA - DDRSS3_PHY_170_DATA - DDRSS3_PHY_171_DATA - DDRSS3_PHY_172_DATA - DDRSS3_PHY_173_DATA - DDRSS3_PHY_174_DATA - DDRSS3_PHY_175_DATA - DDRSS3_PHY_176_DATA - DDRSS3_PHY_177_DATA - DDRSS3_PHY_178_DATA - DDRSS3_PHY_179_DATA - DDRSS3_PHY_180_DATA - DDRSS3_PHY_181_DATA - DDRSS3_PHY_182_DATA - DDRSS3_PHY_183_DATA - DDRSS3_PHY_184_DATA - DDRSS3_PHY_185_DATA - DDRSS3_PHY_186_DATA - DDRSS3_PHY_187_DATA - DDRSS3_PHY_188_DATA - DDRSS3_PHY_189_DATA - DDRSS3_PHY_190_DATA - DDRSS3_PHY_191_DATA - DDRSS3_PHY_192_DATA - DDRSS3_PHY_193_DATA - DDRSS3_PHY_194_DATA - DDRSS3_PHY_195_DATA - DDRSS3_PHY_196_DATA - DDRSS3_PHY_197_DATA - DDRSS3_PHY_198_DATA - DDRSS3_PHY_199_DATA - DDRSS3_PHY_200_DATA - DDRSS3_PHY_201_DATA - DDRSS3_PHY_202_DATA - DDRSS3_PHY_203_DATA - DDRSS3_PHY_204_DATA - DDRSS3_PHY_205_DATA - DDRSS3_PHY_206_DATA - DDRSS3_PHY_207_DATA - DDRSS3_PHY_208_DATA - DDRSS3_PHY_209_DATA - DDRSS3_PHY_210_DATA - DDRSS3_PHY_211_DATA - DDRSS3_PHY_212_DATA - DDRSS3_PHY_213_DATA - DDRSS3_PHY_214_DATA - DDRSS3_PHY_215_DATA - DDRSS3_PHY_216_DATA - DDRSS3_PHY_217_DATA - DDRSS3_PHY_218_DATA - DDRSS3_PHY_219_DATA - DDRSS3_PHY_220_DATA - DDRSS3_PHY_221_DATA - DDRSS3_PHY_222_DATA - DDRSS3_PHY_223_DATA - DDRSS3_PHY_224_DATA - DDRSS3_PHY_225_DATA - DDRSS3_PHY_226_DATA - DDRSS3_PHY_227_DATA - DDRSS3_PHY_228_DATA - DDRSS3_PHY_229_DATA - DDRSS3_PHY_230_DATA - DDRSS3_PHY_231_DATA - DDRSS3_PHY_232_DATA - DDRSS3_PHY_233_DATA - DDRSS3_PHY_234_DATA - DDRSS3_PHY_235_DATA - DDRSS3_PHY_236_DATA - DDRSS3_PHY_237_DATA - DDRSS3_PHY_238_DATA - DDRSS3_PHY_239_DATA - DDRSS3_PHY_240_DATA - DDRSS3_PHY_241_DATA - DDRSS3_PHY_242_DATA - DDRSS3_PHY_243_DATA - DDRSS3_PHY_244_DATA - DDRSS3_PHY_245_DATA - DDRSS3_PHY_246_DATA - DDRSS3_PHY_247_DATA - DDRSS3_PHY_248_DATA - DDRSS3_PHY_249_DATA - DDRSS3_PHY_250_DATA - DDRSS3_PHY_251_DATA - DDRSS3_PHY_252_DATA - DDRSS3_PHY_253_DATA - DDRSS3_PHY_254_DATA - DDRSS3_PHY_255_DATA - DDRSS3_PHY_256_DATA - DDRSS3_PHY_257_DATA - DDRSS3_PHY_258_DATA - DDRSS3_PHY_259_DATA - DDRSS3_PHY_260_DATA - DDRSS3_PHY_261_DATA - DDRSS3_PHY_262_DATA - DDRSS3_PHY_263_DATA - DDRSS3_PHY_264_DATA - DDRSS3_PHY_265_DATA - DDRSS3_PHY_266_DATA - DDRSS3_PHY_267_DATA - DDRSS3_PHY_268_DATA - DDRSS3_PHY_269_DATA - DDRSS3_PHY_270_DATA - DDRSS3_PHY_271_DATA - DDRSS3_PHY_272_DATA - DDRSS3_PHY_273_DATA - DDRSS3_PHY_274_DATA - DDRSS3_PHY_275_DATA - DDRSS3_PHY_276_DATA - DDRSS3_PHY_277_DATA - DDRSS3_PHY_278_DATA - DDRSS3_PHY_279_DATA - DDRSS3_PHY_280_DATA - DDRSS3_PHY_281_DATA - DDRSS3_PHY_282_DATA - DDRSS3_PHY_283_DATA - DDRSS3_PHY_284_DATA - DDRSS3_PHY_285_DATA - DDRSS3_PHY_286_DATA - DDRSS3_PHY_287_DATA - DDRSS3_PHY_288_DATA - DDRSS3_PHY_289_DATA - DDRSS3_PHY_290_DATA - DDRSS3_PHY_291_DATA - DDRSS3_PHY_292_DATA - DDRSS3_PHY_293_DATA - DDRSS3_PHY_294_DATA - DDRSS3_PHY_295_DATA - DDRSS3_PHY_296_DATA - DDRSS3_PHY_297_DATA - DDRSS3_PHY_298_DATA - DDRSS3_PHY_299_DATA - DDRSS3_PHY_300_DATA - DDRSS3_PHY_301_DATA - DDRSS3_PHY_302_DATA - DDRSS3_PHY_303_DATA - DDRSS3_PHY_304_DATA - DDRSS3_PHY_305_DATA - DDRSS3_PHY_306_DATA - DDRSS3_PHY_307_DATA - DDRSS3_PHY_308_DATA - DDRSS3_PHY_309_DATA - DDRSS3_PHY_310_DATA - DDRSS3_PHY_311_DATA - DDRSS3_PHY_312_DATA - DDRSS3_PHY_313_DATA - DDRSS3_PHY_314_DATA - DDRSS3_PHY_315_DATA - DDRSS3_PHY_316_DATA - DDRSS3_PHY_317_DATA - DDRSS3_PHY_318_DATA - DDRSS3_PHY_319_DATA - DDRSS3_PHY_320_DATA - DDRSS3_PHY_321_DATA - DDRSS3_PHY_322_DATA - DDRSS3_PHY_323_DATA - DDRSS3_PHY_324_DATA - DDRSS3_PHY_325_DATA - DDRSS3_PHY_326_DATA - DDRSS3_PHY_327_DATA - DDRSS3_PHY_328_DATA - DDRSS3_PHY_329_DATA - DDRSS3_PHY_330_DATA - DDRSS3_PHY_331_DATA - DDRSS3_PHY_332_DATA - DDRSS3_PHY_333_DATA - DDRSS3_PHY_334_DATA - DDRSS3_PHY_335_DATA - DDRSS3_PHY_336_DATA - DDRSS3_PHY_337_DATA - DDRSS3_PHY_338_DATA - DDRSS3_PHY_339_DATA - DDRSS3_PHY_340_DATA - DDRSS3_PHY_341_DATA - DDRSS3_PHY_342_DATA - DDRSS3_PHY_343_DATA - DDRSS3_PHY_344_DATA - DDRSS3_PHY_345_DATA - DDRSS3_PHY_346_DATA - DDRSS3_PHY_347_DATA - DDRSS3_PHY_348_DATA - DDRSS3_PHY_349_DATA - DDRSS3_PHY_350_DATA - DDRSS3_PHY_351_DATA - DDRSS3_PHY_352_DATA - DDRSS3_PHY_353_DATA - DDRSS3_PHY_354_DATA - DDRSS3_PHY_355_DATA - DDRSS3_PHY_356_DATA - DDRSS3_PHY_357_DATA - DDRSS3_PHY_358_DATA - DDRSS3_PHY_359_DATA - DDRSS3_PHY_360_DATA - DDRSS3_PHY_361_DATA - DDRSS3_PHY_362_DATA - DDRSS3_PHY_363_DATA - DDRSS3_PHY_364_DATA - DDRSS3_PHY_365_DATA - DDRSS3_PHY_366_DATA - DDRSS3_PHY_367_DATA - DDRSS3_PHY_368_DATA - DDRSS3_PHY_369_DATA - DDRSS3_PHY_370_DATA - DDRSS3_PHY_371_DATA - DDRSS3_PHY_372_DATA - DDRSS3_PHY_373_DATA - DDRSS3_PHY_374_DATA - DDRSS3_PHY_375_DATA - DDRSS3_PHY_376_DATA - DDRSS3_PHY_377_DATA - DDRSS3_PHY_378_DATA - DDRSS3_PHY_379_DATA - DDRSS3_PHY_380_DATA - DDRSS3_PHY_381_DATA - DDRSS3_PHY_382_DATA - DDRSS3_PHY_383_DATA - DDRSS3_PHY_384_DATA - DDRSS3_PHY_385_DATA - DDRSS3_PHY_386_DATA - DDRSS3_PHY_387_DATA - DDRSS3_PHY_388_DATA - DDRSS3_PHY_389_DATA - DDRSS3_PHY_390_DATA - DDRSS3_PHY_391_DATA - DDRSS3_PHY_392_DATA - DDRSS3_PHY_393_DATA - DDRSS3_PHY_394_DATA - DDRSS3_PHY_395_DATA - DDRSS3_PHY_396_DATA - DDRSS3_PHY_397_DATA - DDRSS3_PHY_398_DATA - DDRSS3_PHY_399_DATA - DDRSS3_PHY_400_DATA - DDRSS3_PHY_401_DATA - DDRSS3_PHY_402_DATA - DDRSS3_PHY_403_DATA - DDRSS3_PHY_404_DATA - DDRSS3_PHY_405_DATA - DDRSS3_PHY_406_DATA - DDRSS3_PHY_407_DATA - DDRSS3_PHY_408_DATA - DDRSS3_PHY_409_DATA - DDRSS3_PHY_410_DATA - DDRSS3_PHY_411_DATA - DDRSS3_PHY_412_DATA - DDRSS3_PHY_413_DATA - DDRSS3_PHY_414_DATA - DDRSS3_PHY_415_DATA - DDRSS3_PHY_416_DATA - DDRSS3_PHY_417_DATA - DDRSS3_PHY_418_DATA - DDRSS3_PHY_419_DATA - DDRSS3_PHY_420_DATA - DDRSS3_PHY_421_DATA - DDRSS3_PHY_422_DATA - DDRSS3_PHY_423_DATA - DDRSS3_PHY_424_DATA - DDRSS3_PHY_425_DATA - DDRSS3_PHY_426_DATA - DDRSS3_PHY_427_DATA - DDRSS3_PHY_428_DATA - DDRSS3_PHY_429_DATA - DDRSS3_PHY_430_DATA - DDRSS3_PHY_431_DATA - DDRSS3_PHY_432_DATA - DDRSS3_PHY_433_DATA - DDRSS3_PHY_434_DATA - DDRSS3_PHY_435_DATA - DDRSS3_PHY_436_DATA - DDRSS3_PHY_437_DATA - DDRSS3_PHY_438_DATA - DDRSS3_PHY_439_DATA - DDRSS3_PHY_440_DATA - DDRSS3_PHY_441_DATA - DDRSS3_PHY_442_DATA - DDRSS3_PHY_443_DATA - DDRSS3_PHY_444_DATA - DDRSS3_PHY_445_DATA - DDRSS3_PHY_446_DATA - DDRSS3_PHY_447_DATA - DDRSS3_PHY_448_DATA - DDRSS3_PHY_449_DATA - DDRSS3_PHY_450_DATA - DDRSS3_PHY_451_DATA - DDRSS3_PHY_452_DATA - DDRSS3_PHY_453_DATA - DDRSS3_PHY_454_DATA - DDRSS3_PHY_455_DATA - DDRSS3_PHY_456_DATA - DDRSS3_PHY_457_DATA - DDRSS3_PHY_458_DATA - DDRSS3_PHY_459_DATA - DDRSS3_PHY_460_DATA - DDRSS3_PHY_461_DATA - DDRSS3_PHY_462_DATA - DDRSS3_PHY_463_DATA - DDRSS3_PHY_464_DATA - DDRSS3_PHY_465_DATA - DDRSS3_PHY_466_DATA - DDRSS3_PHY_467_DATA - DDRSS3_PHY_468_DATA - DDRSS3_PHY_469_DATA - DDRSS3_PHY_470_DATA - DDRSS3_PHY_471_DATA - DDRSS3_PHY_472_DATA - DDRSS3_PHY_473_DATA - DDRSS3_PHY_474_DATA - DDRSS3_PHY_475_DATA - DDRSS3_PHY_476_DATA - DDRSS3_PHY_477_DATA - DDRSS3_PHY_478_DATA - DDRSS3_PHY_479_DATA - DDRSS3_PHY_480_DATA - DDRSS3_PHY_481_DATA - DDRSS3_PHY_482_DATA - DDRSS3_PHY_483_DATA - DDRSS3_PHY_484_DATA - DDRSS3_PHY_485_DATA - DDRSS3_PHY_486_DATA - DDRSS3_PHY_487_DATA - DDRSS3_PHY_488_DATA - DDRSS3_PHY_489_DATA - DDRSS3_PHY_490_DATA - DDRSS3_PHY_491_DATA - DDRSS3_PHY_492_DATA - DDRSS3_PHY_493_DATA - DDRSS3_PHY_494_DATA - DDRSS3_PHY_495_DATA - DDRSS3_PHY_496_DATA - DDRSS3_PHY_497_DATA - DDRSS3_PHY_498_DATA - DDRSS3_PHY_499_DATA - DDRSS3_PHY_500_DATA - DDRSS3_PHY_501_DATA - DDRSS3_PHY_502_DATA - DDRSS3_PHY_503_DATA - DDRSS3_PHY_504_DATA - DDRSS3_PHY_505_DATA - DDRSS3_PHY_506_DATA - DDRSS3_PHY_507_DATA - DDRSS3_PHY_508_DATA - DDRSS3_PHY_509_DATA - DDRSS3_PHY_510_DATA - DDRSS3_PHY_511_DATA - DDRSS3_PHY_512_DATA - DDRSS3_PHY_513_DATA - DDRSS3_PHY_514_DATA - DDRSS3_PHY_515_DATA - DDRSS3_PHY_516_DATA - DDRSS3_PHY_517_DATA - DDRSS3_PHY_518_DATA - DDRSS3_PHY_519_DATA - DDRSS3_PHY_520_DATA - DDRSS3_PHY_521_DATA - DDRSS3_PHY_522_DATA - DDRSS3_PHY_523_DATA - DDRSS3_PHY_524_DATA - DDRSS3_PHY_525_DATA - DDRSS3_PHY_526_DATA - DDRSS3_PHY_527_DATA - DDRSS3_PHY_528_DATA - DDRSS3_PHY_529_DATA - DDRSS3_PHY_530_DATA - DDRSS3_PHY_531_DATA - DDRSS3_PHY_532_DATA - DDRSS3_PHY_533_DATA - DDRSS3_PHY_534_DATA - DDRSS3_PHY_535_DATA - DDRSS3_PHY_536_DATA - DDRSS3_PHY_537_DATA - DDRSS3_PHY_538_DATA - DDRSS3_PHY_539_DATA - DDRSS3_PHY_540_DATA - DDRSS3_PHY_541_DATA - DDRSS3_PHY_542_DATA - DDRSS3_PHY_543_DATA - DDRSS3_PHY_544_DATA - DDRSS3_PHY_545_DATA - DDRSS3_PHY_546_DATA - DDRSS3_PHY_547_DATA - DDRSS3_PHY_548_DATA - DDRSS3_PHY_549_DATA - DDRSS3_PHY_550_DATA - DDRSS3_PHY_551_DATA - DDRSS3_PHY_552_DATA - DDRSS3_PHY_553_DATA - DDRSS3_PHY_554_DATA - DDRSS3_PHY_555_DATA - DDRSS3_PHY_556_DATA - DDRSS3_PHY_557_DATA - DDRSS3_PHY_558_DATA - DDRSS3_PHY_559_DATA - DDRSS3_PHY_560_DATA - DDRSS3_PHY_561_DATA - DDRSS3_PHY_562_DATA - DDRSS3_PHY_563_DATA - DDRSS3_PHY_564_DATA - DDRSS3_PHY_565_DATA - DDRSS3_PHY_566_DATA - DDRSS3_PHY_567_DATA - DDRSS3_PHY_568_DATA - DDRSS3_PHY_569_DATA - DDRSS3_PHY_570_DATA - DDRSS3_PHY_571_DATA - DDRSS3_PHY_572_DATA - DDRSS3_PHY_573_DATA - DDRSS3_PHY_574_DATA - DDRSS3_PHY_575_DATA - DDRSS3_PHY_576_DATA - DDRSS3_PHY_577_DATA - DDRSS3_PHY_578_DATA - DDRSS3_PHY_579_DATA - DDRSS3_PHY_580_DATA - DDRSS3_PHY_581_DATA - DDRSS3_PHY_582_DATA - DDRSS3_PHY_583_DATA - DDRSS3_PHY_584_DATA - DDRSS3_PHY_585_DATA - DDRSS3_PHY_586_DATA - DDRSS3_PHY_587_DATA - DDRSS3_PHY_588_DATA - DDRSS3_PHY_589_DATA - DDRSS3_PHY_590_DATA - DDRSS3_PHY_591_DATA - DDRSS3_PHY_592_DATA - DDRSS3_PHY_593_DATA - DDRSS3_PHY_594_DATA - DDRSS3_PHY_595_DATA - DDRSS3_PHY_596_DATA - DDRSS3_PHY_597_DATA - DDRSS3_PHY_598_DATA - DDRSS3_PHY_599_DATA - DDRSS3_PHY_600_DATA - DDRSS3_PHY_601_DATA - DDRSS3_PHY_602_DATA - DDRSS3_PHY_603_DATA - DDRSS3_PHY_604_DATA - DDRSS3_PHY_605_DATA - DDRSS3_PHY_606_DATA - DDRSS3_PHY_607_DATA - DDRSS3_PHY_608_DATA - DDRSS3_PHY_609_DATA - DDRSS3_PHY_610_DATA - DDRSS3_PHY_611_DATA - DDRSS3_PHY_612_DATA - DDRSS3_PHY_613_DATA - DDRSS3_PHY_614_DATA - DDRSS3_PHY_615_DATA - DDRSS3_PHY_616_DATA - DDRSS3_PHY_617_DATA - DDRSS3_PHY_618_DATA - DDRSS3_PHY_619_DATA - DDRSS3_PHY_620_DATA - DDRSS3_PHY_621_DATA - DDRSS3_PHY_622_DATA - DDRSS3_PHY_623_DATA - DDRSS3_PHY_624_DATA - DDRSS3_PHY_625_DATA - DDRSS3_PHY_626_DATA - DDRSS3_PHY_627_DATA - DDRSS3_PHY_628_DATA - DDRSS3_PHY_629_DATA - DDRSS3_PHY_630_DATA - DDRSS3_PHY_631_DATA - DDRSS3_PHY_632_DATA - DDRSS3_PHY_633_DATA - DDRSS3_PHY_634_DATA - DDRSS3_PHY_635_DATA - DDRSS3_PHY_636_DATA - DDRSS3_PHY_637_DATA - DDRSS3_PHY_638_DATA - DDRSS3_PHY_639_DATA - DDRSS3_PHY_640_DATA - DDRSS3_PHY_641_DATA - DDRSS3_PHY_642_DATA - DDRSS3_PHY_643_DATA - DDRSS3_PHY_644_DATA - DDRSS3_PHY_645_DATA - DDRSS3_PHY_646_DATA - DDRSS3_PHY_647_DATA - DDRSS3_PHY_648_DATA - DDRSS3_PHY_649_DATA - DDRSS3_PHY_650_DATA - DDRSS3_PHY_651_DATA - DDRSS3_PHY_652_DATA - DDRSS3_PHY_653_DATA - DDRSS3_PHY_654_DATA - DDRSS3_PHY_655_DATA - DDRSS3_PHY_656_DATA - DDRSS3_PHY_657_DATA - DDRSS3_PHY_658_DATA - DDRSS3_PHY_659_DATA - DDRSS3_PHY_660_DATA - DDRSS3_PHY_661_DATA - DDRSS3_PHY_662_DATA - DDRSS3_PHY_663_DATA - DDRSS3_PHY_664_DATA - DDRSS3_PHY_665_DATA - DDRSS3_PHY_666_DATA - DDRSS3_PHY_667_DATA - DDRSS3_PHY_668_DATA - DDRSS3_PHY_669_DATA - DDRSS3_PHY_670_DATA - DDRSS3_PHY_671_DATA - DDRSS3_PHY_672_DATA - DDRSS3_PHY_673_DATA - DDRSS3_PHY_674_DATA - DDRSS3_PHY_675_DATA - DDRSS3_PHY_676_DATA - DDRSS3_PHY_677_DATA - DDRSS3_PHY_678_DATA - DDRSS3_PHY_679_DATA - DDRSS3_PHY_680_DATA - DDRSS3_PHY_681_DATA - DDRSS3_PHY_682_DATA - DDRSS3_PHY_683_DATA - DDRSS3_PHY_684_DATA - DDRSS3_PHY_685_DATA - DDRSS3_PHY_686_DATA - DDRSS3_PHY_687_DATA - DDRSS3_PHY_688_DATA - DDRSS3_PHY_689_DATA - DDRSS3_PHY_690_DATA - DDRSS3_PHY_691_DATA - DDRSS3_PHY_692_DATA - DDRSS3_PHY_693_DATA - DDRSS3_PHY_694_DATA - DDRSS3_PHY_695_DATA - DDRSS3_PHY_696_DATA - DDRSS3_PHY_697_DATA - DDRSS3_PHY_698_DATA - DDRSS3_PHY_699_DATA - DDRSS3_PHY_700_DATA - DDRSS3_PHY_701_DATA - DDRSS3_PHY_702_DATA - DDRSS3_PHY_703_DATA - DDRSS3_PHY_704_DATA - DDRSS3_PHY_705_DATA - DDRSS3_PHY_706_DATA - DDRSS3_PHY_707_DATA - DDRSS3_PHY_708_DATA - DDRSS3_PHY_709_DATA - DDRSS3_PHY_710_DATA - DDRSS3_PHY_711_DATA - DDRSS3_PHY_712_DATA - DDRSS3_PHY_713_DATA - DDRSS3_PHY_714_DATA - DDRSS3_PHY_715_DATA - DDRSS3_PHY_716_DATA - DDRSS3_PHY_717_DATA - DDRSS3_PHY_718_DATA - DDRSS3_PHY_719_DATA - DDRSS3_PHY_720_DATA - DDRSS3_PHY_721_DATA - DDRSS3_PHY_722_DATA - DDRSS3_PHY_723_DATA - DDRSS3_PHY_724_DATA - DDRSS3_PHY_725_DATA - DDRSS3_PHY_726_DATA - DDRSS3_PHY_727_DATA - DDRSS3_PHY_728_DATA - DDRSS3_PHY_729_DATA - DDRSS3_PHY_730_DATA - DDRSS3_PHY_731_DATA - DDRSS3_PHY_732_DATA - DDRSS3_PHY_733_DATA - DDRSS3_PHY_734_DATA - DDRSS3_PHY_735_DATA - DDRSS3_PHY_736_DATA - DDRSS3_PHY_737_DATA - DDRSS3_PHY_738_DATA - DDRSS3_PHY_739_DATA - DDRSS3_PHY_740_DATA - DDRSS3_PHY_741_DATA - DDRSS3_PHY_742_DATA - DDRSS3_PHY_743_DATA - DDRSS3_PHY_744_DATA - DDRSS3_PHY_745_DATA - DDRSS3_PHY_746_DATA - DDRSS3_PHY_747_DATA - DDRSS3_PHY_748_DATA - DDRSS3_PHY_749_DATA - DDRSS3_PHY_750_DATA - DDRSS3_PHY_751_DATA - DDRSS3_PHY_752_DATA - DDRSS3_PHY_753_DATA - DDRSS3_PHY_754_DATA - DDRSS3_PHY_755_DATA - DDRSS3_PHY_756_DATA - DDRSS3_PHY_757_DATA - DDRSS3_PHY_758_DATA - DDRSS3_PHY_759_DATA - DDRSS3_PHY_760_DATA - DDRSS3_PHY_761_DATA - DDRSS3_PHY_762_DATA - DDRSS3_PHY_763_DATA - DDRSS3_PHY_764_DATA - DDRSS3_PHY_765_DATA - DDRSS3_PHY_766_DATA - DDRSS3_PHY_767_DATA - DDRSS3_PHY_768_DATA - DDRSS3_PHY_769_DATA - DDRSS3_PHY_770_DATA - DDRSS3_PHY_771_DATA - DDRSS3_PHY_772_DATA - DDRSS3_PHY_773_DATA - DDRSS3_PHY_774_DATA - DDRSS3_PHY_775_DATA - DDRSS3_PHY_776_DATA - DDRSS3_PHY_777_DATA - DDRSS3_PHY_778_DATA - DDRSS3_PHY_779_DATA - DDRSS3_PHY_780_DATA - DDRSS3_PHY_781_DATA - DDRSS3_PHY_782_DATA - DDRSS3_PHY_783_DATA - DDRSS3_PHY_784_DATA - DDRSS3_PHY_785_DATA - DDRSS3_PHY_786_DATA - DDRSS3_PHY_787_DATA - DDRSS3_PHY_788_DATA - DDRSS3_PHY_789_DATA - DDRSS3_PHY_790_DATA - DDRSS3_PHY_791_DATA - DDRSS3_PHY_792_DATA - DDRSS3_PHY_793_DATA - DDRSS3_PHY_794_DATA - DDRSS3_PHY_795_DATA - DDRSS3_PHY_796_DATA - DDRSS3_PHY_797_DATA - DDRSS3_PHY_798_DATA - DDRSS3_PHY_799_DATA - DDRSS3_PHY_800_DATA - DDRSS3_PHY_801_DATA - DDRSS3_PHY_802_DATA - DDRSS3_PHY_803_DATA - DDRSS3_PHY_804_DATA - DDRSS3_PHY_805_DATA - DDRSS3_PHY_806_DATA - DDRSS3_PHY_807_DATA - DDRSS3_PHY_808_DATA - DDRSS3_PHY_809_DATA - DDRSS3_PHY_810_DATA - DDRSS3_PHY_811_DATA - DDRSS3_PHY_812_DATA - DDRSS3_PHY_813_DATA - DDRSS3_PHY_814_DATA - DDRSS3_PHY_815_DATA - DDRSS3_PHY_816_DATA - DDRSS3_PHY_817_DATA - DDRSS3_PHY_818_DATA - DDRSS3_PHY_819_DATA - DDRSS3_PHY_820_DATA - DDRSS3_PHY_821_DATA - DDRSS3_PHY_822_DATA - DDRSS3_PHY_823_DATA - DDRSS3_PHY_824_DATA - DDRSS3_PHY_825_DATA - DDRSS3_PHY_826_DATA - DDRSS3_PHY_827_DATA - DDRSS3_PHY_828_DATA - DDRSS3_PHY_829_DATA - DDRSS3_PHY_830_DATA - DDRSS3_PHY_831_DATA - DDRSS3_PHY_832_DATA - DDRSS3_PHY_833_DATA - DDRSS3_PHY_834_DATA - DDRSS3_PHY_835_DATA - DDRSS3_PHY_836_DATA - DDRSS3_PHY_837_DATA - DDRSS3_PHY_838_DATA - DDRSS3_PHY_839_DATA - DDRSS3_PHY_840_DATA - DDRSS3_PHY_841_DATA - DDRSS3_PHY_842_DATA - DDRSS3_PHY_843_DATA - DDRSS3_PHY_844_DATA - DDRSS3_PHY_845_DATA - DDRSS3_PHY_846_DATA - DDRSS3_PHY_847_DATA - DDRSS3_PHY_848_DATA - DDRSS3_PHY_849_DATA - DDRSS3_PHY_850_DATA - DDRSS3_PHY_851_DATA - DDRSS3_PHY_852_DATA - DDRSS3_PHY_853_DATA - DDRSS3_PHY_854_DATA - DDRSS3_PHY_855_DATA - DDRSS3_PHY_856_DATA - DDRSS3_PHY_857_DATA - DDRSS3_PHY_858_DATA - DDRSS3_PHY_859_DATA - DDRSS3_PHY_860_DATA - DDRSS3_PHY_861_DATA - DDRSS3_PHY_862_DATA - DDRSS3_PHY_863_DATA - DDRSS3_PHY_864_DATA - DDRSS3_PHY_865_DATA - DDRSS3_PHY_866_DATA - DDRSS3_PHY_867_DATA - DDRSS3_PHY_868_DATA - DDRSS3_PHY_869_DATA - DDRSS3_PHY_870_DATA - DDRSS3_PHY_871_DATA - DDRSS3_PHY_872_DATA - DDRSS3_PHY_873_DATA - DDRSS3_PHY_874_DATA - DDRSS3_PHY_875_DATA - DDRSS3_PHY_876_DATA - DDRSS3_PHY_877_DATA - DDRSS3_PHY_878_DATA - DDRSS3_PHY_879_DATA - DDRSS3_PHY_880_DATA - DDRSS3_PHY_881_DATA - DDRSS3_PHY_882_DATA - DDRSS3_PHY_883_DATA - DDRSS3_PHY_884_DATA - DDRSS3_PHY_885_DATA - DDRSS3_PHY_886_DATA - DDRSS3_PHY_887_DATA - DDRSS3_PHY_888_DATA - DDRSS3_PHY_889_DATA - DDRSS3_PHY_890_DATA - DDRSS3_PHY_891_DATA - DDRSS3_PHY_892_DATA - DDRSS3_PHY_893_DATA - DDRSS3_PHY_894_DATA - DDRSS3_PHY_895_DATA - DDRSS3_PHY_896_DATA - DDRSS3_PHY_897_DATA - DDRSS3_PHY_898_DATA - DDRSS3_PHY_899_DATA - DDRSS3_PHY_900_DATA - DDRSS3_PHY_901_DATA - DDRSS3_PHY_902_DATA - DDRSS3_PHY_903_DATA - DDRSS3_PHY_904_DATA - DDRSS3_PHY_905_DATA - DDRSS3_PHY_906_DATA - DDRSS3_PHY_907_DATA - DDRSS3_PHY_908_DATA - DDRSS3_PHY_909_DATA - DDRSS3_PHY_910_DATA - DDRSS3_PHY_911_DATA - DDRSS3_PHY_912_DATA - DDRSS3_PHY_913_DATA - DDRSS3_PHY_914_DATA - DDRSS3_PHY_915_DATA - DDRSS3_PHY_916_DATA - DDRSS3_PHY_917_DATA - DDRSS3_PHY_918_DATA - DDRSS3_PHY_919_DATA - DDRSS3_PHY_920_DATA - DDRSS3_PHY_921_DATA - DDRSS3_PHY_922_DATA - DDRSS3_PHY_923_DATA - DDRSS3_PHY_924_DATA - DDRSS3_PHY_925_DATA - DDRSS3_PHY_926_DATA - DDRSS3_PHY_927_DATA - DDRSS3_PHY_928_DATA - DDRSS3_PHY_929_DATA - DDRSS3_PHY_930_DATA - DDRSS3_PHY_931_DATA - DDRSS3_PHY_932_DATA - DDRSS3_PHY_933_DATA - DDRSS3_PHY_934_DATA - DDRSS3_PHY_935_DATA - DDRSS3_PHY_936_DATA - DDRSS3_PHY_937_DATA - DDRSS3_PHY_938_DATA - DDRSS3_PHY_939_DATA - DDRSS3_PHY_940_DATA - DDRSS3_PHY_941_DATA - DDRSS3_PHY_942_DATA - DDRSS3_PHY_943_DATA - DDRSS3_PHY_944_DATA - DDRSS3_PHY_945_DATA - DDRSS3_PHY_946_DATA - DDRSS3_PHY_947_DATA - DDRSS3_PHY_948_DATA - DDRSS3_PHY_949_DATA - DDRSS3_PHY_950_DATA - DDRSS3_PHY_951_DATA - DDRSS3_PHY_952_DATA - DDRSS3_PHY_953_DATA - DDRSS3_PHY_954_DATA - DDRSS3_PHY_955_DATA - DDRSS3_PHY_956_DATA - DDRSS3_PHY_957_DATA - DDRSS3_PHY_958_DATA - DDRSS3_PHY_959_DATA - DDRSS3_PHY_960_DATA - DDRSS3_PHY_961_DATA - DDRSS3_PHY_962_DATA - DDRSS3_PHY_963_DATA - DDRSS3_PHY_964_DATA - DDRSS3_PHY_965_DATA - DDRSS3_PHY_966_DATA - DDRSS3_PHY_967_DATA - DDRSS3_PHY_968_DATA - DDRSS3_PHY_969_DATA - DDRSS3_PHY_970_DATA - DDRSS3_PHY_971_DATA - DDRSS3_PHY_972_DATA - DDRSS3_PHY_973_DATA - DDRSS3_PHY_974_DATA - DDRSS3_PHY_975_DATA - DDRSS3_PHY_976_DATA - DDRSS3_PHY_977_DATA - DDRSS3_PHY_978_DATA - DDRSS3_PHY_979_DATA - DDRSS3_PHY_980_DATA - DDRSS3_PHY_981_DATA - DDRSS3_PHY_982_DATA - DDRSS3_PHY_983_DATA - DDRSS3_PHY_984_DATA - DDRSS3_PHY_985_DATA - DDRSS3_PHY_986_DATA - DDRSS3_PHY_987_DATA - DDRSS3_PHY_988_DATA - DDRSS3_PHY_989_DATA - DDRSS3_PHY_990_DATA - DDRSS3_PHY_991_DATA - DDRSS3_PHY_992_DATA - DDRSS3_PHY_993_DATA - DDRSS3_PHY_994_DATA - DDRSS3_PHY_995_DATA - DDRSS3_PHY_996_DATA - DDRSS3_PHY_997_DATA - DDRSS3_PHY_998_DATA - DDRSS3_PHY_999_DATA - DDRSS3_PHY_1000_DATA - DDRSS3_PHY_1001_DATA - DDRSS3_PHY_1002_DATA - DDRSS3_PHY_1003_DATA - DDRSS3_PHY_1004_DATA - DDRSS3_PHY_1005_DATA - DDRSS3_PHY_1006_DATA - DDRSS3_PHY_1007_DATA - DDRSS3_PHY_1008_DATA - DDRSS3_PHY_1009_DATA - DDRSS3_PHY_1010_DATA - DDRSS3_PHY_1011_DATA - DDRSS3_PHY_1012_DATA - DDRSS3_PHY_1013_DATA - DDRSS3_PHY_1014_DATA - DDRSS3_PHY_1015_DATA - DDRSS3_PHY_1016_DATA - DDRSS3_PHY_1017_DATA - DDRSS3_PHY_1018_DATA - DDRSS3_PHY_1019_DATA - DDRSS3_PHY_1020_DATA - DDRSS3_PHY_1021_DATA - DDRSS3_PHY_1022_DATA - DDRSS3_PHY_1023_DATA - DDRSS3_PHY_1024_DATA - DDRSS3_PHY_1025_DATA - DDRSS3_PHY_1026_DATA - DDRSS3_PHY_1027_DATA - DDRSS3_PHY_1028_DATA - DDRSS3_PHY_1029_DATA - DDRSS3_PHY_1030_DATA - DDRSS3_PHY_1031_DATA - DDRSS3_PHY_1032_DATA - DDRSS3_PHY_1033_DATA - DDRSS3_PHY_1034_DATA - DDRSS3_PHY_1035_DATA - DDRSS3_PHY_1036_DATA - DDRSS3_PHY_1037_DATA - DDRSS3_PHY_1038_DATA - DDRSS3_PHY_1039_DATA - DDRSS3_PHY_1040_DATA - DDRSS3_PHY_1041_DATA - DDRSS3_PHY_1042_DATA - DDRSS3_PHY_1043_DATA - DDRSS3_PHY_1044_DATA - DDRSS3_PHY_1045_DATA - DDRSS3_PHY_1046_DATA - DDRSS3_PHY_1047_DATA - DDRSS3_PHY_1048_DATA - DDRSS3_PHY_1049_DATA - DDRSS3_PHY_1050_DATA - DDRSS3_PHY_1051_DATA - DDRSS3_PHY_1052_DATA - DDRSS3_PHY_1053_DATA - DDRSS3_PHY_1054_DATA - DDRSS3_PHY_1055_DATA - DDRSS3_PHY_1056_DATA - DDRSS3_PHY_1057_DATA - DDRSS3_PHY_1058_DATA - DDRSS3_PHY_1059_DATA - DDRSS3_PHY_1060_DATA - DDRSS3_PHY_1061_DATA - DDRSS3_PHY_1062_DATA - DDRSS3_PHY_1063_DATA - DDRSS3_PHY_1064_DATA - DDRSS3_PHY_1065_DATA - DDRSS3_PHY_1066_DATA - DDRSS3_PHY_1067_DATA - DDRSS3_PHY_1068_DATA - DDRSS3_PHY_1069_DATA - DDRSS3_PHY_1070_DATA - DDRSS3_PHY_1071_DATA - DDRSS3_PHY_1072_DATA - DDRSS3_PHY_1073_DATA - DDRSS3_PHY_1074_DATA - DDRSS3_PHY_1075_DATA - DDRSS3_PHY_1076_DATA - DDRSS3_PHY_1077_DATA - DDRSS3_PHY_1078_DATA - DDRSS3_PHY_1079_DATA - DDRSS3_PHY_1080_DATA - DDRSS3_PHY_1081_DATA - DDRSS3_PHY_1082_DATA - DDRSS3_PHY_1083_DATA - DDRSS3_PHY_1084_DATA - DDRSS3_PHY_1085_DATA - DDRSS3_PHY_1086_DATA - DDRSS3_PHY_1087_DATA - DDRSS3_PHY_1088_DATA - DDRSS3_PHY_1089_DATA - DDRSS3_PHY_1090_DATA - DDRSS3_PHY_1091_DATA - DDRSS3_PHY_1092_DATA - DDRSS3_PHY_1093_DATA - DDRSS3_PHY_1094_DATA - DDRSS3_PHY_1095_DATA - DDRSS3_PHY_1096_DATA - DDRSS3_PHY_1097_DATA - DDRSS3_PHY_1098_DATA - DDRSS3_PHY_1099_DATA - DDRSS3_PHY_1100_DATA - DDRSS3_PHY_1101_DATA - DDRSS3_PHY_1102_DATA - DDRSS3_PHY_1103_DATA - DDRSS3_PHY_1104_DATA - DDRSS3_PHY_1105_DATA - DDRSS3_PHY_1106_DATA - DDRSS3_PHY_1107_DATA - DDRSS3_PHY_1108_DATA - DDRSS3_PHY_1109_DATA - DDRSS3_PHY_1110_DATA - DDRSS3_PHY_1111_DATA - DDRSS3_PHY_1112_DATA - DDRSS3_PHY_1113_DATA - DDRSS3_PHY_1114_DATA - DDRSS3_PHY_1115_DATA - DDRSS3_PHY_1116_DATA - DDRSS3_PHY_1117_DATA - DDRSS3_PHY_1118_DATA - DDRSS3_PHY_1119_DATA - DDRSS3_PHY_1120_DATA - DDRSS3_PHY_1121_DATA - DDRSS3_PHY_1122_DATA - DDRSS3_PHY_1123_DATA - DDRSS3_PHY_1124_DATA - DDRSS3_PHY_1125_DATA - DDRSS3_PHY_1126_DATA - DDRSS3_PHY_1127_DATA - DDRSS3_PHY_1128_DATA - DDRSS3_PHY_1129_DATA - DDRSS3_PHY_1130_DATA - DDRSS3_PHY_1131_DATA - DDRSS3_PHY_1132_DATA - DDRSS3_PHY_1133_DATA - DDRSS3_PHY_1134_DATA - DDRSS3_PHY_1135_DATA - DDRSS3_PHY_1136_DATA - DDRSS3_PHY_1137_DATA - DDRSS3_PHY_1138_DATA - DDRSS3_PHY_1139_DATA - DDRSS3_PHY_1140_DATA - DDRSS3_PHY_1141_DATA - DDRSS3_PHY_1142_DATA - DDRSS3_PHY_1143_DATA - DDRSS3_PHY_1144_DATA - DDRSS3_PHY_1145_DATA - DDRSS3_PHY_1146_DATA - DDRSS3_PHY_1147_DATA - DDRSS3_PHY_1148_DATA - DDRSS3_PHY_1149_DATA - DDRSS3_PHY_1150_DATA - DDRSS3_PHY_1151_DATA - DDRSS3_PHY_1152_DATA - DDRSS3_PHY_1153_DATA - DDRSS3_PHY_1154_DATA - DDRSS3_PHY_1155_DATA - DDRSS3_PHY_1156_DATA - DDRSS3_PHY_1157_DATA - DDRSS3_PHY_1158_DATA - DDRSS3_PHY_1159_DATA - DDRSS3_PHY_1160_DATA - DDRSS3_PHY_1161_DATA - DDRSS3_PHY_1162_DATA - DDRSS3_PHY_1163_DATA - DDRSS3_PHY_1164_DATA - DDRSS3_PHY_1165_DATA - DDRSS3_PHY_1166_DATA - DDRSS3_PHY_1167_DATA - DDRSS3_PHY_1168_DATA - DDRSS3_PHY_1169_DATA - DDRSS3_PHY_1170_DATA - DDRSS3_PHY_1171_DATA - DDRSS3_PHY_1172_DATA - DDRSS3_PHY_1173_DATA - DDRSS3_PHY_1174_DATA - DDRSS3_PHY_1175_DATA - DDRSS3_PHY_1176_DATA - DDRSS3_PHY_1177_DATA - DDRSS3_PHY_1178_DATA - DDRSS3_PHY_1179_DATA - DDRSS3_PHY_1180_DATA - DDRSS3_PHY_1181_DATA - DDRSS3_PHY_1182_DATA - DDRSS3_PHY_1183_DATA - DDRSS3_PHY_1184_DATA - DDRSS3_PHY_1185_DATA - DDRSS3_PHY_1186_DATA - DDRSS3_PHY_1187_DATA - DDRSS3_PHY_1188_DATA - DDRSS3_PHY_1189_DATA - DDRSS3_PHY_1190_DATA - DDRSS3_PHY_1191_DATA - DDRSS3_PHY_1192_DATA - DDRSS3_PHY_1193_DATA - DDRSS3_PHY_1194_DATA - DDRSS3_PHY_1195_DATA - DDRSS3_PHY_1196_DATA - DDRSS3_PHY_1197_DATA - DDRSS3_PHY_1198_DATA - DDRSS3_PHY_1199_DATA - DDRSS3_PHY_1200_DATA - DDRSS3_PHY_1201_DATA - DDRSS3_PHY_1202_DATA - DDRSS3_PHY_1203_DATA - DDRSS3_PHY_1204_DATA - DDRSS3_PHY_1205_DATA - DDRSS3_PHY_1206_DATA - DDRSS3_PHY_1207_DATA - DDRSS3_PHY_1208_DATA - DDRSS3_PHY_1209_DATA - DDRSS3_PHY_1210_DATA - DDRSS3_PHY_1211_DATA - DDRSS3_PHY_1212_DATA - DDRSS3_PHY_1213_DATA - DDRSS3_PHY_1214_DATA - DDRSS3_PHY_1215_DATA - DDRSS3_PHY_1216_DATA - DDRSS3_PHY_1217_DATA - DDRSS3_PHY_1218_DATA - DDRSS3_PHY_1219_DATA - DDRSS3_PHY_1220_DATA - DDRSS3_PHY_1221_DATA - DDRSS3_PHY_1222_DATA - DDRSS3_PHY_1223_DATA - DDRSS3_PHY_1224_DATA - DDRSS3_PHY_1225_DATA - DDRSS3_PHY_1226_DATA - DDRSS3_PHY_1227_DATA - DDRSS3_PHY_1228_DATA - DDRSS3_PHY_1229_DATA - DDRSS3_PHY_1230_DATA - DDRSS3_PHY_1231_DATA - DDRSS3_PHY_1232_DATA - DDRSS3_PHY_1233_DATA - DDRSS3_PHY_1234_DATA - DDRSS3_PHY_1235_DATA - DDRSS3_PHY_1236_DATA - DDRSS3_PHY_1237_DATA - DDRSS3_PHY_1238_DATA - DDRSS3_PHY_1239_DATA - DDRSS3_PHY_1240_DATA - DDRSS3_PHY_1241_DATA - DDRSS3_PHY_1242_DATA - DDRSS3_PHY_1243_DATA - DDRSS3_PHY_1244_DATA - DDRSS3_PHY_1245_DATA - DDRSS3_PHY_1246_DATA - DDRSS3_PHY_1247_DATA - DDRSS3_PHY_1248_DATA - DDRSS3_PHY_1249_DATA - DDRSS3_PHY_1250_DATA - DDRSS3_PHY_1251_DATA - DDRSS3_PHY_1252_DATA - DDRSS3_PHY_1253_DATA - DDRSS3_PHY_1254_DATA - DDRSS3_PHY_1255_DATA - DDRSS3_PHY_1256_DATA - DDRSS3_PHY_1257_DATA - DDRSS3_PHY_1258_DATA - DDRSS3_PHY_1259_DATA - DDRSS3_PHY_1260_DATA - DDRSS3_PHY_1261_DATA - DDRSS3_PHY_1262_DATA - DDRSS3_PHY_1263_DATA - DDRSS3_PHY_1264_DATA - DDRSS3_PHY_1265_DATA - DDRSS3_PHY_1266_DATA - DDRSS3_PHY_1267_DATA - DDRSS3_PHY_1268_DATA - DDRSS3_PHY_1269_DATA - DDRSS3_PHY_1270_DATA - DDRSS3_PHY_1271_DATA - DDRSS3_PHY_1272_DATA - DDRSS3_PHY_1273_DATA - DDRSS3_PHY_1274_DATA - DDRSS3_PHY_1275_DATA - DDRSS3_PHY_1276_DATA - DDRSS3_PHY_1277_DATA - DDRSS3_PHY_1278_DATA - DDRSS3_PHY_1279_DATA - DDRSS3_PHY_1280_DATA - DDRSS3_PHY_1281_DATA - DDRSS3_PHY_1282_DATA - DDRSS3_PHY_1283_DATA - DDRSS3_PHY_1284_DATA - DDRSS3_PHY_1285_DATA - DDRSS3_PHY_1286_DATA - DDRSS3_PHY_1287_DATA - DDRSS3_PHY_1288_DATA - DDRSS3_PHY_1289_DATA - DDRSS3_PHY_1290_DATA - DDRSS3_PHY_1291_DATA - DDRSS3_PHY_1292_DATA - DDRSS3_PHY_1293_DATA - DDRSS3_PHY_1294_DATA - DDRSS3_PHY_1295_DATA - DDRSS3_PHY_1296_DATA - DDRSS3_PHY_1297_DATA - DDRSS3_PHY_1298_DATA - DDRSS3_PHY_1299_DATA - DDRSS3_PHY_1300_DATA - DDRSS3_PHY_1301_DATA - DDRSS3_PHY_1302_DATA - DDRSS3_PHY_1303_DATA - DDRSS3_PHY_1304_DATA - DDRSS3_PHY_1305_DATA - DDRSS3_PHY_1306_DATA - DDRSS3_PHY_1307_DATA - DDRSS3_PHY_1308_DATA - DDRSS3_PHY_1309_DATA - DDRSS3_PHY_1310_DATA - DDRSS3_PHY_1311_DATA - DDRSS3_PHY_1312_DATA - DDRSS3_PHY_1313_DATA - DDRSS3_PHY_1314_DATA - DDRSS3_PHY_1315_DATA - DDRSS3_PHY_1316_DATA - DDRSS3_PHY_1317_DATA - DDRSS3_PHY_1318_DATA - DDRSS3_PHY_1319_DATA - DDRSS3_PHY_1320_DATA - DDRSS3_PHY_1321_DATA - DDRSS3_PHY_1322_DATA - DDRSS3_PHY_1323_DATA - DDRSS3_PHY_1324_DATA - DDRSS3_PHY_1325_DATA - DDRSS3_PHY_1326_DATA - DDRSS3_PHY_1327_DATA - DDRSS3_PHY_1328_DATA - DDRSS3_PHY_1329_DATA - DDRSS3_PHY_1330_DATA - DDRSS3_PHY_1331_DATA - DDRSS3_PHY_1332_DATA - DDRSS3_PHY_1333_DATA - DDRSS3_PHY_1334_DATA - DDRSS3_PHY_1335_DATA - DDRSS3_PHY_1336_DATA - DDRSS3_PHY_1337_DATA - DDRSS3_PHY_1338_DATA - DDRSS3_PHY_1339_DATA - DDRSS3_PHY_1340_DATA - DDRSS3_PHY_1341_DATA - DDRSS3_PHY_1342_DATA - DDRSS3_PHY_1343_DATA - DDRSS3_PHY_1344_DATA - DDRSS3_PHY_1345_DATA - DDRSS3_PHY_1346_DATA - DDRSS3_PHY_1347_DATA - DDRSS3_PHY_1348_DATA - DDRSS3_PHY_1349_DATA - DDRSS3_PHY_1350_DATA - DDRSS3_PHY_1351_DATA - DDRSS3_PHY_1352_DATA - DDRSS3_PHY_1353_DATA - DDRSS3_PHY_1354_DATA - DDRSS3_PHY_1355_DATA - DDRSS3_PHY_1356_DATA - DDRSS3_PHY_1357_DATA - DDRSS3_PHY_1358_DATA - DDRSS3_PHY_1359_DATA - DDRSS3_PHY_1360_DATA - DDRSS3_PHY_1361_DATA - DDRSS3_PHY_1362_DATA - DDRSS3_PHY_1363_DATA - DDRSS3_PHY_1364_DATA - DDRSS3_PHY_1365_DATA - DDRSS3_PHY_1366_DATA - DDRSS3_PHY_1367_DATA - DDRSS3_PHY_1368_DATA - DDRSS3_PHY_1369_DATA - DDRSS3_PHY_1370_DATA - DDRSS3_PHY_1371_DATA - DDRSS3_PHY_1372_DATA - DDRSS3_PHY_1373_DATA - DDRSS3_PHY_1374_DATA - DDRSS3_PHY_1375_DATA - DDRSS3_PHY_1376_DATA - DDRSS3_PHY_1377_DATA - DDRSS3_PHY_1378_DATA - DDRSS3_PHY_1379_DATA - DDRSS3_PHY_1380_DATA - DDRSS3_PHY_1381_DATA - DDRSS3_PHY_1382_DATA - DDRSS3_PHY_1383_DATA - DDRSS3_PHY_1384_DATA - DDRSS3_PHY_1385_DATA - DDRSS3_PHY_1386_DATA - DDRSS3_PHY_1387_DATA - DDRSS3_PHY_1388_DATA - DDRSS3_PHY_1389_DATA - DDRSS3_PHY_1390_DATA - DDRSS3_PHY_1391_DATA - DDRSS3_PHY_1392_DATA - DDRSS3_PHY_1393_DATA - DDRSS3_PHY_1394_DATA - DDRSS3_PHY_1395_DATA - DDRSS3_PHY_1396_DATA - DDRSS3_PHY_1397_DATA - DDRSS3_PHY_1398_DATA - DDRSS3_PHY_1399_DATA - DDRSS3_PHY_1400_DATA - DDRSS3_PHY_1401_DATA - DDRSS3_PHY_1402_DATA - DDRSS3_PHY_1403_DATA - DDRSS3_PHY_1404_DATA - DDRSS3_PHY_1405_DATA - DDRSS3_PHY_1406_DATA - DDRSS3_PHY_1407_DATA - DDRSS3_PHY_1408_DATA - DDRSS3_PHY_1409_DATA - DDRSS3_PHY_1410_DATA - DDRSS3_PHY_1411_DATA - DDRSS3_PHY_1412_DATA - DDRSS3_PHY_1413_DATA - DDRSS3_PHY_1414_DATA - DDRSS3_PHY_1415_DATA - DDRSS3_PHY_1416_DATA - DDRSS3_PHY_1417_DATA - DDRSS3_PHY_1418_DATA - DDRSS3_PHY_1419_DATA - DDRSS3_PHY_1420_DATA - DDRSS3_PHY_1421_DATA - DDRSS3_PHY_1422_DATA - >; - }; + ti,phy-data = < + DDRSS3_PHY_00_DATA + DDRSS3_PHY_01_DATA + DDRSS3_PHY_02_DATA + DDRSS3_PHY_03_DATA + DDRSS3_PHY_04_DATA + DDRSS3_PHY_05_DATA + DDRSS3_PHY_06_DATA + DDRSS3_PHY_07_DATA + DDRSS3_PHY_08_DATA + DDRSS3_PHY_09_DATA + DDRSS3_PHY_10_DATA + DDRSS3_PHY_11_DATA + DDRSS3_PHY_12_DATA + DDRSS3_PHY_13_DATA + DDRSS3_PHY_14_DATA + DDRSS3_PHY_15_DATA + DDRSS3_PHY_16_DATA + DDRSS3_PHY_17_DATA + DDRSS3_PHY_18_DATA + DDRSS3_PHY_19_DATA + DDRSS3_PHY_20_DATA + DDRSS3_PHY_21_DATA + DDRSS3_PHY_22_DATA + DDRSS3_PHY_23_DATA + DDRSS3_PHY_24_DATA + DDRSS3_PHY_25_DATA + DDRSS3_PHY_26_DATA + DDRSS3_PHY_27_DATA + DDRSS3_PHY_28_DATA + DDRSS3_PHY_29_DATA + DDRSS3_PHY_30_DATA + DDRSS3_PHY_31_DATA + DDRSS3_PHY_32_DATA + DDRSS3_PHY_33_DATA + DDRSS3_PHY_34_DATA + DDRSS3_PHY_35_DATA + DDRSS3_PHY_36_DATA + DDRSS3_PHY_37_DATA + DDRSS3_PHY_38_DATA + DDRSS3_PHY_39_DATA + DDRSS3_PHY_40_DATA + DDRSS3_PHY_41_DATA + DDRSS3_PHY_42_DATA + DDRSS3_PHY_43_DATA + DDRSS3_PHY_44_DATA + DDRSS3_PHY_45_DATA + DDRSS3_PHY_46_DATA + DDRSS3_PHY_47_DATA + DDRSS3_PHY_48_DATA + DDRSS3_PHY_49_DATA + DDRSS3_PHY_50_DATA + DDRSS3_PHY_51_DATA + DDRSS3_PHY_52_DATA + DDRSS3_PHY_53_DATA + DDRSS3_PHY_54_DATA + DDRSS3_PHY_55_DATA + DDRSS3_PHY_56_DATA + DDRSS3_PHY_57_DATA + DDRSS3_PHY_58_DATA + DDRSS3_PHY_59_DATA + DDRSS3_PHY_60_DATA + DDRSS3_PHY_61_DATA + DDRSS3_PHY_62_DATA + DDRSS3_PHY_63_DATA + DDRSS3_PHY_64_DATA + DDRSS3_PHY_65_DATA + DDRSS3_PHY_66_DATA + DDRSS3_PHY_67_DATA + DDRSS3_PHY_68_DATA + DDRSS3_PHY_69_DATA + DDRSS3_PHY_70_DATA + DDRSS3_PHY_71_DATA + DDRSS3_PHY_72_DATA + DDRSS3_PHY_73_DATA + DDRSS3_PHY_74_DATA + DDRSS3_PHY_75_DATA + DDRSS3_PHY_76_DATA + DDRSS3_PHY_77_DATA + DDRSS3_PHY_78_DATA + DDRSS3_PHY_79_DATA + DDRSS3_PHY_80_DATA + DDRSS3_PHY_81_DATA + DDRSS3_PHY_82_DATA + DDRSS3_PHY_83_DATA + DDRSS3_PHY_84_DATA + DDRSS3_PHY_85_DATA + DDRSS3_PHY_86_DATA + DDRSS3_PHY_87_DATA + DDRSS3_PHY_88_DATA + DDRSS3_PHY_89_DATA + DDRSS3_PHY_90_DATA + DDRSS3_PHY_91_DATA + DDRSS3_PHY_92_DATA + DDRSS3_PHY_93_DATA + DDRSS3_PHY_94_DATA + DDRSS3_PHY_95_DATA + DDRSS3_PHY_96_DATA + DDRSS3_PHY_97_DATA + DDRSS3_PHY_98_DATA + DDRSS3_PHY_99_DATA + DDRSS3_PHY_100_DATA + DDRSS3_PHY_101_DATA + DDRSS3_PHY_102_DATA + DDRSS3_PHY_103_DATA + DDRSS3_PHY_104_DATA + DDRSS3_PHY_105_DATA + DDRSS3_PHY_106_DATA + DDRSS3_PHY_107_DATA + DDRSS3_PHY_108_DATA + DDRSS3_PHY_109_DATA + DDRSS3_PHY_110_DATA + DDRSS3_PHY_111_DATA + DDRSS3_PHY_112_DATA + DDRSS3_PHY_113_DATA + DDRSS3_PHY_114_DATA + DDRSS3_PHY_115_DATA + DDRSS3_PHY_116_DATA + DDRSS3_PHY_117_DATA + DDRSS3_PHY_118_DATA + DDRSS3_PHY_119_DATA + DDRSS3_PHY_120_DATA + DDRSS3_PHY_121_DATA + DDRSS3_PHY_122_DATA + DDRSS3_PHY_123_DATA + DDRSS3_PHY_124_DATA + DDRSS3_PHY_125_DATA + DDRSS3_PHY_126_DATA + DDRSS3_PHY_127_DATA + DDRSS3_PHY_128_DATA + DDRSS3_PHY_129_DATA + DDRSS3_PHY_130_DATA + DDRSS3_PHY_131_DATA + DDRSS3_PHY_132_DATA + DDRSS3_PHY_133_DATA + DDRSS3_PHY_134_DATA + DDRSS3_PHY_135_DATA + DDRSS3_PHY_136_DATA + DDRSS3_PHY_137_DATA + DDRSS3_PHY_138_DATA + DDRSS3_PHY_139_DATA + DDRSS3_PHY_140_DATA + DDRSS3_PHY_141_DATA + DDRSS3_PHY_142_DATA + DDRSS3_PHY_143_DATA + DDRSS3_PHY_144_DATA + DDRSS3_PHY_145_DATA + DDRSS3_PHY_146_DATA + DDRSS3_PHY_147_DATA + DDRSS3_PHY_148_DATA + DDRSS3_PHY_149_DATA + DDRSS3_PHY_150_DATA + DDRSS3_PHY_151_DATA + DDRSS3_PHY_152_DATA + DDRSS3_PHY_153_DATA + DDRSS3_PHY_154_DATA + DDRSS3_PHY_155_DATA + DDRSS3_PHY_156_DATA + DDRSS3_PHY_157_DATA + DDRSS3_PHY_158_DATA + DDRSS3_PHY_159_DATA + DDRSS3_PHY_160_DATA + DDRSS3_PHY_161_DATA + DDRSS3_PHY_162_DATA + DDRSS3_PHY_163_DATA + DDRSS3_PHY_164_DATA + DDRSS3_PHY_165_DATA + DDRSS3_PHY_166_DATA + DDRSS3_PHY_167_DATA + DDRSS3_PHY_168_DATA + DDRSS3_PHY_169_DATA + DDRSS3_PHY_170_DATA + DDRSS3_PHY_171_DATA + DDRSS3_PHY_172_DATA + DDRSS3_PHY_173_DATA + DDRSS3_PHY_174_DATA + DDRSS3_PHY_175_DATA + DDRSS3_PHY_176_DATA + DDRSS3_PHY_177_DATA + DDRSS3_PHY_178_DATA + DDRSS3_PHY_179_DATA + DDRSS3_PHY_180_DATA + DDRSS3_PHY_181_DATA + DDRSS3_PHY_182_DATA + DDRSS3_PHY_183_DATA + DDRSS3_PHY_184_DATA + DDRSS3_PHY_185_DATA + DDRSS3_PHY_186_DATA + DDRSS3_PHY_187_DATA + DDRSS3_PHY_188_DATA + DDRSS3_PHY_189_DATA + DDRSS3_PHY_190_DATA + DDRSS3_PHY_191_DATA + DDRSS3_PHY_192_DATA + DDRSS3_PHY_193_DATA + DDRSS3_PHY_194_DATA + DDRSS3_PHY_195_DATA + DDRSS3_PHY_196_DATA + DDRSS3_PHY_197_DATA + DDRSS3_PHY_198_DATA + DDRSS3_PHY_199_DATA + DDRSS3_PHY_200_DATA + DDRSS3_PHY_201_DATA + DDRSS3_PHY_202_DATA + DDRSS3_PHY_203_DATA + DDRSS3_PHY_204_DATA + DDRSS3_PHY_205_DATA + DDRSS3_PHY_206_DATA + DDRSS3_PHY_207_DATA + DDRSS3_PHY_208_DATA + DDRSS3_PHY_209_DATA + DDRSS3_PHY_210_DATA + DDRSS3_PHY_211_DATA + DDRSS3_PHY_212_DATA + DDRSS3_PHY_213_DATA + DDRSS3_PHY_214_DATA + DDRSS3_PHY_215_DATA + DDRSS3_PHY_216_DATA + DDRSS3_PHY_217_DATA + DDRSS3_PHY_218_DATA + DDRSS3_PHY_219_DATA + DDRSS3_PHY_220_DATA + DDRSS3_PHY_221_DATA + DDRSS3_PHY_222_DATA + DDRSS3_PHY_223_DATA + DDRSS3_PHY_224_DATA + DDRSS3_PHY_225_DATA + DDRSS3_PHY_226_DATA + DDRSS3_PHY_227_DATA + DDRSS3_PHY_228_DATA + DDRSS3_PHY_229_DATA + DDRSS3_PHY_230_DATA + DDRSS3_PHY_231_DATA + DDRSS3_PHY_232_DATA + DDRSS3_PHY_233_DATA + DDRSS3_PHY_234_DATA + DDRSS3_PHY_235_DATA + DDRSS3_PHY_236_DATA + DDRSS3_PHY_237_DATA + DDRSS3_PHY_238_DATA + DDRSS3_PHY_239_DATA + DDRSS3_PHY_240_DATA + DDRSS3_PHY_241_DATA + DDRSS3_PHY_242_DATA + DDRSS3_PHY_243_DATA + DDRSS3_PHY_244_DATA + DDRSS3_PHY_245_DATA + DDRSS3_PHY_246_DATA + DDRSS3_PHY_247_DATA + DDRSS3_PHY_248_DATA + DDRSS3_PHY_249_DATA + DDRSS3_PHY_250_DATA + DDRSS3_PHY_251_DATA + DDRSS3_PHY_252_DATA + DDRSS3_PHY_253_DATA + DDRSS3_PHY_254_DATA + DDRSS3_PHY_255_DATA + DDRSS3_PHY_256_DATA + DDRSS3_PHY_257_DATA + DDRSS3_PHY_258_DATA + DDRSS3_PHY_259_DATA + DDRSS3_PHY_260_DATA + DDRSS3_PHY_261_DATA + DDRSS3_PHY_262_DATA + DDRSS3_PHY_263_DATA + DDRSS3_PHY_264_DATA + DDRSS3_PHY_265_DATA + DDRSS3_PHY_266_DATA + DDRSS3_PHY_267_DATA + DDRSS3_PHY_268_DATA + DDRSS3_PHY_269_DATA + DDRSS3_PHY_270_DATA + DDRSS3_PHY_271_DATA + DDRSS3_PHY_272_DATA + DDRSS3_PHY_273_DATA + DDRSS3_PHY_274_DATA + DDRSS3_PHY_275_DATA + DDRSS3_PHY_276_DATA + DDRSS3_PHY_277_DATA + DDRSS3_PHY_278_DATA + DDRSS3_PHY_279_DATA + DDRSS3_PHY_280_DATA + DDRSS3_PHY_281_DATA + DDRSS3_PHY_282_DATA + DDRSS3_PHY_283_DATA + DDRSS3_PHY_284_DATA + DDRSS3_PHY_285_DATA + DDRSS3_PHY_286_DATA + DDRSS3_PHY_287_DATA + DDRSS3_PHY_288_DATA + DDRSS3_PHY_289_DATA + DDRSS3_PHY_290_DATA + DDRSS3_PHY_291_DATA + DDRSS3_PHY_292_DATA + DDRSS3_PHY_293_DATA + DDRSS3_PHY_294_DATA + DDRSS3_PHY_295_DATA + DDRSS3_PHY_296_DATA + DDRSS3_PHY_297_DATA + DDRSS3_PHY_298_DATA + DDRSS3_PHY_299_DATA + DDRSS3_PHY_300_DATA + DDRSS3_PHY_301_DATA + DDRSS3_PHY_302_DATA + DDRSS3_PHY_303_DATA + DDRSS3_PHY_304_DATA + DDRSS3_PHY_305_DATA + DDRSS3_PHY_306_DATA + DDRSS3_PHY_307_DATA + DDRSS3_PHY_308_DATA + DDRSS3_PHY_309_DATA + DDRSS3_PHY_310_DATA + DDRSS3_PHY_311_DATA + DDRSS3_PHY_312_DATA + DDRSS3_PHY_313_DATA + DDRSS3_PHY_314_DATA + DDRSS3_PHY_315_DATA + DDRSS3_PHY_316_DATA + DDRSS3_PHY_317_DATA + DDRSS3_PHY_318_DATA + DDRSS3_PHY_319_DATA + DDRSS3_PHY_320_DATA + DDRSS3_PHY_321_DATA + DDRSS3_PHY_322_DATA + DDRSS3_PHY_323_DATA + DDRSS3_PHY_324_DATA + DDRSS3_PHY_325_DATA + DDRSS3_PHY_326_DATA + DDRSS3_PHY_327_DATA + DDRSS3_PHY_328_DATA + DDRSS3_PHY_329_DATA + DDRSS3_PHY_330_DATA + DDRSS3_PHY_331_DATA + DDRSS3_PHY_332_DATA + DDRSS3_PHY_333_DATA + DDRSS3_PHY_334_DATA + DDRSS3_PHY_335_DATA + DDRSS3_PHY_336_DATA + DDRSS3_PHY_337_DATA + DDRSS3_PHY_338_DATA + DDRSS3_PHY_339_DATA + DDRSS3_PHY_340_DATA + DDRSS3_PHY_341_DATA + DDRSS3_PHY_342_DATA + DDRSS3_PHY_343_DATA + DDRSS3_PHY_344_DATA + DDRSS3_PHY_345_DATA + DDRSS3_PHY_346_DATA + DDRSS3_PHY_347_DATA + DDRSS3_PHY_348_DATA + DDRSS3_PHY_349_DATA + DDRSS3_PHY_350_DATA + DDRSS3_PHY_351_DATA + DDRSS3_PHY_352_DATA + DDRSS3_PHY_353_DATA + DDRSS3_PHY_354_DATA + DDRSS3_PHY_355_DATA + DDRSS3_PHY_356_DATA + DDRSS3_PHY_357_DATA + DDRSS3_PHY_358_DATA + DDRSS3_PHY_359_DATA + DDRSS3_PHY_360_DATA + DDRSS3_PHY_361_DATA + DDRSS3_PHY_362_DATA + DDRSS3_PHY_363_DATA + DDRSS3_PHY_364_DATA + DDRSS3_PHY_365_DATA + DDRSS3_PHY_366_DATA + DDRSS3_PHY_367_DATA + DDRSS3_PHY_368_DATA + DDRSS3_PHY_369_DATA + DDRSS3_PHY_370_DATA + DDRSS3_PHY_371_DATA + DDRSS3_PHY_372_DATA + DDRSS3_PHY_373_DATA + DDRSS3_PHY_374_DATA + DDRSS3_PHY_375_DATA + DDRSS3_PHY_376_DATA + DDRSS3_PHY_377_DATA + DDRSS3_PHY_378_DATA + DDRSS3_PHY_379_DATA + DDRSS3_PHY_380_DATA + DDRSS3_PHY_381_DATA + DDRSS3_PHY_382_DATA + DDRSS3_PHY_383_DATA + DDRSS3_PHY_384_DATA + DDRSS3_PHY_385_DATA + DDRSS3_PHY_386_DATA + DDRSS3_PHY_387_DATA + DDRSS3_PHY_388_DATA + DDRSS3_PHY_389_DATA + DDRSS3_PHY_390_DATA + DDRSS3_PHY_391_DATA + DDRSS3_PHY_392_DATA + DDRSS3_PHY_393_DATA + DDRSS3_PHY_394_DATA + DDRSS3_PHY_395_DATA + DDRSS3_PHY_396_DATA + DDRSS3_PHY_397_DATA + DDRSS3_PHY_398_DATA + DDRSS3_PHY_399_DATA + DDRSS3_PHY_400_DATA + DDRSS3_PHY_401_DATA + DDRSS3_PHY_402_DATA + DDRSS3_PHY_403_DATA + DDRSS3_PHY_404_DATA + DDRSS3_PHY_405_DATA + DDRSS3_PHY_406_DATA + DDRSS3_PHY_407_DATA + DDRSS3_PHY_408_DATA + DDRSS3_PHY_409_DATA + DDRSS3_PHY_410_DATA + DDRSS3_PHY_411_DATA + DDRSS3_PHY_412_DATA + DDRSS3_PHY_413_DATA + DDRSS3_PHY_414_DATA + DDRSS3_PHY_415_DATA + DDRSS3_PHY_416_DATA + DDRSS3_PHY_417_DATA + DDRSS3_PHY_418_DATA + DDRSS3_PHY_419_DATA + DDRSS3_PHY_420_DATA + DDRSS3_PHY_421_DATA + DDRSS3_PHY_422_DATA + DDRSS3_PHY_423_DATA + DDRSS3_PHY_424_DATA + DDRSS3_PHY_425_DATA + DDRSS3_PHY_426_DATA + DDRSS3_PHY_427_DATA + DDRSS3_PHY_428_DATA + DDRSS3_PHY_429_DATA + DDRSS3_PHY_430_DATA + DDRSS3_PHY_431_DATA + DDRSS3_PHY_432_DATA + DDRSS3_PHY_433_DATA + DDRSS3_PHY_434_DATA + DDRSS3_PHY_435_DATA + DDRSS3_PHY_436_DATA + DDRSS3_PHY_437_DATA + DDRSS3_PHY_438_DATA + DDRSS3_PHY_439_DATA + DDRSS3_PHY_440_DATA + DDRSS3_PHY_441_DATA + DDRSS3_PHY_442_DATA + DDRSS3_PHY_443_DATA + DDRSS3_PHY_444_DATA + DDRSS3_PHY_445_DATA + DDRSS3_PHY_446_DATA + DDRSS3_PHY_447_DATA + DDRSS3_PHY_448_DATA + DDRSS3_PHY_449_DATA + DDRSS3_PHY_450_DATA + DDRSS3_PHY_451_DATA + DDRSS3_PHY_452_DATA + DDRSS3_PHY_453_DATA + DDRSS3_PHY_454_DATA + DDRSS3_PHY_455_DATA + DDRSS3_PHY_456_DATA + DDRSS3_PHY_457_DATA + DDRSS3_PHY_458_DATA + DDRSS3_PHY_459_DATA + DDRSS3_PHY_460_DATA + DDRSS3_PHY_461_DATA + DDRSS3_PHY_462_DATA + DDRSS3_PHY_463_DATA + DDRSS3_PHY_464_DATA + DDRSS3_PHY_465_DATA + DDRSS3_PHY_466_DATA + DDRSS3_PHY_467_DATA + DDRSS3_PHY_468_DATA + DDRSS3_PHY_469_DATA + DDRSS3_PHY_470_DATA + DDRSS3_PHY_471_DATA + DDRSS3_PHY_472_DATA + DDRSS3_PHY_473_DATA + DDRSS3_PHY_474_DATA + DDRSS3_PHY_475_DATA + DDRSS3_PHY_476_DATA + DDRSS3_PHY_477_DATA + DDRSS3_PHY_478_DATA + DDRSS3_PHY_479_DATA + DDRSS3_PHY_480_DATA + DDRSS3_PHY_481_DATA + DDRSS3_PHY_482_DATA + DDRSS3_PHY_483_DATA + DDRSS3_PHY_484_DATA + DDRSS3_PHY_485_DATA + DDRSS3_PHY_486_DATA + DDRSS3_PHY_487_DATA + DDRSS3_PHY_488_DATA + DDRSS3_PHY_489_DATA + DDRSS3_PHY_490_DATA + DDRSS3_PHY_491_DATA + DDRSS3_PHY_492_DATA + DDRSS3_PHY_493_DATA + DDRSS3_PHY_494_DATA + DDRSS3_PHY_495_DATA + DDRSS3_PHY_496_DATA + DDRSS3_PHY_497_DATA + DDRSS3_PHY_498_DATA + DDRSS3_PHY_499_DATA + DDRSS3_PHY_500_DATA + DDRSS3_PHY_501_DATA + DDRSS3_PHY_502_DATA + DDRSS3_PHY_503_DATA + DDRSS3_PHY_504_DATA + DDRSS3_PHY_505_DATA + DDRSS3_PHY_506_DATA + DDRSS3_PHY_507_DATA + DDRSS3_PHY_508_DATA + DDRSS3_PHY_509_DATA + DDRSS3_PHY_510_DATA + DDRSS3_PHY_511_DATA + DDRSS3_PHY_512_DATA + DDRSS3_PHY_513_DATA + DDRSS3_PHY_514_DATA + DDRSS3_PHY_515_DATA + DDRSS3_PHY_516_DATA + DDRSS3_PHY_517_DATA + DDRSS3_PHY_518_DATA + DDRSS3_PHY_519_DATA + DDRSS3_PHY_520_DATA + DDRSS3_PHY_521_DATA + DDRSS3_PHY_522_DATA + DDRSS3_PHY_523_DATA + DDRSS3_PHY_524_DATA + DDRSS3_PHY_525_DATA + DDRSS3_PHY_526_DATA + DDRSS3_PHY_527_DATA + DDRSS3_PHY_528_DATA + DDRSS3_PHY_529_DATA + DDRSS3_PHY_530_DATA + DDRSS3_PHY_531_DATA + DDRSS3_PHY_532_DATA + DDRSS3_PHY_533_DATA + DDRSS3_PHY_534_DATA + DDRSS3_PHY_535_DATA + DDRSS3_PHY_536_DATA + DDRSS3_PHY_537_DATA + DDRSS3_PHY_538_DATA + DDRSS3_PHY_539_DATA + DDRSS3_PHY_540_DATA + DDRSS3_PHY_541_DATA + DDRSS3_PHY_542_DATA + DDRSS3_PHY_543_DATA + DDRSS3_PHY_544_DATA + DDRSS3_PHY_545_DATA + DDRSS3_PHY_546_DATA + DDRSS3_PHY_547_DATA + DDRSS3_PHY_548_DATA + DDRSS3_PHY_549_DATA + DDRSS3_PHY_550_DATA + DDRSS3_PHY_551_DATA + DDRSS3_PHY_552_DATA + DDRSS3_PHY_553_DATA + DDRSS3_PHY_554_DATA + DDRSS3_PHY_555_DATA + DDRSS3_PHY_556_DATA + DDRSS3_PHY_557_DATA + DDRSS3_PHY_558_DATA + DDRSS3_PHY_559_DATA + DDRSS3_PHY_560_DATA + DDRSS3_PHY_561_DATA + DDRSS3_PHY_562_DATA + DDRSS3_PHY_563_DATA + DDRSS3_PHY_564_DATA + DDRSS3_PHY_565_DATA + DDRSS3_PHY_566_DATA + DDRSS3_PHY_567_DATA + DDRSS3_PHY_568_DATA + DDRSS3_PHY_569_DATA + DDRSS3_PHY_570_DATA + DDRSS3_PHY_571_DATA + DDRSS3_PHY_572_DATA + DDRSS3_PHY_573_DATA + DDRSS3_PHY_574_DATA + DDRSS3_PHY_575_DATA + DDRSS3_PHY_576_DATA + DDRSS3_PHY_577_DATA + DDRSS3_PHY_578_DATA + DDRSS3_PHY_579_DATA + DDRSS3_PHY_580_DATA + DDRSS3_PHY_581_DATA + DDRSS3_PHY_582_DATA + DDRSS3_PHY_583_DATA + DDRSS3_PHY_584_DATA + DDRSS3_PHY_585_DATA + DDRSS3_PHY_586_DATA + DDRSS3_PHY_587_DATA + DDRSS3_PHY_588_DATA + DDRSS3_PHY_589_DATA + DDRSS3_PHY_590_DATA + DDRSS3_PHY_591_DATA + DDRSS3_PHY_592_DATA + DDRSS3_PHY_593_DATA + DDRSS3_PHY_594_DATA + DDRSS3_PHY_595_DATA + DDRSS3_PHY_596_DATA + DDRSS3_PHY_597_DATA + DDRSS3_PHY_598_DATA + DDRSS3_PHY_599_DATA + DDRSS3_PHY_600_DATA + DDRSS3_PHY_601_DATA + DDRSS3_PHY_602_DATA + DDRSS3_PHY_603_DATA + DDRSS3_PHY_604_DATA + DDRSS3_PHY_605_DATA + DDRSS3_PHY_606_DATA + DDRSS3_PHY_607_DATA + DDRSS3_PHY_608_DATA + DDRSS3_PHY_609_DATA + DDRSS3_PHY_610_DATA + DDRSS3_PHY_611_DATA + DDRSS3_PHY_612_DATA + DDRSS3_PHY_613_DATA + DDRSS3_PHY_614_DATA + DDRSS3_PHY_615_DATA + DDRSS3_PHY_616_DATA + DDRSS3_PHY_617_DATA + DDRSS3_PHY_618_DATA + DDRSS3_PHY_619_DATA + DDRSS3_PHY_620_DATA + DDRSS3_PHY_621_DATA + DDRSS3_PHY_622_DATA + DDRSS3_PHY_623_DATA + DDRSS3_PHY_624_DATA + DDRSS3_PHY_625_DATA + DDRSS3_PHY_626_DATA + DDRSS3_PHY_627_DATA + DDRSS3_PHY_628_DATA + DDRSS3_PHY_629_DATA + DDRSS3_PHY_630_DATA + DDRSS3_PHY_631_DATA + DDRSS3_PHY_632_DATA + DDRSS3_PHY_633_DATA + DDRSS3_PHY_634_DATA + DDRSS3_PHY_635_DATA + DDRSS3_PHY_636_DATA + DDRSS3_PHY_637_DATA + DDRSS3_PHY_638_DATA + DDRSS3_PHY_639_DATA + DDRSS3_PHY_640_DATA + DDRSS3_PHY_641_DATA + DDRSS3_PHY_642_DATA + DDRSS3_PHY_643_DATA + DDRSS3_PHY_644_DATA + DDRSS3_PHY_645_DATA + DDRSS3_PHY_646_DATA + DDRSS3_PHY_647_DATA + DDRSS3_PHY_648_DATA + DDRSS3_PHY_649_DATA + DDRSS3_PHY_650_DATA + DDRSS3_PHY_651_DATA + DDRSS3_PHY_652_DATA + DDRSS3_PHY_653_DATA + DDRSS3_PHY_654_DATA + DDRSS3_PHY_655_DATA + DDRSS3_PHY_656_DATA + DDRSS3_PHY_657_DATA + DDRSS3_PHY_658_DATA + DDRSS3_PHY_659_DATA + DDRSS3_PHY_660_DATA + DDRSS3_PHY_661_DATA + DDRSS3_PHY_662_DATA + DDRSS3_PHY_663_DATA + DDRSS3_PHY_664_DATA + DDRSS3_PHY_665_DATA + DDRSS3_PHY_666_DATA + DDRSS3_PHY_667_DATA + DDRSS3_PHY_668_DATA + DDRSS3_PHY_669_DATA + DDRSS3_PHY_670_DATA + DDRSS3_PHY_671_DATA + DDRSS3_PHY_672_DATA + DDRSS3_PHY_673_DATA + DDRSS3_PHY_674_DATA + DDRSS3_PHY_675_DATA + DDRSS3_PHY_676_DATA + DDRSS3_PHY_677_DATA + DDRSS3_PHY_678_DATA + DDRSS3_PHY_679_DATA + DDRSS3_PHY_680_DATA + DDRSS3_PHY_681_DATA + DDRSS3_PHY_682_DATA + DDRSS3_PHY_683_DATA + DDRSS3_PHY_684_DATA + DDRSS3_PHY_685_DATA + DDRSS3_PHY_686_DATA + DDRSS3_PHY_687_DATA + DDRSS3_PHY_688_DATA + DDRSS3_PHY_689_DATA + DDRSS3_PHY_690_DATA + DDRSS3_PHY_691_DATA + DDRSS3_PHY_692_DATA + DDRSS3_PHY_693_DATA + DDRSS3_PHY_694_DATA + DDRSS3_PHY_695_DATA + DDRSS3_PHY_696_DATA + DDRSS3_PHY_697_DATA + DDRSS3_PHY_698_DATA + DDRSS3_PHY_699_DATA + DDRSS3_PHY_700_DATA + DDRSS3_PHY_701_DATA + DDRSS3_PHY_702_DATA + DDRSS3_PHY_703_DATA + DDRSS3_PHY_704_DATA + DDRSS3_PHY_705_DATA + DDRSS3_PHY_706_DATA + DDRSS3_PHY_707_DATA + DDRSS3_PHY_708_DATA + DDRSS3_PHY_709_DATA + DDRSS3_PHY_710_DATA + DDRSS3_PHY_711_DATA + DDRSS3_PHY_712_DATA + DDRSS3_PHY_713_DATA + DDRSS3_PHY_714_DATA + DDRSS3_PHY_715_DATA + DDRSS3_PHY_716_DATA + DDRSS3_PHY_717_DATA + DDRSS3_PHY_718_DATA + DDRSS3_PHY_719_DATA + DDRSS3_PHY_720_DATA + DDRSS3_PHY_721_DATA + DDRSS3_PHY_722_DATA + DDRSS3_PHY_723_DATA + DDRSS3_PHY_724_DATA + DDRSS3_PHY_725_DATA + DDRSS3_PHY_726_DATA + DDRSS3_PHY_727_DATA + DDRSS3_PHY_728_DATA + DDRSS3_PHY_729_DATA + DDRSS3_PHY_730_DATA + DDRSS3_PHY_731_DATA + DDRSS3_PHY_732_DATA + DDRSS3_PHY_733_DATA + DDRSS3_PHY_734_DATA + DDRSS3_PHY_735_DATA + DDRSS3_PHY_736_DATA + DDRSS3_PHY_737_DATA + DDRSS3_PHY_738_DATA + DDRSS3_PHY_739_DATA + DDRSS3_PHY_740_DATA + DDRSS3_PHY_741_DATA + DDRSS3_PHY_742_DATA + DDRSS3_PHY_743_DATA + DDRSS3_PHY_744_DATA + DDRSS3_PHY_745_DATA + DDRSS3_PHY_746_DATA + DDRSS3_PHY_747_DATA + DDRSS3_PHY_748_DATA + DDRSS3_PHY_749_DATA + DDRSS3_PHY_750_DATA + DDRSS3_PHY_751_DATA + DDRSS3_PHY_752_DATA + DDRSS3_PHY_753_DATA + DDRSS3_PHY_754_DATA + DDRSS3_PHY_755_DATA + DDRSS3_PHY_756_DATA + DDRSS3_PHY_757_DATA + DDRSS3_PHY_758_DATA + DDRSS3_PHY_759_DATA + DDRSS3_PHY_760_DATA + DDRSS3_PHY_761_DATA + DDRSS3_PHY_762_DATA + DDRSS3_PHY_763_DATA + DDRSS3_PHY_764_DATA + DDRSS3_PHY_765_DATA + DDRSS3_PHY_766_DATA + DDRSS3_PHY_767_DATA + DDRSS3_PHY_768_DATA + DDRSS3_PHY_769_DATA + DDRSS3_PHY_770_DATA + DDRSS3_PHY_771_DATA + DDRSS3_PHY_772_DATA + DDRSS3_PHY_773_DATA + DDRSS3_PHY_774_DATA + DDRSS3_PHY_775_DATA + DDRSS3_PHY_776_DATA + DDRSS3_PHY_777_DATA + DDRSS3_PHY_778_DATA + DDRSS3_PHY_779_DATA + DDRSS3_PHY_780_DATA + DDRSS3_PHY_781_DATA + DDRSS3_PHY_782_DATA + DDRSS3_PHY_783_DATA + DDRSS3_PHY_784_DATA + DDRSS3_PHY_785_DATA + DDRSS3_PHY_786_DATA + DDRSS3_PHY_787_DATA + DDRSS3_PHY_788_DATA + DDRSS3_PHY_789_DATA + DDRSS3_PHY_790_DATA + DDRSS3_PHY_791_DATA + DDRSS3_PHY_792_DATA + DDRSS3_PHY_793_DATA + DDRSS3_PHY_794_DATA + DDRSS3_PHY_795_DATA + DDRSS3_PHY_796_DATA + DDRSS3_PHY_797_DATA + DDRSS3_PHY_798_DATA + DDRSS3_PHY_799_DATA + DDRSS3_PHY_800_DATA + DDRSS3_PHY_801_DATA + DDRSS3_PHY_802_DATA + DDRSS3_PHY_803_DATA + DDRSS3_PHY_804_DATA + DDRSS3_PHY_805_DATA + DDRSS3_PHY_806_DATA + DDRSS3_PHY_807_DATA + DDRSS3_PHY_808_DATA + DDRSS3_PHY_809_DATA + DDRSS3_PHY_810_DATA + DDRSS3_PHY_811_DATA + DDRSS3_PHY_812_DATA + DDRSS3_PHY_813_DATA + DDRSS3_PHY_814_DATA + DDRSS3_PHY_815_DATA + DDRSS3_PHY_816_DATA + DDRSS3_PHY_817_DATA + DDRSS3_PHY_818_DATA + DDRSS3_PHY_819_DATA + DDRSS3_PHY_820_DATA + DDRSS3_PHY_821_DATA + DDRSS3_PHY_822_DATA + DDRSS3_PHY_823_DATA + DDRSS3_PHY_824_DATA + DDRSS3_PHY_825_DATA + DDRSS3_PHY_826_DATA + DDRSS3_PHY_827_DATA + DDRSS3_PHY_828_DATA + DDRSS3_PHY_829_DATA + DDRSS3_PHY_830_DATA + DDRSS3_PHY_831_DATA + DDRSS3_PHY_832_DATA + DDRSS3_PHY_833_DATA + DDRSS3_PHY_834_DATA + DDRSS3_PHY_835_DATA + DDRSS3_PHY_836_DATA + DDRSS3_PHY_837_DATA + DDRSS3_PHY_838_DATA + DDRSS3_PHY_839_DATA + DDRSS3_PHY_840_DATA + DDRSS3_PHY_841_DATA + DDRSS3_PHY_842_DATA + DDRSS3_PHY_843_DATA + DDRSS3_PHY_844_DATA + DDRSS3_PHY_845_DATA + DDRSS3_PHY_846_DATA + DDRSS3_PHY_847_DATA + DDRSS3_PHY_848_DATA + DDRSS3_PHY_849_DATA + DDRSS3_PHY_850_DATA + DDRSS3_PHY_851_DATA + DDRSS3_PHY_852_DATA + DDRSS3_PHY_853_DATA + DDRSS3_PHY_854_DATA + DDRSS3_PHY_855_DATA + DDRSS3_PHY_856_DATA + DDRSS3_PHY_857_DATA + DDRSS3_PHY_858_DATA + DDRSS3_PHY_859_DATA + DDRSS3_PHY_860_DATA + DDRSS3_PHY_861_DATA + DDRSS3_PHY_862_DATA + DDRSS3_PHY_863_DATA + DDRSS3_PHY_864_DATA + DDRSS3_PHY_865_DATA + DDRSS3_PHY_866_DATA + DDRSS3_PHY_867_DATA + DDRSS3_PHY_868_DATA + DDRSS3_PHY_869_DATA + DDRSS3_PHY_870_DATA + DDRSS3_PHY_871_DATA + DDRSS3_PHY_872_DATA + DDRSS3_PHY_873_DATA + DDRSS3_PHY_874_DATA + DDRSS3_PHY_875_DATA + DDRSS3_PHY_876_DATA + DDRSS3_PHY_877_DATA + DDRSS3_PHY_878_DATA + DDRSS3_PHY_879_DATA + DDRSS3_PHY_880_DATA + DDRSS3_PHY_881_DATA + DDRSS3_PHY_882_DATA + DDRSS3_PHY_883_DATA + DDRSS3_PHY_884_DATA + DDRSS3_PHY_885_DATA + DDRSS3_PHY_886_DATA + DDRSS3_PHY_887_DATA + DDRSS3_PHY_888_DATA + DDRSS3_PHY_889_DATA + DDRSS3_PHY_890_DATA + DDRSS3_PHY_891_DATA + DDRSS3_PHY_892_DATA + DDRSS3_PHY_893_DATA + DDRSS3_PHY_894_DATA + DDRSS3_PHY_895_DATA + DDRSS3_PHY_896_DATA + DDRSS3_PHY_897_DATA + DDRSS3_PHY_898_DATA + DDRSS3_PHY_899_DATA + DDRSS3_PHY_900_DATA + DDRSS3_PHY_901_DATA + DDRSS3_PHY_902_DATA + DDRSS3_PHY_903_DATA + DDRSS3_PHY_904_DATA + DDRSS3_PHY_905_DATA + DDRSS3_PHY_906_DATA + DDRSS3_PHY_907_DATA + DDRSS3_PHY_908_DATA + DDRSS3_PHY_909_DATA + DDRSS3_PHY_910_DATA + DDRSS3_PHY_911_DATA + DDRSS3_PHY_912_DATA + DDRSS3_PHY_913_DATA + DDRSS3_PHY_914_DATA + DDRSS3_PHY_915_DATA + DDRSS3_PHY_916_DATA + DDRSS3_PHY_917_DATA + DDRSS3_PHY_918_DATA + DDRSS3_PHY_919_DATA + DDRSS3_PHY_920_DATA + DDRSS3_PHY_921_DATA + DDRSS3_PHY_922_DATA + DDRSS3_PHY_923_DATA + DDRSS3_PHY_924_DATA + DDRSS3_PHY_925_DATA + DDRSS3_PHY_926_DATA + DDRSS3_PHY_927_DATA + DDRSS3_PHY_928_DATA + DDRSS3_PHY_929_DATA + DDRSS3_PHY_930_DATA + DDRSS3_PHY_931_DATA + DDRSS3_PHY_932_DATA + DDRSS3_PHY_933_DATA + DDRSS3_PHY_934_DATA + DDRSS3_PHY_935_DATA + DDRSS3_PHY_936_DATA + DDRSS3_PHY_937_DATA + DDRSS3_PHY_938_DATA + DDRSS3_PHY_939_DATA + DDRSS3_PHY_940_DATA + DDRSS3_PHY_941_DATA + DDRSS3_PHY_942_DATA + DDRSS3_PHY_943_DATA + DDRSS3_PHY_944_DATA + DDRSS3_PHY_945_DATA + DDRSS3_PHY_946_DATA + DDRSS3_PHY_947_DATA + DDRSS3_PHY_948_DATA + DDRSS3_PHY_949_DATA + DDRSS3_PHY_950_DATA + DDRSS3_PHY_951_DATA + DDRSS3_PHY_952_DATA + DDRSS3_PHY_953_DATA + DDRSS3_PHY_954_DATA + DDRSS3_PHY_955_DATA + DDRSS3_PHY_956_DATA + DDRSS3_PHY_957_DATA + DDRSS3_PHY_958_DATA + DDRSS3_PHY_959_DATA + DDRSS3_PHY_960_DATA + DDRSS3_PHY_961_DATA + DDRSS3_PHY_962_DATA + DDRSS3_PHY_963_DATA + DDRSS3_PHY_964_DATA + DDRSS3_PHY_965_DATA + DDRSS3_PHY_966_DATA + DDRSS3_PHY_967_DATA + DDRSS3_PHY_968_DATA + DDRSS3_PHY_969_DATA + DDRSS3_PHY_970_DATA + DDRSS3_PHY_971_DATA + DDRSS3_PHY_972_DATA + DDRSS3_PHY_973_DATA + DDRSS3_PHY_974_DATA + DDRSS3_PHY_975_DATA + DDRSS3_PHY_976_DATA + DDRSS3_PHY_977_DATA + DDRSS3_PHY_978_DATA + DDRSS3_PHY_979_DATA + DDRSS3_PHY_980_DATA + DDRSS3_PHY_981_DATA + DDRSS3_PHY_982_DATA + DDRSS3_PHY_983_DATA + DDRSS3_PHY_984_DATA + DDRSS3_PHY_985_DATA + DDRSS3_PHY_986_DATA + DDRSS3_PHY_987_DATA + DDRSS3_PHY_988_DATA + DDRSS3_PHY_989_DATA + DDRSS3_PHY_990_DATA + DDRSS3_PHY_991_DATA + DDRSS3_PHY_992_DATA + DDRSS3_PHY_993_DATA + DDRSS3_PHY_994_DATA + DDRSS3_PHY_995_DATA + DDRSS3_PHY_996_DATA + DDRSS3_PHY_997_DATA + DDRSS3_PHY_998_DATA + DDRSS3_PHY_999_DATA + DDRSS3_PHY_1000_DATA + DDRSS3_PHY_1001_DATA + DDRSS3_PHY_1002_DATA + DDRSS3_PHY_1003_DATA + DDRSS3_PHY_1004_DATA + DDRSS3_PHY_1005_DATA + DDRSS3_PHY_1006_DATA + DDRSS3_PHY_1007_DATA + DDRSS3_PHY_1008_DATA + DDRSS3_PHY_1009_DATA + DDRSS3_PHY_1010_DATA + DDRSS3_PHY_1011_DATA + DDRSS3_PHY_1012_DATA + DDRSS3_PHY_1013_DATA + DDRSS3_PHY_1014_DATA + DDRSS3_PHY_1015_DATA + DDRSS3_PHY_1016_DATA + DDRSS3_PHY_1017_DATA + DDRSS3_PHY_1018_DATA + DDRSS3_PHY_1019_DATA + DDRSS3_PHY_1020_DATA + DDRSS3_PHY_1021_DATA + DDRSS3_PHY_1022_DATA + DDRSS3_PHY_1023_DATA + DDRSS3_PHY_1024_DATA + DDRSS3_PHY_1025_DATA + DDRSS3_PHY_1026_DATA + DDRSS3_PHY_1027_DATA + DDRSS3_PHY_1028_DATA + DDRSS3_PHY_1029_DATA + DDRSS3_PHY_1030_DATA + DDRSS3_PHY_1031_DATA + DDRSS3_PHY_1032_DATA + DDRSS3_PHY_1033_DATA + DDRSS3_PHY_1034_DATA + DDRSS3_PHY_1035_DATA + DDRSS3_PHY_1036_DATA + DDRSS3_PHY_1037_DATA + DDRSS3_PHY_1038_DATA + DDRSS3_PHY_1039_DATA + DDRSS3_PHY_1040_DATA + DDRSS3_PHY_1041_DATA + DDRSS3_PHY_1042_DATA + DDRSS3_PHY_1043_DATA + DDRSS3_PHY_1044_DATA + DDRSS3_PHY_1045_DATA + DDRSS3_PHY_1046_DATA + DDRSS3_PHY_1047_DATA + DDRSS3_PHY_1048_DATA + DDRSS3_PHY_1049_DATA + DDRSS3_PHY_1050_DATA + DDRSS3_PHY_1051_DATA + DDRSS3_PHY_1052_DATA + DDRSS3_PHY_1053_DATA + DDRSS3_PHY_1054_DATA + DDRSS3_PHY_1055_DATA + DDRSS3_PHY_1056_DATA + DDRSS3_PHY_1057_DATA + DDRSS3_PHY_1058_DATA + DDRSS3_PHY_1059_DATA + DDRSS3_PHY_1060_DATA + DDRSS3_PHY_1061_DATA + DDRSS3_PHY_1062_DATA + DDRSS3_PHY_1063_DATA + DDRSS3_PHY_1064_DATA + DDRSS3_PHY_1065_DATA + DDRSS3_PHY_1066_DATA + DDRSS3_PHY_1067_DATA + DDRSS3_PHY_1068_DATA + DDRSS3_PHY_1069_DATA + DDRSS3_PHY_1070_DATA + DDRSS3_PHY_1071_DATA + DDRSS3_PHY_1072_DATA + DDRSS3_PHY_1073_DATA + DDRSS3_PHY_1074_DATA + DDRSS3_PHY_1075_DATA + DDRSS3_PHY_1076_DATA + DDRSS3_PHY_1077_DATA + DDRSS3_PHY_1078_DATA + DDRSS3_PHY_1079_DATA + DDRSS3_PHY_1080_DATA + DDRSS3_PHY_1081_DATA + DDRSS3_PHY_1082_DATA + DDRSS3_PHY_1083_DATA + DDRSS3_PHY_1084_DATA + DDRSS3_PHY_1085_DATA + DDRSS3_PHY_1086_DATA + DDRSS3_PHY_1087_DATA + DDRSS3_PHY_1088_DATA + DDRSS3_PHY_1089_DATA + DDRSS3_PHY_1090_DATA + DDRSS3_PHY_1091_DATA + DDRSS3_PHY_1092_DATA + DDRSS3_PHY_1093_DATA + DDRSS3_PHY_1094_DATA + DDRSS3_PHY_1095_DATA + DDRSS3_PHY_1096_DATA + DDRSS3_PHY_1097_DATA + DDRSS3_PHY_1098_DATA + DDRSS3_PHY_1099_DATA + DDRSS3_PHY_1100_DATA + DDRSS3_PHY_1101_DATA + DDRSS3_PHY_1102_DATA + DDRSS3_PHY_1103_DATA + DDRSS3_PHY_1104_DATA + DDRSS3_PHY_1105_DATA + DDRSS3_PHY_1106_DATA + DDRSS3_PHY_1107_DATA + DDRSS3_PHY_1108_DATA + DDRSS3_PHY_1109_DATA + DDRSS3_PHY_1110_DATA + DDRSS3_PHY_1111_DATA + DDRSS3_PHY_1112_DATA + DDRSS3_PHY_1113_DATA + DDRSS3_PHY_1114_DATA + DDRSS3_PHY_1115_DATA + DDRSS3_PHY_1116_DATA + DDRSS3_PHY_1117_DATA + DDRSS3_PHY_1118_DATA + DDRSS3_PHY_1119_DATA + DDRSS3_PHY_1120_DATA + DDRSS3_PHY_1121_DATA + DDRSS3_PHY_1122_DATA + DDRSS3_PHY_1123_DATA + DDRSS3_PHY_1124_DATA + DDRSS3_PHY_1125_DATA + DDRSS3_PHY_1126_DATA + DDRSS3_PHY_1127_DATA + DDRSS3_PHY_1128_DATA + DDRSS3_PHY_1129_DATA + DDRSS3_PHY_1130_DATA + DDRSS3_PHY_1131_DATA + DDRSS3_PHY_1132_DATA + DDRSS3_PHY_1133_DATA + DDRSS3_PHY_1134_DATA + DDRSS3_PHY_1135_DATA + DDRSS3_PHY_1136_DATA + DDRSS3_PHY_1137_DATA + DDRSS3_PHY_1138_DATA + DDRSS3_PHY_1139_DATA + DDRSS3_PHY_1140_DATA + DDRSS3_PHY_1141_DATA + DDRSS3_PHY_1142_DATA + DDRSS3_PHY_1143_DATA + DDRSS3_PHY_1144_DATA + DDRSS3_PHY_1145_DATA + DDRSS3_PHY_1146_DATA + DDRSS3_PHY_1147_DATA + DDRSS3_PHY_1148_DATA + DDRSS3_PHY_1149_DATA + DDRSS3_PHY_1150_DATA + DDRSS3_PHY_1151_DATA + DDRSS3_PHY_1152_DATA + DDRSS3_PHY_1153_DATA + DDRSS3_PHY_1154_DATA + DDRSS3_PHY_1155_DATA + DDRSS3_PHY_1156_DATA + DDRSS3_PHY_1157_DATA + DDRSS3_PHY_1158_DATA + DDRSS3_PHY_1159_DATA + DDRSS3_PHY_1160_DATA + DDRSS3_PHY_1161_DATA + DDRSS3_PHY_1162_DATA + DDRSS3_PHY_1163_DATA + DDRSS3_PHY_1164_DATA + DDRSS3_PHY_1165_DATA + DDRSS3_PHY_1166_DATA + DDRSS3_PHY_1167_DATA + DDRSS3_PHY_1168_DATA + DDRSS3_PHY_1169_DATA + DDRSS3_PHY_1170_DATA + DDRSS3_PHY_1171_DATA + DDRSS3_PHY_1172_DATA + DDRSS3_PHY_1173_DATA + DDRSS3_PHY_1174_DATA + DDRSS3_PHY_1175_DATA + DDRSS3_PHY_1176_DATA + DDRSS3_PHY_1177_DATA + DDRSS3_PHY_1178_DATA + DDRSS3_PHY_1179_DATA + DDRSS3_PHY_1180_DATA + DDRSS3_PHY_1181_DATA + DDRSS3_PHY_1182_DATA + DDRSS3_PHY_1183_DATA + DDRSS3_PHY_1184_DATA + DDRSS3_PHY_1185_DATA + DDRSS3_PHY_1186_DATA + DDRSS3_PHY_1187_DATA + DDRSS3_PHY_1188_DATA + DDRSS3_PHY_1189_DATA + DDRSS3_PHY_1190_DATA + DDRSS3_PHY_1191_DATA + DDRSS3_PHY_1192_DATA + DDRSS3_PHY_1193_DATA + DDRSS3_PHY_1194_DATA + DDRSS3_PHY_1195_DATA + DDRSS3_PHY_1196_DATA + DDRSS3_PHY_1197_DATA + DDRSS3_PHY_1198_DATA + DDRSS3_PHY_1199_DATA + DDRSS3_PHY_1200_DATA + DDRSS3_PHY_1201_DATA + DDRSS3_PHY_1202_DATA + DDRSS3_PHY_1203_DATA + DDRSS3_PHY_1204_DATA + DDRSS3_PHY_1205_DATA + DDRSS3_PHY_1206_DATA + DDRSS3_PHY_1207_DATA + DDRSS3_PHY_1208_DATA + DDRSS3_PHY_1209_DATA + DDRSS3_PHY_1210_DATA + DDRSS3_PHY_1211_DATA + DDRSS3_PHY_1212_DATA + DDRSS3_PHY_1213_DATA + DDRSS3_PHY_1214_DATA + DDRSS3_PHY_1215_DATA + DDRSS3_PHY_1216_DATA + DDRSS3_PHY_1217_DATA + DDRSS3_PHY_1218_DATA + DDRSS3_PHY_1219_DATA + DDRSS3_PHY_1220_DATA + DDRSS3_PHY_1221_DATA + DDRSS3_PHY_1222_DATA + DDRSS3_PHY_1223_DATA + DDRSS3_PHY_1224_DATA + DDRSS3_PHY_1225_DATA + DDRSS3_PHY_1226_DATA + DDRSS3_PHY_1227_DATA + DDRSS3_PHY_1228_DATA + DDRSS3_PHY_1229_DATA + DDRSS3_PHY_1230_DATA + DDRSS3_PHY_1231_DATA + DDRSS3_PHY_1232_DATA + DDRSS3_PHY_1233_DATA + DDRSS3_PHY_1234_DATA + DDRSS3_PHY_1235_DATA + DDRSS3_PHY_1236_DATA + DDRSS3_PHY_1237_DATA + DDRSS3_PHY_1238_DATA + DDRSS3_PHY_1239_DATA + DDRSS3_PHY_1240_DATA + DDRSS3_PHY_1241_DATA + DDRSS3_PHY_1242_DATA + DDRSS3_PHY_1243_DATA + DDRSS3_PHY_1244_DATA + DDRSS3_PHY_1245_DATA + DDRSS3_PHY_1246_DATA + DDRSS3_PHY_1247_DATA + DDRSS3_PHY_1248_DATA + DDRSS3_PHY_1249_DATA + DDRSS3_PHY_1250_DATA + DDRSS3_PHY_1251_DATA + DDRSS3_PHY_1252_DATA + DDRSS3_PHY_1253_DATA + DDRSS3_PHY_1254_DATA + DDRSS3_PHY_1255_DATA + DDRSS3_PHY_1256_DATA + DDRSS3_PHY_1257_DATA + DDRSS3_PHY_1258_DATA + DDRSS3_PHY_1259_DATA + DDRSS3_PHY_1260_DATA + DDRSS3_PHY_1261_DATA + DDRSS3_PHY_1262_DATA + DDRSS3_PHY_1263_DATA + DDRSS3_PHY_1264_DATA + DDRSS3_PHY_1265_DATA + DDRSS3_PHY_1266_DATA + DDRSS3_PHY_1267_DATA + DDRSS3_PHY_1268_DATA + DDRSS3_PHY_1269_DATA + DDRSS3_PHY_1270_DATA + DDRSS3_PHY_1271_DATA + DDRSS3_PHY_1272_DATA + DDRSS3_PHY_1273_DATA + DDRSS3_PHY_1274_DATA + DDRSS3_PHY_1275_DATA + DDRSS3_PHY_1276_DATA + DDRSS3_PHY_1277_DATA + DDRSS3_PHY_1278_DATA + DDRSS3_PHY_1279_DATA + DDRSS3_PHY_1280_DATA + DDRSS3_PHY_1281_DATA + DDRSS3_PHY_1282_DATA + DDRSS3_PHY_1283_DATA + DDRSS3_PHY_1284_DATA + DDRSS3_PHY_1285_DATA + DDRSS3_PHY_1286_DATA + DDRSS3_PHY_1287_DATA + DDRSS3_PHY_1288_DATA + DDRSS3_PHY_1289_DATA + DDRSS3_PHY_1290_DATA + DDRSS3_PHY_1291_DATA + DDRSS3_PHY_1292_DATA + DDRSS3_PHY_1293_DATA + DDRSS3_PHY_1294_DATA + DDRSS3_PHY_1295_DATA + DDRSS3_PHY_1296_DATA + DDRSS3_PHY_1297_DATA + DDRSS3_PHY_1298_DATA + DDRSS3_PHY_1299_DATA + DDRSS3_PHY_1300_DATA + DDRSS3_PHY_1301_DATA + DDRSS3_PHY_1302_DATA + DDRSS3_PHY_1303_DATA + DDRSS3_PHY_1304_DATA + DDRSS3_PHY_1305_DATA + DDRSS3_PHY_1306_DATA + DDRSS3_PHY_1307_DATA + DDRSS3_PHY_1308_DATA + DDRSS3_PHY_1309_DATA + DDRSS3_PHY_1310_DATA + DDRSS3_PHY_1311_DATA + DDRSS3_PHY_1312_DATA + DDRSS3_PHY_1313_DATA + DDRSS3_PHY_1314_DATA + DDRSS3_PHY_1315_DATA + DDRSS3_PHY_1316_DATA + DDRSS3_PHY_1317_DATA + DDRSS3_PHY_1318_DATA + DDRSS3_PHY_1319_DATA + DDRSS3_PHY_1320_DATA + DDRSS3_PHY_1321_DATA + DDRSS3_PHY_1322_DATA + DDRSS3_PHY_1323_DATA + DDRSS3_PHY_1324_DATA + DDRSS3_PHY_1325_DATA + DDRSS3_PHY_1326_DATA + DDRSS3_PHY_1327_DATA + DDRSS3_PHY_1328_DATA + DDRSS3_PHY_1329_DATA + DDRSS3_PHY_1330_DATA + DDRSS3_PHY_1331_DATA + DDRSS3_PHY_1332_DATA + DDRSS3_PHY_1333_DATA + DDRSS3_PHY_1334_DATA + DDRSS3_PHY_1335_DATA + DDRSS3_PHY_1336_DATA + DDRSS3_PHY_1337_DATA + DDRSS3_PHY_1338_DATA + DDRSS3_PHY_1339_DATA + DDRSS3_PHY_1340_DATA + DDRSS3_PHY_1341_DATA + DDRSS3_PHY_1342_DATA + DDRSS3_PHY_1343_DATA + DDRSS3_PHY_1344_DATA + DDRSS3_PHY_1345_DATA + DDRSS3_PHY_1346_DATA + DDRSS3_PHY_1347_DATA + DDRSS3_PHY_1348_DATA + DDRSS3_PHY_1349_DATA + DDRSS3_PHY_1350_DATA + DDRSS3_PHY_1351_DATA + DDRSS3_PHY_1352_DATA + DDRSS3_PHY_1353_DATA + DDRSS3_PHY_1354_DATA + DDRSS3_PHY_1355_DATA + DDRSS3_PHY_1356_DATA + DDRSS3_PHY_1357_DATA + DDRSS3_PHY_1358_DATA + DDRSS3_PHY_1359_DATA + DDRSS3_PHY_1360_DATA + DDRSS3_PHY_1361_DATA + DDRSS3_PHY_1362_DATA + DDRSS3_PHY_1363_DATA + DDRSS3_PHY_1364_DATA + DDRSS3_PHY_1365_DATA + DDRSS3_PHY_1366_DATA + DDRSS3_PHY_1367_DATA + DDRSS3_PHY_1368_DATA + DDRSS3_PHY_1369_DATA + DDRSS3_PHY_1370_DATA + DDRSS3_PHY_1371_DATA + DDRSS3_PHY_1372_DATA + DDRSS3_PHY_1373_DATA + DDRSS3_PHY_1374_DATA + DDRSS3_PHY_1375_DATA + DDRSS3_PHY_1376_DATA + DDRSS3_PHY_1377_DATA + DDRSS3_PHY_1378_DATA + DDRSS3_PHY_1379_DATA + DDRSS3_PHY_1380_DATA + DDRSS3_PHY_1381_DATA + DDRSS3_PHY_1382_DATA + DDRSS3_PHY_1383_DATA + DDRSS3_PHY_1384_DATA + DDRSS3_PHY_1385_DATA + DDRSS3_PHY_1386_DATA + DDRSS3_PHY_1387_DATA + DDRSS3_PHY_1388_DATA + DDRSS3_PHY_1389_DATA + DDRSS3_PHY_1390_DATA + DDRSS3_PHY_1391_DATA + DDRSS3_PHY_1392_DATA + DDRSS3_PHY_1393_DATA + DDRSS3_PHY_1394_DATA + DDRSS3_PHY_1395_DATA + DDRSS3_PHY_1396_DATA + DDRSS3_PHY_1397_DATA + DDRSS3_PHY_1398_DATA + DDRSS3_PHY_1399_DATA + DDRSS3_PHY_1400_DATA + DDRSS3_PHY_1401_DATA + DDRSS3_PHY_1402_DATA + DDRSS3_PHY_1403_DATA + DDRSS3_PHY_1404_DATA + DDRSS3_PHY_1405_DATA + DDRSS3_PHY_1406_DATA + DDRSS3_PHY_1407_DATA + DDRSS3_PHY_1408_DATA + DDRSS3_PHY_1409_DATA + DDRSS3_PHY_1410_DATA + DDRSS3_PHY_1411_DATA + DDRSS3_PHY_1412_DATA + DDRSS3_PHY_1413_DATA + DDRSS3_PHY_1414_DATA + DDRSS3_PHY_1415_DATA + DDRSS3_PHY_1416_DATA + DDRSS3_PHY_1417_DATA + DDRSS3_PHY_1418_DATA + DDRSS3_PHY_1419_DATA + DDRSS3_PHY_1420_DATA + DDRSS3_PHY_1421_DATA + DDRSS3_PHY_1422_DATA + >; }; }; diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi index 8f0307321e8..8a60d7c6107 100644 --- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi @@ -3,8 +3,83 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ +#define SPL_BOARD_DTB "spl/dts/ti/k3-j784s4-evm.dtb" +#define BOARD_DESCRIPTION "k3-j784s4-evm" +#define UBOOT_BOARD_DESCRIPTION "U-Boot for J784S4 board" + #include "k3-j784s4-binman.dtsi" +#if defined(CONFIG_CPU_V7R) + +&binman { + tiboot3-j784s4-hs { + insert-template = <&tiboot3_j784s4_hs>; + filename = "tiboot3-j784s4-hs-evm.bin"; + }; + + tiboot3-j784s4-hs-fs { + insert-template = <&tiboot3_j784s4_hs_fs>; + filename = "tiboot3-j784s4-hs-fs-evm.bin"; + }; + + tiboot3-j784s4-gp { + insert-template = <&tiboot3_j784s4_gp>; + filename = "tiboot3-j784s4-gp-evm.bin"; + symlink = "tiboot3.bin"; + }; +}; + +&ti_fs_gp { + filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin"; +}; + +&ti_fs_enc { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; +}; + +&sysfw_inner_cert { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; +}; + +&ti_fs_enc_fs { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin"; +}; + +&sysfw_inner_cert_fs { + filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin"; +}; + +#else // CONFIG_ARM64 + +&binman { + ti-dm { + filename = "ti-dm.bin"; + + blob-ext { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + tispl { + insert-template = <&ti_spl>; + }; + + u-boot { + insert-template = <&u_boot>; + }; + + tispl-unsigned { + insert-template = <&ti_spl_unsigned>; + }; + + u-boot-unsigned { + insert-template = <&u_boot_unsigned>; + }; +}; + +#endif + / { memory@80000000 { bootph-all; diff --git a/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi b/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi new file mode 100644 index 00000000000..c03eddcb560 --- /dev/null +++ b/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi @@ -0,0 +1,4448 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&main_navss { + ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr + <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg + <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg + <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg + <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg + <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0 + <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1 + <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2 + <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3 + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + + msmc0: msmc { + compatible = "ti,j721s2-msmc"; + intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>; + intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>; + ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>; + emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>; + emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>; + #address-cells = <2>; + #size-cells = <2>; + + bootph-pre-ram; + + memorycontroller0: memorycontroller@2990000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>, + <0x0 0x02980000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; + power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>, + <&k3_pds 131 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 191 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <0>; + + bootph-pre-ram; + + ti,ctl-data = < + DDRSS0_CTL_00_DATA + DDRSS0_CTL_01_DATA + DDRSS0_CTL_02_DATA + DDRSS0_CTL_03_DATA + DDRSS0_CTL_04_DATA + DDRSS0_CTL_05_DATA + DDRSS0_CTL_06_DATA + DDRSS0_CTL_07_DATA + DDRSS0_CTL_08_DATA + DDRSS0_CTL_09_DATA + DDRSS0_CTL_10_DATA + DDRSS0_CTL_11_DATA + DDRSS0_CTL_12_DATA + DDRSS0_CTL_13_DATA + DDRSS0_CTL_14_DATA + DDRSS0_CTL_15_DATA + DDRSS0_CTL_16_DATA + DDRSS0_CTL_17_DATA + DDRSS0_CTL_18_DATA + DDRSS0_CTL_19_DATA + DDRSS0_CTL_20_DATA + DDRSS0_CTL_21_DATA + DDRSS0_CTL_22_DATA + DDRSS0_CTL_23_DATA + DDRSS0_CTL_24_DATA + DDRSS0_CTL_25_DATA + DDRSS0_CTL_26_DATA + DDRSS0_CTL_27_DATA + DDRSS0_CTL_28_DATA + DDRSS0_CTL_29_DATA + DDRSS0_CTL_30_DATA + DDRSS0_CTL_31_DATA + DDRSS0_CTL_32_DATA + DDRSS0_CTL_33_DATA + DDRSS0_CTL_34_DATA + DDRSS0_CTL_35_DATA + DDRSS0_CTL_36_DATA + DDRSS0_CTL_37_DATA + DDRSS0_CTL_38_DATA + DDRSS0_CTL_39_DATA + DDRSS0_CTL_40_DATA + DDRSS0_CTL_41_DATA + DDRSS0_CTL_42_DATA + DDRSS0_CTL_43_DATA + DDRSS0_CTL_44_DATA + DDRSS0_CTL_45_DATA + DDRSS0_CTL_46_DATA + DDRSS0_CTL_47_DATA + DDRSS0_CTL_48_DATA + DDRSS0_CTL_49_DATA + DDRSS0_CTL_50_DATA + DDRSS0_CTL_51_DATA + DDRSS0_CTL_52_DATA + DDRSS0_CTL_53_DATA + DDRSS0_CTL_54_DATA + DDRSS0_CTL_55_DATA + DDRSS0_CTL_56_DATA + DDRSS0_CTL_57_DATA + DDRSS0_CTL_58_DATA + DDRSS0_CTL_59_DATA + DDRSS0_CTL_60_DATA + DDRSS0_CTL_61_DATA + DDRSS0_CTL_62_DATA + DDRSS0_CTL_63_DATA + DDRSS0_CTL_64_DATA + DDRSS0_CTL_65_DATA + DDRSS0_CTL_66_DATA + DDRSS0_CTL_67_DATA + DDRSS0_CTL_68_DATA + DDRSS0_CTL_69_DATA + DDRSS0_CTL_70_DATA + DDRSS0_CTL_71_DATA + DDRSS0_CTL_72_DATA + DDRSS0_CTL_73_DATA + DDRSS0_CTL_74_DATA + DDRSS0_CTL_75_DATA + DDRSS0_CTL_76_DATA + DDRSS0_CTL_77_DATA + DDRSS0_CTL_78_DATA + DDRSS0_CTL_79_DATA + DDRSS0_CTL_80_DATA + DDRSS0_CTL_81_DATA + DDRSS0_CTL_82_DATA + DDRSS0_CTL_83_DATA + DDRSS0_CTL_84_DATA + DDRSS0_CTL_85_DATA + DDRSS0_CTL_86_DATA + DDRSS0_CTL_87_DATA + DDRSS0_CTL_88_DATA + DDRSS0_CTL_89_DATA + DDRSS0_CTL_90_DATA + DDRSS0_CTL_91_DATA + DDRSS0_CTL_92_DATA + DDRSS0_CTL_93_DATA + DDRSS0_CTL_94_DATA + DDRSS0_CTL_95_DATA + DDRSS0_CTL_96_DATA + DDRSS0_CTL_97_DATA + DDRSS0_CTL_98_DATA + DDRSS0_CTL_99_DATA + DDRSS0_CTL_100_DATA + DDRSS0_CTL_101_DATA + DDRSS0_CTL_102_DATA + DDRSS0_CTL_103_DATA + DDRSS0_CTL_104_DATA + DDRSS0_CTL_105_DATA + DDRSS0_CTL_106_DATA + DDRSS0_CTL_107_DATA + DDRSS0_CTL_108_DATA + DDRSS0_CTL_109_DATA + DDRSS0_CTL_110_DATA + DDRSS0_CTL_111_DATA + DDRSS0_CTL_112_DATA + DDRSS0_CTL_113_DATA + DDRSS0_CTL_114_DATA + DDRSS0_CTL_115_DATA + DDRSS0_CTL_116_DATA + DDRSS0_CTL_117_DATA + DDRSS0_CTL_118_DATA + DDRSS0_CTL_119_DATA + DDRSS0_CTL_120_DATA + DDRSS0_CTL_121_DATA + DDRSS0_CTL_122_DATA + DDRSS0_CTL_123_DATA + DDRSS0_CTL_124_DATA + DDRSS0_CTL_125_DATA + DDRSS0_CTL_126_DATA + DDRSS0_CTL_127_DATA + DDRSS0_CTL_128_DATA + DDRSS0_CTL_129_DATA + DDRSS0_CTL_130_DATA + DDRSS0_CTL_131_DATA + DDRSS0_CTL_132_DATA + DDRSS0_CTL_133_DATA + DDRSS0_CTL_134_DATA + DDRSS0_CTL_135_DATA + DDRSS0_CTL_136_DATA + DDRSS0_CTL_137_DATA + DDRSS0_CTL_138_DATA + DDRSS0_CTL_139_DATA + DDRSS0_CTL_140_DATA + DDRSS0_CTL_141_DATA + DDRSS0_CTL_142_DATA + DDRSS0_CTL_143_DATA + DDRSS0_CTL_144_DATA + DDRSS0_CTL_145_DATA + DDRSS0_CTL_146_DATA + DDRSS0_CTL_147_DATA + DDRSS0_CTL_148_DATA + DDRSS0_CTL_149_DATA + DDRSS0_CTL_150_DATA + DDRSS0_CTL_151_DATA + DDRSS0_CTL_152_DATA + DDRSS0_CTL_153_DATA + DDRSS0_CTL_154_DATA + DDRSS0_CTL_155_DATA + DDRSS0_CTL_156_DATA + DDRSS0_CTL_157_DATA + DDRSS0_CTL_158_DATA + DDRSS0_CTL_159_DATA + DDRSS0_CTL_160_DATA + DDRSS0_CTL_161_DATA + DDRSS0_CTL_162_DATA + DDRSS0_CTL_163_DATA + DDRSS0_CTL_164_DATA + DDRSS0_CTL_165_DATA + DDRSS0_CTL_166_DATA + DDRSS0_CTL_167_DATA + DDRSS0_CTL_168_DATA + DDRSS0_CTL_169_DATA + DDRSS0_CTL_170_DATA + DDRSS0_CTL_171_DATA + DDRSS0_CTL_172_DATA + DDRSS0_CTL_173_DATA + DDRSS0_CTL_174_DATA + DDRSS0_CTL_175_DATA + DDRSS0_CTL_176_DATA + DDRSS0_CTL_177_DATA + DDRSS0_CTL_178_DATA + DDRSS0_CTL_179_DATA + DDRSS0_CTL_180_DATA + DDRSS0_CTL_181_DATA + DDRSS0_CTL_182_DATA + DDRSS0_CTL_183_DATA + DDRSS0_CTL_184_DATA + DDRSS0_CTL_185_DATA + DDRSS0_CTL_186_DATA + DDRSS0_CTL_187_DATA + DDRSS0_CTL_188_DATA + DDRSS0_CTL_189_DATA + DDRSS0_CTL_190_DATA + DDRSS0_CTL_191_DATA + DDRSS0_CTL_192_DATA + DDRSS0_CTL_193_DATA + DDRSS0_CTL_194_DATA + DDRSS0_CTL_195_DATA + DDRSS0_CTL_196_DATA + DDRSS0_CTL_197_DATA + DDRSS0_CTL_198_DATA + DDRSS0_CTL_199_DATA + DDRSS0_CTL_200_DATA + DDRSS0_CTL_201_DATA + DDRSS0_CTL_202_DATA + DDRSS0_CTL_203_DATA + DDRSS0_CTL_204_DATA + DDRSS0_CTL_205_DATA + DDRSS0_CTL_206_DATA + DDRSS0_CTL_207_DATA + DDRSS0_CTL_208_DATA + DDRSS0_CTL_209_DATA + DDRSS0_CTL_210_DATA + DDRSS0_CTL_211_DATA + DDRSS0_CTL_212_DATA + DDRSS0_CTL_213_DATA + DDRSS0_CTL_214_DATA + DDRSS0_CTL_215_DATA + DDRSS0_CTL_216_DATA + DDRSS0_CTL_217_DATA + DDRSS0_CTL_218_DATA + DDRSS0_CTL_219_DATA + DDRSS0_CTL_220_DATA + DDRSS0_CTL_221_DATA + DDRSS0_CTL_222_DATA + DDRSS0_CTL_223_DATA + DDRSS0_CTL_224_DATA + DDRSS0_CTL_225_DATA + DDRSS0_CTL_226_DATA + DDRSS0_CTL_227_DATA + DDRSS0_CTL_228_DATA + DDRSS0_CTL_229_DATA + DDRSS0_CTL_230_DATA + DDRSS0_CTL_231_DATA + DDRSS0_CTL_232_DATA + DDRSS0_CTL_233_DATA + DDRSS0_CTL_234_DATA + DDRSS0_CTL_235_DATA + DDRSS0_CTL_236_DATA + DDRSS0_CTL_237_DATA + DDRSS0_CTL_238_DATA + DDRSS0_CTL_239_DATA + DDRSS0_CTL_240_DATA + DDRSS0_CTL_241_DATA + DDRSS0_CTL_242_DATA + DDRSS0_CTL_243_DATA + DDRSS0_CTL_244_DATA + DDRSS0_CTL_245_DATA + DDRSS0_CTL_246_DATA + DDRSS0_CTL_247_DATA + DDRSS0_CTL_248_DATA + DDRSS0_CTL_249_DATA + DDRSS0_CTL_250_DATA + DDRSS0_CTL_251_DATA + DDRSS0_CTL_252_DATA + DDRSS0_CTL_253_DATA + DDRSS0_CTL_254_DATA + DDRSS0_CTL_255_DATA + DDRSS0_CTL_256_DATA + DDRSS0_CTL_257_DATA + DDRSS0_CTL_258_DATA + DDRSS0_CTL_259_DATA + DDRSS0_CTL_260_DATA + DDRSS0_CTL_261_DATA + DDRSS0_CTL_262_DATA + DDRSS0_CTL_263_DATA + DDRSS0_CTL_264_DATA + DDRSS0_CTL_265_DATA + DDRSS0_CTL_266_DATA + DDRSS0_CTL_267_DATA + DDRSS0_CTL_268_DATA + DDRSS0_CTL_269_DATA + DDRSS0_CTL_270_DATA + DDRSS0_CTL_271_DATA + DDRSS0_CTL_272_DATA + DDRSS0_CTL_273_DATA + DDRSS0_CTL_274_DATA + DDRSS0_CTL_275_DATA + DDRSS0_CTL_276_DATA + DDRSS0_CTL_277_DATA + DDRSS0_CTL_278_DATA + DDRSS0_CTL_279_DATA + DDRSS0_CTL_280_DATA + DDRSS0_CTL_281_DATA + DDRSS0_CTL_282_DATA + DDRSS0_CTL_283_DATA + DDRSS0_CTL_284_DATA + DDRSS0_CTL_285_DATA + DDRSS0_CTL_286_DATA + DDRSS0_CTL_287_DATA + DDRSS0_CTL_288_DATA + DDRSS0_CTL_289_DATA + DDRSS0_CTL_290_DATA + DDRSS0_CTL_291_DATA + DDRSS0_CTL_292_DATA + DDRSS0_CTL_293_DATA + DDRSS0_CTL_294_DATA + DDRSS0_CTL_295_DATA + DDRSS0_CTL_296_DATA + DDRSS0_CTL_297_DATA + DDRSS0_CTL_298_DATA + DDRSS0_CTL_299_DATA + DDRSS0_CTL_300_DATA + DDRSS0_CTL_301_DATA + DDRSS0_CTL_302_DATA + DDRSS0_CTL_303_DATA + DDRSS0_CTL_304_DATA + DDRSS0_CTL_305_DATA + DDRSS0_CTL_306_DATA + DDRSS0_CTL_307_DATA + DDRSS0_CTL_308_DATA + DDRSS0_CTL_309_DATA + DDRSS0_CTL_310_DATA + DDRSS0_CTL_311_DATA + DDRSS0_CTL_312_DATA + DDRSS0_CTL_313_DATA + DDRSS0_CTL_314_DATA + DDRSS0_CTL_315_DATA + DDRSS0_CTL_316_DATA + DDRSS0_CTL_317_DATA + DDRSS0_CTL_318_DATA + DDRSS0_CTL_319_DATA + DDRSS0_CTL_320_DATA + DDRSS0_CTL_321_DATA + DDRSS0_CTL_322_DATA + DDRSS0_CTL_323_DATA + DDRSS0_CTL_324_DATA + DDRSS0_CTL_325_DATA + DDRSS0_CTL_326_DATA + DDRSS0_CTL_327_DATA + DDRSS0_CTL_328_DATA + DDRSS0_CTL_329_DATA + DDRSS0_CTL_330_DATA + DDRSS0_CTL_331_DATA + DDRSS0_CTL_332_DATA + DDRSS0_CTL_333_DATA + DDRSS0_CTL_334_DATA + DDRSS0_CTL_335_DATA + DDRSS0_CTL_336_DATA + DDRSS0_CTL_337_DATA + DDRSS0_CTL_338_DATA + DDRSS0_CTL_339_DATA + DDRSS0_CTL_340_DATA + DDRSS0_CTL_341_DATA + DDRSS0_CTL_342_DATA + DDRSS0_CTL_343_DATA + DDRSS0_CTL_344_DATA + DDRSS0_CTL_345_DATA + DDRSS0_CTL_346_DATA + DDRSS0_CTL_347_DATA + DDRSS0_CTL_348_DATA + DDRSS0_CTL_349_DATA + DDRSS0_CTL_350_DATA + DDRSS0_CTL_351_DATA + DDRSS0_CTL_352_DATA + DDRSS0_CTL_353_DATA + DDRSS0_CTL_354_DATA + DDRSS0_CTL_355_DATA + DDRSS0_CTL_356_DATA + DDRSS0_CTL_357_DATA + DDRSS0_CTL_358_DATA + DDRSS0_CTL_359_DATA + DDRSS0_CTL_360_DATA + DDRSS0_CTL_361_DATA + DDRSS0_CTL_362_DATA + DDRSS0_CTL_363_DATA + DDRSS0_CTL_364_DATA + DDRSS0_CTL_365_DATA + DDRSS0_CTL_366_DATA + DDRSS0_CTL_367_DATA + DDRSS0_CTL_368_DATA + DDRSS0_CTL_369_DATA + DDRSS0_CTL_370_DATA + DDRSS0_CTL_371_DATA + DDRSS0_CTL_372_DATA + DDRSS0_CTL_373_DATA + DDRSS0_CTL_374_DATA + DDRSS0_CTL_375_DATA + DDRSS0_CTL_376_DATA + DDRSS0_CTL_377_DATA + DDRSS0_CTL_378_DATA + DDRSS0_CTL_379_DATA + DDRSS0_CTL_380_DATA + DDRSS0_CTL_381_DATA + DDRSS0_CTL_382_DATA + DDRSS0_CTL_383_DATA + DDRSS0_CTL_384_DATA + DDRSS0_CTL_385_DATA + DDRSS0_CTL_386_DATA + DDRSS0_CTL_387_DATA + DDRSS0_CTL_388_DATA + DDRSS0_CTL_389_DATA + DDRSS0_CTL_390_DATA + DDRSS0_CTL_391_DATA + DDRSS0_CTL_392_DATA + DDRSS0_CTL_393_DATA + DDRSS0_CTL_394_DATA + DDRSS0_CTL_395_DATA + DDRSS0_CTL_396_DATA + DDRSS0_CTL_397_DATA + DDRSS0_CTL_398_DATA + DDRSS0_CTL_399_DATA + DDRSS0_CTL_400_DATA + DDRSS0_CTL_401_DATA + DDRSS0_CTL_402_DATA + DDRSS0_CTL_403_DATA + DDRSS0_CTL_404_DATA + DDRSS0_CTL_405_DATA + DDRSS0_CTL_406_DATA + DDRSS0_CTL_407_DATA + DDRSS0_CTL_408_DATA + DDRSS0_CTL_409_DATA + DDRSS0_CTL_410_DATA + DDRSS0_CTL_411_DATA + DDRSS0_CTL_412_DATA + DDRSS0_CTL_413_DATA + DDRSS0_CTL_414_DATA + DDRSS0_CTL_415_DATA + DDRSS0_CTL_416_DATA + DDRSS0_CTL_417_DATA + DDRSS0_CTL_418_DATA + DDRSS0_CTL_419_DATA + DDRSS0_CTL_420_DATA + DDRSS0_CTL_421_DATA + DDRSS0_CTL_422_DATA + DDRSS0_CTL_423_DATA + DDRSS0_CTL_424_DATA + DDRSS0_CTL_425_DATA + DDRSS0_CTL_426_DATA + DDRSS0_CTL_427_DATA + DDRSS0_CTL_428_DATA + DDRSS0_CTL_429_DATA + DDRSS0_CTL_430_DATA + DDRSS0_CTL_431_DATA + DDRSS0_CTL_432_DATA + DDRSS0_CTL_433_DATA + DDRSS0_CTL_434_DATA + DDRSS0_CTL_435_DATA + DDRSS0_CTL_436_DATA + DDRSS0_CTL_437_DATA + DDRSS0_CTL_438_DATA + DDRSS0_CTL_439_DATA + DDRSS0_CTL_440_DATA + DDRSS0_CTL_441_DATA + DDRSS0_CTL_442_DATA + DDRSS0_CTL_443_DATA + DDRSS0_CTL_444_DATA + DDRSS0_CTL_445_DATA + DDRSS0_CTL_446_DATA + DDRSS0_CTL_447_DATA + DDRSS0_CTL_448_DATA + DDRSS0_CTL_449_DATA + DDRSS0_CTL_450_DATA + DDRSS0_CTL_451_DATA + DDRSS0_CTL_452_DATA + DDRSS0_CTL_453_DATA + DDRSS0_CTL_454_DATA + DDRSS0_CTL_455_DATA + DDRSS0_CTL_456_DATA + DDRSS0_CTL_457_DATA + DDRSS0_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS0_PI_00_DATA + DDRSS0_PI_01_DATA + DDRSS0_PI_02_DATA + DDRSS0_PI_03_DATA + DDRSS0_PI_04_DATA + DDRSS0_PI_05_DATA + DDRSS0_PI_06_DATA + DDRSS0_PI_07_DATA + DDRSS0_PI_08_DATA + DDRSS0_PI_09_DATA + DDRSS0_PI_10_DATA + DDRSS0_PI_11_DATA + DDRSS0_PI_12_DATA + DDRSS0_PI_13_DATA + DDRSS0_PI_14_DATA + DDRSS0_PI_15_DATA + DDRSS0_PI_16_DATA + DDRSS0_PI_17_DATA + DDRSS0_PI_18_DATA + DDRSS0_PI_19_DATA + DDRSS0_PI_20_DATA + DDRSS0_PI_21_DATA + DDRSS0_PI_22_DATA + DDRSS0_PI_23_DATA + DDRSS0_PI_24_DATA + DDRSS0_PI_25_DATA + DDRSS0_PI_26_DATA + DDRSS0_PI_27_DATA + DDRSS0_PI_28_DATA + DDRSS0_PI_29_DATA + DDRSS0_PI_30_DATA + DDRSS0_PI_31_DATA + DDRSS0_PI_32_DATA + DDRSS0_PI_33_DATA + DDRSS0_PI_34_DATA + DDRSS0_PI_35_DATA + DDRSS0_PI_36_DATA + DDRSS0_PI_37_DATA + DDRSS0_PI_38_DATA + DDRSS0_PI_39_DATA + DDRSS0_PI_40_DATA + DDRSS0_PI_41_DATA + DDRSS0_PI_42_DATA + DDRSS0_PI_43_DATA + DDRSS0_PI_44_DATA + DDRSS0_PI_45_DATA + DDRSS0_PI_46_DATA + DDRSS0_PI_47_DATA + DDRSS0_PI_48_DATA + DDRSS0_PI_49_DATA + DDRSS0_PI_50_DATA + DDRSS0_PI_51_DATA + DDRSS0_PI_52_DATA + DDRSS0_PI_53_DATA + DDRSS0_PI_54_DATA + DDRSS0_PI_55_DATA + DDRSS0_PI_56_DATA + DDRSS0_PI_57_DATA + DDRSS0_PI_58_DATA + DDRSS0_PI_59_DATA + DDRSS0_PI_60_DATA + DDRSS0_PI_61_DATA + DDRSS0_PI_62_DATA + DDRSS0_PI_63_DATA + DDRSS0_PI_64_DATA + DDRSS0_PI_65_DATA + DDRSS0_PI_66_DATA + DDRSS0_PI_67_DATA + DDRSS0_PI_68_DATA + DDRSS0_PI_69_DATA + DDRSS0_PI_70_DATA + DDRSS0_PI_71_DATA + DDRSS0_PI_72_DATA + DDRSS0_PI_73_DATA + DDRSS0_PI_74_DATA + DDRSS0_PI_75_DATA + DDRSS0_PI_76_DATA + DDRSS0_PI_77_DATA + DDRSS0_PI_78_DATA + DDRSS0_PI_79_DATA + DDRSS0_PI_80_DATA + DDRSS0_PI_81_DATA + DDRSS0_PI_82_DATA + DDRSS0_PI_83_DATA + DDRSS0_PI_84_DATA + DDRSS0_PI_85_DATA + DDRSS0_PI_86_DATA + DDRSS0_PI_87_DATA + DDRSS0_PI_88_DATA + DDRSS0_PI_89_DATA + DDRSS0_PI_90_DATA + DDRSS0_PI_91_DATA + DDRSS0_PI_92_DATA + DDRSS0_PI_93_DATA + DDRSS0_PI_94_DATA + DDRSS0_PI_95_DATA + DDRSS0_PI_96_DATA + DDRSS0_PI_97_DATA + DDRSS0_PI_98_DATA + DDRSS0_PI_99_DATA + DDRSS0_PI_100_DATA + DDRSS0_PI_101_DATA + DDRSS0_PI_102_DATA + DDRSS0_PI_103_DATA + DDRSS0_PI_104_DATA + DDRSS0_PI_105_DATA + DDRSS0_PI_106_DATA + DDRSS0_PI_107_DATA + DDRSS0_PI_108_DATA + DDRSS0_PI_109_DATA + DDRSS0_PI_110_DATA + DDRSS0_PI_111_DATA + DDRSS0_PI_112_DATA + DDRSS0_PI_113_DATA + DDRSS0_PI_114_DATA + DDRSS0_PI_115_DATA + DDRSS0_PI_116_DATA + DDRSS0_PI_117_DATA + DDRSS0_PI_118_DATA + DDRSS0_PI_119_DATA + DDRSS0_PI_120_DATA + DDRSS0_PI_121_DATA + DDRSS0_PI_122_DATA + DDRSS0_PI_123_DATA + DDRSS0_PI_124_DATA + DDRSS0_PI_125_DATA + DDRSS0_PI_126_DATA + DDRSS0_PI_127_DATA + DDRSS0_PI_128_DATA + DDRSS0_PI_129_DATA + DDRSS0_PI_130_DATA + DDRSS0_PI_131_DATA + DDRSS0_PI_132_DATA + DDRSS0_PI_133_DATA + DDRSS0_PI_134_DATA + DDRSS0_PI_135_DATA + DDRSS0_PI_136_DATA + DDRSS0_PI_137_DATA + DDRSS0_PI_138_DATA + DDRSS0_PI_139_DATA + DDRSS0_PI_140_DATA + DDRSS0_PI_141_DATA + DDRSS0_PI_142_DATA + DDRSS0_PI_143_DATA + DDRSS0_PI_144_DATA + DDRSS0_PI_145_DATA + DDRSS0_PI_146_DATA + DDRSS0_PI_147_DATA + DDRSS0_PI_148_DATA + DDRSS0_PI_149_DATA + DDRSS0_PI_150_DATA + DDRSS0_PI_151_DATA + DDRSS0_PI_152_DATA + DDRSS0_PI_153_DATA + DDRSS0_PI_154_DATA + DDRSS0_PI_155_DATA + DDRSS0_PI_156_DATA + DDRSS0_PI_157_DATA + DDRSS0_PI_158_DATA + DDRSS0_PI_159_DATA + DDRSS0_PI_160_DATA + DDRSS0_PI_161_DATA + DDRSS0_PI_162_DATA + DDRSS0_PI_163_DATA + DDRSS0_PI_164_DATA + DDRSS0_PI_165_DATA + DDRSS0_PI_166_DATA + DDRSS0_PI_167_DATA + DDRSS0_PI_168_DATA + DDRSS0_PI_169_DATA + DDRSS0_PI_170_DATA + DDRSS0_PI_171_DATA + DDRSS0_PI_172_DATA + DDRSS0_PI_173_DATA + DDRSS0_PI_174_DATA + DDRSS0_PI_175_DATA + DDRSS0_PI_176_DATA + DDRSS0_PI_177_DATA + DDRSS0_PI_178_DATA + DDRSS0_PI_179_DATA + DDRSS0_PI_180_DATA + DDRSS0_PI_181_DATA + DDRSS0_PI_182_DATA + DDRSS0_PI_183_DATA + DDRSS0_PI_184_DATA + DDRSS0_PI_185_DATA + DDRSS0_PI_186_DATA + DDRSS0_PI_187_DATA + DDRSS0_PI_188_DATA + DDRSS0_PI_189_DATA + DDRSS0_PI_190_DATA + DDRSS0_PI_191_DATA + DDRSS0_PI_192_DATA + DDRSS0_PI_193_DATA + DDRSS0_PI_194_DATA + DDRSS0_PI_195_DATA + DDRSS0_PI_196_DATA + DDRSS0_PI_197_DATA + DDRSS0_PI_198_DATA + DDRSS0_PI_199_DATA + DDRSS0_PI_200_DATA + DDRSS0_PI_201_DATA + DDRSS0_PI_202_DATA + DDRSS0_PI_203_DATA + DDRSS0_PI_204_DATA + DDRSS0_PI_205_DATA + DDRSS0_PI_206_DATA + DDRSS0_PI_207_DATA + DDRSS0_PI_208_DATA + DDRSS0_PI_209_DATA + DDRSS0_PI_210_DATA + DDRSS0_PI_211_DATA + DDRSS0_PI_212_DATA + DDRSS0_PI_213_DATA + DDRSS0_PI_214_DATA + DDRSS0_PI_215_DATA + DDRSS0_PI_216_DATA + DDRSS0_PI_217_DATA + DDRSS0_PI_218_DATA + DDRSS0_PI_219_DATA + DDRSS0_PI_220_DATA + DDRSS0_PI_221_DATA + DDRSS0_PI_222_DATA + DDRSS0_PI_223_DATA + DDRSS0_PI_224_DATA + DDRSS0_PI_225_DATA + DDRSS0_PI_226_DATA + DDRSS0_PI_227_DATA + DDRSS0_PI_228_DATA + DDRSS0_PI_229_DATA + DDRSS0_PI_230_DATA + DDRSS0_PI_231_DATA + DDRSS0_PI_232_DATA + DDRSS0_PI_233_DATA + DDRSS0_PI_234_DATA + DDRSS0_PI_235_DATA + DDRSS0_PI_236_DATA + DDRSS0_PI_237_DATA + DDRSS0_PI_238_DATA + DDRSS0_PI_239_DATA + DDRSS0_PI_240_DATA + DDRSS0_PI_241_DATA + DDRSS0_PI_242_DATA + DDRSS0_PI_243_DATA + DDRSS0_PI_244_DATA + DDRSS0_PI_245_DATA + DDRSS0_PI_246_DATA + DDRSS0_PI_247_DATA + DDRSS0_PI_248_DATA + DDRSS0_PI_249_DATA + DDRSS0_PI_250_DATA + DDRSS0_PI_251_DATA + DDRSS0_PI_252_DATA + DDRSS0_PI_253_DATA + DDRSS0_PI_254_DATA + DDRSS0_PI_255_DATA + DDRSS0_PI_256_DATA + DDRSS0_PI_257_DATA + DDRSS0_PI_258_DATA + DDRSS0_PI_259_DATA + DDRSS0_PI_260_DATA + DDRSS0_PI_261_DATA + DDRSS0_PI_262_DATA + DDRSS0_PI_263_DATA + DDRSS0_PI_264_DATA + DDRSS0_PI_265_DATA + DDRSS0_PI_266_DATA + DDRSS0_PI_267_DATA + DDRSS0_PI_268_DATA + DDRSS0_PI_269_DATA + DDRSS0_PI_270_DATA + DDRSS0_PI_271_DATA + DDRSS0_PI_272_DATA + DDRSS0_PI_273_DATA + DDRSS0_PI_274_DATA + DDRSS0_PI_275_DATA + DDRSS0_PI_276_DATA + DDRSS0_PI_277_DATA + DDRSS0_PI_278_DATA + DDRSS0_PI_279_DATA + DDRSS0_PI_280_DATA + DDRSS0_PI_281_DATA + DDRSS0_PI_282_DATA + DDRSS0_PI_283_DATA + DDRSS0_PI_284_DATA + DDRSS0_PI_285_DATA + DDRSS0_PI_286_DATA + DDRSS0_PI_287_DATA + DDRSS0_PI_288_DATA + DDRSS0_PI_289_DATA + DDRSS0_PI_290_DATA + DDRSS0_PI_291_DATA + DDRSS0_PI_292_DATA + DDRSS0_PI_293_DATA + DDRSS0_PI_294_DATA + DDRSS0_PI_295_DATA + DDRSS0_PI_296_DATA + DDRSS0_PI_297_DATA + DDRSS0_PI_298_DATA + DDRSS0_PI_299_DATA + >; + + ti,phy-data = < + DDRSS0_PHY_00_DATA + DDRSS0_PHY_01_DATA + DDRSS0_PHY_02_DATA + DDRSS0_PHY_03_DATA + DDRSS0_PHY_04_DATA + DDRSS0_PHY_05_DATA + DDRSS0_PHY_06_DATA + DDRSS0_PHY_07_DATA + DDRSS0_PHY_08_DATA + DDRSS0_PHY_09_DATA + DDRSS0_PHY_10_DATA + DDRSS0_PHY_11_DATA + DDRSS0_PHY_12_DATA + DDRSS0_PHY_13_DATA + DDRSS0_PHY_14_DATA + DDRSS0_PHY_15_DATA + DDRSS0_PHY_16_DATA + DDRSS0_PHY_17_DATA + DDRSS0_PHY_18_DATA + DDRSS0_PHY_19_DATA + DDRSS0_PHY_20_DATA + DDRSS0_PHY_21_DATA + DDRSS0_PHY_22_DATA + DDRSS0_PHY_23_DATA + DDRSS0_PHY_24_DATA + DDRSS0_PHY_25_DATA + DDRSS0_PHY_26_DATA + DDRSS0_PHY_27_DATA + DDRSS0_PHY_28_DATA + DDRSS0_PHY_29_DATA + DDRSS0_PHY_30_DATA + DDRSS0_PHY_31_DATA + DDRSS0_PHY_32_DATA + DDRSS0_PHY_33_DATA + DDRSS0_PHY_34_DATA + DDRSS0_PHY_35_DATA + DDRSS0_PHY_36_DATA + DDRSS0_PHY_37_DATA + DDRSS0_PHY_38_DATA + DDRSS0_PHY_39_DATA + DDRSS0_PHY_40_DATA + DDRSS0_PHY_41_DATA + DDRSS0_PHY_42_DATA + DDRSS0_PHY_43_DATA + DDRSS0_PHY_44_DATA + DDRSS0_PHY_45_DATA + DDRSS0_PHY_46_DATA + DDRSS0_PHY_47_DATA + DDRSS0_PHY_48_DATA + DDRSS0_PHY_49_DATA + DDRSS0_PHY_50_DATA + DDRSS0_PHY_51_DATA + DDRSS0_PHY_52_DATA + DDRSS0_PHY_53_DATA + DDRSS0_PHY_54_DATA + DDRSS0_PHY_55_DATA + DDRSS0_PHY_56_DATA + DDRSS0_PHY_57_DATA + DDRSS0_PHY_58_DATA + DDRSS0_PHY_59_DATA + DDRSS0_PHY_60_DATA + DDRSS0_PHY_61_DATA + DDRSS0_PHY_62_DATA + DDRSS0_PHY_63_DATA + DDRSS0_PHY_64_DATA + DDRSS0_PHY_65_DATA + DDRSS0_PHY_66_DATA + DDRSS0_PHY_67_DATA + DDRSS0_PHY_68_DATA + DDRSS0_PHY_69_DATA + DDRSS0_PHY_70_DATA + DDRSS0_PHY_71_DATA + DDRSS0_PHY_72_DATA + DDRSS0_PHY_73_DATA + DDRSS0_PHY_74_DATA + DDRSS0_PHY_75_DATA + DDRSS0_PHY_76_DATA + DDRSS0_PHY_77_DATA + DDRSS0_PHY_78_DATA + DDRSS0_PHY_79_DATA + DDRSS0_PHY_80_DATA + DDRSS0_PHY_81_DATA + DDRSS0_PHY_82_DATA + DDRSS0_PHY_83_DATA + DDRSS0_PHY_84_DATA + DDRSS0_PHY_85_DATA + DDRSS0_PHY_86_DATA + DDRSS0_PHY_87_DATA + DDRSS0_PHY_88_DATA + DDRSS0_PHY_89_DATA + DDRSS0_PHY_90_DATA + DDRSS0_PHY_91_DATA + DDRSS0_PHY_92_DATA + DDRSS0_PHY_93_DATA + DDRSS0_PHY_94_DATA + DDRSS0_PHY_95_DATA + DDRSS0_PHY_96_DATA + DDRSS0_PHY_97_DATA + DDRSS0_PHY_98_DATA + DDRSS0_PHY_99_DATA + DDRSS0_PHY_100_DATA + DDRSS0_PHY_101_DATA + DDRSS0_PHY_102_DATA + DDRSS0_PHY_103_DATA + DDRSS0_PHY_104_DATA + DDRSS0_PHY_105_DATA + DDRSS0_PHY_106_DATA + DDRSS0_PHY_107_DATA + DDRSS0_PHY_108_DATA + DDRSS0_PHY_109_DATA + DDRSS0_PHY_110_DATA + DDRSS0_PHY_111_DATA + DDRSS0_PHY_112_DATA + DDRSS0_PHY_113_DATA + DDRSS0_PHY_114_DATA + DDRSS0_PHY_115_DATA + DDRSS0_PHY_116_DATA + DDRSS0_PHY_117_DATA + DDRSS0_PHY_118_DATA + DDRSS0_PHY_119_DATA + DDRSS0_PHY_120_DATA + DDRSS0_PHY_121_DATA + DDRSS0_PHY_122_DATA + DDRSS0_PHY_123_DATA + DDRSS0_PHY_124_DATA + DDRSS0_PHY_125_DATA + DDRSS0_PHY_126_DATA + DDRSS0_PHY_127_DATA + DDRSS0_PHY_128_DATA + DDRSS0_PHY_129_DATA + DDRSS0_PHY_130_DATA + DDRSS0_PHY_131_DATA + DDRSS0_PHY_132_DATA + DDRSS0_PHY_133_DATA + DDRSS0_PHY_134_DATA + DDRSS0_PHY_135_DATA + DDRSS0_PHY_136_DATA + DDRSS0_PHY_137_DATA + DDRSS0_PHY_138_DATA + DDRSS0_PHY_139_DATA + DDRSS0_PHY_140_DATA + DDRSS0_PHY_141_DATA + DDRSS0_PHY_142_DATA + DDRSS0_PHY_143_DATA + DDRSS0_PHY_144_DATA + DDRSS0_PHY_145_DATA + DDRSS0_PHY_146_DATA + DDRSS0_PHY_147_DATA + DDRSS0_PHY_148_DATA + DDRSS0_PHY_149_DATA + DDRSS0_PHY_150_DATA + DDRSS0_PHY_151_DATA + DDRSS0_PHY_152_DATA + DDRSS0_PHY_153_DATA + DDRSS0_PHY_154_DATA + DDRSS0_PHY_155_DATA + DDRSS0_PHY_156_DATA + DDRSS0_PHY_157_DATA + DDRSS0_PHY_158_DATA + DDRSS0_PHY_159_DATA + DDRSS0_PHY_160_DATA + DDRSS0_PHY_161_DATA + DDRSS0_PHY_162_DATA + DDRSS0_PHY_163_DATA + DDRSS0_PHY_164_DATA + DDRSS0_PHY_165_DATA + DDRSS0_PHY_166_DATA + DDRSS0_PHY_167_DATA + DDRSS0_PHY_168_DATA + DDRSS0_PHY_169_DATA + DDRSS0_PHY_170_DATA + DDRSS0_PHY_171_DATA + DDRSS0_PHY_172_DATA + DDRSS0_PHY_173_DATA + DDRSS0_PHY_174_DATA + DDRSS0_PHY_175_DATA + DDRSS0_PHY_176_DATA + DDRSS0_PHY_177_DATA + DDRSS0_PHY_178_DATA + DDRSS0_PHY_179_DATA + DDRSS0_PHY_180_DATA + DDRSS0_PHY_181_DATA + DDRSS0_PHY_182_DATA + DDRSS0_PHY_183_DATA + DDRSS0_PHY_184_DATA + DDRSS0_PHY_185_DATA + DDRSS0_PHY_186_DATA + DDRSS0_PHY_187_DATA + DDRSS0_PHY_188_DATA + DDRSS0_PHY_189_DATA + DDRSS0_PHY_190_DATA + DDRSS0_PHY_191_DATA + DDRSS0_PHY_192_DATA + DDRSS0_PHY_193_DATA + DDRSS0_PHY_194_DATA + DDRSS0_PHY_195_DATA + DDRSS0_PHY_196_DATA + DDRSS0_PHY_197_DATA + DDRSS0_PHY_198_DATA + DDRSS0_PHY_199_DATA + DDRSS0_PHY_200_DATA + DDRSS0_PHY_201_DATA + DDRSS0_PHY_202_DATA + DDRSS0_PHY_203_DATA + DDRSS0_PHY_204_DATA + DDRSS0_PHY_205_DATA + DDRSS0_PHY_206_DATA + DDRSS0_PHY_207_DATA + DDRSS0_PHY_208_DATA + DDRSS0_PHY_209_DATA + DDRSS0_PHY_210_DATA + DDRSS0_PHY_211_DATA + DDRSS0_PHY_212_DATA + DDRSS0_PHY_213_DATA + DDRSS0_PHY_214_DATA + DDRSS0_PHY_215_DATA + DDRSS0_PHY_216_DATA + DDRSS0_PHY_217_DATA + DDRSS0_PHY_218_DATA + DDRSS0_PHY_219_DATA + DDRSS0_PHY_220_DATA + DDRSS0_PHY_221_DATA + DDRSS0_PHY_222_DATA + DDRSS0_PHY_223_DATA + DDRSS0_PHY_224_DATA + DDRSS0_PHY_225_DATA + DDRSS0_PHY_226_DATA + DDRSS0_PHY_227_DATA + DDRSS0_PHY_228_DATA + DDRSS0_PHY_229_DATA + DDRSS0_PHY_230_DATA + DDRSS0_PHY_231_DATA + DDRSS0_PHY_232_DATA + DDRSS0_PHY_233_DATA + DDRSS0_PHY_234_DATA + DDRSS0_PHY_235_DATA + DDRSS0_PHY_236_DATA + DDRSS0_PHY_237_DATA + DDRSS0_PHY_238_DATA + DDRSS0_PHY_239_DATA + DDRSS0_PHY_240_DATA + DDRSS0_PHY_241_DATA + DDRSS0_PHY_242_DATA + DDRSS0_PHY_243_DATA + DDRSS0_PHY_244_DATA + DDRSS0_PHY_245_DATA + DDRSS0_PHY_246_DATA + DDRSS0_PHY_247_DATA + DDRSS0_PHY_248_DATA + DDRSS0_PHY_249_DATA + DDRSS0_PHY_250_DATA + DDRSS0_PHY_251_DATA + DDRSS0_PHY_252_DATA + DDRSS0_PHY_253_DATA + DDRSS0_PHY_254_DATA + DDRSS0_PHY_255_DATA + DDRSS0_PHY_256_DATA + DDRSS0_PHY_257_DATA + DDRSS0_PHY_258_DATA + DDRSS0_PHY_259_DATA + DDRSS0_PHY_260_DATA + DDRSS0_PHY_261_DATA + DDRSS0_PHY_262_DATA + DDRSS0_PHY_263_DATA + DDRSS0_PHY_264_DATA + DDRSS0_PHY_265_DATA + DDRSS0_PHY_266_DATA + DDRSS0_PHY_267_DATA + DDRSS0_PHY_268_DATA + DDRSS0_PHY_269_DATA + DDRSS0_PHY_270_DATA + DDRSS0_PHY_271_DATA + DDRSS0_PHY_272_DATA + DDRSS0_PHY_273_DATA + DDRSS0_PHY_274_DATA + DDRSS0_PHY_275_DATA + DDRSS0_PHY_276_DATA + DDRSS0_PHY_277_DATA + DDRSS0_PHY_278_DATA + DDRSS0_PHY_279_DATA + DDRSS0_PHY_280_DATA + DDRSS0_PHY_281_DATA + DDRSS0_PHY_282_DATA + DDRSS0_PHY_283_DATA + DDRSS0_PHY_284_DATA + DDRSS0_PHY_285_DATA + DDRSS0_PHY_286_DATA + DDRSS0_PHY_287_DATA + DDRSS0_PHY_288_DATA + DDRSS0_PHY_289_DATA + DDRSS0_PHY_290_DATA + DDRSS0_PHY_291_DATA + DDRSS0_PHY_292_DATA + DDRSS0_PHY_293_DATA + DDRSS0_PHY_294_DATA + DDRSS0_PHY_295_DATA + DDRSS0_PHY_296_DATA + DDRSS0_PHY_297_DATA + DDRSS0_PHY_298_DATA + DDRSS0_PHY_299_DATA + DDRSS0_PHY_300_DATA + DDRSS0_PHY_301_DATA + DDRSS0_PHY_302_DATA + DDRSS0_PHY_303_DATA + DDRSS0_PHY_304_DATA + DDRSS0_PHY_305_DATA + DDRSS0_PHY_306_DATA + DDRSS0_PHY_307_DATA + DDRSS0_PHY_308_DATA + DDRSS0_PHY_309_DATA + DDRSS0_PHY_310_DATA + DDRSS0_PHY_311_DATA + DDRSS0_PHY_312_DATA + DDRSS0_PHY_313_DATA + DDRSS0_PHY_314_DATA + DDRSS0_PHY_315_DATA + DDRSS0_PHY_316_DATA + DDRSS0_PHY_317_DATA + DDRSS0_PHY_318_DATA + DDRSS0_PHY_319_DATA + DDRSS0_PHY_320_DATA + DDRSS0_PHY_321_DATA + DDRSS0_PHY_322_DATA + DDRSS0_PHY_323_DATA + DDRSS0_PHY_324_DATA + DDRSS0_PHY_325_DATA + DDRSS0_PHY_326_DATA + DDRSS0_PHY_327_DATA + DDRSS0_PHY_328_DATA + DDRSS0_PHY_329_DATA + DDRSS0_PHY_330_DATA + DDRSS0_PHY_331_DATA + DDRSS0_PHY_332_DATA + DDRSS0_PHY_333_DATA + DDRSS0_PHY_334_DATA + DDRSS0_PHY_335_DATA + DDRSS0_PHY_336_DATA + DDRSS0_PHY_337_DATA + DDRSS0_PHY_338_DATA + DDRSS0_PHY_339_DATA + DDRSS0_PHY_340_DATA + DDRSS0_PHY_341_DATA + DDRSS0_PHY_342_DATA + DDRSS0_PHY_343_DATA + DDRSS0_PHY_344_DATA + DDRSS0_PHY_345_DATA + DDRSS0_PHY_346_DATA + DDRSS0_PHY_347_DATA + DDRSS0_PHY_348_DATA + DDRSS0_PHY_349_DATA + DDRSS0_PHY_350_DATA + DDRSS0_PHY_351_DATA + DDRSS0_PHY_352_DATA + DDRSS0_PHY_353_DATA + DDRSS0_PHY_354_DATA + DDRSS0_PHY_355_DATA + DDRSS0_PHY_356_DATA + DDRSS0_PHY_357_DATA + DDRSS0_PHY_358_DATA + DDRSS0_PHY_359_DATA + DDRSS0_PHY_360_DATA + DDRSS0_PHY_361_DATA + DDRSS0_PHY_362_DATA + DDRSS0_PHY_363_DATA + DDRSS0_PHY_364_DATA + DDRSS0_PHY_365_DATA + DDRSS0_PHY_366_DATA + DDRSS0_PHY_367_DATA + DDRSS0_PHY_368_DATA + DDRSS0_PHY_369_DATA + DDRSS0_PHY_370_DATA + DDRSS0_PHY_371_DATA + DDRSS0_PHY_372_DATA + DDRSS0_PHY_373_DATA + DDRSS0_PHY_374_DATA + DDRSS0_PHY_375_DATA + DDRSS0_PHY_376_DATA + DDRSS0_PHY_377_DATA + DDRSS0_PHY_378_DATA + DDRSS0_PHY_379_DATA + DDRSS0_PHY_380_DATA + DDRSS0_PHY_381_DATA + DDRSS0_PHY_382_DATA + DDRSS0_PHY_383_DATA + DDRSS0_PHY_384_DATA + DDRSS0_PHY_385_DATA + DDRSS0_PHY_386_DATA + DDRSS0_PHY_387_DATA + DDRSS0_PHY_388_DATA + DDRSS0_PHY_389_DATA + DDRSS0_PHY_390_DATA + DDRSS0_PHY_391_DATA + DDRSS0_PHY_392_DATA + DDRSS0_PHY_393_DATA + DDRSS0_PHY_394_DATA + DDRSS0_PHY_395_DATA + DDRSS0_PHY_396_DATA + DDRSS0_PHY_397_DATA + DDRSS0_PHY_398_DATA + DDRSS0_PHY_399_DATA + DDRSS0_PHY_400_DATA + DDRSS0_PHY_401_DATA + DDRSS0_PHY_402_DATA + DDRSS0_PHY_403_DATA + DDRSS0_PHY_404_DATA + DDRSS0_PHY_405_DATA + DDRSS0_PHY_406_DATA + DDRSS0_PHY_407_DATA + DDRSS0_PHY_408_DATA + DDRSS0_PHY_409_DATA + DDRSS0_PHY_410_DATA + DDRSS0_PHY_411_DATA + DDRSS0_PHY_412_DATA + DDRSS0_PHY_413_DATA + DDRSS0_PHY_414_DATA + DDRSS0_PHY_415_DATA + DDRSS0_PHY_416_DATA + DDRSS0_PHY_417_DATA + DDRSS0_PHY_418_DATA + DDRSS0_PHY_419_DATA + DDRSS0_PHY_420_DATA + DDRSS0_PHY_421_DATA + DDRSS0_PHY_422_DATA + DDRSS0_PHY_423_DATA + DDRSS0_PHY_424_DATA + DDRSS0_PHY_425_DATA + DDRSS0_PHY_426_DATA + DDRSS0_PHY_427_DATA + DDRSS0_PHY_428_DATA + DDRSS0_PHY_429_DATA + DDRSS0_PHY_430_DATA + DDRSS0_PHY_431_DATA + DDRSS0_PHY_432_DATA + DDRSS0_PHY_433_DATA + DDRSS0_PHY_434_DATA + DDRSS0_PHY_435_DATA + DDRSS0_PHY_436_DATA + DDRSS0_PHY_437_DATA + DDRSS0_PHY_438_DATA + DDRSS0_PHY_439_DATA + DDRSS0_PHY_440_DATA + DDRSS0_PHY_441_DATA + DDRSS0_PHY_442_DATA + DDRSS0_PHY_443_DATA + DDRSS0_PHY_444_DATA + DDRSS0_PHY_445_DATA + DDRSS0_PHY_446_DATA + DDRSS0_PHY_447_DATA + DDRSS0_PHY_448_DATA + DDRSS0_PHY_449_DATA + DDRSS0_PHY_450_DATA + DDRSS0_PHY_451_DATA + DDRSS0_PHY_452_DATA + DDRSS0_PHY_453_DATA + DDRSS0_PHY_454_DATA + DDRSS0_PHY_455_DATA + DDRSS0_PHY_456_DATA + DDRSS0_PHY_457_DATA + DDRSS0_PHY_458_DATA + DDRSS0_PHY_459_DATA + DDRSS0_PHY_460_DATA + DDRSS0_PHY_461_DATA + DDRSS0_PHY_462_DATA + DDRSS0_PHY_463_DATA + DDRSS0_PHY_464_DATA + DDRSS0_PHY_465_DATA + DDRSS0_PHY_466_DATA + DDRSS0_PHY_467_DATA + DDRSS0_PHY_468_DATA + DDRSS0_PHY_469_DATA + DDRSS0_PHY_470_DATA + DDRSS0_PHY_471_DATA + DDRSS0_PHY_472_DATA + DDRSS0_PHY_473_DATA + DDRSS0_PHY_474_DATA + DDRSS0_PHY_475_DATA + DDRSS0_PHY_476_DATA + DDRSS0_PHY_477_DATA + DDRSS0_PHY_478_DATA + DDRSS0_PHY_479_DATA + DDRSS0_PHY_480_DATA + DDRSS0_PHY_481_DATA + DDRSS0_PHY_482_DATA + DDRSS0_PHY_483_DATA + DDRSS0_PHY_484_DATA + DDRSS0_PHY_485_DATA + DDRSS0_PHY_486_DATA + DDRSS0_PHY_487_DATA + DDRSS0_PHY_488_DATA + DDRSS0_PHY_489_DATA + DDRSS0_PHY_490_DATA + DDRSS0_PHY_491_DATA + DDRSS0_PHY_492_DATA + DDRSS0_PHY_493_DATA + DDRSS0_PHY_494_DATA + DDRSS0_PHY_495_DATA + DDRSS0_PHY_496_DATA + DDRSS0_PHY_497_DATA + DDRSS0_PHY_498_DATA + DDRSS0_PHY_499_DATA + DDRSS0_PHY_500_DATA + DDRSS0_PHY_501_DATA + DDRSS0_PHY_502_DATA + DDRSS0_PHY_503_DATA + DDRSS0_PHY_504_DATA + DDRSS0_PHY_505_DATA + DDRSS0_PHY_506_DATA + DDRSS0_PHY_507_DATA + DDRSS0_PHY_508_DATA + DDRSS0_PHY_509_DATA + DDRSS0_PHY_510_DATA + DDRSS0_PHY_511_DATA + DDRSS0_PHY_512_DATA + DDRSS0_PHY_513_DATA + DDRSS0_PHY_514_DATA + DDRSS0_PHY_515_DATA + DDRSS0_PHY_516_DATA + DDRSS0_PHY_517_DATA + DDRSS0_PHY_518_DATA + DDRSS0_PHY_519_DATA + DDRSS0_PHY_520_DATA + DDRSS0_PHY_521_DATA + DDRSS0_PHY_522_DATA + DDRSS0_PHY_523_DATA + DDRSS0_PHY_524_DATA + DDRSS0_PHY_525_DATA + DDRSS0_PHY_526_DATA + DDRSS0_PHY_527_DATA + DDRSS0_PHY_528_DATA + DDRSS0_PHY_529_DATA + DDRSS0_PHY_530_DATA + DDRSS0_PHY_531_DATA + DDRSS0_PHY_532_DATA + DDRSS0_PHY_533_DATA + DDRSS0_PHY_534_DATA + DDRSS0_PHY_535_DATA + DDRSS0_PHY_536_DATA + DDRSS0_PHY_537_DATA + DDRSS0_PHY_538_DATA + DDRSS0_PHY_539_DATA + DDRSS0_PHY_540_DATA + DDRSS0_PHY_541_DATA + DDRSS0_PHY_542_DATA + DDRSS0_PHY_543_DATA + DDRSS0_PHY_544_DATA + DDRSS0_PHY_545_DATA + DDRSS0_PHY_546_DATA + DDRSS0_PHY_547_DATA + DDRSS0_PHY_548_DATA + DDRSS0_PHY_549_DATA + DDRSS0_PHY_550_DATA + DDRSS0_PHY_551_DATA + DDRSS0_PHY_552_DATA + DDRSS0_PHY_553_DATA + DDRSS0_PHY_554_DATA + DDRSS0_PHY_555_DATA + DDRSS0_PHY_556_DATA + DDRSS0_PHY_557_DATA + DDRSS0_PHY_558_DATA + DDRSS0_PHY_559_DATA + DDRSS0_PHY_560_DATA + DDRSS0_PHY_561_DATA + DDRSS0_PHY_562_DATA + DDRSS0_PHY_563_DATA + DDRSS0_PHY_564_DATA + DDRSS0_PHY_565_DATA + DDRSS0_PHY_566_DATA + DDRSS0_PHY_567_DATA + DDRSS0_PHY_568_DATA + DDRSS0_PHY_569_DATA + DDRSS0_PHY_570_DATA + DDRSS0_PHY_571_DATA + DDRSS0_PHY_572_DATA + DDRSS0_PHY_573_DATA + DDRSS0_PHY_574_DATA + DDRSS0_PHY_575_DATA + DDRSS0_PHY_576_DATA + DDRSS0_PHY_577_DATA + DDRSS0_PHY_578_DATA + DDRSS0_PHY_579_DATA + DDRSS0_PHY_580_DATA + DDRSS0_PHY_581_DATA + DDRSS0_PHY_582_DATA + DDRSS0_PHY_583_DATA + DDRSS0_PHY_584_DATA + DDRSS0_PHY_585_DATA + DDRSS0_PHY_586_DATA + DDRSS0_PHY_587_DATA + DDRSS0_PHY_588_DATA + DDRSS0_PHY_589_DATA + DDRSS0_PHY_590_DATA + DDRSS0_PHY_591_DATA + DDRSS0_PHY_592_DATA + DDRSS0_PHY_593_DATA + DDRSS0_PHY_594_DATA + DDRSS0_PHY_595_DATA + DDRSS0_PHY_596_DATA + DDRSS0_PHY_597_DATA + DDRSS0_PHY_598_DATA + DDRSS0_PHY_599_DATA + DDRSS0_PHY_600_DATA + DDRSS0_PHY_601_DATA + DDRSS0_PHY_602_DATA + DDRSS0_PHY_603_DATA + DDRSS0_PHY_604_DATA + DDRSS0_PHY_605_DATA + DDRSS0_PHY_606_DATA + DDRSS0_PHY_607_DATA + DDRSS0_PHY_608_DATA + DDRSS0_PHY_609_DATA + DDRSS0_PHY_610_DATA + DDRSS0_PHY_611_DATA + DDRSS0_PHY_612_DATA + DDRSS0_PHY_613_DATA + DDRSS0_PHY_614_DATA + DDRSS0_PHY_615_DATA + DDRSS0_PHY_616_DATA + DDRSS0_PHY_617_DATA + DDRSS0_PHY_618_DATA + DDRSS0_PHY_619_DATA + DDRSS0_PHY_620_DATA + DDRSS0_PHY_621_DATA + DDRSS0_PHY_622_DATA + DDRSS0_PHY_623_DATA + DDRSS0_PHY_624_DATA + DDRSS0_PHY_625_DATA + DDRSS0_PHY_626_DATA + DDRSS0_PHY_627_DATA + DDRSS0_PHY_628_DATA + DDRSS0_PHY_629_DATA + DDRSS0_PHY_630_DATA + DDRSS0_PHY_631_DATA + DDRSS0_PHY_632_DATA + DDRSS0_PHY_633_DATA + DDRSS0_PHY_634_DATA + DDRSS0_PHY_635_DATA + DDRSS0_PHY_636_DATA + DDRSS0_PHY_637_DATA + DDRSS0_PHY_638_DATA + DDRSS0_PHY_639_DATA + DDRSS0_PHY_640_DATA + DDRSS0_PHY_641_DATA + DDRSS0_PHY_642_DATA + DDRSS0_PHY_643_DATA + DDRSS0_PHY_644_DATA + DDRSS0_PHY_645_DATA + DDRSS0_PHY_646_DATA + DDRSS0_PHY_647_DATA + DDRSS0_PHY_648_DATA + DDRSS0_PHY_649_DATA + DDRSS0_PHY_650_DATA + DDRSS0_PHY_651_DATA + DDRSS0_PHY_652_DATA + DDRSS0_PHY_653_DATA + DDRSS0_PHY_654_DATA + DDRSS0_PHY_655_DATA + DDRSS0_PHY_656_DATA + DDRSS0_PHY_657_DATA + DDRSS0_PHY_658_DATA + DDRSS0_PHY_659_DATA + DDRSS0_PHY_660_DATA + DDRSS0_PHY_661_DATA + DDRSS0_PHY_662_DATA + DDRSS0_PHY_663_DATA + DDRSS0_PHY_664_DATA + DDRSS0_PHY_665_DATA + DDRSS0_PHY_666_DATA + DDRSS0_PHY_667_DATA + DDRSS0_PHY_668_DATA + DDRSS0_PHY_669_DATA + DDRSS0_PHY_670_DATA + DDRSS0_PHY_671_DATA + DDRSS0_PHY_672_DATA + DDRSS0_PHY_673_DATA + DDRSS0_PHY_674_DATA + DDRSS0_PHY_675_DATA + DDRSS0_PHY_676_DATA + DDRSS0_PHY_677_DATA + DDRSS0_PHY_678_DATA + DDRSS0_PHY_679_DATA + DDRSS0_PHY_680_DATA + DDRSS0_PHY_681_DATA + DDRSS0_PHY_682_DATA + DDRSS0_PHY_683_DATA + DDRSS0_PHY_684_DATA + DDRSS0_PHY_685_DATA + DDRSS0_PHY_686_DATA + DDRSS0_PHY_687_DATA + DDRSS0_PHY_688_DATA + DDRSS0_PHY_689_DATA + DDRSS0_PHY_690_DATA + DDRSS0_PHY_691_DATA + DDRSS0_PHY_692_DATA + DDRSS0_PHY_693_DATA + DDRSS0_PHY_694_DATA + DDRSS0_PHY_695_DATA + DDRSS0_PHY_696_DATA + DDRSS0_PHY_697_DATA + DDRSS0_PHY_698_DATA + DDRSS0_PHY_699_DATA + DDRSS0_PHY_700_DATA + DDRSS0_PHY_701_DATA + DDRSS0_PHY_702_DATA + DDRSS0_PHY_703_DATA + DDRSS0_PHY_704_DATA + DDRSS0_PHY_705_DATA + DDRSS0_PHY_706_DATA + DDRSS0_PHY_707_DATA + DDRSS0_PHY_708_DATA + DDRSS0_PHY_709_DATA + DDRSS0_PHY_710_DATA + DDRSS0_PHY_711_DATA + DDRSS0_PHY_712_DATA + DDRSS0_PHY_713_DATA + DDRSS0_PHY_714_DATA + DDRSS0_PHY_715_DATA + DDRSS0_PHY_716_DATA + DDRSS0_PHY_717_DATA + DDRSS0_PHY_718_DATA + DDRSS0_PHY_719_DATA + DDRSS0_PHY_720_DATA + DDRSS0_PHY_721_DATA + DDRSS0_PHY_722_DATA + DDRSS0_PHY_723_DATA + DDRSS0_PHY_724_DATA + DDRSS0_PHY_725_DATA + DDRSS0_PHY_726_DATA + DDRSS0_PHY_727_DATA + DDRSS0_PHY_728_DATA + DDRSS0_PHY_729_DATA + DDRSS0_PHY_730_DATA + DDRSS0_PHY_731_DATA + DDRSS0_PHY_732_DATA + DDRSS0_PHY_733_DATA + DDRSS0_PHY_734_DATA + DDRSS0_PHY_735_DATA + DDRSS0_PHY_736_DATA + DDRSS0_PHY_737_DATA + DDRSS0_PHY_738_DATA + DDRSS0_PHY_739_DATA + DDRSS0_PHY_740_DATA + DDRSS0_PHY_741_DATA + DDRSS0_PHY_742_DATA + DDRSS0_PHY_743_DATA + DDRSS0_PHY_744_DATA + DDRSS0_PHY_745_DATA + DDRSS0_PHY_746_DATA + DDRSS0_PHY_747_DATA + DDRSS0_PHY_748_DATA + DDRSS0_PHY_749_DATA + DDRSS0_PHY_750_DATA + DDRSS0_PHY_751_DATA + DDRSS0_PHY_752_DATA + DDRSS0_PHY_753_DATA + DDRSS0_PHY_754_DATA + DDRSS0_PHY_755_DATA + DDRSS0_PHY_756_DATA + DDRSS0_PHY_757_DATA + DDRSS0_PHY_758_DATA + DDRSS0_PHY_759_DATA + DDRSS0_PHY_760_DATA + DDRSS0_PHY_761_DATA + DDRSS0_PHY_762_DATA + DDRSS0_PHY_763_DATA + DDRSS0_PHY_764_DATA + DDRSS0_PHY_765_DATA + DDRSS0_PHY_766_DATA + DDRSS0_PHY_767_DATA + DDRSS0_PHY_768_DATA + DDRSS0_PHY_769_DATA + DDRSS0_PHY_770_DATA + DDRSS0_PHY_771_DATA + DDRSS0_PHY_772_DATA + DDRSS0_PHY_773_DATA + DDRSS0_PHY_774_DATA + DDRSS0_PHY_775_DATA + DDRSS0_PHY_776_DATA + DDRSS0_PHY_777_DATA + DDRSS0_PHY_778_DATA + DDRSS0_PHY_779_DATA + DDRSS0_PHY_780_DATA + DDRSS0_PHY_781_DATA + DDRSS0_PHY_782_DATA + DDRSS0_PHY_783_DATA + DDRSS0_PHY_784_DATA + DDRSS0_PHY_785_DATA + DDRSS0_PHY_786_DATA + DDRSS0_PHY_787_DATA + DDRSS0_PHY_788_DATA + DDRSS0_PHY_789_DATA + DDRSS0_PHY_790_DATA + DDRSS0_PHY_791_DATA + DDRSS0_PHY_792_DATA + DDRSS0_PHY_793_DATA + DDRSS0_PHY_794_DATA + DDRSS0_PHY_795_DATA + DDRSS0_PHY_796_DATA + DDRSS0_PHY_797_DATA + DDRSS0_PHY_798_DATA + DDRSS0_PHY_799_DATA + DDRSS0_PHY_800_DATA + DDRSS0_PHY_801_DATA + DDRSS0_PHY_802_DATA + DDRSS0_PHY_803_DATA + DDRSS0_PHY_804_DATA + DDRSS0_PHY_805_DATA + DDRSS0_PHY_806_DATA + DDRSS0_PHY_807_DATA + DDRSS0_PHY_808_DATA + DDRSS0_PHY_809_DATA + DDRSS0_PHY_810_DATA + DDRSS0_PHY_811_DATA + DDRSS0_PHY_812_DATA + DDRSS0_PHY_813_DATA + DDRSS0_PHY_814_DATA + DDRSS0_PHY_815_DATA + DDRSS0_PHY_816_DATA + DDRSS0_PHY_817_DATA + DDRSS0_PHY_818_DATA + DDRSS0_PHY_819_DATA + DDRSS0_PHY_820_DATA + DDRSS0_PHY_821_DATA + DDRSS0_PHY_822_DATA + DDRSS0_PHY_823_DATA + DDRSS0_PHY_824_DATA + DDRSS0_PHY_825_DATA + DDRSS0_PHY_826_DATA + DDRSS0_PHY_827_DATA + DDRSS0_PHY_828_DATA + DDRSS0_PHY_829_DATA + DDRSS0_PHY_830_DATA + DDRSS0_PHY_831_DATA + DDRSS0_PHY_832_DATA + DDRSS0_PHY_833_DATA + DDRSS0_PHY_834_DATA + DDRSS0_PHY_835_DATA + DDRSS0_PHY_836_DATA + DDRSS0_PHY_837_DATA + DDRSS0_PHY_838_DATA + DDRSS0_PHY_839_DATA + DDRSS0_PHY_840_DATA + DDRSS0_PHY_841_DATA + DDRSS0_PHY_842_DATA + DDRSS0_PHY_843_DATA + DDRSS0_PHY_844_DATA + DDRSS0_PHY_845_DATA + DDRSS0_PHY_846_DATA + DDRSS0_PHY_847_DATA + DDRSS0_PHY_848_DATA + DDRSS0_PHY_849_DATA + DDRSS0_PHY_850_DATA + DDRSS0_PHY_851_DATA + DDRSS0_PHY_852_DATA + DDRSS0_PHY_853_DATA + DDRSS0_PHY_854_DATA + DDRSS0_PHY_855_DATA + DDRSS0_PHY_856_DATA + DDRSS0_PHY_857_DATA + DDRSS0_PHY_858_DATA + DDRSS0_PHY_859_DATA + DDRSS0_PHY_860_DATA + DDRSS0_PHY_861_DATA + DDRSS0_PHY_862_DATA + DDRSS0_PHY_863_DATA + DDRSS0_PHY_864_DATA + DDRSS0_PHY_865_DATA + DDRSS0_PHY_866_DATA + DDRSS0_PHY_867_DATA + DDRSS0_PHY_868_DATA + DDRSS0_PHY_869_DATA + DDRSS0_PHY_870_DATA + DDRSS0_PHY_871_DATA + DDRSS0_PHY_872_DATA + DDRSS0_PHY_873_DATA + DDRSS0_PHY_874_DATA + DDRSS0_PHY_875_DATA + DDRSS0_PHY_876_DATA + DDRSS0_PHY_877_DATA + DDRSS0_PHY_878_DATA + DDRSS0_PHY_879_DATA + DDRSS0_PHY_880_DATA + DDRSS0_PHY_881_DATA + DDRSS0_PHY_882_DATA + DDRSS0_PHY_883_DATA + DDRSS0_PHY_884_DATA + DDRSS0_PHY_885_DATA + DDRSS0_PHY_886_DATA + DDRSS0_PHY_887_DATA + DDRSS0_PHY_888_DATA + DDRSS0_PHY_889_DATA + DDRSS0_PHY_890_DATA + DDRSS0_PHY_891_DATA + DDRSS0_PHY_892_DATA + DDRSS0_PHY_893_DATA + DDRSS0_PHY_894_DATA + DDRSS0_PHY_895_DATA + DDRSS0_PHY_896_DATA + DDRSS0_PHY_897_DATA + DDRSS0_PHY_898_DATA + DDRSS0_PHY_899_DATA + DDRSS0_PHY_900_DATA + DDRSS0_PHY_901_DATA + DDRSS0_PHY_902_DATA + DDRSS0_PHY_903_DATA + DDRSS0_PHY_904_DATA + DDRSS0_PHY_905_DATA + DDRSS0_PHY_906_DATA + DDRSS0_PHY_907_DATA + DDRSS0_PHY_908_DATA + DDRSS0_PHY_909_DATA + DDRSS0_PHY_910_DATA + DDRSS0_PHY_911_DATA + DDRSS0_PHY_912_DATA + DDRSS0_PHY_913_DATA + DDRSS0_PHY_914_DATA + DDRSS0_PHY_915_DATA + DDRSS0_PHY_916_DATA + DDRSS0_PHY_917_DATA + DDRSS0_PHY_918_DATA + DDRSS0_PHY_919_DATA + DDRSS0_PHY_920_DATA + DDRSS0_PHY_921_DATA + DDRSS0_PHY_922_DATA + DDRSS0_PHY_923_DATA + DDRSS0_PHY_924_DATA + DDRSS0_PHY_925_DATA + DDRSS0_PHY_926_DATA + DDRSS0_PHY_927_DATA + DDRSS0_PHY_928_DATA + DDRSS0_PHY_929_DATA + DDRSS0_PHY_930_DATA + DDRSS0_PHY_931_DATA + DDRSS0_PHY_932_DATA + DDRSS0_PHY_933_DATA + DDRSS0_PHY_934_DATA + DDRSS0_PHY_935_DATA + DDRSS0_PHY_936_DATA + DDRSS0_PHY_937_DATA + DDRSS0_PHY_938_DATA + DDRSS0_PHY_939_DATA + DDRSS0_PHY_940_DATA + DDRSS0_PHY_941_DATA + DDRSS0_PHY_942_DATA + DDRSS0_PHY_943_DATA + DDRSS0_PHY_944_DATA + DDRSS0_PHY_945_DATA + DDRSS0_PHY_946_DATA + DDRSS0_PHY_947_DATA + DDRSS0_PHY_948_DATA + DDRSS0_PHY_949_DATA + DDRSS0_PHY_950_DATA + DDRSS0_PHY_951_DATA + DDRSS0_PHY_952_DATA + DDRSS0_PHY_953_DATA + DDRSS0_PHY_954_DATA + DDRSS0_PHY_955_DATA + DDRSS0_PHY_956_DATA + DDRSS0_PHY_957_DATA + DDRSS0_PHY_958_DATA + DDRSS0_PHY_959_DATA + DDRSS0_PHY_960_DATA + DDRSS0_PHY_961_DATA + DDRSS0_PHY_962_DATA + DDRSS0_PHY_963_DATA + DDRSS0_PHY_964_DATA + DDRSS0_PHY_965_DATA + DDRSS0_PHY_966_DATA + DDRSS0_PHY_967_DATA + DDRSS0_PHY_968_DATA + DDRSS0_PHY_969_DATA + DDRSS0_PHY_970_DATA + DDRSS0_PHY_971_DATA + DDRSS0_PHY_972_DATA + DDRSS0_PHY_973_DATA + DDRSS0_PHY_974_DATA + DDRSS0_PHY_975_DATA + DDRSS0_PHY_976_DATA + DDRSS0_PHY_977_DATA + DDRSS0_PHY_978_DATA + DDRSS0_PHY_979_DATA + DDRSS0_PHY_980_DATA + DDRSS0_PHY_981_DATA + DDRSS0_PHY_982_DATA + DDRSS0_PHY_983_DATA + DDRSS0_PHY_984_DATA + DDRSS0_PHY_985_DATA + DDRSS0_PHY_986_DATA + DDRSS0_PHY_987_DATA + DDRSS0_PHY_988_DATA + DDRSS0_PHY_989_DATA + DDRSS0_PHY_990_DATA + DDRSS0_PHY_991_DATA + DDRSS0_PHY_992_DATA + DDRSS0_PHY_993_DATA + DDRSS0_PHY_994_DATA + DDRSS0_PHY_995_DATA + DDRSS0_PHY_996_DATA + DDRSS0_PHY_997_DATA + DDRSS0_PHY_998_DATA + DDRSS0_PHY_999_DATA + DDRSS0_PHY_1000_DATA + DDRSS0_PHY_1001_DATA + DDRSS0_PHY_1002_DATA + DDRSS0_PHY_1003_DATA + DDRSS0_PHY_1004_DATA + DDRSS0_PHY_1005_DATA + DDRSS0_PHY_1006_DATA + DDRSS0_PHY_1007_DATA + DDRSS0_PHY_1008_DATA + DDRSS0_PHY_1009_DATA + DDRSS0_PHY_1010_DATA + DDRSS0_PHY_1011_DATA + DDRSS0_PHY_1012_DATA + DDRSS0_PHY_1013_DATA + DDRSS0_PHY_1014_DATA + DDRSS0_PHY_1015_DATA + DDRSS0_PHY_1016_DATA + DDRSS0_PHY_1017_DATA + DDRSS0_PHY_1018_DATA + DDRSS0_PHY_1019_DATA + DDRSS0_PHY_1020_DATA + DDRSS0_PHY_1021_DATA + DDRSS0_PHY_1022_DATA + DDRSS0_PHY_1023_DATA + DDRSS0_PHY_1024_DATA + DDRSS0_PHY_1025_DATA + DDRSS0_PHY_1026_DATA + DDRSS0_PHY_1027_DATA + DDRSS0_PHY_1028_DATA + DDRSS0_PHY_1029_DATA + DDRSS0_PHY_1030_DATA + DDRSS0_PHY_1031_DATA + DDRSS0_PHY_1032_DATA + DDRSS0_PHY_1033_DATA + DDRSS0_PHY_1034_DATA + DDRSS0_PHY_1035_DATA + DDRSS0_PHY_1036_DATA + DDRSS0_PHY_1037_DATA + DDRSS0_PHY_1038_DATA + DDRSS0_PHY_1039_DATA + DDRSS0_PHY_1040_DATA + DDRSS0_PHY_1041_DATA + DDRSS0_PHY_1042_DATA + DDRSS0_PHY_1043_DATA + DDRSS0_PHY_1044_DATA + DDRSS0_PHY_1045_DATA + DDRSS0_PHY_1046_DATA + DDRSS0_PHY_1047_DATA + DDRSS0_PHY_1048_DATA + DDRSS0_PHY_1049_DATA + DDRSS0_PHY_1050_DATA + DDRSS0_PHY_1051_DATA + DDRSS0_PHY_1052_DATA + DDRSS0_PHY_1053_DATA + DDRSS0_PHY_1054_DATA + DDRSS0_PHY_1055_DATA + DDRSS0_PHY_1056_DATA + DDRSS0_PHY_1057_DATA + DDRSS0_PHY_1058_DATA + DDRSS0_PHY_1059_DATA + DDRSS0_PHY_1060_DATA + DDRSS0_PHY_1061_DATA + DDRSS0_PHY_1062_DATA + DDRSS0_PHY_1063_DATA + DDRSS0_PHY_1064_DATA + DDRSS0_PHY_1065_DATA + DDRSS0_PHY_1066_DATA + DDRSS0_PHY_1067_DATA + DDRSS0_PHY_1068_DATA + DDRSS0_PHY_1069_DATA + DDRSS0_PHY_1070_DATA + DDRSS0_PHY_1071_DATA + DDRSS0_PHY_1072_DATA + DDRSS0_PHY_1073_DATA + DDRSS0_PHY_1074_DATA + DDRSS0_PHY_1075_DATA + DDRSS0_PHY_1076_DATA + DDRSS0_PHY_1077_DATA + DDRSS0_PHY_1078_DATA + DDRSS0_PHY_1079_DATA + DDRSS0_PHY_1080_DATA + DDRSS0_PHY_1081_DATA + DDRSS0_PHY_1082_DATA + DDRSS0_PHY_1083_DATA + DDRSS0_PHY_1084_DATA + DDRSS0_PHY_1085_DATA + DDRSS0_PHY_1086_DATA + DDRSS0_PHY_1087_DATA + DDRSS0_PHY_1088_DATA + DDRSS0_PHY_1089_DATA + DDRSS0_PHY_1090_DATA + DDRSS0_PHY_1091_DATA + DDRSS0_PHY_1092_DATA + DDRSS0_PHY_1093_DATA + DDRSS0_PHY_1094_DATA + DDRSS0_PHY_1095_DATA + DDRSS0_PHY_1096_DATA + DDRSS0_PHY_1097_DATA + DDRSS0_PHY_1098_DATA + DDRSS0_PHY_1099_DATA + DDRSS0_PHY_1100_DATA + DDRSS0_PHY_1101_DATA + DDRSS0_PHY_1102_DATA + DDRSS0_PHY_1103_DATA + DDRSS0_PHY_1104_DATA + DDRSS0_PHY_1105_DATA + DDRSS0_PHY_1106_DATA + DDRSS0_PHY_1107_DATA + DDRSS0_PHY_1108_DATA + DDRSS0_PHY_1109_DATA + DDRSS0_PHY_1110_DATA + DDRSS0_PHY_1111_DATA + DDRSS0_PHY_1112_DATA + DDRSS0_PHY_1113_DATA + DDRSS0_PHY_1114_DATA + DDRSS0_PHY_1115_DATA + DDRSS0_PHY_1116_DATA + DDRSS0_PHY_1117_DATA + DDRSS0_PHY_1118_DATA + DDRSS0_PHY_1119_DATA + DDRSS0_PHY_1120_DATA + DDRSS0_PHY_1121_DATA + DDRSS0_PHY_1122_DATA + DDRSS0_PHY_1123_DATA + DDRSS0_PHY_1124_DATA + DDRSS0_PHY_1125_DATA + DDRSS0_PHY_1126_DATA + DDRSS0_PHY_1127_DATA + DDRSS0_PHY_1128_DATA + DDRSS0_PHY_1129_DATA + DDRSS0_PHY_1130_DATA + DDRSS0_PHY_1131_DATA + DDRSS0_PHY_1132_DATA + DDRSS0_PHY_1133_DATA + DDRSS0_PHY_1134_DATA + DDRSS0_PHY_1135_DATA + DDRSS0_PHY_1136_DATA + DDRSS0_PHY_1137_DATA + DDRSS0_PHY_1138_DATA + DDRSS0_PHY_1139_DATA + DDRSS0_PHY_1140_DATA + DDRSS0_PHY_1141_DATA + DDRSS0_PHY_1142_DATA + DDRSS0_PHY_1143_DATA + DDRSS0_PHY_1144_DATA + DDRSS0_PHY_1145_DATA + DDRSS0_PHY_1146_DATA + DDRSS0_PHY_1147_DATA + DDRSS0_PHY_1148_DATA + DDRSS0_PHY_1149_DATA + DDRSS0_PHY_1150_DATA + DDRSS0_PHY_1151_DATA + DDRSS0_PHY_1152_DATA + DDRSS0_PHY_1153_DATA + DDRSS0_PHY_1154_DATA + DDRSS0_PHY_1155_DATA + DDRSS0_PHY_1156_DATA + DDRSS0_PHY_1157_DATA + DDRSS0_PHY_1158_DATA + DDRSS0_PHY_1159_DATA + DDRSS0_PHY_1160_DATA + DDRSS0_PHY_1161_DATA + DDRSS0_PHY_1162_DATA + DDRSS0_PHY_1163_DATA + DDRSS0_PHY_1164_DATA + DDRSS0_PHY_1165_DATA + DDRSS0_PHY_1166_DATA + DDRSS0_PHY_1167_DATA + DDRSS0_PHY_1168_DATA + DDRSS0_PHY_1169_DATA + DDRSS0_PHY_1170_DATA + DDRSS0_PHY_1171_DATA + DDRSS0_PHY_1172_DATA + DDRSS0_PHY_1173_DATA + DDRSS0_PHY_1174_DATA + DDRSS0_PHY_1175_DATA + DDRSS0_PHY_1176_DATA + DDRSS0_PHY_1177_DATA + DDRSS0_PHY_1178_DATA + DDRSS0_PHY_1179_DATA + DDRSS0_PHY_1180_DATA + DDRSS0_PHY_1181_DATA + DDRSS0_PHY_1182_DATA + DDRSS0_PHY_1183_DATA + DDRSS0_PHY_1184_DATA + DDRSS0_PHY_1185_DATA + DDRSS0_PHY_1186_DATA + DDRSS0_PHY_1187_DATA + DDRSS0_PHY_1188_DATA + DDRSS0_PHY_1189_DATA + DDRSS0_PHY_1190_DATA + DDRSS0_PHY_1191_DATA + DDRSS0_PHY_1192_DATA + DDRSS0_PHY_1193_DATA + DDRSS0_PHY_1194_DATA + DDRSS0_PHY_1195_DATA + DDRSS0_PHY_1196_DATA + DDRSS0_PHY_1197_DATA + DDRSS0_PHY_1198_DATA + DDRSS0_PHY_1199_DATA + DDRSS0_PHY_1200_DATA + DDRSS0_PHY_1201_DATA + DDRSS0_PHY_1202_DATA + DDRSS0_PHY_1203_DATA + DDRSS0_PHY_1204_DATA + DDRSS0_PHY_1205_DATA + DDRSS0_PHY_1206_DATA + DDRSS0_PHY_1207_DATA + DDRSS0_PHY_1208_DATA + DDRSS0_PHY_1209_DATA + DDRSS0_PHY_1210_DATA + DDRSS0_PHY_1211_DATA + DDRSS0_PHY_1212_DATA + DDRSS0_PHY_1213_DATA + DDRSS0_PHY_1214_DATA + DDRSS0_PHY_1215_DATA + DDRSS0_PHY_1216_DATA + DDRSS0_PHY_1217_DATA + DDRSS0_PHY_1218_DATA + DDRSS0_PHY_1219_DATA + DDRSS0_PHY_1220_DATA + DDRSS0_PHY_1221_DATA + DDRSS0_PHY_1222_DATA + DDRSS0_PHY_1223_DATA + DDRSS0_PHY_1224_DATA + DDRSS0_PHY_1225_DATA + DDRSS0_PHY_1226_DATA + DDRSS0_PHY_1227_DATA + DDRSS0_PHY_1228_DATA + DDRSS0_PHY_1229_DATA + DDRSS0_PHY_1230_DATA + DDRSS0_PHY_1231_DATA + DDRSS0_PHY_1232_DATA + DDRSS0_PHY_1233_DATA + DDRSS0_PHY_1234_DATA + DDRSS0_PHY_1235_DATA + DDRSS0_PHY_1236_DATA + DDRSS0_PHY_1237_DATA + DDRSS0_PHY_1238_DATA + DDRSS0_PHY_1239_DATA + DDRSS0_PHY_1240_DATA + DDRSS0_PHY_1241_DATA + DDRSS0_PHY_1242_DATA + DDRSS0_PHY_1243_DATA + DDRSS0_PHY_1244_DATA + DDRSS0_PHY_1245_DATA + DDRSS0_PHY_1246_DATA + DDRSS0_PHY_1247_DATA + DDRSS0_PHY_1248_DATA + DDRSS0_PHY_1249_DATA + DDRSS0_PHY_1250_DATA + DDRSS0_PHY_1251_DATA + DDRSS0_PHY_1252_DATA + DDRSS0_PHY_1253_DATA + DDRSS0_PHY_1254_DATA + DDRSS0_PHY_1255_DATA + DDRSS0_PHY_1256_DATA + DDRSS0_PHY_1257_DATA + DDRSS0_PHY_1258_DATA + DDRSS0_PHY_1259_DATA + DDRSS0_PHY_1260_DATA + DDRSS0_PHY_1261_DATA + DDRSS0_PHY_1262_DATA + DDRSS0_PHY_1263_DATA + DDRSS0_PHY_1264_DATA + DDRSS0_PHY_1265_DATA + DDRSS0_PHY_1266_DATA + DDRSS0_PHY_1267_DATA + DDRSS0_PHY_1268_DATA + DDRSS0_PHY_1269_DATA + DDRSS0_PHY_1270_DATA + DDRSS0_PHY_1271_DATA + DDRSS0_PHY_1272_DATA + DDRSS0_PHY_1273_DATA + DDRSS0_PHY_1274_DATA + DDRSS0_PHY_1275_DATA + DDRSS0_PHY_1276_DATA + DDRSS0_PHY_1277_DATA + DDRSS0_PHY_1278_DATA + DDRSS0_PHY_1279_DATA + DDRSS0_PHY_1280_DATA + DDRSS0_PHY_1281_DATA + DDRSS0_PHY_1282_DATA + DDRSS0_PHY_1283_DATA + DDRSS0_PHY_1284_DATA + DDRSS0_PHY_1285_DATA + DDRSS0_PHY_1286_DATA + DDRSS0_PHY_1287_DATA + DDRSS0_PHY_1288_DATA + DDRSS0_PHY_1289_DATA + DDRSS0_PHY_1290_DATA + DDRSS0_PHY_1291_DATA + DDRSS0_PHY_1292_DATA + DDRSS0_PHY_1293_DATA + DDRSS0_PHY_1294_DATA + DDRSS0_PHY_1295_DATA + DDRSS0_PHY_1296_DATA + DDRSS0_PHY_1297_DATA + DDRSS0_PHY_1298_DATA + DDRSS0_PHY_1299_DATA + DDRSS0_PHY_1300_DATA + DDRSS0_PHY_1301_DATA + DDRSS0_PHY_1302_DATA + DDRSS0_PHY_1303_DATA + DDRSS0_PHY_1304_DATA + DDRSS0_PHY_1305_DATA + DDRSS0_PHY_1306_DATA + DDRSS0_PHY_1307_DATA + DDRSS0_PHY_1308_DATA + DDRSS0_PHY_1309_DATA + DDRSS0_PHY_1310_DATA + DDRSS0_PHY_1311_DATA + DDRSS0_PHY_1312_DATA + DDRSS0_PHY_1313_DATA + DDRSS0_PHY_1314_DATA + DDRSS0_PHY_1315_DATA + DDRSS0_PHY_1316_DATA + DDRSS0_PHY_1317_DATA + DDRSS0_PHY_1318_DATA + DDRSS0_PHY_1319_DATA + DDRSS0_PHY_1320_DATA + DDRSS0_PHY_1321_DATA + DDRSS0_PHY_1322_DATA + DDRSS0_PHY_1323_DATA + DDRSS0_PHY_1324_DATA + DDRSS0_PHY_1325_DATA + DDRSS0_PHY_1326_DATA + DDRSS0_PHY_1327_DATA + DDRSS0_PHY_1328_DATA + DDRSS0_PHY_1329_DATA + DDRSS0_PHY_1330_DATA + DDRSS0_PHY_1331_DATA + DDRSS0_PHY_1332_DATA + DDRSS0_PHY_1333_DATA + DDRSS0_PHY_1334_DATA + DDRSS0_PHY_1335_DATA + DDRSS0_PHY_1336_DATA + DDRSS0_PHY_1337_DATA + DDRSS0_PHY_1338_DATA + DDRSS0_PHY_1339_DATA + DDRSS0_PHY_1340_DATA + DDRSS0_PHY_1341_DATA + DDRSS0_PHY_1342_DATA + DDRSS0_PHY_1343_DATA + DDRSS0_PHY_1344_DATA + DDRSS0_PHY_1345_DATA + DDRSS0_PHY_1346_DATA + DDRSS0_PHY_1347_DATA + DDRSS0_PHY_1348_DATA + DDRSS0_PHY_1349_DATA + DDRSS0_PHY_1350_DATA + DDRSS0_PHY_1351_DATA + DDRSS0_PHY_1352_DATA + DDRSS0_PHY_1353_DATA + DDRSS0_PHY_1354_DATA + DDRSS0_PHY_1355_DATA + DDRSS0_PHY_1356_DATA + DDRSS0_PHY_1357_DATA + DDRSS0_PHY_1358_DATA + DDRSS0_PHY_1359_DATA + DDRSS0_PHY_1360_DATA + DDRSS0_PHY_1361_DATA + DDRSS0_PHY_1362_DATA + DDRSS0_PHY_1363_DATA + DDRSS0_PHY_1364_DATA + DDRSS0_PHY_1365_DATA + DDRSS0_PHY_1366_DATA + DDRSS0_PHY_1367_DATA + DDRSS0_PHY_1368_DATA + DDRSS0_PHY_1369_DATA + DDRSS0_PHY_1370_DATA + DDRSS0_PHY_1371_DATA + DDRSS0_PHY_1372_DATA + DDRSS0_PHY_1373_DATA + DDRSS0_PHY_1374_DATA + DDRSS0_PHY_1375_DATA + DDRSS0_PHY_1376_DATA + DDRSS0_PHY_1377_DATA + DDRSS0_PHY_1378_DATA + DDRSS0_PHY_1379_DATA + DDRSS0_PHY_1380_DATA + DDRSS0_PHY_1381_DATA + DDRSS0_PHY_1382_DATA + DDRSS0_PHY_1383_DATA + DDRSS0_PHY_1384_DATA + DDRSS0_PHY_1385_DATA + DDRSS0_PHY_1386_DATA + DDRSS0_PHY_1387_DATA + DDRSS0_PHY_1388_DATA + DDRSS0_PHY_1389_DATA + DDRSS0_PHY_1390_DATA + DDRSS0_PHY_1391_DATA + DDRSS0_PHY_1392_DATA + DDRSS0_PHY_1393_DATA + DDRSS0_PHY_1394_DATA + DDRSS0_PHY_1395_DATA + DDRSS0_PHY_1396_DATA + DDRSS0_PHY_1397_DATA + DDRSS0_PHY_1398_DATA + DDRSS0_PHY_1399_DATA + DDRSS0_PHY_1400_DATA + DDRSS0_PHY_1401_DATA + DDRSS0_PHY_1402_DATA + DDRSS0_PHY_1403_DATA + DDRSS0_PHY_1404_DATA + DDRSS0_PHY_1405_DATA + DDRSS0_PHY_1406_DATA + DDRSS0_PHY_1407_DATA + DDRSS0_PHY_1408_DATA + DDRSS0_PHY_1409_DATA + DDRSS0_PHY_1410_DATA + DDRSS0_PHY_1411_DATA + DDRSS0_PHY_1412_DATA + DDRSS0_PHY_1413_DATA + DDRSS0_PHY_1414_DATA + DDRSS0_PHY_1415_DATA + DDRSS0_PHY_1416_DATA + DDRSS0_PHY_1417_DATA + DDRSS0_PHY_1418_DATA + DDRSS0_PHY_1419_DATA + DDRSS0_PHY_1420_DATA + DDRSS0_PHY_1421_DATA + DDRSS0_PHY_1422_DATA + >; + }; + + memorycontroller1: memorycontroller@29b0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029b0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029a0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; + power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>, + <&k3_pds 132 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 192 1>, <&k3_clks 78 2>; + ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + instance = <1>; + + bootph-pre-ram; + + ti,ctl-data = < + DDRSS1_CTL_00_DATA + DDRSS1_CTL_01_DATA + DDRSS1_CTL_02_DATA + DDRSS1_CTL_03_DATA + DDRSS1_CTL_04_DATA + DDRSS1_CTL_05_DATA + DDRSS1_CTL_06_DATA + DDRSS1_CTL_07_DATA + DDRSS1_CTL_08_DATA + DDRSS1_CTL_09_DATA + DDRSS1_CTL_10_DATA + DDRSS1_CTL_11_DATA + DDRSS1_CTL_12_DATA + DDRSS1_CTL_13_DATA + DDRSS1_CTL_14_DATA + DDRSS1_CTL_15_DATA + DDRSS1_CTL_16_DATA + DDRSS1_CTL_17_DATA + DDRSS1_CTL_18_DATA + DDRSS1_CTL_19_DATA + DDRSS1_CTL_20_DATA + DDRSS1_CTL_21_DATA + DDRSS1_CTL_22_DATA + DDRSS1_CTL_23_DATA + DDRSS1_CTL_24_DATA + DDRSS1_CTL_25_DATA + DDRSS1_CTL_26_DATA + DDRSS1_CTL_27_DATA + DDRSS1_CTL_28_DATA + DDRSS1_CTL_29_DATA + DDRSS1_CTL_30_DATA + DDRSS1_CTL_31_DATA + DDRSS1_CTL_32_DATA + DDRSS1_CTL_33_DATA + DDRSS1_CTL_34_DATA + DDRSS1_CTL_35_DATA + DDRSS1_CTL_36_DATA + DDRSS1_CTL_37_DATA + DDRSS1_CTL_38_DATA + DDRSS1_CTL_39_DATA + DDRSS1_CTL_40_DATA + DDRSS1_CTL_41_DATA + DDRSS1_CTL_42_DATA + DDRSS1_CTL_43_DATA + DDRSS1_CTL_44_DATA + DDRSS1_CTL_45_DATA + DDRSS1_CTL_46_DATA + DDRSS1_CTL_47_DATA + DDRSS1_CTL_48_DATA + DDRSS1_CTL_49_DATA + DDRSS1_CTL_50_DATA + DDRSS1_CTL_51_DATA + DDRSS1_CTL_52_DATA + DDRSS1_CTL_53_DATA + DDRSS1_CTL_54_DATA + DDRSS1_CTL_55_DATA + DDRSS1_CTL_56_DATA + DDRSS1_CTL_57_DATA + DDRSS1_CTL_58_DATA + DDRSS1_CTL_59_DATA + DDRSS1_CTL_60_DATA + DDRSS1_CTL_61_DATA + DDRSS1_CTL_62_DATA + DDRSS1_CTL_63_DATA + DDRSS1_CTL_64_DATA + DDRSS1_CTL_65_DATA + DDRSS1_CTL_66_DATA + DDRSS1_CTL_67_DATA + DDRSS1_CTL_68_DATA + DDRSS1_CTL_69_DATA + DDRSS1_CTL_70_DATA + DDRSS1_CTL_71_DATA + DDRSS1_CTL_72_DATA + DDRSS1_CTL_73_DATA + DDRSS1_CTL_74_DATA + DDRSS1_CTL_75_DATA + DDRSS1_CTL_76_DATA + DDRSS1_CTL_77_DATA + DDRSS1_CTL_78_DATA + DDRSS1_CTL_79_DATA + DDRSS1_CTL_80_DATA + DDRSS1_CTL_81_DATA + DDRSS1_CTL_82_DATA + DDRSS1_CTL_83_DATA + DDRSS1_CTL_84_DATA + DDRSS1_CTL_85_DATA + DDRSS1_CTL_86_DATA + DDRSS1_CTL_87_DATA + DDRSS1_CTL_88_DATA + DDRSS1_CTL_89_DATA + DDRSS1_CTL_90_DATA + DDRSS1_CTL_91_DATA + DDRSS1_CTL_92_DATA + DDRSS1_CTL_93_DATA + DDRSS1_CTL_94_DATA + DDRSS1_CTL_95_DATA + DDRSS1_CTL_96_DATA + DDRSS1_CTL_97_DATA + DDRSS1_CTL_98_DATA + DDRSS1_CTL_99_DATA + DDRSS1_CTL_100_DATA + DDRSS1_CTL_101_DATA + DDRSS1_CTL_102_DATA + DDRSS1_CTL_103_DATA + DDRSS1_CTL_104_DATA + DDRSS1_CTL_105_DATA + DDRSS1_CTL_106_DATA + DDRSS1_CTL_107_DATA + DDRSS1_CTL_108_DATA + DDRSS1_CTL_109_DATA + DDRSS1_CTL_110_DATA + DDRSS1_CTL_111_DATA + DDRSS1_CTL_112_DATA + DDRSS1_CTL_113_DATA + DDRSS1_CTL_114_DATA + DDRSS1_CTL_115_DATA + DDRSS1_CTL_116_DATA + DDRSS1_CTL_117_DATA + DDRSS1_CTL_118_DATA + DDRSS1_CTL_119_DATA + DDRSS1_CTL_120_DATA + DDRSS1_CTL_121_DATA + DDRSS1_CTL_122_DATA + DDRSS1_CTL_123_DATA + DDRSS1_CTL_124_DATA + DDRSS1_CTL_125_DATA + DDRSS1_CTL_126_DATA + DDRSS1_CTL_127_DATA + DDRSS1_CTL_128_DATA + DDRSS1_CTL_129_DATA + DDRSS1_CTL_130_DATA + DDRSS1_CTL_131_DATA + DDRSS1_CTL_132_DATA + DDRSS1_CTL_133_DATA + DDRSS1_CTL_134_DATA + DDRSS1_CTL_135_DATA + DDRSS1_CTL_136_DATA + DDRSS1_CTL_137_DATA + DDRSS1_CTL_138_DATA + DDRSS1_CTL_139_DATA + DDRSS1_CTL_140_DATA + DDRSS1_CTL_141_DATA + DDRSS1_CTL_142_DATA + DDRSS1_CTL_143_DATA + DDRSS1_CTL_144_DATA + DDRSS1_CTL_145_DATA + DDRSS1_CTL_146_DATA + DDRSS1_CTL_147_DATA + DDRSS1_CTL_148_DATA + DDRSS1_CTL_149_DATA + DDRSS1_CTL_150_DATA + DDRSS1_CTL_151_DATA + DDRSS1_CTL_152_DATA + DDRSS1_CTL_153_DATA + DDRSS1_CTL_154_DATA + DDRSS1_CTL_155_DATA + DDRSS1_CTL_156_DATA + DDRSS1_CTL_157_DATA + DDRSS1_CTL_158_DATA + DDRSS1_CTL_159_DATA + DDRSS1_CTL_160_DATA + DDRSS1_CTL_161_DATA + DDRSS1_CTL_162_DATA + DDRSS1_CTL_163_DATA + DDRSS1_CTL_164_DATA + DDRSS1_CTL_165_DATA + DDRSS1_CTL_166_DATA + DDRSS1_CTL_167_DATA + DDRSS1_CTL_168_DATA + DDRSS1_CTL_169_DATA + DDRSS1_CTL_170_DATA + DDRSS1_CTL_171_DATA + DDRSS1_CTL_172_DATA + DDRSS1_CTL_173_DATA + DDRSS1_CTL_174_DATA + DDRSS1_CTL_175_DATA + DDRSS1_CTL_176_DATA + DDRSS1_CTL_177_DATA + DDRSS1_CTL_178_DATA + DDRSS1_CTL_179_DATA + DDRSS1_CTL_180_DATA + DDRSS1_CTL_181_DATA + DDRSS1_CTL_182_DATA + DDRSS1_CTL_183_DATA + DDRSS1_CTL_184_DATA + DDRSS1_CTL_185_DATA + DDRSS1_CTL_186_DATA + DDRSS1_CTL_187_DATA + DDRSS1_CTL_188_DATA + DDRSS1_CTL_189_DATA + DDRSS1_CTL_190_DATA + DDRSS1_CTL_191_DATA + DDRSS1_CTL_192_DATA + DDRSS1_CTL_193_DATA + DDRSS1_CTL_194_DATA + DDRSS1_CTL_195_DATA + DDRSS1_CTL_196_DATA + DDRSS1_CTL_197_DATA + DDRSS1_CTL_198_DATA + DDRSS1_CTL_199_DATA + DDRSS1_CTL_200_DATA + DDRSS1_CTL_201_DATA + DDRSS1_CTL_202_DATA + DDRSS1_CTL_203_DATA + DDRSS1_CTL_204_DATA + DDRSS1_CTL_205_DATA + DDRSS1_CTL_206_DATA + DDRSS1_CTL_207_DATA + DDRSS1_CTL_208_DATA + DDRSS1_CTL_209_DATA + DDRSS1_CTL_210_DATA + DDRSS1_CTL_211_DATA + DDRSS1_CTL_212_DATA + DDRSS1_CTL_213_DATA + DDRSS1_CTL_214_DATA + DDRSS1_CTL_215_DATA + DDRSS1_CTL_216_DATA + DDRSS1_CTL_217_DATA + DDRSS1_CTL_218_DATA + DDRSS1_CTL_219_DATA + DDRSS1_CTL_220_DATA + DDRSS1_CTL_221_DATA + DDRSS1_CTL_222_DATA + DDRSS1_CTL_223_DATA + DDRSS1_CTL_224_DATA + DDRSS1_CTL_225_DATA + DDRSS1_CTL_226_DATA + DDRSS1_CTL_227_DATA + DDRSS1_CTL_228_DATA + DDRSS1_CTL_229_DATA + DDRSS1_CTL_230_DATA + DDRSS1_CTL_231_DATA + DDRSS1_CTL_232_DATA + DDRSS1_CTL_233_DATA + DDRSS1_CTL_234_DATA + DDRSS1_CTL_235_DATA + DDRSS1_CTL_236_DATA + DDRSS1_CTL_237_DATA + DDRSS1_CTL_238_DATA + DDRSS1_CTL_239_DATA + DDRSS1_CTL_240_DATA + DDRSS1_CTL_241_DATA + DDRSS1_CTL_242_DATA + DDRSS1_CTL_243_DATA + DDRSS1_CTL_244_DATA + DDRSS1_CTL_245_DATA + DDRSS1_CTL_246_DATA + DDRSS1_CTL_247_DATA + DDRSS1_CTL_248_DATA + DDRSS1_CTL_249_DATA + DDRSS1_CTL_250_DATA + DDRSS1_CTL_251_DATA + DDRSS1_CTL_252_DATA + DDRSS1_CTL_253_DATA + DDRSS1_CTL_254_DATA + DDRSS1_CTL_255_DATA + DDRSS1_CTL_256_DATA + DDRSS1_CTL_257_DATA + DDRSS1_CTL_258_DATA + DDRSS1_CTL_259_DATA + DDRSS1_CTL_260_DATA + DDRSS1_CTL_261_DATA + DDRSS1_CTL_262_DATA + DDRSS1_CTL_263_DATA + DDRSS1_CTL_264_DATA + DDRSS1_CTL_265_DATA + DDRSS1_CTL_266_DATA + DDRSS1_CTL_267_DATA + DDRSS1_CTL_268_DATA + DDRSS1_CTL_269_DATA + DDRSS1_CTL_270_DATA + DDRSS1_CTL_271_DATA + DDRSS1_CTL_272_DATA + DDRSS1_CTL_273_DATA + DDRSS1_CTL_274_DATA + DDRSS1_CTL_275_DATA + DDRSS1_CTL_276_DATA + DDRSS1_CTL_277_DATA + DDRSS1_CTL_278_DATA + DDRSS1_CTL_279_DATA + DDRSS1_CTL_280_DATA + DDRSS1_CTL_281_DATA + DDRSS1_CTL_282_DATA + DDRSS1_CTL_283_DATA + DDRSS1_CTL_284_DATA + DDRSS1_CTL_285_DATA + DDRSS1_CTL_286_DATA + DDRSS1_CTL_287_DATA + DDRSS1_CTL_288_DATA + DDRSS1_CTL_289_DATA + DDRSS1_CTL_290_DATA + DDRSS1_CTL_291_DATA + DDRSS1_CTL_292_DATA + DDRSS1_CTL_293_DATA + DDRSS1_CTL_294_DATA + DDRSS1_CTL_295_DATA + DDRSS1_CTL_296_DATA + DDRSS1_CTL_297_DATA + DDRSS1_CTL_298_DATA + DDRSS1_CTL_299_DATA + DDRSS1_CTL_300_DATA + DDRSS1_CTL_301_DATA + DDRSS1_CTL_302_DATA + DDRSS1_CTL_303_DATA + DDRSS1_CTL_304_DATA + DDRSS1_CTL_305_DATA + DDRSS1_CTL_306_DATA + DDRSS1_CTL_307_DATA + DDRSS1_CTL_308_DATA + DDRSS1_CTL_309_DATA + DDRSS1_CTL_310_DATA + DDRSS1_CTL_311_DATA + DDRSS1_CTL_312_DATA + DDRSS1_CTL_313_DATA + DDRSS1_CTL_314_DATA + DDRSS1_CTL_315_DATA + DDRSS1_CTL_316_DATA + DDRSS1_CTL_317_DATA + DDRSS1_CTL_318_DATA + DDRSS1_CTL_319_DATA + DDRSS1_CTL_320_DATA + DDRSS1_CTL_321_DATA + DDRSS1_CTL_322_DATA + DDRSS1_CTL_323_DATA + DDRSS1_CTL_324_DATA + DDRSS1_CTL_325_DATA + DDRSS1_CTL_326_DATA + DDRSS1_CTL_327_DATA + DDRSS1_CTL_328_DATA + DDRSS1_CTL_329_DATA + DDRSS1_CTL_330_DATA + DDRSS1_CTL_331_DATA + DDRSS1_CTL_332_DATA + DDRSS1_CTL_333_DATA + DDRSS1_CTL_334_DATA + DDRSS1_CTL_335_DATA + DDRSS1_CTL_336_DATA + DDRSS1_CTL_337_DATA + DDRSS1_CTL_338_DATA + DDRSS1_CTL_339_DATA + DDRSS1_CTL_340_DATA + DDRSS1_CTL_341_DATA + DDRSS1_CTL_342_DATA + DDRSS1_CTL_343_DATA + DDRSS1_CTL_344_DATA + DDRSS1_CTL_345_DATA + DDRSS1_CTL_346_DATA + DDRSS1_CTL_347_DATA + DDRSS1_CTL_348_DATA + DDRSS1_CTL_349_DATA + DDRSS1_CTL_350_DATA + DDRSS1_CTL_351_DATA + DDRSS1_CTL_352_DATA + DDRSS1_CTL_353_DATA + DDRSS1_CTL_354_DATA + DDRSS1_CTL_355_DATA + DDRSS1_CTL_356_DATA + DDRSS1_CTL_357_DATA + DDRSS1_CTL_358_DATA + DDRSS1_CTL_359_DATA + DDRSS1_CTL_360_DATA + DDRSS1_CTL_361_DATA + DDRSS1_CTL_362_DATA + DDRSS1_CTL_363_DATA + DDRSS1_CTL_364_DATA + DDRSS1_CTL_365_DATA + DDRSS1_CTL_366_DATA + DDRSS1_CTL_367_DATA + DDRSS1_CTL_368_DATA + DDRSS1_CTL_369_DATA + DDRSS1_CTL_370_DATA + DDRSS1_CTL_371_DATA + DDRSS1_CTL_372_DATA + DDRSS1_CTL_373_DATA + DDRSS1_CTL_374_DATA + DDRSS1_CTL_375_DATA + DDRSS1_CTL_376_DATA + DDRSS1_CTL_377_DATA + DDRSS1_CTL_378_DATA + DDRSS1_CTL_379_DATA + DDRSS1_CTL_380_DATA + DDRSS1_CTL_381_DATA + DDRSS1_CTL_382_DATA + DDRSS1_CTL_383_DATA + DDRSS1_CTL_384_DATA + DDRSS1_CTL_385_DATA + DDRSS1_CTL_386_DATA + DDRSS1_CTL_387_DATA + DDRSS1_CTL_388_DATA + DDRSS1_CTL_389_DATA + DDRSS1_CTL_390_DATA + DDRSS1_CTL_391_DATA + DDRSS1_CTL_392_DATA + DDRSS1_CTL_393_DATA + DDRSS1_CTL_394_DATA + DDRSS1_CTL_395_DATA + DDRSS1_CTL_396_DATA + DDRSS1_CTL_397_DATA + DDRSS1_CTL_398_DATA + DDRSS1_CTL_399_DATA + DDRSS1_CTL_400_DATA + DDRSS1_CTL_401_DATA + DDRSS1_CTL_402_DATA + DDRSS1_CTL_403_DATA + DDRSS1_CTL_404_DATA + DDRSS1_CTL_405_DATA + DDRSS1_CTL_406_DATA + DDRSS1_CTL_407_DATA + DDRSS1_CTL_408_DATA + DDRSS1_CTL_409_DATA + DDRSS1_CTL_410_DATA + DDRSS1_CTL_411_DATA + DDRSS1_CTL_412_DATA + DDRSS1_CTL_413_DATA + DDRSS1_CTL_414_DATA + DDRSS1_CTL_415_DATA + DDRSS1_CTL_416_DATA + DDRSS1_CTL_417_DATA + DDRSS1_CTL_418_DATA + DDRSS1_CTL_419_DATA + DDRSS1_CTL_420_DATA + DDRSS1_CTL_421_DATA + DDRSS1_CTL_422_DATA + DDRSS1_CTL_423_DATA + DDRSS1_CTL_424_DATA + DDRSS1_CTL_425_DATA + DDRSS1_CTL_426_DATA + DDRSS1_CTL_427_DATA + DDRSS1_CTL_428_DATA + DDRSS1_CTL_429_DATA + DDRSS1_CTL_430_DATA + DDRSS1_CTL_431_DATA + DDRSS1_CTL_432_DATA + DDRSS1_CTL_433_DATA + DDRSS1_CTL_434_DATA + DDRSS1_CTL_435_DATA + DDRSS1_CTL_436_DATA + DDRSS1_CTL_437_DATA + DDRSS1_CTL_438_DATA + DDRSS1_CTL_439_DATA + DDRSS1_CTL_440_DATA + DDRSS1_CTL_441_DATA + DDRSS1_CTL_442_DATA + DDRSS1_CTL_443_DATA + DDRSS1_CTL_444_DATA + DDRSS1_CTL_445_DATA + DDRSS1_CTL_446_DATA + DDRSS1_CTL_447_DATA + DDRSS1_CTL_448_DATA + DDRSS1_CTL_449_DATA + DDRSS1_CTL_450_DATA + DDRSS1_CTL_451_DATA + DDRSS1_CTL_452_DATA + DDRSS1_CTL_453_DATA + DDRSS1_CTL_454_DATA + DDRSS1_CTL_455_DATA + DDRSS1_CTL_456_DATA + DDRSS1_CTL_457_DATA + DDRSS1_CTL_458_DATA + >; + + ti,pi-data = < + DDRSS1_PI_00_DATA + DDRSS1_PI_01_DATA + DDRSS1_PI_02_DATA + DDRSS1_PI_03_DATA + DDRSS1_PI_04_DATA + DDRSS1_PI_05_DATA + DDRSS1_PI_06_DATA + DDRSS1_PI_07_DATA + DDRSS1_PI_08_DATA + DDRSS1_PI_09_DATA + DDRSS1_PI_10_DATA + DDRSS1_PI_11_DATA + DDRSS1_PI_12_DATA + DDRSS1_PI_13_DATA + DDRSS1_PI_14_DATA + DDRSS1_PI_15_DATA + DDRSS1_PI_16_DATA + DDRSS1_PI_17_DATA + DDRSS1_PI_18_DATA + DDRSS1_PI_19_DATA + DDRSS1_PI_20_DATA + DDRSS1_PI_21_DATA + DDRSS1_PI_22_DATA + DDRSS1_PI_23_DATA + DDRSS1_PI_24_DATA + DDRSS1_PI_25_DATA + DDRSS1_PI_26_DATA + DDRSS1_PI_27_DATA + DDRSS1_PI_28_DATA + DDRSS1_PI_29_DATA + DDRSS1_PI_30_DATA + DDRSS1_PI_31_DATA + DDRSS1_PI_32_DATA + DDRSS1_PI_33_DATA + DDRSS1_PI_34_DATA + DDRSS1_PI_35_DATA + DDRSS1_PI_36_DATA + DDRSS1_PI_37_DATA + DDRSS1_PI_38_DATA + DDRSS1_PI_39_DATA + DDRSS1_PI_40_DATA + DDRSS1_PI_41_DATA + DDRSS1_PI_42_DATA + DDRSS1_PI_43_DATA + DDRSS1_PI_44_DATA + DDRSS1_PI_45_DATA + DDRSS1_PI_46_DATA + DDRSS1_PI_47_DATA + DDRSS1_PI_48_DATA + DDRSS1_PI_49_DATA + DDRSS1_PI_50_DATA + DDRSS1_PI_51_DATA + DDRSS1_PI_52_DATA + DDRSS1_PI_53_DATA + DDRSS1_PI_54_DATA + DDRSS1_PI_55_DATA + DDRSS1_PI_56_DATA + DDRSS1_PI_57_DATA + DDRSS1_PI_58_DATA + DDRSS1_PI_59_DATA + DDRSS1_PI_60_DATA + DDRSS1_PI_61_DATA + DDRSS1_PI_62_DATA + DDRSS1_PI_63_DATA + DDRSS1_PI_64_DATA + DDRSS1_PI_65_DATA + DDRSS1_PI_66_DATA + DDRSS1_PI_67_DATA + DDRSS1_PI_68_DATA + DDRSS1_PI_69_DATA + DDRSS1_PI_70_DATA + DDRSS1_PI_71_DATA + DDRSS1_PI_72_DATA + DDRSS1_PI_73_DATA + DDRSS1_PI_74_DATA + DDRSS1_PI_75_DATA + DDRSS1_PI_76_DATA + DDRSS1_PI_77_DATA + DDRSS1_PI_78_DATA + DDRSS1_PI_79_DATA + DDRSS1_PI_80_DATA + DDRSS1_PI_81_DATA + DDRSS1_PI_82_DATA + DDRSS1_PI_83_DATA + DDRSS1_PI_84_DATA + DDRSS1_PI_85_DATA + DDRSS1_PI_86_DATA + DDRSS1_PI_87_DATA + DDRSS1_PI_88_DATA + DDRSS1_PI_89_DATA + DDRSS1_PI_90_DATA + DDRSS1_PI_91_DATA + DDRSS1_PI_92_DATA + DDRSS1_PI_93_DATA + DDRSS1_PI_94_DATA + DDRSS1_PI_95_DATA + DDRSS1_PI_96_DATA + DDRSS1_PI_97_DATA + DDRSS1_PI_98_DATA + DDRSS1_PI_99_DATA + DDRSS1_PI_100_DATA + DDRSS1_PI_101_DATA + DDRSS1_PI_102_DATA + DDRSS1_PI_103_DATA + DDRSS1_PI_104_DATA + DDRSS1_PI_105_DATA + DDRSS1_PI_106_DATA + DDRSS1_PI_107_DATA + DDRSS1_PI_108_DATA + DDRSS1_PI_109_DATA + DDRSS1_PI_110_DATA + DDRSS1_PI_111_DATA + DDRSS1_PI_112_DATA + DDRSS1_PI_113_DATA + DDRSS1_PI_114_DATA + DDRSS1_PI_115_DATA + DDRSS1_PI_116_DATA + DDRSS1_PI_117_DATA + DDRSS1_PI_118_DATA + DDRSS1_PI_119_DATA + DDRSS1_PI_120_DATA + DDRSS1_PI_121_DATA + DDRSS1_PI_122_DATA + DDRSS1_PI_123_DATA + DDRSS1_PI_124_DATA + DDRSS1_PI_125_DATA + DDRSS1_PI_126_DATA + DDRSS1_PI_127_DATA + DDRSS1_PI_128_DATA + DDRSS1_PI_129_DATA + DDRSS1_PI_130_DATA + DDRSS1_PI_131_DATA + DDRSS1_PI_132_DATA + DDRSS1_PI_133_DATA + DDRSS1_PI_134_DATA + DDRSS1_PI_135_DATA + DDRSS1_PI_136_DATA + DDRSS1_PI_137_DATA + DDRSS1_PI_138_DATA + DDRSS1_PI_139_DATA + DDRSS1_PI_140_DATA + DDRSS1_PI_141_DATA + DDRSS1_PI_142_DATA + DDRSS1_PI_143_DATA + DDRSS1_PI_144_DATA + DDRSS1_PI_145_DATA + DDRSS1_PI_146_DATA + DDRSS1_PI_147_DATA + DDRSS1_PI_148_DATA + DDRSS1_PI_149_DATA + DDRSS1_PI_150_DATA + DDRSS1_PI_151_DATA + DDRSS1_PI_152_DATA + DDRSS1_PI_153_DATA + DDRSS1_PI_154_DATA + DDRSS1_PI_155_DATA + DDRSS1_PI_156_DATA + DDRSS1_PI_157_DATA + DDRSS1_PI_158_DATA + DDRSS1_PI_159_DATA + DDRSS1_PI_160_DATA + DDRSS1_PI_161_DATA + DDRSS1_PI_162_DATA + DDRSS1_PI_163_DATA + DDRSS1_PI_164_DATA + DDRSS1_PI_165_DATA + DDRSS1_PI_166_DATA + DDRSS1_PI_167_DATA + DDRSS1_PI_168_DATA + DDRSS1_PI_169_DATA + DDRSS1_PI_170_DATA + DDRSS1_PI_171_DATA + DDRSS1_PI_172_DATA + DDRSS1_PI_173_DATA + DDRSS1_PI_174_DATA + DDRSS1_PI_175_DATA + DDRSS1_PI_176_DATA + DDRSS1_PI_177_DATA + DDRSS1_PI_178_DATA + DDRSS1_PI_179_DATA + DDRSS1_PI_180_DATA + DDRSS1_PI_181_DATA + DDRSS1_PI_182_DATA + DDRSS1_PI_183_DATA + DDRSS1_PI_184_DATA + DDRSS1_PI_185_DATA + DDRSS1_PI_186_DATA + DDRSS1_PI_187_DATA + DDRSS1_PI_188_DATA + DDRSS1_PI_189_DATA + DDRSS1_PI_190_DATA + DDRSS1_PI_191_DATA + DDRSS1_PI_192_DATA + DDRSS1_PI_193_DATA + DDRSS1_PI_194_DATA + DDRSS1_PI_195_DATA + DDRSS1_PI_196_DATA + DDRSS1_PI_197_DATA + DDRSS1_PI_198_DATA + DDRSS1_PI_199_DATA + DDRSS1_PI_200_DATA + DDRSS1_PI_201_DATA + DDRSS1_PI_202_DATA + DDRSS1_PI_203_DATA + DDRSS1_PI_204_DATA + DDRSS1_PI_205_DATA + DDRSS1_PI_206_DATA + DDRSS1_PI_207_DATA + DDRSS1_PI_208_DATA + DDRSS1_PI_209_DATA + DDRSS1_PI_210_DATA + DDRSS1_PI_211_DATA + DDRSS1_PI_212_DATA + DDRSS1_PI_213_DATA + DDRSS1_PI_214_DATA + DDRSS1_PI_215_DATA + DDRSS1_PI_216_DATA + DDRSS1_PI_217_DATA + DDRSS1_PI_218_DATA + DDRSS1_PI_219_DATA + DDRSS1_PI_220_DATA + DDRSS1_PI_221_DATA + DDRSS1_PI_222_DATA + DDRSS1_PI_223_DATA + DDRSS1_PI_224_DATA + DDRSS1_PI_225_DATA + DDRSS1_PI_226_DATA + DDRSS1_PI_227_DATA + DDRSS1_PI_228_DATA + DDRSS1_PI_229_DATA + DDRSS1_PI_230_DATA + DDRSS1_PI_231_DATA + DDRSS1_PI_232_DATA + DDRSS1_PI_233_DATA + DDRSS1_PI_234_DATA + DDRSS1_PI_235_DATA + DDRSS1_PI_236_DATA + DDRSS1_PI_237_DATA + DDRSS1_PI_238_DATA + DDRSS1_PI_239_DATA + DDRSS1_PI_240_DATA + DDRSS1_PI_241_DATA + DDRSS1_PI_242_DATA + DDRSS1_PI_243_DATA + DDRSS1_PI_244_DATA + DDRSS1_PI_245_DATA + DDRSS1_PI_246_DATA + DDRSS1_PI_247_DATA + DDRSS1_PI_248_DATA + DDRSS1_PI_249_DATA + DDRSS1_PI_250_DATA + DDRSS1_PI_251_DATA + DDRSS1_PI_252_DATA + DDRSS1_PI_253_DATA + DDRSS1_PI_254_DATA + DDRSS1_PI_255_DATA + DDRSS1_PI_256_DATA + DDRSS1_PI_257_DATA + DDRSS1_PI_258_DATA + DDRSS1_PI_259_DATA + DDRSS1_PI_260_DATA + DDRSS1_PI_261_DATA + DDRSS1_PI_262_DATA + DDRSS1_PI_263_DATA + DDRSS1_PI_264_DATA + DDRSS1_PI_265_DATA + DDRSS1_PI_266_DATA + DDRSS1_PI_267_DATA + DDRSS1_PI_268_DATA + DDRSS1_PI_269_DATA + DDRSS1_PI_270_DATA + DDRSS1_PI_271_DATA + DDRSS1_PI_272_DATA + DDRSS1_PI_273_DATA + DDRSS1_PI_274_DATA + DDRSS1_PI_275_DATA + DDRSS1_PI_276_DATA + DDRSS1_PI_277_DATA + DDRSS1_PI_278_DATA + DDRSS1_PI_279_DATA + DDRSS1_PI_280_DATA + DDRSS1_PI_281_DATA + DDRSS1_PI_282_DATA + DDRSS1_PI_283_DATA + DDRSS1_PI_284_DATA + DDRSS1_PI_285_DATA + DDRSS1_PI_286_DATA + DDRSS1_PI_287_DATA + DDRSS1_PI_288_DATA + DDRSS1_PI_289_DATA + DDRSS1_PI_290_DATA + DDRSS1_PI_291_DATA + DDRSS1_PI_292_DATA + DDRSS1_PI_293_DATA + DDRSS1_PI_294_DATA + DDRSS1_PI_295_DATA + DDRSS1_PI_296_DATA + DDRSS1_PI_297_DATA + DDRSS1_PI_298_DATA + DDRSS1_PI_299_DATA + >; + + ti,phy-data = < + DDRSS1_PHY_00_DATA + DDRSS1_PHY_01_DATA + DDRSS1_PHY_02_DATA + DDRSS1_PHY_03_DATA + DDRSS1_PHY_04_DATA + DDRSS1_PHY_05_DATA + DDRSS1_PHY_06_DATA + DDRSS1_PHY_07_DATA + DDRSS1_PHY_08_DATA + DDRSS1_PHY_09_DATA + DDRSS1_PHY_10_DATA + DDRSS1_PHY_11_DATA + DDRSS1_PHY_12_DATA + DDRSS1_PHY_13_DATA + DDRSS1_PHY_14_DATA + DDRSS1_PHY_15_DATA + DDRSS1_PHY_16_DATA + DDRSS1_PHY_17_DATA + DDRSS1_PHY_18_DATA + DDRSS1_PHY_19_DATA + DDRSS1_PHY_20_DATA + DDRSS1_PHY_21_DATA + DDRSS1_PHY_22_DATA + DDRSS1_PHY_23_DATA + DDRSS1_PHY_24_DATA + DDRSS1_PHY_25_DATA + DDRSS1_PHY_26_DATA + DDRSS1_PHY_27_DATA + DDRSS1_PHY_28_DATA + DDRSS1_PHY_29_DATA + DDRSS1_PHY_30_DATA + DDRSS1_PHY_31_DATA + DDRSS1_PHY_32_DATA + DDRSS1_PHY_33_DATA + DDRSS1_PHY_34_DATA + DDRSS1_PHY_35_DATA + DDRSS1_PHY_36_DATA + DDRSS1_PHY_37_DATA + DDRSS1_PHY_38_DATA + DDRSS1_PHY_39_DATA + DDRSS1_PHY_40_DATA + DDRSS1_PHY_41_DATA + DDRSS1_PHY_42_DATA + DDRSS1_PHY_43_DATA + DDRSS1_PHY_44_DATA + DDRSS1_PHY_45_DATA + DDRSS1_PHY_46_DATA + DDRSS1_PHY_47_DATA + DDRSS1_PHY_48_DATA + DDRSS1_PHY_49_DATA + DDRSS1_PHY_50_DATA + DDRSS1_PHY_51_DATA + DDRSS1_PHY_52_DATA + DDRSS1_PHY_53_DATA + DDRSS1_PHY_54_DATA + DDRSS1_PHY_55_DATA + DDRSS1_PHY_56_DATA + DDRSS1_PHY_57_DATA + DDRSS1_PHY_58_DATA + DDRSS1_PHY_59_DATA + DDRSS1_PHY_60_DATA + DDRSS1_PHY_61_DATA + DDRSS1_PHY_62_DATA + DDRSS1_PHY_63_DATA + DDRSS1_PHY_64_DATA + DDRSS1_PHY_65_DATA + DDRSS1_PHY_66_DATA + DDRSS1_PHY_67_DATA + DDRSS1_PHY_68_DATA + DDRSS1_PHY_69_DATA + DDRSS1_PHY_70_DATA + DDRSS1_PHY_71_DATA + DDRSS1_PHY_72_DATA + DDRSS1_PHY_73_DATA + DDRSS1_PHY_74_DATA + DDRSS1_PHY_75_DATA + DDRSS1_PHY_76_DATA + DDRSS1_PHY_77_DATA + DDRSS1_PHY_78_DATA + DDRSS1_PHY_79_DATA + DDRSS1_PHY_80_DATA + DDRSS1_PHY_81_DATA + DDRSS1_PHY_82_DATA + DDRSS1_PHY_83_DATA + DDRSS1_PHY_84_DATA + DDRSS1_PHY_85_DATA + DDRSS1_PHY_86_DATA + DDRSS1_PHY_87_DATA + DDRSS1_PHY_88_DATA + DDRSS1_PHY_89_DATA + DDRSS1_PHY_90_DATA + DDRSS1_PHY_91_DATA + DDRSS1_PHY_92_DATA + DDRSS1_PHY_93_DATA + DDRSS1_PHY_94_DATA + DDRSS1_PHY_95_DATA + DDRSS1_PHY_96_DATA + DDRSS1_PHY_97_DATA + DDRSS1_PHY_98_DATA + DDRSS1_PHY_99_DATA + DDRSS1_PHY_100_DATA + DDRSS1_PHY_101_DATA + DDRSS1_PHY_102_DATA + DDRSS1_PHY_103_DATA + DDRSS1_PHY_104_DATA + DDRSS1_PHY_105_DATA + DDRSS1_PHY_106_DATA + DDRSS1_PHY_107_DATA + DDRSS1_PHY_108_DATA + DDRSS1_PHY_109_DATA + DDRSS1_PHY_110_DATA + DDRSS1_PHY_111_DATA + DDRSS1_PHY_112_DATA + DDRSS1_PHY_113_DATA + DDRSS1_PHY_114_DATA + DDRSS1_PHY_115_DATA + DDRSS1_PHY_116_DATA + DDRSS1_PHY_117_DATA + DDRSS1_PHY_118_DATA + DDRSS1_PHY_119_DATA + DDRSS1_PHY_120_DATA + DDRSS1_PHY_121_DATA + DDRSS1_PHY_122_DATA + DDRSS1_PHY_123_DATA + DDRSS1_PHY_124_DATA + DDRSS1_PHY_125_DATA + DDRSS1_PHY_126_DATA + DDRSS1_PHY_127_DATA + DDRSS1_PHY_128_DATA + DDRSS1_PHY_129_DATA + DDRSS1_PHY_130_DATA + DDRSS1_PHY_131_DATA + DDRSS1_PHY_132_DATA + DDRSS1_PHY_133_DATA + DDRSS1_PHY_134_DATA + DDRSS1_PHY_135_DATA + DDRSS1_PHY_136_DATA + DDRSS1_PHY_137_DATA + DDRSS1_PHY_138_DATA + DDRSS1_PHY_139_DATA + DDRSS1_PHY_140_DATA + DDRSS1_PHY_141_DATA + DDRSS1_PHY_142_DATA + DDRSS1_PHY_143_DATA + DDRSS1_PHY_144_DATA + DDRSS1_PHY_145_DATA + DDRSS1_PHY_146_DATA + DDRSS1_PHY_147_DATA + DDRSS1_PHY_148_DATA + DDRSS1_PHY_149_DATA + DDRSS1_PHY_150_DATA + DDRSS1_PHY_151_DATA + DDRSS1_PHY_152_DATA + DDRSS1_PHY_153_DATA + DDRSS1_PHY_154_DATA + DDRSS1_PHY_155_DATA + DDRSS1_PHY_156_DATA + DDRSS1_PHY_157_DATA + DDRSS1_PHY_158_DATA + DDRSS1_PHY_159_DATA + DDRSS1_PHY_160_DATA + DDRSS1_PHY_161_DATA + DDRSS1_PHY_162_DATA + DDRSS1_PHY_163_DATA + DDRSS1_PHY_164_DATA + DDRSS1_PHY_165_DATA + DDRSS1_PHY_166_DATA + DDRSS1_PHY_167_DATA + DDRSS1_PHY_168_DATA + DDRSS1_PHY_169_DATA + DDRSS1_PHY_170_DATA + DDRSS1_PHY_171_DATA + DDRSS1_PHY_172_DATA + DDRSS1_PHY_173_DATA + DDRSS1_PHY_174_DATA + DDRSS1_PHY_175_DATA + DDRSS1_PHY_176_DATA + DDRSS1_PHY_177_DATA + DDRSS1_PHY_178_DATA + DDRSS1_PHY_179_DATA + DDRSS1_PHY_180_DATA + DDRSS1_PHY_181_DATA + DDRSS1_PHY_182_DATA + DDRSS1_PHY_183_DATA + DDRSS1_PHY_184_DATA + DDRSS1_PHY_185_DATA + DDRSS1_PHY_186_DATA + DDRSS1_PHY_187_DATA + DDRSS1_PHY_188_DATA + DDRSS1_PHY_189_DATA + DDRSS1_PHY_190_DATA + DDRSS1_PHY_191_DATA + DDRSS1_PHY_192_DATA + DDRSS1_PHY_193_DATA + DDRSS1_PHY_194_DATA + DDRSS1_PHY_195_DATA + DDRSS1_PHY_196_DATA + DDRSS1_PHY_197_DATA + DDRSS1_PHY_198_DATA + DDRSS1_PHY_199_DATA + DDRSS1_PHY_200_DATA + DDRSS1_PHY_201_DATA + DDRSS1_PHY_202_DATA + DDRSS1_PHY_203_DATA + DDRSS1_PHY_204_DATA + DDRSS1_PHY_205_DATA + DDRSS1_PHY_206_DATA + DDRSS1_PHY_207_DATA + DDRSS1_PHY_208_DATA + DDRSS1_PHY_209_DATA + DDRSS1_PHY_210_DATA + DDRSS1_PHY_211_DATA + DDRSS1_PHY_212_DATA + DDRSS1_PHY_213_DATA + DDRSS1_PHY_214_DATA + DDRSS1_PHY_215_DATA + DDRSS1_PHY_216_DATA + DDRSS1_PHY_217_DATA + DDRSS1_PHY_218_DATA + DDRSS1_PHY_219_DATA + DDRSS1_PHY_220_DATA + DDRSS1_PHY_221_DATA + DDRSS1_PHY_222_DATA + DDRSS1_PHY_223_DATA + DDRSS1_PHY_224_DATA + DDRSS1_PHY_225_DATA + DDRSS1_PHY_226_DATA + DDRSS1_PHY_227_DATA + DDRSS1_PHY_228_DATA + DDRSS1_PHY_229_DATA + DDRSS1_PHY_230_DATA + DDRSS1_PHY_231_DATA + DDRSS1_PHY_232_DATA + DDRSS1_PHY_233_DATA + DDRSS1_PHY_234_DATA + DDRSS1_PHY_235_DATA + DDRSS1_PHY_236_DATA + DDRSS1_PHY_237_DATA + DDRSS1_PHY_238_DATA + DDRSS1_PHY_239_DATA + DDRSS1_PHY_240_DATA + DDRSS1_PHY_241_DATA + DDRSS1_PHY_242_DATA + DDRSS1_PHY_243_DATA + DDRSS1_PHY_244_DATA + DDRSS1_PHY_245_DATA + DDRSS1_PHY_246_DATA + DDRSS1_PHY_247_DATA + DDRSS1_PHY_248_DATA + DDRSS1_PHY_249_DATA + DDRSS1_PHY_250_DATA + DDRSS1_PHY_251_DATA + DDRSS1_PHY_252_DATA + DDRSS1_PHY_253_DATA + DDRSS1_PHY_254_DATA + DDRSS1_PHY_255_DATA + DDRSS1_PHY_256_DATA + DDRSS1_PHY_257_DATA + DDRSS1_PHY_258_DATA + DDRSS1_PHY_259_DATA + DDRSS1_PHY_260_DATA + DDRSS1_PHY_261_DATA + DDRSS1_PHY_262_DATA + DDRSS1_PHY_263_DATA + DDRSS1_PHY_264_DATA + DDRSS1_PHY_265_DATA + DDRSS1_PHY_266_DATA + DDRSS1_PHY_267_DATA + DDRSS1_PHY_268_DATA + DDRSS1_PHY_269_DATA + DDRSS1_PHY_270_DATA + DDRSS1_PHY_271_DATA + DDRSS1_PHY_272_DATA + DDRSS1_PHY_273_DATA + DDRSS1_PHY_274_DATA + DDRSS1_PHY_275_DATA + DDRSS1_PHY_276_DATA + DDRSS1_PHY_277_DATA + DDRSS1_PHY_278_DATA + DDRSS1_PHY_279_DATA + DDRSS1_PHY_280_DATA + DDRSS1_PHY_281_DATA + DDRSS1_PHY_282_DATA + DDRSS1_PHY_283_DATA + DDRSS1_PHY_284_DATA + DDRSS1_PHY_285_DATA + DDRSS1_PHY_286_DATA + DDRSS1_PHY_287_DATA + DDRSS1_PHY_288_DATA + DDRSS1_PHY_289_DATA + DDRSS1_PHY_290_DATA + DDRSS1_PHY_291_DATA + DDRSS1_PHY_292_DATA + DDRSS1_PHY_293_DATA + DDRSS1_PHY_294_DATA + DDRSS1_PHY_295_DATA + DDRSS1_PHY_296_DATA + DDRSS1_PHY_297_DATA + DDRSS1_PHY_298_DATA + DDRSS1_PHY_299_DATA + DDRSS1_PHY_300_DATA + DDRSS1_PHY_301_DATA + DDRSS1_PHY_302_DATA + DDRSS1_PHY_303_DATA + DDRSS1_PHY_304_DATA + DDRSS1_PHY_305_DATA + DDRSS1_PHY_306_DATA + DDRSS1_PHY_307_DATA + DDRSS1_PHY_308_DATA + DDRSS1_PHY_309_DATA + DDRSS1_PHY_310_DATA + DDRSS1_PHY_311_DATA + DDRSS1_PHY_312_DATA + DDRSS1_PHY_313_DATA + DDRSS1_PHY_314_DATA + DDRSS1_PHY_315_DATA + DDRSS1_PHY_316_DATA + DDRSS1_PHY_317_DATA + DDRSS1_PHY_318_DATA + DDRSS1_PHY_319_DATA + DDRSS1_PHY_320_DATA + DDRSS1_PHY_321_DATA + DDRSS1_PHY_322_DATA + DDRSS1_PHY_323_DATA + DDRSS1_PHY_324_DATA + DDRSS1_PHY_325_DATA + DDRSS1_PHY_326_DATA + DDRSS1_PHY_327_DATA + DDRSS1_PHY_328_DATA + DDRSS1_PHY_329_DATA + DDRSS1_PHY_330_DATA + DDRSS1_PHY_331_DATA + DDRSS1_PHY_332_DATA + DDRSS1_PHY_333_DATA + DDRSS1_PHY_334_DATA + DDRSS1_PHY_335_DATA + DDRSS1_PHY_336_DATA + DDRSS1_PHY_337_DATA + DDRSS1_PHY_338_DATA + DDRSS1_PHY_339_DATA + DDRSS1_PHY_340_DATA + DDRSS1_PHY_341_DATA + DDRSS1_PHY_342_DATA + DDRSS1_PHY_343_DATA + DDRSS1_PHY_344_DATA + DDRSS1_PHY_345_DATA + DDRSS1_PHY_346_DATA + DDRSS1_PHY_347_DATA + DDRSS1_PHY_348_DATA + DDRSS1_PHY_349_DATA + DDRSS1_PHY_350_DATA + DDRSS1_PHY_351_DATA + DDRSS1_PHY_352_DATA + DDRSS1_PHY_353_DATA + DDRSS1_PHY_354_DATA + DDRSS1_PHY_355_DATA + DDRSS1_PHY_356_DATA + DDRSS1_PHY_357_DATA + DDRSS1_PHY_358_DATA + DDRSS1_PHY_359_DATA + DDRSS1_PHY_360_DATA + DDRSS1_PHY_361_DATA + DDRSS1_PHY_362_DATA + DDRSS1_PHY_363_DATA + DDRSS1_PHY_364_DATA + DDRSS1_PHY_365_DATA + DDRSS1_PHY_366_DATA + DDRSS1_PHY_367_DATA + DDRSS1_PHY_368_DATA + DDRSS1_PHY_369_DATA + DDRSS1_PHY_370_DATA + DDRSS1_PHY_371_DATA + DDRSS1_PHY_372_DATA + DDRSS1_PHY_373_DATA + DDRSS1_PHY_374_DATA + DDRSS1_PHY_375_DATA + DDRSS1_PHY_376_DATA + DDRSS1_PHY_377_DATA + DDRSS1_PHY_378_DATA + DDRSS1_PHY_379_DATA + DDRSS1_PHY_380_DATA + DDRSS1_PHY_381_DATA + DDRSS1_PHY_382_DATA + DDRSS1_PHY_383_DATA + DDRSS1_PHY_384_DATA + DDRSS1_PHY_385_DATA + DDRSS1_PHY_386_DATA + DDRSS1_PHY_387_DATA + DDRSS1_PHY_388_DATA + DDRSS1_PHY_389_DATA + DDRSS1_PHY_390_DATA + DDRSS1_PHY_391_DATA + DDRSS1_PHY_392_DATA + DDRSS1_PHY_393_DATA + DDRSS1_PHY_394_DATA + DDRSS1_PHY_395_DATA + DDRSS1_PHY_396_DATA + DDRSS1_PHY_397_DATA + DDRSS1_PHY_398_DATA + DDRSS1_PHY_399_DATA + DDRSS1_PHY_400_DATA + DDRSS1_PHY_401_DATA + DDRSS1_PHY_402_DATA + DDRSS1_PHY_403_DATA + DDRSS1_PHY_404_DATA + DDRSS1_PHY_405_DATA + DDRSS1_PHY_406_DATA + DDRSS1_PHY_407_DATA + DDRSS1_PHY_408_DATA + DDRSS1_PHY_409_DATA + DDRSS1_PHY_410_DATA + DDRSS1_PHY_411_DATA + DDRSS1_PHY_412_DATA + DDRSS1_PHY_413_DATA + DDRSS1_PHY_414_DATA + DDRSS1_PHY_415_DATA + DDRSS1_PHY_416_DATA + DDRSS1_PHY_417_DATA + DDRSS1_PHY_418_DATA + DDRSS1_PHY_419_DATA + DDRSS1_PHY_420_DATA + DDRSS1_PHY_421_DATA + DDRSS1_PHY_422_DATA + DDRSS1_PHY_423_DATA + DDRSS1_PHY_424_DATA + DDRSS1_PHY_425_DATA + DDRSS1_PHY_426_DATA + DDRSS1_PHY_427_DATA + DDRSS1_PHY_428_DATA + DDRSS1_PHY_429_DATA + DDRSS1_PHY_430_DATA + DDRSS1_PHY_431_DATA + DDRSS1_PHY_432_DATA + DDRSS1_PHY_433_DATA + DDRSS1_PHY_434_DATA + DDRSS1_PHY_435_DATA + DDRSS1_PHY_436_DATA + DDRSS1_PHY_437_DATA + DDRSS1_PHY_438_DATA + DDRSS1_PHY_439_DATA + DDRSS1_PHY_440_DATA + DDRSS1_PHY_441_DATA + DDRSS1_PHY_442_DATA + DDRSS1_PHY_443_DATA + DDRSS1_PHY_444_DATA + DDRSS1_PHY_445_DATA + DDRSS1_PHY_446_DATA + DDRSS1_PHY_447_DATA + DDRSS1_PHY_448_DATA + DDRSS1_PHY_449_DATA + DDRSS1_PHY_450_DATA + DDRSS1_PHY_451_DATA + DDRSS1_PHY_452_DATA + DDRSS1_PHY_453_DATA + DDRSS1_PHY_454_DATA + DDRSS1_PHY_455_DATA + DDRSS1_PHY_456_DATA + DDRSS1_PHY_457_DATA + DDRSS1_PHY_458_DATA + DDRSS1_PHY_459_DATA + DDRSS1_PHY_460_DATA + DDRSS1_PHY_461_DATA + DDRSS1_PHY_462_DATA + DDRSS1_PHY_463_DATA + DDRSS1_PHY_464_DATA + DDRSS1_PHY_465_DATA + DDRSS1_PHY_466_DATA + DDRSS1_PHY_467_DATA + DDRSS1_PHY_468_DATA + DDRSS1_PHY_469_DATA + DDRSS1_PHY_470_DATA + DDRSS1_PHY_471_DATA + DDRSS1_PHY_472_DATA + DDRSS1_PHY_473_DATA + DDRSS1_PHY_474_DATA + DDRSS1_PHY_475_DATA + DDRSS1_PHY_476_DATA + DDRSS1_PHY_477_DATA + DDRSS1_PHY_478_DATA + DDRSS1_PHY_479_DATA + DDRSS1_PHY_480_DATA + DDRSS1_PHY_481_DATA + DDRSS1_PHY_482_DATA + DDRSS1_PHY_483_DATA + DDRSS1_PHY_484_DATA + DDRSS1_PHY_485_DATA + DDRSS1_PHY_486_DATA + DDRSS1_PHY_487_DATA + DDRSS1_PHY_488_DATA + DDRSS1_PHY_489_DATA + DDRSS1_PHY_490_DATA + DDRSS1_PHY_491_DATA + DDRSS1_PHY_492_DATA + DDRSS1_PHY_493_DATA + DDRSS1_PHY_494_DATA + DDRSS1_PHY_495_DATA + DDRSS1_PHY_496_DATA + DDRSS1_PHY_497_DATA + DDRSS1_PHY_498_DATA + DDRSS1_PHY_499_DATA + DDRSS1_PHY_500_DATA + DDRSS1_PHY_501_DATA + DDRSS1_PHY_502_DATA + DDRSS1_PHY_503_DATA + DDRSS1_PHY_504_DATA + DDRSS1_PHY_505_DATA + DDRSS1_PHY_506_DATA + DDRSS1_PHY_507_DATA + DDRSS1_PHY_508_DATA + DDRSS1_PHY_509_DATA + DDRSS1_PHY_510_DATA + DDRSS1_PHY_511_DATA + DDRSS1_PHY_512_DATA + DDRSS1_PHY_513_DATA + DDRSS1_PHY_514_DATA + DDRSS1_PHY_515_DATA + DDRSS1_PHY_516_DATA + DDRSS1_PHY_517_DATA + DDRSS1_PHY_518_DATA + DDRSS1_PHY_519_DATA + DDRSS1_PHY_520_DATA + DDRSS1_PHY_521_DATA + DDRSS1_PHY_522_DATA + DDRSS1_PHY_523_DATA + DDRSS1_PHY_524_DATA + DDRSS1_PHY_525_DATA + DDRSS1_PHY_526_DATA + DDRSS1_PHY_527_DATA + DDRSS1_PHY_528_DATA + DDRSS1_PHY_529_DATA + DDRSS1_PHY_530_DATA + DDRSS1_PHY_531_DATA + DDRSS1_PHY_532_DATA + DDRSS1_PHY_533_DATA + DDRSS1_PHY_534_DATA + DDRSS1_PHY_535_DATA + DDRSS1_PHY_536_DATA + DDRSS1_PHY_537_DATA + DDRSS1_PHY_538_DATA + DDRSS1_PHY_539_DATA + DDRSS1_PHY_540_DATA + DDRSS1_PHY_541_DATA + DDRSS1_PHY_542_DATA + DDRSS1_PHY_543_DATA + DDRSS1_PHY_544_DATA + DDRSS1_PHY_545_DATA + DDRSS1_PHY_546_DATA + DDRSS1_PHY_547_DATA + DDRSS1_PHY_548_DATA + DDRSS1_PHY_549_DATA + DDRSS1_PHY_550_DATA + DDRSS1_PHY_551_DATA + DDRSS1_PHY_552_DATA + DDRSS1_PHY_553_DATA + DDRSS1_PHY_554_DATA + DDRSS1_PHY_555_DATA + DDRSS1_PHY_556_DATA + DDRSS1_PHY_557_DATA + DDRSS1_PHY_558_DATA + DDRSS1_PHY_559_DATA + DDRSS1_PHY_560_DATA + DDRSS1_PHY_561_DATA + DDRSS1_PHY_562_DATA + DDRSS1_PHY_563_DATA + DDRSS1_PHY_564_DATA + DDRSS1_PHY_565_DATA + DDRSS1_PHY_566_DATA + DDRSS1_PHY_567_DATA + DDRSS1_PHY_568_DATA + DDRSS1_PHY_569_DATA + DDRSS1_PHY_570_DATA + DDRSS1_PHY_571_DATA + DDRSS1_PHY_572_DATA + DDRSS1_PHY_573_DATA + DDRSS1_PHY_574_DATA + DDRSS1_PHY_575_DATA + DDRSS1_PHY_576_DATA + DDRSS1_PHY_577_DATA + DDRSS1_PHY_578_DATA + DDRSS1_PHY_579_DATA + DDRSS1_PHY_580_DATA + DDRSS1_PHY_581_DATA + DDRSS1_PHY_582_DATA + DDRSS1_PHY_583_DATA + DDRSS1_PHY_584_DATA + DDRSS1_PHY_585_DATA + DDRSS1_PHY_586_DATA + DDRSS1_PHY_587_DATA + DDRSS1_PHY_588_DATA + DDRSS1_PHY_589_DATA + DDRSS1_PHY_590_DATA + DDRSS1_PHY_591_DATA + DDRSS1_PHY_592_DATA + DDRSS1_PHY_593_DATA + DDRSS1_PHY_594_DATA + DDRSS1_PHY_595_DATA + DDRSS1_PHY_596_DATA + DDRSS1_PHY_597_DATA + DDRSS1_PHY_598_DATA + DDRSS1_PHY_599_DATA + DDRSS1_PHY_600_DATA + DDRSS1_PHY_601_DATA + DDRSS1_PHY_602_DATA + DDRSS1_PHY_603_DATA + DDRSS1_PHY_604_DATA + DDRSS1_PHY_605_DATA + DDRSS1_PHY_606_DATA + DDRSS1_PHY_607_DATA + DDRSS1_PHY_608_DATA + DDRSS1_PHY_609_DATA + DDRSS1_PHY_610_DATA + DDRSS1_PHY_611_DATA + DDRSS1_PHY_612_DATA + DDRSS1_PHY_613_DATA + DDRSS1_PHY_614_DATA + DDRSS1_PHY_615_DATA + DDRSS1_PHY_616_DATA + DDRSS1_PHY_617_DATA + DDRSS1_PHY_618_DATA + DDRSS1_PHY_619_DATA + DDRSS1_PHY_620_DATA + DDRSS1_PHY_621_DATA + DDRSS1_PHY_622_DATA + DDRSS1_PHY_623_DATA + DDRSS1_PHY_624_DATA + DDRSS1_PHY_625_DATA + DDRSS1_PHY_626_DATA + DDRSS1_PHY_627_DATA + DDRSS1_PHY_628_DATA + DDRSS1_PHY_629_DATA + DDRSS1_PHY_630_DATA + DDRSS1_PHY_631_DATA + DDRSS1_PHY_632_DATA + DDRSS1_PHY_633_DATA + DDRSS1_PHY_634_DATA + DDRSS1_PHY_635_DATA + DDRSS1_PHY_636_DATA + DDRSS1_PHY_637_DATA + DDRSS1_PHY_638_DATA + DDRSS1_PHY_639_DATA + DDRSS1_PHY_640_DATA + DDRSS1_PHY_641_DATA + DDRSS1_PHY_642_DATA + DDRSS1_PHY_643_DATA + DDRSS1_PHY_644_DATA + DDRSS1_PHY_645_DATA + DDRSS1_PHY_646_DATA + DDRSS1_PHY_647_DATA + DDRSS1_PHY_648_DATA + DDRSS1_PHY_649_DATA + DDRSS1_PHY_650_DATA + DDRSS1_PHY_651_DATA + DDRSS1_PHY_652_DATA + DDRSS1_PHY_653_DATA + DDRSS1_PHY_654_DATA + DDRSS1_PHY_655_DATA + DDRSS1_PHY_656_DATA + DDRSS1_PHY_657_DATA + DDRSS1_PHY_658_DATA + DDRSS1_PHY_659_DATA + DDRSS1_PHY_660_DATA + DDRSS1_PHY_661_DATA + DDRSS1_PHY_662_DATA + DDRSS1_PHY_663_DATA + DDRSS1_PHY_664_DATA + DDRSS1_PHY_665_DATA + DDRSS1_PHY_666_DATA + DDRSS1_PHY_667_DATA + DDRSS1_PHY_668_DATA + DDRSS1_PHY_669_DATA + DDRSS1_PHY_670_DATA + DDRSS1_PHY_671_DATA + DDRSS1_PHY_672_DATA + DDRSS1_PHY_673_DATA + DDRSS1_PHY_674_DATA + DDRSS1_PHY_675_DATA + DDRSS1_PHY_676_DATA + DDRSS1_PHY_677_DATA + DDRSS1_PHY_678_DATA + DDRSS1_PHY_679_DATA + DDRSS1_PHY_680_DATA + DDRSS1_PHY_681_DATA + DDRSS1_PHY_682_DATA + DDRSS1_PHY_683_DATA + DDRSS1_PHY_684_DATA + DDRSS1_PHY_685_DATA + DDRSS1_PHY_686_DATA + DDRSS1_PHY_687_DATA + DDRSS1_PHY_688_DATA + DDRSS1_PHY_689_DATA + DDRSS1_PHY_690_DATA + DDRSS1_PHY_691_DATA + DDRSS1_PHY_692_DATA + DDRSS1_PHY_693_DATA + DDRSS1_PHY_694_DATA + DDRSS1_PHY_695_DATA + DDRSS1_PHY_696_DATA + DDRSS1_PHY_697_DATA + DDRSS1_PHY_698_DATA + DDRSS1_PHY_699_DATA + DDRSS1_PHY_700_DATA + DDRSS1_PHY_701_DATA + DDRSS1_PHY_702_DATA + DDRSS1_PHY_703_DATA + DDRSS1_PHY_704_DATA + DDRSS1_PHY_705_DATA + DDRSS1_PHY_706_DATA + DDRSS1_PHY_707_DATA + DDRSS1_PHY_708_DATA + DDRSS1_PHY_709_DATA + DDRSS1_PHY_710_DATA + DDRSS1_PHY_711_DATA + DDRSS1_PHY_712_DATA + DDRSS1_PHY_713_DATA + DDRSS1_PHY_714_DATA + DDRSS1_PHY_715_DATA + DDRSS1_PHY_716_DATA + DDRSS1_PHY_717_DATA + DDRSS1_PHY_718_DATA + DDRSS1_PHY_719_DATA + DDRSS1_PHY_720_DATA + DDRSS1_PHY_721_DATA + DDRSS1_PHY_722_DATA + DDRSS1_PHY_723_DATA + DDRSS1_PHY_724_DATA + DDRSS1_PHY_725_DATA + DDRSS1_PHY_726_DATA + DDRSS1_PHY_727_DATA + DDRSS1_PHY_728_DATA + DDRSS1_PHY_729_DATA + DDRSS1_PHY_730_DATA + DDRSS1_PHY_731_DATA + DDRSS1_PHY_732_DATA + DDRSS1_PHY_733_DATA + DDRSS1_PHY_734_DATA + DDRSS1_PHY_735_DATA + DDRSS1_PHY_736_DATA + DDRSS1_PHY_737_DATA + DDRSS1_PHY_738_DATA + DDRSS1_PHY_739_DATA + DDRSS1_PHY_740_DATA + DDRSS1_PHY_741_DATA + DDRSS1_PHY_742_DATA + DDRSS1_PHY_743_DATA + DDRSS1_PHY_744_DATA + DDRSS1_PHY_745_DATA + DDRSS1_PHY_746_DATA + DDRSS1_PHY_747_DATA + DDRSS1_PHY_748_DATA + DDRSS1_PHY_749_DATA + DDRSS1_PHY_750_DATA + DDRSS1_PHY_751_DATA + DDRSS1_PHY_752_DATA + DDRSS1_PHY_753_DATA + DDRSS1_PHY_754_DATA + DDRSS1_PHY_755_DATA + DDRSS1_PHY_756_DATA + DDRSS1_PHY_757_DATA + DDRSS1_PHY_758_DATA + DDRSS1_PHY_759_DATA + DDRSS1_PHY_760_DATA + DDRSS1_PHY_761_DATA + DDRSS1_PHY_762_DATA + DDRSS1_PHY_763_DATA + DDRSS1_PHY_764_DATA + DDRSS1_PHY_765_DATA + DDRSS1_PHY_766_DATA + DDRSS1_PHY_767_DATA + DDRSS1_PHY_768_DATA + DDRSS1_PHY_769_DATA + DDRSS1_PHY_770_DATA + DDRSS1_PHY_771_DATA + DDRSS1_PHY_772_DATA + DDRSS1_PHY_773_DATA + DDRSS1_PHY_774_DATA + DDRSS1_PHY_775_DATA + DDRSS1_PHY_776_DATA + DDRSS1_PHY_777_DATA + DDRSS1_PHY_778_DATA + DDRSS1_PHY_779_DATA + DDRSS1_PHY_780_DATA + DDRSS1_PHY_781_DATA + DDRSS1_PHY_782_DATA + DDRSS1_PHY_783_DATA + DDRSS1_PHY_784_DATA + DDRSS1_PHY_785_DATA + DDRSS1_PHY_786_DATA + DDRSS1_PHY_787_DATA + DDRSS1_PHY_788_DATA + DDRSS1_PHY_789_DATA + DDRSS1_PHY_790_DATA + DDRSS1_PHY_791_DATA + DDRSS1_PHY_792_DATA + DDRSS1_PHY_793_DATA + DDRSS1_PHY_794_DATA + DDRSS1_PHY_795_DATA + DDRSS1_PHY_796_DATA + DDRSS1_PHY_797_DATA + DDRSS1_PHY_798_DATA + DDRSS1_PHY_799_DATA + DDRSS1_PHY_800_DATA + DDRSS1_PHY_801_DATA + DDRSS1_PHY_802_DATA + DDRSS1_PHY_803_DATA + DDRSS1_PHY_804_DATA + DDRSS1_PHY_805_DATA + DDRSS1_PHY_806_DATA + DDRSS1_PHY_807_DATA + DDRSS1_PHY_808_DATA + DDRSS1_PHY_809_DATA + DDRSS1_PHY_810_DATA + DDRSS1_PHY_811_DATA + DDRSS1_PHY_812_DATA + DDRSS1_PHY_813_DATA + DDRSS1_PHY_814_DATA + DDRSS1_PHY_815_DATA + DDRSS1_PHY_816_DATA + DDRSS1_PHY_817_DATA + DDRSS1_PHY_818_DATA + DDRSS1_PHY_819_DATA + DDRSS1_PHY_820_DATA + DDRSS1_PHY_821_DATA + DDRSS1_PHY_822_DATA + DDRSS1_PHY_823_DATA + DDRSS1_PHY_824_DATA + DDRSS1_PHY_825_DATA + DDRSS1_PHY_826_DATA + DDRSS1_PHY_827_DATA + DDRSS1_PHY_828_DATA + DDRSS1_PHY_829_DATA + DDRSS1_PHY_830_DATA + DDRSS1_PHY_831_DATA + DDRSS1_PHY_832_DATA + DDRSS1_PHY_833_DATA + DDRSS1_PHY_834_DATA + DDRSS1_PHY_835_DATA + DDRSS1_PHY_836_DATA + DDRSS1_PHY_837_DATA + DDRSS1_PHY_838_DATA + DDRSS1_PHY_839_DATA + DDRSS1_PHY_840_DATA + DDRSS1_PHY_841_DATA + DDRSS1_PHY_842_DATA + DDRSS1_PHY_843_DATA + DDRSS1_PHY_844_DATA + DDRSS1_PHY_845_DATA + DDRSS1_PHY_846_DATA + DDRSS1_PHY_847_DATA + DDRSS1_PHY_848_DATA + DDRSS1_PHY_849_DATA + DDRSS1_PHY_850_DATA + DDRSS1_PHY_851_DATA + DDRSS1_PHY_852_DATA + DDRSS1_PHY_853_DATA + DDRSS1_PHY_854_DATA + DDRSS1_PHY_855_DATA + DDRSS1_PHY_856_DATA + DDRSS1_PHY_857_DATA + DDRSS1_PHY_858_DATA + DDRSS1_PHY_859_DATA + DDRSS1_PHY_860_DATA + DDRSS1_PHY_861_DATA + DDRSS1_PHY_862_DATA + DDRSS1_PHY_863_DATA + DDRSS1_PHY_864_DATA + DDRSS1_PHY_865_DATA + DDRSS1_PHY_866_DATA + DDRSS1_PHY_867_DATA + DDRSS1_PHY_868_DATA + DDRSS1_PHY_869_DATA + DDRSS1_PHY_870_DATA + DDRSS1_PHY_871_DATA + DDRSS1_PHY_872_DATA + DDRSS1_PHY_873_DATA + DDRSS1_PHY_874_DATA + DDRSS1_PHY_875_DATA + DDRSS1_PHY_876_DATA + DDRSS1_PHY_877_DATA + DDRSS1_PHY_878_DATA + DDRSS1_PHY_879_DATA + DDRSS1_PHY_880_DATA + DDRSS1_PHY_881_DATA + DDRSS1_PHY_882_DATA + DDRSS1_PHY_883_DATA + DDRSS1_PHY_884_DATA + DDRSS1_PHY_885_DATA + DDRSS1_PHY_886_DATA + DDRSS1_PHY_887_DATA + DDRSS1_PHY_888_DATA + DDRSS1_PHY_889_DATA + DDRSS1_PHY_890_DATA + DDRSS1_PHY_891_DATA + DDRSS1_PHY_892_DATA + DDRSS1_PHY_893_DATA + DDRSS1_PHY_894_DATA + DDRSS1_PHY_895_DATA + DDRSS1_PHY_896_DATA + DDRSS1_PHY_897_DATA + DDRSS1_PHY_898_DATA + DDRSS1_PHY_899_DATA + DDRSS1_PHY_900_DATA + DDRSS1_PHY_901_DATA + DDRSS1_PHY_902_DATA + DDRSS1_PHY_903_DATA + DDRSS1_PHY_904_DATA + DDRSS1_PHY_905_DATA + DDRSS1_PHY_906_DATA + DDRSS1_PHY_907_DATA + DDRSS1_PHY_908_DATA + DDRSS1_PHY_909_DATA + DDRSS1_PHY_910_DATA + DDRSS1_PHY_911_DATA + DDRSS1_PHY_912_DATA + DDRSS1_PHY_913_DATA + DDRSS1_PHY_914_DATA + DDRSS1_PHY_915_DATA + DDRSS1_PHY_916_DATA + DDRSS1_PHY_917_DATA + DDRSS1_PHY_918_DATA + DDRSS1_PHY_919_DATA + DDRSS1_PHY_920_DATA + DDRSS1_PHY_921_DATA + DDRSS1_PHY_922_DATA + DDRSS1_PHY_923_DATA + DDRSS1_PHY_924_DATA + DDRSS1_PHY_925_DATA + DDRSS1_PHY_926_DATA + DDRSS1_PHY_927_DATA + DDRSS1_PHY_928_DATA + DDRSS1_PHY_929_DATA + DDRSS1_PHY_930_DATA + DDRSS1_PHY_931_DATA + DDRSS1_PHY_932_DATA + DDRSS1_PHY_933_DATA + DDRSS1_PHY_934_DATA + DDRSS1_PHY_935_DATA + DDRSS1_PHY_936_DATA + DDRSS1_PHY_937_DATA + DDRSS1_PHY_938_DATA + DDRSS1_PHY_939_DATA + DDRSS1_PHY_940_DATA + DDRSS1_PHY_941_DATA + DDRSS1_PHY_942_DATA + DDRSS1_PHY_943_DATA + DDRSS1_PHY_944_DATA + DDRSS1_PHY_945_DATA + DDRSS1_PHY_946_DATA + DDRSS1_PHY_947_DATA + DDRSS1_PHY_948_DATA + DDRSS1_PHY_949_DATA + DDRSS1_PHY_950_DATA + DDRSS1_PHY_951_DATA + DDRSS1_PHY_952_DATA + DDRSS1_PHY_953_DATA + DDRSS1_PHY_954_DATA + DDRSS1_PHY_955_DATA + DDRSS1_PHY_956_DATA + DDRSS1_PHY_957_DATA + DDRSS1_PHY_958_DATA + DDRSS1_PHY_959_DATA + DDRSS1_PHY_960_DATA + DDRSS1_PHY_961_DATA + DDRSS1_PHY_962_DATA + DDRSS1_PHY_963_DATA + DDRSS1_PHY_964_DATA + DDRSS1_PHY_965_DATA + DDRSS1_PHY_966_DATA + DDRSS1_PHY_967_DATA + DDRSS1_PHY_968_DATA + DDRSS1_PHY_969_DATA + DDRSS1_PHY_970_DATA + DDRSS1_PHY_971_DATA + DDRSS1_PHY_972_DATA + DDRSS1_PHY_973_DATA + DDRSS1_PHY_974_DATA + DDRSS1_PHY_975_DATA + DDRSS1_PHY_976_DATA + DDRSS1_PHY_977_DATA + DDRSS1_PHY_978_DATA + DDRSS1_PHY_979_DATA + DDRSS1_PHY_980_DATA + DDRSS1_PHY_981_DATA + DDRSS1_PHY_982_DATA + DDRSS1_PHY_983_DATA + DDRSS1_PHY_984_DATA + DDRSS1_PHY_985_DATA + DDRSS1_PHY_986_DATA + DDRSS1_PHY_987_DATA + DDRSS1_PHY_988_DATA + DDRSS1_PHY_989_DATA + DDRSS1_PHY_990_DATA + DDRSS1_PHY_991_DATA + DDRSS1_PHY_992_DATA + DDRSS1_PHY_993_DATA + DDRSS1_PHY_994_DATA + DDRSS1_PHY_995_DATA + DDRSS1_PHY_996_DATA + DDRSS1_PHY_997_DATA + DDRSS1_PHY_998_DATA + DDRSS1_PHY_999_DATA + DDRSS1_PHY_1000_DATA + DDRSS1_PHY_1001_DATA + DDRSS1_PHY_1002_DATA + DDRSS1_PHY_1003_DATA + DDRSS1_PHY_1004_DATA + DDRSS1_PHY_1005_DATA + DDRSS1_PHY_1006_DATA + DDRSS1_PHY_1007_DATA + DDRSS1_PHY_1008_DATA + DDRSS1_PHY_1009_DATA + DDRSS1_PHY_1010_DATA + DDRSS1_PHY_1011_DATA + DDRSS1_PHY_1012_DATA + DDRSS1_PHY_1013_DATA + DDRSS1_PHY_1014_DATA + DDRSS1_PHY_1015_DATA + DDRSS1_PHY_1016_DATA + DDRSS1_PHY_1017_DATA + DDRSS1_PHY_1018_DATA + DDRSS1_PHY_1019_DATA + DDRSS1_PHY_1020_DATA + DDRSS1_PHY_1021_DATA + DDRSS1_PHY_1022_DATA + DDRSS1_PHY_1023_DATA + DDRSS1_PHY_1024_DATA + DDRSS1_PHY_1025_DATA + DDRSS1_PHY_1026_DATA + DDRSS1_PHY_1027_DATA + DDRSS1_PHY_1028_DATA + DDRSS1_PHY_1029_DATA + DDRSS1_PHY_1030_DATA + DDRSS1_PHY_1031_DATA + DDRSS1_PHY_1032_DATA + DDRSS1_PHY_1033_DATA + DDRSS1_PHY_1034_DATA + DDRSS1_PHY_1035_DATA + DDRSS1_PHY_1036_DATA + DDRSS1_PHY_1037_DATA + DDRSS1_PHY_1038_DATA + DDRSS1_PHY_1039_DATA + DDRSS1_PHY_1040_DATA + DDRSS1_PHY_1041_DATA + DDRSS1_PHY_1042_DATA + DDRSS1_PHY_1043_DATA + DDRSS1_PHY_1044_DATA + DDRSS1_PHY_1045_DATA + DDRSS1_PHY_1046_DATA + DDRSS1_PHY_1047_DATA + DDRSS1_PHY_1048_DATA + DDRSS1_PHY_1049_DATA + DDRSS1_PHY_1050_DATA + DDRSS1_PHY_1051_DATA + DDRSS1_PHY_1052_DATA + DDRSS1_PHY_1053_DATA + DDRSS1_PHY_1054_DATA + DDRSS1_PHY_1055_DATA + DDRSS1_PHY_1056_DATA + DDRSS1_PHY_1057_DATA + DDRSS1_PHY_1058_DATA + DDRSS1_PHY_1059_DATA + DDRSS1_PHY_1060_DATA + DDRSS1_PHY_1061_DATA + DDRSS1_PHY_1062_DATA + DDRSS1_PHY_1063_DATA + DDRSS1_PHY_1064_DATA + DDRSS1_PHY_1065_DATA + DDRSS1_PHY_1066_DATA + DDRSS1_PHY_1067_DATA + DDRSS1_PHY_1068_DATA + DDRSS1_PHY_1069_DATA + DDRSS1_PHY_1070_DATA + DDRSS1_PHY_1071_DATA + DDRSS1_PHY_1072_DATA + DDRSS1_PHY_1073_DATA + DDRSS1_PHY_1074_DATA + DDRSS1_PHY_1075_DATA + DDRSS1_PHY_1076_DATA + DDRSS1_PHY_1077_DATA + DDRSS1_PHY_1078_DATA + DDRSS1_PHY_1079_DATA + DDRSS1_PHY_1080_DATA + DDRSS1_PHY_1081_DATA + DDRSS1_PHY_1082_DATA + DDRSS1_PHY_1083_DATA + DDRSS1_PHY_1084_DATA + DDRSS1_PHY_1085_DATA + DDRSS1_PHY_1086_DATA + DDRSS1_PHY_1087_DATA + DDRSS1_PHY_1088_DATA + DDRSS1_PHY_1089_DATA + DDRSS1_PHY_1090_DATA + DDRSS1_PHY_1091_DATA + DDRSS1_PHY_1092_DATA + DDRSS1_PHY_1093_DATA + DDRSS1_PHY_1094_DATA + DDRSS1_PHY_1095_DATA + DDRSS1_PHY_1096_DATA + DDRSS1_PHY_1097_DATA + DDRSS1_PHY_1098_DATA + DDRSS1_PHY_1099_DATA + DDRSS1_PHY_1100_DATA + DDRSS1_PHY_1101_DATA + DDRSS1_PHY_1102_DATA + DDRSS1_PHY_1103_DATA + DDRSS1_PHY_1104_DATA + DDRSS1_PHY_1105_DATA + DDRSS1_PHY_1106_DATA + DDRSS1_PHY_1107_DATA + DDRSS1_PHY_1108_DATA + DDRSS1_PHY_1109_DATA + DDRSS1_PHY_1110_DATA + DDRSS1_PHY_1111_DATA + DDRSS1_PHY_1112_DATA + DDRSS1_PHY_1113_DATA + DDRSS1_PHY_1114_DATA + DDRSS1_PHY_1115_DATA + DDRSS1_PHY_1116_DATA + DDRSS1_PHY_1117_DATA + DDRSS1_PHY_1118_DATA + DDRSS1_PHY_1119_DATA + DDRSS1_PHY_1120_DATA + DDRSS1_PHY_1121_DATA + DDRSS1_PHY_1122_DATA + DDRSS1_PHY_1123_DATA + DDRSS1_PHY_1124_DATA + DDRSS1_PHY_1125_DATA + DDRSS1_PHY_1126_DATA + DDRSS1_PHY_1127_DATA + DDRSS1_PHY_1128_DATA + DDRSS1_PHY_1129_DATA + DDRSS1_PHY_1130_DATA + DDRSS1_PHY_1131_DATA + DDRSS1_PHY_1132_DATA + DDRSS1_PHY_1133_DATA + DDRSS1_PHY_1134_DATA + DDRSS1_PHY_1135_DATA + DDRSS1_PHY_1136_DATA + DDRSS1_PHY_1137_DATA + DDRSS1_PHY_1138_DATA + DDRSS1_PHY_1139_DATA + DDRSS1_PHY_1140_DATA + DDRSS1_PHY_1141_DATA + DDRSS1_PHY_1142_DATA + DDRSS1_PHY_1143_DATA + DDRSS1_PHY_1144_DATA + DDRSS1_PHY_1145_DATA + DDRSS1_PHY_1146_DATA + DDRSS1_PHY_1147_DATA + DDRSS1_PHY_1148_DATA + DDRSS1_PHY_1149_DATA + DDRSS1_PHY_1150_DATA + DDRSS1_PHY_1151_DATA + DDRSS1_PHY_1152_DATA + DDRSS1_PHY_1153_DATA + DDRSS1_PHY_1154_DATA + DDRSS1_PHY_1155_DATA + DDRSS1_PHY_1156_DATA + DDRSS1_PHY_1157_DATA + DDRSS1_PHY_1158_DATA + DDRSS1_PHY_1159_DATA + DDRSS1_PHY_1160_DATA + DDRSS1_PHY_1161_DATA + DDRSS1_PHY_1162_DATA + DDRSS1_PHY_1163_DATA + DDRSS1_PHY_1164_DATA + DDRSS1_PHY_1165_DATA + DDRSS1_PHY_1166_DATA + DDRSS1_PHY_1167_DATA + DDRSS1_PHY_1168_DATA + DDRSS1_PHY_1169_DATA + DDRSS1_PHY_1170_DATA + DDRSS1_PHY_1171_DATA + DDRSS1_PHY_1172_DATA + DDRSS1_PHY_1173_DATA + DDRSS1_PHY_1174_DATA + DDRSS1_PHY_1175_DATA + DDRSS1_PHY_1176_DATA + DDRSS1_PHY_1177_DATA + DDRSS1_PHY_1178_DATA + DDRSS1_PHY_1179_DATA + DDRSS1_PHY_1180_DATA + DDRSS1_PHY_1181_DATA + DDRSS1_PHY_1182_DATA + DDRSS1_PHY_1183_DATA + DDRSS1_PHY_1184_DATA + DDRSS1_PHY_1185_DATA + DDRSS1_PHY_1186_DATA + DDRSS1_PHY_1187_DATA + DDRSS1_PHY_1188_DATA + DDRSS1_PHY_1189_DATA + DDRSS1_PHY_1190_DATA + DDRSS1_PHY_1191_DATA + DDRSS1_PHY_1192_DATA + DDRSS1_PHY_1193_DATA + DDRSS1_PHY_1194_DATA + DDRSS1_PHY_1195_DATA + DDRSS1_PHY_1196_DATA + DDRSS1_PHY_1197_DATA + DDRSS1_PHY_1198_DATA + DDRSS1_PHY_1199_DATA + DDRSS1_PHY_1200_DATA + DDRSS1_PHY_1201_DATA + DDRSS1_PHY_1202_DATA + DDRSS1_PHY_1203_DATA + DDRSS1_PHY_1204_DATA + DDRSS1_PHY_1205_DATA + DDRSS1_PHY_1206_DATA + DDRSS1_PHY_1207_DATA + DDRSS1_PHY_1208_DATA + DDRSS1_PHY_1209_DATA + DDRSS1_PHY_1210_DATA + DDRSS1_PHY_1211_DATA + DDRSS1_PHY_1212_DATA + DDRSS1_PHY_1213_DATA + DDRSS1_PHY_1214_DATA + DDRSS1_PHY_1215_DATA + DDRSS1_PHY_1216_DATA + DDRSS1_PHY_1217_DATA + DDRSS1_PHY_1218_DATA + DDRSS1_PHY_1219_DATA + DDRSS1_PHY_1220_DATA + DDRSS1_PHY_1221_DATA + DDRSS1_PHY_1222_DATA + DDRSS1_PHY_1223_DATA + DDRSS1_PHY_1224_DATA + DDRSS1_PHY_1225_DATA + DDRSS1_PHY_1226_DATA + DDRSS1_PHY_1227_DATA + DDRSS1_PHY_1228_DATA + DDRSS1_PHY_1229_DATA + DDRSS1_PHY_1230_DATA + DDRSS1_PHY_1231_DATA + DDRSS1_PHY_1232_DATA + DDRSS1_PHY_1233_DATA + DDRSS1_PHY_1234_DATA + DDRSS1_PHY_1235_DATA + DDRSS1_PHY_1236_DATA + DDRSS1_PHY_1237_DATA + DDRSS1_PHY_1238_DATA + DDRSS1_PHY_1239_DATA + DDRSS1_PHY_1240_DATA + DDRSS1_PHY_1241_DATA + DDRSS1_PHY_1242_DATA + DDRSS1_PHY_1243_DATA + DDRSS1_PHY_1244_DATA + DDRSS1_PHY_1245_DATA + DDRSS1_PHY_1246_DATA + DDRSS1_PHY_1247_DATA + DDRSS1_PHY_1248_DATA + DDRSS1_PHY_1249_DATA + DDRSS1_PHY_1250_DATA + DDRSS1_PHY_1251_DATA + DDRSS1_PHY_1252_DATA + DDRSS1_PHY_1253_DATA + DDRSS1_PHY_1254_DATA + DDRSS1_PHY_1255_DATA + DDRSS1_PHY_1256_DATA + DDRSS1_PHY_1257_DATA + DDRSS1_PHY_1258_DATA + DDRSS1_PHY_1259_DATA + DDRSS1_PHY_1260_DATA + DDRSS1_PHY_1261_DATA + DDRSS1_PHY_1262_DATA + DDRSS1_PHY_1263_DATA + DDRSS1_PHY_1264_DATA + DDRSS1_PHY_1265_DATA + DDRSS1_PHY_1266_DATA + DDRSS1_PHY_1267_DATA + DDRSS1_PHY_1268_DATA + DDRSS1_PHY_1269_DATA + DDRSS1_PHY_1270_DATA + DDRSS1_PHY_1271_DATA + DDRSS1_PHY_1272_DATA + DDRSS1_PHY_1273_DATA + DDRSS1_PHY_1274_DATA + DDRSS1_PHY_1275_DATA + DDRSS1_PHY_1276_DATA + DDRSS1_PHY_1277_DATA + DDRSS1_PHY_1278_DATA + DDRSS1_PHY_1279_DATA + DDRSS1_PHY_1280_DATA + DDRSS1_PHY_1281_DATA + DDRSS1_PHY_1282_DATA + DDRSS1_PHY_1283_DATA + DDRSS1_PHY_1284_DATA + DDRSS1_PHY_1285_DATA + DDRSS1_PHY_1286_DATA + DDRSS1_PHY_1287_DATA + DDRSS1_PHY_1288_DATA + DDRSS1_PHY_1289_DATA + DDRSS1_PHY_1290_DATA + DDRSS1_PHY_1291_DATA + DDRSS1_PHY_1292_DATA + DDRSS1_PHY_1293_DATA + DDRSS1_PHY_1294_DATA + DDRSS1_PHY_1295_DATA + DDRSS1_PHY_1296_DATA + DDRSS1_PHY_1297_DATA + DDRSS1_PHY_1298_DATA + DDRSS1_PHY_1299_DATA + DDRSS1_PHY_1300_DATA + DDRSS1_PHY_1301_DATA + DDRSS1_PHY_1302_DATA + DDRSS1_PHY_1303_DATA + DDRSS1_PHY_1304_DATA + DDRSS1_PHY_1305_DATA + DDRSS1_PHY_1306_DATA + DDRSS1_PHY_1307_DATA + DDRSS1_PHY_1308_DATA + DDRSS1_PHY_1309_DATA + DDRSS1_PHY_1310_DATA + DDRSS1_PHY_1311_DATA + DDRSS1_PHY_1312_DATA + DDRSS1_PHY_1313_DATA + DDRSS1_PHY_1314_DATA + DDRSS1_PHY_1315_DATA + DDRSS1_PHY_1316_DATA + DDRSS1_PHY_1317_DATA + DDRSS1_PHY_1318_DATA + DDRSS1_PHY_1319_DATA + DDRSS1_PHY_1320_DATA + DDRSS1_PHY_1321_DATA + DDRSS1_PHY_1322_DATA + DDRSS1_PHY_1323_DATA + DDRSS1_PHY_1324_DATA + DDRSS1_PHY_1325_DATA + DDRSS1_PHY_1326_DATA + DDRSS1_PHY_1327_DATA + DDRSS1_PHY_1328_DATA + DDRSS1_PHY_1329_DATA + DDRSS1_PHY_1330_DATA + DDRSS1_PHY_1331_DATA + DDRSS1_PHY_1332_DATA + DDRSS1_PHY_1333_DATA + DDRSS1_PHY_1334_DATA + DDRSS1_PHY_1335_DATA + DDRSS1_PHY_1336_DATA + DDRSS1_PHY_1337_DATA + DDRSS1_PHY_1338_DATA + DDRSS1_PHY_1339_DATA + DDRSS1_PHY_1340_DATA + DDRSS1_PHY_1341_DATA + DDRSS1_PHY_1342_DATA + DDRSS1_PHY_1343_DATA + DDRSS1_PHY_1344_DATA + DDRSS1_PHY_1345_DATA + DDRSS1_PHY_1346_DATA + DDRSS1_PHY_1347_DATA + DDRSS1_PHY_1348_DATA + DDRSS1_PHY_1349_DATA + DDRSS1_PHY_1350_DATA + DDRSS1_PHY_1351_DATA + DDRSS1_PHY_1352_DATA + DDRSS1_PHY_1353_DATA + DDRSS1_PHY_1354_DATA + DDRSS1_PHY_1355_DATA + DDRSS1_PHY_1356_DATA + DDRSS1_PHY_1357_DATA + DDRSS1_PHY_1358_DATA + DDRSS1_PHY_1359_DATA + DDRSS1_PHY_1360_DATA + DDRSS1_PHY_1361_DATA + DDRSS1_PHY_1362_DATA + DDRSS1_PHY_1363_DATA + DDRSS1_PHY_1364_DATA + DDRSS1_PHY_1365_DATA + DDRSS1_PHY_1366_DATA + DDRSS1_PHY_1367_DATA + DDRSS1_PHY_1368_DATA + DDRSS1_PHY_1369_DATA + DDRSS1_PHY_1370_DATA + DDRSS1_PHY_1371_DATA + DDRSS1_PHY_1372_DATA + DDRSS1_PHY_1373_DATA + DDRSS1_PHY_1374_DATA + DDRSS1_PHY_1375_DATA + DDRSS1_PHY_1376_DATA + DDRSS1_PHY_1377_DATA + DDRSS1_PHY_1378_DATA + DDRSS1_PHY_1379_DATA + DDRSS1_PHY_1380_DATA + DDRSS1_PHY_1381_DATA + DDRSS1_PHY_1382_DATA + DDRSS1_PHY_1383_DATA + DDRSS1_PHY_1384_DATA + DDRSS1_PHY_1385_DATA + DDRSS1_PHY_1386_DATA + DDRSS1_PHY_1387_DATA + DDRSS1_PHY_1388_DATA + DDRSS1_PHY_1389_DATA + DDRSS1_PHY_1390_DATA + DDRSS1_PHY_1391_DATA + DDRSS1_PHY_1392_DATA + DDRSS1_PHY_1393_DATA + DDRSS1_PHY_1394_DATA + DDRSS1_PHY_1395_DATA + DDRSS1_PHY_1396_DATA + DDRSS1_PHY_1397_DATA + DDRSS1_PHY_1398_DATA + DDRSS1_PHY_1399_DATA + DDRSS1_PHY_1400_DATA + DDRSS1_PHY_1401_DATA + DDRSS1_PHY_1402_DATA + DDRSS1_PHY_1403_DATA + DDRSS1_PHY_1404_DATA + DDRSS1_PHY_1405_DATA + DDRSS1_PHY_1406_DATA + DDRSS1_PHY_1407_DATA + DDRSS1_PHY_1408_DATA + DDRSS1_PHY_1409_DATA + DDRSS1_PHY_1410_DATA + DDRSS1_PHY_1411_DATA + DDRSS1_PHY_1412_DATA + DDRSS1_PHY_1413_DATA + DDRSS1_PHY_1414_DATA + DDRSS1_PHY_1415_DATA + DDRSS1_PHY_1416_DATA + DDRSS1_PHY_1417_DATA + DDRSS1_PHY_1418_DATA + DDRSS1_PHY_1419_DATA + DDRSS1_PHY_1420_DATA + DDRSS1_PHY_1421_DATA + DDRSS1_PHY_1422_DATA + >; + }; + }; +}; diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi deleted file mode 100644 index 61b1433af91..00000000000 --- a/arch/arm/dts/px30-evb-u-boot.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * (C) Copyright 2020 Rockchip Electronics Co., Ltd - */ - -#include "px30-u-boot.dtsi" - -&rng { - status = "okay"; -}; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index abc6b49e666..157d0ea6930 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -24,7 +24,6 @@ rng: rng@ff0b0000 { compatible = "rockchip,cryptov2-rng"; reg = <0x0 0xff0b0000 0x0 0x4000>; - status = "disabled"; }; }; diff --git a/arch/arm/dts/qemu-sbsa.dts b/arch/arm/dts/qemu-sbsa.dts index ed00e501366..099b51b927f 100644 --- a/arch/arm/dts/qemu-sbsa.dts +++ b/arch/arm/dts/qemu-sbsa.dts @@ -97,11 +97,13 @@ /bits/ 64 <0 0>, /bits/ 64 <SBSA_GIC_HBASE_ADDR SBSA_GIC_HBASE_LENGTH>, /bits/ 64 <SBSA_GIC_VBASE_ADDR SBSA_GIC_VBASE_LENGTH>; - }; - its { - compatible = "arm,gic-v3-its"; - status = "disabled"; + its: msi-controller { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/rk3328-generic-u-boot.dtsi b/arch/arm/dts/rk3328-generic-u-boot.dtsi new file mode 100644 index 00000000000..af890e912dd --- /dev/null +++ b/arch/arm/dts/rk3328-generic-u-boot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3328-u-boot.dtsi" + +&gpio0 { + /delete-property/ bootph-pre-ram; +}; + +&pcfg_pull_down_4ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&spi0m2_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0m2_cs0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0m2_rx { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi0m2_tx { + bootph-pre-ram; + bootph-some-ram; +}; diff --git a/arch/arm/dts/rk3328-generic.dts b/arch/arm/dts/rk3328-generic.dts new file mode 100644 index 00000000000..af0da845716 --- /dev/null +++ b/arch/arm/dts/rk3328-generic.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3328 with eMMC, SD-card, SPI flash and USB OTG enabled + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Generic RK3328"; + compatible = "rockchip,rk3328"; + + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&sdmmc0m1_pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down_4ma>; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4 &sdmmc0m1_pin>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-generic-u-boot.dtsi b/arch/arm/dts/rk3399-generic-u-boot.dtsi new file mode 100644 index 00000000000..d977b642f8d --- /dev/null +++ b/arch/arm/dts/rk3399-generic-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3399-u-boot.dtsi" + +&spi1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3399-generic.dts b/arch/arm/dts/rk3399-generic.dts new file mode 100644 index 00000000000..c698f59c565 --- /dev/null +++ b/arch/arm/dts/rk3399-generic.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3399 with eMMC, SD-card, SPI flash and USB OTG enabled + */ + +/dts-v1/; +#include "rk3399.dtsi" + +/ { + model = "Generic RK3399"; + compatible = "rockchip,rk3399"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi new file mode 100644 index 00000000000..cc830b51456 --- /dev/null +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts new file mode 100644 index 00000000000..792d3e04a4c --- /dev/null +++ b/arch/arm/dts/rk3528-generic.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3528 with eMMC enabled + */ + +/dts-v1/; +#include "rk3528.dtsi" + +/ { + model = "Generic RK3528"; + compatible = "rockchip,rk3528"; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi new file mode 100644 index 00000000000..9c2f03a786c --- /dev/null +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi new file mode 100644 index 00000000000..eb6a55cd5c9 --- /dev/null +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rockchip-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + + dmc { + compatible = "rockchip,rk3528-dmc"; + bootph-all; + }; + + soc { + rng: rng@ffc50000 { + compatible = "rockchip,rkrng"; + reg = <0x0 0xffc50000 0x0 0x200>; + }; + + otp: nvmem@ffce0000 { + compatible = "rockchip,rk3528-otp"; + reg = <0x0 0xffce0000 0x0 0x4000>; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + rockchip,default-sample-phase = <90>; + status = "disabled"; + }; + }; +}; + +&cru { + bootph-all; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_strb { + bootph-pre-ram; + bootph-some-ram; +}; + +&gmac0_clk { + bootph-all; +}; + +&ioc_grf { + bootph-all; +}; + +&otp { + bootph-some-ram; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&sdhci { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&uart0 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart0m0_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 24a976cf7e2..87186973953 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -21,11 +21,6 @@ bootph-all; }; - rng: rng@fe388000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xfe388000 0x0 0x2000>; - }; - otp: nvmem@fe38c000 { compatible = "rockchip,rk3568-otp"; reg = <0x0 0xfe38c000 0x0 0x4000>; @@ -121,6 +116,10 @@ bootph-all; }; +&rng { + status = "okay"; +}; + &sdhci { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi new file mode 100644 index 00000000000..97240345ed4 --- /dev/null +++ b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Joshua Riek <jjriek@verizon.net> + * + */ + +#include "rk3576-u-boot.dtsi" + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi new file mode 100644 index 00000000000..be99a48a630 --- /dev/null +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2025 Rockchip Electronics Co., Ltd + */ + +#include "rockchip-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + + dmc { + compatible = "rockchip,rk3576-dmc"; + bootph-all; + }; +}; + +&cru { + bootph-all; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_rstnout { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_strb { + bootph-pre-ram; + bootph-some-ram; +}; + +&ioc_grf { + bootph-all; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_drv_level_2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up_drv_level_3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl { + bootph-all; +}; + +&pmu1_grf { + bootph-all; +}; + +&sdhci { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + u-boot,spl-fifo-mode; +}; + +&sdmmc0_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc0_pwren { + bootph-pre-ram; + bootph-some-ram; +}; + +&sys_grf { + bootph-all; +}; + +&uart0 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart0m0_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 8880d162b11..5eeb138f351 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -18,11 +18,6 @@ compatible = "rockchip,rk3588-dmc"; bootph-all; }; - - rng: rng@fe378000 { - compatible = "rockchip,trngv1"; - reg = <0x0 0xfe378000 0x0 0x200>; - }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 60de9140226..7631dfaa07f 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -70,6 +70,19 @@ #size-cells = <1>; ranges; + usb0: gadget@500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sam9x60-udc"; + reg = <0x500000 0x100000>, + <0xf803c000 0x400>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE 8>; + clock-names = "pclk", "hclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE 8>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 7b62fffb4ff..62191ff5d97 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -778,6 +778,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xf8048030 0x10>; clocks = <&h32ck>; + bootph-all; }; watchdog: watchdog@f8048040 { diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 8d6503dd091..874e71b5ca4 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -208,7 +208,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; @@ -218,7 +219,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; }; @@ -673,6 +675,17 @@ bootph-all; }; +&gpio1 { + /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */ + portb: gpio-controller@0{ + sdio_sel { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + &i2c0 { reset-names = "i2c"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index d7ab58267eb..8d7dc0945ab 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -25,34 +25,44 @@ /* * Both Memory base address and size default info is retrieved from HW setting. * Reconfiguration / Overwrite these info can be done with examples below. - */ - /* + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * * Example for memory size with 2GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>; * }; - */ - /* + * * Example for memory size with 8GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x1 0x80000000>; * }; - */ - /* + * * Example for memory size with 32GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x7 0x80000000>; * }; - */ - /* + * * Example for memory size with 512GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x7 0x80000000>, * <0x88 0x00000000 0x78 0x00000000>; * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; */ chosen { diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 15306db6002..93a8e0697d6 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -106,8 +106,13 @@ arch = "arm64"; os = "linux"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x86000000>; + entry = <0x86000000>; + #else load = <0x6000000>; entry = <0x6000000>; + #endif kernel_blob: blob-ext { filename = "Image"; }; diff --git a/arch/arm/dts/st-pincfg.h b/arch/arm/dts/st-pincfg.h deleted file mode 100644 index d8055120229..00000000000 --- a/arch/arm/dts/st-pincfg.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ST_PINCFG_H_ -#define _ST_PINCFG_H_ - -/* Alternate functions */ -#define ALT1 1 -#define ALT2 2 -#define ALT3 3 -#define ALT4 4 -#define ALT5 5 -#define ALT6 6 -#define ALT7 7 - -/* Output enable */ -#define OE (1 << 27) -/* Pull Up */ -#define PU (1 << 26) -/* Open Drain */ -#define OD (1 << 25) -#define RT (1 << 23) -#define INVERTCLK (1 << 22) -#define CLKNOTDATA (1 << 21) -#define DOUBLE_EDGE (1 << 20) -#define CLK_A (0 << 18) -#define CLK_B (1 << 18) -#define CLK_C (2 << 18) -#define CLK_D (3 << 18) - -/* User-frendly defines for Pin Direction */ - /* oe = 0, pu = 0, od = 0 */ -#define IN (0) - /* oe = 0, pu = 1, od = 0 */ -#define IN_PU (PU) - /* oe = 1, pu = 0, od = 0 */ -#define OUT (OE) - /* oe = 1, pu = 0, od = 1 */ -#define BIDIR (OE | OD) - /* oe = 1, pu = 1, od = 1 */ -#define BIDIR_PU (OE | PU | OD) - -/* RETIME_TYPE */ -/* - * B Mode - * Bypass retime with optional delay parameter - */ -#define BYPASS (0) -/* - * R0, R1, R0D, R1D modes - * single-edge data non inverted clock, retime data with clk - */ -#define SE_NICLK_IO (RT) -/* - * RIV0, RIV1, RIV0D, RIV1D modes - * single-edge data inverted clock, retime data with clk - */ -#define SE_ICLK_IO (RT | INVERTCLK) -/* - * R0E, R1E, R0ED, R1ED modes - * double-edge data, retime data with clk - */ -#define DE_IO (RT | DOUBLE_EDGE) -/* - * CIV0, CIV1 modes with inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define ICLK (RT | CLKNOTDATA | INVERTCLK) -/* - * CLK0, CLK1 modes with non-inverted clock - * Retiming the clk pins will park clock & reduce the noise within the core. - */ -#define NICLK (RT | CLKNOTDATA) -#endif /* _ST_PINCFG_H_ */ diff --git a/arch/arm/dts/stih407-clock.dtsi b/arch/arm/dts/stih407-clock.dtsi deleted file mode 100644 index 1ab40db7c91..00000000000 --- a/arch/arm/dts/stih407-clock.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include <dt-bindings/clock/stih407-clks.h> -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0"; - clock-critical = <CLK_IC_LMI0>; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp"; - clock-critical = <CLK_PROC_STFE>, - <CLK_ICN_CPU>, - <CLK_TX_ICN_DMU>, - <CLK_EXT2F_A9>, - <CLK_ICN_LMI>, - <CLK_ICN_SBC>; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "clk-pix-pip", - "clk-pix-gdp1", - "clk-pix-gdp2", - "clk-pix-gdp3", - "clk-pix-gdp4", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi deleted file mode 100644 index 7c36c37260a..00000000000 --- a/arch/arm/dts/stih407-family.dtsi +++ /dev/null @@ -1,1000 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> - */ -#include "stih407-pinctrl.dtsi" -#include <dt-bindings/mfd/st-lpc.h> -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/reset/stih407-resets.h> -#include <dt-bindings/interrupt-controller/irq-st.h> -/ { - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gp0_reserved: rproc@45000000 { - compatible = "shared-dma-pool"; - reg = <0x45000000 0x00400000>; - no-map; - }; - - delta_reserved: rproc@44000000 { - compatible = "shared-dma-pool"; - reg = <0x44000000 0x01000000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - - clocks = <&clk_m_a9>; - clock-names = "cpu"; - clock-latency = <100000>; - cpu0-supply = <&pwm_regulator>; - st,syscfg = <&syscfg_core 0x8e0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - - /* u-boot puts hpen in SBC dmem at 0xa4 offset */ - cpu-release-addr = <0x94100A4>; - - /* kHz uV */ - operating-points = <1500000 0 - 1200000 0 - 800000 0 - 500000 0>; - }; - }; - - intc: interrupt-controller@8761000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x08761000 0x1000>, <0x08760100 0x100>; - }; - - scu@8760000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x08760000 0x1000>; - }; - - timer@8760200 { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-global-timer"; - reg = <0x08760200 0x100>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&arm_periph_clk>; - }; - - l2: cache-controller@8762000 { - compatible = "arm,pl310-cache"; - reg = <0x08762000 0x1000>; - arm,data-latency = <3 3 3>; - arm,tag-latency = <2 2 2>; - cache-unified; - cache-level = <2>; - }; - - arm-pmu { - interrupt-parent = <&intc>; - compatible = "arm,cortex-a9-pmu"; - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; - }; - - pwm_regulator: pwm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 3 8448>; - regulator-name = "CPU_1V0_AVS"; - regulator-min-microvolt = <784000>; - regulator-max-microvolt = <1299000>; - regulator-always-on; - max-duty-cycle = <255>; - status = "okay"; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - compatible = "simple-bus"; - - restart: restart-controller@0 { - compatible = "st,stih407-restart"; - reg = <0 0>; - st,syscfg = <&syscfg_sbc_reg>; - status = "okay"; - }; - - powerdown: powerdown-controller@0 { - compatible = "st,stih407-powerdown"; - reg = <0 0>; - #reset-cells = <1>; - }; - - softreset: softreset-controller@0 { - compatible = "st,stih407-softreset"; - reg = <0 0>; - #reset-cells = <1>; - }; - - picophyreset: picophyreset-controller@0 { - compatible = "st,stih407-picophyreset"; - reg = <0 0>; - #reset-cells = <1>; - }; - - syscfg_sbc: sbc-syscfg@9620000 { - compatible = "st,stih407-sbc-syscfg", "syscon"; - reg = <0x9620000 0x1000>; - }; - - syscfg_front: front-syscfg@9280000 { - compatible = "st,stih407-front-syscfg", "syscon"; - reg = <0x9280000 0x1000>; - }; - - syscfg_rear: rear-syscfg@9290000 { - compatible = "st,stih407-rear-syscfg", "syscon"; - reg = <0x9290000 0x1000>; - }; - - syscfg_flash: flash-syscfg@92a0000 { - compatible = "st,stih407-flash-syscfg", "syscon"; - reg = <0x92a0000 0x1000>; - }; - - syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { - compatible = "st,stih407-sbc-reg-syscfg", "syscon"; - reg = <0x9600000 0x1000>; - }; - - syscfg_core: core-syscfg@92b0000 { - compatible = "st,stih407-core-syscfg", "syscon"; - reg = <0x92b0000 0x1000>; - - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; - status = "disabled"; - st,syscfg = <&syscfg_core>; - }; - }; - - syscfg_lpm: lpm-syscfg@94b5100 { - compatible = "st,stih407-lpm-syscfg", "syscon"; - reg = <0x94b5100 0x1000>; - }; - - irq-syscfg@0 { - compatible = "st,stih407-irq-syscfg"; - reg = <0 0>; - st,syscfg = <&syscfg_core>; - st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, - <ST_IRQ_SYSCFG_PMU_1>; - st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, - <ST_IRQ_SYSCFG_DISABLED>; - }; - - /* Display */ - vtg_main: sti-vtg-main@8d02800 { - compatible = "st,vtg"; - reg = <0x8d02800 0x200>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - }; - - vtg_aux: sti-vtg-aux@8d00200 { - compatible = "st,vtg"; - reg = <0x8d00200 0x100>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - }; - - serial@9830000 { - compatible = "st,asc"; - reg = <0x9830000 0x2c>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - /* Pinctrl moved out to a per-board configuration */ - - status = "disabled"; - }; - - serial@9831000 { - compatible = "st,asc"; - reg = <0x9831000 0x2c>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial1>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - serial@9832000 { - compatible = "st,asc"; - reg = <0x9832000 0x2c>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0: serial@9530000 { - compatible = "st,asc"; - reg = <0x9530000 0x2c>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial0>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - serial@9531000 { - compatible = "st,asc"; - reg = <0x9531000 0x2c>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; - - status = "disabled"; - }; - - i2c@9840000 { - compatible = "st,comms-ssc4-i2c"; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x9840000 0x110>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9841000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9841000 0x110>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9842000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9842000 0x110>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9843000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9843000 0x110>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9844000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9844000 0x110>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9845000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9845000 0x110>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - - /* SSCs on SBC */ - i2c@9540000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9540000 0x110>; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c@9541000 { - compatible = "st,comms-ssc4-i2c"; - reg = <0x9541000 0x110>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - usb2_picophy0: phy1@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names = "global", "port"; - }; - - miphy28lp_phy: miphy28lp@0 { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0 0>; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - - spi@9840000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9840000 0x110>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-0 = <&pinctrl_spi0_default>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9841000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9841000 0x110>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9842000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9842000 0x110>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9843000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9843000 0x110>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi3_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9844000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9844000 0x110>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi4_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - /* SBC SSC */ - spi@9540000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9540000 0x110>; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi10_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9541000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9541000 0x110>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi11_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi@9542000 { - compatible = "st,comms-ssc4-spi"; - reg = <0x9542000 0x110>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_sysin>; - clock-names = "ssc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi12_default>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - mmc0: sdhci@9060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - bus-width = <8>; - }; - - mmc1: sdhci@9080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - status = "disabled"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc", "icn"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>, - <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; - }; - - /* Watchdog and Real-Time Clock */ - lpc@8787000 { - compatible = "st,stih407-lpc"; - reg = <0x8787000 0x1000>; - interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; - clocks = <&clk_s_d3_flexgen CLK_LPC_0>; - timeout-sec = <120>; - st,syscfg = <&syscfg_core>; - st,lpc-mode = <ST_LPC_MODE_WDT>; - }; - - lpc@8788000 { - compatible = "st,stih407-lpc"; - reg = <0x8788000 0x1000>; - interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; - clocks = <&clk_s_d3_flexgen CLK_LPC_1>; - st,lpc-mode = <ST_LPC_MODE_CLKSRC>; - }; - - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - - interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hostc"; - - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - sata1: sata@9b28000 { - compatible = "st,ahci"; - reg = <0x9b28000 0x1000>; - - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hostc"; - - phys = <&phy_port1 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - - resets = <&powerdown STIH407_SATA1_POWERDOWN>, - <&softreset STIH407_SATA1_SOFTRESET>, - <&softreset STIH407_SATA1_PWR_SOFTRESET>; - reset-names = "pwr-dwn", - "sw-rst", - "pwr-rst"; - - clock-names = "ahci_clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - - ports-implemented = <0x1>; - - status = "disabled"; - }; - - - st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - ranges; - - status = "disabled"; - - dwc3: dwc3@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy0>, - <&phy_port2 PHY_TYPE_USB3>; - snps,dis_u3_susphy_quirk; - }; - }; - - /* COMMS PWM Module */ - pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <1>; - - status = "disabled"; - }; - - /* SBC PWM Module */ - pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; - st,pwm-num-chan = <4>; - - status = "disabled"; - }; - - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - device_type = "network"; - status = "disabled"; - compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; - reg = <0x9630000 0x8000>, <0x80 0x4>; - reg-names = "stmmaceth", "sti-ethconf"; - - st,syscon = <&syscfg_sbc_reg 0x80>; - st,gmac_en; - resets = <&softreset STIH407_ETH1_SOFTRESET>; - reset-names = "stmmaceth"; - - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - - /* DMA Bus Mode */ - snps,pbl = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - - clock-names = "stmmaceth", "sti-ethclk"; - clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_ETH_PHY>; - }; - - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - mailbox0: mailbox@8f00000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f00000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - mbox-name = "a9"; - status = "okay"; - }; - - mailbox1: mailbox@8f01000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f01000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_1"; - status = "okay"; - }; - - mailbox2: mailbox@8f02000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f02000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_0"; - status = "okay"; - }; - - mailbox3: mailbox@8f03000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f03000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_audio_video"; - status = "okay"; - }; - - st231_gp0: st231-gp0@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; - }; - - st231_delta: st231-delta@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&delta_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; - }; - - /* fdma audio */ - fdma0: dma-controller@8e20000 { - compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; - reg = <0x8e20000 0x8000>, - <0x8e30000 0x3000>, - <0x8e37000 0x1000>, - <0x8e38000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <16>; - #dma-cells = <3>; - }; - - /* fdma app */ - fdma1: dma-controller@8e40000 { - compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; - reg = <0x8e40000 0x8000>, - <0x8e50000 0x3000>, - <0x8e57000 0x1000>, - <0x8e58000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <16>; - #dma-cells = <3>; - - status = "disabled"; - }; - - /* fdma free running */ - fdma2: dma-controller@8e60000 { - compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; - reg = <0x8e60000 0x8000>, - <0x8e70000 0x3000>, - <0x8e77000 0x1000>, - <0x8e78000 0x8000>; - reg-names = "slimcore", "dmem", "peripherals", "imem"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <16>; - #dma-cells = <3>; - clocks = <&clk_s_c0_flexgen CLK_FDMA>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>, - <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_EXT2F_A9>; - - status = "disabled"; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - compatible = "st,stih407-uni-player-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; - assigned-clock-rates = <50000000>; - reg = <0x8d80000 0x158>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&fdma0 2 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player1: sti-uni-player@8d81000 { - compatible = "st,stih407-uni-player-pcm-out"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; - assigned-clock-rates = <50000000>; - reg = <0x8d81000 0x158>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&fdma0 3 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - compatible = "st,stih407-uni-player-dac"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; - assigned-clock-rates = <50000000>; - reg = <0x8d82000 0x158>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&fdma0 4 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - compatible = "st,stih407-uni-player-spdif"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; - assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; - assigned-clock-rates = <50000000>; - reg = <0x8d85000 0x158>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&fdma0 7 0 1>; - dma-names = "tx"; - - status = "disabled"; - }; - - sti_uni_reader0: sti-uni-reader@8d83000 { - compatible = "st,stih407-uni-reader-pcm_in"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d83000 0x158>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&fdma0 5 0 1>; - dma-names = "rx"; - - status = "disabled"; - }; - - sti_uni_reader1: sti-uni-reader@8d84000 { - compatible = "st,stih407-uni-reader-hdmi"; - #sound-dai-cells = <0>; - st,syscfg = <&syscfg_core>; - reg = <0x8d84000 0x158>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&fdma0 6 0 1>; - dma-names = "rx"; - - status = "disabled"; - }; - - delta0@0 { - compatible = "st,st-delta"; - reg = <0 0>; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - }; -}; diff --git a/arch/arm/dts/stih407-pinctrl.dtsi b/arch/arm/dts/stih407-pinctrl.dtsi deleted file mode 100644 index 2cf335714ca..00000000000 --- a/arch/arm/dts/stih407-pinctrl.dtsi +++ /dev/null @@ -1,1262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> - */ -#include "st-pincfg.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -/ { - - aliases { - /* 0-5: PIO_SBC */ - gpio0 = &pio0; - gpio1 = &pio1; - gpio2 = &pio2; - gpio3 = &pio3; - gpio4 = &pio4; - gpio5 = &pio5; - /* 10-19: PIO_FRONT0 */ - gpio6 = &pio10; - gpio7 = &pio11; - gpio8 = &pio12; - gpio9 = &pio13; - gpio10 = &pio14; - gpio11 = &pio15; - gpio12 = &pio16; - gpio13 = &pio17; - gpio14 = &pio18; - gpio15 = &pio19; - /* 20: PIO_FRONT1 */ - gpio16 = &pio20; - /* 30-35: PIO_REAR */ - gpio17 = &pio30; - gpio18 = &pio31; - gpio19 = &pio32; - gpio20 = &pio33; - gpio21 = &pio34; - gpio22 = &pio35; - /* 40-42: PIO_FLASH */ - gpio23 = &pio40; - gpio24 = &pio41; - gpio25 = &pio42; - }; - - soc { - pin-controller-sbc@961f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-sbc-pinctrl"; - st,syscfg = <&syscfg_sbc>; - reg = <0x0961f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0x09610000 0x6000>; - - pio0: gpio@9610000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO0"; - }; - pio1: gpio@9611000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO1"; - }; - pio2: gpio@9612000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO2"; - }; - pio3: gpio@9613000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO3"; - }; - pio4: gpio@9614000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO4"; - }; - - pio5: gpio@9615000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO5"; - st,retime-pin-mask = <0x3f>; - }; - - cec0 { - pinctrl_cec0_default: cec0-default { - st,pins { - hdmi_cec = <&pio2 4 ALT1 BIDIR>; - }; - }; - }; - - rc { - pinctrl_ir: ir0 { - st,pins { - ir = <&pio4 0 ALT2 IN>; - }; - }; - - pinctrl_uhf: uhf0 { - st,pins { - ir = <&pio4 1 ALT2 IN>; - }; - }; - - pinctrl_tx: tx0 { - st,pins { - tx = <&pio4 2 ALT2 OUT>; - }; - }; - - pinctrl_tx_od: tx_od0 { - st,pins { - tx_od = <&pio4 3 ALT2 OUT>; - }; - }; - }; - - /* SBC_ASC0 - UART10 */ - sbc_serial0 { - pinctrl_sbc_serial0: sbc_serial0-0 { - st,pins { - tx = <&pio3 4 ALT1 OUT>; - rx = <&pio3 5 ALT1 IN>; - }; - }; - }; - /* SBC_ASC1 - UART11 */ - sbc_serial1 { - pinctrl_sbc_serial1: sbc_serial1-0 { - st,pins { - tx = <&pio2 6 ALT3 OUT>; - rx = <&pio2 7 ALT3 IN>; - }; - }; - }; - - i2c10 { - pinctrl_i2c10_default: i2c10-default { - st,pins { - sda = <&pio4 6 ALT1 BIDIR>; - scl = <&pio4 5 ALT1 BIDIR>; - }; - }; - }; - - i2c11 { - pinctrl_i2c11_default: i2c11-default { - st,pins { - sda = <&pio5 1 ALT1 BIDIR>; - scl = <&pio5 0 ALT1 BIDIR>; - }; - }; - }; - - keyscan { - pinctrl_keyscan: keyscan { - st,pins { - keyin0 = <&pio4 0 ALT6 IN>; - keyin1 = <&pio4 5 ALT4 IN>; - keyin2 = <&pio0 4 ALT2 IN>; - keyin3 = <&pio2 6 ALT2 IN>; - - keyout0 = <&pio4 6 ALT4 OUT>; - keyout1 = <&pio1 7 ALT2 OUT>; - keyout2 = <&pio0 6 ALT2 OUT>; - keyout3 = <&pio2 7 ALT2 OUT>; - }; - }; - }; - - gmac1 { - /* - * Almost all the boards based on STiH407 SoC have an embedded - * switch where the mdio/mdc have been used for managing the SMI - * iface via I2C. For this reason these lines can be allocated - * by using dedicated configuration (in case of there will be a - * standard PHY transceiver on-board). - */ - pinctrl_rgmii1: rgmii1-0 { - st,pins { - - txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; - rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; - }; - }; - - pinctrl_rgmii1_mdio: rgmii1-mdio { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - }; - }; - - pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { - st,pins { - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_mii1: mii1 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&pio0 7 ALT1 IN BYPASS 1000>; - - mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&pio1 2 ALT1 IN BYPASS 1000>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1: rmii1-0 { - st,pins { - txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - mdio = <&pio1 0 ALT1 OUT BYPASS 0>; - mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; - mdint = <&pio1 3 ALT1 IN BYPASS 0>; - rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; - rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk: rmii1_phyclk { - st,pins { - phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; - }; - }; - - pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { - st,pins { - phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; - }; - }; - }; - - pwm1 { - pinctrl_pwm1_chan0_default: pwm1-0-default { - st,pins { - pwm-out = <&pio3 0 ALT1 OUT>; - pwm-capturein = <&pio3 2 ALT1 IN>; - }; - }; - pinctrl_pwm1_chan1_default: pwm1-1-default { - st,pins { - pwm-capturein = <&pio4 3 ALT1 IN>; - pwm-out = <&pio4 4 ALT1 OUT>; - }; - }; - pinctrl_pwm1_chan2_default: pwm1-2-default { - st,pins { - pwm-out = <&pio4 6 ALT3 OUT>; - }; - }; - pinctrl_pwm1_chan3_default: pwm1-3-default { - st,pins { - pwm-out = <&pio4 7 ALT3 OUT>; - }; - }; - }; - - spi10 { - pinctrl_spi10_default: spi10-4w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 OUT>; - mrst = <&pio4 7 ALT1 IN>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - - pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 { - st,pins { - mtsr = <&pio4 6 ALT1 BIDIR_PU>; - scl = <&pio4 5 ALT1 OUT>; - }; - }; - }; - - spi11 { - pinctrl_spi11_default: spi11-4w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 OUT>; - mrst = <&pio3 0 ALT2 IN>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - - pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 { - st,pins { - mtsr = <&pio3 1 ALT2 BIDIR_PU>; - scl = <&pio3 2 ALT2 OUT>; - }; - }; - }; - - spi12 { - pinctrl_spi12_default: spi12-4w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 OUT>; - mrst = <&pio3 4 ALT2 IN>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - - pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 { - st,pins { - mtsr = <&pio3 6 ALT2 BIDIR_PU>; - scl = <&pio3 7 ALT2 OUT>; - }; - }; - }; - }; - - pin-controller-front0@920f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0920f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0x09200000 0x10000>; - - pio10: pio@9200000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO10"; - }; - pio11: pio@9201000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO11"; - }; - pio12: pio@9202000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO12"; - }; - pio13: pio@9203000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO13"; - }; - pio14: pio@9204000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO14"; - }; - pio15: pio@9205000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO15"; - }; - pio16: pio@9206000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x100>; - st,bank-name = "PIO16"; - }; - pio17: pio@9207000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x100>; - st,bank-name = "PIO17"; - }; - pio18: pio@9208000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x100>; - st,bank-name = "PIO18"; - }; - pio19: pio@9209000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x100>; - st,bank-name = "PIO19"; - }; - - /* Comms */ - serial0 { - pinctrl_serial0: serial0-0 { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - }; - }; - pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { - st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; - cts = <&pio17 2 ALT1 IN>; - rts = <&pio17 3 ALT1 OUT>; - }; - }; - }; - - serial1 { - pinctrl_serial1: serial1-0 { - st,pins { - tx = <&pio16 0 ALT1 OUT>; - rx = <&pio16 1 ALT1 IN>; - }; - }; - }; - - serial2 { - pinctrl_serial2: serial2-0 { - st,pins { - tx = <&pio15 0 ALT1 OUT>; - rx = <&pio15 1 ALT1 IN>; - }; - }; - }; - - mmc1 { - pinctrl_sd1: sd1-0 { - st,pins { - sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; - sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; - sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; - sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; - sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; - sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; - sd_led = <&pio16 6 ALT6 OUT>; - sd_pwren = <&pio16 7 ALT6 OUT>; - sd_cd = <&pio19 0 ALT6 IN>; - sd_wp = <&pio19 1 ALT6 IN>; - }; - }; - }; - - - i2c0 { - pinctrl_i2c0_default: i2c0-default { - st,pins { - sda = <&pio10 6 ALT2 BIDIR>; - scl = <&pio10 5 ALT2 BIDIR>; - }; - }; - }; - - i2c1 { - pinctrl_i2c1_default: i2c1-default { - st,pins { - sda = <&pio11 1 ALT2 BIDIR>; - scl = <&pio11 0 ALT2 BIDIR>; - }; - }; - }; - - i2c2 { - pinctrl_i2c2_default: i2c2-default { - st,pins { - sda = <&pio15 6 ALT2 BIDIR>; - scl = <&pio15 5 ALT2 BIDIR>; - }; - }; - - pinctrl_i2c2_alt2_1: i2c2-alt2-1 { - st,pins { - sda = <&pio12 6 ALT2 BIDIR>; - scl = <&pio12 5 ALT2 BIDIR>; - }; - }; - }; - - i2c3 { - pinctrl_i2c3_default: i2c3-alt1-0 { - st,pins { - sda = <&pio18 6 ALT1 BIDIR>; - scl = <&pio18 5 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt1_1: i2c3-alt1-1 { - st,pins { - sda = <&pio17 7 ALT1 BIDIR>; - scl = <&pio17 6 ALT1 BIDIR>; - }; - }; - pinctrl_i2c3_alt3_0: i2c3-alt3-0 { - st,pins { - sda = <&pio13 6 ALT3 BIDIR>; - scl = <&pio13 5 ALT3 BIDIR>; - }; - }; - }; - - spi0 { - pinctrl_spi0_default: spi0-4w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 OUT>; - mrst = <&pio10 7 ALT2 IN>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 { - st,pins { - mtsr = <&pio10 6 ALT2 BIDIR_PU>; - scl = <&pio10 5 ALT2 OUT>; - }; - }; - - pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 OUT>; - mrst = <&pio19 5 ALT1 IN>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - - pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 { - st,pins { - mtsr = <&pio19 7 ALT1 BIDIR_PU>; - scl = <&pio19 6 ALT1 OUT>; - }; - }; - }; - - spi1 { - pinctrl_spi1_default: spi1-4w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 OUT>; - mrst = <&pio11 2 ALT2 IN>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 { - st,pins { - mtsr = <&pio11 1 ALT2 BIDIR_PU>; - scl = <&pio11 0 ALT2 OUT>; - }; - }; - - pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 OUT>; - mrst = <&pio14 4 ALT1 IN>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - - pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 { - st,pins { - mtsr = <&pio14 3 ALT1 BIDIR_PU>; - scl = <&pio14 2 ALT1 OUT>; - }; - }; - }; - - spi2 { - pinctrl_spi2_default: spi2-4w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 OUT>; - mrst = <&pio12 7 ALT2 IN>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 { - st,pins { - mtsr = <&pio12 6 ALT2 BIDIR_PU>; - scl = <&pio12 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 OUT>; - mrst = <&pio14 7 ALT1 IN>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 { - st,pins { - mtsr = <&pio14 6 ALT1 BIDIR_PU>; - scl = <&pio14 5 ALT1 OUT>; - }; - }; - - pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 OUT>; - mrst = <&pio15 7 ALT2 IN>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - - pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 { - st,pins { - mtsr = <&pio15 6 ALT2 BIDIR_PU>; - scl = <&pio15 5 ALT2 OUT>; - }; - }; - }; - - spi3 { - pinctrl_spi3_default: spi3-4w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 OUT>; - mrst = <&pio13 7 ALT3 IN>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 { - st,pins { - mtsr = <&pio13 6 ALT3 BIDIR_PU>; - scl = <&pio13 5 ALT3 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 OUT>; - mrst = <&pio17 5 ALT1 IN>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 { - st,pins { - mtsr = <&pio17 7 ALT1 BIDIR_PU>; - scl = <&pio17 6 ALT1 OUT>; - }; - }; - - pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 OUT>; - mrst = <&pio18 7 ALT1 IN>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - - pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 { - st,pins { - mtsr = <&pio18 6 ALT1 BIDIR_PU>; - scl = <&pio18 5 ALT1 OUT>; - }; - }; - }; - - tsin0 { - pinctrl_tsin0_parallel: tsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin0_serial: tsin0_serial { - st,pins { - DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin1 { - pinctrl_tsin1_parallel: tsin1_parallel { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin1_serial: tsin1_serial { - st,pins { - DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin2 { - pinctrl_tsin2_parallel: tsin2_parallel { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>; - DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin2_serial: tsin2_serial { - st,pins { - DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin3 { - pinctrl_tsin3_serial: tsin3_serial { - st,pins { - DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin4 { - pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 { - st,pins { - DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>; - ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>; - PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsin5 { - pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { - st,pins { - DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { - st,pins { - DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout0 { - pinctrl_tsout0_parallel: tsout0_parallel { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - pinctrl_tsout0_serial: tsout0_serial { - st,pins { - DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>; - VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - tsout1 { - pinctrl_tsout1_serial: tsout1_serial { - st,pins { - DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>; - VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - mtsin0 { - pinctrl_mtsin0_parallel: mtsin0_parallel { - st,pins { - DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - - systrace { - pinctrl_systrace_default: systrace-default { - st,pins { - trc_data0 = <&pio11 3 ALT5 OUT>; - trc_data1 = <&pio11 4 ALT5 OUT>; - trc_data2 = <&pio11 5 ALT5 OUT>; - trc_data3 = <&pio11 6 ALT5 OUT>; - trc_clk = <&pio11 7 ALT5 OUT>; - }; - }; - }; - }; - - pin-controller-front1@921f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-front-pinctrl"; - st,syscfg = <&syscfg_front>; - reg = <0x0921f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0x09210000 0x10000>; - - pio20: pio@9210000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO20"; - }; - - tsin4 { - pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { - st,pins { - DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>; - VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - }; - - pin-controller-rear@922f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-rear-pinctrl"; - st,syscfg = <&syscfg_rear>; - reg = <0x0922f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0x09220000 0x6000>; - - pio30: gpio@9220000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO30"; - }; - pio31: gpio@9221000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO31"; - }; - pio32: gpio@9222000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO32"; - }; - pio33: gpio@9223000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x100>; - st,bank-name = "PIO33"; - }; - pio34: gpio@9224000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x100>; - st,bank-name = "PIO34"; - }; - pio35: gpio@9225000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x100>; - st,bank-name = "PIO35"; - st,retime-pin-mask = <0x7f>; - }; - - i2c4 { - pinctrl_i2c4_default: i2c4-default { - st,pins { - sda = <&pio30 1 ALT1 BIDIR>; - scl = <&pio30 0 ALT1 BIDIR>; - }; - }; - }; - - i2c5 { - pinctrl_i2c5_default: i2c5-default { - st,pins { - sda = <&pio34 4 ALT1 BIDIR>; - scl = <&pio34 3 ALT1 BIDIR>; - }; - }; - }; - - usb3 { - pinctrl_usb3: usb3-2 { - st,pins { - usb-oc-detect = <&pio35 4 ALT1 IN>; - usb-pwr-enable = <&pio35 5 ALT1 OUT>; - usb-vbus-valid = <&pio35 6 ALT1 IN>; - }; - }; - }; - - pwm0 { - pinctrl_pwm0_chan0_default: pwm0-0-default { - st,pins { - pwm-capturein = <&pio31 0 ALT1 IN>; - pwm-out = <&pio31 1 ALT1 OUT>; - }; - }; - }; - - spi4 { - pinctrl_spi4_default: spi4-4w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 OUT>; - mrst = <&pio30 2 ALT1 IN>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 { - st,pins { - mtsr = <&pio30 1 ALT1 BIDIR_PU>; - scl = <&pio30 0 ALT1 OUT>; - }; - }; - - pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 OUT>; - mrst = <&pio34 2 ALT3 IN>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - - pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 { - st,pins { - mtsr = <&pio34 1 ALT3 BIDIR_PU>; - scl = <&pio34 0 ALT3 OUT>; - }; - }; - }; - - i2s_out { - pinctrl_i2s_8ch_out: i2s_8ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - data1 = <&pio34 0 ALT1 OUT>; - data2 = <&pio34 1 ALT1 OUT>; - data3 = <&pio34 2 ALT1 OUT>; - }; - }; - - pinctrl_i2s_2ch_out: i2s_2ch_out{ - st,pins { - mclk = <&pio33 5 ALT1 OUT>; - lrclk = <&pio33 7 ALT1 OUT>; - sclk = <&pio33 6 ALT1 OUT>; - data0 = <&pio33 4 ALT1 OUT>; - }; - }; - }; - - i2s_in { - pinctrl_i2s_8ch_in: i2s_8ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - data1 = <&pio33 0 ALT1 IN>; - data2 = <&pio33 1 ALT1 IN>; - data3 = <&pio33 2 ALT1 IN>; - data4 = <&pio33 3 ALT1 IN>; - }; - }; - - pinctrl_i2s_2ch_in: i2s_2ch_in{ - st,pins { - mclk = <&pio32 5 ALT1 IN>; - lrclk = <&pio32 7 ALT1 IN>; - sclk = <&pio32 6 ALT1 IN>; - data0 = <&pio32 4 ALT1 IN>; - }; - }; - }; - - spdif_out { - pinctrl_spdif_out: spdif_out{ - st,pins { - spdif_out = <&pio34 7 ALT1 OUT>; - }; - }; - }; - - serial3 { - pinctrl_serial3: serial3-0 { - st,pins { - tx = <&pio31 3 ALT1 OUT>; - rx = <&pio31 4 ALT1 IN>; - }; - }; - }; - }; - - pin-controller-flash@923f080 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stih407-flash-pinctrl"; - st,syscfg = <&syscfg_flash>; - reg = <0x0923f080 0x4>; - reg-names = "irqmux"; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irqmux"; - ranges = <0 0x09230000 0x3000>; - - pio40: gpio@9230000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x100>; - st,bank-name = "PIO40"; - }; - pio41: gpio@9231000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x100>; - st,bank-name = "PIO41"; - }; - pio42: gpio@9232000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x100>; - st,bank-name = "PIO42"; - }; - - mmc0 { - pinctrl_mmc0: mmc0-0 { - st,pins { - emmc_clk = <&pio40 6 ALT1 BIDIR>; - emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; - emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; - emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; - emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; - emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; - emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; - emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; - emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; - emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; - }; - }; - pinctrl_sd0: sd0-0 { - st,pins { - sd_clk = <&pio40 6 ALT1 BIDIR>; - sd_cmd = <&pio40 7 ALT1 BIDIR_PU>; - sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>; - sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>; - sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>; - sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>; - sd_led = <&pio42 0 ALT2 OUT>; - sd_pwren = <&pio42 2 ALT2 OUT>; - sd_vsel = <&pio42 3 ALT2 OUT>; - sd_cd = <&pio42 4 ALT2 IN>; - sd_wp = <&pio42 5 ALT2 IN>; - }; - }; - }; - - fsm { - pinctrl_fsm: fsm { - st,pins { - spi-fsm-clk = <&pio40 1 ALT1 OUT>; - spi-fsm-cs = <&pio40 0 ALT1 OUT>; - spi-fsm-mosi = <&pio40 2 ALT1 OUT>; - spi-fsm-miso = <&pio40 3 ALT1 IN>; - spi-fsm-hol = <&pio40 5 ALT1 OUT>; - spi-fsm-wp = <&pio40 4 ALT1 OUT>; - }; - }; - }; - - nand { - pinctrl_nand: nand { - st,pins { - nand_cs1 = <&pio40 6 ALT3 OUT>; - nand_cs0 = <&pio40 7 ALT3 OUT>; - nand_d0 = <&pio41 0 ALT3 BIDIR>; - nand_d1 = <&pio41 1 ALT3 BIDIR>; - nand_d2 = <&pio41 2 ALT3 BIDIR>; - nand_d3 = <&pio41 3 ALT3 BIDIR>; - nand_d4 = <&pio41 4 ALT3 BIDIR>; - nand_d5 = <&pio41 5 ALT3 BIDIR>; - nand_d6 = <&pio41 6 ALT3 BIDIR>; - nand_d7 = <&pio41 7 ALT3 BIDIR>; - nand_we = <&pio42 0 ALT3 OUT>; - nand_dqs = <&pio42 1 ALT3 OUT>; - nand_ale = <&pio42 2 ALT3 OUT>; - nand_cle = <&pio42 3 ALT3 OUT>; - nand_rnb = <&pio42 4 ALT3 IN>; - nand_oe = <&pio42 5 ALT3 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi index e9d7ec92281..1aa0a58d237 100644 --- a/arch/arm/dts/stih410-b2260-u-boot.dtsi +++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi @@ -7,37 +7,35 @@ /{ soc { - st_dwc3: dwc3@8f94000 { - dwc3: dwc3@9900000 { - dr_mode = "peripheral"; - phys = <&usb2_picophy0>; - }; - }; - clk_usb: clk-usb { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; + }; +}; - ohci0: usb@9a03c00 { - compatible = "generic-ohci"; - clocks = <&clk_usb>; - }; +&dwc3 { + dr_mode = "peripheral"; + phys = <&usb2_picophy0>; +}; - ehci0: usb@9a03e00 { - compatible = "generic-ehci"; - clocks = <&clk_usb>; - }; +&ehci0 { + compatible = "st,st-ehci-300x", "generic-ehci"; + clocks = <&clk_usb>; +}; - ohci1: usb@9a83c00 { - compatible = "generic-ohci"; - clocks = <&clk_usb>; - }; +&ehci1 { + compatible = "st,st-ehci-300x", "generic-ehci"; + clocks = <&clk_usb>; +}; - ehci1: usb@9a83e00 { - compatible = "generic-ehci"; - clocks = <&clk_usb>; - }; - }; +&ohci0 { + compatible = "st,st-ehci-300x", "generic-ehci"; + clocks = <&clk_usb>; +}; + +&ohci1 { + compatible = "st,st-ehci-300x", "generic-ehci"; + clocks = <&clk_usb>; }; diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts deleted file mode 100644 index 8c4155b6227..00000000000 --- a/arch/arm/dts/stih410-b2260.dts +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 STMicroelectronics (R&D) Limited. - * Author: Patrice Chotard <patrice.chotard@foss.st.com> - */ -/dts-v1/; -#include "stih410.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "STiH410 B2260"; - compatible = "st,stih410-b2260", "st,stih410"; - - chosen { - bootargs = "clk_ignore_unused"; - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - aliases { - serial1 = &uart1; - ethernet0 = ðernet0; - }; - - leds { - compatible = "gpio-leds"; - user_green_1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user_green_2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user_green_3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - user_green_4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2260"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - /* DAC */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - }; - - soc { - /* Low speed expansion connector */ - uart0: serial@9830000 { - label = "LS-UART0"; - pinctrl-names = "default", "no-hw-flowctrl"; - pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; - pinctrl-1 = <&pinctrl_serial0>; - rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - }; - - /* Low speed expansion connector */ - uart1: serial@9831000 { - label = "LS-UART1"; - status = "okay"; - }; - - /* Low speed expansion connector */ - spi0: spi@9844000 { - label = "LS-SPI0"; - cs-gpios = <&pio30 3 0>; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c0: i2c@9840000 { - label = "LS-I2C0"; - status = "okay"; - }; - - /* Low speed expansion connector */ - i2c1: i2c@9841000 { - label = "LS-I2C1"; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c2: i2c@9842000 { - label = "HS-I2C2"; - pinctrl-0 = <&pinctrl_i2c2_alt2_1>; - status = "okay"; - }; - - /* high speed expansion connector */ - i2c3: i2c@9843000 { - label = "HS-I2C3"; - pinctrl-0 = <&pinctrl_i2c3_alt3_0>; - status = "okay"; - }; - - mmc0: sdhci@9060000 { - pinctrl-0 = <&pinctrl_sd0>; - bus-width = <4>; - status = "okay"; - }; - - /* high speed expansion connector */ - mmc1: sdhci@9080000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - phy-mode = "rgmii"; - pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - - snps,phy-bus-name = "stmmac"; - snps,phy-bus-id = <0>; - snps,phy-addr = <0>; - snps,reset-gpio = <&pio0 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - - status = "okay"; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - status = "okay"; - }; - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - status = "okay"; - }; - - miphy28lp_phy: miphy28lp@0 { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - sata1: sata@9b28000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/stih410-clock.dtsi b/arch/arm/dts/stih410-clock.dtsi deleted file mode 100644 index 81a8c25d7ba..00000000000 --- a/arch/arm/dts/stih410-clock.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include <dt-bindings/clock/stih410-clks.h> -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - compatible = "st,stih410-clk", "simple-bus"; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; - }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - - clock-output-names = "clk-ic-lmi0", - "clk-ic-lmi1"; - clock-critical = <CLK_IC_LMI0>; - }; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-fs0-ch0", - "clk-s-c0-fs0-ch1", - "clk-s-c0-fs0-ch2", - "clk-s-c0-fs0-ch3"; - clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1"; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-icn-gpu", - "clk-fdma", - "clk-nand", - "clk-hva", - "clk-proc-stfe", - "clk-proc-tp", - "clk-rx-icn-dmu", - "clk-rx-icn-hva", - "clk-icn-cpu", - "clk-tx-icn-dmu", - "clk-mmc-0", - "clk-mmc-1", - "clk-jpegdec", - "clk-ext2fa9", - "clk-ic-bdisp-0", - "clk-ic-bdisp-1", - "clk-pp-dmu", - "clk-vid-dmu", - "clk-dss-lpc", - "clk-st231-aud-0", - "clk-st231-gp-1", - "clk-st231-dmu", - "clk-icn-lmi", - "clk-tx-icn-disp-1", - "clk-icn-sbc", - "clk-stfe-frc2", - "clk-eth-phy", - "clk-eth-ref-phyclk", - "clk-flash-promip", - "clk-main-disp", - "clk-aux-disp", - "clk-compo-dvp", - "clk-tx-icn-hades", - "clk-rx-icn-hades", - "clk-icn-reg-16", - "clk-pp-hades", - "clk-clust-hades", - "clk-hwpe-hades", - "clk-fc-hades"; - clock-critical = <CLK_PROC_STFE>, - <CLK_ICN_CPU>, - <CLK_TX_ICN_DMU>, - <CLK_EXT2F_A9>, - <CLK_ICN_LMI>, - <CLK_ICN_SBC>; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d0-fs0-ch0", - "clk-s-d0-fs0-ch1", - "clk-s-d0-fs0-ch2", - "clk-s-d0-fs0-ch3"; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-audio", "st,flexgen"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-pcm-0", - "clk-pcm-1", - "clk-pcm-2", - "clk-spdiff", - "clk-pcmr10-master", - "clk-usb2-phy"; - }; - }; - - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d2-fs0-ch0", - "clk-s-d2-fs0-ch1", - "clk-s-d2-fs0-ch2", - "clk-s-d2-fs0-ch3"; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen-video", "st,flexgen"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - - clock-output-names = "clk-pix-main-disp", - "clk-pix-pip", - "clk-pix-gdp1", - "clk-pix-gdp2", - "clk-pix-gdp3", - "clk-pix-gdp4", - "clk-pix-aux-disp", - "clk-denc", - "clk-pix-hddac", - "clk-hddac", - "clk-sddac", - "clk-pix-dvo", - "clk-dvo", - "clk-pix-hdmi", - "clk-tmds-hdmi", - "clk-ref-hdmiphy"; - }; - }; - - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - - clock-output-names = "clk-s-d3-fs0-ch0", - "clk-s-d3-fs0-ch1", - "clk-s-d3-fs0-ch2", - "clk-s-d3-fs0-ch3"; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - - clock-output-names = "clk-stfe-frc1", - "clk-tsout-0", - "clk-tsout-1", - "clk-mchi", - "clk-vsens-compo", - "clk-frc1-remote", - "clk-lpc-0", - "clk-lpc-1"; - }; - }; - }; -}; diff --git a/arch/arm/dts/stih410-pinctrl.dtsi b/arch/arm/dts/stih410-pinctrl.dtsi deleted file mode 100644 index e6eadd12441..00000000000 --- a/arch/arm/dts/stih410-pinctrl.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin <peter.griffin@linaro.org> - */ -#include "st-pincfg.h" -/ { - - soc { - pin-controller-rear@922f080 { - - usb0 { - pinctrl_usb0: usb2-0 { - st,pins { - usb-oc-detect = <&pio35 0 ALT1 IN>; - usb-pwr-enable = <&pio35 1 ALT1 OUT>; - }; - }; - }; - - usb1 { - pinctrl_usb1: usb2-1 { - st,pins { - usb-oc-detect = <&pio35 2 ALT1 IN>; - usb-pwr-enable = <&pio35 3 ALT1 OUT>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stih410.dtsi b/arch/arm/dts/stih410.dtsi deleted file mode 100644 index 6d847019c55..00000000000 --- a/arch/arm/dts/stih410.dtsi +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics Limited. - * Author: Peter Griffin <peter.griffin@linaro.org> - */ -#include "stih410-clock.dtsi" -#include "stih407-family.dtsi" -#include "stih410-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -/ { - aliases { - bdisp0 = &bdisp0; - }; - - soc { - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - ohci0: usb@9a03c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a03c00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci0: usb@9a03e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a03e00 0x100>; - interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, - <&softreset STIH407_USB2_PORT0_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; - phy-names = "usb"; - - status = "disabled"; - }; - - ohci1: usb@9a83c00 { - compatible = "st,st-ohci-300x"; - reg = <0x9a83c00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - ehci1: usb@9a83e00 { - compatible = "st,st-ehci-300x"; - reg = <0x9a83e00 0x100>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, - <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; - resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, - <&softreset STIH407_USB2_PORT1_SOFTRESET>; - reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; - phy-names = "usb"; - - status = "disabled"; - }; - - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - status = "disabled"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - - sti-hqvdp@9c00000 { - compatible = "st,stih407-hqvdp"; - reg = <0x9C00000 0x100000>; - clock-names = "hqvdp", "pix_main"; - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names = "hqvdp"; - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg = <&vtg_main>; - }; - }; - - bdisp0:bdisp@9f10000 { - compatible = "st,stih407-bdisp"; - reg = <0x9f10000 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bdisp"; - clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; - }; - - hva@8c85000 { - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; - }; - - thermal@91a0000 { - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; - }; - - delta0@0 { - compatible = "st,st-delta"; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - - sti-cec@94a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - hdmi-phandle = <&sti_hdmi>; - }; - }; -}; diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts deleted file mode 100644 index 592b182c1aa..00000000000 --- a/arch/arm/dts/stm32429i-eval.dts +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015, STMicroelectronics - All Rights Reserved - * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics. - */ - -/dts-v1/; -#include "stm32f429.dtsi" -#include "stm32f429-pinctrl.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "STMicroelectronics STM32429i-EVAL board"; - compatible = "st,stm32429i-eval", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x00000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_panel: vdd-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpiog 6 1>; - linux,default-trigger = "heartbeat"; - }; - led-orange { - gpios = <&gpiog 7 1>; - }; - led-red { - gpios = <&gpiog 10 1>; - }; - led-blue { - gpios = <&gpiog 12 1>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - button@0 { - label = "Wake up"; - linux,code = <KEY_WAKEUP>; - gpios = <&gpioa 0 0>; - }; - button@1 { - label = "Tamper"; - linux,code = <KEY_RESTART>; - gpios = <&gpioc 13 0>; - }; - }; - - usbotg_hs_phy: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - panel_rgb: panel-rgb { - compatible = "ampire,am-480272h3tmqw-t01h"; - power-supply = <&vdd_panel>; - status = "okay"; - port { - panel_in_rgb: endpoint { - remote-endpoint = <<dc_out_rgb>; - }; - }; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc3_in8_pin>; - vdda-supply = <&vdda>; - vref-supply = <&vref>; - status = "okay"; - adc3: adc@200 { - st,adc-channels = <8>; - status = "okay"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&crc { - status = "okay"; -}; - -&dcmi { - status = "okay"; - - port { - dcmi_0: endpoint { - remote-endpoint = <&ov2640_0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - - ov2640: camera@30 { - compatible = "ovti,ov2640"; - reg = <0x30>; - resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; - clocks = <&clk_ext_camera>; - clock-names = "xvclk"; - status = "okay"; - - port { - ov2640_0: endpoint { - remote-endpoint = <&dcmi_0>; - }; - }; - }; - - stmpe1600: stmpe1600@42 { - compatible = "st,stmpe1600"; - reg = <0x42>; - interrupts = <8 3>; - interrupt-parent = <&gpioi>; - interrupt-controller; - wakeup-source; - - stmpegpio: stmpe_gpio { - compatible = "st,stmpe-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; - -&iwdg { - status = "okay"; - timeout-sec = <32>; -}; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins_a>; - pinctrl-names = "default"; - - port { - ltdc_out_rgb: endpoint { - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - pinctrl-names = "default"; - phy-mode = "mii"; - phy-handle = <&phy1>; - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdio { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - bus-width = <4>; - max-frequency = <12500000>; -}; - -&timers1 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@2 { - status = "okay"; - }; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts deleted file mode 100644 index 0e6445a539e..00000000000 --- a/arch/arm/dts/stm32746g-eval.dts +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> - * - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f746-pinctrl.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "STMicroelectronics STM32746g-EVAL board"; - compatible = "st,stm32746g-eval", "st,stm32f746"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpiof 10 1>; - linux,default-trigger = "heartbeat"; - }; - led-orange { - gpios = <&stmfx_pinctrl 17 1>; - }; - led-red { - gpios = <&gpiob 7 1>; - }; - led-blue { - gpios = <&stmfx_pinctrl 19 1>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "Wake up"; - linux,code = <KEY_WAKEUP>; - gpios = <&gpioc 13 0>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = <KEY_ENTER>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; - button-1 { - label = "JoyDown"; - linux,code = <KEY_DOWN>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = <KEY_LEFT>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - button-3 { - label = "JoyRight"; - linux,code = <KEY_RIGHT>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - button-4 { - label = "JoyUp"; - linux,code = <KEY_UP>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&crc { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - - stmfx_pinctrl: pinctrl { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - drive-push-pull; - bias-pull-up; - }; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdio1 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_a>; - pinctrl-1 = <&sdio_pins_od_a>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi deleted file mode 100644 index 0adc41b2a46..00000000000 --- a/arch/arm/dts/stm32f4-pinctrl.dtsi +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - */ - -#include <dt-bindings/pinctrl/stm32-pinfunc.h> -#include <dt-bindings/mfd/stm32f4-rcc.h> - -/ { - soc { - pinctrl: pinctrl@40020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ - bias-disable; - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ - bias-disable; - }; - }; - - usbotg_fs_pins_a: usbotg-fs-0 { - pins { - pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ - <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ - <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_b: usbotg-fs-1 { - pins { - pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */ - <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */ - <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/ - <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ - <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ - <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ - <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ - <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ - <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ - <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ - <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ - <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ - <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ - <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ethernet_mii: mii-0 { - pins { - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */ - <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */ - <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */ - <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */ - <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */ - <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */ - <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */ - slew-rate = <2>; - }; - }; - - adc3_in8_pin: adc-200 { - pins { - pinmux = <STM32_PINMUX('F', 10, ANALOG)>; - }; - }; - - pwm1_pins: pwm1-0 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ - <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ - <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */ - }; - }; - - pwm3_pins: pwm3-0 { - pins { - pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ - <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ - }; - }; - - i2c1_pins: i2c1-0 { - pins { - pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */ - <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <3>; - }; - }; - - ltdc_pins_a: ltdc-0 { - pins { - pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ - <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ - <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ - <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ - <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ - <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ - <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ - <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ - <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/ - <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ - <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ - <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ - <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ - <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ - <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ - <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ - <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ - <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ - <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/ - <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ - <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ - <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ - <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ - <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ - <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ - <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ - <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ - slew-rate = <2>; - }; - }; - - ltdc_pins_b: ltdc-1 { - pins { - pinmux = <STM32_PINMUX('C', 6, AF14)>, - /* LCD_HSYNC */ - <STM32_PINMUX('A', 4, AF14)>, - /* LCD_VSYNC */ - <STM32_PINMUX('G', 7, AF14)>, - /* LCD_CLK */ - <STM32_PINMUX('C', 10, AF14)>, - /* LCD_R2 */ - <STM32_PINMUX('B', 0, AF9)>, - /* LCD_R3 */ - <STM32_PINMUX('A', 11, AF14)>, - /* LCD_R4 */ - <STM32_PINMUX('A', 12, AF14)>, - /* LCD_R5 */ - <STM32_PINMUX('B', 1, AF9)>, - /* LCD_R6*/ - <STM32_PINMUX('G', 6, AF14)>, - /* LCD_R7 */ - <STM32_PINMUX('A', 6, AF14)>, - /* LCD_G2 */ - <STM32_PINMUX('G', 10, AF9)>, - /* LCD_G3 */ - <STM32_PINMUX('B', 10, AF14)>, - /* LCD_G4 */ - <STM32_PINMUX('D', 6, AF14)>, - /* LCD_B2 */ - <STM32_PINMUX('G', 11, AF14)>, - /* LCD_B3*/ - <STM32_PINMUX('B', 11, AF14)>, - /* LCD_G5 */ - <STM32_PINMUX('C', 7, AF14)>, - /* LCD_G6 */ - <STM32_PINMUX('D', 3, AF14)>, - /* LCD_G7 */ - <STM32_PINMUX('G', 12, AF9)>, - /* LCD_B4 */ - <STM32_PINMUX('A', 3, AF14)>, - /* LCD_B5 */ - <STM32_PINMUX('B', 8, AF14)>, - /* LCD_B6 */ - <STM32_PINMUX('B', 9, AF14)>, - /* LCD_B7 */ - <STM32_PINMUX('F', 10, AF14)>; - /* LCD_DE */ - slew-rate = <2>; - }; - }; - - spi5_pins: spi5-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 7, AF5)>, - /* SPI5_CLK */ - <STM32_PINMUX('F', 9, AF5)>; - /* SPI5_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 8, AF5)>; - /* SPI5_MISO */ - bias-disable; - }; - }; - - i2c3_pins: i2c3-0 { - pins { - pinmux = <STM32_PINMUX('C', 9, AF4)>, - /* I2C3_SDA */ - <STM32_PINMUX('A', 8, AF4)>; - /* I2C3_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <3>; - }; - }; - - dcmi_pins: dcmi-0 { - pins { - pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */ - <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */ - <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */ - <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */ - <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */ - <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */ - <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */ - <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */ - <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */ - <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */ - <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */ - <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */ - <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - sdio_pins: sdio-pins-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */ - <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */ - <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od: sdio-pins-od-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */ - <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - can1_pins_a: can1-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */ - bias-pull-up; - }; - }; - - can2_pins_a: can2-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ - bias-pull-up; - }; - }; - - can2_pins_b: can2-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */ - bias-pull-up; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts deleted file mode 100644 index 30daabd10a2..00000000000 --- a/arch/arm/dts/stm32f429-disco.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> - */ - -/dts-v1/; -#include "stm32f429.dtsi" -#include "stm32f429-pinctrl.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "STMicroelectronics STM32F429i-DISCO board"; - compatible = "st,stm32f429i-disco", "st,stm32f429"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@90000000 { - device_type = "memory"; - reg = <0x90000000 0x800000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - led-red { - gpios = <&gpiog 14 0>; - }; - led-green { - gpios = <&gpiog 13 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "User"; - linux,code = <KEY_HOME>; - gpios = <&gpioa 0 0>; - }; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - gpio = <&gpioc 4 0>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&crc { - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <100000>; - status = "okay"; - - stmpe811@41 { - compatible = "st,stmpe811"; - reg = <0x41>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioa>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - /* 8 sample average control */ - st,ave-ctrl = <3>; - /* 7 length fractional part in z */ - st,fraction-z = <7>; - /* - * 50 mA typical 80 mA max touchscreen drivers - * current limit value - */ - st,i-drive = <1>; - /* 1 ms panel driver settling time */ - st,settling = <3>; - /* 5 ms touch detect interrupt delay */ - st,touch-det-delay = <5>; - }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; - }; -}; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-names = "default"; - - port { - ltdc_out_rgb: endpoint { - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&rtc { - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSI>; - status = "okay"; -}; - -&spi5 { - status = "okay"; - pinctrl-0 = <&spi5_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>; - - l3gd20: l3gd20@0 { - compatible = "st,l3gd20-gyro"; - spi-max-frequency = <10000000>; - st,drdy-int-pin = <2>; - interrupt-parent = <&gpioa>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>, - <2 IRQ_TYPE_EDGE_RISING>; - reg = <0>; - status = "okay"; - }; - - display: display@1{ - /* Connect panel-ilitek-9341 to ltdc */ - compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341"; - reg = <1>; - spi-3wire; - spi-max-frequency = <10000000>; - dc-gpios = <&gpiod 13 0>; - port { - panel_in_rgb: endpoint { - remote-endpoint = <<dc_out_rgb>; - }; - }; - }; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - compatible = "st,stm32f4x9-fsotg"; - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi deleted file mode 100644 index 5be171eea50..00000000000 --- a/arch/arm/dts/stm32f429-pinctrl.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - */ - -#include "stm32f4-pinctrl.dtsi" - -&pinctrl { - compatible = "st,stm32f429-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; -}; diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi deleted file mode 100644 index 8133ea15b03..00000000000 --- a/arch/arm/dts/stm32f429.dtsi +++ /dev/null @@ -1,758 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> - * - */ - -#include "armv7-m.dtsi" -#include <dt-bindings/clock/stm32fx-clock.h> -#include <dt-bindings/mfd/stm32f4-rcc.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_i2s_ckin: i2s-ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - romem: efuse@1fff7800 { - compatible = "st,stm32f4-otp"; - reg = <0x1fff7800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ts_cal1: calib@22c { - reg = <0x22c 0x2>; - }; - ts_cal2: calib@22e { - reg = <0x22e 0x2>; - }; - }; - - timers2: timers@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - }; - - timers3: timers@40000400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000400 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - timers4: timers@40000800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000800 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - }; - - timers5: timers@40000c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000C00 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - }; - - timers6: timers@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - clock-names = "int"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timers@40001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001400 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - clock-names = "int"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timers@40001800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001800 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timers@40001c00 { - compatible = "st,stm32-timers"; - reg = <0x40001C00 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers14: timers@40002000 { - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - iwdg: watchdog@40003000 { - compatible = "st,stm32-iwdg"; - reg = <0x40003000 0x400>; - clocks = <&clk_lsi>; - clock-names = "lsi"; - status = "disabled"; - }; - - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; - status = "disabled"; - }; - - spi3: spi@40003c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40003c00 0x400>; - interrupts = <51>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; - status = "disabled"; - dmas = <&dma1 1 4 0x400 0x0>, - <&dma1 3 4 0x400 0x0>; - dma-names = "rx", "tx"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; - status = "disabled"; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f4-i2c"; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F4_APB1_RESET(I2C1)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@40005c00 { - compatible = "st,stm32f4-i2c"; - reg = <0x40005c00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32F4_APB1_RESET(I2C3)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@40006400 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40006400 0x200>; - interrupts = <19>, <20>, <21>, <22>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F4_APB1_RESET(CAN1)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; - st,can-primary; - st,gcan = <&gcan>; - status = "disabled"; - }; - - gcan: gcan@40006600 { - compatible = "st,stm32f4-gcan", "syscon"; - reg = <0x40006600 0x200>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; - }; - - can2: can@40006800 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40006800 0x200>; - interrupts = <63>, <64>, <65>, <66>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F4_APB1_RESET(CAN2)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; - st,can-secondary; - st,gcan = <&gcan>; - status = "disabled"; - }; - - dac: dac@40007400 { - compatible = "st,stm32f4-dac-core"; - reg = <0x40007400 0x400>; - resets = <&rcc STM32F4_APB1_RESET(DAC)>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - usart7: serial@40007800 { - compatible = "st,stm32-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; - status = "disabled"; - }; - - timers1: timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - }; - - timers8: timers@40010400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010400 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; - status = "disabled"; - dmas = <&dma2 2 4 0x400 0x0>, - <&dma2 7 4 0x400 0x0>; - dma-names = "rx", "tx"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; - status = "disabled"; - }; - - adc: adc@40012000 { - compatible = "st,stm32f4-adc-core"; - reg = <0x40012000 0x400>; - interrupts = <18>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; - clock-names = "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dma2 0 0 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dma2 3 1 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - - adc3: adc@200 { - compatible = "st,stm32f4-adc"; - #io-channel-cells = <1>; - reg = <0x200>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; - interrupt-parent = <&adc>; - interrupts = <2>; - dmas = <&dma2 1 2 0x400 0x0>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - sdio: mmc@40012c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; - clock-names = "apb_pclk"; - interrupts = <49>; - max-frequency = <48000000>; - status = "disabled"; - }; - - spi1: spi@40013000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40013000 0x400>; - interrupts = <35>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; - status = "disabled"; - }; - - spi4: spi@40013400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40013400 0x400>; - interrupts = <84>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; - status = "disabled"; - }; - - syscfg: syscon@40013800 { - compatible = "st,stm32-syscfg", "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - timers9: timers@40014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014000 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@8 { - compatible = "st,stm32-timer-trigger"; - reg = <8>; - status = "disabled"; - }; - }; - - timers10: timers@40014400 { - compatible = "st,stm32-timers"; - reg = <0x40014400 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers11: timers@40014800 { - compatible = "st,stm32-timers"; - reg = <0x40014800 0x400>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - spi5: spi@40015000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40015000 0x400>; - interrupts = <85>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; - dmas = <&dma2 3 2 0x400 0x0>, - <&dma2 4 2 0x400 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi6: spi@40015400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32f4-spi"; - reg = <0x40015400 0x400>; - interrupts = <86>; - clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; - status = "disabled"; - }; - - pwrcfg: power-config@40007000 { - compatible = "st,stm32-power-config", "syscon"; - reg = <0x40007000 0x400>; - }; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F4_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - status = "disabled"; - }; - - crc: crc@40023000 { - compatible = "st,stm32f4-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; - status = "disabled"; - }; - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - st,syscfg = <&pwrcfg>; - assigned-clocks = <&rcc 1 CLK_HSE_RTC>; - assigned-clock-rates = <1000000>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; - #dma-cells = <4>; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; - #dma-cells = <4>; - st,mem2mem; - }; - - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, - <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - snps,mixed-burst; - status = "disabled"; - }; - - dma2d: dma2d@4002b000 { - compatible = "st,stm32-dma2d"; - reg = <0x4002b000 0xc00>; - interrupts = <90>; - resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; - clock-names = "dma2d"; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "snps,dwc2"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; - clock-names = "otg"; - status = "disabled"; - }; - - usbotg_fs: usb@50000000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x50000000 0x40000>; - interrupts = <67>; - clocks = <&rcc 0 39>; - clock-names = "otg"; - status = "disabled"; - }; - - dcmi: dcmi@50050000 { - compatible = "st,stm32-dcmi"; - reg = <0x50050000 0x400>; - interrupts = <78>; - resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&dcmi_pins>; - dmas = <&dma2 1 1 0x414 0x3>; - dma-names = "tx"; - status = "disabled"; - }; - - rng: rng@50060800 { - compatible = "st,stm32-rng"; - reg = <0x50060800 0x400>; - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; - - }; - }; -}; - -&systick { - clocks = <&rcc 1 SYSTICK>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts deleted file mode 100644 index c9acabf0f53..00000000000 --- a/arch/arm/dts/stm32f469-disco.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2016 - Lee Jones <lee.jones@linaro.org> - * - */ - -/dts-v1/; -#include "stm32f469.dtsi" -#include "stm32f469-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "STMicroelectronics STM32F469i-DISCO board"; - compatible = "st,stm32f469i-disco", "st,stm32f469"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x1000000>; - }; - - aliases { - serial0 = &usart3; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_dsi: vdd-dsi { - compatible = "regulator-fixed"; - regulator-name = "vdd_dsi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - soc { - dma-ranges = <0xc0000000 0x0 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - led-orange { - gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; - }; - led-red { - gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; - }; - led-blue { - gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "User"; - linux,code = <KEY_WAKEUP>; - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - }; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; -}; - -&rcc { - compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc"; -}; - -&clk_hse { - clock-frequency = <8000000>; -}; - -&dma2d { - status = "okay"; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - - panel@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; /* dsi virtual channel (0..3) */ - reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; - power-supply = <&vdd_dsi>; - status = "okay"; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -<dc { - status = "okay"; - - port { - ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&timers1 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - status = "okay"; - - pwm { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - timer@2 { - status = "okay"; - }; -}; - -&sdio { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart3 { - pinctrl-0 = <&usart3_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_fs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi deleted file mode 100644 index 0610407c7b2..00000000000 --- a/arch/arm/dts/stm32f469-pinctrl.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - */ - -#include "stm32f4-pinctrl.dtsi" - -&pinctrl { - compatible = "st,stm32f469-pinctrl"; - - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; - - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; -}; diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi deleted file mode 100644 index 5f6a7976bb3..00000000000 --- a/arch/arm/dts/stm32f469.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ - -#include "stm32f429.dtsi" - -/ { - soc { - dsi: dsi@40016c00 { - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - resets = <&rcc STM32F4_APB2_RESET(DSI)>; - reset-names = "apb"; - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; - clock-names = "pclk", "ref"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi deleted file mode 100644 index d3706ee33b5..00000000000 --- a/arch/arm/dts/stm32f7-pinctrl.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#include <dt-bindings/pinctrl/stm32-pinfunc.h> -#include <dt-bindings/mfd/stm32f7-rcc.h> - -/ { - soc { - pinctrl: pinctrl@40020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; - }; - - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; - }; - - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; - }; - - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; - }; - - cec_pins_a: cec-0 { - pins { - pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */ - slew-rate = <0>; - drive-open-drain; - bias-disable; - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_pins_b: usart1-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */ - bias-disable; - }; - }; - - i2c1_pins_b: i2c1-0 { - pins { - pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */ - <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c3_pins_a: i2c3-0 { - pins { - pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */ - <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ - <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ - <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ - <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ - <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ - <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ - <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ - <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ - <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ - <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ - <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ - <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_hs_pins_b: usbotg-hs-1 { - pins { - pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ - <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */ - <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */ - <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */ - <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */ - <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */ - <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */ - <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */ - <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */ - <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */ - <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */ - <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - usbotg_fs_pins_a: usbotg-fs-0 { - pins { - pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ - <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ - <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_a: sdio-pins-a-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */ - <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od_a: sdio-pins-od-a-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */ - <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - sdio_pins_b: sdio-pins-b-0 { - pins { - pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ - <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */ - <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */ - <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */ - <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */ - <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */ - drive-push-pull; - slew-rate = <2>; - }; - }; - - sdio_pins_od_b: sdio-pins-od-b-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ - <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */ - <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */ - <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */ - <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */ - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */ - drive-open-drain; - slew-rate = <2>; - }; - }; - - can1_pins_a: can1-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ - bias-pull-up; - }; - }; - - can1_pins_b: can1-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */ - bias-pull-up; - }; - }; - - can1_pins_c: can1-2 { - pins1 { - pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ - bias-pull-up; - - }; - }; - - can1_pins_d: can1-3 { - pins1 { - pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ - bias-pull-up; - - }; - }; - - can2_pins_a: can2-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ - bias-pull-up; - }; - }; - - can2_pins_b: can2-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */ - bias-pull-up; - }; - }; - - can3_pins_a: can3-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */ - bias-pull-up; - }; - }; - - can3_pins_b: can3-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */ - bias-pull-up; - }; - }; - - ltdc_pins_a: ltdc-0 { - pins { - pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */ - <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */ - <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ - <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */ - <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */ - <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */ - <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ - <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ - <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ - <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ - <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ - <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ - <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ - <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ - <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ - <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ - <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */ - <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */ - <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */ - <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */ - <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */ - <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ - <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ - <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ - <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ - <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ - <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ - <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ - slew-rate = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 38d797e49a0..8ea4ea6c248 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -24,11 +24,6 @@ }; }; -<dc { - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - bootph-all; -}; - &fmc { /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { @@ -53,8 +48,14 @@ }; }; +<dc { + bootph-all; + + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; +}; + &panel_rgb { - compatible = "simple-panel"; + compatible = "rocktech,rk043fn48h", "simple-panel"; display-timings { timing@0 { diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts deleted file mode 100644 index 43127513403..00000000000 --- a/arch/arm/dts/stm32f746-disco.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com> - * - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f746-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "STMicroelectronics STM32F746-DISCO board"; - compatible = "st,stm32f746-disco", "st,stm32f746"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x800000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - no-map; - size = <0x80000>; - linux,dma-default; - }; - }; - - aliases { - serial0 = &usart1; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - /* This turns on vbus for otg fs for host mode (dwc2) */ - vcc5v_otg_fs: vcc5v-otg-fs-regulator { - compatible = "regulator-fixed"; - gpio = <&gpiod 5 0>; - regulator-name = "vcc5_host1"; - regulator-always-on; - }; - - vcc_3v3: vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - panel_rgb: panel-rgb { - compatible = "rocktech,rk043fn48h"; - power-supply = <&vcc_3v3>; - backlight = <&backlight>; - enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>; - status = "okay"; - port { - panel_in_rgb: endpoint { - remote-endpoint = <<dc_out_rgb>; - }; - }; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins_a>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5306"; - reg = <0x38>; - interrupt-parent = <&gpioi>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - }; -}; - -<dc { - pinctrl-0 = <<dc_pins_a>; - pinctrl-names = "default"; - status = "okay"; - - port { - ltdc_out_rgb: endpoint { - remote-endpoint = <&panel_in_rgb>; - }; - }; -}; - -&sdio1 { - status = "okay"; - vmmc-supply = <&vcc_3v3>; - cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_a>; - pinctrl-1 = <&sdio_pins_od_a>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_fs { - dr_mode = "host"; - pinctrl-0 = <&usbotg_fs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "host"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_b>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f746-pinctrl.dtsi b/arch/arm/dts/stm32f746-pinctrl.dtsi deleted file mode 100644 index fcfd2ac7239..00000000000 --- a/arch/arm/dts/stm32f746-pinctrl.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#include "stm32f7-pinctrl.dtsi" - -&pinctrl{ - compatible = "st,stm32f746-pinctrl"; -}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi deleted file mode 100644 index 79dad3192e1..00000000000 --- a/arch/arm/dts/stm32f746.dtsi +++ /dev/null @@ -1,613 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> - * - */ - -#include "armv7-m.dtsi" -#include <dt-bindings/clock/stm32fx-clock.h> -#include <dt-bindings/mfd/stm32f7-rcc.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_i2s_ckin: clk-i2s-ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - }; - - soc { - timers2: timers@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - }; - - timers3: timers@40000400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000400 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - timers4: timers@40000800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000800 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - }; - - timers5: timers@40000c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000C00 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - }; - - timers6: timers@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - clock-names = "int"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timers@40001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001400 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - clock-names = "int"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timers@40001800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001800 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timers@40001c00 { - compatible = "st,stm32-timers"; - reg = <0x40001C00 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers14: timers@40002000 { - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - rtc: rtc@40002800 { - compatible = "st,stm32-rtc"; - reg = <0x40002800 0x400>; - clocks = <&rcc 1 CLK_RTC>; - assigned-clocks = <&rcc 1 CLK_RTC>; - assigned-clock-parents = <&rcc 1 CLK_LSE>; - interrupt-parent = <&exti>; - interrupts = <17 1>; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - can3: can@40003400 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40003400 0x200>; - interrupts = <104>, <105>, <106>, <107>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F7_APB1_RESET(CAN3)>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; - st,gcan = <&gcan3>; - status = "disabled"; - }; - - gcan3: gcan@40003600 { - compatible = "st,stm32f4-gcan", "syscon"; - reg = <0x40003600 0x200>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; - }; - - usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - clocks = <&rcc 1 CLK_USART2>; - status = "disabled"; - }; - - usart3: serial@40004800 { - compatible = "st,stm32f7-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - clocks = <&rcc 1 CLK_USART3>; - status = "disabled"; - }; - - usart4: serial@40004c00 { - compatible = "st,stm32f7-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - clocks = <&rcc 1 CLK_UART4>; - status = "disabled"; - }; - - usart5: serial@40005000 { - compatible = "st,stm32f7-uart"; - reg = <0x40005000 0x400>; - interrupts = <53>; - clocks = <&rcc 1 CLK_UART5>; - status = "disabled"; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32F7_APB1_RESET(I2C1)>; - clocks = <&rcc 1 CLK_I2C1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@40005800 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005800 0x400>; - interrupts = <33>, - <34>; - resets = <&rcc STM32F7_APB1_RESET(I2C2)>; - clocks = <&rcc 1 CLK_I2C2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@40005c00 { - compatible = "st,stm32f7-i2c"; - reg = <0x40005c00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32F7_APB1_RESET(I2C3)>; - clocks = <&rcc 1 CLK_I2C3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@40006000 { - compatible = "st,stm32f7-i2c"; - reg = <0x40006000 0x400>; - interrupts = <95>, - <96>; - resets = <&rcc STM32F7_APB1_RESET(I2C4)>; - clocks = <&rcc 1 CLK_I2C4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@40006400 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40006400 0x200>; - interrupts = <19>, <20>, <21>, <22>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F7_APB1_RESET(CAN1)>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; - st,can-primary; - st,gcan = <&gcan1>; - status = "disabled"; - }; - - gcan1: gcan@40006600 { - compatible = "st,stm32f4-gcan", "syscon"; - reg = <0x40006600 0x200>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; - }; - - can2: can@40006800 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40006800 0x200>; - interrupts = <63>, <64>, <65>, <66>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F7_APB1_RESET(CAN2)>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; - st,can-secondary; - st,gcan = <&gcan1>; - status = "disabled"; - }; - - cec: cec@40006c00 { - compatible = "st,stm32-cec"; - reg = <0x40006C00 0x400>; - interrupts = <94>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - usart7: serial@40007800 { - compatible = "st,stm32f7-uart"; - reg = <0x40007800 0x400>; - interrupts = <82>; - clocks = <&rcc 1 CLK_UART7>; - status = "disabled"; - }; - - usart8: serial@40007c00 { - compatible = "st,stm32f7-uart"; - reg = <0x40007c00 0x400>; - interrupts = <83>; - clocks = <&rcc 1 CLK_UART8>; - status = "disabled"; - }; - - timers1: timers@40010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010000 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - }; - - timers8: timers@40010400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40010400 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 1 CLK_USART1>; - status = "disabled"; - }; - - usart6: serial@40011400 { - compatible = "st,stm32f7-uart"; - reg = <0x40011400 0x400>; - interrupts = <71>; - clocks = <&rcc 1 CLK_USART6>; - status = "disabled"; - }; - - sdio2: mmc@40011c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40011c00 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; - clock-names = "apb_pclk"; - interrupts = <103>; - max-frequency = <48000000>; - status = "disabled"; - }; - - sdio1: mmc@40012c00 { - compatible = "arm,pl180", "arm,primecell"; - arm,primecell-periphid = <0x00880180>; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; - clock-names = "apb_pclk"; - interrupts = <49>; - max-frequency = <48000000>; - status = "disabled"; - }; - - syscfg: syscon@40013800 { - compatible = "st,stm32-syscfg", "syscon"; - reg = <0x40013800 0x400>; - }; - - exti: interrupt-controller@40013c00 { - compatible = "st,stm32-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40013C00 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; - }; - - timers9: timers@40014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40014000 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@8 { - compatible = "st,stm32-timer-trigger"; - reg = <8>; - status = "disabled"; - }; - }; - - timers10: timers@40014400 { - compatible = "st,stm32-timers"; - reg = <0x40014400 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - timers11: timers@40014800 { - compatible = "st,stm32-timers"; - reg = <0x40014800 0x400>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 1 CLK_LCD>; - clock-names = "lcd"; - status = "disabled"; - }; - - pwrcfg: power-config@40007000 { - compatible = "st,stm32-power-config", "syscon"; - reg = <0x40007000 0x400>; - }; - - crc: crc@40023000 { - compatible = "st,stm32f7-crc"; - reg = <0x40023000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; - status = "disabled"; - }; - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f746-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - st,syscfg = <&pwrcfg>; - assigned-clocks = <&rcc 1 CLK_HSE_RTC>; - assigned-clock-rates = <1000000>; - }; - - dma1: dma-controller@40026000 { - compatible = "st,stm32-dma"; - reg = <0x40026000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; - #dma-cells = <4>; - status = "disabled"; - }; - - dma2: dma-controller@40026400 { - compatible = "st,stm32-dma"; - reg = <0x40026400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; - #dma-cells = <4>; - st,mem2mem; - status = "disabled"; - }; - - usbotg_hs: usb@40040000 { - compatible = "st,stm32f7-hsotg"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; - clock-names = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - usbotg_fs: usb@50000000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x50000000 0x40000>; - interrupts = <67>; - clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; - clock-names = "otg"; - status = "disabled"; - }; - }; -}; - -&systick { - clocks = <&rcc 1 0>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 7c99a6e61b6..8413264a73c 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -23,57 +23,13 @@ spi0 = &qspi; }; - panel: panel { - compatible = "orisetech,otm8009a"; - reset-gpios = <&gpioj 15 1>; - status = "okay"; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; - - soc { - dsi: dsi@40016c00 { - compatible = "st,stm32-dsi"; - reg = <0x40016c00 0x800>; - resets = <&rcc STM32F7_APB2_RESET(DSI)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, - <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, - <&clk_hse>; - clock-names = "pclk", "px_clk", "ref"; - bootph-all; - status = "okay"; - - ports { - port@0 { - dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - port@1 { - dsi_in: endpoint { - remote-endpoint = <&dp_out>; - }; - }; - }; - }; - }; }; -<dc { - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - bootph-all; - - ports { - port@0 { - dp_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; +&dsi { + clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, + <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, + <&clk_hse>; + clock-names = "pclk", "px_clk", "ref"; }; &fmc { @@ -100,6 +56,12 @@ }; }; +<dc { + bootph-all; + + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; +}; + &pinctrl { ethernet_mii: mii@0 { pins { diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts deleted file mode 100644 index d63cd2ba7eb..00000000000 --- a/arch/arm/dts/stm32f769-disco.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com> - * - */ - -/dts-v1/; -#include "stm32f746.dtsi" -#include "stm32f769-pinctrl.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f769"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x1000000>; - }; - - aliases { - serial0 = &usart1; - }; - - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - led-red { - gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - button-0 { - label = "User"; - linux,code = <KEY_HOME>; - gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; - }; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; - }; - - mmc_vcard: mmc_vcard { - compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&rcc { - compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc"; -}; - -&cec { - pinctrl-0 = <&cec_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -<dc { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdio2 { - status = "okay"; - vmmc-supply = <&mmc_vcard>; - cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; - broken-cd; - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins_b>; - pinctrl-1 = <&sdio_pins_od_b>; - bus-width = <4>; -}; - -&timers5 { - /* Override timer5 to act as clockevent */ - compatible = "st,stm32-timer"; - interrupts = <50>; - status = "okay"; - /delete-property/#address-cells; - /delete-property/#size-cells; - /delete-property/clock-names; - /delete-node/pwm; - /delete-node/timer@4; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32f769-pinctrl.dtsi b/arch/arm/dts/stm32f769-pinctrl.dtsi deleted file mode 100644 index 31005dd9929..00000000000 --- a/arch/arm/dts/stm32f769-pinctrl.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#include "stm32f7-pinctrl.dtsi" - -&pinctrl{ - compatible = "st,stm32f769-pinctrl"; -}; diff --git a/arch/arm/dts/stm32h7-pinctrl.dtsi b/arch/arm/dts/stm32h7-pinctrl.dtsi deleted file mode 100644 index aefa32468dc..00000000000 --- a/arch/arm/dts/stm32h7-pinctrl.dtsi +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/pinctrl/stm32-pinfunc.h> - -&pinctrl { - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */ - <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - ethernet_rmii: rmii-0 { - pins { - pinmux = <STM32_PINMUX('G', 11, AF11)>, - <STM32_PINMUX('G', 13, AF11)>, - <STM32_PINMUX('G', 12, AF11)>, - <STM32_PINMUX('C', 4, AF11)>, - <STM32_PINMUX('C', 5, AF11)>, - <STM32_PINMUX('A', 7, AF11)>, - <STM32_PINMUX('C', 1, AF11)>, - <STM32_PINMUX('A', 2, AF11)>, - <STM32_PINMUX('A', 1, AF11)>; - slew-rate = <2>; - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */ - slew-rate = <3>; - drive-push-pull; - bias-pull-up; - }; - pins2{ - pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */ - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins { - pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */ - <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */ - <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */ - <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */ - <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */ - <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */ - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - pins2{ - pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */ - slew-rate = <3>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */ - <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */ - <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */ - <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */ - }; - }; - - spi1_pins: spi1-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 5, AF5)>, - /* SPI1_CLK */ - <STM32_PINMUX('B', 5, AF5)>; - /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('G', 9, AF5)>; - /* SPI1_MISO */ - bias-disable; - }; - }; - - uart4_pins: uart4-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - usart1_pins: usart1-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */ - bias-disable; - }; - }; - - usart2_pins: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ - bias-disable; - }; - }; - - usart3_pins: usart3-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ - <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */ - <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */ - <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */ - <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */ - <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */ - <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */ - <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */ - <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */ - <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */ - <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */ - <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */ - <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; -}; diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index dea4db396c1..9148a1fcd4c 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -53,7 +53,6 @@ bootph-all; }; - &fmc { bootph-all; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi deleted file mode 100644 index c490d0a5713..00000000000 --- a/arch/arm/dts/stm32h743.dtsi +++ /dev/null @@ -1,695 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - */ - -#include "armv7-m.dtsi" -#include <dt-bindings/clock/stm32h7-clks.h> -#include <dt-bindings/mfd/stm32h7-rcc.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_i2s: i2s_ckin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - - soc { - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; - }; - - lptimer1: timer@40002400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40002400 0x400>; - clocks = <&rcc LPTIM1_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@40003800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003800 0x400>; - interrupts = <36>; - resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; - clocks = <&rcc SPI2_CK>; - status = "disabled"; - - }; - - spi3: spi@40003c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40003c00 0x400>; - interrupts = <51>; - resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; - clocks = <&rcc SPI3_CK>; - status = "disabled"; - }; - - usart2: serial@40004400 { - compatible = "st,stm32h7-uart"; - reg = <0x40004400 0x400>; - interrupts = <38>; - status = "disabled"; - clocks = <&rcc USART2_CK>; - }; - - usart3: serial@40004800 { - compatible = "st,stm32h7-uart"; - reg = <0x40004800 0x400>; - interrupts = <39>; - status = "disabled"; - clocks = <&rcc USART3_CK>; - }; - - uart4: serial@40004c00 { - compatible = "st,stm32h7-uart"; - reg = <0x40004c00 0x400>; - interrupts = <52>; - status = "disabled"; - clocks = <&rcc UART4_CK>; - }; - - i2c1: i2c@40005400 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005400 0x400>; - interrupts = <31>, - <32>; - resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; - clocks = <&rcc I2C1_CK>; - status = "disabled"; - }; - - i2c2: i2c@40005800 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005800 0x400>; - interrupts = <33>, - <34>; - resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; - clocks = <&rcc I2C2_CK>; - status = "disabled"; - }; - - i2c3: i2c@40005c00 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40005C00 0x400>; - interrupts = <72>, - <73>; - resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; - clocks = <&rcc I2C3_CK>; - status = "disabled"; - }; - - dac: dac@40007400 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40007400 0x400>; - clocks = <&rcc DAC12_CK>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - usart1: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - status = "disabled"; - clocks = <&rcc USART1_CK>; - }; - - spi1: spi@40013000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40013000 0x400>; - interrupts = <35>; - resets = <&rcc STM32H7_APB2_RESET(SPI1)>; - clocks = <&rcc SPI1_CK>; - status = "disabled"; - }; - - spi4: spi@40013400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40013400 0x400>; - interrupts = <84>; - resets = <&rcc STM32H7_APB2_RESET(SPI4)>; - clocks = <&rcc SPI4_CK>; - status = "disabled"; - }; - - spi5: spi@40015000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x40015000 0x400>; - interrupts = <85>; - resets = <&rcc STM32H7_APB2_RESET(SPI5)>; - clocks = <&rcc SPI5_CK>; - status = "disabled"; - }; - - dma1: dma-controller@40020000 { - compatible = "st,stm32-dma"; - reg = <0x40020000 0x400>; - interrupts = <11>, - <12>, - <13>, - <14>, - <15>, - <16>, - <17>, - <47>; - clocks = <&rcc DMA1_CK>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dma2: dma-controller@40020400 { - compatible = "st,stm32-dma"; - reg = <0x40020400 0x400>; - interrupts = <56>, - <57>, - <58>, - <59>, - <60>, - <68>, - <69>, - <70>; - clocks = <&rcc DMA2_CK>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - status = "disabled"; - }; - - dmamux1: dma-router@40020800 { - compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x40>; - #dma-cells = <3>; - dma-channels = <16>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - clocks = <&rcc DMA1_CK>; - }; - - adc_12: adc@40022000 { - compatible = "st,stm32h7-adc-core"; - reg = <0x40022000 0x400>; - interrupts = <18>; - clocks = <&rcc ADC12_CK>; - clock-names = "bus"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc_12>; - interrupts = <0>; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x100>; - interrupt-parent = <&adc_12>; - interrupts = <1>; - status = "disabled"; - }; - }; - - usbotg_hs: usb@40040000 { - compatible = "st,stm32f7-hsotg"; - reg = <0x40040000 0x40000>; - interrupts = <77>; - clocks = <&rcc USB1OTG_CK>; - clock-names = "otg"; - g-rx-fifo-size = <256>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; - status = "disabled"; - }; - - usbotg_fs: usb@40080000 { - compatible = "st,stm32f4x9-fsotg"; - reg = <0x40080000 0x40000>; - interrupts = <101>; - clocks = <&rcc USB2OTG_CK>; - clock-names = "otg"; - status = "disabled"; - }; - - ltdc: display-controller@50001000 { - compatible = "st,stm32-ltdc"; - reg = <0x50001000 0x200>; - interrupts = <88>, <89>; - resets = <&rcc STM32H7_APB3_RESET(LTDC)>; - clocks = <&rcc LTDC_CK>; - clock-names = "lcd"; - status = "disabled"; - }; - - mdma1: dma-controller@52000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x52000000 0x1000>; - interrupts = <122>; - clocks = <&rcc MDMA_CK>; - #dma-cells = <5>; - dma-channels = <16>; - dma-requests = <32>; - }; - - sdmmc1: mmc@52007000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x52007000 0x1000>; - interrupts = <49>; - clocks = <&rcc SDMMC1_CK>; - clock-names = "apb_pclk"; - resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - }; - - sdmmc2: mmc@48022400 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; - reg = <0x48022400 0x400>; - interrupts = <124>; - clocks = <&rcc SDMMC2_CK>; - clock-names = "apb_pclk"; - resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - exti: interrupt-controller@58000000 { - compatible = "st,stm32h7-exti"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x58000000 0x400>; - interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; - }; - - syscfg: syscon@58000400 { - compatible = "st,stm32-syscfg", "syscon"; - reg = <0x58000400 0x400>; - }; - - spi6: spi@58001400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x58001400 0x400>; - interrupts = <86>; - resets = <&rcc STM32H7_APB4_RESET(SPI6)>; - clocks = <&rcc SPI6_CK>; - status = "disabled"; - }; - - i2c4: i2c@58001c00 { - compatible = "st,stm32f7-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x58001C00 0x400>; - interrupts = <95>, - <96>; - resets = <&rcc STM32H7_APB4_RESET(I2C4)>; - clocks = <&rcc I2C4_CK>; - status = "disabled"; - }; - - lptimer2: timer@58002400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002400 0x400>; - clocks = <&rcc LPTIM2_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@58002800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x58002800 0x400>; - clocks = <&rcc LPTIM3_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@58002c00 { - compatible = "st,stm32-lptimer"; - reg = <0x58002c00 0x400>; - clocks = <&rcc LPTIM4_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@58003000 { - compatible = "st,stm32-lptimer"; - reg = <0x58003000 0x400>; - clocks = <&rcc LPTIM5_CK>; - clock-names = "mux"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: regulator@58003c00 { - compatible = "st,stm32-vrefbuf"; - reg = <0x58003C00 0x8>; - clocks = <&rcc VREF_CK>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - status = "disabled"; - }; - - rtc: rtc@58004000 { - compatible = "st,stm32h7-rtc"; - reg = <0x58004000 0x400>; - clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; - clock-names = "pclk", "rtc_ck"; - assigned-clocks = <&rcc RTC_CK>; - assigned-clock-parents = <&rcc LSE_CK>; - interrupt-parent = <&exti>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - st,syscfg = <&pwrcfg 0x00 0x100>; - status = "disabled"; - }; - - rcc: reset-clock-controller@58024400 { - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; - st,syscfg = <&pwrcfg>; - }; - - pwrcfg: power-config@58024800 { - compatible = "st,stm32-power-config", "syscon"; - reg = <0x58024800 0x400>; - }; - - adc_3: adc@58026000 { - compatible = "st,stm32h7-adc-core"; - reg = <0x58026000 0x400>; - interrupts = <127>; - clocks = <&rcc ADC3_CK>; - clock-names = "bus"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc3: adc@0 { - compatible = "st,stm32h7-adc"; - #io-channel-cells = <1>; - reg = <0x0>; - interrupt-parent = <&adc_3>; - interrupts = <0>; - status = "disabled"; - }; - }; - - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <61>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - status = "disabled"; - }; - - pinctrl: pinctrl@58020000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32h743-pinctrl"; - ranges = <0 0x58020000 0x3000>; - interrupt-parent = <&exti>; - st,syscfg = <&syscfg 0x8>; - pins-are-numbered; - - gpioa: gpio@58020000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA_CK>; - st,bank-name = "GPIOA"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@58020400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - clocks = <&rcc GPIOB_CK>; - st,bank-name = "GPIOB"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@58020800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - clocks = <&rcc GPIOC_CK>; - st,bank-name = "GPIOC"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@58020c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - clocks = <&rcc GPIOD_CK>; - st,bank-name = "GPIOD"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@58021000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOE_CK>; - st,bank-name = "GPIOE"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@58021400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - clocks = <&rcc GPIOF_CK>; - st,bank-name = "GPIOF"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@58021800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - clocks = <&rcc GPIOG_CK>; - st,bank-name = "GPIOG"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@58021c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - clocks = <&rcc GPIOH_CK>; - st,bank-name = "GPIOH"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@58022000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOI_CK>; - st,bank-name = "GPIOI"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@58022400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2400 0x400>; - clocks = <&rcc GPIOJ_CK>; - st,bank-name = "GPIOJ"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@58022800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x2800 0x400>; - clocks = <&rcc GPIOK_CK>; - st,bank-name = "GPIOK"; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; - }; -}; - -&systick { - clock-frequency = <250000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts deleted file mode 100644 index b31188f8b9b..00000000000 --- a/arch/arm/dts/stm32h743i-disco.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2017 - Patrice Chotard <patrice.chotard@foss.st.com> - * - */ - -/dts-v1/; -#include "stm32h743.dtsi" -#include "stm32h7-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32H743i-Discovery board"; - compatible = "st,stm32h743i-disco", "st,stm32h743"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@d0000000 { - device_type = "memory"; - reg = <0xd0000000 0x2000000>; - }; - - aliases { - serial0 = &usart2; - }; - - v3v3: regulator-v3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&usart2 { - pinctrl-0 = <&usart2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts deleted file mode 100644 index 5c5d8059bdc..00000000000 --- a/arch/arm/dts/stm32h743i-eval.dts +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "stm32h743.dtsi" -#include "stm32h7-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32H743i-EVAL board"; - compatible = "st,stm32h743i-eval", "st,stm32h743"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:115200n8"; - }; - - memory@d0000000 { - device_type = "memory"; - reg = <0xd0000000 0x2000000>; - }; - - aliases { - serial0 = &usart1; - }; - - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2v9_sd: regulator-v2v9_sd { - compatible = "regulator-fixed"; - regulator-name = "v2v9_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - usbotg_hs_phy: usb-phy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc USB1ULPI_CK>; - clock-names = "main_clk"; - }; -}; - -&adc_12 { - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - adc1: adc@0 { - /* potentiometer */ - st,adc-channels = <0>; - status = "okay"; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-names = "default"; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&v2v9_sd>; - status = "okay"; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbotg_hs_phy>; - phy-names = "usb2-phy"; - dr_mode = "otg"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32h750.dtsi b/arch/arm/dts/stm32h750.dtsi deleted file mode 100644 index 99533f356b5..00000000000 --- a/arch/arm/dts/stm32h750.dtsi +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */ - -#include "stm32h743.dtsi" - diff --git a/arch/arm/dts/stm32h750i-art-pi.dts b/arch/arm/dts/stm32h750i-art-pi.dts deleted file mode 100644 index c7c7132f227..00000000000 --- a/arch/arm/dts/stm32h750i-art-pi.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com> - * - */ - -/dts-v1/; -#include "stm32h750.dtsi" -#include "stm32h7-pinctrl.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "RT-Thread STM32H750i-ART-PI board"; - compatible = "st,stm32h750i-art-pi", "st,stm32h750"; - - chosen { - bootargs = "root=/dev/ram"; - stdout-path = "serial0:2000000n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x2000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - no-map; - size = <0x100000>; - linux,dma-default; - }; - }; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - }; - - leds { - compatible = "gpio-leds"; - led-red { - gpios = <&gpioi 8 0>; - }; - led-green { - gpios = <&gpioc 15 0>; - linux,default-trigger = "heartbeat"; - }; - }; - - v3v3: regulator-v3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - wlan_pwr: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; - -&dma1 { - status = "okay"; -}; - -&dma2 { - status = "okay"; -}; - -&mac { - status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; - broken-cd; - non-removable; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&wlan_pwr>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - - partition@0 { - label = "root filesystem"; - reg = <0 0x1000000>; - }; - }; -}; - -&usart2 { - pinctrl-0 = <&usart2_pins>; - pinctrl-names = "default"; - status = "disabled"; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins>; - dmas = <&dmamux1 45 0x400 0x05>, - <&dmamux1 46 0x400 0x05>; - dma-names = "rx", "tx"; - st,hw-flow-ctrl; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; - max-speed = <115200>; - }; -}; - -&uart4 { - pinctrl-0 = <&uart4_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi deleted file mode 100644 index 52c2a9f24d7..00000000000 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ /dev/null @@ -1,888 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> - */ -#include <dt-bindings/pinctrl/stm32-pinfunc.h> - -&pinctrl { - adc1_pins_a: adc1-pins-0 { - pins { - pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ - }; - }; - - adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { - pins { - pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ - <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ - }; - }; - - adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { - pins { - pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ - <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ - }; - }; - - eth1_rgmii_pins_a: eth1-rgmii-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ - <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ - <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ - bias-disable; - }; - - }; - - eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ - <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ - }; - }; - - eth2_rgmii_pins_a: eth2-rgmii-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ - <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ - <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ - bias-disable; - }; - }; - - eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ - <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ - }; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ - <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_sleep_pins_a: i2c1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ - <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ - }; - }; - - i2c5_pins_a: i2c5-0 { - pins { - pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ - <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_a: i2c5-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ - <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ - }; - }; - - i2c5_pins_b: i2c5-1 { - pins { - pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ - <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_b: i2c5-sleep-1 { - pins { - pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ - <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ - }; - }; - - m_can1_pins_a: m-can1-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_a: m_can1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ - <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ - }; - }; - - m_can2_pins_a: m-can2-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ - bias-disable; - }; - }; - - m_can2_sleep_pins_a: m_can2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ - <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ - }; - }; - - mcp23017_pins_a: mcp23017-0 { - pins { - pinmux = <STM32_PINMUX('G', 12, GPIO)>; - bias-pull-up; - }; - }; - - pwm1_ch3n_pins_a: pwm1-ch3n-0 { - pins { - pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 { - pins { - pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */ - }; - }; - - pwm3_pins_a: pwm3-0 { - pins { - pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_a: pwm3-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ - }; - }; - - pwm4_pins_a: pwm4-0 { - pins { - pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_a: pwm4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ - }; - }; - - pwm5_pins_a: pwm5-0 { - pins { - pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_sleep_pins_a: pwm5-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ - }; - }; - - pwm8_pins_a: pwm8-0 { - pins { - pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm8_sleep_pins_a: pwm8-sleep-0 { - pins { - pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ - }; - }; - - pwm13_pins_a: pwm13-0 { - pins { - pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm13_sleep_pins_a: pwm13-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ - }; - }; - - pwm14_pins_a: pwm14-0 { - pins { - pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm14_sleep_pins_a: pwm14-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ - }; - }; - - qspi_clk_pins_a: qspi-clk-0 { - pins { - pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ - }; - }; - - qspi_bk1_pins_a: qspi-bk1-0 { - pins { - pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ - <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ - <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ - <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ - <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ - }; - }; - - qspi_cs1_pins_a: qspi-cs1-0 { - pins { - pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ - }; - }; - - sai1a_pins_a: sai1a-0 { - pins { - pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ - <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ - <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai1a_sleep_pins_a: sai1a-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ - <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ - <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ - }; - }; - - sai1b_pins_a: sai1b-0 { - pins { - pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ - bias-disable; - }; - }; - - sai1b_sleep_pins_a: sai1b-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_clk_pins_a: sdmmc1-clk-0 { - pins { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins { - pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ - <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ - <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ - <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ - }; - }; - - sdmmc2_clk_pins_a: sdmmc2-clk-0 { - pins { - pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_pins_a: sdmmc2-d47-0 { - pins { - pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ - <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ - }; - }; - - spi2_pins_a: spi2-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ - <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ - bias-disable; - }; - }; - - spi2_sleep_pins_a: spi2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ - <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ - <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ - }; - }; - - spi3_pins_a: spi3-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ - <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ - bias-disable; - }; - }; - - spi3_sleep_pins_a: spi3-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ - <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ - <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ - }; - }; - - spi5_pins_a: spi5-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ - <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ - bias-disable; - }; - }; - - spi5_sleep_pins_a: spi5-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ - <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ - <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ - }; - }; - - stm32g0_intn_pins_a: stm32g0-intn-0 { - pins { - pinmux = <STM32_PINMUX('I', 2, GPIO)>; - bias-pull-up; - }; - }; - - uart4_pins_a: uart4-0 { - pins1 { - pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_sleep_pins_a: uart4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */ - <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ - }; - }; - - uart4_pins_b: uart4-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ - bias-pull-up; - }; - }; - - uart4_idle_pins_b: uart4-idle-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ - bias-pull-up; - }; - }; - - uart4_sleep_pins_b: uart4-sleep-1 { - pins { - pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ - <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ - }; - }; - - uart7_pins_a: uart7-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ - <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ - <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ - bias-disable; - }; - }; - - uart7_idle_pins_a: uart7-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ - <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ - bias-disable; - }; - }; - - uart7_sleep_pins_a: uart7-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ - <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ - <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ - <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ - }; - }; - - uart8_pins_a: uart8-0 { - pins1 { - pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ - bias-pull-up; - }; - }; - - uart8_idle_pins_a: uart8-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ - bias-pull-up; - }; - }; - - uart8_sleep_pins_a: uart8-sleep-0 { - pins { - pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */ - <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */ - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ - <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ - <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ - bias-pull-up; - }; - }; - - usart1_idle_pins_a: usart1-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ - <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */ - bias-pull-up; - }; - }; - - usart1_sleep_pins_a: usart1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ - <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */ - <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */ - <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */ - }; - }; - - usart1_pins_b: usart1-1 { - pins1 { - pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ - bias-pull-up; - }; - }; - - usart1_idle_pins_b: usart1-idle-1 { - pins1 { - pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ - bias-pull-up; - }; - }; - - usart1_sleep_pins_b: usart1-sleep-1 { - pins { - pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ - <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ - }; - }; - - usart2_pins_a: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ - <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_idle_pins_a: usart2-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_b: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ - <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ - <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_idle_pins_b: usart2-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_sleep_pins_b: usart2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; -}; diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index af7edc7e2b2..1fe6966781c 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -48,6 +48,10 @@ bootph-all; }; +&etzpc { + bootph-all; +}; + &gpioa { bootph-all; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi deleted file mode 100644 index ad331b73d18..00000000000 --- a/arch/arm/dts/stm32mp131.dtsi +++ /dev/null @@ -1,1567 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/stm32mp13-clks.h> -#include <dt-bindings/reset/stm32mp13-resets.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; - interrupt-parent = <&intc>; - }; - - firmware { - optee { - method = "smc"; - compatible = "linaro,optee-tz"; - interrupt-parent = <&intc>; - interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; - - scmi: scmi { - compatible = "linaro,scmi-optee"; - #address-cells = <1>; - #size-cells = <0>; - linaro,optee-channel-id = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - - scmi_voltd: protocol@17 { - reg = <0x17>; - - scmi_regu: regulators { - #address-cells = <1>; - #size-cells = <0>; - - scmi_reg11: regulator@0 { - reg = <VOLTD_SCMI_REG11>; - regulator-name = "reg11"; - }; - scmi_reg18: regulator@1 { - reg = <VOLTD_SCMI_REG18>; - regulator-name = "reg18"; - }; - scmi_usb33: regulator@2 { - reg = <VOLTD_SCMI_USB33>; - regulator-name = "usb33"; - }; - }; - }; - }; - }; - - intc: interrupt-controller@a0021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xa0021000 0x1000>, - <0xa0022000 0x2000>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-parent = <&intc>; - always-on; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4000b000 0x400>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi2: spi@4000b000 { - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4000c000 0x400>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi3: spi@4000c000 { - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - reg = <0x4000d000 0x400>; - #sound-dai-cells = <0>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; - - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - resets = <&rcc USART3_R>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x5>, - <&dmamux1 46 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - resets = <&rcc UART4_R>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x5>, - <&dmamux1 64 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - resets = <&rcc UART5_R>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x5>, - <&dmamux1 66 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c1: i2c@40012000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 33 0x400 0x1>, - <&dmamux1 34 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c2: i2c@40013000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 35 0x400 0x1>, - <&dmamux1 36 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - i2c-analog-filter; - status = "disabled"; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - resets = <&rcc UART7_R>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x5>, - <&dmamux1 80 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - resets = <&rcc UART8_R>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x5>, - <&dmamux1 82 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - resets = <&rcc USART6_R>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x5>, - <&dmamux1 72 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - reg = <0x44004000 0x400>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - ranges = <0 0x4400a000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI1_R>; - status = "disabled"; - - sai1a: audio-controller@4400a004 { - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; - - sai1b: audio-controller@4400a024 { - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; - }; - }; - - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - ranges = <0 0x4400b000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI2_R>; - status = "disabled"; - - sai2a: audio-controller@4400b004 { - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; - - sai2b: audio-controller@4400b024 { - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - #sound-dai-cells = <0>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; - }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - reg = <0>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - reg = <1>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - clocks = <&rcc DMAMUX1>; - resets = <&rcc DMAMUX1_R>; - #dma-cells = <3>; - dma-masters = <&dma1 &dma2>; - dma-requests = <128>; - dma-channels = <16>; - }; - - adc_2: adc@48004000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48004000 0x400>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc ADC2>, <&rcc ADC2_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc2: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_2>; - interrupts = <0>; - dmas = <&dmamux1 10 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - channel@16 { - reg = <16>; - label = "vddcpu"; - }; - channel@17 { - reg = <17>; - label = "vddq_ddr"; - }; - }; - }; - - usbotg_hs: usb@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x40000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&scmi_usb33>; - status = "disabled"; - }; - - usart1: serial@4c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - resets = <&rcc USART1_R>; - wakeup-source; - dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart2: serial@4c001000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c001000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - resets = <&rcc USART2_R>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s4: audio-controller@4c002000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4c002000 0x400>; - #sound-dai-cells = <0>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@4c002000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c002000 0x400>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi5: spi@4c003000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c003000 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 85 0x400 0x01>, - <&dmamux1 86 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c3: i2c@4c004000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c004000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 73 0x400 0x1>, - <&dmamux1 74 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c4: i2c@4c005000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c005000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 75 0x400 0x1>, - <&dmamux1 76 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@4c006000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c006000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 115 0x400 0x1>, - <&dmamux1 116 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - i2c-analog-filter; - status = "disabled"; - }; - - timers12: timer@4c007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c007000 0x400>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@4c008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c008000 0x400>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@4c009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c009000 0x400>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - timers15: timer@4c00a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00a000 0x400>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@4c00b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00b000 0x400>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@4c00c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00c000 0x400>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - - rcc: rcc@50000000 { - compatible = "st,stm32mp13-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; - }; - - pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; - status = "disabled"; - - reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp13-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; - - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - rng: rng@54004000 { - compatible = "st,stm32mp13-rng"; - reg = <0x54004000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - - mdma: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc MDMA>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; - - fmc: memory-controller@58002000 { - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - #address-cells = <2>; - #size-cells = <1>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - nand-controller@4,0 { - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, - <&mdma 24 0x2 0x12000a08 0x0 0x0>, - <&mdma 25 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, - <&mdma 26 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - eth1: eth1@5800a000 { - compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, - <&exti 68 1>; - interrupt-names = "macirq", "eth_wake_irq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "ethstp", - "eth-ck"; - clocks = <&rcc ETH1MAC>, - <&rcc ETH1TX>, - <&rcc ETH1RX>, - <&rcc ETH1STP>, - <&rcc ETH1CK_K>; - st,syscon = <&syscfg 0x4 0xff0000>; - snps,mixed-burst; - snps,pbl = <2>; - snps,axi-config = <&stmmac_axi_config_1>; - snps,tso; - status = "disabled"; - - stmmac_axi_config_1: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - }; - - usbh_ohci: usb@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usbh_ehci: usb@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <&scmi_reg11>; - vdda1v8-supply = <&scmi_reg18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scmi_clk CK_SCMI_RTCAPB>, - <&scmi_clk CK_SCMI_RTC>; - clock-names = "pclk", "rtc_ck"; - status = "disabled"; - }; - - bsec: efuse@5c005000 { - compatible = "st,stm32mp13-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - part_number_otp: part_number_otp@4 { - reg = <0x4 0x2>; - bits = <0 12>; - }; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; - ethernet_mac1_address: mac1@e4 { - reg = <0xe4 0x6>; - }; - ethernet_mac2_address: mac2@ea { - reg = <0xea 0x6>; - }; - }; - - /* - * Break node order to solve dependency probe issue between - * pinctrl and exti. - */ - pinctrl: pinctrl@50002000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp135-pinctrl"; - ranges = <0 0x50002000 0x8400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioa: gpio@50002000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA>; - st,bank-name = "GPIOA"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOB>; - st,bank-name = "GPIOB"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOC>; - st,bank-name = "GPIOC"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x400>; - clocks = <&rcc GPIOD>; - st,bank-name = "GPIOD"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x400>; - clocks = <&rcc GPIOE>; - st,bank-name = "GPIOE"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x400>; - clocks = <&rcc GPIOF>; - st,bank-name = "GPIOF"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x400>; - clocks = <&rcc GPIOG>; - st,bank-name = "GPIOG"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x400>; - clocks = <&rcc GPIOH>; - st,bank-name = "GPIOH"; - ngpios = <15>; - gpio-ranges = <&pinctrl 0 112 15>; - }; - - gpioi: gpio@5000a000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x400>; - clocks = <&rcc GPIOI>; - st,bank-name = "GPIOI"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 128 8>; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi deleted file mode 100644 index 5cd5bde9535..00000000000 --- a/arch/arm/dts/stm32mp133.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -#include "stm32mp131.dtsi" - -/ { - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - adc_1: adc@48003000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48003000 0x400>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc ADC1>, <&rcc ADC1_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_1>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@18 { - reg = <18>; - label = "vrefint"; - }; - }; - }; - - eth2: eth2@5800e000 { - compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac"; - reg = <0x5800e000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "ethstp", - "eth-ck"; - clocks = <&rcc ETH2MAC>, - <&rcc ETH2TX>, - <&rcc ETH2RX>, - <&rcc ETH2STP>, - <&rcc ETH2CK_K>; - st,syscon = <&syscfg 0x4 0xff000000>; - snps,mixed-burst; - snps,pbl = <2>; - snps,axi-config = <&stmmac_axi_config_2>; - snps,tso; - status = "disabled"; - - stmmac_axi_config_2: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi deleted file mode 100644 index abf2acd37b4..00000000000 --- a/arch/arm/dts/stm32mp135.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -#include "stm32mp133.dtsi" - -/ { - soc { - }; -}; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts deleted file mode 100644 index 275823da3c6..00000000000 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pwm/pwm.h> -#include <dt-bindings/regulator/st,stm32mp13-regulator.h> -#include "stm32mp135.dtsi" -#include "stm32mp13xf.dtsi" -#include "stm32mp13-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32MP135F-DK Discovery Board"; - compatible = "st,stm32mp135f-dk", "st,stm32mp135"; - - aliases { - serial0 = &uart4; - serial1 = &usart1; - serial2 = &uart8; - serial3 = &usart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - optee@dd000000 { - reg = <0xdd000000 0x3000000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-user { - label = "User-PA13"; - linux,code = <BTN_1>; - gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - function = LED_FUNCTION_HEARTBEAT; - color = <LED_COLOR_ID_BLUE>; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&adc_1 { - pinctrl-names = "default"; - pinctrl-0 = <&adc1_usb_cc_pins_a>; - vdda-supply = <&scmi_vdd_adc>; - vref-supply = <&scmi_vdd_adc>; - status = "okay"; - adc1: adc@0 { - status = "okay"; - /* - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: - * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. - * Use arbitrary margin here (e.g. 5us). - */ - channel@6 { - reg = <6>; - st,min-sample-time-ns = <5000>; - }; - channel@12 { - reg = <12>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <96>; - i2c-scl-falling-time-ns = <3>; - clock-frequency = <1000000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - mcp23017: pinctrl@21 { - compatible = "microchip,mcp23017"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpiog>; - pinctrl-names = "default"; - pinctrl-0 = <&mcp23017_pins_a>; - interrupt-controller; - #interrupt-cells = <2>; - microchip,irq-mirror; - }; - - typec@53 { - compatible = "st,stm32g0-typec"; - reg = <0x53>; - /* Alert pin on PI2 */ - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioi>; - /* Internal pull-up on PI2 */ - pinctrl-names = "default"; - pinctrl-0 = <&stm32g0_intn_pins_a>; - firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - - port { - con_usb_c_g0_ep: endpoint { - remote-endpoint = <&usbotg_hs_ep>; - }; - }; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <170>; - i2c-scl-falling-time-ns = <5>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&scmi_regu { - scmi_vdd_adc: regulator@10 { - reg = <VOLTD_SCMI_STPMIC1_LDO1>; - regulator-name = "vdd_adc"; - }; - scmi_vdd_usb: regulator@13 { - reg = <VOLTD_SCMI_STPMIC1_LDO4>; - regulator-name = "vdd_usb"; - }; - scmi_vdd_sd: regulator@14 { - reg = <VOLTD_SCMI_STPMIC1_LDO5>; - regulator-name = "vdd_sd"; - }; - scmi_v1v8_periph: regulator@15 { - reg = <VOLTD_SCMI_STPMIC1_LDO6>; - regulator-name = "v1v8_periph"; - }; - scmi_v3v3_sw: regulator@19 { - reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>; - regulator-name = "v3v3_sw"; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&scmi_vdd_sd>; - status = "okay"; -}; - -&spi5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_pins_a>; - pinctrl-1 = <&spi5_sleep_pins_a>; - status = "disabled"; -}; - -&timers1 { - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm1: pwm { - pinctrl-0 = <&pwm1_ch3n_pins_a>; - pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; -}; - -&timers3 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm3_pins_a>; - pinctrl-1 = <&pwm3_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@2 { - status = "okay"; - }; -}; - -&timers4 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm4_pins_a>; - pinctrl-1 = <&pwm4_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@3 { - status = "okay"; - }; -}; - -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-1 = <&pwm8_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@7 { - status = "okay"; - }; -}; - -&timers14 { - status = "disabled"; - pwm { - pinctrl-0 = <&pwm14_pins_a>; - pinctrl-1 = <&pwm14_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@13 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart8_pins_a>; - pinctrl-1 = <&uart8_sleep_pins_a>; - pinctrl-2 = <&uart8_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; -}; - -&usart1 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart1_pins_a>; - pinctrl-1 = <&usart1_sleep_pins_a>; - pinctrl-2 = <&usart1_idle_pins_a>; - uart-has-rtscts; - status = "disabled"; -}; - -/* Bluetooth */ -&usart2 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_sleep_pins_a>; - pinctrl-2 = <&usart2_idle_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - /* onboard HUB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - vdd-supply = <&scmi_v3v3_sw>; - }; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - usb-role-switch; - status = "okay"; - port { - usbotg_hs_ep: endpoint { - remote-endpoint = <&con_usb_c_g0_ep>; - }; - }; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&scmi_vdd_usb>; - st,current-boost-microamp = <1000>; - st,decrease-hs-slew-rate; - st,tune-hs-dc-level = <2>; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <11>; - st,trim-hs-impedance = <2>; - st,tune-squelch-level = <1>; - st,enable-hs-rx-gain-eq; - st,no-hs-ftime-ctrl; - st,no-lsfs-sc; -}; - -&usbphyc_port1 { - phy-supply = <&scmi_vdd_usb>; - st,current-boost-microamp = <1000>; - st,decrease-hs-slew-rate; - st,tune-hs-dc-level = <2>; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <11>; - st,trim-hs-impedance = <2>; - st,tune-squelch-level = <1>; - st,enable-hs-rx-gain-eq; - st,no-hs-ftime-ctrl; - st,no-lsfs-sc; -}; diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi deleted file mode 100644 index 4d00e759288..00000000000 --- a/arch/arm/dts/stm32mp13xc.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi deleted file mode 100644 index 4d00e759288..00000000000 --- a/arch/arm/dts/stm32mp13xf.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2021 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi deleted file mode 100644 index 098153ee99a..00000000000 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ /dev/null @@ -1,2826 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. - */ -#include <dt-bindings/pinctrl/stm32-pinfunc.h> - -&pinctrl { - adc1_ain_pins_a: adc1-ain-0 { - pins { - pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */ - <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */ - <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */ - <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */ - <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */ - <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */ - }; - }; - - adc1_in6_pins_a: adc1-in6-0 { - pins { - pinmux = <STM32_PINMUX('F', 12, ANALOG)>; - }; - }; - - adc12_ain_pins_a: adc12-ain-0 { - pins { - pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ - <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ - <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ - <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ - }; - }; - - adc12_ain_pins_b: adc12-ain-1 { - pins { - pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ - <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ - }; - }; - - adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { - pins { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ - <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ - }; - }; - - cec_pins_a: cec-0 { - pins { - pinmux = <STM32_PINMUX('A', 15, AF4)>; - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - cec_sleep_pins_a: cec-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ - }; - }; - - cec_pins_b: cec-1 { - pins { - pinmux = <STM32_PINMUX('B', 6, AF5)>; - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - cec_sleep_pins_b: cec-sleep-1 { - pins { - pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ - }; - }; - - dac_ch1_pins_a: dac-ch1-0 { - pins { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>; - }; - }; - - dac_ch2_pins_a: dac-ch2-0 { - pins { - pinmux = <STM32_PINMUX('A', 5, ANALOG)>; - }; - }; - - dcmi_pins_a: dcmi-0 { - pins { - pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ - <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ - <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ - <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ - <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ - <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ - <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ - <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ - <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ - <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ - <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ - <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ - <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ - bias-disable; - }; - }; - - dcmi_sleep_pins_a: dcmi-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ - <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ - <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ - <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ - <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ - <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ - <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ - <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ - <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ - <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ - <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ - <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ - <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ - }; - }; - - dcmi_pins_b: dcmi-1 { - pins { - pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ - <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ - <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ - <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ - <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ - <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ - <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ - <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ - <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ - bias-disable; - }; - }; - - dcmi_sleep_pins_b: dcmi-sleep-1 { - pins { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ - <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ - <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ - <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ - <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ - <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ - <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ - <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ - <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ - }; - }; - - dcmi_pins_c: dcmi-2 { - pins { - pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ - <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ - <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ - <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ - <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ - <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ - <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ - <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ - <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ - <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ - <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ - bias-pull-up; - }; - }; - - dcmi_sleep_pins_c: dcmi-sleep-2 { - pins { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ - <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ - <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ - <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ - <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ - <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ - <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ - <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ - <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ - <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ - <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ - <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ - <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ - }; - }; - - ethernet0_rgmii_pins_a: rgmii-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_b: rgmii-1 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_c: rgmii-2 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_d: rgmii-3 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { - pins1 { - pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ - <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rgmii_pins_e: rgmii-4 { - pins1 { - pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ - bias-disable; - }; - }; - - ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 { - pins1 { - pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ - <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ - <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ - <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ - <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ - <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ - }; - }; - - ethernet0_rmii_pins_a: rmii-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ - }; - }; - - ethernet0_rmii_pins_b: rmii-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ - <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ - <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ - <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ - bias-disable; - }; - pins4 { - pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ - }; - }; - - ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ - <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ - <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ - <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ - }; - }; - - ethernet0_rmii_pins_c: rmii-2 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ - }; - }; - - fmc_pins_a: fmc-0 { - pins1 { - pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ - <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ - <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ - <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ - <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ - <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ - <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ - <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ - <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ - <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ - <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ - <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ - <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ - bias-pull-up; - }; - }; - - fmc_sleep_pins_a: fmc-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ - <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ - <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ - <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ - <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ - <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ - <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ - <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ - <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ - <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ - <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ - <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ - <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ - <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ - }; - }; - - fmc_pins_b: fmc-1 { - pins { - pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ - <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ - <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ - <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ - <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ - <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ - <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ - <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ - <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ - <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ - <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ - <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ - <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ - <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ - <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ - <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ - <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ - <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ - <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ - <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ - <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - fmc_sleep_pins_b: fmc-sleep-1 { - pins { - pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ - <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ - <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ - <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ - <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ - <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ - <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ - <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ - <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ - <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ - <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ - <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ - <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ - <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ - <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ - <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ - <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ - <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ - <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ - <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ - <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ - }; - }; - - i2c1_pins_a: i2c1-0 { - pins { - pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ - <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_sleep_pins_a: i2c1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ - <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ - }; - }; - - i2c1_pins_b: i2c1-1 { - pins { - pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ - <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c1_sleep_pins_b: i2c1-sleep-1 { - pins { - pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ - <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ - }; - }; - - i2c2_pins_a: i2c2-0 { - pins { - pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ - <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_sleep_pins_a: i2c2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ - <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ - }; - }; - - i2c2_pins_b1: i2c2-1 { - pins { - pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_sleep_pins_b1: i2c2-sleep-1 { - pins { - pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ - }; - }; - - i2c2_pins_c: i2c2-2 { - pins { - pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ - <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_pins_sleep_c: i2c2-sleep-2 { - pins { - pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ - <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ - }; - }; - - i2c5_pins_a: i2c5-0 { - pins { - pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ - <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_a: i2c5-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ - <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ - - }; - }; - - i2c5_pins_b: i2c5-1 { - pins { - pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ - <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c5_sleep_pins_b: i2c5-sleep-1 { - pins { - pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ - <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ - }; - }; - - i2s2_pins_a: i2s2-0 { - pins { - pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ - <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ - <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - i2s2_sleep_pins_a: i2s2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ - <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ - <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ - }; - }; - - ltdc_pins_a: ltdc-0 { - pins { - pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ - <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ - <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ - <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ - <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ - <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ - <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ - <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ - <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ - <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ - <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ - <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ - <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ - <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ - <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ - <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ - <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ - <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ - <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ - <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ - <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ - <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ - <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ - <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ - <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ - <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ - <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_sleep_pins_a: ltdc-sleep-0 { - pins { - pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ - <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ - <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ - <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ - <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ - <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ - <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ - <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ - <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ - <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ - <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ - <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ - <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ - <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ - <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ - <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ - <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ - <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ - <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ - <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ - <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ - <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ - <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ - <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ - <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ - }; - }; - - ltdc_pins_b: ltdc-1 { - pins { - pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ - <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ - <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ - <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ - <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ - <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ - <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ - <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ - <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ - <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ - <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ - <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ - <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ - <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ - <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ - <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ - <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ - <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ - <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ - <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ - <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ - <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ - <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ - <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ - <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ - <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ - <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_sleep_pins_b: ltdc-sleep-1 { - pins { - pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ - <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ - <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ - <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ - <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ - <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ - <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ - <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ - <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ - <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ - <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ - <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ - <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ - <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ - <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ - <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ - <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ - <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ - <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ - <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ - <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ - <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ - <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ - <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ - <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ - <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ - <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ - }; - }; - - ltdc_pins_c: ltdc-2 { - pins1 { - pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ - <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ - <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ - <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ - <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ - <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ - <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ - <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ - <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ - <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ - <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ - <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ - <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ - <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ - <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ - <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ - <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ - <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ - <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ - <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ - <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - ltdc_sleep_pins_c: ltdc-sleep-2 { - pins1 { - pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ - <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ - <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ - <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ - <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ - <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ - <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ - <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ - <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ - <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ - <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ - <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ - <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ - <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ - <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ - <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ - <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ - <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ - <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ - <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ - <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ - <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ - }; - }; - - ltdc_pins_d: ltdc-3 { - pins1 { - pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - pins2 { - pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ - <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ - <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ - <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ - <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ - <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ - <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ - <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ - <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ - <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ - <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ - <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ - <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ - <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ - <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ - <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ - <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ - <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ - <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ - <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ - <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ - <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ - <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ - <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ - <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ - <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - ltdc_sleep_pins_d: ltdc-sleep-3 { - pins { - pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ - <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ - <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ - <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ - <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ - <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ - <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ - <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ - <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ - <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ - <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ - <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ - <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ - <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ - <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ - <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ - <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ - <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ - <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ - <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ - <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ - <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ - <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ - <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ - <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ - <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ - }; - }; - - mco1_pins_a: mco1-0 { - pins { - pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - mco1_sleep_pins_a: mco1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ - }; - }; - - mco2_pins_a: mco2-0 { - pins { - pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - }; - - mco2_sleep_pins_a: mco2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ - }; - }; - - m_can1_pins_a: m-can1-0 { - pins1 { - pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_a: m_can1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ - <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ - }; - }; - - m_can1_pins_b: m-can1-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_b: m_can1-sleep-1 { - pins { - pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ - <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ - }; - }; - - m_can1_pins_c: m-can1-2 { - pins1 { - pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ - bias-disable; - }; - }; - - m_can1_sleep_pins_c: m_can1-sleep-2 { - pins { - pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ - <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */ - }; - }; - - m_can2_pins_a: m-can2-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ - bias-disable; - }; - }; - - m_can2_sleep_pins_a: m_can2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ - <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ - }; - }; - - pwm1_pins_a: pwm1-0 { - pins { - pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ - <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ - <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_sleep_pins_a: pwm1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ - <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ - <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ - }; - }; - - pwm1_pins_b: pwm1-1 { - pins { - pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_sleep_pins_b: pwm1-sleep-1 { - pins { - pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ - }; - }; - - pwm1_pins_c: pwm1-2 { - pins { - pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */ - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm1_sleep_pins_c: pwm1-sleep-2 { - pins { - pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */ - }; - }; - - pwm2_pins_a: pwm2-0 { - pins { - pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm2_sleep_pins_a: pwm2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ - }; - }; - - pwm3_pins_a: pwm3-0 { - pins { - pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_a: pwm3-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ - }; - }; - - pwm3_pins_b: pwm3-1 { - pins { - pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm3_sleep_pins_b: pwm3-sleep-1 { - pins { - pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ - }; - }; - - pwm4_pins_a: pwm4-0 { - pins { - pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ - <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_a: pwm4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ - <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ - }; - }; - - pwm4_pins_b: pwm4-1 { - pins { - pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm4_sleep_pins_b: pwm4-sleep-1 { - pins { - pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ - }; - }; - - pwm5_pins_a: pwm5-0 { - pins { - pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_sleep_pins_a: pwm5-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ - }; - }; - - pwm5_pins_b: pwm5-1 { - pins { - pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ - <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ - <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm5_sleep_pins_b: pwm5-sleep-1 { - pins { - pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ - <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ - <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ - }; - }; - - pwm8_pins_a: pwm8-0 { - pins { - pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm8_sleep_pins_a: pwm8-sleep-0 { - pins { - pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ - }; - }; - - pwm8_pins_b: pwm8-1 { - pins { - pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */ - <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */ - <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */ - <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */ - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm8_sleep_pins_b: pwm8-sleep-1 { - pins { - pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */ - <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */ - <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */ - <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */ - }; - }; - - pwm12_pins_a: pwm12-0 { - pins { - pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ - bias-pull-down; - drive-push-pull; - slew-rate = <0>; - }; - }; - - pwm12_sleep_pins_a: pwm12-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ - }; - }; - - qspi_clk_pins_a: qspi-clk-0 { - pins { - pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; - - qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ - }; - }; - - qspi_bk1_pins_a: qspi-bk1-0 { - pins { - pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ - <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ - <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ - <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ - <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ - }; - }; - - qspi_bk2_pins_a: qspi-bk2-0 { - pins { - pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ - <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ - <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ - <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ - <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ - }; - }; - - qspi_cs1_pins_a: qspi-cs1-0 { - pins { - pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ - }; - }; - - qspi_cs2_pins_a: qspi-cs2-0 { - pins { - pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; - }; - - qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ - }; - }; - - sai2a_pins_a: sai2a-0 { - pins { - pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ - <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ - <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ - <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_a: sai2a-sleep-0 { - pins { - pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ - <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ - <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ - <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ - }; - }; - - sai2a_pins_b: sai2a-1 { - pins1 { - pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ - <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ - <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_b: sai2a-sleep-1 { - pins { - pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ - <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ - <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ - }; - }; - - sai2a_pins_c: sai2a-2 { - pins { - pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ - <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ - <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai2a_sleep_pins_c: sai2a-sleep-2 { - pins { - pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ - <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ - <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ - }; - }; - - sai2b_pins_a: sai2b-0 { - pins1 { - pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ - <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ - <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_a: sai2b-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ - <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ - <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ - <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ - }; - }; - - sai2b_pins_b: sai2b-1 { - pins { - pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_b: sai2b-sleep-1 { - pins { - pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ - }; - }; - - sai2b_pins_c: sai2b-2 { - pins1 { - pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_c: sai2b-sleep-2 { - pins { - pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ - }; - }; - - sai2b_pins_d: sai2b-3 { - pins1 { - pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */ - <STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */ - <STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ - bias-disable; - }; - }; - - sai2b_sleep_pins_d: sai2b-sleep-3 { - pins1 { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */ - <STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */ - <STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */ - <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ - }; - }; - - sai4a_pins_a: sai4a-0 { - pins { - pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ - slew-rate = <0>; - drive-push-pull; - bias-disable; - }; - }; - - sai4a_sleep_pins_a: sai4a-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ - }; - }; - - sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ - <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_b4_pins_b: sdmmc1-b4-1 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ - <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { - pins1 { - pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ - <STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { - pins { - pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ - <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ - <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */ - <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ - <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ - <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ - }; - }; - - sdmmc1_dir_pins_a: sdmmc1-dir-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ - }; - }; - - sdmmc1_dir_pins_b: sdmmc1-dir-1 { - pins1 { - pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ - bias-pull-up; - }; - }; - - sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { - pins { - pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ - }; - }; - - sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ - <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ - <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ - <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ - }; - }; - - sdmmc2_b4_pins_b: sdmmc2-b4-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ - <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ - <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ - <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ - <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { - pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-disable; - }; - }; - - sdmmc2_d47_pins_a: sdmmc2-d47-0 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ - <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_b: sdmmc2-d47-1 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-disable; - }; - }; - - sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { - pins { - pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_c: sdmmc2-d47-2 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { - pins { - pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_d: sdmmc2-d47-3 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { - pins { - pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ - }; - }; - - sdmmc2_d47_pins_e: sdmmc2-d47-4 { - pins { - pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ - <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { - pins { - pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ - <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ - <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ - <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ - }; - }; - - sdmmc3_b4_pins_a: sdmmc3-b4-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ - <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ - <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ - <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ - <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ - <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ - <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ - <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ - <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ - <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ - <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ - <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ - <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ - }; - }; - - sdmmc3_b4_pins_b: sdmmc3-b4-1 { - pins1 { - pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ - <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ - <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ - <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ - <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - }; - - sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { - pins1 { - pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ - <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ - <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ - <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ - slew-rate = <1>; - drive-push-pull; - bias-pull-up; - }; - pins2 { - pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ - slew-rate = <2>; - drive-push-pull; - bias-pull-up; - }; - pins3 { - pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ - slew-rate = <1>; - drive-open-drain; - bias-pull-up; - }; - }; - - sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { - pins { - pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ - <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ - <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ - <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ - <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ - <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ - }; - }; - - spdifrx_pins_a: spdifrx-0 { - pins { - pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ - bias-disable; - }; - }; - - spdifrx_sleep_pins_a: spdifrx-sleep-0 { - pins { - pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ - }; - }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ - bias-disable; - }; - }; - - spi2_pins_a: spi2-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ - bias-disable; - }; - }; - - spi2_pins_b: spi2-1 { - pins1 { - pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ - bias-disable; - }; - }; - - spi2_pins_c: spi2-2 { - pins1 { - pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ - bias-disable; - drive-push-pull; - }; - - pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ - bias-pull-down; - }; - }; - - spi4_pins_a: spi4-0 { - pins { - pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ - <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ - bias-disable; - }; - }; - - spi5_pins_a: spi5-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */ - <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */ - bias-disable; - }; - }; - - stusb1600_pins_a: stusb1600-0 { - pins { - pinmux = <STM32_PINMUX('I', 11, GPIO)>; - bias-pull-up; - }; - }; - - uart4_pins_a: uart4-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_sleep_pins_a: uart4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ - <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ - }; - }; - - uart4_pins_b: uart4-1 { - pins1 { - pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_pins_c: uart4-2 { - pins1 { - pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_pins_d: uart4-3 { - pins1 { - pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_idle_pins_d: uart4-idle-3 { - pins1 { - pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; - }; - - uart4_sleep_pins_d: uart4-sleep-3 { - pins { - pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ - <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ - }; - }; - - uart5_pins_a: uart5-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */ - bias-disable; - }; - }; - - uart7_pins_a: uart7-0 { - pins1 { - pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ - <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ - <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ - bias-disable; - }; - }; - - uart7_pins_b: uart7-1 { - pins1 { - pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ - bias-disable; - }; - }; - - uart7_pins_c: uart7-2 { - pins1 { - pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ - bias-pull-up; - }; - }; - - uart7_idle_pins_c: uart7-idle-2 { - pins1 { - pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ - bias-pull-up; - }; - }; - - uart7_sleep_pins_c: uart7-sleep-2 { - pins { - pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ - <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ - }; - }; - - uart8_pins_a: uart8-0 { - pins1 { - pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ - bias-disable; - }; - }; - - uart8_rtscts_pins_a: uart8rtscts-0 { - pins { - pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ - <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ - bias-disable; - }; - }; - - usart1_pins_a: usart1-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */ - bias-disable; - }; - }; - - usart1_idle_pins_a: usart1-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */ - <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */ - }; - }; - - usart1_sleep_pins_a: usart1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */ - <STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */ - }; - }; - - usart2_pins_a: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ - <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_b: usart2-1 { - pins1 { - pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ - <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ - <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_b: usart2-sleep-1 { - pins { - pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_c: usart2-2 { - pins1 { - pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ - <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_idle_pins_c: usart2-idle-2 { - pins1 { - pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_sleep_pins_c: usart2-sleep-2 { - pins { - pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-disable; - }; - }; - - usart3_idle_pins_a: usart3-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-disable; - }; - }; - - usart3_sleep_pins_a: usart3-sleep-0 { - pins { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ - }; - }; - - usart3_pins_b: usart3-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ - <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ - bias-pull-up; - }; - }; - - usart3_idle_pins_b: usart3-idle-1 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-pull-up; - }; - }; - - usart3_sleep_pins_b: usart3-sleep-1 { - pins { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ - <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ - <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ - }; - }; - - usart3_pins_c: usart3-2 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ - <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ - bias-pull-up; - }; - }; - - usart3_idle_pins_c: usart3-idle-2 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-pull-up; - }; - }; - - usart3_sleep_pins_c: usart3-sleep-2 { - pins { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ - <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ - <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ - }; - }; - - usart3_pins_d: usart3-3 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ - <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ - bias-disable; - }; - }; - - usart3_idle_pins_d: usart3-idle-3 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ - <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ - bias-disable; - }; - }; - - usart3_sleep_pins_d: usart3-sleep-3 { - pins { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ - <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ - <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ - }; - }; - - usart3_pins_e: usart3-4 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ - <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ - bias-pull-up; - }; - }; - - usart3_idle_pins_e: usart3-idle-4 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ - }; - pins2 { - pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins3 { - pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ - bias-pull-up; - }; - }; - - usart3_sleep_pins_e: usart3-sleep-4 { - pins { - pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ - <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ - <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ - <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ - }; - }; - - usart3_pins_f: usart3-5 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ - <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ - <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ - bias-disable; - }; - }; - - usbotg_hs_pins_a: usbotg-hs-0 { - pins { - pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ - }; - }; - - usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { - pins { - pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ - <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ - }; - }; -}; - -&pinctrl_z { - i2c2_pins_b2: i2c2-0 { - pins { - pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c2_sleep_pins_b2: i2c2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ - }; - }; - - i2c4_pins_a: i2c4-0 { - pins { - pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ - <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c4_sleep_pins_a: i2c4-sleep-0 { - pins { - pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ - <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ - }; - }; - - i2c6_pins_a: i2c6-0 { - pins { - pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ - <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */ - bias-disable; - drive-open-drain; - slew-rate = <0>; - }; - }; - - i2c6_sleep_pins_a: i2c6-sleep-0 { - pins { - pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ - <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */ - }; - }; - - spi1_pins_a: spi1-0 { - pins1 { - pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ - bias-disable; - }; - }; - - spi1_sleep_pins_a: spi1-sleep-0 { - pins { - pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */ - <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */ - <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */ - }; - }; - - usart1_pins_b: usart1-1 { - pins1 { - pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_idle_pins_b: usart1-idle-1 { - pins1 { - pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */ - bias-disable; - }; - }; - - usart1_sleep_pins_b: usart1-sleep-1 { - pins { - pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */ - <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */ - }; - }; -}; diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi deleted file mode 100644 index dc3b09f2f2a..00000000000 --- a/arch/arm/dts/stm32mp15-scmi.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "linaro,scmi-optee"; - #address-cells = <1>; - #size-cells = <0>; - linaro,optee-channel-id = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - - scmi_voltd: protocol@17 { - reg = <0x17>; - - scmi_reguls: regulators { - #address-cells = <1>; - #size-cells = <0>; - - scmi_reg11: regulator@0 { - reg = <0>; - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - scmi_reg18: regulator@1 { - reg = <1>; - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - scmi_usb33: regulator@2 { - reg = <2>; - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - }; -}; - -®11 { - status = "disabled"; -}; - -®18 { - status = "disabled"; -}; - -&usb33 { - status = "disabled"; -}; - -&usbotg_hs { - usb33d-supply = <&scmi_usb33>; -}; - -&usbphyc { - vdda1v1-supply = <&scmi_reg11>; - vdda1v8-supply = <&scmi_reg18>; -}; - -/delete-node/ &clk_hse; -/delete-node/ &clk_hsi; -/delete-node/ &clk_lse; -/delete-node/ &clk_lsi; -/delete-node/ &clk_csi; diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 3f57bd5fe0f..327d7760436 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -106,6 +106,10 @@ operating-points-v2 = <&cpu0_opp_table>; }; +&etzpc { + bootph-all; +}; + &gpioa { bootph-all; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi deleted file mode 100644 index e277140d36b..00000000000 --- a/arch/arm/dts/stm32mp151.dtsi +++ /dev/null @@ -1,1868 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. - */ -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/stm32mp1-clks.h> -#include <dt-bindings/reset/stm32mp1-resets.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - clock-frequency = <650000000>; - device_type = "cpu"; - reg = <0>; - operating-points-v2 = <&cpu0_opp_table>; - nvmem-cells = <&part_number_otp>; - nvmem-cell-names = "part_number"; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - opp-650000000 { - opp-hz = /bits/ 64 <650000000>; - opp-microvolt = <1200000>; - opp-supported-hw = <0x1>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1350000>; - opp-supported-hw = <0x2>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - intc: interrupt-controller@a0021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xa0021000 0x1000>, - <0xa0022000 0x2000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-parent = <&intc>; - }; - - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&dts>; - - trips { - cpu_alert1: cpu-alert1 { - temperature = <85000>; - hysteresis = <0>; - type = "passive"; - }; - - cpu-crit { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - booster: regulator-booster { - compatible = "st,stm32mp1-booster"; - st,syscfg = <&syscfg>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges; - - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timer@40006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40006000 0x400>; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@40007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40007000 0x400>; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@40008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40008000 0x400>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000b000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi3: spi@4000c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000c000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - #sound-dai-cells = <0>; - reg = <0x4000d000 0x400>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; - - usart2: serial@4000e000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000e000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x15>, - <&dmamux1 44 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x15>, - <&dmamux1 46 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x15>, - <&dmamux1 64 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x15>, - <&dmamux1 66 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c1: i2c@40012000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c2: i2c@40013000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c3: i2c@40014000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40014000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@40015000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40015000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - cec: cec@40016000 { - compatible = "st,stm32-cec"; - reg = <0x40016000 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CEC_K>, <&rcc CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - dac: dac@40017000 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40017000 0x400>; - clocks = <&rcc DAC12>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x15>, - <&dmamux1 80 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x15>, - <&dmamux1 82 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x44004000 0x400>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@44005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44005000 0x400>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers15: timer@44006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44006000 0x400>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@44007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44007000 0x400>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@44008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44008000 0x400>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - - spi5: spi@44009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44009000 0x400>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400a000 0x400>; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI1_R>; - status = "disabled"; - - sai1a: audio-controller@4400a004 { - #sound-dai-cells = <0>; - - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; - - sai1b: audio-controller@4400a024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; - }; - }; - - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400b000 0x400>; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI2_R>; - status = "disabled"; - - sai2a: audio-controller@4400b004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; - - sai2b: audio-controller@4400b024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; - }; - }; - - sai3: sai@4400c000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400c000 0x400>; - reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI3_R>; - status = "disabled"; - - sai3a: audio-controller@4400c004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 113 0x400 0x01>; - status = "disabled"; - }; - - sai3b: audio-controller@4400c024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 114 0x400 0x01>; - status = "disabled"; - }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <1>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <2>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 103 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm3: filter@3 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <3>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 104 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm4: filter@4 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <4>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 91 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm5: filter@5 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <5>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmamux1 92 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - #dma-cells = <3>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - dma-channels = <16>; - clocks = <&rcc DMAMUX>; - resets = <&rcc DMAMUX_R>; - }; - - adc: adc@48003000 { - compatible = "st,stm32mp1-adc-core"; - reg = <0x48003000 0x400>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc ADC12>, <&rcc ADC12_K>; - clock-names = "bus", "adc"; - interrupt-controller; - st,syscfg = <&syscfg>; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; - dma-names = "rx"; - nvmem-cells = <&vrefint>; - nvmem-cell-names = "vrefint"; - status = "disabled"; - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - }; - }; - - sdmmc3: mmc@48004000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x48004000 0x400>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC3_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC3_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>, <&usbphyc>; - clock-names = "otg", "utmi"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; - - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = - <&exti 61 1>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "rx", "tx"; - clocks = <&rcc IPCC>; - wakeup-source; - status = "disabled"; - }; - - dcmi: dcmi@4c006000 { - compatible = "st,stm32-dcmi"; - reg = <0x4c006000 0x400>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc CAMITF_R>; - clocks = <&rcc DCMI>; - clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x01>; - dma-names = "tx"; - status = "disabled"; - }; - - rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; - reg = <0x50000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, - <&clk_lse>, <&clk_lsi>; - }; - - pwr_regulators: pwr@50001000 { - compatible = "st,stm32mp1,pwr-reg"; - reg = <0x50001000 0x10>; - - reg11: reg11 { - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - - pwr_mcu: pwr_mcu@50001014 { - compatible = "st,stm32mp151-pwr-mcu", "syscon"; - reg = <0x50001014 0x4>; - }; - - exti: interrupt-controller@5000d000 { - compatible = "st,stm32mp1-exti", "syscon"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000d000 0x400>; - }; - - syscfg: syscon@50020000 { - compatible = "st,stm32mp157-syscfg", "syscon"; - reg = <0x50020000 0x400>; - clocks = <&rcc SYSCFG>; - }; - - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; - - sai4: sai@50027000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50027000 0x400>; - reg = <0x50027000 0x4>, <0x500273f0 0x10>; - interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rcc SAI4_R>; - status = "disabled"; - - sai4a: audio-controller@50027004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 99 0x400 0x01>; - status = "disabled"; - }; - - sai4b: audio-controller@50027024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 100 0x400 0x01>; - status = "disabled"; - }; - }; - - dts: thermal@50028000 { - compatible = "st,stm32-thermal"; - reg = <0x50028000 0x100>; - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc TMPSENS>; - clock-names = "pclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - hash1: hash@54002000 { - compatible = "st,stm32f756-hash"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; - dma-names = "in"; - dma-maxburst = <2>; - status = "disabled"; - }; - - rng1: rng@54003000 { - compatible = "st,stm32-rng"; - reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - - mdma1: dma-controller@58000000 { - compatible = "st,stm32h7-mdma"; - reg = <0x58000000 0x1000>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; - #dma-cells = <5>; - dma-channels = <32>; - dma-requests = <48>; - }; - - fmc: memory-controller@58002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - - nand-controller@4,0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, - <&mdma1 22 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58005000 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x58007000 0x1000>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - crc1: crc@58009000 { - compatible = "st,stm32f7-crc"; - reg = <0x58009000 0x400>; - clocks = <&rcc CRC1>; - status = "disabled"; - }; - - ethernet0: ethernet@5800a000 { - compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "eth-ck", - "ptp_ref", - "ethstp"; - clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHCK_K>, - <&rcc ETHPTP_K>, - <&rcc ETHSTP>; - st,syscon = <&syscfg 0x4>; - snps,mixed-burst; - snps,pbl = <2>; - snps,en-tx-lpi-clockgating; - snps,axi-config = <&stmmac_axi_config_0>; - snps,tso; - status = "disabled"; - - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - }; - - usbh_ohci: usb@5800c000 { - compatible = "generic-ohci"; - reg = <0x5800c000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usbh_ehci: usb@5800d000 { - compatible = "generic-ehci"; - reg = <0x5800d000 0x1000>; - clocks = <&usbphyc>, <&rcc USBH>; - resets = <&rcc USBH_R>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - companion = <&usbh_ohci>; - status = "disabled"; - }; - - ltdc: display-controller@5a001000 { - compatible = "st,stm32-ltdc"; - reg = <0x5a001000 0x400>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LTDC_PX>; - clock-names = "lcd"; - resets = <&rcc LTDC_R>; - status = "disabled"; - }; - - iwdg2: watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - status = "disabled"; - }; - - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - - usart1: serial@5c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x5c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - wakeup-source; - status = "disabled"; - }; - - spi6: spi@5c001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x5c001000 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@5c002000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c002000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - rtc: rtc@5c004000 { - compatible = "st,stm32mp1-rtc"; - reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; - clock-names = "pclk", "rtc_ck"; - interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; - reg = <0x5c005000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - part_number_otp: part-number-otp@4 { - reg = <0x4 0x1>; - }; - vrefint: vrefin-cal@52 { - reg = <0x52 0x2>; - }; - ts_cal1: calib@5c { - reg = <0x5c 0x2>; - }; - ts_cal2: calib@5e { - reg = <0x5e 0x2>; - }; - }; - - i2c6: i2c@5c009000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c009000 0x400>; - interrupt-names = "event", "error"; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x20>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - tamp: tamp@5c00a000 { - compatible = "st,stm32-tamp", "syscon", "simple-mfd"; - reg = <0x5c00a000 0x400>; - }; - - /* - * Break node order to solve dependency probe issue between - * pinctrl and exti. - */ - pinctrl: pinctrl@50002000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-pinctrl"; - ranges = <0 0x50002000 0xa400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioa: gpio@50002000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&rcc GPIOA>; - st,bank-name = "GPIOA"; - status = "disabled"; - }; - - gpiob: gpio@50003000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x1000 0x400>; - clocks = <&rcc GPIOB>; - st,bank-name = "GPIOB"; - status = "disabled"; - }; - - gpioc: gpio@50004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x2000 0x400>; - clocks = <&rcc GPIOC>; - st,bank-name = "GPIOC"; - status = "disabled"; - }; - - gpiod: gpio@50005000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x3000 0x400>; - clocks = <&rcc GPIOD>; - st,bank-name = "GPIOD"; - status = "disabled"; - }; - - gpioe: gpio@50006000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4000 0x400>; - clocks = <&rcc GPIOE>; - st,bank-name = "GPIOE"; - status = "disabled"; - }; - - gpiof: gpio@50007000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x5000 0x400>; - clocks = <&rcc GPIOF>; - st,bank-name = "GPIOF"; - status = "disabled"; - }; - - gpiog: gpio@50008000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x6000 0x400>; - clocks = <&rcc GPIOG>; - st,bank-name = "GPIOG"; - status = "disabled"; - }; - - gpioh: gpio@50009000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x7000 0x400>; - clocks = <&rcc GPIOH>; - st,bank-name = "GPIOH"; - status = "disabled"; - }; - - gpioi: gpio@5000a000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x8000 0x400>; - clocks = <&rcc GPIOI>; - st,bank-name = "GPIOI"; - status = "disabled"; - }; - - gpioj: gpio@5000b000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x9000 0x400>; - clocks = <&rcc GPIOJ>; - st,bank-name = "GPIOJ"; - status = "disabled"; - }; - - gpiok: gpio@5000c000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xa000 0x400>; - clocks = <&rcc GPIOK>; - st,bank-name = "GPIOK"; - status = "disabled"; - }; - }; - - pinctrl_z: pinctrl@54004000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp157-z-pinctrl"; - ranges = <0 0x54004000 0x400>; - interrupt-parent = <&exti>; - st,syscfg = <&exti 0x60 0xff>; - - gpioz: gpio@54004000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x400>; - clocks = <&rcc GPIOZ>; - st,bank-name = "GPIOZ"; - st,bank-ioport = <11>; - status = "disabled"; - }; - }; - }; - - mlahb: ahb { - compatible = "st,mlahb", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - dma-ranges = <0x00000000 0x38000000 0x10000>, - <0x10000000 0x10000000 0x60000>, - <0x30000000 0x30000000 0x60000>; - - m4_rproc: m4@10000000 { - compatible = "st,stm32mp1-m4"; - reg = <0x10000000 0x40000>, - <0x30000000 0x40000>, - <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - reset-names = "mcu_rst"; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; - st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; - st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi deleted file mode 100644 index 486084e0b80..00000000000 --- a/arch/arm/dts/stm32mp153.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#include "stm32mp151.dtsi" - -/ { - cpus { - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - clock-frequency = <650000000>; - device_type = "cpu"; - reg = <1>; - }; - }; - - arm-pmu { - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - timer { - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; - - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi deleted file mode 100644 index 6197d878894..00000000000 --- a/arch/arm/dts/stm32mp157.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#include "stm32mp153.dtsi" - -/ { - soc { - gpu: gpu@59000000 { - compatible = "vivante,gc"; - reg = <0x59000000 0x800>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc GPU>, <&rcc GPU_K>; - clock-names = "bus" ,"core"; - resets = <&rcc GPU_R>; - }; - - dsi: dsi@5a000000 { - compatible = "st,stm32-dsi"; - reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; - clock-names = "pclk", "ref", "px_clk"; - phy-dsi-supply = <®18>; - resets = <&rcc DSI_R>; - reset-names = "apb"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts deleted file mode 100644 index afcd6285890..00000000000 --- a/arch/arm/dts/stm32mp157a-dk1-scmi.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157a-dk1.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; - compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; - - reserved-memory { - optee@de000000 { - reg = <0xde000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts deleted file mode 100644 index 0da3667ab1e..00000000000 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp15xx-dkx.dtsi" - -/ { - model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; - compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts deleted file mode 100644 index 1f75f1d4518..00000000000 --- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-icore-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Engicam i.Core STM32MP1 C.TOUCH 2.0"; - compatible = "engicam,icore-stm32mp1-ctouch2", - "engicam,icore-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts deleted file mode 100644 index f4a49429852..00000000000 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-microgea-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame"; - compatible = "engicam,microgea-stm32mp1-microdev2.0-of7", - "engicam,microgea-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - serial1 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; - default-on; - }; - - lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - power-supply = <&panel_pwr>; - }; - - panel_pwr: regulator-panel-pwr { - compatible = "regulator-fixed"; - regulator-name = "panel_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - panel { - compatible = "auo,b101aw03"; - backlight = <&backlight>; - enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; - power-supply = <&lcd_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - }; -}; - -&i2c2 { - i2c-scl-falling-time-ns = <20>; - i2c-scl-rising-time-ns = <185>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_sleep_pins_a>; - status = "okay"; -}; - -<dc { - pinctrl-names = "default"; - pinctrl-0 = <<dc_pins>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pinctrl { - ltdc_pins: ltdc-0 { - pins { - pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */ - <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */ - <STM32_PINMUX('H', 11, AF14)>, /* LTDC_R5 */ - <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ - <STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */ - <STM32_PINMUX('E', 5, AF14)>, /* LTDC_G0 */ - <STM32_PINMUX('E', 6, AF14)>, /* LTDC_G1 */ - <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ - <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ - <STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */ - <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */ - <STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */ - <STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */ - <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ - <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ - <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ - <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ - <STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */ - <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ - <STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */ - <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ - <STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */ - <STM32_PINMUX('I', 4, AF14)>, /* LTDC_B4 */ - <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ - <STM32_PINMUX('B', 8, AF14)>, /* LTDC_B6 */ - <STM32_PINMUX('I', 7, AF14)>, /* LTDC_B7 */ - <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ - <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ - bias-disable; - drive-push-pull; - slew-rate = <3>; - }; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&vdd>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* J31: RS323 */ -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts deleted file mode 100644 index b9d0d3d6ad1..00000000000 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) - */ - -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp157a-microgea-stm32mp1.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board"; - compatible = "engicam,microgea-stm32mp1-microdev2.0", - "engicam,microgea-stm32mp1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - serial1 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&sdmmc1 { - bus-width = <4>; - disable-wp; - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - st,neg-edge; - vmmc-supply = <&vdd>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* J31: RS323 */ -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi deleted file mode 100644 index 0b85175f151..00000000000 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (c) STMicroelectronics 2019 - All Rights Reserved - * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) - */ - -/ { - compatible = "engicam,microgea-stm32mp1", "st,stm32mp157"; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x10000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - vin: regulator-vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddcore: regulator-vddcore { - compatible = "regulator-fixed"; - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - vin-supply = <&vin>; - }; - - vdd: regulator-vdd { - compatible = "regulator-fixed"; - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vin>; - }; - - vddq_ddr: regulator-vddq-ddr { - compatible = "regulator-fixed"; - regulator-name = "vddq_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vin>; - }; -}; - -&dts { - status = "okay"; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; - - nand-controller@4,0 { - status = "okay"; - - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2{ - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc{ - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&rng1 { - status = "okay"; -}; - -&rtc{ - status = "okay"; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts deleted file mode 100644 index 39358d90200..00000000000 --- a/arch/arm/dts/stm32mp157c-dk2-scmi.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157c-dk2.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; - compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; - - reserved-memory { - optee@de000000 { - reg = <0xde000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cryp1 { - clocks = <&scmi_clk CK_SCMI_CRYP1>; - resets = <&scmi_reset RST_SCMI_CRYP1>; -}; - -&dsi { - phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts deleted file mode 100644 index 510cca5acb7..00000000000 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp15xx-dkx.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; - compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial3 = &usart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cryp1 { - status = "okay"; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - panel@0 { - compatible = "orisetech,otm8009a"; - reg = <0>; - reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; - power-supply = <&v3v3>; - status = "okay"; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_in { - remote-endpoint = <<dc_ep1_out>; -}; - -&dsi_out { - remote-endpoint = <&panel_in>; -}; - -&i2c1 { - touchscreen@38 { - compatible = "focaltech,ft6236"; - reg = <0x38>; - interrupts = <2 2>; - interrupt-parent = <&gpiof>; - interrupt-controller; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - status = "okay"; - }; -}; - -<dc { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep1_out: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&usart2 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart2_pins_c>; - pinctrl-1 = <&usart2_sleep_pins_c>; - pinctrl-2 = <&usart2_idle_pins_c>; - status = "disabled"; -}; diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts deleted file mode 100644 index 07ea765a455..00000000000 --- a/arch/arm/dts/stm32mp157c-ed1-scmi.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157c-ed1.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; - compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; - - reserved-memory { - optee@fe000000 { - reg = <0xfe000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cryp1 { - clocks = <&scmi_clk CK_SCMI_CRYP1>; - resets = <&scmi_reset RST_SCMI_CRYP1>; -}; - -&dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts deleted file mode 100644 index 66ed5f9921b..00000000000 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - model = "STMicroelectronics STM32MP157C eval daughter"; - compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - vin: vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&adc { - /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ - pinctrl-0 = <&adc1_in6_pins_a>; - pinctrl-names = "default"; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "disabled"; - adc1: adc@0 { - status = "okay"; - channel@0 { - reg = <0>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-ns = <400>; - }; - channel@1 { - reg = <1>; - st,min-sample-time-ns = <400>; - }; - channel@6 { - reg = <6>; - st,min-sample-time-ns = <400>; - }; - }; -}; - -&crc1 { - status = "okay"; -}; - -&cryp1 { - status = "okay"; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "disabled"; - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -&hash1 { - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <&vin>; - buck2-supply = <&vin>; - buck3-supply = <&vin>; - buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <&vin>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - vref_ddr-supply = <&vin>; - boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO1 0>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = <IT_CURLIM_LDO2 0>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = <IT_CURLIM_LDO4 0>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = <IT_CURLIM_LDO6 0>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names = "vq0", "vq1", "shutdown", "detach"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&timers6 { - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - timer@5 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbotg_hs { - vbus-supply = <&vbus_otg>; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts deleted file mode 100644 index 813086ec248..00000000000 --- a/arch/arm/dts/stm32mp157c-ev1-scmi.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp157c-ev1.dts" -#include "stm32mp15-scmi.dtsi" - -/ { - model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; - compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", - "st,stm32mp157"; - - reserved-memory { - optee@fe000000 { - reg = <0xfe000000 0x2000000>; - no-map; - }; - }; -}; - -&cpu0 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cpu1 { - clocks = <&scmi_clk CK_SCMI_MPU>; -}; - -&cryp1 { - clocks = <&scmi_clk CK_SCMI_CRYP1>; - resets = <&scmi_reset RST_SCMI_CRYP1>; -}; - -&dsi { - phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; -}; - -&gpioz { - clocks = <&scmi_clk CK_SCMI_GPIOZ>; -}; - -&hash1 { - clocks = <&scmi_clk CK_SCMI_HASH1>; - resets = <&scmi_reset RST_SCMI_HASH1>; -}; - -&i2c4 { - clocks = <&scmi_clk CK_SCMI_I2C4>; - resets = <&scmi_reset RST_SCMI_I2C4>; -}; - -&iwdg2 { - clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; -}; - -&m_can1 { - clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; -}; - -&mdma1 { - resets = <&scmi_reset RST_SCMI_MDMA>; -}; - -&m4_rproc { - /delete-property/ st,syscfg-holdboot; - resets = <&scmi_reset RST_SCMI_MCU>, - <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; -}; - -&rcc { - compatible = "st,stm32mp1-rcc-secure", "syscon"; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_CSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>; -}; - -&rng1 { - clocks = <&scmi_clk CK_SCMI_RNG1>; - resets = <&scmi_reset RST_SCMI_RNG1>; -}; - -&rtc { - clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; -}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts deleted file mode 100644 index cd9c3ff5378..00000000000 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ /dev/null @@ -1,414 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. - */ -/dts-v1/; - -#include "stm32mp157c-ed1.dts" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/media/video-interfaces.h> - -/ { - model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; - compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - - aliases { - serial1 = &usart3; - ethernet0 = ðernet0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - clk_ext_camera: clk-ext-camera { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - }; - - joystick { - compatible = "gpio-keys"; - pinctrl-0 = <&joystick_pins>; - pinctrl-names = "default"; - button-0 { - label = "JoySel"; - linux,code = <KEY_ENTER>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - }; - button-1 { - label = "JoyDown"; - linux,code = <KEY_DOWN>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - }; - button-2 { - label = "JoyLeft"; - linux,code = <KEY_LEFT>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - }; - button-3 { - label = "JoyRight"; - linux,code = <KEY_RIGHT>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; - button-4 { - label = "JoyUp"; - linux,code = <KEY_UP>; - interrupt-parent = <&stmfx_pinctrl>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - }; - }; - - panel_backlight: panel-backlight { - compatible = "gpio-backlight"; - gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; - default-on; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -&dcmi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dcmi_pins_a>; - pinctrl-1 = <&dcmi_sleep_pins_a>; - - port { - dcmi_0: endpoint { - remote-endpoint = <&ov5640_0>; - bus-type = <MEDIA_BUS_TYPE_PARALLEL>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; -}; - -&dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - panel@0 { - compatible = "raydium,rm68200"; - reg = <0>; - reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; - backlight = <&panel_backlight>; - power-supply = <&v3v3>; - status = "okay"; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_in { - remote-endpoint = <<dc_ep0_out>; -}; - -&dsi_out { - remote-endpoint = <&dsi_panel_in>; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_a>; - pinctrl-1 = <&fmc_sleep_pins_a>; - status = "okay"; - - nand-controller@4,0 { - status = "okay"; - - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - AVDD-supply = <&v2v8>; - DOVDD-supply = <&v2v8>; - DVDD-supply = <&v2v8>; - powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; - reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; - rotation = <180>; - status = "okay"; - - port { - ov5640_0: endpoint { - remote-endpoint = <&dcmi_0>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; - - stmfx: stmfx@42 { - compatible = "st,stmfx-0300"; - reg = <0x42>; - interrupts = <8 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpioi>; - vdd-supply = <&v3v3>; - - stmfx_pinctrl: pinctrl { - compatible = "st,stmfx-0300-pinctrl"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&stmfx_pinctrl 0 0 24>; - - joystick_pins: joystick-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; - bias-pull-down; - }; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -<dc { - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a - &qspi_bk2_pins_a - &qspi_cs2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a - &qspi_bk2_sleep_pins_a - &qspi_cs2_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - flash1: flash@1 { - compatible = "jedec,spi-nor"; - reg = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - status = "disabled"; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-1 = <&pwm2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&timers8 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm8_pins_a>; - pinctrl-1 = <&pwm8_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@7 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_b>; - pinctrl-1 = <&usart3_sleep_pins_b>; - pinctrl-2 = <&usart3_idle_pins_b>; - /* - * HW flow control USART3_RTS is optional, and isn't default wired to - * the connector. SB23 needs to be soldered in order to use it, and R77 - * (ETH_CLK) should be removed. - */ - uart-has-rtscts; - status = "disabled"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - /* onboard HUB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - vdd-supply = <&v3v3>; - }; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; - - connector { - compatible = "usb-a-connector"; - vbus-supply = <&vbus_sw>; - }; -}; - -&usbphyc_port1 { - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; -}; diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi deleted file mode 100644 index b06a55a2fa1..00000000000 --- a/arch/arm/dts/stm32mp15xc.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -/ { - soc { - cryp1: cryp@54001000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54001000 0x400>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi deleted file mode 100644 index 511113f2e39..00000000000 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ /dev/null @@ -1,741 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - led { - compatible = "gpio-leds"; - led-blue { - label = "heartbeat"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32MP15-DK"; - routing = - "Playback" , "MCLK", - "Capture" , "MCLK", - "MICL" , "Mic Bias"; - dais = <&sai2a_port &sai2b_port &i2s2_port>; - status = "okay"; - }; - - vin: vin { - compatible = "regulator-fixed"; - regulator-name = "vin"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_usb_cc_pins_a>; - vdd-supply = <&vdd>; - vdda-supply = <&vdd>; - vref-supply = <&vrefbuf>; - status = "okay"; - adc1: adc@0 { - status = "okay"; - /* - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: - * 5 * (56 + 47kOhms) * 5pF => 2.5us. - * Use arbitrary margin here (e.g. 5us). - */ - channel@18 { - reg = <18>; - st,min-sample-time-ns = <5000>; - }; - channel@19 { - reg = <19>; - st,min-sample-time-ns = <5000>; - }; - }; - adc2: adc@100 { - status = "okay"; - /* USB Type-C CC1 & CC2 */ - channel@18 { - reg = <18>; - st,min-sample-time-ns = <5000>; - }; - channel@19 { - reg = <19>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -&cec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_sleep_pins_b>; - status = "okay"; -}; - -&crc1 { - status = "okay"; -}; - -&dts { - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&hash1 { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - hdmi-transmitter@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - iovcc-supply = <&v3v3_hdmi>; - cvcc12-supply = <&v1v2_hdmi>; - reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpiog>; - #sound-dai-cells = <0>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sii9022_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@3 { - reg = <3>; - sii9022_tx_endpoint: endpoint { - remote-endpoint = <&i2s2_endpoint>; - }; - }; - }; - }; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - VL-supply = <&v3v3>; - VD-supply = <&v1v8_audio>; - VA-supply = <&v1v8_audio>; - VAHP-supply = <&v1v8_audio>; - reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>; - clocks = <&sai2a>; - clock-names = "MCLK"; - status = "okay"; - - cs42l51_port: port { - #address-cells = <1>; - #size-cells = <0>; - - cs42l51_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master = <&cs42l51_tx_endpoint>; - bitclock-master = <&cs42l51_tx_endpoint>; - }; - - cs42l51_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master = <&cs42l51_rx_endpoint>; - bitclock-master = <&cs42l51_rx_endpoint>; - }; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - stusb1600@28 { - compatible = "st,stusb1600"; - reg = <0x28>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpioi>; - pinctrl-names = "default"; - pinctrl-0 = <&stusb1600_pins_a>; - status = "okay"; - vdd-supply = <&vin>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - typec-power-opmode = "default"; - - port { - con_usbotg_hs_ep: endpoint { - remote-endpoint = <&usbotg_hs_ep>; - }; - }; - }; - }; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - buck1-supply = <&vin>; - buck2-supply = <&vin>; - buck3-supply = <&vin>; - buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; - ldo2-supply = <&vin>; - ldo3-supply = <&vdd_ddr>; - ldo4-supply = <&vin>; - ldo5-supply = <&vin>; - ldo6-supply = <&v3v3>; - vref_ddr-supply = <&vin>; - boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - interrupts = <IT_CURLIM_LDO1 0>; - }; - - v3v3_hdmi: ldo2 { - regulator-name = "v3v3_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - interrupts = <IT_CURLIM_LDO2 0>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = <IT_CURLIM_LDO4 0>; - }; - - vdda: ldo5 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - regulator-boot-on; - }; - - v1v2_hdmi: ldo6 { - regulator-name = "v1v2_hdmi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - interrupts = <IT_CURLIM_LDO6 0>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_sleep_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - clock-frequency = <400000>; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; -}; - -&i2s2 { - clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "i2sclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_sleep_pins_a>; - status = "okay"; - - i2s2_port: port { - i2s2_endpoint: endpoint { - remote-endpoint = <&sii9022_tx_endpoint>; - dai-format = "i2s"; - mclk-fs = <256>; - }; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_sleep_pins_a>; - status = "okay"; - - port { - ltdc_ep0_out: endpoint { - remote-endpoint = <&sii9022_in>; - }; - }; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names = "vq0", "vq1", "shutdown", "detach"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&cs42l51_tx_endpoint>; - dai-format = "i2s"; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&cs42l51_rx_endpoint>; - dai-format = "i2s"; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - status = "disabled"; -}; - -&timers1 { - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm1_pins_a>; - pinctrl-1 = <&pwm1_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@0 { - status = "okay"; - }; -}; - -&timers3 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm3_pins_a>; - pinctrl-1 = <&pwm3_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@2 { - status = "okay"; - }; -}; - -&timers4 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; - pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@3 { - status = "okay"; - }; -}; - -&timers5 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm5_pins_a>; - pinctrl-1 = <&pwm5_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@4 { - status = "okay"; - }; -}; - -&timers6 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - timer@5 { - status = "okay"; - }; -}; - -&timers12 { - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; - pwm { - pinctrl-0 = <&pwm12_pins_a>; - pinctrl-1 = <&pwm12_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@11 { - status = "okay"; - }; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart7_pins_c>; - pinctrl-1 = <&uart7_sleep_pins_c>; - pinctrl-2 = <&uart7_idle_pins_c>; - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_c>; - pinctrl-1 = <&usart3_sleep_pins_c>; - pinctrl-2 = <&usart3_idle_pins_c>; - uart-has-rtscts; - status = "disabled"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - /* onboard HUB */ - hub@1 { - compatible = "usb424,2514"; - reg = <1>; - vdd-supply = <&v3v3>; - }; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - usb-role-switch; - status = "okay"; - - port { - usbotg_hs_ep: endpoint { - remote-endpoint = <&con_usbotg_hs_ep>; - }; - }; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - st,tune-hs-dc-level = <2>; - st,enable-fs-rftime-tuning; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <15>; - st,trim-hs-impedance = <1>; - st,tune-squelch-level = <3>; - st,tune-hs-rx-offset = <2>; - st,no-lsfs-sc; -}; - -&vrefbuf { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - vdda-supply = <&vdd>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi deleted file mode 100644 index 04f7a43ad66..00000000000 --- a/arch/arm/dts/stm32mp15xxaa-pinctrl.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AA>; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@5000a000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@5000b000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@5000c000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; - }; -}; - -&pinctrl_z { - st,package = <STM32MP_PKG_AA>; - - gpioz: gpio@54004000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; - }; -}; diff --git a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi deleted file mode 100644 index 328dad140e9..00000000000 --- a/arch/arm/dts/stm32mp15xxab-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AB>; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi deleted file mode 100644 index 7eaa245f44d..00000000000 --- a/arch/arm/dts/stm32mp15xxac-pinctrl.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AC>; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 112 16>; - }; - - gpioi: gpio@5000a000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - st,package = <STM32MP_PKG_AC>; - - gpioz: gpio@54004000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl_z 0 400 8>; - }; -}; diff --git a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi deleted file mode 100644 index b63e207de21..00000000000 --- a/arch/arm/dts/stm32mp15xxad-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AD>; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi deleted file mode 100644 index d34a1d5e79c..00000000000 --- a/arch/arm/dts/stm32mp25-pinctrl.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ -#include <dt-bindings/pinctrl/stm32-pinfunc.h> - -&pinctrl { - usart2_pins_a: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_idle_pins_a: usart2-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ - }; - }; -}; diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi deleted file mode 100644 index e2d1c88a57f..00000000000 --- a/arch/arm/dts/stm32mp251.dtsi +++ /dev/null @@ -1,301 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a35"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a35-pmu"; - interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; - interrupt-parent = <&intc>; - }; - - arm_wdt: watchdog { - compatible = "arm,smc-wdt"; - arm,smc-id = <0xb200005a>; - status = "disabled"; - }; - - clocks { - ck_flexgen_08: ck-flexgen-08 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - ck_flexgen_51: ck-flexgen-51 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_ls_mcu: ck-icn-ls-mcu { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi { - compatible = "linaro,scmi-optee"; - #address-cells = <1>; - #size-cells = <0>; - linaro,optee-channel-id = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - intc: interrupt-controller@4ac00000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x0 0x4ac10000 0x0 0x1000>, - <0x0 0x4ac20000 0x0 0x2000>, - <0x0 0x4ac40000 0x0 0x2000>, - <0x0 0x4ac60000 0x0 0x2000>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&intc>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - always-on; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - ranges = <0x0 0x0 0x0 0x80000000>; - - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; - reg = <0x42080000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usart2: serial@400e0000 { - compatible = "st,stm32h7-uart"; - reg = <0x400e0000 0x400>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ck_flexgen_08>; - status = "disabled"; - }; - }; - - bsec: efuse@44000000 { - compatible = "st,stm32mp25-bsec"; - reg = <0x44000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - part_number_otp@24 { - reg = <0x24 0x4>; - }; - - package_otp@1e8 { - reg = <0x1e8 0x1>; - bits = <0 3>; - }; - }; - - syscfg: syscon@44230000 { - compatible = "st,stm32mp25-syscfg", "syscon"; - reg = <0x44230000 0x10000>; - }; - - pinctrl: pinctrl@44240000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp257-pinctrl"; - ranges = <0 0x44240000 0xa0400>; - pins-are-numbered; - - gpioa: gpio@44240000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOA"; - status = "disabled"; - }; - - gpiob: gpio@44250000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x10000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOB"; - status = "disabled"; - }; - - gpioc: gpio@44260000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x20000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOC"; - status = "disabled"; - }; - - gpiod: gpio@44270000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x30000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOD"; - status = "disabled"; - }; - - gpioe: gpio@44280000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x40000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOE"; - status = "disabled"; - }; - - gpiof: gpio@44290000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x50000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOF"; - status = "disabled"; - }; - - gpiog: gpio@442a0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x60000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOG"; - status = "disabled"; - }; - - gpioh: gpio@442b0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x70000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOH"; - status = "disabled"; - }; - - gpioi: gpio@442c0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x80000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOI"; - status = "disabled"; - }; - - gpioj: gpio@442d0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x90000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOJ"; - status = "disabled"; - }; - - gpiok: gpio@442e0000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0xa0000 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOK"; - status = "disabled"; - }; - }; - - pinctrl_z: pinctrl@46200000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32mp257-z-pinctrl"; - ranges = <0 0x46200000 0x400>; - pins-are-numbered; - - gpioz: gpio@46200000 { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0 0x400>; - clocks = <&ck_icn_ls_mcu>; - st,bank-name = "GPIOZ"; - st,bank-ioport = <11>; - status = "disabled"; - }; - - }; - }; -}; diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi deleted file mode 100644 index af48e82efe8..00000000000 --- a/arch/arm/dts/stm32mp253.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ -#include "stm32mp251.dtsi" - -/ { - cpus { - cpu1: cpu@1 { - compatible = "arm,cortex-a35"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - }; - }; - - arm-pmu { - interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; -}; diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi deleted file mode 100644 index e6fa596211f..00000000000 --- a/arch/arm/dts/stm32mp255.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ -#include "stm32mp253.dtsi" - -/ { -}; diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi deleted file mode 100644 index 5c5000d3d9d..00000000000 --- a/arch/arm/dts/stm32mp257.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ -#include "stm32mp255.dtsi" - -/ { -}; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi index a35a9b90388..d778b8d8d05 100644 --- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -5,8 +5,89 @@ #include "stm32mp25-u-boot.dtsi" +/ { + config { + u-boot,boot-led = "led-blue"; + u-boot,mmc-env-partition = "u-boot-env"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; +}; + +&gpioa { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpiob { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpioc { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpiod { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpioe { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpiof { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpiog { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpioh { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpioi { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpioj { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpiok { + clocks = <&ck_icn_ls_mcu>; +}; + +&gpioz { + clocks = <&ck_icn_ls_mcu>; +}; + +&sdmmc1 { + clocks = <&ck_flexgen_51>; + /delete-property/resets; +}; + &usart2 { bootph-all; + clocks = <&ck_flexgen_08>; }; &usart2_pins_a { diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts deleted file mode 100644 index a88494eed34..00000000000 --- a/arch/arm/dts/stm32mp257f-ev1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/dts-v1/; - -#include "stm32mp257.dtsi" -#include "stm32mp25xf.dtsi" -#include "stm32mp25-pinctrl.dtsi" -#include "stm32mp25xxai-pinctrl.dtsi" - -/ { - model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; - compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; - - aliases { - serial0 = &usart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - fw@80000000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x80000000 0x0 0x4000000>; - no-map; - }; - }; -}; - -&arm_wdt { - timeout-sec = <32>; - status = "okay"; -}; - -&usart2 { - pinctrl-names = "default", "idle", "sleep"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_idle_pins_a>; - pinctrl-2 = <&usart2_sleep_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi deleted file mode 100644 index 5e83a692648..00000000000 --- a/arch/arm/dts/stm32mp25xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi deleted file mode 100644 index 5e83a692648..00000000000 --- a/arch/arm/dts/stm32mp25xf.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi deleted file mode 100644 index abdbc7aebc7..00000000000 --- a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AI>; - - gpioa: gpio@44240000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@44250000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@44260000 { - status = "okay"; - ngpios = <14>; - gpio-ranges = <&pinctrl 0 32 14>; - }; - - gpiod: gpio@44270000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@44280000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@44290000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@442a0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@442b0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 2 114 12>; - }; - - gpioi: gpio@442c0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 128 16>; - }; - - gpioj: gpio@442d0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 144 16>; - }; - - gpiok: gpio@442e0000 { - status = "okay"; - ngpios = <8>; - gpio-ranges = <&pinctrl 0 160 8>; - }; -}; - -&pinctrl_z { - gpioz: gpio@46200000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl_z 0 400 10>; - }; -}; diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi deleted file mode 100644 index 2e0d4d349d1..00000000000 --- a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AK>; - - gpioa: gpio@44240000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@44250000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@44260000 { - status = "okay"; - ngpios = <14>; - gpio-ranges = <&pinctrl 0 32 14>; - }; - - gpiod: gpio@44270000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@44280000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@44290000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@442a0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@442b0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 2 114 12>; - }; - - gpioi: gpio@442c0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - gpioz: gpio@46200000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl_z 0 400 10>; - }; -}; diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi deleted file mode 100644 index 2406e972554..00000000000 --- a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. - */ - -&pinctrl { - st,package = <STM32MP_PKG_AL>; - - gpioa: gpio@44240000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@44250000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@44260000 { - status = "okay"; - ngpios = <14>; - gpio-ranges = <&pinctrl 0 32 14>; - }; - - gpiod: gpio@44270000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@44280000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@44290000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@442a0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@442b0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 2 114 12>; - }; - - gpioi: gpio@442c0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - gpioz: gpio@46200000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl_z 0 400 10>; - }; -}; diff --git a/arch/arm/dts/tegra114-asus-tf701t.dts b/arch/arm/dts/tegra114-asus-tf701t.dts new file mode 100644 index 00000000000..2505b9bb726 --- /dev/null +++ b/arch/arm/dts/tegra114-asus-tf701t.dts @@ -0,0 +1,1245 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra114.dtsi" + +/ { + model = "ASUS Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + nvidia,ganged-mode = <&dsib>; + + panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&dvdd_1v8_lcd>; + backlight = <&backlight>; + }; + }; + + dsib: dsi@54400000 { + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wlan-power { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wlan-reset { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wlan-host-wake { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wlan-3v3-com { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-A pinmux */ + uarta-cts { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uarta-rts { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GNSS UART-B pinmux */ + uartb-cts { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb-rts { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Bluetooth UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-shutdown { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-dev-wake { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt-pcm-dap4-out { + nvidia,pins = "dap4_fs_pp4", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-pcm-dap4-in { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-D pinmux */ + uartd-cts { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartd-rts { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* MicroSD pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + microsd-pwr { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* EMMC pinmux */ + sdmmc4-clk-cmd { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + /* SPI pinmux */ + spi1-out { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi1-in { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2 { + nvidia,pins = "ulpi_data4_po5", + "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi4-out { + nvidia,pins = "gmi_ad6_pg6", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi4-in { + nvidia,pins = "gmi_ad5_pg5", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + hall-switch { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lineout-switch { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + power-key { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume-keys { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + nct-irq { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mpu-irq { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi-hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi-en { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* LED pinmux */ + backlight-pwm { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + backlight-en { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Touchscreen pinmux */ + touch-irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + touch-rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-pwr { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-vio { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUDIO pinmux */ + audio-ldo1 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hp-detect { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s0-in { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s0-out { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap-i2s1-in { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s1-out { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap-i2s2-in { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s2-out { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif-in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif-out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AsusEC pinmux */ + ec-irq { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ec-req { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hotplug-i2c { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ps2-irq { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kbd-irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dvfs-pin { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Core pinmux */ + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sys-clk-req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* ULPI pinmux */ + ulpi-data0-6 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi-data1-5 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi-data2-3 { + nvidia,pins = "ulpi_data2_po3", + "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT V */ + pv0-gpio { + nvidia,pins = "pv0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv1-gpio { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT U */ + pu0-gpio { + nvidia,pins = "pu0"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu2-gpio { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PWM pinmux */ + pwm0 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm1 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* EXTPERIPH pinmux */ + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk2-out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk1-req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GMI pinmux */ + gmi-wp-n { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-adv { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad0-ad1 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad2-ad3 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-iordy { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-a18 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-wait { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs6-n { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs7-n { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-dqs-p { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-cs2-ad { + nvidia,pins = "gmi_cs2_n_pk3", + "gmi_ad14_ph6", + "gmi_ad15_ph7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-cs4-clk { + nvidia,pins = "gmi_cs4_n_pk2", + "gmi_clk_lb"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad11 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs1-oe { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad13 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-rst-n { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT CC */ + pcc-gpio { + nvidia,pins = "pcc1", "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT BB */ + pbb3-gpio { + nvidia,pins = "pbb3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb4-5-6-gpio { + nvidia,pins = "pbb4", "pbb5", "pbb6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb7-gpio { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC pinmux */ + kb-r0-c1 { + nvidia,pins = "kb_row0_pr0", + "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-r8-c3 { + nvidia,pins = "kb_row8_ps0", + "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* VI pinmux */ + cam-mclk { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUD pinmux */ + gpio-x4-aud { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-x1-aud { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x3-aud { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x6-aud { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + usb-vbus { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; + }; + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: smps9 { + regulator-name = "vdd_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo2 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + }; + + dvdd_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra114-nvidia-tegratab.dts b/arch/arm/dts/tegra114-nvidia-tegratab.dts new file mode 100644 index 00000000000..f65772a8e01 --- /dev/null +++ b/arch/arm/dts/tegra114-nvidia-tegratab.dts @@ -0,0 +1,1041 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra Note 7"; + compatible = "nvidia,tegratab", "nvidia,tegra114"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + nvidia,180-rotation; + }; + + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + vdd-supply = <&avdd_3v3_lcd>; + vcc-supply = <&dvdd_1v8_lcd>; + + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* ULPI pinmux */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi-data3 { + nvidia,pins = "ulpi_data3_po4", + "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SPI1 pinmux */ + ulpi-clk { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi-dir { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2S pinmux */ + dap1-pins { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap2-dout { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap2-din { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4-din { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4-dout { + nvidia,pins = "dap4_fs_pp4", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC1 pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-wp-n { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-clk-lb { + nvidia,pins = "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* EXTPERIPH pinmux */ + clk1-req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk2-req { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk2-out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3-req-pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dvfs-pinmux { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* HDMI pinmux */ + hdmi-irq { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* UARTA pinmux */ + uarta-out { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uarta-in { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UARTB pinmux */ + uart2-cts-rts { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UARTC pinmux */ + uart3-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UARTD pinmux */ + gmi-a17 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-a18 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartd-out { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT U */ + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu1-2 { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GMI section */ + gmi-wp-n-pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_adv_n_pk0", + "gmi_cs0_n_pj0", + "gmi_wr_n_pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-iordy-pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-wait-pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-clk-pk1 { + nvidia,pins = "gmi_clk_pk1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs2-n-pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-cs4-n-pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad1-pg1 { + nvidia,pins = "gmi_ad1_pg1", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad2-pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_oe_n_pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad8-ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad9 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad12-ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad13-ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad15-ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-dqs-p-pj3 { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-clk-lb { + nvidia,pins = "gmi_clk_lb"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* VI_ALT3 pinmux */ + cam-mclk { + nvidia,pins = "pbb0", "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + port-bb { + nvidia,pins = "pbb3", "pbb4", "pbb5", + "pbb6", "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + port-cc { + nvidia,pins = "pcc1", "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* KBC pinmux */ + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row2-pr2 { + nvidia,pins = "kb_row2_pr2", + "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row3-pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row4-pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row5_pr5", + "kb_row6_pr6", + "kb_col3_pq3", + "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row7-pr7 { + nvidia,pins = "kb_row7_pr7", + "kb_col2_pq2", + "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row8-ps0 { + nvidia,pins = "kb_row8_ps0", + "kb_col1_pq1", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* CORE pinmux */ + sys-clk-req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0", + "gmi_cs1_n_pj2"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUD pinmux */ + gpio-x1-aud-px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x3-aud-px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-x4-aud-px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x5_aud_px5", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-x6-aud-px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-w2-aud-pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-w3-aud-pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + usb-vbus-en { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; + }; + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + avdd_3v3_lcd: smps6 { + regulator-name = "vdd_lcd_hv"; + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + regulator-boot-on; + }; + + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: smps9 { + regulator-name = "vdd_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo2 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + dvdd_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra20-motorola-daytona.dts b/arch/arm/dts/tegra20-motorola-daytona.dts new file mode 100644 index 00000000000..1be8887a332 --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-daytona.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-motorola-mot.dtsi" + +/ { + model = "Motorola Droid X2 (MB870)"; + compatible = "motorola,daytona", "nvidia,tegra20"; +}; diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi new file mode 100644 index 00000000000..f00707c2859 --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> +#include "tegra20.dtsi" + +/ { + chosen { + stdout-path = &uartb; + }; + + aliases { + i2c0 = &gen1_i2c; + + spi0 = &cpcap_spi; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel { + compatible = "motorola,mot-panel"; + + reset-gpios = <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_5v0_panel>; + vddio-supply = <&vdd_1v8_vio>; + + backlight = <&backlight>; + }; + }; + }; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = <TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + output-low; + }; + + usb-mux-hog { + gpio-hog; + gpios = <TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; + output-high; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + crt { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + displaya { + nvidia,pins = "lcsn", "ld0", "ld1", "ld3", + "ld5", "ld6", "ld7", "ld8", + "ld9", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", + "lpp", "lsc0", "lpw1", "lsda", + "lspi"; + nvidia,function = "displaya"; + }; + + gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "gmb", "gmd", "gpu"; + nvidia,function = "gmi"; + }; + + hdmi { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2c1 { + nvidia,pins = "i2cp", "rm"; + nvidia,function = "i2c1"; + }; + + i2c2 { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + kbc { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + osc { + nvidia,pins = "cdev1", "cdev2"; + nvidia,function = "osc"; + }; + + owr { + nvidia,pins = "owc", "uac"; + nvidia,function = "owr"; + }; + + pcie { + nvidia,pins = "gpv"; + nvidia,function = "pcie"; + }; + + pwr-on { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rsvd4 { + nvidia,pins = "lvp0", "lvp1", "lvs", "lsc0", + "ld10", "ld11", "lm1", "ld2", + "ld4", "ldc"; + nvidia,function = "rsvd4"; + }; + + rtck { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + sdio3 { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + + sdio4 { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + spdif { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spi2 { + nvidia,pins = "spia", "spib", "spic", "spig", + "spih"; + nvidia,function = "spi2"; + }; + + spi3 { + nvidia,pins = "lm0", "lpw0", "lpw2", "lsc1"; + nvidia,function = "spi3"; + }; + + uarta { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + + uartc { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + uartd { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + ulpi { + nvidia,pins = "uab"; + nvidia,function = "ulpi"; + }; + + vi { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "dte"; + nvidia,function = "vi"; + }; + + vi-sensor-clk { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + conf-lcsn { + nvidia,pins = "lcsn", "lpw1", "lsck", "lsda", + "lsdi", "ldc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-ata { + nvidia,pins = "ata", "atb", "atc", "ddc", + "gmc", "gpu", "kbca", "kbcb", + "kbcc", "kbcd", "kbce", "kbcf", + "lm1", "lvp0", "owc", "sdb", + "sdc", "sdd", "sdio1", "uaa", + "uad", "uca", "ucb", "pmce", + "lvs"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-cdev1 { + nvidia,pins = "cdev1", "crtp", "csus", "pta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + + conf-atd { + nvidia,pins = "atd", "ate", "cdev2", "dte", + "gma", "gmb", "gmd", "gme", + "gpu7", "gpv", "hdint", "i2cp", + "irrx", "irtx", "pmc", "rm", + "slxa", "slxc", "slxd", "slxk", + "spdi", "spdo", "spid", "spie", + "spif", "uda", "ck32", "ddrc", + "pmca", "pmcb", "pmcc", "pmcd", + "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", + "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", + "lpp", "lpw0", "lpw2", "lsc0", + "lsc1", "lspi", "lvp1"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-dap1 { + nvidia,pins = "dap1", "dap2", "dap3", "dap4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + }; + + conf-dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "dtf"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-spi2 { + nvidia,pins = "spia", "spib", "spic", "spig", + "spih"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + uartb: serial@70006040 { + clocks = <&tegra_car 7>; + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + backlight: led-controller@38 { + compatible = "ti,lm3532"; + reg = <0x38>; + + enable-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight_led: led@0 { + reg = <0>; + + led-sources = <2>; + led-max-microamp = <26600>; + + ti,led-mode = <0>; + ti,linear-mapping-mode; + + label = ":backlight"; + }; + }; + }; + + cpcap_spi: spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + + pmic: cpcap@0 { + compatible = "motorola,cpcap"; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + + spi-cs-high; + spi-max-frequency = <8000000>; + + power_button: button { + compatible = "motorola,cpcap-pwrbutton"; + + interrupt-parent = <&pmic>; + interrupts = <23 IRQ_TYPE_NONE>; + + linux,code = <KEY_ENTER>; + }; + + regulator { + compatible = "motorola,mot-cpcap-regulator"; + + regulators { + /* SW1 is vdd_cpu */ + /* SW2 is vdd_core */ + + vdd_1v8_vio: sw3 { + regulator-name = "vdd_1v8_vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SW4 is vdd_aon (rtc) */ + + vcore_emmc: vsdio { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: vcsi { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: vsimcard { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + avdd_3v3_periph: vusb { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + micro_usb: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&avdd_3v3_periph>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>; + timeout-ms = <500>; + }; + + vdd_5v0_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_disp"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(F, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_usd: regulator-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_usd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(F, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra20-motorola-olympus.dts b/arch/arm/dts/tegra20-motorola-olympus.dts new file mode 100644 index 00000000000..bba5513d6bf --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-olympus.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-motorola-mot.dtsi" + +/ { + model = "Motorola Atrix 4G (MB860)"; + compatible = "motorola,olympus", "nvidia,tegra20"; +}; diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi new file mode 100644 index 00000000000..3cc8ee8b810 --- /dev/null +++ b/arch/arm/dts/zynq-binman-brcp1.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 B&R Industrial Automation GmbH + */ + + #include <config.h> + +/ { + binman { + bootph-all; + filename = "flash.bin"; + pad-byte = <0xff>; + align-size = <16>; + align = <16>; + + blob@0 { + filename = "spl/boot.bin"; + offset = <0x0>; + }; + + fit { + description = "U-Boot BR Zynq boards"; + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + + images { + uboot { + description = "U-Boot BR Zynq"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + u-boot-nodtb { + }; + }; + + fdt-0 { + description = "DTB BR Zynq"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + u-boot-dtb { + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "BR Zynq"; + firmware = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + + blob-ext@0 { + filename = "blobs/cfg.img"; + offset = <0xC0000>; + size = <0x10000>; + optional; + }; + + blob-ext@5 { + filename = "blobs/cfg_opt.img"; + offset = <0xD0000>; + size = <0x10000>; + optional; + }; + + blob-ext@1 { + bootph-all; + filename = "blobs/bitstream.bit"; + offset = <0x100000>; + size = <0x200000>; + optional; + }; + + blob-ext@4 { + bootph-all; + filename = "blobs/bitstream_update.bit"; + offset = <0x400000>; + size = <0x200000>; + optional; + }; + + blob-ext@2 { + filename = "blobs/bootar.itb"; + offset = <0x900000>; + size = <0x600000>; + optional; + }; + + blob-ext@3 { + filename = "blobs/dtb.bin"; + offset = <0xF00000>; + size = <0x100000>; + optional; + }; + }; +}; diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi new file mode 100644 index 00000000000..ebaf42d9419 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP1 CPU"; + compatible = "br,cp1", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; + + pmic0: da9062@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + }; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi new file mode 100644 index 00000000000..1bfd5f27a7e --- /dev/null +++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; + +&rs232_en { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts new file mode 100644 index 00000000000..1b22d3793db --- /dev/null +++ b/arch/arm/dts/zynq-brcp150.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP150 CPU"; + compatible = "br,cp150", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + /* Put this pin active high to enable RS232 debug serial */ + rs232_en: rs232_enable { + compatible = "br,rs232-en"; + pin = <&gpio0 52 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_red { + label = "RDY_F_RED"; + gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user1_green { + label = "USER1_GREEN"; + gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user1_red { + label = "USER1_RED"; + gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user2_green { + label = "USER2_GREEN"; + gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user2_red { + label = "USER2_RED"; + gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <ðernet_phy>; + + ethernet_phy: emio-phy@2 { + reg = <2>; + max-speed = <100>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <16>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; + +/* Since the gem0 clock is configured EMIO this dummy entry is needed */ +&clkc { + clocks = <&clkc 16>; + clock-names = "gem0_emio_clk"; +}; diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi new file mode 100644 index 00000000000..ceea610ec17 --- /dev/null +++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts new file mode 100644 index 00000000000..eee19ce4c5f --- /dev/null +++ b/arch/arm/dts/zynq-brcp170.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP170 CPU"; + compatible = "br,cp170", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_red { + label = "RDY_F_RED"; + gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@58 { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x58>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi new file mode 100644 index 00000000000..58c4558ddff --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts new file mode 100644 index 00000000000..fd7ae5539c3 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi new file mode 120000 index 00000000000..5a31a05ea66 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi @@ -0,0 +1 @@ +zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts new file mode 100644 index 00000000000..a68d530bfe2 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "gmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +/* Since the gem0 clock is configured EMIO this dummy entry is needed */ +&clkc { + clocks = <&clkc 16>; + clock-names = "gem0_emio_clk"; +}; diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi new file mode 120000 index 00000000000..5a31a05ea66 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi @@ -0,0 +1 @@ +zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts new file mode 100644 index 00000000000..353d8a1235c --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_2r.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi new file mode 100644 index 00000000000..58c4558ddff --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts new file mode 100644 index 00000000000..32f873d1b4c --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRSMARC2 CPU"; + compatible = "br,smarc2", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + can0 = &can0; + can1 = &can1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + plk_se_red { + label = "PLK_S_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + + ethernet_phy0: ethernet-phy@1 { + ti,ledcr = <0x0480>; + ti,rgmii-rxclk-shift; + reg = <1>; + }; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy1>; + mac-address = [ 00 00 00 00 00 00 ]; + + ethernet_phy1: ethernet-phy@3{ + ti,ledcr = <0x0480>; + reg = <3>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + resetc: rststm@60 { /* reset controller */ + compatible = "bur,rststm"; + reg = <0x60>; + hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>; + cooling-min-state = <0>; + cooling-max-state = <1>; /* reset gets fired */ + #cooling-cells = <2>; /* min followed by max */ + }; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index 8307a2ef9dd..73eea372079 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -11,6 +11,10 @@ model = "Topic Miami Zynq Board"; compatible = "topic,miami", "xlnx,zynq-7000"; + config { + u-boot,spl-payload-offset = <0x20000>; + }; + aliases { serial0 = &uart0; spi0 = &qspi; @@ -35,6 +39,7 @@ status = "okay"; num-cs = <1>; flash@0 { + bootph-all; compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; reg = <0x0>; @@ -44,24 +49,12 @@ #address-cells = <1>; #size-cells = <1>; partition@0 { - label = "qspi-u-boot-spl"; - reg = <0x00000 0x10000>; - }; - partition@10000 { - label = "qspi-u-boot-img"; - reg = <0x10000 0x60000>; + label = "qspi-boot-bin"; + reg = <0x00000 0x100000>; }; - partition@70000 { - label = "qspi-device-tree"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "qspi-linux"; - reg = <0x80000 0x400000>; - }; - partition@480000 { + partition@100000 { label = "qspi-rootfs"; - reg = <0x480000 0x1b80000>; + reg = <0x100000 0>; }; }; }; @@ -74,6 +67,14 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + /* GPIO expander */ + gpioex: gpio@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-line-names = "USB_RESET", "VTT_SHDWN_N", "V_PRESENT", "DEBUG_PRESENT"; + gpio-controller; + #gpio-cells = <2>; + }; }; &clkc { diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index d5b63ef604b..a70123feead 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -2,13 +2,19 @@ /* * dts file for Xilinx ZynqMP SOMs (k24/k26) * - * (C) Copyright 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2024-2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ #include <config.h> +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) +#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#else +#define U_BOOT_ITB_FILENAME "u-boot.itb" +#endif + /dts-v1/; / { binman: binman { @@ -103,9 +109,9 @@ }; }; - /* u-boot.itb generation in a static way */ + /* Generation in a static way */ itb { - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; pad-byte = <0>; fit { @@ -227,7 +233,7 @@ }; blob-ext@2 { offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; }; fdtmap { }; diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts index 252c2ad552b..59c1388fb1d 100644 --- a/arch/arm/dts/zynqmp-binman.dts +++ b/arch/arm/dts/zynqmp-binman.dts @@ -2,22 +2,28 @@ /* * dts file for Xilinx ZynqMP platforms * - * (C) Copyright 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2024-2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ #include <config.h> +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) +#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#else +#define U_BOOT_ITB_FILENAME "u-boot.itb" +#endif + /dts-v1/; / { binman: binman { multiple-images; #ifdef CONFIG_SPL - /* u-boot.itb generation in a static way */ + /* Generation in a static way */ itb { - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; pad-byte = <0>; fit { @@ -196,7 +202,7 @@ }; blob-ext@2 { offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; }; fdtmap { }; diff --git a/arch/arm/include/asm/arch-apple/rtkit.h b/arch/arm/include/asm/arch-apple/rtkit.h index eff18ddb9d2..4b11e2a72dc 100644 --- a/arch/arm/include/asm/arch-apple/rtkit.h +++ b/arch/arm/include/asm/arch-apple/rtkit.h @@ -12,6 +12,7 @@ struct apple_rtkit_buffer { u64 dva; size_t size; bool is_mapped; + int endpoint; }; typedef int (*apple_rtkit_shmem_setup)(void *cookie, @@ -26,4 +27,8 @@ struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie, apple_rtkit_shmem_destroy shmem_destroy); void apple_rtkit_free(struct apple_rtkit *rtk); int apple_rtkit_boot(struct apple_rtkit *rtk); +int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate); +int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout); int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate); + +int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout); diff --git a/arch/arm/include/asm/arch-rk3528/boot0.h b/arch/arm/include/asm/arch-rk3528/boot0.h new file mode 100644 index 00000000000..8ae46f25a87 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3528/boot0.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3528/gpio.h b/arch/arm/include/asm/arch-rk3528/gpio.h new file mode 100644 index 00000000000..5516e649b80 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3528/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3576/boot0.h b/arch/arm/include/asm/arch-rk3576/boot0.h new file mode 100644 index 00000000000..dea2b20252d --- /dev/null +++ b/arch/arm/include/asm/arch-rk3576/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3576/gpio.h b/arch/arm/include/asm/arch-rk3576/gpio.h new file mode 100644 index 00000000000..b48c0a5cf84 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3576/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 73e5283108b..3c204501f70 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -15,6 +15,13 @@ struct udevice; #define RKCLK_PLL_MODE_NORMAL 1 #define RKCLK_PLL_MODE_DEEP 2 +/* + * PLL flags + */ +#define ROCKCHIP_PLL_SYNC_RATE BIT(0) +/* normal mode only. now only for pll_rk3036, pll_rk3328 type */ +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) + enum { ROCKCHIP_SYSCON_NOC, ROCKCHIP_SYSCON_GRF, @@ -208,6 +215,26 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table, u32 reg_offset, u32 reg_number); /* + * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3528 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* + * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3576 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); +/* * rk3588_reset_bind_lut() - Bind soft reset device as child of clock device * using dedicated RK3588 lookup table * diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h new file mode 100644 index 00000000000..b4020958a04 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h @@ -0,0 +1,388 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3528_H +#define _ASM_ARCH_CRU_RK3528_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define CPU_PVTPLL_HZ (1200 * MHz) +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (996 * MHz) +#define PPLL_HZ (1000 * MHz) + +/* RK3528 pll id */ +enum rk3528_pll_id { + APLL, + CPLL, + GPLL, + PPLL, + DPLL, + PLL_COUNT, +}; + +struct rk3528_clk_priv { + struct rk3528_cru *cru; + unsigned long ppll_hz; + unsigned long gpll_hz; + unsigned long cpll_hz; + unsigned long armclk_hz; + unsigned long armclk_enter_hz; + unsigned long armclk_init_hz; + bool sync_kernel; +}; + +struct rk3528_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000) + +struct rk3528_cru { + unsigned int apll_con[5]; + unsigned int reserved0014[3]; + unsigned int cpll_con[5]; + unsigned int reserved0034[11]; + unsigned int gpll_con[5]; + unsigned int reserved0074[51 + 32]; + unsigned int reserved01c0[48]; + unsigned int mode_con[1]; + unsigned int reserved0284[31]; + unsigned int clksel_con[91]; + unsigned int reserved046c[229]; + unsigned int gate_con[46]; + unsigned int reserved08b8[82]; + unsigned int softrst_con[47]; + unsigned int reserved0abc[81]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved0c14[6]; + unsigned int corewfi_con; + unsigned int reserved0c30[15604]; + + /* pmucru */ + unsigned int reserved10000[192]; + unsigned int pmuclksel_con[3]; + unsigned int reserved1030c[317]; + unsigned int pmugate_con[3]; + unsigned int reserved1080c[125]; + unsigned int pmusoftrst_con[3]; + unsigned int reserved10a08[7550 + 8191]; + + /* pciecru */ + unsigned int reserved20000[32]; + unsigned int ppll_con[5]; + unsigned int reserved20094[155]; + unsigned int pcieclksel_con[2]; + unsigned int reserved20308[318]; + unsigned int pciegate_con; +}; + +check_member(rk3528_cru, pciegate_con, 0x20800); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_PLL_CON(x) ((x) * 0x4) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) + +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 +#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT) +#define RK3528_DIV_PCLK_DBG_SHIFT 1 +#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT) + +enum { + /* CRU_CLKSEL_CON00 */ + CLK_MATRIX_50M_SRC_DIV_SHIFT = 2, + CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT, + CLK_MATRIX_100M_SRC_DIV_SHIFT = 7, + CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON01 */ + CLK_MATRIX_150M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT, + CLK_MATRIX_200M_SRC_DIV_SHIFT = 5, + CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_SEL_SHIFT = 15, + CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT, + + /* CRU_CLKSEL_CON02 */ + CLK_MATRIX_300M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT, + CLK_MATRIX_339M_SRC_DIV_SHIFT = 5, + CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT, + CLK_MATRIX_400M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON03 */ + CLK_MATRIX_500M_SRC_DIV_SHIFT = 6, + CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT, + CLK_MATRIX_500M_SRC_SEL_SHIFT = 11, + CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT, + + /* CRU_CLKSEL_CON04 */ + CLK_MATRIX_600M_SRC_DIV_SHIFT = 0, + CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT, + CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U, + CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U, + CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U, + CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U, + + /* PMUCRU_CLKSEL_CON00 */ + CLK_I2C2_SEL_SHIFT = 0, + CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, + + /* PCIE_CRU_CLKSEL_CON01 */ + PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7, + PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT, + PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11, + PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON32 */ + DCLK_VOP_SRC0_SEL_SHIFT = 10, + DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT, + DCLK_VOP_SRC0_DIV_SHIFT = 2, + DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT, + + /* CRU_CLKSEL_CON33 */ + DCLK_VOP_SRC1_SEL_SHIFT = 8, + DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT, + DCLK_VOP_SRC1_DIV_SHIFT = 0, + DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT, + + /* CRU_CLKSEL_CON43 */ + CLK_CORE_CRYPTO_SEL_SHIFT = 14, + CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, + ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U, + ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT, + + /* CRU_CLKSEL_CON44 */ + CLK_PWM0_SEL_SHIFT = 6, + CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, + CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U, + CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U, + CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U, + CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U, + CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U, + CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U, + CLK_PKA_CRYPTO_SEL_SHIFT = 0, + CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, + CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, + CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, + + /* CRU_CLKSEL_CON60 */ + CLK_MATRIX_25M_SRC_DIV_SHIFT = 2, + CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT, + CLK_MATRIX_125M_SRC_DIV_SHIFT = 10, + CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT, + + /* CRU_CLKSEL_CON61 */ + SCLK_SFC_DIV_SHIFT = 6, + SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT, + SCLK_SFC_SEL_SHIFT = 12, + SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, + SCLK_SFC_SEL_CLK_GPLL_MUX = 0U, + SCLK_SFC_SEL_CLK_CPLL_MUX = 1U, + SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON62 */ + CCLK_SRC_EMMC_DIV_SHIFT = 0, + CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT, + CCLK_SRC_EMMC_SEL_SHIFT = 6, + CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_SHIFT = 8, + BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT, + + /* CRU_CLKSEL_CON63 */ + CLK_I2C3_SEL_SHIFT = 12, + CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, + CLK_I2C5_SEL_SHIFT = 14, + CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 10, + CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, + + /* CRU_CLKSEL_CON64 */ + CLK_I2C6_SEL_SHIFT = 0, + CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT, + + /* CRU_CLKSEL_CON74 */ + CLK_SARADC_DIV_SHIFT = 0, + CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, + CLK_TSADC_DIV_SHIFT = 3, + CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, + CLK_TSADC_TSEN_DIV_SHIFT = 8, + CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, + + /* CRU_CLKSEL_CON79 */ + CLK_I2C1_SEL_SHIFT = 9, + CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, + CLK_I2C0_SEL_SHIFT = 11, + CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, + CLK_SPI0_SEL_SHIFT = 13, + CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, + + /* CRU_CLKSEL_CON83 */ + ACLK_VOP_ROOT_DIV_SHIFT = 12, + ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT, + ACLK_VOP_ROOT_SEL_SHIFT = 15, + ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT, + + /* CRU_CLKSEL_CON84 */ + DCLK_VOP0_SEL_SHIFT = 0, + DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT, + DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U, + DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U, + ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U, + ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U, + DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U, + DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U, + + /* CRU_CLKSEL_CON85 */ + CLK_I2C4_SEL_SHIFT = 13, + CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, + CLK_I2C7_SEL_SHIFT = 0, + CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT, + CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U, + CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U, + CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U, + CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U, + CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U, + CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U, + CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U, + CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U, + CCLK_SRC_SDMMC0_DIV_SHIFT = 0, + CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT, + CCLK_SRC_SDMMC0_SEL_SHIFT = 6, + CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT, + CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U, + CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U, + CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U, + BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U, + BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U, + BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U, + BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U, + CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U, + CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U, + CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON04 */ + CLK_UART0_SRC_DIV_SHIFT = 5, + CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON05 */ + CLK_UART0_FRAC_DIV_SHIFT = 0, + CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON06 */ + SCLK_UART0_SRC_SEL_SHIFT = 0, + SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT, + CLK_UART1_SRC_DIV_SHIFT = 2, + CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON07 */ + CLK_UART1_FRAC_DIV_SHIFT = 0, + CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON08 */ + SCLK_UART1_SRC_SEL_SHIFT = 0, + SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT, + CLK_UART2_SRC_DIV_SHIFT = 2, + CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON09 */ + CLK_UART2_FRAC_DIV_SHIFT = 0, + CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON10 */ + SCLK_UART2_SRC_SEL_SHIFT = 0, + SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT, + CLK_UART3_SRC_DIV_SHIFT = 2, + CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON11 */ + CLK_UART3_FRAC_DIV_SHIFT = 0, + CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON12 */ + SCLK_UART3_SRC_SEL_SHIFT = 0, + SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT, + CLK_UART4_SRC_DIV_SHIFT = 2, + CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON13 */ + CLK_UART4_FRAC_DIV_SHIFT = 0, + CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON14 */ + SCLK_UART4_SRC_SEL_SHIFT = 0, + SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT, + CLK_UART5_SRC_DIV_SHIFT = 2, + CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON15 */ + CLK_UART5_FRAC_DIV_SHIFT = 0, + CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON16 */ + SCLK_UART5_SRC_SEL_SHIFT = 0, + SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT, + CLK_UART6_SRC_DIV_SHIFT = 2, + CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON17 */ + CLK_UART6_FRAC_DIV_SHIFT = 0, + CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON18 */ + SCLK_UART6_SRC_SEL_SHIFT = 0, + SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT, + CLK_UART7_SRC_DIV_SHIFT = 2, + CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT, + /* CRU_CLKSEL_CON19 */ + CLK_UART7_FRAC_DIV_SHIFT = 0, + CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT, + /* CRU_CLKSEL_CON20 */ + SCLK_UART7_SRC_SEL_SHIFT = 0, + SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT, + SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U, + SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U, + SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U, + + /* CRU_CLKSEL_CON60 */ + CLK_GMAC1_VPU_25M_DIV_SHIFT = 2, + CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT, + /* CRU_CLKSEL_CON66 */ + CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0, + CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT, + /* CRU_CLKSEL_CON84 */ + CLK_GMAC0_SRC_DIV_SHIFT = 3, + CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT, +}; + +#endif /* _ASM_ARCH_CRU_RK3528_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h new file mode 100644 index 00000000000..c51750beff2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h @@ -0,0 +1,491 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3576_H +#define _ASM_ARCH_CRU_RK3576_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#define CPU_PVTPLL_HZ (1008 * MHz) +#define LPLL_HZ (816 * MHz) +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (1000 * MHz) +#define PPLL_HZ (1100 * MHz) +#define GMAC0_PTP_REFCLK_IN (24 * MHz) +#define GMAC1_PTP_REFCLK_IN (24 * MHz) + +/* RK3576 pll id */ +enum rk3576_pll_id { + BPLL, + LPLL, + DPLL, + CPLL, + GPLL, + VPLL, + AUPLL, + SPLL, + PPLL, + PLL_COUNT, +}; + +struct rk3576_clk_priv { + struct rk3576_cru *cru; + ulong ppll_hz; + ulong gpll_hz; + ulong cpll_hz; + ulong vpll_hz; + ulong aupll_hz; + ulong spll_hz; + ulong lpll_hz; + ulong bpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rk3576_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int reserved0[3]; +}; + +struct rk3576_cru { + struct rk3576_pll pll[18]; + unsigned int reserved0[16];/* Address Offset: 0x0240 */ + unsigned int mode_con00;/* Address Offset: 0x0280 */ + unsigned int reserved1[31];/* Address Offset: 0x0284 */ + unsigned int clksel_con[181]; /* Address Offset: 0x0300 */ + unsigned int reserved2[139];/* Address Offset: 0x05d4 */ + unsigned int clkgate_con[80];/* Address Offset: 0x0800 */ + unsigned int reserved3[48];/* Address Offset: 0x0938 */ + unsigned int softrst_con[80];/* Address Offset: 0x0400 */ + unsigned int reserved4[48];/* Address Offset: 0x0b38 */ + unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */ + unsigned int glb_rst_st;/* Address Offset: 0x0c04 */ + unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */ + unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */ + unsigned int glb_rst_con;/* Address Offset: 0x0c10 */ + unsigned int reserved5[43];/* Address Offset: 0x0c14 */ + unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */ + unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */ + unsigned int reserved8[32137];/* Address Offset: 0x0c38 */ + unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */ + unsigned int reserved9[298];/* Address Offset: 0x20358 */ + unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */ + unsigned int reserved10[32440];/* Address Offset: 0x20820 */ + unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */ +}; + +check_member(rk3576_cru, mode_con00, 0x280); +check_member(rk3576_cru, pmuclksel_con[1], 0x20304); + +struct pll_rate_table { + unsigned long rate; + unsigned int m; + unsigned int p; + unsigned int s; + unsigned int k; +}; + +#define RK3576_PHP_CRU_BASE 0x8000 +#define RK3576_PMU_CRU_BASE 0x20000 +#define RK3576_BIGCORE_CRU_BASE 0x38000 +#define RK3576_LITCORE_CRU_BASE 0x40000 +#define RK3576_CCI_CRU_BASE 0x48000 +#define RK3576_CRU_BASE 0x27200000 +#define RK3576_SCRU_BASE 0x27214000 + +#define RK3576_BIGCORE_GRF_BASE 0x2600C000 +#define RK3576_LITCORE_GRF_BASE 0x2600E000 +#define RK3576_CCI_GRF_BASE 0x26010000 + +#define RK3576_PLL_CON(x) ((x) * 0x4) +#define RK3576_MODE_CON0 0x280 +#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) +#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) +#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) +#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3576_GLB_CNT_TH 0xc00 +#define RK3576_GLB_SRST_FST 0xc08 +#define RK3576_GLB_SRST_SND 0xc0c +#define RK3576_GLB_RST_CON 0xc10 +#define RK3576_GLB_RST_ST 0xc04 +#define RK3576_SDIO_CON0 0xC24 +#define RK3576_SDIO_CON1 0xC28 +#define RK3576_SDMMC_CON0 0xC30 +#define RK3576_SDMMC_CON1 0xC34 + +#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) +#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) +#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) + +#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) +#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) +#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) +#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) + +#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) +#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) +#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) + +#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) +#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) +#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) +#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) +#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) +#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) +#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) +#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) + +enum { + /* CRU_CLK_SEL8_CON */ + PCLK_TOP_SEL_SHIFT = 7, + PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT, + PCLK_TOP_SEL_100M = 0, + PCLK_TOP_SEL_50M, + PCLK_TOP_SEL_OSC, + + /* CRU_CLK_SEL9_CON */ + ACLK_TOP_SEL_SHIFT = 5, + ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT, + ACLK_TOP_SEL_GPLL = 0, + ACLK_TOP_SEL_CPLL, + ACLK_TOP_SEL_AUPLL, + ACLK_TOP_DIV_SHIFT = 0, + ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT, + + /* CRU_CLK_SEL10_CON */ + ACLK_TOP_MID_SEL_SHIFT = 5, + ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT, + ACLK_TOP_MID_SEL_GPLL = 0, + ACLK_TOP_MID_SEL_CPLL, + ACLK_TOP_MID_DIV_SHIFT = 0, + ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT, + + /* CRU_CLK_SEL19_CON */ + HCLK_TOP_SEL_SHIFT = 2, + HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT, + HCLK_TOP_SEL_200M = 0, + HCLK_TOP_SEL_100M, + HCLK_TOP_SEL_50M, + HCLK_TOP_SEL_OSC, + + /* CRU_CLK_SEL25_CON */ + CLK_UART_FRAC_NUMERATOR_SHIFT = 16, + CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, + CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL26_CON */ + CLK_UART_SRC_SEL_SHIFT = 0, + CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT, + CLK_UART_SRC_SEL_GPLL = 0, + CLK_UART_SRC_SEL_CPLL, + CLK_UART_SRC_SEL_AUPLL, + CLK_UART_SRC_SEL_OSC, + + /* CRU_CLK_SEL27_CON */ + CLK_UART1_SRC_SEL_SHIFT = 13, + CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT, + CLK_UART1_SRC_DIV_SHIFT = 5, + CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL30_CON */ + CLK_GMAC0_125M_DIV_SHIFT = 10, + CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT, + + /* CRU_CLK_SEL31_CON */ + CLK_GMAC1_125M_DIV_SHIFT = 0, + CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT, + + /* CRU_CLK_SEL33_CON */ + REF_CLK0_OUT_PLL_SEL_SHIFT = 8, + REF_CLK0_OUT_PLL_SEL_MASK = 7 << REF_CLK0_OUT_PLL_SEL_SHIFT, + REF_CLK0_OUT_PLL_SEL_GPLL = 0, + REF_CLK0_OUT_PLL_SEL_CPLL, + REF_CLK0_OUT_PLL_SEL_SPLL, + REF_CLK0_OUT_PLL_SEL_AUPLL, + REF_CLK0_OUT_PLL_SEL_LPLL, + REF_CLK0_OUT_PLL_SEL_OSC, + REF_CLK0_OUT_PLL_DIV_SHIFT = 0, + REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, + + /* CRU_CLK_SEL55_CON */ + ACLK_BUS_ROOT_SEL_SHIFT = 9, + ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, + ACLK_BUS_ROOT_SEL_GPLL = 0, + ACLK_BUS_ROOT_SEL_CPLL, + ACLK_BUS_ROOT_DIV_SHIFT = 4, + ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT, + PCLK_BUS_ROOT_SEL_SHIFT = 2, + PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT, + PCLK_BUS_ROOT_SEL_100M = 0, + PCLK_BUS_ROOT_SEL_50M, + PCLK_BUS_ROOT_SEL_OSC, + HCLK_BUS_ROOT_SEL_SHIFT = 0, + HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT, + HCLK_BUS_ROOT_SEL_200M = 0, + HCLK_BUS_ROOT_SEL_100M, + HCLK_BUS_ROOT_SEL_50M, + HCLK_BUS_ROOT_SEL_OSC, + + /* CRU_CLK_SEL57_CON */ + CLK_I2C8_SEL_SHIFT = 14, + CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT, + CLK_I2C7_SEL_SHIFT = 12, + CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT, + CLK_I2C6_SEL_SHIFT = 10, + CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT, + CLK_I2C5_SEL_SHIFT = 8, + CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT, + CLK_I2C4_SEL_SHIFT = 6, + CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT, + CLK_I2C3_SEL_SHIFT = 4, + CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT, + CLK_I2C2_SEL_SHIFT = 2, + CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT, + CLK_I2C1_SEL_SHIFT = 0, + CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT, + CLK_I2C_SEL_200M = 0, + CLK_I2C_SEL_100M, + CLK_I2C_SEL_50M, + CLK_I2C_SEL_OSC, + + /* CRU_CLK_SEL58_CON */ + CLK_SARADC_SEL_SHIFT = 12, + CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT, + CLK_SARADC_SEL_GPLL = 0, + CLK_SARADC_SEL_OSC, + CLK_SARADC_DIV_SHIFT = 4, + CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT, + CLK_I2C9_SEL_SHIFT = 0, + CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT, + + /* CRU_CLK_SEL59_CON */ + CLK_TSADC_DIV_SHIFT = 0, + CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT, + + /* CRU_CLK_SEL60_CON */ + CLK_UART_SEL_SHIFT = 8, + CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT, + CLK_UART_SEL_GPLL = 0, + CLK_UART_SEL_CPLL, + CLK_UART_SEL_AUPLL, + CLK_UART_SEL_OSC, + CLK_UART_SEL_FRAC0, + CLK_UART_SEL_FRAC1, + CLK_UART_SEL_FRAC2, + CLK_UART_DIV_SHIFT = 0, + CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT, + + /* CRU_CLK_SEL70_CON */ + CLK_SPI0_SEL_SHIFT = 13, + CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT, + CLK_SPI_SEL_200M = 0, + CLK_SPI_SEL_100M, + CLK_SPI_SEL_50M, + CLK_SPI_SEL_OSC, + + /* CRU_CLK_SEL71_CON */ + CLK_PWM1_SEL_SHIFT = 8, + CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT, + CLK_SPI4_SEL_SHIFT = 6, + CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT, + CLK_SPI3_SEL_SHIFT = 4, + CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT, + CLK_SPI2_SEL_SHIFT = 2, + CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT, + CLK_SPI1_SEL_SHIFT = 0, + CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT, + CLK_PWM_SEL_100M = 0, + CLK_PWM_SEL_50M, + CLK_PWM_SEL_OSC, + + /* CRU_CLK_SEL72_CON */ + DCLK_DECOM_SEL_SHIFT = 5, + DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, + DCLK_DECOM_SEL_GPLL = 0, + DCLK_DECOM_SEL_SPLL, + DCLK_DECOM_DIV_SHIFT = 0, + DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT, + + /* CRU_CLK_SEL74_CON */ + CLK_PWM2_SEL_SHIFT = 6, + CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT, + + /* CRU_CLK_SEL89_CON */ + CCLK_EMMC_SEL_SHIFT = 14, + CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT, + CCLK_EMMC_SEL_GPLL = 0, + CCLK_EMMC_SEL_CPLL, + CCLK_EMMC_SEL_OSC, + CCLK_EMMC_DIV_SHIFT = 8, + CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT, + SCLK_FSPI_SEL_SHIFT = 6, + SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT, + SCLK_FSPI_SEL_GPLL = 0, + SCLK_FSPI_SEL_CPLL, + SCLK_FSPI_SEL_OSC, + SCLK_FSPI_DIV_SHIFT = 0, + SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT, + + /* CRU_CLK_SEL90_CON */ + BCLK_EMMC_SEL_SHIFT = 0, + BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT, + BCLK_EMMC_SEL_200M = 0, + BCLK_EMMC_SEL_100M, + BCLK_EMMC_SEL_50M, + BCLK_EMMC_SEL_OSC, + + /* CRU_CLK_SEL104_CON */ + CLK_GMAC1_PTP_SEL_SHIFT = 13, + CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT, + CLK_GMAC1_PTP_SEL_GPLL = 0, + CLK_GMAC1_PTP_SEL_CPLL, + CLK_GMAC1_PTP_SEL_REFIN, + CLK_GMAC1_PTP_DIV_SHIFT = 8, + CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT, + CCLK_SDIO_SRC_SEL_SHIFT = 6, + CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT, + CCLK_SDIO_SRC_SEL_GPLL = 0, + CCLK_SDIO_SRC_SEL_CPLL, + CCLK_SDIO_SRC_SEL_OSC, + CCLK_SDIO_SRC_DIV_SHIFT = 0, + CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL105_CON */ + CCLK_SDMMC0_SRC_SEL_SHIFT = 13, + CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT, + CCLK_SDMMC0_SRC_SEL_GPLL = 0, + CCLK_SDMMC0_SRC_SEL_CPLL, + CCLK_SDMMC0_SRC_SEL_OSC, + CCLK_SDMMC0_SRC_DIV_SHIFT = 7, + CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT, + CLK_GMAC0_PTP_SEL_SHIFT = 5, + CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT, + CLK_GMAC0_PTP_SEL_GPLL = 0, + CLK_GMAC0_PTP_SEL_CPLL, + CLK_GMAC0_PTP_SEL_REFIN, + CLK_GMAC0_PTP_DIV_SHIFT = 0, + CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT, + + /* CRU_CLK_SEL123_CON */ + DCLK_EBC_SEL_SHIFT = 12, + DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT, + DCLK_EBC_SEL_GPLL = 0, + DCLK_EBC_SEL_CPLL, + DCLK_EBC_SEL_VPLL, + DCLK_EBC_SEL_AUPLL, + DCLK_EBC_SEL_LPLL, + DCLK_EBC_SEL_FRAC_SRC, + DCLK_EBC_SEL_OSC, + DCLK_EBC_DIV_SHIFT = 3, + DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT, + DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0, + DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT, + DCLK_EBC_FRAC_SRC_SEL_GPLL = 0, + DCLK_EBC_FRAC_SRC_SEL_CPLL, + DCLK_EBC_FRAC_SRC_SEL_VPLL, + DCLK_EBC_FRAC_SRC_SEL_AUPLL, + DCLK_EBC_FRAC_SRC_SEL_OSC, + + /* CRU_CLK_SEL144_CON */ + PCLK_VOP_ROOT_SEL_SHIFT = 12, + PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT, + PCLK_VOP_ROOT_SEL_100M = 0, + PCLK_VOP_ROOT_SEL_50M, + PCLK_VOP_ROOT_SEL_OSC, + HCLK_VOP_ROOT_SEL_SHIFT = 10, + HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT, + HCLK_VOP_ROOT_SEL_200M = 0, + HCLK_VOP_ROOT_SEL_100M, + HCLK_VOP_ROOT_SEL_50M, + HCLK_VOP_ROOT_SEL_OSC, + ACLK_VOP_ROOT_SEL_SHIFT = 5, + ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, + ACLK_VOP_ROOT_SEL_GPLL = 0, + ACLK_VOP_ROOT_SEL_CPLL, + ACLK_VOP_ROOT_SEL_AUPLL, + ACLK_VOP_ROOT_SEL_SPLL, + ACLK_VOP_ROOT_SEL_LPLL, + ACLK_VOP_ROOT_DIV_SHIFT = 0, + ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT, + + /* CRU_CLK_SEL145_CON */ + DCLK0_VOP_SRC_SEL_SHIFT = 8, + DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT, + DCLK_VOP_SRC_SEL_GPLL = 0, + DCLK_VOP_SRC_SEL_CPLL, + DCLK_VOP_SRC_SEL_VPLL, + DCLK_VOP_SRC_SEL_BPLL, + DCLK_VOP_SRC_SEL_LPLL, + DCLK0_VOP_SRC_DIV_SHIFT = 0, + DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT, + + /* CRU_CLK_SEL147_CON */ + DCLK2_VOP_SEL_SHIFT = 13, + DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT, + DCLK1_VOP_SEL_SHIFT = 12, + DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT, + DCLK0_VOP_SEL_SHIFT = 11, + DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT, + + /* CRU_CLK_SEL149_CON */ + ACLK_VO0_ROOT_SEL_SHIFT = 5, + ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT, + ACLK_VO0_ROOT_SEL_GPLL = 0, + ACLK_VO0_ROOT_SEL_CPLL, + ACLK_VO0_ROOT_SEL_LPLL, + ACLK_VO0_ROOT_SEL_BPLL, + ACLK_VO0_ROOT_DIV_SHIFT = 0, + ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT, + + /* CRU_CLK_SEL151_CON */ + CLK_DSIHOST0_SEL_SHIFT = 7, + CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT, + CLK_DSIHOST0_SEL_GPLL = 0, + CLK_DSIHOST0_SEL_CPLL, + CLK_DSIHOST0_SEL_SPLL, + CLK_DSIHOST0_SEL_VPLL, + CLK_DSIHOST0_SEL_BPLL, + CLK_DSIHOST0_SEL_LPLL, + CLK_DSIHOST0_DIV_SHIFT = 0, + CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT, + + /* PMUCRU_CLK_SEL5_CON */ + CLK_PMU1PWM_SEL_SHIFT = 2, + CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT, + + /* PMUCRU_CLK_SEL6_CON */ + CLK_I2C0_SEL_SHIFT = 7, + CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT, + + /* PMUCRU_CLK_SEL8_CON */ + CLK_UART1_SEL_SHIFT = 0, + CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT, + CLK_UART1_SEL_TOP = 0, + CLK_UART1_SEL_OSC, + + /* LITCRU_CLK_SEL0_CON */ + CLK_LITCORE_SEL_SHIFT = 12, + CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT, + CLK_LITCORE_SEL_LPLL = 0, + CLK_LITCORE_SEL_GPLL, + CLK_LITCORE_SEL_PVTPLL, + CLK_LITCORE_DIV_SHIFT = 7, + CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT, + +}; +#endif diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 24c81391d58..d79aea97a40 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -26,11 +26,21 @@ .word 0xe580e004 // str lr, [r0, #4] .word 0xe10fe000 // mrs lr, CPSR .word 0xe580e008 // str lr, [r0, #8] + .word 0xe101e300 // mrs lr, SP_irq + .word 0xe580e014 // str lr, [r0, #20] .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} .word 0xe580e00c // str lr, [r0, #12] .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} .word 0xe580e010 // str lr, [r0, #16] - +#ifdef CONFIG_MACH_SUN55I_A523 + .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5} + .word 0xe31e0001 // tst lr, #1 + .word 0x0a000003 // beq cc <start32+0x48> + .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0} + .word 0xe580e018 // str lr, [r0, #24] + .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} + .word 0xe580e01c // str lr, [r0, #28] +#endif .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 2cec91cb20e..00bdd5f938d 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -10,6 +10,12 @@ #ifndef _SUNXI_CLOCK_SUN4I_H #define _SUNXI_CLOCK_SUN4I_H +#define CCU_AHB_GATE0 0x60 +#define CCU_MMC0_CLK_CFG 0x88 +#define CCU_MMC1_CLK_CFG 0x8c +#define CCU_MMC2_CLK_CFG 0x90 +#define CCU_MMC3_CLK_CFG 0x94 + struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control */ u32 pll1_tun; /* 0x04 pll1 tuning */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 76dd33c9477..ccacc99d018 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -13,218 +13,23 @@ #include <linux/bitops.h> #endif -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ - u8 reserved_0x004[12]; - u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ - u8 reserved_0x014[12]; - u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ - u8 reserved_0x020[4]; - u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ - u8 reserved_0x028[4]; - u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ - u8 reserved_0x034[12]; - u32 pll3_cfg; /* 0x040 pll3 (video0) control */ - u8 reserved_0x044[4]; - u32 pll_video1_cfg; /* 0x048 pll video1 control */ - u8 reserved_0x04c[12]; - u32 pll4_cfg; /* 0x058 pll4 (ve) control */ - u8 reserved_0x05c[4]; - u32 pll10_cfg; /* 0x060 pll10 (de) control */ - u8 reserved_0x064[12]; - u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ - u8 reserved_0x074[4]; - u32 pll2_cfg; /* 0x078 pll2 (audio) control */ - u8 reserved_0x07c[148]; - u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ - u8 reserved_0x114[20]; - u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ - u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ - u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ - u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ - u8 reserved_0x138[8]; - u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ - u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ - u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ - u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ - u8 reserved_0x150[8]; - u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ - u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ - u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ - u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ - u8 reserved_0x168[8]; - u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ - u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ - u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ - u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ - u8 reserved_0x180[384]; - u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ - u8 reserved_0x304[12]; - u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ - u8 reserved_0x314[12]; - u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ - u8 reserved_0x324[4]; - u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ - u8 reserved_0x32c[4]; - u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ - u8 reserved_0x334[12]; - u32 pll3_bias; /* 0x340 pll3 (video0) bias */ - u8 reserved_0x344[4]; - u32 pll_video1_bias; /* 0x348 pll video1 bias */ - u8 reserved_0x34c[12]; - u32 pll4_bias; /* 0x358 pll4 (ve) bias */ - u8 reserved_0x35c[4]; - u32 pll10_bias; /* 0x360 pll10 (de) bias */ - u8 reserved_0x364[12]; - u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ - u8 reserved_0x374[4]; - u32 pll2_bias; /* 0x378 pll2 (audio) bias */ - u8 reserved_0x37c[132]; - u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ - u8 reserved_0x404[252]; - u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ - u8 reserved_0x504[12]; - u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ - u8 reserved_0x514[8]; - u32 ahb3_cfg; /* 0x51c AHB3 clock control */ - u32 apb1_cfg; /* 0x520 APB1 clock control */ - u32 apb2_cfg; /* 0x524 APB2 clock control */ - u8 reserved_0x528[24]; - u32 mbus_cfg; /* 0x540 MBUS clock control */ - u8 reserved_0x544[188]; - u32 de_clk_cfg; /* 0x600 DE clock control */ - u8 reserved_0x604[8]; - u32 de_gate_reset; /* 0x60c DE gate/reset control */ - u8 reserved_0x610[16]; - u32 di_clk_cfg; /* 0x620 DI clock control */ - u8 reserved_0x024[8]; - u32 di_gate_reset; /* 0x62c DI gate/reset control */ - u8 reserved_0x630[64]; - u32 gpu_clk_cfg; /* 0x670 GPU clock control */ - u8 reserved_0x674[8]; - u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ - u32 ce_clk_cfg; /* 0x680 CE clock control */ - u8 reserved_0x684[8]; - u32 ce_gate_reset; /* 0x68c CE gate/reset control */ - u32 ve_clk_cfg; /* 0x690 VE clock control */ - u8 reserved_0x694[8]; - u32 ve_gate_reset; /* 0x69c VE gate/reset control */ - u8 reserved_0x6a0[16]; - u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ - u8 reserved_0x6b4[8]; - u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ - u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ - u8 reserved_0x6c4[8]; - u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ - u8 reserved_0x6d0[60]; - u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ - u8 reserved_0x710[12]; - u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ - u8 reserved_0x720[12]; - u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ - u8 reserved_0x730[12]; - u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ - u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ - u8 reserved_0x744[72]; - u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ - u8 reserved_0x790[12]; - u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ - u8 reserved_0x7a0[12]; - u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ - u8 reserved_0x7b0[12]; - u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ - u8 reserved_0x7c0[64]; - u32 dram_clk_cfg; /* 0x800 DRAM clock control */ - u32 mbus_gate; /* 0x804 MBUS gate control */ - u8 reserved_0x808[4]; - u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ - u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ - u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ - u8 reserved_0x818[20]; - u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ - u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ - u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ - u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ - u8 reserved_0x83c[16]; - u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ - u8 reserved_0x850[188]; - u32 uart_gate_reset; /* 0x90c UART gate/reset control */ - u8 reserved_0x910[12]; - u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ - u8 reserved_0x920[28]; - u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ - u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ - u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ - u8 reserved_0x948[36]; - u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ - u8 reserved_0x970[12]; - u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ - u8 reserved_0x980[48]; - u32 ts_clk_cfg; /* 0x9b0 TS clock control */ - u8 reserved_0x9b4[8]; - u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ - u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ - u8 reserved_0x9c4[8]; - u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ - u8 reserved_0x9d0[44]; - u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ - u8 reserved_0xa00[12]; - u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ - u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ - u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ - u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ - u8 reserved_0xa24[8]; - u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ - u8 reserved_0xa30[16]; - u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ - u8 reserved_0xa44[8]; - u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ - u8 reserved_0xa50[16]; - u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ - u8 reserved_0xa64[8]; - u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ - u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ - u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ - u8 reserved_0xa78[4]; - u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ - u8 reserved_0xa80[12]; - u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ - u8 reserved_0xa90[32]; - u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ - u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ - u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ - u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ - u8 reserved_0xac0[64]; - u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ - u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ - u8 reserved_0xb08[8]; - u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ - u8 reserved_0xb14[8]; - u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ - u8 reserved_0xb20[60]; - u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ - u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ - u8 reserved_0xb64[24]; - u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ - u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ - u8 reserved_0xb84[24]; - u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ - u8 reserved_0xba0[96]; - u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ - u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ - u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ - u8 reserved_0xc0c[32]; - u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ - u8 reserved_0xc30[16]; - u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ - u8 reserved_0xc44[8]; - u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ - u8 reserved_0xc50[688]; - u32 ccu_sec_switch; /* 0xf00 CCU security switch */ - u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ -}; +#define CCU_H6_PLL1_CFG 0x000 +#define CCU_H6_PLL5_CFG 0x010 +#define CCU_H6_PLL6_CFG 0x020 +#define CCU_H6_CPU_AXI_CFG 0x500 +#define CCU_H6_PSI_AHB1_AHB2_CFG 0x510 +#define CCU_H6_AHB3_CFG 0x51c +#define CCU_H6_APB1_CFG 0x520 +#define CCU_H6_APB2_CFG 0x524 +#define CCU_H6_MBUS_CFG 0x540 +#define CCU_H6_DRAM_CLK_CFG 0x800 +#define CCU_H6_DRAM_GATE_RESET 0x80c +#define CCU_MMC0_CLK_CFG 0x830 +#define CCU_MMC1_CLK_CFG 0x834 +#define CCU_MMC2_CLK_CFG 0x838 +#define CCU_H6_MMC_GATE_RESET 0x84c +#define CCU_H6_UART_GATE_RESET 0x90c +#define CCU_H6_I2C_GATE_RESET 0x91c /* pll1 bit field */ #define CCM_PLL1_CTRL_EN BIT(31) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 7fcf340db69..28c3faccbbc 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -10,6 +10,13 @@ #ifndef _SUNXI_CLOCK_SUN6I_H #define _SUNXI_CLOCK_SUN6I_H +#define CCU_AHB_GATE0 0x060 +#define CCU_MMC0_CLK_CFG 0x088 +#define CCU_MMC1_CLK_CFG 0x08c +#define CCU_MMC2_CLK_CFG 0x090 +#define CCU_MMC3_CLK_CFG 0x094 +#define CCU_AHB_RESET0_CFG 0x2c0 + struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control */ u32 reserved0; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 35ca0491ac9..5ad2163926a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -13,6 +13,13 @@ #ifndef _SUNXI_CLOCK_SUN8I_A83T_H #define _SUNXI_CLOCK_SUN8I_A83T_H +#define CCU_AHB_GATE0 0x060 +#define CCU_MMC0_CLK_CFG 0x088 +#define CCU_MMC1_CLK_CFG 0x08c +#define CCU_MMC2_CLK_CFG 0x090 +#define CCU_MMC3_CLK_CFG 0x094 +#define CCU_AHB_RESET0_CFG 0x2c0 + struct sunxi_ccm_reg { u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 006f7761fc6..8d696e533f8 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -12,6 +12,13 @@ #include <linux/bitops.h> #endif +#define CCU_MMC0_CLK_CFG 0x410 +#define CCU_MMC1_CLK_CFG 0x414 +#define CCU_MMC2_CLK_CFG 0x418 +#define CCU_MMC3_CLK_CFG 0x41c +#define CCU_AHB_GATE0 0x580 +#define CCU_AHB_RESET0_CFG 0x5a0 + struct sunxi_ccm_reg { u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h new file mode 100644 index 00000000000..bc9e0d868c5 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Helpers that are commonly used with DW memory controller. + * + * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com> + * + */ + +#ifndef _DRAM_DW_HELPERS_H +#define _DRAM_DW_HELPERS_H + +#include <asm/arch/dram.h> + +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config); +void mctl_auto_detect_rank_width(const struct dram_para *para, + struct dram_config *config); +void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config); +unsigned long mctl_calc_size(const struct dram_config *config); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index f0caecc807d..af6cd337d7e 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -315,12 +315,15 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); struct dram_para { u32 clk; enum sunxi_dram_type type; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + +struct dram_config { u8 cols; u8 rows; u8 ranks; u8 bus_full_width; - const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; static inline int ns_to_t(int nanoseconds) @@ -330,6 +333,6 @@ static inline int ns_to_t(int nanoseconds) return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); } -void mctl_set_timing_params(struct dram_para *para); +void mctl_set_timing_params(void); #endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h index fd63d3aad83..d6653c3bb06 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h +++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h @@ -9,46 +9,12 @@ #define _SUN50I_PRCM_H #ifndef __ASSEMBLY__ -#include <linux/compiler.h> -struct sunxi_prcm_reg { - u32 cpus_cfg; /* 0x000 */ - u8 res0[0x8]; /* 0x004 */ - u32 apbs1_cfg; /* 0x00c */ - u32 apbs2_cfg; /* 0x010 */ - u8 res1[0x108]; /* 0x014 */ - u32 tmr_gate_reset; /* 0x11c */ - u8 res2[0xc]; /* 0x120 */ - u32 twd_gate_reset; /* 0x12c */ - u8 res3[0xc]; /* 0x130 */ - u32 pwm_gate_reset; /* 0x13c */ - u8 res4[0x4c]; /* 0x140 */ - u32 uart_gate_reset; /* 0x18c */ - u8 res5[0xc]; /* 0x190 */ - u32 twi_gate_reset; /* 0x19c */ - u8 res6[0x1c]; /* 0x1a0 */ - u32 rsb_gate_reset; /* 0x1bc */ - u32 cir_cfg; /* 0x1c0 */ - u8 res7[0x8]; /* 0x1c4 */ - u32 cir_gate_reset; /* 0x1cc */ - u8 res8[0x10]; /* 0x1d0 */ - u32 w1_cfg; /* 0x1e0 */ - u8 res9[0x8]; /* 0x1e4 */ - u32 w1_gate_reset; /* 0x1ec */ - u8 res10[0x1c]; /* 0x1f0 */ - u32 rtc_gate_reset; /* 0x20c */ - u8 res11[0x34]; /* 0x210 */ - u32 pll_ldo_cfg; /* 0x244 */ - u8 res12[0x8]; /* 0x248 */ - u32 sys_pwroff_gating; /* 0x250 */ - u8 res13[0xbc]; /* 0x254 */ - u32 res_cal_ctrl; /* 0x310 */ - u32 ohms200; /* 0x314 */ - u32 ohms240; /* 0x318 */ - u32 res_cal_status; /* 0x31c */ -}; -check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c); -check_member(sunxi_prcm_reg, res_cal_status, 0x31c); +#define CCU_PRCM_I2C_GATE_RESET 0x19c +#define CCU_PRCM_PLL_LDO_CFG 0x244 +#define CCU_PRCM_SYS_PWROFF_GATING 0x250 +#define CCU_PRCM_RES_CAL_CTRL 0x310 +#define CCU_PRCM_OHMS240 0x318 #define PRCM_TWI_GATE (1 << 0) #define PRCM_TWI_RESET (1 << 16) diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h index e9e96c1f933..bafcf857620 100644 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ b/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -19,6 +19,7 @@ enum { FUNCMUX_UART1_UAA_UAB, FUNCMUX_UART1_GPU, FUNCMUX_UART1_SDIO1, + FUNCMUX_UART1_SDB_SDD, FUNCMUX_UART2_UAD = 0, FUNCMUX_UART4_GMC = 0, diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 4dbb589aab8..e906fdf1bf1 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -5,8 +5,11 @@ #define MIDR_PARTNUM_CORTEX_A35 0xD04 #define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A55 0xD05 #define MIDR_PARTNUM_CORTEX_A57 0xD07 #define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_CORTEX_A73 0xD09 +#define MIDR_PARTNUM_CORTEX_A75 0xD0A #define MIDR_PARTNUM_CORTEX_A76 0xD0B #define MIDR_PARTNUM_SHIFT 0x4 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) @@ -31,6 +34,9 @@ static inline unsigned int read_midr(void) is_cortex_a(35) is_cortex_a(53) +is_cortex_a(55) is_cortex_a(57) is_cortex_a(72) +is_cortex_a(73) +is_cortex_a(75) is_cortex_a(76) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 849b3d0efb7..4c1b81483c9 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -428,11 +428,21 @@ void switch_to_hypervisor_ret(void); #define wfi() #endif +#if !defined(__thumb2__) +/* + * We will need to switch to ARM mode (.arm) for some instructions such as + * mrc p15 etc. + */ +#define asm_arm_or_thumb2(insn) asm volatile(".arm\n\t" insn) +#else +#define asm_arm_or_thumb2(insn) asm volatile(insn) +#endif + static inline unsigned long read_mpidr(void) { unsigned long val; - asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); + asm_arm_or_thumb2("mrc p15, 0, %0, c0, c0, 5" : "=r" (val)); return val; } @@ -461,11 +471,13 @@ static inline unsigned int get_cr(void) unsigned int val; if (is_hyp()) - asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) + asm_arm_or_thumb2("mrc p15, 4, %0, c1, c0, 0 @ get CR" + : "=r" (val) : : "cc"); else - asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) + asm_arm_or_thumb2("mrc p15, 0, %0, c1, c0, 0 @ get CR" + : "=r" (val) : : "cc"); return val; @@ -474,11 +486,11 @@ static inline unsigned int get_cr(void) static inline void set_cr(unsigned int val) { if (is_hyp()) - asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : + asm_arm_or_thumb2("mcr p15, 4, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); else - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : + asm_arm_or_thumb2("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); isb(); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 74cd5051552..ade42d0ca43 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -97,7 +97,7 @@ endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL ifndef CONFIG_HAS_THUMB2 diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index dd19bd3e4fb..ed6f15cb570 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <asm/cache.h> #include <asm/global_data.h> +#include <asm/system.h> #include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -126,8 +127,8 @@ void invalidate_l2_cache(void) { unsigned int val = 0; - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); + asm_arm_or_thumb2("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); isb(); } #endif diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index 51cc2397768..34f05e94672 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -232,6 +232,9 @@ U_BOOT_DRIVER(arm_gic_v3) = { .id = UCLASS_IRQ, .of_match = gic_v3_ids, .ops = &arm_gic_v3_ops, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif ACPI_OPS_PTR(&gic_v3_acpi_ops) }; diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index d78d704cb58..1f672eee2c8 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -28,13 +28,6 @@ struct Image_header { uint32_t res5; }; -bool booti_is_valid(const void *img) -{ - const struct Image_header *ih = img; - - return ih->magic == le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC); -} - int booti_setup(ulong image, ulong *relocated_addr, ulong *size, bool force_reloc) { @@ -46,7 +39,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, ih = (struct Image_header *)map_sysmem(image, 0); - if (!booti_is_valid(ih)) { + if (ih->magic != le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC)) { puts("Bad Linux ARM64 Image magic!\n"); return 1; } diff --git a/arch/arm/lib/setjmp.S b/arch/arm/lib/setjmp.S index 2f041aeef01..81bef578719 100644 --- a/arch/arm/lib/setjmp.S +++ b/arch/arm/lib/setjmp.S @@ -34,3 +34,15 @@ ENTRY(longjmp) ret lr ENDPROC(longjmp) .popsection + +.pushsection .text.initjmp, "ax" +ENTRY(initjmp) + stm a1, {v1-v8} + /* a2: entry point address, a3: stack base, a4: stack size */ + add a3, a3, a4 + str a3, [a1, #32] /* where setjmp would save sp */ + str a2, [a1, #36] /* where setjmp would save lr */ + mov a1, #0 + ret lr +ENDPROC(initjmp) +.popsection diff --git a/arch/arm/lib/setjmp_aarch64.S b/arch/arm/lib/setjmp_aarch64.S index 1b8d000eb48..01193ccc426 100644 --- a/arch/arm/lib/setjmp_aarch64.S +++ b/arch/arm/lib/setjmp_aarch64.S @@ -39,3 +39,13 @@ ENTRY(longjmp) ret ENDPROC(longjmp) .popsection + +.pushsection .text.initjmp, "ax" +ENTRY(initjmp) + /* x1: entry point address, x2: stack base, x3: stack size */ + add x2, x2, x3 + stp x1, x2, [x0,#88] + mov x0, #0 + ret +ENDPROC(initjmp) +.popsection diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Makefile index 50b465b9473..d79a3a69592 100644 --- a/arch/arm/mach-apple/Makefile +++ b/arch/arm/mach-apple/Makefile @@ -3,4 +3,5 @@ obj-y += board.o obj-y += lowlevel_init.o obj-y += rtkit.o +obj-$(CONFIG_APPLE_MTP_KEYB) += rtkit_helper.o obj-$(CONFIG_NVME_APPLE) += sart.o diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c index b8f4771e5e7..f3561543a35 100644 --- a/arch/arm/mach-apple/rtkit.c +++ b/arch/arm/mach-apple/rtkit.c @@ -11,6 +11,7 @@ #include <linux/apple-mailbox.h> #include <linux/bitfield.h> #include <linux/errno.h> +#include <linux/sizes.h> #include <linux/types.h> #define APPLE_RTKIT_EP_MGMT 0 @@ -18,6 +19,7 @@ #define APPLE_RTKIT_EP_SYSLOG 2 #define APPLE_RTKIT_EP_DEBUG 3 #define APPLE_RTKIT_EP_IOREPORT 4 +#define APPLE_RTKIT_EP_OSLOG 8 #define APPLE_RTKIT_EP_TRACEKIT 10 /* Messages for management endpoint. */ @@ -36,6 +38,7 @@ #define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE 6 #define APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK 7 +#define APPLE_RTKIT_MGMT_SET_AP_PWR_STATE 11 #define APPLE_RTKIT_MGMT_EPMAP 8 #define APPLE_RTKIT_MGMT_EPMAP_LAST BIT(51) @@ -45,6 +48,11 @@ #define APPLE_RTKIT_MGMT_EPMAP_REPLY 8 #define APPLE_RTKIT_MGMT_EPMAP_REPLY_MORE BIT(0) +#define APPLE_RTKIT_OSLOG_TYPE GENMASK_ULL(63, 56) +#define APPLE_RTKIT_OSLOG_BUFFER_REQUEST 1 +#define APPLE_RTKIT_OSLOG_SIZE GENMASK_ULL(55, 36) +#define APPLE_RTKIT_OSLOG_IOVA GENMASK_ULL(35, 0) + #define APPLE_RTKIT_MIN_SUPPORTED_VERSION 11 #define APPLE_RTKIT_MAX_SUPPORTED_VERSION 12 @@ -64,6 +72,10 @@ struct apple_rtkit { struct apple_rtkit_buffer syslog_buffer; struct apple_rtkit_buffer crashlog_buffer; struct apple_rtkit_buffer ioreport_buffer; + struct apple_rtkit_buffer oslog_buffer; + + int iop_pwr; + int ap_pwr; }; struct apple_rtkit *apple_rtkit_init(struct mbox_chan *chan, void *cookie, @@ -93,6 +105,17 @@ void apple_rtkit_free(struct apple_rtkit *rtk) rtk->shmem_destroy(rtk->cookie, &rtk->crashlog_buffer); if (rtk->ioreport_buffer.buffer) rtk->shmem_destroy(rtk->cookie, &rtk->ioreport_buffer); + if (rtk->oslog_buffer.buffer) + rtk->shmem_destroy(rtk->cookie, &rtk->oslog_buffer); + } else { + if (rtk->syslog_buffer.buffer) + free(rtk->syslog_buffer.buffer); + if (rtk->crashlog_buffer.buffer) + free(rtk->crashlog_buffer.buffer); + if (rtk->ioreport_buffer.buffer) + free(rtk->ioreport_buffer.buffer); + if (rtk->oslog_buffer.buffer) + free(rtk->oslog_buffer.buffer); } free(rtk); } @@ -100,16 +123,8 @@ void apple_rtkit_free(struct apple_rtkit *rtk) static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct apple_mbox_msg *msg) { struct apple_rtkit_buffer *buf; - size_t num_4kpages; int ret; - num_4kpages = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0); - - if (num_4kpages == 0) { - printf("%s: unexpected request for buffer without size\n", __func__); - return -1; - } - switch (endpoint) { case APPLE_RTKIT_EP_CRASHLOG: buf = &rtk->crashlog_buffer; @@ -120,14 +135,33 @@ static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct ap case APPLE_RTKIT_EP_IOREPORT: buf = &rtk->ioreport_buffer; break; + case APPLE_RTKIT_EP_OSLOG: + buf = &rtk->oslog_buffer; + break; default: printf("%s: unexpected endpoint %d\n", __func__, endpoint); return -1; } + switch (endpoint) { + case APPLE_RTKIT_EP_OSLOG: + buf->size = FIELD_GET(APPLE_RTKIT_OSLOG_SIZE, msg->msg0); + buf->dva = FIELD_GET(APPLE_RTKIT_OSLOG_IOVA, msg->msg0 << 12); + break; + default: + buf->size = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_SIZE, msg->msg0) << 12; + buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0); + break; + } + + if (buf->size == 0) { + printf("%s: unexpected request for buffer without size\n", __func__); + return -1; + } + buf->dva = FIELD_GET(APPLE_RTKIT_BUFFER_REQUEST_IOVA, msg->msg0); - buf->size = num_4kpages << 12; - buf->is_mapped = false; + buf->is_mapped = !!buf->dva; + buf->endpoint = endpoint; if (rtk->shmem_setup) { ret = rtk->shmem_setup(rtk->cookie, buf); @@ -136,13 +170,27 @@ static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct ap endpoint); return ret; } + } else if (!buf->is_mapped){ + buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K)); + if (!buf->buffer) + return -ENOMEM; + + buf->dva = (u64)buf->buffer; } if (!buf->is_mapped) { - msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_BUFFER_REQUEST) | - FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, num_4kpages) | - FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva); - msg->msg1 = endpoint; + /* oslog uses different fields */ + if (endpoint == APPLE_RTKIT_EP_OSLOG) { + msg->msg0 = FIELD_PREP(APPLE_RTKIT_OSLOG_TYPE, + APPLE_RTKIT_OSLOG_BUFFER_REQUEST); + msg->msg0 |= FIELD_PREP(APPLE_RTKIT_OSLOG_SIZE, buf->size); + msg->msg0 |= FIELD_PREP(APPLE_RTKIT_OSLOG_IOVA, buf->dva >> 12); + } else { + msg->msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, + APPLE_RTKIT_BUFFER_REQUEST); + msg->msg0 |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_SIZE, buf->size >> 12); + msg->msg0 |= FIELD_PREP(APPLE_RTKIT_BUFFER_REQUEST_IOVA, buf->dva); + } return mbox_send(rtk->chan, msg); } @@ -150,6 +198,89 @@ static int rtkit_handle_buf_req(struct apple_rtkit *rtk, int endpoint, struct ap return 0; } +int apple_rtkit_poll(struct apple_rtkit *rtk, ulong timeout) +{ + struct apple_mbox_msg msg; + int ret; + int endpoint; + int msgtype; + + ret = mbox_recv(rtk->chan, &msg, timeout); + if (ret < 0) + return ret; + + endpoint = msg.msg1; + msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); + + if (endpoint == APPLE_RTKIT_EP_CRASHLOG || + endpoint == APPLE_RTKIT_EP_SYSLOG || + endpoint == APPLE_RTKIT_EP_IOREPORT) { + if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) { + ret = rtkit_handle_buf_req(rtk, endpoint, &msg); + if (ret < 0) + return ret; + return 0; + } + } + + if (endpoint == APPLE_RTKIT_EP_OSLOG) { + msgtype = FIELD_GET(APPLE_RTKIT_OSLOG_TYPE, msg.msg0); + + if (msgtype == APPLE_RTKIT_OSLOG_BUFFER_REQUEST) { + ret = rtkit_handle_buf_req(rtk, endpoint, &msg); + if (ret < 0) + return ret; + return 0; + } else { + /* Ignore */ + return 0; + } + } + + if (endpoint == APPLE_RTKIT_EP_IOREPORT) { + // these two messages have to be ack-ed for proper startup + if (msgtype == 0xc || msgtype == 0x8) { + ret = mbox_send(rtk->chan, &msg); + if (ret < 0) + return ret; + return 0; + } + } + + if (endpoint == APPLE_RTKIT_EP_SYSLOG) { + /* Ignore init */ + if (msgtype == 0x8) + return 0; + + /* Ack logs */ + if (msgtype == 0x5) { + ret = mbox_send(rtk->chan, &msg); + if (ret < 0) + return ret; + return 0; + } + } + + if (endpoint != APPLE_RTKIT_EP_MGMT) { + printf("%s: unexpected endpoint %d\n", __func__, endpoint); + return -EINVAL; + } + + switch (msgtype) { + case APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK: + rtk->iop_pwr = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0); + return 0; + case APPLE_RTKIT_MGMT_SET_AP_PWR_STATE: + rtk->ap_pwr = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0); + return 0; + default: + printf("%s: unexpected message type %d\n", __func__, msgtype); + + /* Just ignore it */ + return 0; + } +} + int apple_rtkit_boot(struct apple_rtkit *rtk) { struct apple_mbox_msg msg; @@ -157,7 +288,7 @@ int apple_rtkit_boot(struct apple_rtkit *rtk) int nendpoints = 0; int endpoint; int min_ver, max_ver, want_ver; - int msgtype, pwrstate; + int msgtype; u64 reply; u32 bitmap, base; int i, ret; @@ -276,46 +407,37 @@ wait_epmap: return ret; } - pwrstate = APPLE_RTKIT_PWR_STATE_SLEEP; - while (pwrstate != APPLE_RTKIT_PWR_STATE_ON) { - ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US); + rtk->iop_pwr = APPLE_RTKIT_PWR_STATE_SLEEP; + rtk->ap_pwr = APPLE_RTKIT_PWR_STATE_QUIESCED; + + while (rtk->iop_pwr != APPLE_RTKIT_PWR_STATE_ON) { + ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US); if (ret < 0) return ret; + } - endpoint = msg.msg1; - msgtype = FIELD_GET(APPLE_RTKIT_MGMT_TYPE, msg.msg0); - - if (endpoint == APPLE_RTKIT_EP_CRASHLOG || - endpoint == APPLE_RTKIT_EP_SYSLOG || - endpoint == APPLE_RTKIT_EP_IOREPORT) { - if (msgtype == APPLE_RTKIT_BUFFER_REQUEST) { - ret = rtkit_handle_buf_req(rtk, endpoint, &msg); - if (ret < 0) - return ret; - continue; - } - } + return 0; +} - if (endpoint == APPLE_RTKIT_EP_IOREPORT) { - // these two messages have to be ack-ed for proper startup - if (msgtype == 0xc || msgtype == 0x8) { - ret = mbox_send(rtk->chan, &msg); - if (ret < 0) - return ret; - continue; - } - } +int apple_rtkit_set_ap_power(struct apple_rtkit *rtk, int pwrstate) +{ + struct apple_mbox_msg msg; + int ret; - if (endpoint != APPLE_RTKIT_EP_MGMT) { - printf("%s: unexpected endpoint %d\n", __func__, endpoint); - return -EINVAL; - } - if (msgtype != APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE_ACK) { - printf("%s: unexpected message type %d\n", __func__, msgtype); - return -EINVAL; - } + if (rtk->ap_pwr == pwrstate) + return 0; - pwrstate = FIELD_GET(APPLE_RTKIT_MGMT_PWR_STATE, msg.msg0); + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_AP_PWR_STATE) | + FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate); + msg.msg1 = APPLE_RTKIT_EP_MGMT; + ret = mbox_send(rtk->chan, &msg); + if (ret < 0) + return ret; + + while (rtk->ap_pwr != pwrstate) { + ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US); + if (ret < 0) + return ret; } return 0; @@ -326,6 +448,12 @@ int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate) struct apple_mbox_msg msg; int ret; + if (rtk->ap_pwr != APPLE_RTKIT_PWR_STATE_QUIESCED) { + ret = apple_rtkit_set_ap_power(rtk, APPLE_RTKIT_PWR_STATE_QUIESCED); + if (ret < 0) + return ret; + } + msg.msg0 = FIELD_PREP(APPLE_RTKIT_MGMT_TYPE, APPLE_RTKIT_MGMT_SET_IOP_PWR_STATE) | FIELD_PREP(APPLE_RTKIT_MGMT_PWR_STATE, pwrstate); msg.msg1 = APPLE_RTKIT_EP_MGMT; @@ -333,9 +461,11 @@ int apple_rtkit_shutdown(struct apple_rtkit *rtk, int pwrstate) if (ret < 0) return ret; - ret = mbox_recv(rtk->chan, &msg, TIMEOUT_1SEC_US); - if (ret < 0) - return ret; + while (rtk->iop_pwr != pwrstate) { + ret = apple_rtkit_poll(rtk, TIMEOUT_1SEC_US); + if (ret < 0) + return ret; + } return 0; } diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c new file mode 100644 index 00000000000..b7d60e15700 --- /dev/null +++ b/arch/arm/mach-apple/rtkit_helper.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright The Asahi Linux Contributors + */ + +#include <dm.h> +#include <mailbox.h> +#include <mapmem.h> +#include <reset.h> + +#include <asm/io.h> +#include <asm/arch/rtkit.h> +#include <linux/iopoll.h> + +/* ASC registers */ +#define REG_CPU_CTRL 0x0044 +#define REG_CPU_CTRL_RUN BIT(4) + +#define APPLE_RTKIT_EP_OSLOG 8 + +struct rtkit_helper_priv { + void *asc; /* ASC registers */ + struct mbox_chan chan; + struct apple_rtkit *rtk; + bool sram_stolen; +}; + +static int shmem_setup(void *cookie, struct apple_rtkit_buffer *buf) { + struct udevice *dev = cookie; + struct rtkit_helper_priv *priv = dev_get_priv(dev); + + if (!buf->is_mapped) { + /* + * Special case: The OSLog buffer on MTP persists on Linux handoff. + * Steal some SRAM instead of putting this in DRAM, so we don't + * have to hand off DART/DAPF mappings. + */ + if (buf->endpoint == APPLE_RTKIT_EP_OSLOG) { + if (priv->sram_stolen) { + printf("%s: Tried to map more than one OSLog buffer out of SRAM\n", + __func__); + } else { + fdt_size_t size; + fdt_addr_t addr; + + addr = dev_read_addr_size_name(dev, "sram", &size); + + if (addr != FDT_ADDR_T_NONE) { + buf->dva = ALIGN_DOWN(addr + size - buf->size, SZ_16K); + priv->sram_stolen = true; + + return 0; + } else { + printf("%s: No SRAM, falling back to DRAM\n", __func__); + } + } + } + + buf->buffer = memalign(SZ_16K, ALIGN(buf->size, SZ_16K)); + if (!buf->buffer) + return -ENOMEM; + + buf->dva = (u64)buf->buffer; + } + return 0; +} + +static void shmem_destroy(void *cookie, struct apple_rtkit_buffer *buf) { + if (buf->buffer) + free(buf->buffer); +} + +static int rtkit_helper_probe(struct udevice *dev) +{ + struct rtkit_helper_priv *priv = dev_get_priv(dev); + u32 ctrl; + int ret; + + priv->asc = dev_read_addr_ptr(dev); + if (!priv->asc) + return -EINVAL; + + ret = mbox_get_by_index(dev, 0, &priv->chan); + if (ret < 0) + return ret; + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + priv->rtk = apple_rtkit_init(&priv->chan, dev, shmem_setup, shmem_destroy); + if (!priv->rtk) + return -ENOMEM; + + ret = apple_rtkit_boot(priv->rtk); + if (ret < 0) { + printf("%s: Helper apple_rtkit_boot returned: %d\n", __func__, ret); + return ret; + } + + ret = apple_rtkit_set_ap_power(priv->rtk, APPLE_RTKIT_PWR_STATE_ON); + if (ret < 0) { + printf("%s: Helper apple_rtkit_set_ap_power returned: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int rtkit_helper_remove(struct udevice *dev) +{ + struct rtkit_helper_priv *priv = dev_get_priv(dev); + u32 ctrl; + + apple_rtkit_shutdown(priv->rtk, APPLE_RTKIT_PWR_STATE_QUIESCED); + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + apple_rtkit_free(priv->rtk); + priv->rtk = NULL; + + return 0; +} + +int apple_rtkit_helper_poll(struct udevice *dev, ulong timeout) +{ + struct rtkit_helper_priv *priv = dev_get_priv(dev); + + return apple_rtkit_poll(priv->rtk, timeout); +} + +static const struct udevice_id rtkit_helper_ids[] = { + { .compatible = "apple,rtk-helper-asc4" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(rtkit_helper) = { + .name = "rtkit_helper", + .id = UCLASS_MISC, + .of_match = rtkit_helper_ids, + .priv_auto = sizeof(struct rtkit_helper_priv), + .probe = rtkit_helper_probe, + .remove = rtkit_helper_remove, + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 8f0bc5d997e..62c44b997e4 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -32,7 +32,7 @@ obj-y += lowlevel_init.o endif endif -ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cache.o := -marm diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h index 835b47d91ba..23c71985c90 100644 --- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h +++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h @@ -20,7 +20,7 @@ } #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ - defined(CONFIG_AT91SAM9X5) + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAM9X60) static struct usba_ep_data usba_udc_ep[] = { EP("ep0", 0, 64, 1, 0, 0), EP("ep1", 1, 1024, 2, 1, 1), diff --git a/arch/arm/mach-bcm283x/bcm2711_acpi.c b/arch/arm/mach-bcm283x/bcm2711_acpi.c index 79b283353cf..58f8ee232b9 100644 --- a/arch/arm/mach-bcm283x/bcm2711_acpi.c +++ b/arch/arm/mach-bcm283x/bcm2711_acpi.c @@ -81,7 +81,7 @@ static int acpi_write_pptt(struct acpi_ctx *ctx, const struct acpi_writer *entry } header->length = ctx->current - ctx->tab_start; - header->checksum = table_compute_checksum(header, header->length); + acpi_update_checksum(header); acpi_inc(ctx, header->length); acpi_add_table(ctx, header); @@ -116,7 +116,7 @@ static int rpi_write_gtdt(struct acpi_ctx *ctx, const struct acpi_writer *entry) gtdt->el2_flags = GTDT_FLAG_INT_ACTIVE_LOW; gtdt->cnt_read_base = 0xffffffffffffffff; - header->checksum = table_compute_checksum(header, header->length); + acpi_update_checksum(header); acpi_add_table(ctx, gtdt); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 011cca5d975..8bd85e889ab 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -60,7 +60,7 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif -obj-$(CONFIG_$(XPL_)SATA) += sata.o +obj-$(CONFIG_$(PHASE_)SATA) += sata.o obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 31f2f003d35..74416a78847 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -291,6 +291,12 @@ config TARGET_KONTRON_PITX_IMX8M select IMX8MQ select IMX8M_LPDDR4 +config TARGET_TORADEX_SMARC_IMX8MP + bool "Support Toradex SMARC iMX8M Plus module" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" select IMX8MM @@ -410,6 +416,7 @@ source "board/purism/librem5/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" source "board/technexion/pico-imx8mq/Kconfig" source "board/variscite/imx8mn_var_som/Kconfig" +source "board/toradex/smarc-imx8mp/Kconfig" source "board/toradex/verdin-imx8mm/Kconfig" source "board/toradex/verdin-imx8mp/Kconfig" diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 1f8cb8e3822..1b8c0b1eb96 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -22,6 +22,9 @@ config SOC_K3_AM654 config SOC_K3_J721E bool "TI's K3 based J721E SoC Family Support" +config SOC_K3_J7200 + bool "TI's K3 based J7200 SoC Family Support" + config SOC_K3_J721S2 bool "TI's K3 based J721S2 SoC Family Support" @@ -33,18 +36,13 @@ config SOC_K3_J784S4 endchoice -if SOC_K3_J721E -config SOC_K3_J721E_J7200 - bool "TI's K3 based J7200 SoC variant Family Support" -endif - config SYS_SOC default "k3" config SYS_K3_NON_SECURE_MSRAM_SIZE hex default 0x80000 if SOC_K3_AM654 - default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 + default 0x100000 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4 default 0x1c0000 if SOC_K3_AM642 default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7 help @@ -56,7 +54,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE hex default 0x58000 if SOC_K3_AM654 - default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 + default 0xc0000 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4 default 0x180000 if SOC_K3_AM642 default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7 help @@ -66,21 +64,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE config SYS_K3_MCU_SCRATCHPAD_BASE hex default 0x40280000 if SOC_K3_AM654 - default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 + default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4 help Describes the base address of MCU Scratchpad RAM. config SYS_K3_MCU_SCRATCHPAD_SIZE hex default 0x200 if SOC_K3_AM654 - default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4 + default 0x200 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4 help Describes the size of MCU Scratchpad RAM. config SYS_K3_BOOT_PARAM_TABLE_INDEX hex default 0x41c7fbfc if SOC_K3_AM654 - default 0x41cffbfc if SOC_K3_J721E + default 0x41cffbfc if SOC_K3_J721E || SOC_K3_J7200 default 0x41cfdbfc if SOC_K3_J721S2 || SOC_K3_J784S4 default 0x701bebfc if SOC_K3_AM642 default 0x43c3f290 if SOC_K3_AM625 @@ -193,6 +191,7 @@ source "arch/arm/mach-k3/am62x/Kconfig" source "arch/arm/mach-k3/am62ax/Kconfig" source "arch/arm/mach-k3/am62px/Kconfig" source "arch/arm/mach-k3/j721e/Kconfig" +source "arch/arm/mach-k3/j7200/Kconfig" source "arch/arm/mach-k3/j721s2/Kconfig" source "arch/arm/mach-k3/j722s/Kconfig" source "arch/arm/mach-k3/j784s4/Kconfig" diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 5ce7fc62d80..b2fd5810b67 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM642) += am64x/ obj-$(CONFIG_SOC_K3_AM654) += am65x/ obj-$(CONFIG_SOC_K3_J721E) += j721e/ +obj-$(CONFIG_SOC_K3_J7200) += j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ obj-$(CONFIG_SOC_K3_J722S) += j722s/ obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 698e6d5c587..28aee34f30b 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -194,6 +194,15 @@ void board_init_f(ulong dummy) setup_qos(); + if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && + spl_boot_device() == BOOT_DEVICE_ETHERNET) { + struct udevice *cpswdev; + + if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), + &cpswdev)) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } + debug("am62a_init: %s done\n", __func__); } @@ -207,6 +216,10 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) switch (bootmode) { case BOOT_DEVICE_EMMC: + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; return MMCSD_MODE_EMMCBOOT; case BOOT_DEVICE_MMC: if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 14a46fa28d2..6e3c66e5107 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -262,10 +262,15 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) switch (bootmode) { case BOOT_DEVICE_EMMC: + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; return MMCSD_MODE_EMMCBOOT; case BOOT_DEVICE_MMC: if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK) return MMCSD_MODE_RAW; + fallthrough; default: return MMCSD_MODE_FS; } diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index 595fc391ac5..a422919fab1 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -29,6 +29,12 @@ /* TISCI DEV ID for A53 Clock */ #define AM62X_DEV_A53SS0_CORE_0_DEV_ID 135 +struct fwl_data rom_fwls[] = { + { "SOC_DEVGRP_MAIN", 641, 1 }, + { "SOC_DEVGRP_MAIN", 642, 1 }, + { "SOC_DEVGRP_MAIN", 642, 2 }, +}; + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -177,6 +183,7 @@ void board_init_f(ulong dummy) { struct udevice *dev; int ret; + int i; if (IS_ENABLED(CONFIG_CPU_V7R)) { setup_k3_mpu_regions(); @@ -261,6 +268,11 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + /* Disable firewalls ROM has configured. */ + if (IS_ENABLED(CONFIG_CPU_V7R)) + for (i = 0; i < ARRAY_SIZE(rom_fwls); i++) + remove_fwl_region(&rom_fwls[i]); + if (IS_ENABLED(CONFIG_ESM_K3)) { /* Probe/configure ESM0 */ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 7bd72da1de8..2ec60c7879a 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -35,6 +35,7 @@ enum k3_device_type { void setup_k3_mpu_regions(void); int early_console_init(void); void disable_linefill_optimization(void); +int remove_fwl_region(struct fwl_data *fwl); void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); void k3_sysfw_print_ver(void); diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 361b0c0b31b..867ed173142 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -119,6 +119,9 @@ int fdt_fixup_reserved(void *blob, const char *name, { int nodeoffset, subnode; int ret; + struct fdt_memory carveout = { + .start = new_address, + }; /* Find reserved-memory */ nodeoffset = fdt_subnode_offset(blob, 0, "reserved-memory"); @@ -153,10 +156,7 @@ int fdt_fixup_reserved(void *blob, const char *name, } add_carveout: - struct fdt_memory carveout = { - .start = new_address, - .end = new_address + new_size - 1, - }; + carveout.end = new_address + new_size - 1; ret = fdtdec_add_reserved_memory(blob, name, &carveout, NULL, 0, NULL, FDTDEC_RESERVED_MEMORY_NO_MAP); if (ret < 0) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index b191d53a0f5..fc7bee4d00b 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -32,6 +32,10 @@ #include "j721e_hardware.h" #endif +#ifdef CONFIG_SOC_K3_J7200 +#include "j721e_hardware.h" +#endif + #ifdef CONFIG_SOC_K3_J721S2 #include "j721s2_hardware.h" #endif @@ -62,6 +66,12 @@ #define JTAG_ID_PARTNO_J722S 0xbba0 #define JTAG_ID_PARTNO_J784S4 0xbb80 +#define CTRLMMR_WKUP_JTAG_DEVICE_ID (WKUP_CTRL_MMR0_BASE + 0x18) +#define JTAG_DEV_J742S2_PKG_MASK GENMASK(2, 0) +#define JTAG_DEV_J742S2_PKG_SHIFT 0 + +#define JTAG_ID_PKG_J742S2 0x7 + #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ { \ diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h index 95496e1c59d..39e6725bb9b 100644 --- a/arch/arm/mach-k3/include/mach/k3-ddr.h +++ b/arch/arm/mach-k3/include/mach/k3-ddr.h @@ -6,6 +6,8 @@ #ifndef _K3_DDR_H_ #define _K3_DDR_H_ +#include <spl.h> + int dram_init(void); int dram_init_banksize(void); diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index ac1a34502ed..a47441ae6a5 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -14,6 +14,10 @@ #include "j721e_spl.h" #endif +#ifdef CONFIG_SOC_K3_J7200 +#include "j721e_spl.h" +#endif + #ifdef CONFIG_SOC_K3_J721S2 #include "j721s2_spl.h" #endif diff --git a/arch/arm/mach-k3/j7200/Kconfig b/arch/arm/mach-k3/j7200/Kconfig new file mode 100644 index 00000000000..399daad8767 --- /dev/null +++ b/arch/arm/mach-k3/j7200/Kconfig @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +if SOC_K3_J7200 + +choice + prompt "K3 J7200 based boards" + optional + +config TARGET_J7200_A72_EVM + bool "TI K3 based J7200 EVM running on A72" + select ARM64 + select BOARD_LATE_INIT + imply TI_I2C_BOARD_DETECT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J7200_R5_EVM + bool "TI K3 based J7200 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +source "board/ti/j7200/Kconfig" + +endif diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile new file mode 100644 index 00000000000..6d3ff36e363 --- /dev/null +++ b/arch/arm/mach-k3/j7200/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis <afd@ti.com> + +obj-$(CONFIG_OF_SYSTEM_SETUP) += ../j721e/j721e_fdt.o +obj-$(CONFIG_XPL_BUILD) += ../j721e/j721e_init.o diff --git a/arch/arm/mach-k3/j721e/Kconfig b/arch/arm/mach-k3/j721e/Kconfig index 0761b82b15a..4d01f2c8af2 100644 --- a/arch/arm/mach-k3/j721e/Kconfig +++ b/arch/arm/mach-k3/j721e/Kconfig @@ -29,27 +29,6 @@ config TARGET_J721E_R5_EVM imply SYS_K3_SPL_ATF imply TI_I2C_BOARD_DETECT -config TARGET_J7200_A72_EVM - bool "TI K3 based J7200 EVM running on A72" - select ARM64 - select SOC_K3_J721E_J7200 - select BOARD_LATE_INIT - imply TI_I2C_BOARD_DETECT - select SYS_DISABLE_DCACHE_OPS - select BINMAN - -config TARGET_J7200_R5_EVM - bool "TI K3 based J7200 EVM running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF - imply TI_I2C_BOARD_DETECT - endchoice source "board/beagle/beagleboneai64/Kconfig" diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index 7e2d2c16b45..f31c20f7ed6 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -48,7 +48,7 @@ #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { -#if defined(CONFIG_TARGET_J721E_R5_EVM) +#if defined(CONFIG_SOC_K3_J721E) { "PCIE0_CFG", 2560, 8 }, { "PCIE1_CFG", 2561, 8 }, { "USB3SS0_CORE", 2568, 4 }, @@ -57,11 +57,11 @@ struct fwl_data cbass_hc_cfg0_fwls[] = { { "UFS_HCI0_CFG", 2580, 4 }, { "SERDES0", 2584, 1 }, { "SERDES1", 2585, 1 }, -#elif defined(CONFIG_TARGET_J7200_R5_EVM) +#elif defined(CONFIG_SOC_K3_J7200) { "PCIE1_CFG", 2561, 7 }, #endif }, cbass_hc0_fwls[] = { -#if defined(CONFIG_TARGET_J721E_R5_EVM) +#if defined(CONFIG_SOC_K3_J721E) { "PCIE0_HP", 2528, 24 }, { "PCIE0_LP", 2529, 24 }, { "PCIE1_HP", 2530, 24 }, diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig index 1eadfb346a3..84194f6efa8 100644 --- a/arch/arm/mach-k3/j784s4/Kconfig +++ b/arch/arm/mach-k3/j784s4/Kconfig @@ -27,6 +27,24 @@ config TARGET_J784S4_R5_EVM select BINMAN imply SYS_K3_SPL_ATF +config TARGET_J742S2_A72_EVM + bool "TI K3 based J742S2 EVM running on A72" + select ARM64 + select BOARD_LATE_INIT + select SYS_DISABLE_DCACHE_OPS + select BINMAN + +config TARGET_J742S2_R5_EVM + bool "TI K3 based J742S2 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + endchoice source "board/ti/j784s4/Kconfig" diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile index f533c5e7743..074e3b61a26 100644 --- a/arch/arm/mach-k3/r5/Makefile +++ b/arch/arm/mach-k3/r5/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/ obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ obj-$(CONFIG_SOC_K3_AM62P5) += am62px/ obj-$(CONFIG_SOC_K3_J721E) += j721e/ -obj-$(CONFIG_SOC_K3_J721E) += j7200/ +obj-$(CONFIG_SOC_K3_J7200) += j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ obj-$(CONFIG_SOC_K3_J722S) += j722s/ obj-$(CONFIG_SOC_K3_J784S4) += j784s4/ diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c index d950b35e0be..9d9a43c055b 100644 --- a/arch/arm/mach-k3/r5/am62ax/clk-data.c +++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c @@ -64,7 +64,18 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", +}; + +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { @@ -137,7 +148,16 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -180,6 +200,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -187,6 +208,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), @@ -203,6 +225,29 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"), + DEV_CLK(13, 20, "board_0_rgmii1_txc_out"), + DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"), + DEV_CLK(13, 23, "board_0_rgmii2_txc_out"), + DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -272,16 +317,19 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 20, "clkout0_ctrl_out0"), DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"), DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 133, "cpsw_3guss_main_0_rgmii1_txc_o"), + DEV_CLK(157, 136, "cpsw_3guss_main_0_rgmii2_txc_o"), DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"), DEV_CLK(157, 160, "wkup_clkout_sel_out0"), @@ -311,7 +359,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata am62ax_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 80, + .clk_list_cnt = 90, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 104, + .soc_dev_clk_data_cnt = 130, }; diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c index 6cced9efd08..fe025923f1b 100644 --- a/arch/arm/mach-k3/r5/am62ax/dev-data.c +++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c @@ -17,9 +17,10 @@ static struct ti_psc soc_psc_list[] = { static struct ti_pd soc_pd_list[] = { [0] = PSC_PD(0, &soc_psc_list[1], NULL), - [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), - [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]), - [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), + [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]), + [4] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), }; static struct ti_lpsc soc_lpsc_list[] = { @@ -32,11 +33,12 @@ static struct ti_lpsc soc_lpsc_list[] = { [6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), [7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), [8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), - [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]), - [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]), - [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]), - [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]), + [9] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[8]), + [11] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[10]), + [12] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[8]), + [13] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[12]), + [14] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]), }; static struct ti_dev soc_dev_list[] = { @@ -55,11 +57,12 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(36, &soc_lpsc_list[8]), PSC_DEV(102, &soc_lpsc_list[8]), PSC_DEV(146, &soc_lpsc_list[8]), - PSC_DEV(166, &soc_lpsc_list[9]), - PSC_DEV(135, &soc_lpsc_list[10]), - PSC_DEV(170, &soc_lpsc_list[11]), - PSC_DEV(177, &soc_lpsc_list[12]), - PSC_DEV(55, &soc_lpsc_list[13]), + PSC_DEV(13, &soc_lpsc_list[9]), + PSC_DEV(166, &soc_lpsc_list[10]), + PSC_DEV(135, &soc_lpsc_list[11]), + PSC_DEV(170, &soc_lpsc_list[12]), + PSC_DEV(177, &soc_lpsc_list[13]), + PSC_DEV(55, &soc_lpsc_list[14]), }; const struct ti_k3_pd_platdata am62ax_pd_platdata = { diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index 4b9892fe051..bc62d1d0d08 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -59,7 +59,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { @@ -193,6 +193,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -281,7 +282,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 36, "clkout0_ctrl_out0"), DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 0f6c294f1eb..0b6604039f3 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -144,7 +144,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) int ret, size = 0, shut_cpu = 0; /* Release all the exclusive devices held by SPL before starting ATF */ - ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci); + ti_sci->ops.dev_ops.release_exclusive_devices(); ret = rproc_init(); if (ret) @@ -253,6 +253,31 @@ void disable_linefill_optimization(void) asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); } +int remove_fwl_region(struct fwl_data *fwl) +{ + struct ti_sci_handle *sci = get_ti_sci_handle(); + struct ti_sci_fwl_ops *ops = &sci->ops.fwl_ops; + struct ti_sci_msg_fwl_region region; + int ret; + + region.fwl_id = fwl->fwl_id; + region.region = fwl->regions; + region.n_permission_regs = 3; + + ops->get_fwl_region(sci, ®ion); + + /* zero out the enable field of the firewall */ + region.control = region.control & ~0xF; + + pr_debug("Disabling firewall id: %d region: %d\n", + region.fwl_id, region.region); + + ret = ops->set_fwl_region(sci, ®ion); + if (ret) + pr_err("Could not disable firewall\n"); + return ret; +} + static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions, enum k3_firewall_region_type fwl_type) { diff --git a/arch/arm/mach-k3/r5/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c index eb8436decbd..996ba2023fe 100644 --- a/arch/arm/mach-k3/r5/j7200/clk-data.c +++ b/arch/arm/mach-k3/r5/j7200/clk-data.c @@ -62,6 +62,16 @@ static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { "gluelogic_hfosc0_clkout", }; +static const char * const wkupusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv2_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_usart_mcupll_bypass_clksel_out0_parents[] = { + "wkupusart_clk_sel_out0", + "gluelogic_hfosc0_clkout", +}; + static const char * const main_pll_hfosc_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -345,6 +355,8 @@ static const struct clk_data clk_list[] = { CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("wkupusart_clk_sel_out0", wkupusart_clk_sel_out0_parents, 2, 0x43008064, 0, 1, 0), + CLK_MUX("wkup_usart_mcupll_bypass_clksel_out0", wkup_usart_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), @@ -543,6 +555,10 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(287, 2, "wkup_usart_mcupll_bypass_clksel_out0"), + DEV_CLK(287, 3, "wkupusart_clk_sel_out0"), + DEV_CLK(287, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(287, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), diff --git a/arch/arm/mach-k3/r5/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c index 8ce6796fd04..12a1386f9d1 100644 --- a/arch/arm/mach-k3/r5/j7200/dev-data.c +++ b/arch/arm/mach-k3/r5/j7200/dev-data.c @@ -66,6 +66,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(149, &soc_lpsc_list[12]), PSC_DEV(113, &soc_lpsc_list[13]), PSC_DEV(197, &soc_lpsc_list[13]), + PSC_DEV(287, &soc_lpsc_list[13]), PSC_DEV(103, &soc_lpsc_list[14]), PSC_DEV(104, &soc_lpsc_list[15]), PSC_DEV(102, &soc_lpsc_list[16]), diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 9eec786fe8f..dce190ddee2 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -85,8 +85,9 @@ struct mbus_win { static inline unsigned int readfr_extra_feature_reg(void) { unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" - (val)::"cc"); + + asm_arm_or_thumb2("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); return val; } @@ -96,8 +97,8 @@ static inline unsigned int readfr_extra_feature_reg(void) */ static inline void writefr_extra_feature_reg(unsigned int val) { - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" - (val):"cc"); + asm_arm_or_thumb2("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); isb(); } diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index adb816982f8..b76510ab452 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -260,7 +260,7 @@ config DDR_LOG_LEVEL failure, RL, WL errors and other algorithm failure. At level 1, provides the D-Unit setup (SPD/Static configuration). At level 2, provides the windows margin as a results of DQS centeralization. - At level 3, rovides the windows margin of each DQ as a results of + At level 3, provides the windows margin of each DQ as a results of DQS centeralization. config DDR_IMMUTABLE_DEBUG_SETTINGS @@ -394,7 +394,6 @@ config MVEBU_SPL_BOOT_DEVICE_MMC imply SPL_LIBDISK_SUPPORT imply SPL_MMC select SUPPORT_EMMC_BOOT if SPL_MMC - select SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if SPL_MMC select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_SATA @@ -450,7 +449,7 @@ config MVEBU_EFUSE_VHV_GPIO string "VHV_Enable GPIO name for eFuse programming" depends on MVEBU_EFUSE && !ARMADA_3700 help - The eFuse programing (burning) phase requires supplying 1.8V to the + The eFuse programming (burning) phase requires supplying 1.8V to the device on the VHV power pin, while for normal operation the VHV power rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details. diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 6f3587f01d0..233dcc84393 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -11,7 +11,7 @@ endif obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif obj-y += board.o diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S index 1ab9472e198..5541a4714ac 100644 --- a/arch/arm/mach-omap2/omap3/lowlevel_init.S +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -176,10 +176,10 @@ ENTRY(lowlevel_init) ldr sp, SRAM_STACK str ip, [sp] /* stash ip register */ mov ip, lr /* save link reg across call */ -#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) +#if !defined(CONFIG_SYS_NAND_BOOT) /* * No need to copy/exec the clock code - DPLL adjust already done - * in NAND/oneNAND Boot. + * in NAND Boot. */ ldr r1, =SRAM_CLK_CODE bl cpy_clk_code diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 3c381dedaf8..d0769b55efa 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -11,13 +11,13 @@ obj-y = cpu.o obj-y += dram.o obj-y += timer.o -ifndef CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT +ifndef CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c6e347b8d9d..9210877a4a4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -15,7 +15,9 @@ config ROCKCHIP_PX30 select TPL_SERIAL select DEBUG_UART_BOARD_INIT imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR imply SPL_ROCKCHIP_COMMON_BOARD + imply TPL_LIBGENERIC_SUPPORT imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN help @@ -176,6 +178,8 @@ config ROCKCHIP_RK3308 imply OF_UPSTREAM imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL imply ROCKCHIP_OTP imply SPL_CLK imply SPL_DM_SEQ_ALIAS @@ -197,7 +201,6 @@ config ROCKCHIP_RK3328 select SUPPORT_SPL select SPL select SUPPORT_TPL - select TPL select TPL_HAVE_INIT_STACK if TPL imply ARMV8_CRYPTO imply ARMV8_SET_SMPEN @@ -208,11 +211,14 @@ config ROCKCHIP_RK3328 imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS imply SPL_SERIAL + imply TPL if !ROCKCHIP_EXTERNAL_TPL + imply TPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. @@ -285,6 +291,7 @@ config ROCKCHIP_RK3399 imply PRE_CONSOLE_BUFFER imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_DM_SEQ_ALIAS @@ -312,6 +319,56 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3528 + bool "Support Rockchip RK3528" + select ARM64 + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply BOOTSTD_FULL + imply DM_RNG + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply OF_UPSTREAM + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ATF + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_RELOC_GD_ENV_ADDR + imply SYSRESET + imply SYSRESET_PSCI if SPL_ATF + help + The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53. + config ROCKCHIP_RK3568 bool "Support Rockchip RK3568" select ARM64 @@ -334,6 +391,8 @@ config ROCKCHIP_RK3568 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL imply ROCKCHIP_OTP imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT @@ -344,6 +403,56 @@ config ROCKCHIP_RK3568 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3576 + bool "Support Rockchip RK3576" + select ARM64 + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply BOOTSTD_FULL + imply DM_RNG + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply OF_UPSTREAM + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ATF + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_RELOC_GD_ENV_ADDR + imply SYSRESET + help + The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and + and quad-core Cortex-A53. + config ROCKCHIP_RK3588 bool "Support Rockchip RK3588" select ARM64 @@ -367,6 +476,8 @@ config ROCKCHIP_RK3588 imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL imply ROCKCHIP_OTP imply SCMI_FIRMWARE imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF @@ -493,7 +604,6 @@ config TPL_ROCKCHIP_COMMON_BOARD config ROCKCHIP_EXTERNAL_TPL bool "Use external TPL binary" - default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588 help Some Rockchip SoCs require an external TPL to initialize DRAM. Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to @@ -603,17 +713,17 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE config ROCKCHIP_COMMON_STACK_ADDR bool depends on SPL_SHARES_INIT_SP_ADDR + depends on TPL || ROCKCHIP_EXTERNAL_TPL select HAS_CUSTOM_SYS_INIT_SP_ADDR imply SPL_LIBCOMMON_SUPPORT if SPL imply SPL_LIBGENERIC_SUPPORT if SPL imply SPL_ROCKCHIP_COMMON_BOARD if SPL imply SPL_SYS_MALLOC_F if SPL imply SPL_SYS_MALLOC_SIMPLE if SPL - imply TPL_LIBCOMMON_SUPPORT if TPL - imply TPL_LIBGENERIC_SUPPORT if TPL - imply TPL_ROCKCHIP_COMMON_BOARD if TPL - imply TPL_SYS_MALLOC_F if TPL - imply TPL_SYS_MALLOC_SIMPLE if TPL + imply TPL_LIBCOMMON_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD + imply TPL_LIBGENERIC_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SYS_MALLOC_F if TPL && TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SYS_MALLOC_SIMPLE if TPL && TPL_ROCKCHIP_COMMON_BOARD config NR_DRAM_BANKS default 10 if ROCKCHIP_EXTERNAL_TPL @@ -629,7 +739,9 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3528/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" +source "arch/arm/mach-rockchip/rk3576/Kconfig" source "arch/arm/mach-rockchip/rk3588/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" source "arch/arm/mach-rockchip/rv1126/Kconfig" @@ -637,40 +749,64 @@ source "arch/arm/mach-rockchip/rv1126/Kconfig" if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR config CUSTOM_SYS_INIT_SP_ADDR - default 0x3f00000 + default 0x63f00000 if SPL_TEXT_BASE = 0x60000000 + default 0x43f00000 if SPL_TEXT_BASE = 0x40000000 + default 0x03f00000 if SPL_TEXT_BASE = 0x00000000 config SYS_MALLOC_F_LEN - default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config SPL_SYS_MALLOC_F_LEN - default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TPL_SYS_MALLOC_F_LEN - default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x0800 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TEXT_BASE - default 0x00200000 if ARM64 + default 0x60200000 if SPL_TEXT_BASE = 0x60000000 + default 0x40200000 if SPL_TEXT_BASE = 0x40000000 + default 0x00200000 if SPL_TEXT_BASE = 0x00000000 config SPL_TEXT_BASE - default 0x0 if ARM64 + default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \ + ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \ + ROCKCHIP_RK322X || ROCKCHIP_RV1108 + default 0x40000000 if ROCKCHIP_RK3576 + default 0x00000000 config SPL_HAS_BSS_LINKER_SECTION default y if ARM64 config SPL_BSS_START_ADDR - default 0x3f80000 + default 0x63f80000 if SPL_TEXT_BASE = 0x60000000 + default 0x43f80000 if SPL_TEXT_BASE = 0x40000000 + default 0x03f80000 if SPL_TEXT_BASE = 0x00000000 config SPL_BSS_MAX_SIZE - default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000 + default 0x8000 if SPL_BSS_START_ADDR = 0x63f80000 + default 0x8000 if SPL_BSS_START_ADDR = 0x43f80000 + default 0x8000 if SPL_BSS_START_ADDR = 0x03f80000 config SPL_STACK_R - default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config SPL_STACK_R_ADDR - default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + default 0x63e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000 + default 0x43e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000 + default 0x03e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config SPL_STACK_R_MALLOC_SIMPLE_LEN - default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000 + default 0x200000 if SPL_STACK_R_ADDR = 0x63e00000 + default 0x200000 if SPL_STACK_R_ADDR = 0x43e00000 + default 0x200000 if SPL_STACK_R_ADDR = 0x03e00000 endif endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5e7edc99cdc..ae15a9f8a2d 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,7 +42,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ +obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/ obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index dcf9eb8144b..2b57b166894 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,9 +68,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "px30" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config SYS_MALLOC_F_LEN default 0x400 if !SPL_SHARES_INIT_SP_ADDR diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index fac966207a9..06572d545f6 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TEXT_BASE default 0x00600000 diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 03d97e1d746..6916f1a2444 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -3,15 +3,12 @@ *Copyright (c) 2018 Rockchip Electronics Co., Ltd */ #include <init.h> -#include <malloc.h> +#include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3308.h> #include <asm/arch-rockchip/hardware.h> -#include <asm/gpio.h> -#include <debug_uart.h> #include <linux/bitops.h> -#include <asm/armv8/mmu.h> static struct mm_region rk3308_mem_map[] = { { .virt = 0x0UL, @@ -38,22 +35,6 @@ struct mm_region *mem_map = rk3308_mem_map; #define SGRF_BASE 0xff2b0000 enum { - GPIO1C7_SHIFT = 8, - GPIO1C7_MASK = GENMASK(11, 8), - GPIO1C7_GPIO = 0, - GPIO1C7_UART1_RTSN, - GPIO1C7_UART2_TX_M0, - GPIO1C7_SPI2_MOSI, - GPIO1C7_JTAG_TMS, - - GPIO1C6_SHIFT = 4, - GPIO1C6_MASK = GENMASK(7, 4), - GPIO1C6_GPIO = 0, - GPIO1C6_UART1_CTSN, - GPIO1C6_UART2_RX_M0, - GPIO1C6_SPI2_MISO, - GPIO1C6_JTAG_TCLK, - GPIO4D3_SHIFT = 6, GPIO4D3_MASK = GENMASK(7, 6), GPIO4D3_GPIO = 0, @@ -116,60 +97,12 @@ enum { GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1, }; -enum { - IOVSEL3_CTRL_SHIFT = 8, - IOVSEL3_CTRL_MASK = BIT(8), - VCCIO3_SEL_BY_GPIO = 0, - VCCIO3_SEL_BY_IOVSEL3, - - IOVSEL3_SHIFT = 3, - IOVSEL3_MASK = BIT(3), - VCCIO3_3V3 = 0, - VCCIO3_1V8, -}; - -/* - * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc - * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults - * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware, - * then we can switch to io_vsel3 after system power on, and release GPIO0_A4 - * for other usage. - */ - -#define GPIO0_A4 4 - const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000", [BROM_BOOTSOURCE_SPINOR] = "/spi@ff4c0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff480000", }; -int rk_board_init(void) -{ - static struct rk3308_grf * const grf = (void *)GRF_BASE; - u32 val; - int ret; - - ret = gpio_request(GPIO0_A4, "gpio0_a4"); - if (ret < 0) { - printf("request for gpio0_a4 failed:%d\n", ret); - return 0; - } - - gpio_direction_input(GPIO0_A4); - - if (gpio_get_value(GPIO0_A4)) - val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | - VCCIO3_1V8 << IOVSEL3_SHIFT; - else - val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | - VCCIO3_3V3 << IOVSEL3_SHIFT; - rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val); - - gpio_free(GPIO0_A4); - return 0; -} - #ifdef CONFIG_DEBUG_UART_BOARD_INIT __weak void board_debug_uart_init(void) { diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 70770da5fdf..ec1dae8d413 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,9 +21,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3328" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 500cfcd87af..b2430207ee9 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -143,9 +143,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3399" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig new file mode 100644 index 00000000000..993b2dd274e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/Kconfig @@ -0,0 +1,15 @@ +if ROCKCHIP_RK3528 + +config ROCKCHIP_BOOT_MODE_REG + default 0xff370200 + +config ROCKCHIP_STIMER_BASE + default 0xff620000 + +config SYS_SOC + default "rk3528" + +config SYS_CONFIG_NAME + default "rk3528_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS new file mode 100644 index 00000000000..f343f71cf7f --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS @@ -0,0 +1,11 @@ +GENERIC-RK3528 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3528-generic* +F: configs/generic-rk3528_defconfig + +RADXA-E20C +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3528-radxa-e20c* +F: configs/radxa-e20c-rk3528_defconfig diff --git a/arch/arm/mach-rockchip/rk3528/Makefile b/arch/arm/mach-rockchip/rk3528/Makefile new file mode 100644 index 00000000000..f0c18cd39d2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += rk3528.o +obj-y += clk_rk3528.o +obj-y += syscon_rk3528.o diff --git a/arch/arm/mach-rockchip/rk3528/clk_rk3528.c b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c new file mode 100644 index 00000000000..6e77f11cbec --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <asm/arch-rockchip/cru_rk3528.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3528_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return RK3528_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c new file mode 100644 index 00000000000..4892ff6ba9d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <misc.h> +#include <asm/armv8/mmu.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> + +#define FIREWALL_DDR_BASE 0xff2e0000 +#define FW_DDR_MST6_REG 0x58 +#define FW_DDR_MST7_REG 0x5c +#define FW_DDR_MST14_REG 0x78 +#define FW_DDR_MST16_REG 0x80 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000", +}; + +static struct mm_region rk3528_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xfc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xfc000000UL, + .phys = 0xfc000000UL, + .size = 0x04000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3528_mem_map; + +void board_debug_uart_init(void) +{ +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Set the emmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG); + writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG); + + /* Set the fspi to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG); + writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG); + + /* Set the sdmmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG); + writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG); + + /* Set the usb to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + + return 0; +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +#define RK3528_OTP_CPU_CODE_OFFSET 0x02 +#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET 0x28 + +int checkboard(void) +{ + u8 cpu_code[2], chip_type; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x28 */ + ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1); + if (ret < 0) { + log_debug("Could not read chip type, ret=%d\n", ret); + return 0; + } + + suffix[0] = chip_type != 0x1 ? 'A' : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c new file mode 100644 index 00000000000..4a32a5f732e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3528_syscon_ids[] = { + { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3528_syscon) = { + .name = "rockchip_rk3528_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3528_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index ce327ed6f9e..01b53a47ddb 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -5,7 +5,6 @@ choice config TARGET_EVB_RK3568 bool "RK3568 evaluation board" - select BOARD_LATE_INIT help RK3568 EVB is a evaluation board for Rockchp RK3568. @@ -71,9 +70,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TEXT_BASE default 0x00a00000 @@ -87,4 +83,7 @@ source "board/qnap/ts433/Kconfig" source "board/radxa/zero3-rk3566/Kconfig" source "board/xunlong/orangepi-3b-rk3566/Kconfig" +config SYS_CONFIG_NAME + default "rk3568_common" + endif diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig new file mode 100644 index 00000000000..f347caf8904 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/Kconfig @@ -0,0 +1,23 @@ +if ROCKCHIP_RK3576 + +config TARGET_ROC_PC_RK3576 + bool "Firefly ROC-RK3576-PC" + help + ROC-RK3576-PC is a single board computer from Firefly + using the Rockchip RK3576. + +config ROCKCHIP_BOOT_MODE_REG + default 0x26024040 + +config ROCKCHIP_STIMER_BASE + default 0x27400000 + +config SYS_SOC + default "rk3576" + +source board/firefly/roc-pc-rk3576/Kconfig + +config SYS_CONFIG_NAME + default "rk3576_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3576/Makefile b/arch/arm/mach-rockchip/rk3576/Makefile new file mode 100644 index 00000000000..cbc58257deb --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2023 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3576.o +obj-y += clk_rk3576.o +obj-y += syscon_rk3576.o diff --git a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c new file mode 100644 index 00000000000..edda1afd0bd --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2020 Rockchip Electronics Co., Ltd. + */ + +#include <dm.h> +#include <asm/arch-rockchip/cru_rk3576.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3576_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return (void *)RK3576_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c new file mode 100644 index 00000000000..ba5c94b4b3d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + */ + +#include <asm/armv8/mmu.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> + +#define SYS_GRF_BASE 0x2600A000 +#define SYS_GRF_SOC_CON2 0x0008 +#define SYS_GRF_SOC_CON7 0x001c +#define SYS_GRF_SOC_CON11 0x002c +#define SYS_GRF_SOC_CON12 0x0030 + +#define GPIO0_IOC_BASE 0x26040000 +#define GPIO0B_PULL_L 0x0024 +#define GPIO0B_IE_L 0x002C + +#define SYS_SGRF_BASE 0x26004000 +#define SYS_SGRF_SOC_CON14 0x0058 +#define SYS_SGRF_SOC_CON15 0x005C +#define SYS_SGRF_SOC_CON20 0x0070 + +#define FW_SYS_SGRF_BASE 0x26005000 +#define SGRF_DOMAIN_CON1 0x4 +#define SGRF_DOMAIN_CON2 0x8 +#define SGRF_DOMAIN_CON3 0xc +#define SGRF_DOMAIN_CON4 0x10 +#define SGRF_DOMAIN_CON5 0x14 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", +}; + +static struct mm_region rk3576_mem_map[] = { + { + /* I/O area */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0xb080000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PMU_SRAM, CBUF, SYSTEM_SRAM */ + .virt = 0x3fe70000UL, + .phys = 0x3fe70000UL, + .size = 0x190000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* MSCH_DDR_PORT */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* PCIe 0+1 */ + .virt = 0x900000000UL, + .phys = 0x900000000UL, + .size = 0x100800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3576_mem_map; + +void board_debug_uart_init(void) +{ +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Set the emmc to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); + writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); + + /* Set the sdmmc0 to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5); + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5); + + /* Set the UFS to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3); + writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3); + + /* Set the fspi0 and fspi1 to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4); + writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4); + + /* Set the decom to access ddr memory */ + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1); + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1); + + /* + * Set the GPIO0B0~B3 pull up and input enable. + * Keep consistent with other IO. + */ + writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L); + writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L); + + /* + * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0, + * keep consistent with other pwm. + */ + writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2); + + /* Enable noc slave response timeout */ + writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11); + writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12); + + /* + * Enable cci channels for below module AXI R/W + * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3) + */ + writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c new file mode 100644 index 00000000000..0dbf8f8d9c0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2023 Rockchip Electronics Co., Ltd + */ + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3576_syscon_ids[] = { + { .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3576_syscon) = { + .name = "rockchip_rk3576_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3576_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 155b8f00ca2..4e7942ada87 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -2,13 +2,11 @@ if ROCKCHIP_RK3588 config TARGET_EVB_RK3588 bool "Rockchip EVB1 v10" - select BOARD_LATE_INIT help RK3588 EVB is a evaluation board for Rockchp RK3588. config TARGET_CM3588_NAS_RK3588 bool "FriendlyElec CM3588 NAS" - select BOARD_LATE_INIT help The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. @@ -31,7 +29,6 @@ config TARGET_CM3588_NAS_RK3588 config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" - select BOARD_LATE_INIT help GeenBook is a notebook based on Rockchip RK3588, and works as a carrier board connect with CM5 SOM. @@ -49,7 +46,6 @@ config TARGET_GENBOOK_CM5_RK3588 config TARGET_JAGUAR_RK3588 bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" - select BOARD_LATE_INIT help The SBC-RK3588-AMR is a Single Board Computer designed by Theobroma Systems for autonomous mobile robots. @@ -76,7 +72,6 @@ config TARGET_JAGUAR_RK3588 config TARGET_KHADAS_EDGE2_RK3588 bool "Khadas Edge2 RK3588 board" - select BOARD_LATE_INIT help Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer) by Khadas. @@ -98,7 +93,6 @@ config TARGET_KHADAS_EDGE2_RK3588 config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" - select BOARD_LATE_INIT help The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec. @@ -143,7 +137,6 @@ config TARGET_NANOPCT6_RK3588 config TARGET_NANOPI_R6C_RK3588S bool "FriendlyElec NanoPi R6C" - select BOARD_LATE_INIT help The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip RK3588s. @@ -155,7 +148,6 @@ config TARGET_NANOPI_R6C_RK3588S config TARGET_NANOPI_R6S_RK3588S bool "FriendlyElec NanoPi R6S" - select BOARD_LATE_INIT help The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip RK3588s. @@ -167,7 +159,6 @@ config TARGET_NANOPI_R6S_RK3588S config TARGET_NOVA_RK3588 bool "Indiedroid Nova RK3588" - select BOARD_LATE_INIT help Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid. It comes in configurations from 4GB of RAM to 16GB of RAM, @@ -176,13 +167,11 @@ config TARGET_NOVA_RK3588 config TARGET_ODROID_M2_RK3588S bool "Hardkernel ODROID-M2" - select BOARD_LATE_INIT help Hardkernel ODROID-M2 single board computer with a RK3588S2 SoC. config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" - select BOARD_LATE_INIT help Neu6A: Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module @@ -204,7 +193,6 @@ config TARGET_RK3588_NEU6 config TARGET_ROCK5A_RK3588 bool "Radxa ROCK5A RK3588 board" - select BOARD_LATE_INIT help Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa. @@ -231,7 +219,6 @@ config TARGET_ROCK5A_RK3588 config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" - select BOARD_LATE_INIT help Radxa ROCK5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa. @@ -256,7 +243,6 @@ config TARGET_ROCK5B_RK3588 config TARGET_ROCK_5_ITX_RK3588 bool "Radxa ROCK-5-ITX RK3588 board" - select BOARD_LATE_INIT help Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa in the ITX formfactor. @@ -284,7 +270,6 @@ config TARGET_ROCK_5_ITX_RK3588 config TARGET_ROCK_5C_RK3588S bool "Radxa ROCK 5C RK3588S2 board" - select BOARD_LATE_INIT help Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer. @@ -304,7 +289,6 @@ config TARGET_ROCK_5C_RK3588S config TARGET_SIGE7_RK3588 bool "ArmSoM Sige7 RK3588 board" - select BOARD_LATE_INIT help ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by ArmSoM. @@ -329,14 +313,12 @@ config TARGET_SIGE7_RK3588 config TARGET_QUARTZPRO64_RK3588 bool "Pine64 QuartzPro64 RK3588 board" - select BOARD_LATE_INIT help Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board Computer) by Pine64. config TARGET_TIGER_RK3588 bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)" - select BOARD_LATE_INIT help The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the @@ -366,7 +348,6 @@ config TARGET_TIGER_RK3588 config TARGET_TURINGRK1_RK3588 bool "Turing Machines RK1 RK3588 board" - select BOARD_LATE_INIT help The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines. @@ -389,7 +370,6 @@ config TARGET_TURINGRK1_RK3588 config TARGET_TOYBRICK_RK3588 bool "Toybrick TB-RK3588X board" - select BOARD_LATE_INIT help Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board. TB-RK3588X adopts core board and mainboard design. The core board is connected @@ -420,9 +400,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config ROCKCHIP_COMMON_STACK_ADDR - default y - config TEXT_BASE default 0x00a00000 @@ -447,4 +424,7 @@ source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" source "board/theobroma-systems/tiger_rk3588/Kconfig" +config SYS_CONFIG_NAME + default "rk3588_common" + endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index c1dce3ee370..e2278ff792b 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -116,18 +116,25 @@ void board_debug_uart_init(void) } #ifdef CONFIG_XPL_BUILD + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + void rockchip_stimer_init(void) { /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4); + u32 reg = readl(HP_TIMER_BASE + HP_CTRL_REG); - if (reg & 0x1) + if (reg & TIMER_EN) return; - asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18); - writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4); + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); } #endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index f7d32829295..3bc482331c7 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -110,7 +110,9 @@ static int rockchip_dram_init_banksize(void) u8 i, j; if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) && - !IS_ENABLED(CONFIG_ROCKCHIP_RK3568)) + !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) && + !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) && + !IS_ENABLED(CONFIG_ROCKCHIP_RK3528)) return -ENOTSUPP; if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL)) @@ -181,9 +183,9 @@ static int rockchip_dram_init_banksize(void) * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not * have it, so force this space as reserved. */ - if (start_addr < SZ_2M) { - size -= SZ_2M - start_addr; - start_addr = SZ_2M; + if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) { + size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr; + start_addr = CFG_SYS_SDRAM_BASE + SZ_2M; } /* @@ -228,7 +230,7 @@ static int rockchip_dram_init_banksize(void) return -EINVAL; } - size -= rsrv_end - start_addr; + size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE); start_addr = rsrv_end; break; } @@ -301,8 +303,8 @@ int dram_init_banksize(void) debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n", ret); - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; + /* Reserve 2M for ATF bl31 */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index cc8f405e20b..11e8104baf2 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -46,4 +46,19 @@ static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsig return pindata->special_pins_start && pin >= pindata->special_pins_start; } +struct udevice; + +/** + * msm_pinctrl_is_reserved() - Check if a pin lies in a reserved range + * + * @dev: pinctrl device + * @pin: Pin number + * + * Returns: true if pin is reserved, otherwise false + * + * Call using dev_get_parent() from the GPIO device, it is a child of + * the pinctrl device. + */ +bool msm_pinctrl_is_reserved(struct udevice *dev, unsigned int pin); + #endif /* _QCOM_GPIO_H_ */ diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 55368dd43b6..1ea0c18c2f2 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -86,13 +86,13 @@ static int fixup_qcom_dwc3(struct device_node *glue_np) } /* Overwrite "phy-names" to only contain a single entry */ - ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy"); + ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy") + 1, "usb2-phy"); if (ret) { log_err("Failed to overwrite 'phy-names' property: %d\n", ret); return ret; } - ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed"); + ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed") + 1, "high-speed"); if (ret) { log_err("Failed to set 'maximum-speed' property: %d\n", ret); return ret; @@ -161,14 +161,14 @@ int ft_board_setup(void *blob, struct bd_info __maybe_unused *bd) struct fdt_header *fdt = blob; int node; - /* We only want to do this fix-up for the RB1 board, quick return for all others */ - if (!fdt_node_check_compatible(fdt, 0, "qcom,qrb4210-rb2")) - return 0; - - fdt_for_each_node_by_compatible(node, blob, 0, "snps,dwc3") { - log_debug("%s: Setting 'dr_mode' to OTG\n", fdt_get_name(blob, node, NULL)); - fdt_setprop_string(fdt, node, "dr_mode", "otg"); - break; + /* On RB1/2 we need to fix-up the dr_mode */ + if (!fdt_node_check_compatible(fdt, 0, "qcom,qrb4210-rb2") || + !fdt_node_check_compatible(fdt, 0, "qcom,qrb2210-rb1")) { + fdt_for_each_node_by_compatible(node, blob, 0, "snps,dwc3") { + log_debug("%s: Setting 'dr_mode' to OTG\n", fdt_get_name(blob, node, NULL)); + fdt_setprop_string(fdt, node, "dr_mode", "otg"); + break; + } } return 0; diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 22d48dfae1c..c43fdee4a48 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -68,6 +68,8 @@ obj-y += altera-sysmgr.o obj-y += ccu_ncore3.o obj-y += system_manager_soc64.o obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 27072e53135..8506d510413 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -195,3 +195,16 @@ void board_prep_linux(struct bootm_headers *images) } } #endif + +#if CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP) +void lmb_arch_add_memory(void) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (bd->bi_dram[i].size) + lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + } +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2b..5ac868a281b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -51,6 +51,7 @@ #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 45cc9912f94..2099c51b682 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -128,6 +128,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 /* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -385,6 +386,8 @@ enum MBOX_CFGSTAT_MINOR_ERR_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31) +#define HPS_EXECUTION_STATE_FSBL 0 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -401,6 +404,7 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 058fdd6e548..4b010be9ee8 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -10,9 +10,12 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); -void socfpga_bridges_reset(int enable); +void socfpga_bridges_reset(int enable, unsigned int mask); #define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_HDSKEN 0x10 +#define RSTMGR_SOC64_HDSKREQ 0x14 +#define RSTMGR_SOC64_HDSKACK 0x18 #define RSTMGR_SOC64_MPUMODRST 0x20 #define RSTMGR_SOC64_PER0MODRST 0x24 #define RSTMGR_SOC64_PER1MODRST 0x28 @@ -20,8 +23,17 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0) +#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1) +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2) +#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3) +#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) +#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) +#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) + +#define RSTMGR_HDSKEN_FPGAHSEN BIT(2) +#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) /* SDM, Watchdogs and MPU warm reset mask */ #define RSTMGR_STAT_SDMWARMRST 0x2 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index b69bd3e47ec..f9c34e85711 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -6,6 +6,7 @@ #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> @@ -474,6 +475,17 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); } +int mbox_hps_stage_notify(u32 execution_stage) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1, &execution_stage, + 0, 0, NULL); +#else + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +#endif +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index e0b2b4237e1..4f080f4f0b3 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -61,7 +61,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", + printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; @@ -107,5 +107,5 @@ void do_bridge_reset(int enable, unsigned int mask) return; } - socfpga_bridges_reset(enable); + socfpga_bridges_reset(enable, mask); } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index b8e40d9a788..1dc44ab4797 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -58,6 +58,20 @@ static struct mm_region socfpga_agilex5_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE, }, { + /* MEM 30GB */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x780000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* MEM 480GB */ + .virt = 0x8800000000UL, + .phys = 0x8800000000UL, + .size = 0x7800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { /* List terminator */ }, }; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index a634c11a028..abb62a9b49f 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,21 +1,34 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <errno.h> #include <hang.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/secure.h> #include <asm/arch/reset_manager.h> #include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <exports.h> #include <linux/iopoll.h> #include <linux/intel-smc.h> +#include <wait_bit.h> DECLARE_GLOBAL_DATA_PTR; +#define TIMEOUT_300MS 300 + +/* F2S manager registers */ +#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14 +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 + /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -56,66 +69,213 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } -void socfpga_bridges_reset(int enable) +static void socfpga_f2s_bridges_reset(int enable, unsigned int mask) { -#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) - u64 arg = enable; + int ret; + u32 brg_mask; + u32 flagout_idlereq = 0; + u32 flagoutset_fdrain = 0; + u32 flagoutset_en = 0; + u32 flaginstatus_idleack = 0; + u32 flaginstatus_respempty = 0; + + if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + /* Support fpga2soc and f2sdram */ + brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | + RSTMGR_BRGMODRST_F2SDRAM0_MASK | + RSTMGR_BRGMODRST_F2SDRAM1_MASK | + RSTMGR_BRGMODRST_F2SDRAM2_MASK); - int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); - if (ret) { - printf("SMC call failed with error %d in %s.\n", ret, __func__); + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) { + flagout_idlereq |= BIT(3); + flaginstatus_idleack |= BIT(5); + flagoutset_fdrain |= BIT(5); + flagoutset_en |= BIT(4); + flaginstatus_respempty |= BIT(7); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) { + flagout_idlereq |= BIT(6); + flaginstatus_idleack |= BIT(9); + flagoutset_fdrain |= BIT(8); + flagoutset_en |= BIT(7); + flaginstatus_respempty |= BIT(11); + } + } else { + /* Support fpga2soc only */ + brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK; + if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + } + + /* mask is not set, return here */ + if (!brg_mask) return; + + if (enable) { + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); + + /* Wait for mpfe noc idleack to 0 */ + wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_idleack, false, TIMEOUT_300MS, false); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagoutset_fdrain); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); + + udelay(1); /* wait 1us */ + } else { + if (readl((socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_BRGMODRST) & brg_mask)) { + /* Bridge cannot be reset twice */ + return; + } + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN, + RSTMGR_HDSKEN_FPGAHSEN); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + + /* Wait for FPGA ack the handshake request to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_HDSKACK), RSTMGR_HDSKREQ_FPGAHSREQ, + true, TIMEOUT_300MS, false); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en); + + udelay(1); + + /* Requests MPFE NoC to idle */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagout_idlereq); + + /* Force F2S bridge to drain */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_fdrain); + + /* Wait for respond queue empty status to 1 (resp idle) */ + ret = wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS, false); + + /* Confirm again */ + if (!ret) + ret = wait_for_bit_le32((u32 *) + (SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS, false); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); } -#else - u32 reg; +} + +static void socfpga_s2f_bridges_reset(int enable, unsigned int mask) +{ + unsigned int noc_mask = 0; + unsigned int brg_mask = 0; + + if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) { + noc_mask = SYSMGR_NOC_H2F_MSK; + brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK; + } + + if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) { + noc_mask |= SYSMGR_NOC_LWH2F_MSK; + brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK; + } + + /* s2f mask is not set, return here */ + if (!brg_mask) + return; if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask); - /* Release all bridges from reset state */ + /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~0); + brg_mask); - /* Poll until all idleack to 0 */ - read_poll_timeout(readl, reg, !reg, 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); + /* Wait for all NOC master ack to 0 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, false, + TIMEOUT_300MS, false); } else { /* set idle request to all bridges */ - writel(~0, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_SET); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask); /* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); - /* Poll until all idleack to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); - - /* Poll until all idlestatus to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS); - - /* Reset all bridges (except NOR DDR scheduler & F2S) */ + /* Wait for all NOC master ack to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, true, + TIMEOUT_300MS, false); + + /* Wait for all NOC master idlestatus to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLESTATUS), noc_mask, true, + TIMEOUT_300MS, false); + + /* Reset all SOC2FPGA bridges */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + brg_mask); /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } -#endif +} + +void socfpga_bridges_reset(int enable, unsigned int mask) +{ + if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + u64 arg[2]; + int ret; + + /* Set bit-1 to indicate has mask value in arg[1]. */ + arg[0] = (enable & BIT(0)) | BIT(1); + arg[1] = mask; + + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg, + ARRAY_SIZE(arg), NULL, 0); + if (ret) + printf("Failed to %s the HPS bridges, check bridges availability. Status %d.\n", + enable ? "enable" : "disable", ret); + } else { + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); + } } /* diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 52617a39cca..91c27a5543d 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -50,6 +50,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); ret = uclass_get_device(UCLASS_CLK, 0, &dev); @@ -77,8 +81,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 3451611082d..a9aad5350d2 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -62,6 +62,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { debug("Clock init failed: %d\n", ret); @@ -100,8 +104,6 @@ void board_init_f(ulong dummy) } } - mbox_init(); - if (IS_ENABLED(CONFIG_CADENCE_QSPI)) mbox_qspi_open(); diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 5ff137e5c6f..81283ef7162 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -49,6 +49,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); preloader_console_init(); @@ -84,8 +88,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 53852cb7443..fa83ff96adc 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -52,6 +52,10 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); /* configuring the HPS clocks */ @@ -84,8 +88,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index a44ebf25975..de9d8547e61 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -15,6 +15,7 @@ config STM32F4 select STM32_SERIAL select STM32_TIMER select TIMER + imply OF_UPSTREAM config STM32F7 bool "stm32f7 family" @@ -32,6 +33,7 @@ config STM32F7 select STM32_TIMER select SUPPORT_SPL select TIMER + imply OF_UPSTREAM imply SPL_OS_BOOT config STM32H7 @@ -51,6 +53,7 @@ config STM32H7 select STM32_TIMER select SYSCON select TIMER + imply OF_UPSTREAM source "arch/arm/mach-stm32/stm32f4/Kconfig" source "arch/arm/mach-stm32/stm32f7/Kconfig" diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 002da2e3d3b..58250901101 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -52,6 +52,7 @@ config STM32MP13X select STM32_SERIAL select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO + imply OF_UPSTREAM help support of STMicroelectronics SOC STM32MP13x family STMicroelectronics MPU with core ARMv7 @@ -73,6 +74,7 @@ config STM32MP15X select SUPPORT_SPL select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO + imply OF_UPSTREAM help support of STMicroelectronics SOC STM32MP15x family STM32MP157, STM32MP153 or STM32MP151 @@ -94,6 +96,7 @@ config STM32MP25X imply CMD_NVEDIT_INFO imply DM_REGULATOR imply DM_REGULATOR_SCMI + imply OF_UPSTREAM imply OPTEE imply RESET_SCMI imply SYSRESET_PSCI @@ -127,14 +130,6 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 Partition on the second MMC to load U-Boot from when the MMC is being used in raw mode -config STM32_ETZPC - bool "STM32 Extended TrustZone Protection" - depends on STM32MP15X || STM32MP13X - default y - imply BOOTP_SERVERIP - help - Say y to enable STM32 Extended TrustZone Protection - config STM32_ECDSA_VERIFY bool "STM32 ECDSA verification via the ROM API" depends on SPL_ECDSA_VERIFY diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 040a70f581c..6bfa67859e1 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -14,12 +14,23 @@ /* * Closed device: OTP0 - * STM32MP15x: bit 6 of OPT0 + * STM32MP15x: bit 6 of OTP0 * STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device + * STM32MP25x: bit 0 of OTP18 */ -#define STM32_OTP_CLOSE_ID 0 -#define STM32_OTP_STM32MP13X_CLOSE_MASK 0x3F -#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6) +#define STM32MP1_OTP_CLOSE_ID 0 +#define STM32_OTP_STM32MP13X_CLOSE_MASK GENMASK(5, 0) +#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6) +#define STM32MP25_OTP_WORD8 8 +#define STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK GENMASK(7, 0) +#define STM32MP25_OTP_CLOSE_ID 18 +#define STM32_OTP_STM32MP25X_CLOSE_MASK GENMASK(3, 0) +#define STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK GENMASK(7, 4) +#define STM32MP25_OTP_HWCONFIG 124 +#define STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK BIT(20) + +#define STM32MP25_OTP_BOOTROM_CONF8 17 +#define STM32_OTP_STM32MP25X_OEM_KEY2_EN BIT(8) /* PKH is the first element of the key list */ #define STM32KEY_PKH 0 @@ -27,8 +38,9 @@ struct stm32key { char *name; char *desc; - u8 start; + u16 start; u8 size; + int (*post_process)(struct udevice *dev); }; const struct stm32key stm32mp13_list[] = { @@ -55,6 +67,99 @@ const struct stm32key stm32mp15_list[] = { } }; +static int post_process_oem_key2(struct udevice *dev); + +const struct stm32key stm32mp25_list[] = { + [STM32KEY_PKH] = { + .name = "OEM-KEY1", + .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLA or M", + .start = 144, + .size = 8, + }, + { + .name = "OEM-KEY2", + .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLM", + .start = 152, + .size = 8, + .post_process = post_process_oem_key2, + }, + { + .name = "FIP-EDMK", + .desc = "Encryption/Decryption Master Key for FIP", + .start = 260, + .size = 8, + }, + { + .name = "EDMK1", + .desc = "Encryption/Decryption Master Key for FSBLA or M", + .start = 364, + .size = 4, + }, + { + .name = "EDMK2", + .desc = "Encryption/Decryption Master Key for FSBLM", + .start = 360, + .size = 4, + } +}; + +struct otp_close { + u32 word; + u32 mask_wr; + u32 mask_rd; + bool (*close_status_ops)(u32 value, u32 mask); +}; + +static bool compare_mask_exact(u32 value, u32 mask) +{ + return ((value & mask) == mask); +} + +static bool compare_any_bits(u32 value, u32 mask) +{ + return ((value & mask) != 0); +} + +const struct otp_close stm32mp13_close_state_otp[] = { + { + .word = STM32MP1_OTP_CLOSE_ID, + .mask_wr = STM32_OTP_STM32MP13X_CLOSE_MASK, + .mask_rd = STM32_OTP_STM32MP13X_CLOSE_MASK, + .close_status_ops = compare_mask_exact, + } +}; + +const struct otp_close stm32mp15_close_state_otp[] = { + { + .word = STM32MP1_OTP_CLOSE_ID, + .mask_wr = STM32_OTP_STM32MP15X_CLOSE_MASK, + .mask_rd = STM32_OTP_STM32MP15X_CLOSE_MASK, + .close_status_ops = compare_mask_exact, + } +}; + +const struct otp_close stm32mp25_close_state_otp[] = { + { + .word = STM32MP25_OTP_WORD8, + .mask_wr = STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK, + .mask_rd = 0, + .close_status_ops = NULL + }, + { + .word = STM32MP25_OTP_CLOSE_ID, + .mask_wr = STM32_OTP_STM32MP25X_CLOSE_MASK | + STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK, + .mask_rd = STM32_OTP_STM32MP25X_CLOSE_MASK, + .close_status_ops = compare_any_bits + }, + { + .word = STM32MP25_OTP_HWCONFIG, + .mask_wr = STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK, + .mask_rd = 0, + .close_status_ops = NULL + }, +}; + /* index of current selected key in stm32key list, 0 = PKH by default */ static u8 stm32key_index; @@ -65,6 +170,9 @@ static u8 get_key_nb(void) if (IS_ENABLED(CONFIG_STM32MP15X)) return ARRAY_SIZE(stm32mp15_list); + + if (IS_ENABLED(CONFIG_STM32MP25X)) + return ARRAY_SIZE(stm32mp25_list); } static const struct stm32key *get_key(u8 index) @@ -74,15 +182,33 @@ static const struct stm32key *get_key(u8 index) if (IS_ENABLED(CONFIG_STM32MP15X)) return &stm32mp15_list[index]; + + if (IS_ENABLED(CONFIG_STM32MP25X)) + return &stm32mp25_list[index]; } -static u32 get_otp_close_mask(void) +static u8 get_otp_close_state_nb(void) { if (IS_ENABLED(CONFIG_STM32MP13X)) - return STM32_OTP_STM32MP13X_CLOSE_MASK; + return ARRAY_SIZE(stm32mp13_close_state_otp); if (IS_ENABLED(CONFIG_STM32MP15X)) - return STM32_OTP_STM32MP15X_CLOSE_MASK; + return ARRAY_SIZE(stm32mp15_close_state_otp); + + if (IS_ENABLED(CONFIG_STM32MP25X)) + return ARRAY_SIZE(stm32mp25_close_state_otp); +} + +static const struct otp_close *get_otp_close_state(u8 index) +{ + if (IS_ENABLED(CONFIG_STM32MP13X)) + return &stm32mp13_close_state_otp[index]; + + if (IS_ENABLED(CONFIG_STM32MP15X)) + return &stm32mp15_close_state_otp[index]; + + if (IS_ENABLED(CONFIG_STM32MP25X)) + return &stm32mp25_close_state_otp[index]; } static int get_misc_dev(struct udevice **dev) @@ -96,13 +222,13 @@ static int get_misc_dev(struct udevice **dev) return ret; } -static void read_key_value(const struct stm32key *key, u32 addr) +static void read_key_value(const struct stm32key *key, unsigned long addr) { int i; for (i = 0; i < key->size; i++) { printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i, - addr, __be32_to_cpu(*(u32 *)addr)); + (u32)addr, __be32_to_cpu(*(u32 *)addr)); addr += 4; } } @@ -157,26 +283,42 @@ static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool pr static int read_close_status(struct udevice *dev, bool print, bool *closed) { - int word, ret, result; - u32 val, lock, mask; - bool status; + int ret, result, i; + const struct otp_close *otp_close = NULL; + u32 otp_close_nb = get_otp_close_state_nb(); + u32 val, lock, mask, word = 0; + bool status = true; + bool tested_once = false; result = 0; - word = STM32_OTP_CLOSE_ID; - ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); - if (ret < 0) - result = ret; - if (ret != 4) - val = 0x0; - - ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); - if (ret < 0) - result = ret; - if (ret != 4) - lock = BSEC_LOCK_ERROR; - - mask = get_otp_close_mask(); - status = (val & mask) == mask; + for (i = 0; status && (i < otp_close_nb); i++) { + otp_close = get_otp_close_state(i); + + if (!otp_close->close_status_ops) + continue; + + mask = otp_close->mask_rd; + word = otp_close->word; + + ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret < 0) + result = ret; + if (ret != 4) + val = 0x0; + + ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); + if (ret < 0) + result = ret; + if (ret != 4) + lock = BSEC_LOCK_ERROR; + + status = otp_close->close_status_ops(val, mask); + tested_once = true; + } + + if (!tested_once) + status = false; + if (closed) *closed = status; if (print) @@ -185,7 +327,49 @@ static int read_close_status(struct udevice *dev, bool print, bool *closed) return result; } -static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print) +static int write_close_status(struct udevice *dev) +{ + int i; + u32 val, word, ret; + const struct otp_close *otp_close = NULL; + u32 otp_num = get_otp_close_state_nb(); + + for (i = 0; i < otp_num; i++) { + otp_close = get_otp_close_state(i); + val = otp_close->mask_wr; + word = otp_close->word; + ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret != 4) { + log_err("Error: can't update OTP %d\n", word); + return ret; + } + } + return 0; +} + +static int post_process_oem_key2(struct udevice *dev) +{ + int ret; + u32 val; + + ret = misc_read(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4); + if (ret != 4) { + log_err("Error %d failed to read STM32MP25_OTP_BOOTROM_CONF8\n", ret); + return -EIO; + } + + val |= STM32_OTP_STM32MP25X_OEM_KEY2_EN; + ret = misc_write(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4); + if (ret != 4) { + log_err("Error %d failed to write OEM_KEY2_ENABLE\n", ret); + return -EIO; + } + + return 0; +} + +static int fuse_key_value(struct udevice *dev, const struct stm32key *key, unsigned long addr, + bool print) { u32 word, val; int i, ret; @@ -229,7 +413,7 @@ static int confirm_prog(void) static void display_key_info(const struct stm32key *key) { printf("%s : %s\n", key->name, key->desc); - printf("\tOTP%d..%d\n", key->start, key->start + key->size); + printf("\tOTP%d..%d\n", key->start, key->start + key->size - 1); } static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -272,7 +456,7 @@ static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *con { const struct stm32key *key; struct udevice *dev; - u32 addr; + unsigned long addr; int ret, i; int result; @@ -310,7 +494,7 @@ static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *con return CMD_RET_USAGE; key = get_key(stm32key_index); - printf("Read %s at 0x%08x\n", key->name, addr); + printf("Read %s at 0x%08x\n", key->name, (u32)addr); read_key_value(key, addr); return CMD_RET_SUCCESS; @@ -320,7 +504,7 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con { const struct stm32key *key = get_key(stm32key_index); struct udevice *dev; - u32 addr; + unsigned long addr; int ret; bool yes = false, lock; @@ -361,6 +545,13 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con if (fuse_key_value(dev, key, addr, !yes)) return CMD_RET_FAILURE; + if (key->post_process) { + if (key->post_process(dev)) { + printf("Error: %s for post process\n", key->name); + return CMD_RET_FAILURE; + } + } + printf("%s updated !\n", key->name); return CMD_RET_SUCCESS; @@ -371,7 +562,6 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co const struct stm32key *key; bool yes, lock, closed; struct udevice *dev; - u32 val; int ret; yes = false; @@ -407,12 +597,8 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co if (!yes && !confirm_prog()) return CMD_RET_FAILURE; - val = get_otp_close_mask(); - ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4); - if (ret != 4) { - printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID); + if (write_close_status(dev)) return CMD_RET_FAILURE; - } printf("Device is closed !\n"); @@ -432,3 +618,25 @@ U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text, U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read), U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse), U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close)); + +/* + * Check the "closed" state in product life cycle, when product secrets have + * been provisioned into the device, by SSP tools for example. + * On closed devices, authentication is mandatory. + */ +bool stm32mp_is_closed(void) +{ + struct udevice *dev; + bool closed; + int ret; + + ret = get_misc_dev(&dev); + if (ret) + return false; + + ret = read_close_status(dev, false, &closed); + if (ret) + return false; + + return closed; +} diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 589276282e4..490097e98be 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -27,6 +27,8 @@ config CMD_STM32PROG_USB config CMD_STM32PROG_SERIAL bool "support stm32prog over UART" depends on CMD_STM32PROG + imply DISABLE_CONSOLE + imply SILENT_CONSOLE default y help activate the command "stm32prog serial" for STM32MP soc family diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 353aecc09de..5b027fad048 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -13,6 +13,7 @@ #include <part.h> #include <tee.h> #include <asm/arch/stm32mp1_smc.h> +#include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <dm/device_compat.h> #include <dm/uclass.h> @@ -1156,7 +1157,8 @@ static int create_gpt_partitions(struct stm32prog_data *data) /* partition UUID */ uuid_bin = NULL; - if (!rootfs_found && !strcmp(part->name, "rootfs")) { + if (!rootfs_found && (!strcmp(part->name, "rootfs") || + !strcmp(part->name, "rootfs-a"))) { mmc_id = part->dev_id; rootfs_found = true; if (mmc_id < ARRAY_SIZE(uuid_mmc)) @@ -1357,7 +1359,7 @@ static int dfu_init_entities(struct stm32prog_data *data) alt_nb = 1; /* number of virtual = CMD*/ - if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && !stm32mp_is_closed()) { /* OTP_SIZE_SMC = 0 if SMC is not supported */ otp_size = OTP_SIZE_SMC; /* check if PTA BSEC is supported */ diff --git a/arch/arm/mach-stm32mp/include/mach/etzpc.h b/arch/arm/mach-stm32mp/include/mach/etzpc.h new file mode 100644 index 00000000000..fd697c3e2ac --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/etzpc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef MACH_ETZPC_H +#define MACH_ETZPC_H + +#include <linux/types.h> + +/** + * stm32_etzpc_check_access - Check ETZPC accesses for given device node + * + * @device_node Node of the device for which the accesses are checked + * + * @returns 0 on success (if access is granted), -EINVAL if access is denied. + * Else, returns an appropriate negative ERRNO value + */ +int stm32_etzpc_check_access(ofnode device_node); + +/** + * stm32_etzpc_check_access_by_id - Check ETZPC accesses for given id + * + * @device_node Node of the device to get a reference on ETZPC + * @id ID of the resource to check + * + * @returns 0 on success (if access is granted), -EINVAL if access is denied. + * Else, returns an appropriate negative ERRNO value + */ +int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id); + +#endif /* MACH_ETZPC_H*/ diff --git a/arch/arm/mach-stm32mp/include/mach/rif.h b/arch/arm/mach-stm32mp/include/mach/rif.h new file mode 100644 index 00000000000..10b22108120 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/rif.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef MACH_RIF_H +#define MACH_RIF_H + +#include <linux/types.h> + +/** + * stm32_rifsc_check_access - Check RIF accesses for given device node + * + * @device_node Node of the device for which the accesses are checked + */ +int stm32_rifsc_check_access(ofnode device_node); + +/** + * stm32_rifsc_check_access - Check RIF accesses for given id + * + * @device_node Node of the device to get a reference on RIFSC + * @id ID of the resource to check + */ +int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id); + +#endif /* MACH_RIF_H*/ diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 6eb85ba7233..a9ac49bc5d2 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -42,6 +42,9 @@ enum boot_device { BOOT_FLASH_SPINAND = 0x70, BOOT_FLASH_SPINAND_1 = 0x71, + + BOOT_FLASH_HYPERFLASH = 0x80, + BOOT_FLASH_HYPERFLASH_1 = 0x81 }; #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) @@ -158,8 +161,20 @@ enum forced_boot_mode { #endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ #ifdef CONFIG_STM32MP25X +#define STM32_USART2_BASE 0x400E0000 +#define STM32_USART3_BASE 0x400F0000 +#define STM32_UART4_BASE 0x40100000 +#define STM32_UART5_BASE 0x40110000 +#define STM32_USART6_BASE 0x40220000 +#define STM32_UART9_BASE 0x402C0000 +#define STM32_USART1_BASE 0x40330000 +#define STM32_UART7_BASE 0x40370000 +#define STM32_UART8_BASE 0x40380000 #define STM32_RCC_BASE 0x44200000 #define STM32_TAMP_BASE 0x46010000 +#define STM32_SDMMC1_BASE 0x48220000 +#define STM32_SDMMC2_BASE 0x48230000 +#define STM32_SDMMC3_BASE 0x48240000 #define STM32_DDR_BASE 0x80000000 @@ -197,6 +212,7 @@ enum forced_boot_mode { #ifdef CONFIG_STM32MP25X #define BSEC_OTP_SERIAL 5 #define BSEC_OTP_RPN 9 +#define BSEC_OTP_REVID 102 #define BSEC_OTP_PKG 122 #define BSEC_OTP_BOARD 246 #define BSEC_OTP_MAC 247 diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 2a65efc0a50..19073668497 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -58,6 +58,7 @@ u32 get_cpu_type(void); /* return CPU_DEV constants */ u32 get_cpu_dev(void); +/* Silicon revision = REV_ID[15:0] of Device Version */ #define CPU_REV1 0x1000 #define CPU_REV1_1 0x1001 #define CPU_REV1_2 0x1003 @@ -65,7 +66,15 @@ u32 get_cpu_dev(void); #define CPU_REV2_1 0x2001 #define CPU_REV2_2 0x2003 -/* return Silicon revision = REV_ID[15:0] of Device Version */ +/* OTP revision ID = 6 bits : 3 for Major / 3 for Minor */ +#define OTP_REVID_1 0b001000 +#define OTP_REVID_1_1 0b001001 +#define OTP_REVID_1_2 0b001010 +#define OTP_REVID_2 0b010000 +#define OTP_REVID_2_1 0b010001 +#define OTP_REVID_2_2 0b010010 + +/* return SoC revision = Silicon revision (STM32MP1) or OTP revision ID (STM32MP2)*/ u32 get_cpu_rev(void); /* Get Package options from OTP */ @@ -80,9 +89,9 @@ u32 get_cpu_package(void); /* package used for STM32MP25x */ #define STM32MP25_PKG_CUSTOM 0 -#define STM32MP25_PKG_AL_TBGA361 3 -#define STM32MP25_PKG_AK_TBGA424 4 -#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_AL_VFBGA361 1 +#define STM32MP25_PKG_AK_VFBGA424 3 +#define STM32MP25_PKG_AI_TFBGA436 5 #define STM32MP25_PKG_UNKNOWN 7 /* Get SOC name */ @@ -111,3 +120,10 @@ u32 get_otp(int index, int shift, int mask); uintptr_t get_stm32mp_rom_api_table(void); uintptr_t get_stm32mp_bl2_dtb(void); + +/* helper function: check "closed" state in product "Life Cycle" */ +#ifdef CONFIG_CMD_STM32KEY +bool stm32mp_is_closed(void); +#else +static inline bool stm32mp_is_closed(void) { return false; } +#endif diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index db160c24cbc..1f4ada3ac70 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -4,6 +4,7 @@ # obj-y += cpu.o +obj-y += etzpc.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o @@ -15,5 +16,5 @@ else obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_$(PHASE_)STM32MP15_PWR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/etzpc.c b/arch/arm/mach-stm32mp/stm32mp1/etzpc.c new file mode 100644 index 00000000000..7013bf97167 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/etzpc.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <dm.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/lists.h> +#include <linux/bitfield.h> +#include <mach/etzpc.h> + +/* ETZPC peripheral as firewall bus */ +/* ETZPC registers */ +#define ETZPC_DECPROT 0x10 +#define ETZPC_HWCFGR 0x3F0 + +/* ETZPC miscellaneous */ +#define ETZPC_PROT_MASK GENMASK(1, 0) +#define ETZPC_PROT_A7NS 0x3 +#define ETZPC_DECPROT_SHIFT 1 + +#define IDS_PER_DECPROT_REGS 16 + +#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8) +#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16) + +/* + * struct stm32_etzpc_plat: Information about ETZPC device + * + * @base: Base address of ETZPC + * @max_entries: Number of securable peripherals in ETZPC + */ +struct stm32_etzpc_plat { + void *base; + unsigned int max_entries; +}; + +static int etzpc_parse_feature_domain(ofnode node, struct ofnode_phandle_args *args) +{ + int ret; + + ret = ofnode_parse_phandle_with_args(node, "access-controllers", + "#access-controller-cells", 0, + 0, args); + if (ret) { + log_debug("failed to parse access-controller (%d)\n", ret); + return ret; + } + + if (args->args_count != 1) { + log_debug("invalid domain args_count: %d\n", args->args_count); + return -EINVAL; + } + + return 0; +} + +static int etzpc_check_access(void *base, u32 id) +{ + u32 reg_offset, offset, sec_val; + + /* Check access configuration, 16 peripherals per register */ + reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS); + offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT; + + /* Verify peripheral is non-secure and attributed to cortex A7 */ + sec_val = (readl(base + reg_offset) >> offset) & ETZPC_PROT_MASK; + if (sec_val != ETZPC_PROT_A7NS) { + log_debug("Invalid bus configuration: reg_offset %#x, value %d\n", + reg_offset, sec_val); + return -EACCES; + } + + return 0; +} + +int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id) +{ + struct stm32_etzpc_plat *plat; + struct ofnode_phandle_args args; + struct udevice *dev; + int err; + + err = etzpc_parse_feature_domain(device_node, &args); + if (err) + return err; + + if (id == -1U) + id = args.args[0]; + + err = uclass_get_device_by_ofnode(UCLASS_NOP, args.node, &dev); + if (err || dev->driver != DM_DRIVER_GET(stm32_etzpc)) { + log_err("No device found\n"); + return -EINVAL; + } + + plat = dev_get_plat(dev); + + if (id >= plat->max_entries) { + dev_err(dev, "Invalid sys bus ID for %s\n", ofnode_get_name(device_node)); + return -EINVAL; + } + + return etzpc_check_access(plat->base, id); +} + +int stm32_etzpc_check_access(ofnode device_node) +{ + return stm32_etzpc_check_access_by_id(device_node, -1U); +} + +static int stm32_etzpc_bind(struct udevice *dev) +{ + struct stm32_etzpc_plat *plat = dev_get_plat(dev); + struct ofnode_phandle_args args; + u32 nb_per, nb_master; + int ret = 0, err = 0; + ofnode node, parent; + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get registers base address\n"); + return -ENOENT; + } + + /* Get number of etzpc entries*/ + nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC, + readl(plat->base + ETZPC_HWCFGR)); + nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC, + readl(plat->base + ETZPC_HWCFGR)); + plat->max_entries = nb_per + nb_master; + + parent = dev_ofnode(dev); + for (node = ofnode_first_subnode(parent); + ofnode_valid(node); + node = ofnode_next_subnode(node)) { + const char *node_name = ofnode_get_name(node); + + if (!ofnode_is_enabled(node)) + continue; + + err = etzpc_parse_feature_domain(node, &args); + if (err) { + dev_err(dev, "%s failed to parse child on bus (%d)\n", node_name, err); + continue; + } + + if (!ofnode_equal(args.node, parent)) { + dev_err(dev, "%s phandle to %s\n", + node_name, ofnode_get_name(args.node)); + continue; + } + + if (args.args[0] >= plat->max_entries) { + dev_err(dev, "Invalid sys bus ID for %s\n", node_name); + return -EINVAL; + } + + err = etzpc_check_access(plat->base, args.args[0]); + if (err) { + dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err); + continue; + } + + err = lists_bind_fdt(dev, node, NULL, NULL, + gd->flags & GD_FLG_RELOC ? false : true); + if (err) { + ret = err; + dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret); + } + } + + if (ret) + dev_err(dev, "Some child failed to bind (%d)\n", ret); + + return ret; +} + +static const struct udevice_id stm32_etzpc_ids[] = { + { .compatible = "st,stm32-etzpc" }, + {}, +}; + +U_BOOT_DRIVER(stm32_etzpc) = { + .name = "stm32_etzpc", + .id = UCLASS_NOP, + .of_match = stm32_etzpc_ids, + .bind = stm32_etzpc_bind, + .plat_auto = sizeof(struct stm32_etzpc_plat), +}; diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c index e1e4dc04e01..72474fa73f6 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c @@ -14,20 +14,6 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <linux/io.h> -#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n)) -#define ETZPC_DECPROT_NB 6 - -#define DECPROT_MASK 0x03 -#define NB_PROT_PER_REG 0x10 -#define DECPROT_NB_BITS 2 - -#define DECPROT_SECURED 0x00 -#define DECPROT_WRITE_SECURE 0x01 -#define DECPROT_MCU_ISOLATION 0x02 -#define DECPROT_NON_SECURED 0x03 - -#define ETZPC_RESERVED 0xffffffff - #define STM32MP13_FDCAN_BASE 0x4400F000 #define STM32MP13_ADC1_BASE 0x48003000 #define STM32MP13_TSC_BASE 0x5000B000 @@ -42,204 +28,6 @@ #define STM32MP15_GPU_BASE 0x59000000 #define STM32MP15_DSI_BASE 0x5a000000 -static const u32 stm32mp13_ip_addr[] = { - 0x50025000, /* 0 VREFBUF APB3 */ - 0x50021000, /* 1 LPTIM2 APB3 */ - 0x50022000, /* 2 LPTIM3 APB3 */ - STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ - STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ - 0x5A006000, /* 5 USBPHYCTRL APB4 */ - 0x5A003000, /* 6 DDRCTRLPHY APB4 */ - ETZPC_RESERVED, /* 7 Reserved*/ - ETZPC_RESERVED, /* 8 Reserved*/ - ETZPC_RESERVED, /* 9 Reserved*/ - 0x5C006000, /* 10 TZC APB5 */ - 0x58001000, /* 11 MCE APB5 */ - 0x5C000000, /* 12 IWDG1 APB5 */ - 0x5C008000, /* 13 STGENC APB5 */ - ETZPC_RESERVED, /* 14 Reserved*/ - ETZPC_RESERVED, /* 15 Reserved*/ - 0x4C000000, /* 16 USART1 APB6 */ - 0x4C001000, /* 17 USART2 APB6 */ - 0x4C002000, /* 18 SPI4 APB6 */ - 0x4C003000, /* 19 SPI5 APB6 */ - 0x4C004000, /* 20 I2C3 APB6 */ - 0x4C005000, /* 21 I2C4 APB6 */ - 0x4C006000, /* 22 I2C5 APB6 */ - 0x4C007000, /* 23 TIM12 APB6 */ - 0x4C008000, /* 24 TIM13 APB6 */ - 0x4C009000, /* 25 TIM14 APB6 */ - 0x4C00A000, /* 26 TIM15 APB6 */ - 0x4C00B000, /* 27 TIM16 APB6 */ - 0x4C00C000, /* 28 TIM17 APB6 */ - ETZPC_RESERVED, /* 29 Reserved*/ - ETZPC_RESERVED, /* 30 Reserved*/ - ETZPC_RESERVED, /* 31 Reserved*/ - STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ - 0x48004000, /* 33 ADC2 AHB2 */ - 0x49000000, /* 34 OTG AHB2 */ - ETZPC_RESERVED, /* 35 Reserved*/ - ETZPC_RESERVED, /* 36 Reserved*/ - STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ - ETZPC_RESERVED, /* 38 Reserved*/ - ETZPC_RESERVED, /* 39 Reserved*/ - 0x54004000, /* 40 RNG AHB5 */ - 0x54003000, /* 41 HASH AHB5 */ - STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ - 0x54005000, /* 43 SAES AHB5 */ - 0x54006000, /* 44 PKA AHB5 */ - 0x54000000, /* 45 BKPSRAM AHB5 */ - ETZPC_RESERVED, /* 46 Reserved*/ - ETZPC_RESERVED, /* 47 Reserved*/ - 0x5800A000, /* 48 ETH1 AHB6 */ - STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ - 0x58005000, /* 50 SDMMC1 AHB6 */ - 0x58007000, /* 51 SDMMC2 AHB6 */ - ETZPC_RESERVED, /* 52 Reserved*/ - ETZPC_RESERVED, /* 53 Reserved*/ - 0x58002000, /* 54 FMC AHB6 */ - 0x58003000, /* 55 QSPI AHB6 */ - ETZPC_RESERVED, /* 56 Reserved*/ - ETZPC_RESERVED, /* 57 Reserved*/ - ETZPC_RESERVED, /* 58 Reserved*/ - ETZPC_RESERVED, /* 59 Reserved*/ - 0x30000000, /* 60 SRAM1 MLAHB */ - 0x30004000, /* 61 SRAM2 MLAHB */ - 0x30006000, /* 62 SRAM3 MLAHB */ - ETZPC_RESERVED, /* 63 Reserved*/ - ETZPC_RESERVED, /* 64 Reserved*/ - ETZPC_RESERVED, /* 65 Reserved*/ - ETZPC_RESERVED, /* 66 Reserved*/ - ETZPC_RESERVED, /* 67 Reserved*/ - ETZPC_RESERVED, /* 68 Reserved*/ - ETZPC_RESERVED, /* 69 Reserved*/ - ETZPC_RESERVED, /* 70 Reserved*/ - ETZPC_RESERVED, /* 71 Reserved*/ - ETZPC_RESERVED, /* 72 Reserved*/ - ETZPC_RESERVED, /* 73 Reserved*/ - ETZPC_RESERVED, /* 74 Reserved*/ - ETZPC_RESERVED, /* 75 Reserved*/ - ETZPC_RESERVED, /* 76 Reserved*/ - ETZPC_RESERVED, /* 77 Reserved*/ - ETZPC_RESERVED, /* 78 Reserved*/ - ETZPC_RESERVED, /* 79 Reserved*/ - ETZPC_RESERVED, /* 80 Reserved*/ - ETZPC_RESERVED, /* 81 Reserved*/ - ETZPC_RESERVED, /* 82 Reserved*/ - ETZPC_RESERVED, /* 83 Reserved*/ - ETZPC_RESERVED, /* 84 Reserved*/ - ETZPC_RESERVED, /* 85 Reserved*/ - ETZPC_RESERVED, /* 86 Reserved*/ - ETZPC_RESERVED, /* 87 Reserved*/ - ETZPC_RESERVED, /* 88 Reserved*/ - ETZPC_RESERVED, /* 89 Reserved*/ - ETZPC_RESERVED, /* 90 Reserved*/ - ETZPC_RESERVED, /* 91 Reserved*/ - ETZPC_RESERVED, /* 92 Reserved*/ - ETZPC_RESERVED, /* 93 Reserved*/ - ETZPC_RESERVED, /* 94 Reserved*/ - ETZPC_RESERVED, /* 95 Reserved*/ -}; - -static const u32 stm32mp15_ip_addr[] = { - 0x5c008000, /* 00 stgenc */ - 0x54000000, /* 01 bkpsram */ - 0x5c003000, /* 02 iwdg1 */ - 0x5c000000, /* 03 usart1 */ - 0x5c001000, /* 04 spi6 */ - 0x5c002000, /* 05 i2c4 */ - ETZPC_RESERVED, /* 06 reserved */ - 0x54003000, /* 07 rng1 */ - 0x54002000, /* 08 hash1 */ - STM32MP15_CRYP1_BASE, /* 09 cryp1 */ - 0x5a003000, /* 0A ddrctrl */ - 0x5a004000, /* 0B ddrphyc */ - 0x5c009000, /* 0C i2c6 */ - ETZPC_RESERVED, /* 0D reserved */ - ETZPC_RESERVED, /* 0E reserved */ - ETZPC_RESERVED, /* 0F reserved */ - 0x40000000, /* 10 tim2 */ - 0x40001000, /* 11 tim3 */ - 0x40002000, /* 12 tim4 */ - 0x40003000, /* 13 tim5 */ - 0x40004000, /* 14 tim6 */ - 0x40005000, /* 15 tim7 */ - 0x40006000, /* 16 tim12 */ - 0x40007000, /* 17 tim13 */ - 0x40008000, /* 18 tim14 */ - 0x40009000, /* 19 lptim1 */ - 0x4000a000, /* 1A wwdg1 */ - 0x4000b000, /* 1B spi2 */ - 0x4000c000, /* 1C spi3 */ - 0x4000d000, /* 1D spdifrx */ - 0x4000e000, /* 1E usart2 */ - 0x4000f000, /* 1F usart3 */ - 0x40010000, /* 20 uart4 */ - 0x40011000, /* 21 uart5 */ - 0x40012000, /* 22 i2c1 */ - 0x40013000, /* 23 i2c2 */ - 0x40014000, /* 24 i2c3 */ - 0x40015000, /* 25 i2c5 */ - 0x40016000, /* 26 cec */ - 0x40017000, /* 27 dac */ - 0x40018000, /* 28 uart7 */ - 0x40019000, /* 29 uart8 */ - ETZPC_RESERVED, /* 2A reserved */ - ETZPC_RESERVED, /* 2B reserved */ - 0x4001c000, /* 2C mdios */ - ETZPC_RESERVED, /* 2D reserved */ - ETZPC_RESERVED, /* 2E reserved */ - ETZPC_RESERVED, /* 2F reserved */ - 0x44000000, /* 30 tim1 */ - 0x44001000, /* 31 tim8 */ - ETZPC_RESERVED, /* 32 reserved */ - 0x44003000, /* 33 usart6 */ - 0x44004000, /* 34 spi1 */ - 0x44005000, /* 35 spi4 */ - 0x44006000, /* 36 tim15 */ - 0x44007000, /* 37 tim16 */ - 0x44008000, /* 38 tim17 */ - 0x44009000, /* 39 spi5 */ - 0x4400a000, /* 3A sai1 */ - 0x4400b000, /* 3B sai2 */ - 0x4400c000, /* 3C sai3 */ - 0x4400d000, /* 3D dfsdm */ - STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ - ETZPC_RESERVED, /* 3F reserved */ - 0x50021000, /* 40 lptim2 */ - 0x50022000, /* 41 lptim3 */ - 0x50023000, /* 42 lptim4 */ - 0x50024000, /* 43 lptim5 */ - 0x50027000, /* 44 sai4 */ - 0x50025000, /* 45 vrefbuf */ - 0x4c006000, /* 46 dcmi */ - 0x4c004000, /* 47 crc2 */ - 0x48003000, /* 48 adc */ - 0x4c002000, /* 49 hash2 */ - 0x4c003000, /* 4A rng2 */ - STM32MP15_CRYP2_BASE, /* 4B cryp2 */ - ETZPC_RESERVED, /* 4C reserved */ - ETZPC_RESERVED, /* 4D reserved */ - ETZPC_RESERVED, /* 4E reserved */ - ETZPC_RESERVED, /* 4F reserved */ - ETZPC_RESERVED, /* 50 sram1 */ - ETZPC_RESERVED, /* 51 sram2 */ - ETZPC_RESERVED, /* 52 sram3 */ - ETZPC_RESERVED, /* 53 sram4 */ - ETZPC_RESERVED, /* 54 retram */ - 0x49000000, /* 55 otg */ - 0x48004000, /* 56 sdmmc3 */ - 0x48005000, /* 57 dlybsd3 */ - 0x48000000, /* 58 dma1 */ - 0x48001000, /* 59 dma2 */ - 0x48002000, /* 5A dmamux */ - 0x58002000, /* 5B fmc */ - 0x58003000, /* 5C qspi */ - 0x58004000, /* 5D dlybq */ - 0x5800a000, /* 5E eth */ - ETZPC_RESERVED, /* 5F reserved */ -}; - /* fdt helper */ static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) { @@ -263,46 +51,6 @@ static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) return false; } -static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) -{ - const u32 *array; - int array_size, i; - int offset, shift; - u32 addr, status, decprot[ETZPC_DECPROT_NB]; - - if (IS_ENABLED(CONFIG_STM32MP13X)) { - array = stm32mp13_ip_addr; - array_size = ARRAY_SIZE(stm32mp13_ip_addr); - } - - if (IS_ENABLED(CONFIG_STM32MP15X)) { - array = stm32mp15_ip_addr; - array_size = ARRAY_SIZE(stm32mp15_ip_addr); - } - - for (i = 0; i < ETZPC_DECPROT_NB; i++) - decprot[i] = readl(ETZPC_DECPROT(i)); - - for (i = 0; i < array_size; i++) { - offset = i / NB_PROT_PER_REG; - shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; - status = (decprot[offset] >> shift) & DECPROT_MASK; - addr = array[i]; - - log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status); - - if (addr == ETZPC_RESERVED || - status == DECPROT_NON_SECURED) - continue; - - if (fdt_disable_subnode_by_address(fdt, soc_node, addr)) - log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n", - addr, i, status); - } - - return 0; -} - /* deactivate all the cpu except core 0 */ static void stm32_fdt_fixup_cpu(void *blob, char *name) { @@ -481,12 +229,6 @@ int ft_system_setup(void *blob, struct bd_info *bd) if (soc < 0) return soc; - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { - ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; - } - /* MPUs Part Numbers and name*/ cpu = get_cpu_type(); get_soc_name(name); diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile index b579ce5a800..5dbf75daa76 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -5,5 +5,6 @@ obj-y += cpu.o obj-y += arm64-mmu.o +obj-y += rifsc.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c index 9530aa8534b..c3b87d7f981 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -24,7 +24,7 @@ * early TLB into the .data section so that it not get cleared * with 16kB alignment */ -#define EARLY_TLB_SIZE 0xA000 +#define EARLY_TLB_SIZE 0x10000 u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); /* @@ -55,6 +55,19 @@ int arch_cpu_init(void) return 0; } +int mach_cpu_init(void) +{ + u32 boot_mode; + + boot_mode = get_bootmode(); + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && + (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + + return 0; +} + void enable_caches(void) { /* deactivate the data cache, early enabled in arch_cpu_init() */ @@ -67,14 +80,6 @@ void enable_caches(void) dcache_enable(); } -int arch_misc_init(void) -{ - setup_serial_number(); - setup_mac_address(); - - return 0; -} - /* * Force data-section, as .bss will not be valid * when save_boot_params is invoked. @@ -97,3 +102,150 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, save_boot_params_ret(); } + +u32 get_bootmode(void) +{ + /* read bootmode from TAMP backup register */ + return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> + TAMP_BOOT_MODE_SHIFT; +} + +static void setup_boot_mode(void) +{ + const u32 serial_addr[] = { + STM32_USART1_BASE, + STM32_USART2_BASE, + STM32_USART3_BASE, + STM32_UART4_BASE, + STM32_UART5_BASE, + STM32_USART6_BASE, + STM32_UART7_BASE, + STM32_UART8_BASE, + STM32_UART9_BASE + }; + const u32 sdmmc_addr[] = { + STM32_SDMMC1_BASE, + STM32_SDMMC2_BASE, + STM32_SDMMC3_BASE + }; + char cmd[60]; + u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); + u32 boot_mode = + (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; + unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); + struct udevice *dev; + + log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", + __func__, boot_ctx, boot_mode, instance, forced_mode); + switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_SERIAL_UART: + if (instance > ARRAY_SIZE(serial_addr)) + break; + /* serial : search associated node in devicetree */ + sprintf(cmd, "serial@%x", serial_addr[instance]); + if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { + /* restore console on error */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_err("uart%d = %s not found in device tree!\n", + instance + 1, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "serial"); + env_set("boot_instance", cmd); + + /* restore console on uart when not used */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_info("serial boot with console enabled!\n"); + } + break; + case BOOT_SERIAL_USB: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + if (instance > ARRAY_SIZE(sdmmc_addr)) + break; + /* search associated sdmmc node in devicetree */ + sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); + if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { + printf("mmc%d = %s not found in device tree!\n", + instance, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "mmc"); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_NAND: + env_set("boot_device", "nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SPINAND: + env_set("boot_device", "spi-nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_NOR: + env_set("boot_device", "nor"); + if (IS_ENABLED(CONFIG_SYS_MAX_FLASH_BANKS)) + sprintf(cmd, "%d", CONFIG_SYS_MAX_FLASH_BANKS); + else + sprintf(cmd, "%d", 0); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_HYPERFLASH: + env_set("boot_device", "nor"); + env_set("boot_instance", "0"); + break; + default: + env_set("boot_device", "invalid"); + env_set("boot_instance", ""); + log_err("unexpected boot mode = %x\n", boot_mode); + break; + } + + switch (forced_mode) { + case BOOT_FASTBOOT: + log_info("Enter fastboot!\n"); + env_set("preboot", "env set preboot; fastboot 0"); + break; + case BOOT_STM32PROG: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_UMS_MMC0: + case BOOT_UMS_MMC1: + case BOOT_UMS_MMC2: + log_info("Enter UMS!\n"); + instance = forced_mode - BOOT_UMS_MMC0; + sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); + env_set("preboot", cmd); + break; + case BOOT_RECOVERY: + env_set("preboot", "env set preboot; run altbootcmd"); + break; + case BOOT_NORMAL: + break; + default: + log_debug("unexpected forced boot mode = %x\n", forced_mode); + break; + } + + /* clear TAMP for next reboot */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); +} + +int arch_misc_init(void) +{ + setup_boot_mode(); + setup_serial_number(); + setup_mac_address(); + + return 0; +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c new file mode 100644 index 00000000000..50dececf77b --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <dm.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/lists.h> +#include <linux/bitfield.h> +#include <mach/rif.h> + +/* RIFSC offset register */ +#define RIFSC_RISC_SECCFGR0(id) (0x10 + 0x4 * (id)) +#define RIFSC_RISC_PER0_CIDCFGR(id) (0x100 + 0x8 * (id)) +#define RIFSC_RISC_PER0_SEMCR(id) (0x104 + 0x8 * (id)) + +/* + * SEMCR register + */ +#define SEMCR_MUTEX BIT(0) + +/* RIFSC miscellaneous */ +#define RIFSC_RISC_SCID_MASK GENMASK(6, 4) +#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) + +#define IDS_PER_RISC_SEC_PRIV_REGS 32 + +/* + * CIDCFGR register fields + */ +#define CIDCFGR_CFEN BIT(0) +#define CIDCFGR_SEMEN BIT(1) + +#define SEMWL_SHIFT 16 + +#define STM32MP25_RIFSC_ENTRIES 178 + +/* Compartiment IDs */ +#define RIF_CID0 0x0 +#define RIF_CID1 0x1 + +/* + * struct stm32_rifsc_plat: Information about RIFSC device + * + * @base: Base address of RIFSC + */ +struct stm32_rifsc_plat { + void *base; +}; + +/* + * struct stm32_rifsc_child_plat: Information about each child + * + * @domain_id: Domain id + */ +struct stm32_rifsc_child_plat { + u32 domain_id; +}; + +static bool stm32_rif_is_semaphore_available(void *base, u32 id) +{ + void *addr = base + RIFSC_RISC_PER0_SEMCR(id); + + return !(readl(addr) & SEMCR_MUTEX); +} + +static int stm32_rif_acquire_semaphore(void *base, u32 id) +{ + void *addr = base + RIFSC_RISC_PER0_SEMCR(id); + + /* Check that the semaphore is available */ + if (!stm32_rif_is_semaphore_available(base, id)) + return -EACCES; + + setbits_le32(addr, SEMCR_MUTEX); + + /* Check that CID1 has the semaphore */ + if (stm32_rif_is_semaphore_available(base, id) || + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) + return -EACCES; + + return 0; +} + +static int stm32_rif_release_semaphore(void *base, u32 id) +{ + void *addr = base + RIFSC_RISC_PER0_SEMCR(id); + + if (stm32_rif_is_semaphore_available(base, id)) + return 0; + + clrbits_le32(addr, SEMCR_MUTEX); + + /* Ok if another compartment takes the semaphore before the check */ + if (!stm32_rif_is_semaphore_available(base, id) && + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1)) + return -EACCES; + + return 0; +} + +static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args) +{ + int ret; + + ret = ofnode_parse_phandle_with_args(node, "access-controllers", + "#access-controller-cells", 0, + 0, args); + if (ret) { + log_debug("failed to parse access-controller (%d)\n", ret); + return ret; + } + + if (args->args_count != 1) { + log_debug("invalid domain args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args[0] >= STM32MP25_RIFSC_ENTRIES) { + log_err("Invalid sys bus ID for %s\n", ofnode_get_name(node)); + return -EINVAL; + } + + return 0; +} + +static int rifsc_check_access(void *base, u32 id) +{ + u32 reg_offset, reg_id, sec_reg_value, cid_reg_value, sem_reg_value; + + /* + * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for + * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register + * per peripheral + */ + reg_id = id / IDS_PER_RISC_SEC_PRIV_REGS; + reg_offset = id % IDS_PER_RISC_SEC_PRIV_REGS; + sec_reg_value = readl(base + RIFSC_RISC_SECCFGR0(reg_id)); + cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id)); + sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id)); + + /* + * First check conditions for semaphore mode, which doesn't take into + * account static CID. + */ + if (cid_reg_value & CIDCFGR_SEMEN) + goto skip_cid_check; + + /* + * Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which + * corresponds to whatever CID. + */ + if (!(cid_reg_value & CIDCFGR_CFEN) || + FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0) + goto skip_cid_check; + + /* Coherency check with the CID configuration */ + if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { + log_debug("Invalid CID configuration for peripheral %d\n", id); + return -EACCES; + } + + /* Check semaphore accesses */ + if (cid_reg_value & CIDCFGR_SEMEN) { + if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + log_debug("Not in semaphore whitelist for peripheral %d\n", id); + return -EACCES; + } + if (!stm32_rif_is_semaphore_available(base, id) && + !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) { + log_debug("Semaphore unavailable for peripheral %d\n", id); + return -EACCES; + } + } + +skip_cid_check: + /* Check security configuration */ + if (sec_reg_value & BIT(reg_offset)) { + log_debug("Invalid security configuration for peripheral %d\n", id); + return -EACCES; + } + + return 0; +} + +int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id) +{ + struct ofnode_phandle_args args; + int err; + + if (id >= STM32MP25_RIFSC_ENTRIES) + return -EINVAL; + + err = rifsc_parse_access_controller(device_node, &args); + if (err) + return err; + + return rifsc_check_access((void *)ofnode_get_addr(args.node), id); +} + +int stm32_rifsc_check_access(ofnode device_node) +{ + struct ofnode_phandle_args args; + int err; + + err = rifsc_parse_access_controller(device_node, &args); + if (err) + return err; + + return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]); +} + +static int stm32_rifsc_child_pre_probe(struct udevice *dev) +{ + struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + u32 cid_reg_value; + int err; + u32 id = child_plat->domain_id; + + cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if (cid_reg_value & CIDCFGR_SEMEN && + (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + err = stm32_rif_acquire_semaphore(plat->base, id); + if (err) { + dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n", + id, err); + return err; + } + dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id); + } + + return 0; +} + +static int stm32_rifsc_child_post_remove(struct udevice *dev) +{ + struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + u32 cid_reg_value; + int err; + u32 id = child_plat->domain_id; + + cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* + * If the peripheral is in semaphore mode, release the semaphore so that + * there's no ownership. + */ + if (cid_reg_value & CIDCFGR_SEMEN && + (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + err = stm32_rif_release_semaphore(plat->base, id); + if (err) + dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n", + id, err); + } + + return 0; +} + +static int stm32_rifsc_child_post_bind(struct udevice *dev) +{ + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + struct ofnode_phandle_args args; + int ret; + + if (!dev_has_ofnode(dev)) + return -EPERM; + + ret = rifsc_parse_access_controller(dev_ofnode(dev), &args); + if (ret) + return ret; + + child_plat->domain_id = args.args[0]; + + return 0; +} + +static int stm32_rifsc_bind(struct udevice *dev) +{ + struct stm32_rifsc_plat *plat = dev_get_plat(dev); + struct ofnode_phandle_args args; + int ret = 0, err = 0; + ofnode node; + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get registers base address\n"); + return -ENOENT; + } + + for (node = ofnode_first_subnode(dev_ofnode(dev)); + ofnode_valid(node); + node = ofnode_next_subnode(node)) { + const char *node_name = ofnode_get_name(node); + + if (!ofnode_is_enabled(node)) + continue; + + err = rifsc_parse_access_controller(node, &args); + if (err) { + dev_dbg(dev, "%s failed to parse child on bus (%d)\n", node_name, err); + continue; + } + + err = rifsc_check_access(plat->base, args.args[0]); + if (err) { + dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err); + continue; + } + + err = lists_bind_fdt(dev, node, NULL, NULL, + gd->flags & GD_FLG_RELOC ? false : true); + if (err && !ret) { + ret = err; + dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret); + } + } + + if (ret) + dev_err(dev, "Some child failed to bind (%d)\n", ret); + + return ret; +} + +static int stm32_rifsc_remove(struct udevice *bus) +{ + struct udevice *dev; + + /* Deactivate all child devices not yet removed */ + for (device_find_first_child(bus, &dev); dev; device_find_next_child(&dev)) + if (device_active(dev)) + stm32_rifsc_child_post_remove(dev); + + return 0; +} + +static const struct udevice_id stm32_rifsc_ids[] = { + { .compatible = "st,stm32mp25-rifsc" }, + {}, +}; + +U_BOOT_DRIVER(stm32_rifsc) = { + .name = "stm32_rifsc", + .id = UCLASS_NOP, + .of_match = stm32_rifsc_ids, + .bind = stm32_rifsc_bind, + .remove = stm32_rifsc_remove, + .child_post_bind = stm32_rifsc_child_post_bind, + .child_pre_probe = stm32_rifsc_child_pre_probe, + .child_post_remove = stm32_rifsc_child_post_remove, + .plat_auto = sizeof(struct stm32_rifsc_plat), + .per_child_plat_auto = sizeof(struct stm32_rifsc_child_plat), + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c index 7f896a0d65d..12b43ea5cdf 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -15,8 +15,10 @@ #define SYSCFG_DEVICEID_OFFSET 0x6400 #define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) #define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 -#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) -#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ +#define REVID_SHIFT 0 +#define REVID_MASK GENMASK(5, 0) /* Device Part Number (RPN) = OTP9 */ #define RPN_SHIFT 0 @@ -24,8 +26,8 @@ /* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines * - 000: Custom package - * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm - * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 011: VFBGA424 => AK = 14x14, 424 balls pith 0.5mm * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm * - others: Reserved */ @@ -46,7 +48,7 @@ u32 get_cpu_dev(void) u32 get_cpu_rev(void) { - return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; + return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); } /* Get Device Part Number (RPN) from OTP */ @@ -164,12 +166,21 @@ void get_soc_name(char name[SOC_NAME_SIZE]) } /* REVISION */ switch (get_cpu_rev()) { - case CPU_REV1: + case OTP_REVID_1: cpu_r = "A"; break; - case CPU_REV2: + case OTP_REVID_1_1: + cpu_r = "Z"; + break; + case OTP_REVID_2: cpu_r = "B"; break; + case OTP_REVID_2_1: + cpu_r = "Y"; + break; + case OTP_REVID_2_2: + cpu_r = "X"; + break; default: break; } @@ -178,13 +189,13 @@ void get_soc_name(char name[SOC_NAME_SIZE]) case STM32MP25_PKG_CUSTOM: package = "XX"; break; - case STM32MP25_PKG_AL_TBGA361: + case STM32MP25_PKG_AL_VFBGA361: package = "AL"; break; - case STM32MP25_PKG_AK_TBGA424: + case STM32MP25_PKG_AK_VFBGA424: package = "AK"; break; - case STM32MP25_PKG_AI_TBGA436: + case STM32MP25_PKG_AI_TFBGA436: package = "AI"; break; default: diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ab432390d3c..fce817c9d40 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -782,49 +782,6 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. -config USB0_VBUS_PIN - string "Vbus enable pin for usb0 (otg)" - default "" - ---help--- - Set the Vbus enable pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB0_VBUS_DET - string "Vbus detect pin for usb0 (otg)" - default "" - ---help--- - Set the Vbus detect pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB0_ID_DET - string "ID detect pin for usb0 (otg)" - default "" - ---help--- - Set the ID detect pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB1_VBUS_PIN - string "Vbus enable pin for usb1 (ehci0)" - default "PH6" if MACH_SUN4I || MACH_SUN7I - default "PH27" if MACH_SUN6I - ---help--- - Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes - a string in the format understood by sunxi_name_to_gpio, e.g. - PH1 for pin 1 of port H. - -config USB2_VBUS_PIN - string "Vbus enable pin for usb2 (ehci1)" - default "PH3" if MACH_SUN4I || MACH_SUN7I - default "PH24" if MACH_SUN6I - ---help--- - See USB1_VBUS_PIN help text. - -config USB3_VBUS_PIN - string "Vbus enable pin for usb3 (ehci2)" - default "" - ---help--- - See USB1_VBUS_PIN help text. - config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index eb6a49119a1..a33cd5b0f07 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -41,8 +41,8 @@ obj-$(CONFIG_DRAM_SUN9I) += dram_sun9i.o obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ -obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o +obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/ -obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o +obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/ endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 701899ee4b2..b1bf51f40c5 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -35,6 +35,9 @@ struct fel_stash { uint32_t cpsr; uint32_t sctlr; uint32_t vbar; + uint32_t sp_irq; + uint32_t icc_pmr; + uint32_t icc_igrpen1; }; struct fel_stash fel_stash __section(".data"); diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 359513d1669..4c522f60810 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -6,86 +6,83 @@ #ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { /* this seems to enable PLLs on H616 */ - setbits_le32(&prcm->sys_pwroff_gating, 0x10); - setbits_le32(&prcm->res_cal_ctrl, 2); + setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 2); } if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { - clrbits_le32(&prcm->res_cal_ctrl, 1); - setbits_le32(&prcm->res_cal_ctrl, 1); + clrbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); } if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { /* set key field for ldo enable */ - setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000); + setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0xA7000000); /* set PLL VDD LDO output to 1.14 V */ - setbits_le32(&prcm->pll_ldo_cfg, 0x60000); + setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0x60000); } clock_set_pll1(408000000); - writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); - while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) + writel(CCM_PLL6_DEFAULT, ccm + CCU_H6_PLL6_CFG); + while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL6_LOCK)) ; - clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, + clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG, + CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, CCM_CPU_AXI_DEFAULT_FACTORS); - writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); + writel(CCM_PSI_AHB1_AHB2_DEFAULT, ccm + CCU_H6_PSI_AHB1_AHB2_CFG); #ifdef CCM_AHB3_DEFAULT - writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); + writel(CCM_AHB3_DEFAULT, ccm + CCU_H6_AHB3_CFG); #endif - writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); + writel(CCM_APB1_DEFAULT, ccm + CCU_H6_APB1_CFG); /* * The mux and factor are set, but the clock will be enabled in * DRAM initialization code. */ - writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); + writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), ccm + CCU_H6_MBUS_CFG); } void clock_init_uart(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| APB2_CLK_RATE_M(1), - &ccm->apb2_cfg); + ccm + CCU_H6_APB2_CFG); /* open the clock for uart */ - setbits_le32(&ccm->uart_gate_reset, + setbits_le32(ccm + CCU_H6_UART_GATE_RESET, 1 << (CONFIG_CONS_INDEX - 1)); /* deassert uart reset */ - setbits_le32(&ccm->uart_gate_reset, + setbits_le32(ccm + CCU_H6_UART_GATE_RESET, 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } void clock_set_pll1(unsigned int clk) { - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; u32 val; /* Do not support clocks < 288MHz as they need factor P */ if (clk < 288000000) clk = 288000000; /* Switch to 24MHz clock while changing PLL1 */ - val = readl(&ccm->cpu_axi_cfg); + val = readl(ccm + CCU_H6_CPU_AXI_CFG); val &= ~CCM_CPU_AXI_MUX_MASK; val |= CCM_CPU_AXI_MUX_OSC24M; - writel(val, &ccm->cpu_axi_cfg); + writel(val, ccm + CCU_H6_CPU_AXI_CFG); /* clk = 24*n/p, p is ignored if clock is >288MHz */ val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2; @@ -94,22 +91,20 @@ void clock_set_pll1(unsigned int clk) val |= CCM_PLL1_OUT_EN; if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN; - writel(val, &ccm->pll1_cfg); - while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} + writel(val, ccm + CCU_H6_PLL1_CFG); + while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL1_LOCK)) {} /* Switch CPU to PLL1 */ - val = readl(&ccm->cpu_axi_cfg); + val = readl(ccm + CCU_H6_CPU_AXI_CFG); val &= ~CCM_CPU_AXI_MUX_MASK; val |= CCM_CPU_AXI_MUX_PLL_CPUX; - writel(val, &ccm->cpu_axi_cfg); + writel(val, ccm + CCU_H6_CPU_AXI_CFG); } int clock_twi_onoff(int port, int state) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; u32 value, *ptr; int shift; @@ -117,10 +112,10 @@ int clock_twi_onoff(int port, int state) if (port == 5) { shift = 0; - ptr = &prcm->twi_gate_reset; + ptr = prcm + CCU_PRCM_I2C_GATE_RESET; } else { shift = port; - ptr = &ccm->twi_gate_reset; + ptr = ccm + CCU_H6_I2C_GATE_RESET; } /* set the apb clock gate and reset for twi */ @@ -136,9 +131,8 @@ int clock_twi_onoff(int port, int state) /* PLL_PERIPH0 clock, used by the MMC driver */ unsigned int clock_get_pll6(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); + void *const ccm = (void *)SUNXI_CCM_BASE; + uint32_t rval = readl(ccm + CCU_H6_PLL6_CFG); int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> CCM_PLL6_CTRL_DIV2_SHIFT) + 1; diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c new file mode 100644 index 00000000000..24767354935 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_dw_helpers.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Helpers that are commonly used with DW memory controller. + * + * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com> + * + */ + +#include <init.h> +#include <asm/arch/dram_dw_helpers.h> + +void mctl_auto_detect_rank_width(const struct dram_para *para, + struct dram_config *config) +{ + /* this is minimum size that it's supported */ + config->cols = 8; + config->rows = 13; + + /* + * Strategy here is to test most demanding combination first and least + * demanding last, otherwise HW might not be fully utilized. For + * example, half bus width and rank = 1 combination would also work + * on HW with full bus width and rank = 2, but only 1/4 RAM would be + * visible. + */ + + debug("testing 32-bit width, rank = 2\n"); + config->bus_full_width = 1; + config->ranks = 2; + if (mctl_core_init(para, config)) + return; + + debug("testing 32-bit width, rank = 1\n"); + config->bus_full_width = 1; + config->ranks = 1; + if (mctl_core_init(para, config)) + return; + + debug("testing 16-bit width, rank = 2\n"); + config->bus_full_width = 0; + config->ranks = 2; + if (mctl_core_init(para, config)) + return; + + debug("testing 16-bit width, rank = 1\n"); + config->bus_full_width = 0; + config->ranks = 1; + if (mctl_core_init(para, config)) + return; + + panic("This DRAM setup is currently not supported.\n"); +} + +static void mctl_write_pattern(void) +{ + unsigned int i; + u32 *ptr, val; + + ptr = (u32 *)CFG_SYS_SDRAM_BASE; + for (i = 0; i < 16; ptr++, i++) { + if (i & 1) + val = ~(ulong)ptr; + else + val = (ulong)ptr; + writel(val, ptr); + } +} + +static bool mctl_check_pattern(ulong offset) +{ + unsigned int i; + u32 *ptr, val; + + ptr = (u32 *)CFG_SYS_SDRAM_BASE; + for (i = 0; i < 16; ptr++, i++) { + if (i & 1) + val = ~(ulong)ptr; + else + val = (ulong)ptr; + if (val != *(ptr + offset / 4)) + return false; + } + + return true; +} + +void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config) +{ + unsigned int shift, cols, rows; + u32 buffer[16]; + + /* max. config for columns, but not rows */ + config->cols = 11; + config->rows = 13; + mctl_core_init(para, config); + + /* + * Store content so it can be restored later. This is important + * if controller was already initialized and holds any data + * which is important for restoring system. + */ + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + + mctl_write_pattern(); + + shift = config->bus_full_width + 1; + + /* detect column address bits */ + for (cols = 8; cols < 11; cols++) { + if (mctl_check_pattern(1ULL << (cols + shift))) + break; + } + debug("detected %u columns\n", cols); + + /* restore data */ + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + + /* reconfigure to make sure that all active rows are accessible */ + config->cols = 8; + config->rows = 17; + mctl_core_init(para, config); + + /* store data again as it might be moved */ + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + + mctl_write_pattern(); + + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; + for (rows = 13; rows < 17; rows++) { + if (mctl_check_pattern(1ULL << (rows + shift))) + break; + } + debug("detected %u rows\n", rows); + + /* restore data again */ + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + + config->cols = cols; + config->rows = rows; +} + +unsigned long mctl_calc_size(const struct dram_config *config) +{ + u8 width = config->bus_full_width ? 4 : 2; + + /* 8 banks */ + return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; +} diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index e7862bd06ea..84fd64a2bfc 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/dram_dw_helpers.h> #include <asm/arch/cpu.h> #include <asm/arch/prcm.h> #include <linux/bitops.h> @@ -34,23 +35,26 @@ * similar PHY is ZynqMP. */ -static void mctl_sys_init(struct dram_para *para); -static void mctl_com_init(struct dram_para *para); -static bool mctl_channel_init(struct dram_para *para); +static void mctl_sys_init(u32 clk_rate); +static void mctl_com_init(const struct dram_para *para, + const struct dram_config *config); +static bool mctl_channel_init(const struct dram_para *para, + const struct dram_config *config); -static bool mctl_core_init(struct dram_para *para) +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) { - mctl_sys_init(para); - mctl_com_init(para); + mctl_sys_init(para->clk); + mctl_com_init(para, config); switch (para->type) { case SUNXI_DRAM_TYPE_LPDDR3: case SUNXI_DRAM_TYPE_DDR3: - mctl_set_timing_params(para); + mctl_set_timing_params(); break; default: panic("Unsupported DRAM type!"); }; - return mctl_channel_init(para); + return mctl_channel_init(para, config); } /* PHY initialisation */ @@ -150,36 +154,36 @@ static void mctl_set_master_priority(void) MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32); } -static void mctl_sys_init(struct dram_para *para) +static void mctl_sys_init(u32 clk_rate) { - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; /* Put all DRAM-related blocks to reset state */ - clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); - clrbits_le32(&ccm->dram_gate_reset, BIT(0)); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE | MBUS_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0)); udelay(5); - writel(0, &ccm->dram_gate_reset); - clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); - clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + writel(0, ccm + CCU_H6_DRAM_GATE_RESET); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set PLL5 rate to doubled DRAM clock rate */ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | - CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg); - mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG); + mctl_await_completion(ccm + CCU_H6_PLL5_CFG, + CCM_PLL5_LOCK, CCM_PLL5_LOCK); /* Configure DRAM mod clock */ - writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); - setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); - writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_CLK_UPDATE); + writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET); udelay(5); - setbits_le32(&ccm->dram_gate_reset, BIT(0)); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0)); /* Disable all channels */ writel(0, &mctl_com->maer0); @@ -187,24 +191,24 @@ static void mctl_sys_init(struct dram_para *para) writel(0, &mctl_com->maer2); /* Configure MBUS and enable DRAM mod reset */ - setbits_le32(&ccm->mbus_cfg, MBUS_RESET); - setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); - setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Unknown hack from the BSP, which enables access of mctl_ctl regs */ writel(0x8000, &mctl_ctl->unk_0x00c); } -static void mctl_set_addrmap(struct dram_para *para) +static void mctl_set_addrmap(const struct dram_config *config) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - u8 cols = para->cols; - u8 rows = para->rows; - u8 ranks = para->ranks; + u8 cols = config->cols; + u8 rows = config->rows; + u8 ranks = config->ranks; - if (!para->bus_full_width) + if (!config->bus_full_width) cols -= 1; /* Ranks */ @@ -282,7 +286,8 @@ static void mctl_set_addrmap(struct dram_para *para) mctl_ctl->addrmap[8] = 0x3F3F; } -static void mctl_com_init(struct dram_para *para) +static void mctl_com_init(const struct dram_para *para, + const struct dram_config *config) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; @@ -292,7 +297,7 @@ static void mctl_com_init(struct dram_para *para) (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; u32 reg_val, tmp; - mctl_set_addrmap(para); + mctl_set_addrmap(config); setbits_le32(&mctl_com->cr, BIT(31)); @@ -311,12 +316,12 @@ static void mctl_com_init(struct dram_para *para) clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); /* TODO: DDR4 */ - reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks); + reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) reg_val |= MSTR_DEVICETYPE_LPDDR3; if (para->type == SUNXI_DRAM_TYPE_DDR3) reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; - if (para->bus_full_width) + if (config->bus_full_width) reg_val |= MSTR_BUSWIDTH_FULL; else reg_val |= MSTR_BUSWIDTH_HALF; @@ -328,7 +333,7 @@ static void mctl_com_init(struct dram_para *para) reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T; writel(reg_val | 0x400, &mctl_phy->dcr); - if (para->ranks == 2) + if (config->ranks == 2) writel(0x0303, &mctl_ctl->odtmap); else writel(0x0201, &mctl_ctl->odtmap); @@ -346,13 +351,13 @@ static void mctl_com_init(struct dram_para *para) } writel(reg_val, &mctl_ctl->odtcfg); - if (!para->bus_full_width) { + if (!config->bus_full_width) { writel(0x0, &mctl_phy->dx[2].gcr[0]); writel(0x0, &mctl_phy->dx[3].gcr[0]); } } -static void mctl_bit_delay_set(struct dram_para *para) +static void mctl_bit_delay_set(const struct dram_para *para) { struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; @@ -411,7 +416,8 @@ static void mctl_bit_delay_set(struct dram_para *para) } } -static bool mctl_channel_init(struct dram_para *para) +static bool mctl_channel_init(const struct dram_para *para, + const struct dram_config *config) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; @@ -446,14 +452,14 @@ static bool mctl_channel_init(struct dram_para *para) udelay(100); - if (para->ranks == 2) + if (config->ranks == 2) setbits_le32(&mctl_phy->dtcr[1], 0x30000); else clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); if (sunxi_dram_is_lpddr(para->type)) clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); - if (para->ranks == 2) { + if (config->ranks == 2) { writel(0x00010001, &mctl_phy->rankidr); writel(0x20000, &mctl_phy->odtcr); } else { @@ -555,90 +561,6 @@ static bool mctl_channel_init(struct dram_para *para) return true; } -static void mctl_auto_detect_rank_width(struct dram_para *para) -{ - /* this is minimum size that it's supported */ - para->cols = 8; - para->rows = 13; - - /* - * Previous versions of this driver tried to auto detect the rank - * and width by looking at controller registers. However this proved - * to be not reliable, so this approach here is the more robust - * solution. Check the git history for details. - * - * Strategy here is to test most demanding combination first and least - * demanding last, otherwise HW might not be fully utilized. For - * example, half bus width and rank = 1 combination would also work - * on HW with full bus width and rank = 2, but only 1/4 RAM would be - * visible. - */ - - debug("testing 32-bit width, rank = 2\n"); - para->bus_full_width = 1; - para->ranks = 2; - if (mctl_core_init(para)) - return; - - debug("testing 32-bit width, rank = 1\n"); - para->bus_full_width = 1; - para->ranks = 1; - if (mctl_core_init(para)) - return; - - debug("testing 16-bit width, rank = 2\n"); - para->bus_full_width = 0; - para->ranks = 2; - if (mctl_core_init(para)) - return; - - debug("testing 16-bit width, rank = 1\n"); - para->bus_full_width = 0; - para->ranks = 1; - if (mctl_core_init(para)) - return; - - panic("This DRAM setup is currently not supported.\n"); -} - -static void mctl_auto_detect_dram_size(struct dram_para *para) -{ - /* TODO: non-(LP)DDR3 */ - - /* detect row address bits */ - para->cols = 8; - para->rows = 18; - mctl_core_init(para); - - for (para->rows = 13; para->rows < 18; para->rows++) { - /* 8 banks, 8 bit per byte and 16/32 bit width */ - if (mctl_mem_matches((1 << (para->rows + para->cols + - 4 + para->bus_full_width)))) - break; - } - - /* detect column address bits */ - para->cols = 11; - mctl_core_init(para); - - for (para->cols = 8; para->cols < 11; para->cols++) { - /* 8 bits per byte and 16/32 bit width */ - if (mctl_mem_matches(1 << (para->cols + 1 + - para->bus_full_width))) - break; - } -} - -unsigned long mctl_calc_size(struct dram_para *para) -{ - u8 width = para->bus_full_width ? 4 : 2; - - /* TODO: non-(LP)DDR3 */ - - /* 8 banks */ - return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; -} - #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ @@ -661,36 +583,36 @@ unsigned long mctl_calc_size(struct dram_para *para) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }} -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - struct dram_para para = { - .clk = CONFIG_DRAM_CLK, +static const struct dram_para para = { + .clk = CONFIG_DRAM_CLK, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 - .type = SUNXI_DRAM_TYPE_LPDDR3, - .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, - .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS, + .type = SUNXI_DRAM_TYPE_LPDDR3, + .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS, #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333) - .type = SUNXI_DRAM_TYPE_DDR3, - .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS, - .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS, + .type = SUNXI_DRAM_TYPE_DDR3, + .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS, #endif - }; +}; +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; + struct dram_config config; unsigned long size; - setbits_le32(&prcm->res_cal_ctrl, BIT(8)); - clrbits_le32(&prcm->ohms240, 0x3f); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8)); + clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f); - mctl_auto_detect_rank_width(¶); - mctl_auto_detect_dram_size(¶); + mctl_auto_detect_rank_width(¶, &config); + mctl_auto_detect_dram_size(¶, &config); - mctl_core_init(¶); + mctl_core_init(¶, &config); - size = mctl_calc_size(¶); + size = mctl_calc_size(&config); clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0); diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index cd9d321a018..5a59f82d1ef 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/dram_dw_helpers.h> #include <asm/arch/cpu.h> #include <asm/arch/prcm.h> #include <linux/bitops.h> @@ -93,34 +94,34 @@ static void mctl_set_master_priority(void) static void mctl_sys_init(u32 clk_rate) { - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; /* Put all DRAM-related blocks to reset state */ - clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); - clrbits_le32(&ccm->mbus_cfg, MBUS_RESET); - clrbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT)); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); udelay(5); - clrbits_le32(&ccm->dram_gate_reset, BIT(RESET_SHIFT)); - clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); - clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set PLL5 rate to doubled DRAM clock rate */ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN | - CCM_PLL5_CTRL_N(clk_rate * 2 / 24), &ccm->pll5_cfg); - mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG); + mctl_await_completion(ccm + CCU_H6_PLL5_CFG, + CCM_PLL5_LOCK, CCM_PLL5_LOCK); /* Configure DRAM mod clock */ - writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); - writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); + writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET); udelay(5); - setbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT)); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); /* Disable all channels */ writel(0, &mctl_com->maer0); @@ -128,12 +129,12 @@ static void mctl_sys_init(u32 clk_rate) writel(0, &mctl_com->maer2); /* Configure MBUS and enable DRAM mod reset */ - setbits_le32(&ccm->mbus_cfg, MBUS_RESET); - setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); clrbits_le32(&mctl_com->unk_0x500, BIT(25)); - setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Unknown hack, which enables access of mctl_ctl regs */ @@ -1310,154 +1311,14 @@ static bool mctl_ctrl_init(const struct dram_para *para, return true; } -static bool mctl_core_init(const struct dram_para *para, - const struct dram_config *config) +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) { mctl_sys_init(para->clk); return mctl_ctrl_init(para, config); } -static void mctl_auto_detect_rank_width(const struct dram_para *para, - struct dram_config *config) -{ - /* this is minimum size that it's supported */ - config->cols = 8; - config->rows = 13; - - /* - * Strategy here is to test most demanding combination first and least - * demanding last, otherwise HW might not be fully utilized. For - * example, half bus width and rank = 1 combination would also work - * on HW with full bus width and rank = 2, but only 1/4 RAM would be - * visible. - */ - - debug("testing 32-bit width, rank = 2\n"); - config->bus_full_width = 1; - config->ranks = 2; - if (mctl_core_init(para, config)) - return; - - debug("testing 32-bit width, rank = 1\n"); - config->bus_full_width = 1; - config->ranks = 1; - if (mctl_core_init(para, config)) - return; - - debug("testing 16-bit width, rank = 2\n"); - config->bus_full_width = 0; - config->ranks = 2; - if (mctl_core_init(para, config)) - return; - - debug("testing 16-bit width, rank = 1\n"); - config->bus_full_width = 0; - config->ranks = 1; - if (mctl_core_init(para, config)) - return; - - panic("This DRAM setup is currently not supported.\n"); -} - -static void mctl_write_pattern(void) -{ - unsigned int i; - u32 *ptr, val; - - ptr = (u32 *)CFG_SYS_SDRAM_BASE; - for (i = 0; i < 16; ptr++, i++) { - if (i & 1) - val = ~(ulong)ptr; - else - val = (ulong)ptr; - writel(val, ptr); - } -} - -static bool mctl_check_pattern(ulong offset) -{ - unsigned int i; - u32 *ptr, val; - - ptr = (u32 *)CFG_SYS_SDRAM_BASE; - for (i = 0; i < 16; ptr++, i++) { - if (i & 1) - val = ~(ulong)ptr; - else - val = (ulong)ptr; - if (val != *(ptr + offset / 4)) - return false; - } - - return true; -} - -static void mctl_auto_detect_dram_size(const struct dram_para *para, - struct dram_config *config) -{ - unsigned int shift, cols, rows; - u32 buffer[16]; - - /* max. config for columns, but not rows */ - config->cols = 11; - config->rows = 13; - mctl_core_init(para, config); - - /* - * Store content so it can be restored later. This is important - * if controller was already initialized and holds any data - * which is important for restoring system. - */ - memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); - - mctl_write_pattern(); - - shift = config->bus_full_width + 1; - - /* detect column address bits */ - for (cols = 8; cols < 11; cols++) { - if (mctl_check_pattern(1ULL << (cols + shift))) - break; - } - debug("detected %u columns\n", cols); - - /* restore data */ - memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); - - /* reconfigure to make sure that all active rows are accessible */ - config->cols = 8; - config->rows = 17; - mctl_core_init(para, config); - - /* store data again as it might be moved */ - memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); - - mctl_write_pattern(); - - /* detect row address bits */ - shift = config->bus_full_width + 4 + config->cols; - for (rows = 13; rows < 17; rows++) { - if (mctl_check_pattern(1ULL << (rows + shift))) - break; - } - debug("detected %u rows\n", rows); - - /* restore data again */ - memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); - - config->cols = cols; - config->rows = rows; -} - -static unsigned long mctl_calc_size(const struct dram_config *config) -{ - u8 width = config->bus_full_width ? 4 : 2; - - /* 8 banks */ - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; -} - static const struct dram_para para = { .clk = CONFIG_DRAM_CLK, #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 @@ -1481,13 +1342,12 @@ static const struct dram_para para = { unsigned long sunxi_dram_init(void) { - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; struct dram_config config; unsigned long size; - setbits_le32(&prcm->res_cal_ctrl, BIT(8)); - clrbits_le32(&prcm->ohms240, 0x3f); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8)); + clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f); mctl_auto_detect_rank_width(¶, &config); mctl_auto_detect_dram_size(¶, &config); diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index afe8e25c7f5..1ed46fed411 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -37,7 +37,7 @@ static u32 mr_ddr3[7] = { }; /* TODO: flexible timing */ -void mctl_set_timing_params(struct dram_para *para) +void mctl_set_timing_params(void) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c index c243b574406..c02f542c989 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c @@ -16,7 +16,7 @@ static u32 mr_lpddr3[12] = { }; /* TODO: flexible timing */ -void mctl_set_timing_params(struct dram_para *para) +void mctl_set_timing_params(void) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S index 422007c985b..a6d75c32ed9 100644 --- a/arch/arm/mach-sunxi/rmr_switch.S +++ b/arch/arm/mach-sunxi/rmr_switch.S @@ -49,10 +49,22 @@ start32: str lr, [r0, #4] mrs lr, CPSR str lr, [r0, #8] + mrs lr, SP_irq + str lr, [r0, #20] mrc p15, 0, lr, cr1, cr0, 0 // SCTLR str lr, [r0, #12] mrc p15, 0, lr, cr12, cr0, 0 // VBAR str lr, [r0, #16] +//#ifdef CONFIG_MACH_SUN55I_A523 + mrc p15, 0, lr, cr12, cr12, 5 // ICC_SRE + tst lr, #1 + beq 1f + mrc p15, 0, lr, c4, c6, 0 // ICC_PMR + str lr, [r0, #24] + mrc p15, 0, lr, c12, c12, 7 // ICC_IGRPEN1 + str lr, [r0, #28] +1: +//#endif ldr r1, =CONFIG_SUNXI_RVBAR_ADDRESS ldr r0, =SUNXI_SRAMC_BASE diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index ebac3473a1f..2f0341bc02a 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o -obj-$(CONFIG_$(XPL_)TEGRA_CRYPTO) += crypto.o +obj-$(CONFIG_$(PHASE_)TEGRA_CRYPTO) += crypto.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 7ca56a3b081..4835824f724 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -169,6 +169,8 @@ static int uart_configs[] = { FUNCMUX_UART1_GPU, #elif defined(CONFIG_TEGRA_UARTA_SDIO1) FUNCMUX_UART1_SDIO1, + #elif defined(CONFIG_TEGRA_UARTA_SDB_SDD) + FUNCMUX_UART1_SDB_SDD, #else FUNCMUX_UART1_IRRX_IRTX, #endif @@ -236,18 +238,23 @@ void board_init_uart_f(void) int uart_ids = 0; /* bit mask of which UART ids to enable */ #ifdef CONFIG_TEGRA_ENABLE_UARTA +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE uart_ids |= UARTA; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTB +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE uart_ids |= UARTB; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTC +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTC_BASE uart_ids |= UARTC; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTD +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE uart_ids |= UARTD; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTE_BASE uart_ids |= UARTE; #endif setup_uarts(uart_ids); diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 6e9ef68caf9..68534dcbb22 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -96,7 +96,7 @@ int checkboard(void) { int board_id = tegra_board_id(); - printf("Board: %s", CFG_TEGRA_BOARD_STRING); + printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); if (board_id != -1) printf(", ID: %d\n", board_id); printf("\n"); diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index a375693481e..4f0cc19df50 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -703,6 +703,12 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) else writel(base_reg, &simple_pll->pll_base); + /* PLLD and PLLD2 are only clocks which have ENABLE bit */ + if (clkid == CLOCK_ID_DISPLAY) + setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE)); + if (clkid == CLOCK_ID_DISPLAY2) + setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE)); + /* * Changing clocks was never intended in the U-Boot for Tegra. * If a clock is changed after clock_init() the parent rate is wrong. diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 5f0f909dd3b..98f1d0e71c1 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,11 +8,21 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_TEGRATAB + bool "NVIDIA Tegra114 TegraTab evaluation board" + select BOARD_LATE_INIT + +config TARGET_TRANSFORMER_T114 + bool "ASUS Tegra114 Transformer board" + select BOARD_LATE_INIT + endchoice config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/nvidia/tegratab/Kconfig" +source "board/asus/transformer-t114/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index d5cc8ac44dd..d67d808b724 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -796,7 +796,6 @@ struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, - { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 0ea212f80e2..8a6735d71af 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -598,8 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ - { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, - .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, + .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index e2735d93e28..a79fdc25650 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -17,6 +17,9 @@ config TEGRA_UARTA_GPU config TEGRA_UARTA_SDIO1 bool +config TEGRA_UARTA_SDB_SDD + bool + choice prompt "Tegra20 board select" optional @@ -29,6 +32,10 @@ config TARGET_MEDCOM_WIDE bool "Avionic Design Medcom-Wide board" select BOARD_LATE_INIT +config TARGET_MOT + bool "Motorola Tegra20 board" + select BOARD_LATE_INIT + config TARGET_PAZ00 bool "Paz00 board" select BOARD_LATE_INIT @@ -76,6 +83,7 @@ config SYS_SOC source "board/nvidia/harmony/Kconfig" source "board/avionic-design/medcom-wide/Kconfig" +source "board/motorola/mot/Kconfig" source "board/compal/paz00/Kconfig" source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 32c1866b099..a3ea759d764 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2010,2011 Nvidia Corporation. obj-$(CONFIG_XPL_BUILD) += cpu.o -obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_$(PHASE_)CMD_EBTUPDATE) += bct.o # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 04708f97144..d1ede5238dd 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -668,8 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ - { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, - .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, + .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index b36657a432f..d6351734ec0 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -3,6 +3,6 @@ # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. obj-$(CONFIG_XPL_BUILD) += cpu.o -obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_$(PHASE_)CMD_EBTUPDATE) += bct.o obj-y += clock.o diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 54fb93aeb53..7def7b9139a 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -45,6 +45,5 @@ config ZYNQ_SDHCI_MAX_FREQ default 200000000 source "board/xilinx/Kconfig" -source "board/xilinx/versal-net/Kconfig" endif diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 629a14129d5..5ab901c81ca 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -46,6 +46,5 @@ config VERSAL_NO_DDR access to DDR memory where DDR is not present. source "board/xilinx/Kconfig" -source "board/xilinx/versal/Kconfig" endif diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 9d1c2f0dcfc..b5f80a8e3a9 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -87,6 +87,8 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 +#define PMC_MULTI_BOOT_REG 0xF1110004 +#define PMC_MULTI_BOOT_MASK 0x1FFF #define FLASH_RESET_GPIO 0xc #define WPROT_CRP 0xF126001C diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 757bd873fbe..a6dfa556966 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -5,11 +5,11 @@ #include <linux/build_bug.h> -enum { - TCM_LOCK, - TCM_SPLIT, +enum tcm_mode { + TCM_LOCK = 0, + TCM_SPLIT = 1, }; -void initialize_tcm(bool mode); -void tcm_init(u8 mode); +void initialize_tcm(enum tcm_mode mode); +void tcm_init(enum tcm_mode mode); void mem_map_fill(void); diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 921ca49c359..7423b8dc312 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -24,7 +24,7 @@ #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 -static void set_r5_halt_mode(u8 halt, u8 mode) +static void set_r5_halt_mode(u8 halt, enum tcm_mode mode) { u32 tmp; @@ -45,7 +45,7 @@ static void set_r5_halt_mode(u8 halt, u8 mode) } } -static void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(enum tcm_mode mode) { u32 tmp; @@ -63,7 +63,7 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void release_r5_reset(u8 mode) +static void release_r5_reset(enum tcm_mode mode) { u32 tmp; @@ -87,9 +87,9 @@ static void enable_clock_r5(void) writel(tmp, &crlapb_base->cpu_r5_ctrl); } -void initialize_tcm(bool mode) +void initialize_tcm(enum tcm_mode mode) { - if (!mode) { + if (mode == TCM_LOCK) { set_r5_tcm_mode(TCM_LOCK); set_r5_halt_mode(HALT, TCM_LOCK); enable_clock_r5(); @@ -102,7 +102,7 @@ void initialize_tcm(bool mode) } } -void tcm_init(u8 mode) +void tcm_init(enum tcm_mode mode) { puts("WARNING: Initializing TCM overwrites TCM content\n"); initialize_tcm(mode); diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig index 3f18e3351aa..2a595151d6f 100644 --- a/arch/arm/mach-versal2/Kconfig +++ b/arch/arm/mach-versal2/Kconfig @@ -50,6 +50,5 @@ config ZYNQ_SDHCI_MAX_FREQ default 200000000 source "board/xilinx/Kconfig" -source "board/amd/versal2/Kconfig" endif diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 15085f941e0..7ca2bbb7550 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -68,6 +68,7 @@ struct crp_regs { #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 #define SELECTMAP_MODE 0x0000000A +#define UFS_MODE 0x0000000B #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 @@ -96,3 +97,9 @@ enum versal2_platform { #define MIO_PIN_12 0xF1060030 #define BANK0_OUTPUT 0xF1020040 #define BANK0_TRI 0xF1060200 + +#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000 +#define PMXC_SLCR_BASE_ADDRESS 0xF1061000 +#define PMXC_UFS_CAL_1_OFFSET 0xBE8 +#define PMXC_SRAM_CSR 0x4C +#define PMXC_TX_RX_CFG_RDY 0x54 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 376d1bc7131..c3f505fa15c 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -58,5 +58,6 @@ config ZYNQ_SDHCI_MAX_FREQ source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" +source "board/BuR/zynq/Kconfig" endif diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index ff426044797..4bd4014dc15 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -7,7 +7,7 @@ obj-y += aes.o clk.o cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_XPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o -obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o +obj-$(CONFIG_$(PHASE_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 960ffac2105..b7a4142fd54 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -113,7 +113,7 @@ u64 get_page_table_size(void) } #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode) +void tcm_init(enum tcm_mode mode) { int ret; diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 9af3ab5d6b6..b6a41df1da4 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -41,18 +41,18 @@ enum { ZYNQMP_SILICON_V4, }; -enum { - TCM_LOCK, - TCM_SPLIT, +enum tcm_mode { + TCM_LOCK = 0, + TCM_SPLIT = 1, }; unsigned int zynqmp_get_silicon_version(void); -int check_tcm_mode(bool mode); -void initialize_tcm(bool mode); +int check_tcm_mode(enum tcm_mode mode); +void initialize_tcm(enum tcm_mode mode); void mem_map_fill(void); #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode); +void tcm_init(enum tcm_mode mode); #endif #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 448bc532867..d2a7f305ccc 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -17,9 +17,6 @@ #include <linux/errno.h> #include <linux/string.h> -#define LOCK 0 -#define SPLIT 1 - #define HALT 0 #define RELEASE 1 @@ -65,11 +62,11 @@ int cpu_reset(u32 nr) return 0; } -static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) +static void set_r5_halt_mode(u32 nr, u8 halt, enum tcm_mode mode) { u32 tmp; - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) { + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) { tmp = readl(&rpu_base->rpu0_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -78,7 +75,7 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) writel(tmp, &rpu_base->rpu0_cfg); } - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) { + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) { tmp = readl(&rpu_base->rpu1_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -88,12 +85,12 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) } } -static void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(enum tcm_mode mode) { u32 tmp; tmp = readl(&rpu_base->rpu_glbl_ctrl); - if (mode == LOCK) { + if (mode == TCM_LOCK) { tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; @@ -106,12 +103,12 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void set_r5_reset(u32 nr, u8 mode) +static void set_r5_reset(u32 nr, enum tcm_mode mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK) { + if (mode == TCM_LOCK) { tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); @@ -130,16 +127,16 @@ static void set_r5_reset(u32 nr, u8 mode) writel(tmp, &crlapb_base->rst_lpd_top); } -static void release_r5_reset(u32 nr, u8 mode) +static void release_r5_reset(u32 nr, enum tcm_mode mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); @@ -165,9 +162,9 @@ static int check_r5_mode(void) tmp = readl(&rpu_base->rpu_glbl_ctrl); if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK) - return SPLIT; + return TCM_SPLIT; - return LOCK; + return TCM_LOCK; } int cpu_disable(u32 nr) @@ -249,27 +246,27 @@ static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr) } } -void initialize_tcm(bool mode) +void initialize_tcm(enum tcm_mode mode) { - if (!mode) { - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK); + if (mode == TCM_LOCK) { + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_LOCK); enable_clock_r5(); - release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); + release_r5_reset(ZYNQMP_CORE_RPU0, TCM_LOCK); } else { - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT); - set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, TCM_SPLIT); enable_clock_r5(); - release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT); - release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU0, TCM_SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU1, TCM_SPLIT); } } -int check_tcm_mode(bool mode) +int check_tcm_mode(enum tcm_mode mode) { u32 tmp, cpu_state; - bool mode_prev; + enum tcm_mode mode_prev; tmp = readl(&rpu_base->rpu_glbl_ctrl); mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp); @@ -279,7 +276,7 @@ int check_tcm_mode(bool mode) ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp); cpu_state = cpu_state ? false : true; - if ((mode_prev == SPLIT && mode == LOCK) && cpu_state) + if ((mode_prev == TCM_SPLIT && mode == TCM_LOCK) && cpu_state) return -EACCES; if (mode_prev == mode) @@ -288,11 +285,11 @@ int check_tcm_mode(bool mode) return 0; } -static void mark_r5_used(u32 nr, u8 mode) +static void mark_r5_used(u32 nr, enum tcm_mode mode) { u32 mask = 0; - if (mode == LOCK) { + if (mode == TCM_LOCK) { mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK; } else { switch (nr) { @@ -358,30 +355,30 @@ int cpu_release(u32 nr, int argc, char *const argv[]) return 1; } printf("R5 lockstep mode\n"); - set_r5_reset(nr, LOCK); - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(nr, HALT, LOCK); + set_r5_reset(nr, TCM_LOCK); + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(nr, HALT, TCM_LOCK); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(nr, LOCK); + release_r5_reset(nr, TCM_LOCK); dcache_disable(); write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(nr, RELEASE, LOCK); - mark_r5_used(nr, LOCK); + set_r5_halt_mode(nr, RELEASE, TCM_LOCK); + mark_r5_used(nr, TCM_LOCK); } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) { printf("R5 split mode\n"); - set_r5_reset(nr, SPLIT); - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(nr, HALT, SPLIT); + set_r5_reset(nr, TCM_SPLIT); + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(nr, HALT, TCM_SPLIT); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(nr, SPLIT); + release_r5_reset(nr, TCM_SPLIT); dcache_disable(); write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(nr, RELEASE, SPLIT); - mark_r5_used(nr, SPLIT); + set_r5_halt_mode(nr, RELEASE, TCM_SPLIT); + mark_r5_used(nr, TCM_SPLIT); } else { printf("Unsupported mode\n"); return 1; diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 3aa218545bb..279006b4d13 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -146,7 +146,7 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - u8 mode; + enum tcm_mode mode; if (argc != cmdtp->maxargs) return CMD_RET_USAGE; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7ea439e857c..a0317011de7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -146,7 +146,35 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R6 select SUPPORT_BIG_ENDIAN select SUPPORT_LITTLE_ENDIAN + imply OF_UPSTREAM + imply BOOTSTD_FULL + imply CLK + imply CLK_BOSTON imply CMD_DM + imply AHCI + imply AHCI_PCI + imply CFI_FLASH + imply MTD_NOR_FLASH + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply PCH_GBE + imply PCI + imply PCI_XILINX + imply PCI_INIT_R + imply SCSI + imply SCSI_AHCI + imply SYS_NS16550 + imply SYSRESET + imply SYSRESET_CMD_POWEROFF + imply SYSRESET_SYSCON + imply USB + imply USB_EHCI_HCD + imply USB_EHCI_PCI + imply USB_XHCI_HCD + imply USB_XHCI_PCI + imply CMD_USB config TARGET_XILFPGA bool "Support Imagination Xilfpga" @@ -322,6 +350,7 @@ config MIPS_CACHE_DISABLE config MIPS_RELOCATION_TABLE_SIZE hex "Relocation table size" range 0x100 0x10000 + default "0xc000" if TARGET_MALTA default "0x8000" ---help--- A table of relocation data will be appended to the U-Boot binary diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 752e771514f..7c4ee8b668b 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -3,7 +3,6 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_AP152) += ap152.dtb -dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb diff --git a/arch/mips/dts/boston-u-boot.dtsi b/arch/mips/dts/boston-u-boot.dtsi new file mode 100644 index 00000000000..1b0c0a28961 --- /dev/null +++ b/arch/mips/dts/boston-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&plat_regs { + compatible = "img,boston-platform-regs", "syscon", "simple-mfd"; + bootph-all; +}; + +&clk_boston { + bootph-all; +}; diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts deleted file mode 100644 index c1a73963037..00000000000 --- a/arch/mips/dts/img,boston.dts +++ /dev/null @@ -1,222 +0,0 @@ -/dts-v1/; - -#include <dt-bindings/clock/boston-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/mips-gic.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "img,boston"; - - chosen { - stdout-path = &uart0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "img,mips"; - reg = <0>; - clocks = <&clk_boston BOSTON_CLK_CPU>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - gic: interrupt-controller { - compatible = "mti,gic"; - - interrupt-controller; - #interrupt-cells = <3>; - - timer { - compatible = "mti,gic-timer"; - interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; - clocks = <&clk_boston BOSTON_CLK_CPU>; - }; - }; - - pci0: pci@10000000 { - status = "disabled"; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x10000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; - - ranges = <0x02000000 0 0x40000000 - 0x40000000 0 0x40000000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci0_intc 0>, - <0 0 0 2 &pci0_intc 1>, - <0 0 0 3 &pci0_intc 2>, - <0 0 0 4 &pci0_intc 3>; - - pci0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pci1: pci@12000000 { - status = "disabled"; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x12000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; - - ranges = <0x02000000 0 0x20000000 - 0x20000000 0 0x20000000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci1_intc 0>, - <0 0 0 2 &pci1_intc 1>, - <0 0 0 3 &pci1_intc 2>, - <0 0 0 4 &pci1_intc 3>; - - pci1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pci2: pci@14000000 { - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x14000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; - - ranges = <0x02000000 0 0x16000000 - 0x16000000 0 0x100000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci2_intc 0>, - <0 0 0 2 &pci2_intc 1>, - <0 0 0 3 &pci2_intc 2>, - <0 0 0 4 &pci2_intc 3>; - - pci2_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - pci2_root@0,0,0 { - compatible = "pci10ee,7021"; - reg = <0x00000000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - eg20t_bridge@1,0,0 { - compatible = "pci8086,8800"; - reg = <0x00010000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - eg20t_mac@2,0,1 { - compatible = "pci8086,8802"; - reg = <0x00020100 0 0 0 0>; - phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; - }; - - eg20t_gpio: eg20t_gpio@2,0,2 { - compatible = "pci8086,8803"; - reg = <0x00020200 0 0 0 0>; - - gpio-controller; - #gpio-cells = <2>; - }; - - eg20t_i2c@2,12,2 { - compatible = "pci8086,8817"; - reg = <0x00026200 0 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - rtc@0x68 { - compatible = "st,m41t81s"; - reg = <0x68>; - }; - }; - }; - }; - }; - - plat_regs: system-controller@17ffd000 { - compatible = "img,boston-platform-regs", "syscon"; - reg = <0x17ffd000 0x1000>; - bootph-all; - }; - - clk_boston: clock { - compatible = "img,boston-clock"; - #clock-cells = <1>; - regmap = <&plat_regs>; - bootph-all; - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&plat_regs>; - offset = <0x10>; - mask = <0x10>; - }; - - uart0: uart@17ffe000 { - compatible = "ns16550a"; - reg = <0x17ffe000 0x1000>; - reg-shift = <2>; - reg-io-width = <4>; - - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&clk_boston BOSTON_CLK_SYS>; - - bootph-all; - }; - - lcd: lcd@17fff000 { - compatible = "img,boston-lcd"; - reg = <0x17fff000 0x8>; - }; - - flash@18000000 { - compatible = "cfi-flash"; - reg = <0x18000000 0x8000000>; - bank-width = <2>; - }; -}; diff --git a/arch/mips/include/asm/acpi_table.h b/arch/mips/include/asm/acpi_table.h new file mode 100644 index 00000000000..b4139d0ba32 --- /dev/null +++ b/arch/mips/include/asm/acpi_table.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +/* + * This file is needed by some drivers. + */ + +#endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4e6f347038d..6f80f4a7108 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -48,7 +48,7 @@ endif ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) -ifeq ($(CONFIG_$(XPL_)FRAMEPOINTER),y) +ifeq ($(CONFIG_$(PHASE_)FRAMEPOINTER),y) ARCH_FLAGS += -fno-omit-frame-pointer endif diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds index 907094620bd..0717833df55 100644 --- a/arch/riscv/cpu/u-boot-spl.lds +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -16,6 +16,7 @@ ENTRY(_start) SECTIONS { . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { arch/riscv/cpu/start.o (.text) *(.text*) @@ -46,6 +47,7 @@ SECTIONS _end = .; _image_binary_end = .; + __image_copy_end = .; .bss : { __bss_start = .; diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 2ffe6ba3c8f..b11ea8b56d2 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -10,6 +10,7 @@ ENTRY(_start) SECTIONS { . = ALIGN(4); + __image_copy_start = ADDR(.text); .text : { arch/riscv/cpu/start.o (.text) } @@ -57,6 +58,8 @@ SECTIONS __efi_runtime_rel_stop = .; } + __image_copy_end = .; + /DISCARD/ : { *(.rela.plt*) } .rela.dyn : { __rel_dyn_start = .; diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index ceb916b74a7..5aeeeddb59f 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -35,7 +35,7 @@ compression = "none"; load = /bits/ 64 <CONFIG_TEXT_BASE>; - uboot_blob: blob-ext { + uboot_blob: u-boot-nodtb { filename = "u-boot-nodtb.bin"; }; }; diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi new file mode 100644 index 00000000000..ab882d07f6f --- /dev/null +++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" +#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index ce7d9e16961..a9e318c4a31 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -102,6 +102,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &syscrg { bootph-pre-ram; }; diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts index d2486f70906..6b5b83bcdb9 100644 --- a/arch/riscv/dts/k1-bananapi-f3.dts +++ b/arch/riscv/dts/k1-bananapi-f3.dts @@ -5,6 +5,7 @@ #include "k1.dtsi" #include "binman.dtsi" +#include "k1-pinctrl.dtsi" / { model = "Banana Pi BPI-F3"; @@ -21,5 +22,7 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi new file mode 100644 index 00000000000..14e7096fbcf --- /dev/null +++ b/arch/riscv/dts/k1-pinctrl.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Spacemit Inc. + * Copyright (C) 2025 Yixun Lan <dlan@gentoo.org> + */ + +#define K1_PADCONF(pin, func) (((pin) << 16) | (func)) + +&pinctrl { + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { + pinmux = <K1_PADCONF(68, 2)>, + <K1_PADCONF(69, 2)>; + + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; +}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi index 7c0f1b928e2..a633e43da32 100644 --- a/arch/riscv/dts/k1.dtsi +++ b/arch/riscv/dts/k1.dtsi @@ -470,5 +470,11 @@ #reset-cells = <1>; status = "disabled"; }; + + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl", "pinctrl-single"; + reg = <0x0 0xd401e000 0x0 0x400>; + pinctrl-single,register-width = <32>; + }; }; -};
\ No newline at end of file +}; diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi index 05787bdb92d..6e083bf0537 100644 --- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi +++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi @@ -20,6 +20,7 @@ args = "-T sfspl"; u-boot-spl { + no-write-symbols; }; }; }; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 268116f3757..189b35c24d3 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,22 +11,23 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o -ifeq ($(CONFIG_$(XPL_)RISCV_MMODE),y) -obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += aclint_ipi.o +ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y) +obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o -ifeq ($(CONFIG_$(XPL_)SYSRESET),) +ifeq ($(CONFIG_$(PHASE_)SYSRESET),) obj-y += reset.o endif obj-y += setjmp.o -obj-$(CONFIG_$(XPL_)SMP) += smp.o +obj-$(CONFIG_$(PHASE_)SMP) += smp.o obj-$(CONFIG_XPL_BUILD) += spl.o obj-y += fdt_fixup.o obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o +obj-$(CONFIG_OF_BOARD) += board.o # For building EFI apps CFLAGS_NON_EFI := -fstack-protector-strong diff --git a/arch/riscv/lib/board.c b/arch/riscv/lib/board.c new file mode 100644 index 00000000000..624c4eaaf4d --- /dev/null +++ b/arch/riscv/lib/board.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * RISC-V-specific handling of firmware FDT + */ + +#include <asm/global_data.h> +#include <linux/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int board_fdt_blob_setup(void **fdtp) +{ + if (!gd->arch.firmware_fdt_addr) + return -EEXIST; + + *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; + + return 0; +} diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c index 859326cbac8..a82f48e9a50 100644 --- a/arch/riscv/lib/image.c +++ b/arch/riscv/lib/image.c @@ -32,13 +32,6 @@ struct linux_image_h { uint32_t res4; /* reserved */ }; -bool booti_is_valid(const void *img) -{ - const struct linux_image_h *lhdr = img; - - return lhdr->magic == LINUX_RISCV_IMAGE_MAGIC; -} - int booti_setup(ulong image, ulong *relocated_addr, ulong *size, bool force_reloc) { @@ -46,7 +39,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, lhdr = (struct linux_image_h *)map_sysmem(image, 0); - if (!booti_is_valid(lhdr)) { + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) { puts("Bad Linux RISCV Image magic!\n"); return -EINVAL; } diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 99d6195827e..9e1f3d5749b 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -59,3 +59,14 @@ ENTRY(longjmp) ret ENDPROC(longjmp) .popsection + +.pushsection .text.initjmp, "ax" +ENTRY(initjmp) + /* a1: entry point address, a2: stack base, a3: stack size */ + add a2, a2, a3 + STORE_IDX(a1, 12) + STORE_IDX(a2, 13) + li a0, 0 + ret +ENDPROC(initjmp) +.popsection diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index bfcdc335d32..038ad78accc 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y := cache.o cpu.o state.o +obj-y := cache.o cpu.o state.o initjmp.o extra-y := start.o os.o extra-$(CONFIG_SANDBOX_SDL) += sdl.o obj-$(CONFIG_XPL_BUILD) += spl.o @@ -29,6 +29,15 @@ cmd_cc_eth-raw-os.o = $(CC) $(filter-out -nostdinc, \ $(obj)/eth-raw-os.o: $(src)/eth-raw-os.c FORCE $(call if_changed_dep,cc_eth-raw-os.o) +# initjmp.c is build in the system environment, so needs standard includes +# CFLAGS_REMOVE_initjmp.o cannot be used to drop header include path +quiet_cmd_cc_initjmp.o = CC $(quiet_modtag) $@ +cmd_cc_initjmp.o = $(CC) $(filter-out -nostdinc, \ + $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $< + +$(obj)/initjmp.o: $(src)/initjmp.c FORCE + $(call if_changed_dep,cc_initjmp.o) + # sdl.c fails to build with -fshort-wchar using musl cmd_cc_sdl.o = $(CC) $(filter-out -nostdinc -fshort-wchar, \ $(patsubst -I%,-idirafter%,$(c_flags))) -fno-lto -c -o $@ $< diff --git a/arch/sandbox/cpu/initjmp.c b/arch/sandbox/cpu/initjmp.c new file mode 100644 index 00000000000..6e72d32cb4b --- /dev/null +++ b/arch/sandbox/cpu/initjmp.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: LGPL-2.1-or-later +/* + * An implementation of initjmp() in C, that plays well with the system's + * setjmp() and longjmp() functions. + * Taken verbatim from arch/sandbox/os/setjmp.c in the barebox project. + * Modified so that initjmp() accepts a stack_size argument. + * + * Copyright (C) 2006 Anthony Liguori <anthony@codemonkey.ws> + * Copyright (C) 2011 Kevin Wolf <kwolf@redhat.com> + * Copyright (C) 2012 Alex Barcelo <abarcelo@ac.upc.edu> + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + * Copyright (C) 2025 Linaro Ltd. + * This file is partly based on pth_mctx.c, from the GNU Portable Threads + * Copyright (c) 1999-2006 Ralf S. Engelschall <rse@engelschall.com> + */ + +/* XXX Is there a nicer way to disable glibc's stack check for longjmp? */ +#ifdef _FORTIFY_SOURCE +#undef _FORTIFY_SOURCE +#endif + +#include <pthread.h> +#include <stdio.h> +#include <stdlib.h> +#include <setjmp.h> +#include <signal.h> + +typedef sigjmp_buf _jmp_buf __attribute__((aligned((16)))); +_Static_assert(sizeof(_jmp_buf) <= 512, "sigjmp_buf size exceeds expectation"); + +/* + * Information for the signal handler (trampoline) + */ +static struct { + _jmp_buf *reenter; + void (*entry)(void); + volatile sig_atomic_t called; +} tr_state; + +/* + * "boot" function + * This is what starts the coroutine, is called from the trampoline + * (from the signal handler when it is not signal handling, read ahead + * for more information). + */ +static void __attribute__((noinline, noreturn)) +coroutine_bootstrap(void (*entry)(void)) +{ + for (;;) + entry(); +} + +/* + * This is used as the signal handler. This is called with the brand new stack + * (thanks to sigaltstack). We have to return, given that this is a signal + * handler and the sigmask and some other things are changed. + */ +static void coroutine_trampoline(int signal) +{ + /* Get the thread specific information */ + tr_state.called = 1; + + /* + * Here we have to do a bit of a ping pong between the caller, given that + * this is a signal handler and we have to do a return "soon". Then the + * caller can reestablish everything and do a siglongjmp here again. + */ + if (!sigsetjmp(*tr_state.reenter, 0)) { + return; + } + + /* + * Ok, the caller has siglongjmp'ed back to us, so now prepare + * us for the real machine state switching. We have to jump + * into another function here to get a new stack context for + * the auto variables (which have to be auto-variables + * because the start of the thread happens later). Else with + * PIC (i.e. Position Independent Code which is used when PTH + * is built as a shared library) most platforms would + * horrible core dump as experience showed. + */ + coroutine_bootstrap(tr_state.entry); +} + +int __attribute__((weak)) initjmp(_jmp_buf jmp, void (*func)(void), + void *stack_base, size_t stack_size) +{ + struct sigaction sa; + struct sigaction osa; + stack_t ss; + stack_t oss; + sigset_t sigs; + sigset_t osigs; + + /* The way to manipulate stack is with the sigaltstack function. We + * prepare a stack, with it delivering a signal to ourselves and then + * put sigsetjmp/siglongjmp where needed. + * This has been done keeping coroutine-ucontext (from the QEMU project) + * as a model and with the pth ideas (GNU Portable Threads). + * See coroutine-ucontext for the basics of the coroutines and see + * pth_mctx.c (from the pth project) for the + * sigaltstack way of manipulating stacks. + */ + + tr_state.entry = func; + tr_state.reenter = (void *)jmp; + + /* + * Preserve the SIGUSR2 signal state, block SIGUSR2, + * and establish our signal handler. The signal will + * later transfer control onto the signal stack. + */ + sigemptyset(&sigs); + sigaddset(&sigs, SIGUSR2); + pthread_sigmask(SIG_BLOCK, &sigs, &osigs); + sa.sa_handler = coroutine_trampoline; + sigfillset(&sa.sa_mask); + sa.sa_flags = SA_ONSTACK; + if (sigaction(SIGUSR2, &sa, &osa) != 0) { + return -1; + } + + /* + * Set the new stack. + */ + ss.ss_sp = stack_base; + ss.ss_size = stack_size; + ss.ss_flags = 0; + if (sigaltstack(&ss, &oss) < 0) { + return -1; + } + + /* + * Now transfer control onto the signal stack and set it up. + * It will return immediately via "return" after the sigsetjmp() + * was performed. Be careful here with race conditions. The + * signal can be delivered the first time sigsuspend() is + * called. + */ + tr_state.called = 0; + pthread_kill(pthread_self(), SIGUSR2); + sigfillset(&sigs); + sigdelset(&sigs, SIGUSR2); + while (!tr_state.called) { + sigsuspend(&sigs); + } + + /* + * Inform the system that we are back off the signal stack by + * removing the alternative signal stack. Be careful here: It + * first has to be disabled, before it can be removed. + */ + sigaltstack(NULL, &ss); + ss.ss_flags = SS_DISABLE; + if (sigaltstack(&ss, NULL) < 0) { + return -1; + } + sigaltstack(NULL, &ss); + if (!(oss.ss_flags & SS_DISABLE)) { + sigaltstack(&oss, NULL); + } + + /* + * Restore the old SIGUSR2 signal handler and mask + */ + sigaction(SIGUSR2, &osa, NULL); + pthread_sigmask(SIG_SETMASK, &osigs, NULL); + + /* + * jmp can now be used to enter the trampoline again, but not as a + * signal handler. Instead it's longjmp'd to directly. + */ + return 0; +} + diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h index 4d5e861dbce..3b0717f8fa0 100644 --- a/arch/sandbox/include/asm/power-domain.h +++ b/arch/sandbox/include/asm/power-domain.h @@ -13,6 +13,8 @@ int sandbox_power_domain_query(struct udevice *dev, unsigned long id); int sandbox_power_domain_test_get(struct udevice *dev); int sandbox_power_domain_test_on(struct udevice *dev); int sandbox_power_domain_test_off(struct udevice *dev); +int sandbox_power_domain_test_on_ll(struct udevice *dev); +int sandbox_power_domain_test_off_ll(struct udevice *dev); int sandbox_power_domain_test_free(struct udevice *dev); #endif diff --git a/arch/sandbox/include/asm/serial.h b/arch/sandbox/include/asm/serial.h index 16589a1b219..41506341816 100644 --- a/arch/sandbox/include/asm/serial.h +++ b/arch/sandbox/include/asm/serial.h @@ -44,7 +44,7 @@ void sandbox_serial_endisable(bool enabled); * @buf: holds input characters available to be read by this driver */ struct sandbox_serial_priv { - struct membuff buf; + struct membuf buf; char serial_buf[16]; bool start_of_line; }; diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index 5d7beb250cd..cefe26d8fc0 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -9,4 +9,4 @@ obj-y += fdt_fixup.o interrupts.o obj-$(CONFIG_PCI) += pci_io.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o -obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_table.o +obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_table.o diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index 8ed923750f4..44ba8b52e13 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -89,8 +89,3 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, return 1; } - -bool booti_is_valid(const void *img) -{ - return false; -} diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 53b1c147c2e..2daf54e7c33 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -19,18 +19,13 @@ int dram_init(void) void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr) { - void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r; - - if (new_gd->reloc_off) { + if (new_gd->reloc_off) memcpy((void *)new_gd->relocaddr, (void *)(new_gd->relocaddr - new_gd->reloc_off), new_gd->mon_len); - reloc_board_init_r += new_gd->reloc_off; - } - __asm__ __volatile__("mov.l %0, r15\n" : : "m" (new_gd->start_addr_sp)); while (1) - reloc_board_init_r(new_gd, 0x0); + board_init_r(new_gd, 0x0); } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 006a59d6fa6..dc9483ad723 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -30,7 +30,7 @@ config X86_RUN_32BIT arch_phys_memset() can be used for basic access to other memory. config X86_RUN_64BIT - bool "64-bit" + bool "32-bit SPL followed by 64-bit U-Boot" select X86_64 select SPL if !EFI_APP select SPL_SEPARATE_BSS if !EFI_APP @@ -40,6 +40,14 @@ config X86_RUN_64BIT runs through the 16-bit and 32-bit init, then switches to 64-bit mode and jumps to U-Boot proper. +config X86_RUN_64BIT_NO_SPL + bool "64-bit" + select X86_64 + help + Build U-Boot as a 64-bit binary without SPL. As U-Boot enters + in 64-bit mode, the assumption is that the silicon is fully + initialized (MP, page tables, etc.). + endchoice config X86_64 diff --git a/arch/x86/Makefile b/arch/x86/Makefile index fd409b9f720..7dc3171cebf 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ ifeq ($(CONFIG_EFI_APP),) -ifdef CONFIG_$(XPL_)X86_64 +ifdef CONFIG_$(PHASE_)X86_64 head-y := arch/x86/cpu/start64.o else ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 39c8b0835cc..cc55c8fa39c 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -ifeq ($(CONFIG_$(XPL_)X86_64),y) +ifeq ($(CONFIG_$(PHASE_)X86_64),y) extra-y = start64.o else ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y) @@ -31,7 +31,7 @@ ifndef CONFIG_TPL_BUILD obj-y += cpu_x86.o endif -ifndef CONFIG_$(XPL_)X86_64 +ifndef CONFIG_$(PHASE_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) AFLAGS_call32.o := -fpic -fshort-wchar \ @@ -59,18 +59,18 @@ obj-$(CONFIG_QFW) += qfw_cpu.o ifndef CONFIG_SYS_COREBOOT obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += irq.o endif -ifndef CONFIG_$(XPL_)X86_64 -obj-$(CONFIG_$(XPL_)SMP) += mp_init.o +ifndef CONFIG_$(PHASE_)X86_64 +obj-$(CONFIG_$(PHASE_)SMP) += mp_init.o endif obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o -ifndef CONFIG_$(XPL_)X86_64 +ifndef CONFIG_$(PHASE_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o endif obj-y += turbo.o obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.o -ifeq ($(CONFIG_$(XPL_)X86_64),y) +ifeq ($(CONFIG_$(PHASE_)X86_64),y) obj-y += x86_64/ else obj-y += i386/ diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 039236df02d..284f16cfd91 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -298,7 +298,7 @@ static int apl_acpi_hb_write_tables(const struct udevice *dev, /* (Re)calculate length and checksum */ header->length = ctx->current - (void *)dmar; - header->checksum = table_compute_checksum((void *)dmar, header->length); + acpi_update_checksum(header); acpi_align(ctx); acpi_add_table(ctx, dmar); diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 085302c0482..66f25533b97 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -26,7 +26,7 @@ config SYS_COREBOOT imply CBMEM_CONSOLE imply X86_TSC_READ_BASE imply USE_PREBOOT - select BINMAN if X86_64 + select BINMAN if X86_RUN_64BIT select SYSINFO imply SYSINFO_EXTRA diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index fa7430b436f..d0719d1a405 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -22,7 +22,7 @@ int arch_cpu_init(void) { int ret; - ret = IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() : + ret = IS_ENABLED(CONFIG_X86_64) ? x86_cpu_reinit_f() : x86_cpu_init_f(); if (ret) return ret; diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index a8b21406ac0..c373b14df30 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -364,3 +364,27 @@ long locate_coreboot_table(void) return addr; } + +static bool has_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +static uint cpu_cpuid_extended_level(void) +{ + return cpuid_eax(0x80000000); +} + +int cpu_phys_address_size(void) +{ + if (!has_cpuid()) + return 32; + + if (cpu_cpuid_extended_level() >= 0x80000008) + return cpuid_eax(0x80000008) & 0xff; + + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + return 36; + + return 32; +} diff --git a/arch/x86/cpu/i386/call64.S b/arch/x86/cpu/i386/call64.S index 424732fa3fa..a9d3f16a6ad 100644 --- a/arch/x86/cpu/i386/call64.S +++ b/arch/x86/cpu/i386/call64.S @@ -7,6 +7,7 @@ */ #include <asm/msr-index.h> +#include <asm/processor.h> #include <asm/processor-flags.h> .code32 @@ -21,17 +22,19 @@ cpu_call64: * ecx - target */ cli + pushl $0 /* top 64-bits of target */ push %ecx /* arg2 = target */ push %edx /* arg1 = setup_base */ mov %eax, %ebx - /* Load new GDT with the 64bit segments using 32bit descriptor */ - leal gdt, %eax - movl %eax, gdt+2 - lgdt gdt + # disable paging + movl %cr0, %eax + andl $~X86_CR0_PG, %eax + movl %eax, %cr0 /* Enable PAE mode */ - movl $(X86_CR4_PAE), %eax + movl %cr4, %eax + orl $X86_CR4_PAE, %eax movl %eax, %cr4 /* Enable the boot page tables */ @@ -44,12 +47,6 @@ cpu_call64: btsl $_EFER_LME, %eax wrmsr - /* After gdt is loaded */ - xorl %eax, %eax - lldt %ax - movl $0x20, %eax - ltr %ax - /* * Setup for the jump to 64bit mode * @@ -62,22 +59,18 @@ cpu_call64: */ pop %esi /* setup_base */ - pushl $0x10 - leal lret_target, %eax - pushl %eax - /* Enter paged protected Mode, activating Long Mode */ - movl $(X86_CR0_PG | X86_CR0_PE), %eax + movl %cr0, %eax + orl $X86_CR0_PG, %eax movl %eax, %cr0 /* Jump from 32bit compatibility mode into 64bit mode. */ - lret + ljmp $(X86_GDT_ENTRY_64BIT_CS * X86_GDT_ENTRY_SIZE), $lret_target -code64: +.code64 lret_target: - pop %eax /* target */ - mov %eax, %eax /* Clear bits 63:32 */ - jmp *%eax /* Jump to the 64-bit target */ + pop %rax /* target */ + jmp *%rax /* Jump to the 64-bit target */ .globl call64_stub_size call64_stub_size: diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index a51a24498a7..ee6dbeb5c48 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -35,10 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define CPUID_FEATURE_PAE BIT(6) -#define CPUID_FEATURE_PSE36 BIT(17) -#define CPUID_FEAURE_HTT BIT(28) - /* * Constructor for a conventional segment GDT (or LDT) entry * This is a macro so it can be used in initialisers @@ -160,6 +156,9 @@ void arch_setup_gd(gd_t *new_gd) gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_64BIT_CS] = GDT_ENTRY(0xaf9b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_64BIT_TS1] = GDT_ENTRY(0x8980, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_64BIT_TS2] = 0; load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); load_ds(X86_GDT_ENTRY_32BIT_DS); @@ -409,25 +408,6 @@ static void setup_identity(void) } } -static uint cpu_cpuid_extended_level(void) -{ - return cpuid_eax(0x80000000); -} - -int cpu_phys_address_size(void) -{ - if (!has_cpuid()) - return 32; - - if (cpu_cpuid_extended_level() >= 0x80000008) - return cpuid_eax(0x80000008) & 0xff; - - if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) - return 36; - - return 32; -} - static void setup_mtrr(void) { u64 mtrr_cap; @@ -589,6 +569,13 @@ int cpu_has_64bit(void) #define PAGETABLE_BASE 0x80000 #define PAGETABLE_SIZE (6 * 4096) +#define _PRES BIT(0) /* present */ +#define _RW BIT(1) /* write allowed */ +#define _US BIT(2) /* user-access allowed */ +#define _A BIT(5) /* has been accessed */ +#define _DT BIT(6) /* has been written to */ +#define _PS BIT(7) /* indicates 2MB page size here */ + /** * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode * @@ -601,15 +588,17 @@ static void build_pagetable(uint32_t *pgtable) memset(pgtable, '\0', PAGETABLE_SIZE); /* Level 4 needs a single entry */ - pgtable[0] = (ulong)&pgtable[1024] + 7; + pgtable[0] = (ulong)&pgtable[1024] + _PRES + _RW + _US + _A; /* Level 3 has one 64-bit entry for each GiB of memory */ for (i = 0; i < 4; i++) - pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7; + pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + + _PRES + _RW + _US + _A; /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ for (i = 0; i < 2048; i++) - pgtable[2048 + i * 2] = 0x183 + (i << 21UL); + pgtable[2048 + i * 2] = _PRES + _RW + _US + _PS + _A + _DT + + (i << 21UL); } int cpu_jump_to_64bit(ulong setup_base, ulong target) diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index a28e6c77c9c..3f77f2ba2f1 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -26,10 +26,10 @@ obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o obj-y += lpss.o -obj-$(CONFIG_$(XPL_)INTEL_GENERIC_WIFI) += generic_wifi.o +obj-$(CONFIG_$(PHASE_)INTEL_GENERIC_WIFI) += generic_wifi.o ifndef CONFIG_EFI_APP obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += microcode.o -ifndef CONFIG_$(XPL_)X86_64 +ifndef CONFIG_$(PHASE_)X86_64 obj-y += microcode.o endif endif diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 471ad8d7ebc..6f6d10a405b 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -5,15 +5,15 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += cpu.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o obj-y += northbridge.o ifndef CONFIG_XPL_BUILD obj-y += sata.o endif -obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += sdram.o -ifndef CONFIG_$(XPL_)X86_32BIT_INIT +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += sdram.o +ifndef CONFIG_$(PHASE_)X86_32BIT_INIT obj-y += sdram_nop.o endif endif diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 07ea89162de..7a0f00b9b8f 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 Google, Inc + * Portions added from coreboot * * Memory Type Range Regsters - these are used to tell the CPU whether * memory is cacheable and if so the cache write mode to use. @@ -16,6 +17,7 @@ * since the MTRR registers are sometimes in flux. */ +#include <cpu.h> #include <cpu_func.h> #include <log.h> #include <sort.h> @@ -39,6 +41,27 @@ static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = { "Back", }; +u64 mtrr_to_size(u64 mask) +{ + u64 size; + + size = ~mask & ((1ULL << cpu_phys_address_size()) - 1); + size |= (1 << 12) - 1; + size += 1; + + return size; +} + +u64 mtrr_to_mask(u64 size) +{ + u64 mask; + + mask = ~(size - 1); + mask &= (1ull << cpu_phys_address_size()) - 1; + + return mask; +} + /* Prepare to adjust MTRRs */ void mtrr_open(struct mtrr_state *state, bool do_caches) { @@ -68,11 +91,9 @@ void mtrr_close(struct mtrr_state *state, bool do_caches) static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size) { - u64 mask; + u64 mask = mtrr_to_mask(size); wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type); - mask = ~(size - 1); - mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID); } @@ -184,30 +205,80 @@ int mtrr_commit(bool do_caches) return 0; } -int mtrr_add_request(int type, uint64_t start, uint64_t size) +/* fms: find most significant bit set (from Linux) */ +static inline uint fms(uint val) +{ + uint ret; + + __asm__("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (ret) : "mr" (val)); + + return ret; +} + +/* + * fms64: find most significant bit set in a 64-bit word + * As samples, fms64(0x0) = 0; fms64(0x4400) = 14; + * fms64(0x40400000000) = 42. + */ +static uint fms64(uint64_t val) +{ + u32 hi = (u32)(val >> 32); + + if (!hi) + return fms((u32)val); + + return fms(hi) + 32; +} + +int mtrr_add_request(int type, u64 base, uint64_t size) { struct mtrr_request *req; - uint64_t mask; + u64 mask; debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count); if (!gd->arch.has_mtrr) return -ENOSYS; - if (!is_power_of_2(size)) - return -EINVAL; - - if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) - return -ENOSPC; - req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; - req->type = type; - req->start = start; - req->size = size; - debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1, - req->type, req->start, req->size); - mask = ~(req->size - 1); - mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; - mask |= MTRR_PHYS_MASK_VALID; - debug(" %016llx %016llx\n", req->start | req->type, mask); + while (size) { + uint addr_lsb; + uint size_msb; + u64 mtrr_size; + + addr_lsb = fls64(base); + size_msb = fms64(size); + + /* + * All MTRR entries need to have their base aligned to the + * mask size. The maximum size is calculated by a function of + * the min base bit set and maximum size bit set. + * Algorithm is from coreboot + */ + if (!addr_lsb || addr_lsb > size_msb) + mtrr_size = 1ull << size_msb; + else + mtrr_size = 1ull << addr_lsb; + log_debug("addr_lsb %x size_msb %x mtrr_size %llx\n", + addr_lsb, size_msb, mtrr_size); + + if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) + return -ENOSPC; + req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; + req->type = type; + req->start = base; + req->size = mtrr_size; + log_debug("%d: type=%d, %08llx %08llx ", + gd->arch.mtrr_req_count - 1, req->type, req->start, + req->size); + mask = mtrr_to_mask(req->size); + mask |= MTRR_PHYS_MASK_VALID; + log_debug(" %016llx %016llx\n", req->start | req->type, mask); + + size -= mtrr_size; + base += mtrr_size; + } return 0; } @@ -360,9 +431,7 @@ int mtrr_list(int reg_count, int cpu_select) base = info.mtrr[i].base; mask = info.mtrr[i].mask; - size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1); - size |= (1 << 12) - 1; - size += 1; + size = mtrr_to_size(mask); valid = mask & MTRR_PHYS_MASK_VALID; type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK]; printf("%d %-5s %-12s %016llx %016llx %016llx\n", i, diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 1439916ac2d..2134b0d8654 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> -ifndef CONFIG_$(XPL_)X86_64 +ifndef CONFIG_$(PHASE_)X86_64 obj-y += car.o endif obj-y += dram.o diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index 62a301c0fd3..ba3638e6acc 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -4,7 +4,9 @@ */ #include <init.h> +#include <spl.h> #include <asm/global_data.h> +#include <asm/mtrr.h> #include <asm/post.h> #include <asm/arch/qemu.h> #include <linux/sizes.h> @@ -44,6 +46,22 @@ int dram_init(void) gd->ram_size += qemu_get_high_memory_size(); post_code(POST_DRAM); + if (xpl_phase() == PHASE_BOARD_F) { + u64 total = gd->ram_size; + int ret; + + if (total > SZ_2G + SZ_1G) + total += SZ_1G; + ret = mtrr_add_request(MTRR_TYPE_WRBACK, 0, total); + if (ret != -ENOSYS) { + if (ret) + return log_msg_ret("mta", ret); + ret = mtrr_commit(false); + if (ret) + return log_msg_ret("mtc", ret); + } + } + return 0; } diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index 17a04f86479..078d1d86b02 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -6,6 +6,7 @@ * (C) Copyright 2019 Bin Meng <bmeng.cn@gmail.com> */ +#include <bloblist.h> #include <env_internal.h> #include <malloc.h> #include <asm/e820.h> @@ -19,51 +20,34 @@ unsigned int install_e820_map(unsigned int max_entries, struct e820_entry *entries) { u64 high_mem_size; - int n = 0; + struct e820_ctx ctx; - entries[n].addr = 0; - entries[n].size = ISA_START_ADDRESS; - entries[n].type = E820_RAM; - n++; + e820_init(&ctx, entries, max_entries); - entries[n].addr = ISA_START_ADDRESS; - entries[n].size = ISA_END_ADDRESS - ISA_START_ADDRESS; - entries[n].type = E820_RESERVED; - n++; + e820_next(&ctx, E820_RAM, ISA_START_ADDRESS); + e820_next(&ctx, E820_RESERVED, ISA_END_ADDRESS); /* - * since we use memalign(malloc) to allocate high memory for - * storing ACPI tables, we need to reserve them in e820 tables, - * otherwise kernel will reclaim them and data will be corrupted + * if we use bloblist to allocate high memory for storing ACPI tables, + * we need to reserve that region in e820 tables, otherwise the kernel + * will reclaim them and data will be corrupted. The ACPI tables may not + * have been written yet, so use the whole bloblist size */ - entries[n].addr = ISA_END_ADDRESS; - entries[n].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; - entries[n].type = E820_RAM; - n++; - - /* for simplicity, reserve entire malloc space */ - entries[n].addr = gd->relocaddr - TOTAL_MALLOC_LEN; - entries[n].size = TOTAL_MALLOC_LEN; - entries[n].type = E820_RESERVED; - n++; - - entries[n].addr = gd->relocaddr; - entries[n].size = qemu_get_low_memory_size() - gd->relocaddr; - entries[n].type = E820_RESERVED; - n++; - - entries[n].addr = CONFIG_PCIE_ECAM_BASE; - entries[n].size = CONFIG_PCIE_ECAM_SIZE; - entries[n].type = E820_RESERVED; - n++; + if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) { + e820_to_addr(&ctx, E820_RAM, (ulong)gd->bloblist); + e820_next(&ctx, E820_ACPI, bloblist_get_total_size()); + } else { + /* If using memalign() reserve that whole region instead */ + e820_to_addr(&ctx, E820_RAM, gd->relocaddr - TOTAL_MALLOC_LEN); + e820_next(&ctx, E820_ACPI, TOTAL_MALLOC_LEN); + } + e820_to_addr(&ctx, E820_RAM, qemu_get_low_memory_size()); + e820_add(&ctx, E820_RESERVED, CONFIG_PCIE_ECAM_BASE, + CONFIG_PCIE_ECAM_SIZE); high_mem_size = qemu_get_high_memory_size(); - if (high_mem_size) { - entries[n].addr = SZ_4G; - entries[n].size = high_mem_size; - entries[n].type = E820_RAM; - n++; - } + if (high_mem_size) + e820_add(&ctx, E820_RAM, SZ_4G, high_mem_size); - return n; + return e820_finish(&ctx); } diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 563f63e2bc8..e846ccd44aa 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -15,14 +15,21 @@ #include <asm/arch/qemu.h> #include <asm/u-boot-x86.h> -static bool i440fx; - #if CONFIG_IS_ENABLED(QFW_PIO) U_BOOT_DRVINFO(x86_qfw_pio) = { .name = "qfw_pio", }; #endif +static bool is_i440fx(void) +{ + u16 device; + + pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); + + return device == PCI_DEVICE_ID_INTEL_82441; +} + static void enable_pm_piix(void) { u8 en; @@ -50,16 +57,17 @@ static void enable_pm_ich9(void) void qemu_chipset_init(void) { - u16 device, xbcs; + bool i440fx; + u16 xbcs; int pam, i; + i440fx = is_i440fx(); + /* * i440FX and Q35 chipset have different PAM register offset, but with * the same bitfield layout. Here we determine the offset based on its * PCI device ID. */ - pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device); - i440fx = (device == PCI_DEVICE_ID_INTEL_82441); pam = i440fx ? I440FX_PAM : Q35_PAM; /* @@ -123,7 +131,7 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) { u8 irq; - if (i440fx) { + if (is_i440fx()) { /* * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not * connected to I/O APIC INTPIN#16-19. Instead they are routed diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 0ef27cc5a00..385a691265e 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -254,7 +254,7 @@ multiboot_header: * GDT is setup in a safe location in RAM */ gdt_ptr2: - .word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */ + .word gdt2_end - gdt_ptr2 - 1 .long gdt_rom2 /* base */ /* Some CPUs are picky about GDT alignment... */ @@ -313,4 +313,6 @@ gdt_rom2: .byte 0x93 /* access */ .byte 0xcf /* flags + limit_high */ .byte 0x00 /* base_high */ +gdt2_end: + #endif diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S index 865a49731e5..8d9acb193e0 100644 --- a/arch/x86/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -61,7 +61,7 @@ idt_ptr: * GDT is setup in a safe location in RAM */ gdt_ptr: - .word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */ + .word gdt_end - gdt_rom - 1 .long BOOT_SEG + gdt_rom /* base */ /* Some CPUs are picky about GDT alignment... */ @@ -120,3 +120,4 @@ gdt_rom: .byte 0x93 /* access */ .byte 0xcf /* flags + limit_high */ .byte 0x00 /* base_high */ +gdt_end: diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 71bc07f872a..25ae92c702f 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -59,11 +59,6 @@ int x86_cpu_reinit_f(void) return 0; } -int cpu_phys_address_size(void) -{ - return CONFIG_CPU_ADDR_BITS; -} - int x86_cpu_init_f(void) { return 0; diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index ac4865300f1..657d920b14f 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -122,6 +122,14 @@ struct efi_info { __u32 efi_memmap_hi; }; +/* Gleaned from OFW's set-parameters in cpu/x86/pc/linux.fth */ +struct olpc_ofw_header { + __u32 ofw_magic; /* OFW signature */ + __u32 ofw_version; + __u32 cif_handler; /* callback into OFW */ + __u32 irq_desc_table; +} __attribute__((packed)); + /* The so-called "zeropage" */ struct boot_params { struct screen_info screen_info; /* 0x000 */ @@ -134,7 +142,12 @@ struct boot_params { __u8 hd0_info[16]; /* obsolete! */ /* 0x080 */ __u8 hd1_info[16]; /* obsolete! */ /* 0x090 */ struct sys_desc_table sys_desc_table; /* 0x0a0 */ - __u8 _pad4[144]; /* 0x0b0 */ + struct olpc_ofw_header olpc_ofw_header; /* 0x0b0 */ + __u32 ext_ramdisk_image; /* 0x0c0 */ + __u32 ext_ramdisk_size; /* 0x0c4 */ + __u32 ext_cmd_line_ptr; /* 0x0c8 */ + __u8 _pad4[112]; /* 0x0cc */ + __u32 cc_blob_address; /* 0x13c */ struct edid_info edid_info; /* 0x140 */ struct efi_info efi_info; /* 0x1c0 */ __u32 alt_mem_k; /* 0x1e0 */ diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index fd389d4024c..5d24c17f8a3 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -58,6 +58,10 @@ enum { X86_SYSCON_PUNIT, /* Power unit */ }; +#define CPUID_FEATURE_PAE BIT(6) +#define CPUID_FEATURE_PSE36 BIT(17) +#define CPUID_FEAURE_HTT BIT(28) + struct cpuid_result { uint32_t eax; uint32_t ebx; @@ -105,68 +109,47 @@ static inline struct cpuid_result cpuid_ext(int op, unsigned ecx) return result; } -/* - * CPUID functions returning a single datum - */ -static inline unsigned int cpuid_eax(unsigned int op) +static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) { - unsigned int eax; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax) - : "0" (op) - : "ecx", "edx", "edi"); - return eax; + /* ecx is often an input as well as an output. */ + asm volatile("cpuid" + : "=a" (*eax), + "=b" (*ebx), + "=c" (*ecx), + "=d" (*edx) + : "0" (*eax), "2" (*ecx) + : "memory"); } -static inline unsigned int cpuid_ebx(unsigned int op) -{ - unsigned int eax, ebx; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=S" (ebx) - : "0" (op) - : "ecx", "edx", "edi"); - return ebx; +#define native_cpuid_reg(reg) \ +static inline unsigned int cpuid_##reg(unsigned int op) \ +{ \ + unsigned int eax = op, ebx, ecx = 0, edx; \ + \ + native_cpuid(&eax, &ebx, &ecx, &edx); \ + \ + return reg; \ } -static inline unsigned int cpuid_ecx(unsigned int op) -{ - unsigned int eax, ecx; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=c" (ecx) - : "0" (op) - : "edx", "edi"); - return ecx; -} +/* + * Native CPUID functions returning a single datum. + */ +native_cpuid_reg(eax) +native_cpuid_reg(ebx) +native_cpuid_reg(ecx) +native_cpuid_reg(edx) -static inline unsigned int cpuid_edx(unsigned int op) +#if CONFIG_IS_ENABLED(X86_64) +static inline int flag_is_changeable_p(u32 flag) { - unsigned int eax, edx; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=d" (edx) - : "0" (op) - : "ecx", "edi"); - return edx; + return 1; } - -#if !CONFIG_IS_ENABLED(X86_64) - +#else /* Standard macro to see if a specific flag is changeable */ -static inline int flag_is_changeable_p(uint32_t flag) +static inline int flag_is_changeable_p(u32 flag) { - uint32_t f1, f2; + u32 f1, f2; asm( "pushfl\n\t" @@ -181,9 +164,9 @@ static inline int flag_is_changeable_p(uint32_t flag) "popfl\n\t" : "=&r" (f1), "=&r" (f2) : "ir" (flag)); - return ((f1^f2) & flag) != 0; + return ((f1 ^ f2) & flag) != 0; } -#endif +#endif /* X86_64 */ /** * cpu_enable_paging_pae() - Enable PAE-paging diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 1ab709abfc8..a535818b2d5 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -3,6 +3,8 @@ #define E820MAX 128 /* number of entries in E820MAP */ +#ifdef __ASSEMBLY__ + #define E820_RAM 1 #define E820_RESERVED 2 #define E820_ACPI 3 @@ -10,9 +12,21 @@ #define E820_UNUSABLE 5 #define E820_COUNT 6 /* Number of types */ -#ifndef __ASSEMBLY__ +#else + #include <linux/types.h> +/* Available e820 memory-region types */ +enum e820_type { + E820_RAM = 1, + E820_RESERVED, + E820_ACPI, + E820_NVS, + E820_UNUSABLE, + + E820_COUNT, +}; + struct e820_entry { __u64 addr; /* start of memory segment */ __u64 size; /* size of memory segment */ @@ -22,11 +36,82 @@ struct e820_entry { #define ISA_START_ADDRESS 0xa0000 #define ISA_END_ADDRESS 0x100000 +/** + * Context to use for e820_add() + * + * @entries: Table being filled in + * @addr: Current address we are up to + * @count: Number of entries added to @entries so far + * @max_entries: Maximum number of entries allowed + */ +struct e820_ctx { + struct e820_entry *entries; + u64 addr; + int count; + int max_entries; +}; + +/** + * e820_init() - Start setting up an e820 table + * + * @ctx: Context to set up + * @entries: Place to put entries + * @max_entries: Maximum size of @entries + */ +void e820_init(struct e820_ctx *ctx, struct e820_entry *entries, + int max_entries); + +/** + * e820_add() - Add an entry to the table + * + * @ctx: Context + * @type: Type of entry + * @addr: Start address of entry + * @size Size of entry + */ +void e820_add(struct e820_ctx *ctx, enum e820_type type, u64 addr, u64 size); + +/** + * e820_to_addr() - Add an entry that covers the space up to a given address + * + * @ctx: Context + * @type: Type of entry + * @end_addr: Address where the entry should finish + */ +void e820_to_addr(struct e820_ctx *ctx, enum e820_type type, u64 end_addr); + +/** + * e820_next() - Add an entry that carries on from the last one + * + * @ctx: Context + * @type: Type of entry + * @size Size of entry + */ +void e820_next(struct e820_ctx *ctx, enum e820_type type, u64 size); + +/** + * e820_finish() - Finish the table + * + * Checks the table is not too large, panics if so + * + * @ctx: Context + * Returns: Number of entries + */ +int e820_finish(struct e820_ctx *ctx); + /* Implementation-defined function to install an e820 map */ unsigned int install_e820_map(unsigned int max_entries, struct e820_entry *); /** + * e820_dump() - Dump the e820 table + * + * @entries: Pointer to start of table + * @count: Number of entries in the table + */ +void e820_dump(struct e820_entry *entries, uint count); + +/** * cb_install_e820_map() - Install e820 map provided by coreboot sysinfo * * This should be used when booting from coreboot, since in that case the @@ -39,6 +124,14 @@ unsigned int install_e820_map(unsigned int max_entries, unsigned int cb_install_e820_map(unsigned int max_entries, struct e820_entry *entries); +/** + * e820_dump() - Dump an e820 table + * + * @entries: Pointer to first entry + * @count: Number of entries in the table + */ +void e820_dump(struct e820_entry *entries, uint count); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_E820_H */ diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index e23fb2c8e72..c689fc23d08 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -10,6 +10,7 @@ #ifndef __ASM_INTERRUPT_H_ #define __ASM_INTERRUPT_H_ 1 +#include <stdbool.h> #include <asm/types.h> #define SYS_NUM_IRQS 16 diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index af5f9a11980..39dc7b33aa0 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -59,15 +59,14 @@ static inline unsigned long long native_read_tscp(unsigned int *aux) * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, * it means rax *or* rdx. */ -#ifdef CONFIG_X86_64 -#define DECLARE_ARGS(val, low, high) unsigned low, high -#define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) -#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) +#if CONFIG_IS_ENABLED(X86_64) +/* Using 64-bit values saves one instruction clearing the high half of low */ +#define DECLARE_ARGS(val, low, high) unsigned long low, high +#define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) #else #define DECLARE_ARGS(val, low, high) unsigned long long val #define EAX_EDX_VAL(val, low, high) (val) -#define EAX_EDX_ARGS(val, low, high) "A" (val) #define EAX_EDX_RET(val, low, high) "=A" (val) #endif diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 2e995f54061..67e897daa25 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -91,6 +91,22 @@ struct mtrr_info { }; /** + * mtrr_to_size() - Convert a mask to a size value + * + * @mask: Value of the mask register + * Return: associated size + */ +u64 mtrr_to_size(u64 mask); + +/** + * mtrr_to_mask() - Convert a size to a mask value + * + * @size: Value of the size register + * Return: associated mask, without MTRR_PHYS_MASK_VALID + */ +u64 mtrr_to_mask(u64 size); + +/** * mtrr_open() - Prepare to adjust MTRRs * * Use mtrr_open() passing in a structure - this function will init it. Then diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index d7b68367861..ad8240be387 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -18,7 +18,10 @@ #define X86_GDT_ENTRY_16BIT_DS 6 #define X86_GDT_ENTRY_16BIT_FLAT_CS 7 #define X86_GDT_ENTRY_16BIT_FLAT_DS 8 -#define X86_GDT_NUM_ENTRIES 9 +#define X86_GDT_ENTRY_64BIT_CS 9 +#define X86_GDT_ENTRY_64BIT_TS1 10 +#define X86_GDT_ENTRY_64BIT_TS2 11 +#define X86_GDT_NUM_ENTRIES 12 #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 4ed6d8d5cc2..8b542605170 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -10,8 +10,6 @@ #include <asm/bootparam.h> #include <asm/e820.h> -struct bootm_info; - /* linux i386 zImage/bzImage header. Offsets relative to * the start of the image */ @@ -45,27 +43,64 @@ enum { }; /** + * struct zboot_state - Current state of the boot + * + * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already + * been loaded and does not exist (as a cohesive whole) in memory + * @bzimage_size: Size of the bzImage, or 0 to detect this + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @load_address: Address where the bzImage is moved before booting, either + * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR + * This is set up when loading the zimage + * @base_ptr: Pointer to the boot parameters, typically at address + * DEFAULT_SETUP_BASE + * This is set up when loading the zimage + * @cmdline: Environment variable containing the 'override' command line, or + * NULL to use the one in the setup block + */ +struct zboot_state { + ulong bzimage_addr; + ulong bzimage_size; + ulong initrd_addr; + ulong initrd_size; + ulong load_address; + struct boot_params *base_ptr; + const char *cmdline; +}; + +extern struct zboot_state state; + +/** + * zimage_dump() - Dump information about a zimage + * + * @base_ptr: Pointer to the boot parameters + * @show_cmdline: true to show the kernel command line + */ +void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); + +/** * zboot_load() - Load a zimage * * Load the zimage into the correct place * * Return: 0 if OK, -ve on error */ -int zboot_load(struct bootm_info *bmi); +int zboot_load(void); /** * zboot_setup() - Set up the zboot image reeady for booting * * Return: 0 if OK, -ve on error */ -int zboot_setup(struct bootm_info *bmi); +int zboot_setup(void); /** * zboot_go() - Start the image * * Return: 0 if OK, -ve on error */ -int zboot_go(struct bootm_info *bmi); +int zboot_go(void); /** * load_zimage() - Load a zImage or bzImage @@ -104,7 +139,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, * * Record information about a zimage so it can be booted * - * @bmi: Bootm information * @bzimage_addr: Address of the bzImage to boot * @bzimage_size: Size of the bzImage, or 0 to detect this * @initrd_addr: Address of the initial ramdisk, or 0 if none @@ -115,17 +149,14 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, * @cmdline: Environment variable containing the 'override' command line, or * NULL to use the one in the setup block */ -void zboot_start(struct bootm_info *bmi, ulong bzimage_addr, ulong bzimage_size, - ulong initrd_addr, ulong initrd_size, ulong base_addr, - const char *cmdline); +void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr, + ulong initrd_size, ulong base_addr, const char *cmdline); /** * zboot_info() - Show simple info about a zimage * - * Shows where the kernel was loaded and also the setup base - * - * @bmi: Bootm information + * Shows wherer the kernel was loaded and also the setup base */ -void zboot_info(struct bootm_info *bmi); +void zboot_info(void); #endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 43e6a1de77d..afb6abb57d3 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -19,14 +19,16 @@ ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o endif obj-y += cmd_boot.o -obj-$(CONFIG_$(XPL_)COREBOOT_SYSINFO) += coreboot/ +obj-$(CONFIG_$(PHASE_)COREBOOT_SYSINFO) += coreboot/ obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o obj-y += e820.o obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o +ifndef CONFIG_XPL_BUILD obj-y += mpspec.o +endif obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_nhlt.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o @@ -90,7 +92,7 @@ endif ifdef CONFIG_EFI_STUB -ifeq ($(CONFIG_$(XPL_)X86_64),) +ifeq ($(CONFIG_$(PHASE_)X86_64),) extra-y += $(EFI_CRT0) $(EFI_RELOC) endif diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 880ef31df7d..8aae5fa5af7 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -414,7 +414,7 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, cur.start = (void *)header; nhlt_serialise_endpoints(nhlt, &cur); - header->checksum = table_compute_checksum(header, sz); + acpi_update_checksum(header); nhlt_free_resources(nhlt); assert(cur.buf - cur.start == sz); diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 3186e48d63b..b13292c4150 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -173,7 +173,7 @@ int acpi_write_tcpa(struct acpi_ctx *ctx, const struct acpi_writer *entry) /* (Re)calculate length and checksum */ current = (u32)tcpa + sizeof(struct acpi_tcpa); header->length = current - (u32)tcpa; - header->checksum = table_compute_checksum(tcpa, header->length); + acpi_update_checksum(header); acpi_inc(ctx, tcpa->header.length); acpi_add_table(ctx, tcpa); @@ -242,7 +242,7 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx, tpm2->lasa = nomap_to_sysmem(lasa); /* Calculate checksum. */ - header->checksum = table_compute_checksum(tpm2, header->length); + acpi_update_checksum(header); acpi_inc(ctx, tpm2->header.length); acpi_add_table(ctx, tpm2); @@ -279,9 +279,7 @@ int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry) * patched the GNVS address. Set the checksum to zero since it * is part of the region being checksummed. */ - ctx->dsdt->checksum = 0; - ctx->dsdt->checksum = table_compute_checksum((void *)ctx->dsdt, - ctx->dsdt->length); + acpi_update_checksum(ctx->dsdt); } /* Fill in platform-specific global NVS variables */ @@ -330,8 +328,7 @@ static int acpi_create_hpet(struct acpi_hpet *hpet) hpet->number = 0; hpet->min_tick = 0; /* HPET_MIN_TICKS */ - header->checksum = table_compute_checksum(hpet, - sizeof(struct acpi_hpet)); + acpi_update_checksum(header); return 0; } diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 03f7360032c..de4578666fb 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -5,6 +5,9 @@ * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2009-2010 coresystems GmbH */ + +#define LOG_CATEGRORY LOGC_ARCH + #include <compiler.h> #include <bios_emul.h> #include <irq_func.h> @@ -228,7 +231,11 @@ static void vbe_set_graphics(int vesa_mode, struct vesa_state *mode_info) { unsigned char *framebuffer; - mode_info->video_mode = (1 << 14) | vesa_mode; + /* + * bit 14 is linear-framebuffer mode + * bit 15 means don't clear the display + */ + mode_info->video_mode = (1 << 14) | (1 << 15) | vesa_mode; vbe_get_mode_info(mode_info); framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr; @@ -298,16 +305,14 @@ asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses, cs = cs_ip >> 16; flags = stackflags; -#ifdef CONFIG_REALMODE_DEBUG - debug("oprom: INT# 0x%x\n", intnumber); - debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", - eax, ebx, ecx, edx); - debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", - ebp, esp, edi, esi); - debug("oprom: ip: %04x cs: %04x flags: %08x\n", - ip, cs, flags); - debug("oprom: stackflags = %04x\n", stackflags); -#endif + log_debug("oprom: INT# 0x%x\n", intnumber); + log_debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", + eax, ebx, ecx, edx); + log_debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", + ebp, esp, edi, esi); + log_debug("oprom: ip: %04x cs: %04x flags: %08x\n", + ip, cs, flags); + log_debug("oprom: stackflags = %04x\n", stackflags); /* * Fetch arguments from the stack and put them to a place diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index b2cf1527b1c..e0c2284a901 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -7,6 +7,8 @@ * Copyright (C) 2007-2009 coresystems GmbH */ +#define LOG_CATEGRORY LOGC_ARCH + #include <log.h> #include <asm/pci.h> #include "bios_emul.h" @@ -198,10 +200,8 @@ int int1a_handler(void) dm_pci_write_config32(dev, reg, dword); break; } -#ifdef CONFIG_REALMODE_DEBUG - debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, - bus, devfn, reg, M.x86.R_ECX); -#endif + log_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, + bus, devfn, reg, M.x86.R_ECX); M.x86.R_EAX &= 0xffff00ff; /* Clear AH */ M.x86.R_EAX |= PCIBIOS_SUCCESSFUL; retval = 1; diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index d478b7486e3..bcc5f6f3044 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -3,13 +3,39 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ +#define LOG_CATEGORY LOGC_ARCH + #include <efi_loader.h> #include <lmb.h> +#include <log.h> #include <asm/e820.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +static const char *const e820_type_name[E820_COUNT] = { + [E820_RAM] = "RAM", + [E820_RESERVED] = "Reserved", + [E820_ACPI] = "ACPI", + [E820_NVS] = "ACPI NVS", + [E820_UNUSABLE] = "Unusable", +}; + +void e820_dump(struct e820_entry *entries, uint count) +{ + int i; + + printf("%12s %10s %s\n", "Addr", "Size", "Type"); + for (i = 0; i < count; i++) { + struct e820_entry *entry = &entries[i]; + + printf("%12llx %10llx %s\n", entry->addr, entry->size, + entry->type < E820_COUNT ? + e820_type_name[entry->type] : + simple_itoa(entry->type)); + } +} + /* * Install a default e820 table with 4 entries as follows: * @@ -37,6 +63,50 @@ __weak unsigned int install_e820_map(unsigned int max_entries, return 4; } +void e820_init(struct e820_ctx *ctx, struct e820_entry *entries, + int max_entries) +{ + memset(ctx, '\0', sizeof(*ctx)); + ctx->entries = entries; + ctx->max_entries = max_entries; +} + +void e820_add(struct e820_ctx *ctx, enum e820_type type, u64 addr, u64 size) +{ + struct e820_entry *entry = &ctx->entries[ctx->count++]; + + if (ctx->count <= ctx->max_entries) { + entry->addr = addr; + entry->size = size; + entry->type = type; + } + ctx->addr = addr + size; +} + +void e820_next(struct e820_ctx *ctx, enum e820_type type, u64 size) +{ + e820_add(ctx, type, ctx->addr, size); +} + +void e820_to_addr(struct e820_ctx *ctx, enum e820_type type, u64 addr) +{ + e820_next(ctx, type, addr - ctx->addr); +} + +int e820_finish(struct e820_ctx *ctx) +{ + if (ctx->count > ctx->max_entries) { + printf("e820 has %d entries but room for only %d\n", ctx->count, + ctx->max_entries); + panic("e820 table too large"); + } + log_debug("e820 map installed, n=%d\n", ctx->count); + if (_DEBUG) + e820_dump(ctx->entries, ctx->count); + + return ctx->count; +} + #if CONFIG_IS_ENABLED(EFI_LOADER) void efi_add_known_memory(void) { diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c index 465ff70146f..088f78f4661 100644 --- a/arch/x86/lib/i8259.c +++ b/arch/x86/lib/i8259.c @@ -13,6 +13,8 @@ * Programmable Interrupt Controllers. */ +#define LOG_CATEGORY UCLASS_IRQ + #include <log.h> #include <asm/io.h> #include <asm/i8259.h> diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 7a033505101..0a6a761987e 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -84,8 +84,6 @@ static int x86_spl_init(void) log_debug("x86 spl starting\n"); if (IS_ENABLED(TPL)) ret = x86_cpu_reinit_f(); - else - ret = x86_cpu_init_f(); ret = spl_init(); if (ret) { log_debug("spl_init() failed (err=%d)\n", ret); @@ -283,7 +281,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { int ret; - printf("Jumping to 64-bit U-Boot: Note many features are missing\n"); + log_debug("Jumping to 64-bit U-Boot\n"); ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); debug("ret=%d\n", ret); hang(); diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 44fe80c5224..ec52992209f 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -45,6 +45,13 @@ struct table_info { int align; }; +/* QEMU's tables include quite a bit of empty space */ +#ifdef CONFIG_QEMU +#define ACPI_SIZE (192 << 10) +#else +#define ACPI_SIZE SZ_64K +#endif + static struct table_info table_list[] = { #ifdef CONFIG_GENERATE_PIRQ_TABLE { "pirq", write_pirq_routing_table }, @@ -60,7 +67,7 @@ static struct table_info table_list[] = { * that the calculation of gd->table_end works properly */ #ifdef CONFIG_GENERATE_ACPI_TABLE - { "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, SZ_64K, SZ_4K}, + { "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, ACPI_SIZE, SZ_4K}, #endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE /* diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index ba7a008fec7..2ea9bcf59c2 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -55,6 +55,9 @@ DECLARE_GLOBAL_DATA_PTR; #define COMMAND_LINE_SIZE 2048 +/* Current state of the boot */ +struct zboot_state state; + static void build_command_line(char *command_line, int auto_boot) { char *env_command_line; @@ -222,7 +225,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, else *load_addressp = ZIMAGE_LOAD_ADDR; - printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base); + printf("Building boot_params at %lx\n", (ulong)setup_base); memset(setup_base, 0, sizeof(*setup_base)); setup_base->hdr = params->hdr; @@ -298,10 +301,13 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, hdr->type_of_loader = 0x80; /* U-Boot version 0 */ if (initrd_addr) { printf("Initial RAM disk at linear address " - "0x%08lx, size %ld bytes\n", - initrd_addr, initrd_size); + "%lx, size %lx (%ld bytes)\n", + initrd_addr, initrd_size, initrd_size); hdr->ramdisk_image = initrd_addr; + setup_base->ext_ramdisk_image = 0; + setup_base->ext_ramdisk_size = 0; + setup_base->ext_cmd_line_ptr = 0; hdr->ramdisk_size = initrd_size; } } @@ -363,55 +369,54 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -int zboot_load(struct bootm_info *bmi) +int zboot_load(void) { struct boot_params *base_ptr; int ret; - if (bmi->base_ptr) { - struct boot_params *from = (struct boot_params *)bmi->base_ptr; + if (state.base_ptr) { + struct boot_params *from = (struct boot_params *)state.base_ptr; base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE; - log_debug("Building boot_params at 0x%8.8lx\n", - (ulong)base_ptr); + log_debug("Building boot_params at %lx\n", (ulong)base_ptr); memset(base_ptr, '\0', sizeof(*base_ptr)); base_ptr->hdr = from->hdr; } else { - base_ptr = load_zimage((void *)bmi->bzimage_addr, - bmi->bzimage_size, &bmi->load_address); + base_ptr = load_zimage((void *)state.bzimage_addr, state.bzimage_size, + &state.load_address); if (!base_ptr) { puts("## Kernel loading failed ...\n"); return -EINVAL; } } - bmi->base_ptr = base_ptr; + state.base_ptr = base_ptr; - ret = env_set_hex("zbootbase", map_to_sysmem(bmi->base_ptr)); + ret = env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)); if (!ret) - ret = env_set_hex("zbootaddr", bmi->load_address); + ret = env_set_hex("zbootaddr", state.load_address); if (ret) return ret; return 0; } -int zboot_setup(struct bootm_info *bmi) +int zboot_setup(void) { - struct boot_params *base_ptr = bmi->base_ptr; + struct boot_params *base_ptr = state.base_ptr; int ret; ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, - 0, bmi->initrd_addr, bmi->initrd_size, - (ulong)bmi->cmdline); + 0, state.initrd_addr, state.initrd_size, + (ulong)state.cmdline); if (ret) return -EINVAL; return 0; } -int zboot_go(struct bootm_info *bmi) +int zboot_go(void) { - struct boot_params *params = bmi->base_ptr; + struct boot_params *params = state.base_ptr; struct setup_header *hdr = ¶ms->hdr; bool image_64bit; ulong entry; @@ -419,51 +424,38 @@ int zboot_go(struct bootm_info *bmi) disable_interrupts(); - entry = bmi->load_address; + entry = state.load_address; image_64bit = false; - if (IS_ENABLED(CONFIG_X86_RUN_64BIT) && + if (IS_ENABLED(CONFIG_X86_64) && (hdr->xloadflags & XLF_KERNEL_64)) { image_64bit = true; } /* we assume that the kernel is in place */ - ret = boot_linux_kernel((ulong)bmi->base_ptr, entry, image_64bit); + ret = boot_linux_kernel((ulong)state.base_ptr, entry, image_64bit); return ret; } -int zboot_run(struct bootm_info *bmi) +int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size, + ulong base, char *cmdline) { int ret; - ret = zboot_load(bmi); + zboot_start(addr, size, initrd, initrd_size, base, cmdline); + ret = zboot_load(); if (ret) return log_msg_ret("ld", ret); - ret = zboot_setup(bmi); + ret = zboot_setup(); if (ret) return log_msg_ret("set", ret); - ret = zboot_go(bmi); + ret = zboot_go(); if (ret) return log_msg_ret("go", ret); return -EFAULT; } -int zboot_run_args(ulong addr, ulong size, ulong initrd, ulong initrd_size, - ulong base, char *cmdline) -{ - struct bootm_info bmi; - int ret; - - bootm_init(&bmi); - zboot_start(&bmi, addr, size, initrd, initrd_size, base, cmdline); - ret = zboot_run(&bmi); - if (ret) - return log_msg_ret("zra", ret); - - return 0; -} - static void print_num(const char *name, ulong value) { printf("%-20s: %lx\n", name, value); @@ -474,14 +466,6 @@ static void print_num64(const char *name, u64 value) printf("%-20s: %llx\n", name, value); } -static const char *const e820_type_name[E820_COUNT] = { - [E820_RAM] = "RAM", - [E820_RESERVED] = "Reserved", - [E820_ACPI] = "ACPI", - [E820_NVS] = "ACPI NVS", - [E820_UNUSABLE] = "Unusable", -}; - static const char *const bootloader_id[] = { "LILO", "Loadlin", @@ -565,28 +549,17 @@ static void show_loader(struct setup_header *hdr) printf("\n"); } -void zimage_dump(struct bootm_info *bmi, bool show_cmdline) +void zimage_dump(struct boot_params *base_ptr, bool show_cmdline) { - struct boot_params *base_ptr; struct setup_header *hdr; - int i; + const char *version; - base_ptr = bmi->base_ptr; printf("Setup located at %p:\n\n", base_ptr); print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr); printf("E820: %d entries\n", base_ptr->e820_entries); - if (base_ptr->e820_entries) { - printf("%12s %10s %s\n", "Addr", "Size", "Type"); - for (i = 0; i < base_ptr->e820_entries; i++) { - struct e820_entry *entry = &base_ptr->e820_map[i]; - - printf("%12llx %10llx %s\n", entry->addr, entry->size, - entry->type < E820_COUNT ? - e820_type_name[entry->type] : - simple_itoa(entry->type)); - } - } + if (base_ptr->e820_entries) + e820_dump(base_ptr->e820_map, base_ptr->e820_entries); hdr = &base_ptr->hdr; print_num("Setup sectors", hdr->setup_sects); @@ -606,14 +579,10 @@ void zimage_dump(struct bootm_info *bmi, bool show_cmdline) print_num("Real mode switch", hdr->realmode_swtch); print_num("Start sys seg", hdr->start_sys_seg); print_num("Kernel version", hdr->kernel_version); - if (bmi->bzimage_addr) { - const char *version; - - version = zimage_get_kernel_version(base_ptr, - (void *)bmi->bzimage_addr); - if (version) - printf(" @%p: %s\n", version, version); - } + version = zimage_get_kernel_version(base_ptr, + (void *)state.bzimage_addr); + if (version) + printf(" @%p: %s\n", version, version); print_num("Type of loader", hdr->type_of_loader); show_loader(hdr); print_num("Load flags", hdr->loadflags); @@ -654,24 +623,25 @@ void zimage_dump(struct bootm_info *bmi, bool show_cmdline) print_num("Kernel info offset", hdr->kernel_info_offset); } -void zboot_start(struct bootm_info *bmi, ulong bzimage_addr, ulong bzimage_size, - ulong initrd_addr, ulong initrd_size, ulong base_addr, - const char *cmdline) +void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr, + ulong initrd_size, ulong base_addr, const char *cmdline) { - bmi->bzimage_size = bzimage_size; - bmi->initrd_addr = initrd_addr; - bmi->initrd_size = initrd_size; + memset(&state, '\0', sizeof(state)); + + state.bzimage_size = bzimage_size; + state.initrd_addr = initrd_addr; + state.initrd_size = initrd_size; if (base_addr) { - bmi->base_ptr = map_sysmem(base_addr, 0); - bmi->load_address = bzimage_addr; + state.base_ptr = map_sysmem(base_addr, 0); + state.load_address = bzimage_addr; } else { - bmi->bzimage_addr = bzimage_addr; + state.bzimage_addr = bzimage_addr; } - bmi->cmdline = cmdline; + state.cmdline = cmdline; } -void zboot_info(struct bootm_info *bmi) +void zboot_info(void) { printf("Kernel loaded at %08lx, setup_base=%p\n", - bmi->load_address, bmi->base_ptr); + state.load_address, state.base_ptr); } |