diff options
Diffstat (limited to 'arch')
98 files changed, 752 insertions, 610 deletions
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index bde1c3d8af3..0eb44bcf33d 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -12,6 +12,6 @@ obj-y += reset.o obj-y += ints_low.o obj-y += init_helpers.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23ee25269a2..c9f26573f61 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1068,6 +1068,7 @@ config ARCH_RENESAS imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE + imply OF_UPSTREAM imply SYS_THUMB_BUILD imply ARCH_MISC_INIT if DISPLAY_CPUINFO @@ -1344,7 +1345,7 @@ config ARCH_ZYNQMP config ARCH_TEGRA bool "NVIDIA Tegra" select GPIO_EXTRA_HEADER - imply DISTRO_DEFAULTS + imply BOOTSTD_DEFAULTS imply FAT_WRITE imply SPL_TIMER if SPL diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 08dfbdd557b..b1c9c6222e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1056,41 +1056,41 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RCAR_GEN2) += \ - r8a7790-lager-u-boot.dtb \ - r8a7790-stout-u-boot.dtb \ - r8a7791-koelsch-u-boot.dtb \ - r8a7791-porter-u-boot.dtb \ - r8a7792-blanche-u-boot.dtb \ - r8a7793-gose-u-boot.dtb \ - r8a7794-alt-u-boot.dtb \ - r8a7794-silk-u-boot.dtb + r8a7790-lager.dtb \ + r8a7790-stout.dtb \ + r8a7791-koelsch.dtb \ + r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + r8a7794-silk.dtb dtb-$(CONFIG_RCAR_GEN3) += \ r8a774a1-beacon-rzg2m-kit.dtb \ r8a774b1-beacon-rzg2n-kit.dtb \ r8a774e1-beacon-rzg2h-kit.dtb \ - r8a774a1-hihope-rzg2m-u-boot.dtb \ - r8a774b1-hihope-rzg2n-u-boot.dtb \ - r8a774c0-ek874-u-boot.dtb \ - r8a774e1-hihope-rzg2h-u-boot.dtb \ - r8a77950-ulcb-u-boot.dtb \ - r8a77950-salvator-x-u-boot.dtb \ - r8a77960-ulcb-u-boot.dtb \ - r8a77960-salvator-x-u-boot.dtb \ - r8a77965-ulcb-u-boot.dtb \ - r8a77965-salvator-x-u-boot.dtb \ - r8a77970-eagle-u-boot.dtb \ - r8a77970-v3msk-u-boot.dtb \ - r8a77980-condor-u-boot.dtb \ - r8a77980-v3hsk-u-boot.dtb \ - r8a77990-ebisu-u-boot.dtb \ - r8a77995-draak-u-boot.dtb + r8a774a1-hihope-rzg2m.dtb \ + r8a774b1-hihope-rzg2n.dtb \ + r8a774c0-ek874.dtb \ + r8a774e1-hihope-rzg2h.dtb \ + r8a77951-ulcb.dtb \ + r8a77951-salvator-x.dtb \ + r8a77960-ulcb.dtb \ + r8a77960-salvator-x.dtb \ + r8a77965-ulcb.dtb \ + r8a77965-salvator-x.dtb \ + r8a77970-eagle.dtb \ + r8a77970-v3msk.dtb \ + r8a77980-condor.dtb \ + r8a77980-v3hsk.dtb \ + r8a77990-ebisu.dtb \ + r8a77995-draak.dtb dtb-$(CONFIG_RCAR_GEN4) += \ - r8a779a0-falcon-u-boot.dtb \ - r8a779f0-spider-u-boot.dtb \ - r8a779g0-white-hawk-u-boot.dtb \ - r8a779h0-gray-hawk-u-boot.dtb + r8a779a0-falcon.dtb \ + r8a779f0-spider.dtb \ + r8a779g0-white-hawk.dtb \ + r8a779h0-gray-hawk.dtb dtb-$(CONFIG_TARGET_RZG2L) += \ r9a07g044l2-smarc.dts @@ -1100,7 +1100,7 @@ DTC_FLAGS += -R 4 -p 0x1000 endif dtb-$(CONFIG_RZA1) += \ - r7s72100-gr-peach-u-boot.dtb + r7s72100-gr-peach.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 38db56059d6..8b397f535c1 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -60,6 +60,11 @@ ctrl-sleep-moci-hog { bootph-pre-ram; + gpio-hog; + output-high; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + }; }; diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 03f211d5f7d..7b45a87450b 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -58,6 +58,10 @@ ctrl-sleep-moci-hog { bootph-pre-ram; + gpio-hog; + output-high; + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; }; }; diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi index 0ae9f91fbe8..34fba29e859 100644 --- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dts +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> */ -#include "r7s72100-gr-peach.dts" / { aliases { diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi index b735e972214..3ad619bdb90 100644 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts +++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ -#include "r8a774a1-hihope-rzg2m-ex.dts" #include "r8a774a1-u-boot.dtsi" &gpio3 { diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi index 0bdc6909bfb..6f2f6c71c2f 100644 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts +++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a774b1-hihope-rzg2n-ex.dts" #include "r8a774b1-u-boot.dtsi" &gpio3 { diff --git a/arch/arm/dts/r8a774c0-ek874-u-boot.dts b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi index 8fa6d8074b3..dcdddd9aed6 100644 --- a/arch/arm/dts/r8a774c0-ek874-u-boot.dts +++ b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronisc Corporation */ -#include "r8a774c0-ek874.dts" #include "r8a774c0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi index 03a17bac7ec..8e57e03c899 100644 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts +++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a774e1-hihope-rzg2h-ex.dts" #include "r8a774e1-u-boot.dtsi" &gpio3 { diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dts b/arch/arm/dts/r8a7790-lager-u-boot.dtsi index 28b8b604c37..ed1891706ce 100644 --- a/arch/arm/dts/r8a7790-lager-u-boot.dts +++ b/arch/arm/dts/r8a7790-lager-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7790-lager.dts" #include "r8a7790-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dts b/arch/arm/dts/r8a7790-stout-u-boot.dtsi index 85bcb787613..3b393045e36 100644 --- a/arch/arm/dts/r8a7790-stout-u-boot.dts +++ b/arch/arm/dts/r8a7790-stout-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7790-stout.dts" #include "r8a7790-u-boot.dtsi" &scifa0 { diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi index c5a1332131d..541c4191d69 100644 --- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts +++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7791-koelsch.dts" #include "r8a7791-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dts b/arch/arm/dts/r8a7791-porter-u-boot.dtsi index bfec1fc6d62..cbf2c5265d8 100644 --- a/arch/arm/dts/r8a7791-porter-u-boot.dts +++ b/arch/arm/dts/r8a7791-porter-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7791-porter.dts" #include "r8a7791-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts b/arch/arm/dts/r8a7792-blanche-u-boot.dtsi index 1f33df81cef..8c36a3e5850 100644 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dts +++ b/arch/arm/dts/r8a7792-blanche-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7792-blanche.dts" #include "r8a7792-u-boot.dtsi" &iic3 { diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dts b/arch/arm/dts/r8a7793-gose-u-boot.dtsi index dd0932ceca9..41c4361c6e1 100644 --- a/arch/arm/dts/r8a7793-gose-u-boot.dts +++ b/arch/arm/dts/r8a7793-gose-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7793-gose.dts" #include "r8a7793-u-boot.dtsi" &scif0 { diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dts b/arch/arm/dts/r8a7794-alt-u-boot.dtsi index 0a39039fc97..e156b4c93c7 100644 --- a/arch/arm/dts/r8a7794-alt-u-boot.dts +++ b/arch/arm/dts/r8a7794-alt-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7794-alt.dts" #include "r8a7794-u-boot.dtsi" &i2c7 { diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dts b/arch/arm/dts/r8a7794-silk-u-boot.dtsi index 3fcb535a3ac..e448ea7e146 100644 --- a/arch/arm/dts/r8a7794-silk-u-boot.dts +++ b/arch/arm/dts/r8a7794-silk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a7794-silk.dts" #include "r8a7794-u-boot.dtsi" &scif2 { diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index ba7cf521d0d..744f4aaaad9 100644 --- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -5,8 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77950-salvator-x.dts" -#include "r8a77950-u-boot.dtsi" +#include "r8a77951-u-boot.dtsi" / { sysinfo { diff --git a/arch/arm/dts/r8a77950-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 92907ea09bf..4cbec591479 100644 --- a/arch/arm/dts/r8a77950-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -30,7 +30,6 @@ /delete-node/ &can1; /delete-node/ &canfd; /delete-node/ &csi20; -/delete-node/ &csi21; /delete-node/ &csi40; /delete-node/ &csi41; /delete-node/ &drif00; @@ -44,16 +43,13 @@ /delete-node/ &du; /delete-node/ &fcpf0; /delete-node/ &fcpf1; -/delete-node/ &fcpf2; /delete-node/ &fcpvb0; /delete-node/ &fcpvb1; /delete-node/ &fcpvd0; /delete-node/ &fcpvd1; /delete-node/ &fcpvd2; -/delete-node/ &fcpvd3; /delete-node/ &fcpvi0; /delete-node/ &fcpvi1; -/delete-node/ &fcpvi2; /delete-node/ &hdmi0; /delete-node/ &hdmi1; /delete-node/ &lvds0; @@ -72,10 +68,8 @@ /delete-node/ &vspd0; /delete-node/ &vspd1; /delete-node/ &vspd2; -/delete-node/ &vspd3; /delete-node/ &vspi0; /delete-node/ &vspi1; -/delete-node/ &vspi2; / { /delete-node/ cvbs-in; diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index e371cde349f..305c4861520 100644 --- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -5,8 +5,7 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77950-ulcb.dts" -#include "r8a77950-u-boot.dtsi" +#include "r8a77951-u-boot.dtsi" / { cpld { diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 2a9f0aa2180..84a28bf885c 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77960-salvator-x.dts" #include "r8a77960-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index 79042b20852..6372f953956 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77960-ulcb.dts" #include "r8a77960-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index e5421f9ca8f..d9a28fe9bab 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index 969911d89ce..aa5de3d0465 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77965-ulcb.dts" #include "r8a77965-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dts b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi index eb868eda414..c7971b9e9ce 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dts +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77970-eagle.dts" #include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi index 6ee06d7c000..c7b2e07793d 100644 --- a/arch/arm/dts/r8a77970-v3msk-u-boot.dts +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77970-v3msk.dts" #include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dts b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index f4a3b43b8ff..34a735ae5b2 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dts +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77980-condor.dts" #include "r8a77980-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi index d083df65f9a..2901d0e7b57 100644 --- a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts +++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77980-v3hsk.dts" #include "r8a77980-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index fc1c4a79294..b6b7b8f3609 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77990-ebisu.dts" #include "r8a77990-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 41ceae1da77..1922c40a438 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dts +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include "r8a77995-draak.dts" #include "r8a77995-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dts b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi index 9d28791c605..3b8a017cb41 100644 --- a/arch/arm/dts/r8a779a0-falcon-u-boot.dts +++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779a0-falcon.dts" #include "r8a779a0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779f0-spider-u-boot.dts b/arch/arm/dts/r8a779f0-spider-u-boot.dtsi index 26fc8bcf440..2fc7e7789a2 100644 --- a/arch/arm/dts/r8a779f0-spider-u-boot.dts +++ b/arch/arm/dts/r8a779f0-spider-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779f0-spider.dts" #include "r8a779f0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index bd756036645..a102639010d 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779g0-white-hawk.dts" #include "r8a779g0-u-boot.dtsi" / { diff --git a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi index 935ba9465dc..92c13151613 100644 --- a/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dts +++ b/arch/arm/dts/r8a779h0-gray-hawk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ -#include "r8a779h0-gray-hawk.dts" #include "r8a779h0-u-boot.dtsi" / { diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index e0c6aee58ab..7c5067cf002 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -130,6 +130,10 @@ bootph-all; }; +&vop { + bootph-all; +}; + #ifdef CONFIG_ROCKCHIP_SPI_IMAGE &binman { simple-bin-spi { diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi index ba0c02489d1..f004e9840a2 100644 --- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -16,11 +16,26 @@ u-boot,mmc-env-partition = "u-boot-env"; }; + gpio-keys { + button-user-1 { + label = "User-1"; + linux,code = <BTN_2>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user { + /* update label to match the label requested in board_key_check() */ + label = "User-2"; + }; + }; + leds { + led-blue { + /delete-property/default-state; + }; + led-red { - color = <LED_COLOR_ID_RED>; gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 20728f27ee1..a5158fec7ef 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright : STMicroelectronics 2022 */ +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-scmi-u-boot.dtsi" / { @@ -12,20 +13,35 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; }; led { - red { - label = "error"; + led-blue { + /delete-property/label; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index a16358266a2..f97debaa0e4 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" @@ -14,12 +15,10 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "fip"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL) @@ -48,12 +47,29 @@ }; #endif + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + led { - red { - label = "error"; + led-blue { + /delete-property/label; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 4d763bd3a2c..7c0d1bab11a 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright : STMicroelectronics 2022 */ +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-scmi-u-boot.dtsi" / { @@ -11,19 +12,36 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; }; led { - red { - label = "error"; + compatible = "gpio-leds"; + + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index ef91088aa37..d93359f967c 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/stm32mp1-clksrc.h> +#include <dt-bindings/input/linux-event-codes.h> #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" @@ -13,11 +14,9 @@ }; config { - u-boot,boot-led = "heartbeat"; - u-boot,error-led = "error"; + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "fip"; - st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL) @@ -43,12 +42,31 @@ }; #endif + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + led { - red { - label = "error"; + compatible = "gpio-leds"; + + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + }; + + led-red { gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - status = "okay"; }; }; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 139940bd5d4..3515347e91d 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -33,11 +33,11 @@ label = "fsbl1"; reg = <0x00000000 0x00040000>; }; - partition@80000 { + partition@40000 { label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "ssbl"; reg = <0x00080000 0x00200000>; }; @@ -58,7 +58,7 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "fip"; reg = <0x00080000 0x00400000>; }; @@ -112,7 +112,7 @@ label = "fip2"; reg = <0x00600000 0x00400000>; }; - partition@1200000 { + partition@a00000 { label = "UBI"; reg = <0x00a00000 0x3f600000>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 2f70b0690d2..1b445619325 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -106,15 +106,15 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@500000 { + partition@80000 { label = "uboot"; reg = <0x00080000 0x00160000>; }; - partition@900000 { + partition@1e0000 { label = "env1"; reg = <0x001E0000 0x00010000>; }; - partition@980000 { + partition@1f0000 { label = "env2"; reg = <0x001F0000 0x00010000>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 552b35db3c7..ba84db679e1 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -42,15 +42,15 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@500000 { + partition@80000 { label = "uboot"; reg = <0x00080000 0x00160000>; }; - partition@900000 { + partition@1e0000 { label = "env1"; reg = <0x001E0000 0x00010000>; }; - partition@980000 { + partition@1f0000 { label = "env2"; reg = <0x001F0000 0x00010000>; }; diff --git a/arch/arm/dts/tegra114-u-boot.dtsi b/arch/arm/dts/tegra114-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra114-u-boot.dtsi +++ b/arch/arm/dts/tegra114-u-boot.dtsi @@ -1,3 +1,16 @@ #include <config.h> #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 68ee7f31656..250d692f6bf 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -42,7 +42,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP1>, @@ -61,7 +61,7 @@ }; dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP2>, diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5cf604e8659..f851767a55f 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -35,22 +35,6 @@ status = "okay"; nvidia,panel = <&panel>; - - display-timings { - timing@0 { - /* PAZ00 has 1024x600 */ - clock-frequency = <54030000>; - hactive = <1024>; - vactive = <600>; - hback-porch = <160>; - hfront-porch = <24>; - hsync-len = <136>; - vback-porch = <3>; - vfront-porch = <61>; - vsync-len = <6>; - hsync-active = <1>; - }; - }; }; }; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index e8a3511a9f7..d437ddc4dce 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -829,6 +829,12 @@ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; }; + + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; }; panel: panel { diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 350443d55eb..243ff2bda26 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -118,8 +118,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -203,7 +203,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; gen2_i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -213,7 +213,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; cam_i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -223,7 +223,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; ddc_i2c { nvidia,pins = "ddc_scl_pv4", @@ -232,7 +232,7 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; pwr_i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -242,7 +242,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hotplug_i2c { nvidia,pins = "pu4"; @@ -260,7 +260,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hdmi_hpd { nvidia,pins = "hdmi_int_pn7"; @@ -632,8 +632,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -718,8 +718,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_d10_pt2 { nvidia,pins = "vi_d10_pt2", @@ -838,8 +838,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index f49e7341fe0..3ddd78b3df6 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -90,6 +90,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC2 pinmux */ @@ -98,21 +100,15 @@ "vi_d2_pl0", "vi_d3_pl1", "vi_d5_pl3", - "vi_d7_pl5"; - nvidia,function = "sdmmc2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - vi_d8_pl6 { - nvidia,pins = "vi_d8_pl6", + "vi_d7_pl5", + "vi_d8_pl6", "vi_d9_pl7"; nvidia,function = "sdmmc2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -146,6 +142,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; sdmmc4_cmd { nvidia,pins = "sdmmc4_cmd_pt7", @@ -161,6 +159,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; sdmmc4_rst_n { nvidia,pins = "sdmmc4_rst_n_pcc3"; @@ -469,6 +469,42 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; + /* SPI pinmux */ + spi1_ctrl { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_sck { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs1_n { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi4_ctrl { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + /* Display A pinmux */ lcd_pwr0_pb2 { nvidia,pins = "lcd_pwr0_pb2", @@ -577,8 +613,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -657,18 +693,19 @@ nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; vi_vsync_pd6 { - nvidia,pins = "vi_vsync_pd6", + nvidia,pins = "vi_d0_pt4", + "vi_d10_pt2", + "vi_vsync_pd6", "vi_hsync_pd7"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; - vi_d10_pt2 { - nvidia,pins = "vi_d10_pt2", - "vi_d0_pt4", "pbb0"; + pbb0 { + nvidia,pins = "pbb0"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -783,21 +820,15 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; - vi_d4_pl2 { - nvidia,pins = "vi_d4_pl2"; - nvidia,function = "vi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - vi_d6_pl4 { - nvidia,pins = "vi_d6_pl4"; + vi_d4 { + nvidia,pins = "vi_d4_pl2", + "vi_d6_pl4"; nvidia,function = "vi"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; @@ -805,6 +836,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; jtag { @@ -1089,6 +1122,16 @@ clock-output-names = "pmic-oscillator"; }; + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts index cc03f5a7ec2..6dc760b90d6 100644 --- a/arch/arm/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -7,7 +7,18 @@ model = "ASUS Transformer Infinity TF700T"; compatible = "asus,tf700t", "nvidia,tegra30"; - /delete-node/ host1x@50000000; + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&tc358768>; + }; + }; + }; pinmux@70000868 { state_default: pinmux { @@ -62,5 +73,92 @@ }; }; - /delete-node/ panel; + tc358768_refclk: clock-tc358768 { + compatible = "fixed-clock"; + clock-frequency = <23100000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + tc358768_osc: clock-tc358768-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + clocks = <&tc358768_refclk>; + #clock-cells = <0>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + + mux-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + i2c-parent = <&gen1_i2c>; + idle-state = <0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tc358768: dsi@7 { + compatible = "toshiba,tc358768"; + reg = <0x7>; + + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&tc358768_osc>; + clock-names = "refclk"; + + reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + vddc-supply = <&vdd_1v2_mipi>; + vddio-supply = <&vdd_1v8_vio>; + vddmipi-supply = <&vdd_1v2_mipi>; + + panel = <&panel>; + }; + }; + }; + + panel: panel { + compatible = "panasonic,vvx10f004b00"; + + power-supply = <&vdd_pnl_reg>; + backlight = <&backlight>; + + /delete-property/ enable-gpios; + + display-timings { + timing@0 { + /* 1920x1200@60Hz */ + clock-frequency = <154000000>; + + hactive = <1920>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + hsync-active = <1>; + + vactive = <1200>; + vfront-porch = <3>; + vback-porch = <26>; + vsync-len = <6>; + vsync-active = <1>; + }; + }; + }; + + vdd_1v2_mipi: regulator-mipi { + compatible = "regulator-fixed"; + regulator-name = "tc358768_1v2_vdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <10000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index e6cc6e7105f..03ba8fb9604 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -99,8 +99,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* SDMMC3 pinmux */ @@ -189,7 +189,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; gen2_i2c { @@ -200,7 +200,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; cam_i2c { @@ -211,7 +211,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; ddc_i2c { @@ -221,7 +221,7 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; pwr_i2c { @@ -232,7 +232,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,open-drain = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; + nvidia,lock = <1>; }; hotplug_i2c { @@ -647,8 +647,8 @@ nvidia,pull = <TEGRA_PIN_PULL_UP>; nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; /* GPIO keys pinmux */ @@ -741,8 +741,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_d10_pt2 { @@ -879,8 +879,8 @@ nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,lock = <0>; - nvidia,io-reset = <0>; + nvidia,lock = <1>; + nvidia,io-reset = <1>; }; vi_mclk_pt1 { @@ -1150,6 +1150,16 @@ clock-output-names = "pmic-oscillator"; }; + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi index 3038227dbed..6a02714a258 100644 --- a/arch/arm/dts/tegra30-u-boot.dtsi +++ b/arch/arm/dts/tegra30-u-boot.dtsi @@ -8,5 +8,9 @@ dc@54200000 { bootph-all; }; + + dc@54240000 { + bootph-all; + }; }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index f198bc0edbe..1177e2ab1f4 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -158,7 +158,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 226744d67d9..4ad1d33e056 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); enum apll_frequencies { APLL_816_MHZ, APLL_600_MHZ, + + /* CRU_CLK_SEL37_CON */ + ACLK_VIO_PLL_SEL_CPLL = 0, + ACLK_VIO_PLL_SEL_GPLL = 1, + ACLK_VIO_PLL_SEL_HDMIPHY = 2, + ACLK_VIO_PLL_SEL_USB480M = 3, + ACLK_VIO_PLL_SEL_SHIFT = 6, + ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, + ACLK_VIO_DIV_CON_SHIFT = 0, + ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, + HCLK_VIO_DIV_CON_SHIFT = 8, + HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, + + /* CRU_CLK_SEL39_CON */ + ACLK_VOP_PLL_SEL_CPLL = 0, + ACLK_VOP_PLL_SEL_GPLL = 1, + ACLK_VOP_PLL_SEL_HDMIPHY = 2, + ACLK_VOP_PLL_SEL_USB480M = 3, + ACLK_VOP_PLL_SEL_SHIFT = 6, + ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, + ACLK_VOP_DIV_CON_SHIFT = 0, + ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, + + /* CRU_CLK_SEL40_CON */ + DCLK_LCDC_PLL_SEL_GPLL = 0, + DCLK_LCDC_PLL_SEL_CPLL = 1, + DCLK_LCDC_PLL_SEL_SHIFT = 0, + DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, + DCLK_LCDC_SEL_HDMIPHY = 0, + DCLK_LCDC_SEL_PLL = 1, + DCLK_LCDC_SEL_SHIFT = 1, + DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, + DCLK_LCDC_DIV_CON_SHIFT = 8, + DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, }; void rk3328_configure_cpu(struct rk3328_cru *cru, diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index fe6b8ba2732..0264bfe1c50 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -220,10 +220,7 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); -void clock_set_pll2(unsigned int clk); -void clock_set_pll4(unsigned int clk); void clock_set_pll6(unsigned int clk); -void clock_set_pll12(unsigned int clk); unsigned int clock_get_pll4_periph0(void); #endif diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h index 7a6fcaebdb5..92696088a39 100644 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h @@ -28,6 +28,12 @@ struct sunxi_tzpc { #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 void tzpc_init(void); +#else +static inline void tzpc_init(void) +{ +} +#endif #endif /* _SUNXI_TZPC_H */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 7613d84f221..ca3718411ab 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -443,6 +443,11 @@ enum win_color_depth_id { #define WINDOW_D_SELECT BIT(7) #define WINDOW_H_SELECT BIT(8) +/* DC_COM_PIN_OUTPUT_POLARITY1 0x307 */ +#define LHS_OUTPUT_POLARITY_LOW BIT(30) +#define LVS_OUTPUT_POLARITY_LOW BIT(28) +#define LSC0_OUTPUT_POLARITY_LOW BIT(24) + /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ #define CURSOR_ENABLE BIT(16) #define SOR_ENABLE BIT(25) @@ -569,12 +574,4 @@ enum { #define DC_N_WINDOWS 5 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) -#define TEGRA_DSI_A "dsi@54300000" -#define TEGRA_DSI_B "dsi@54400000" - -struct tegra_dc_plat { - struct udevice *dev; /* Display controller device */ - struct dc_ctlr *dc; /* Display controller regmap */ -}; - #endif /* __ASM_ARCH_TEGRA_DC_H */ diff --git a/arch/arm/include/asm/arch-tegra114/pwm.h b/arch/arm/include/asm/arch-tegra114/pwm.h new file mode 100644 index 00000000000..af391518035 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Tegra pulse width frequency modulator definitions + * + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __ASM_ARCH_TEGRA114_PWM_H +#define __ASM_ARCH_TEGRA114_PWM_H + +#include <asm/arch-tegra/pwm.h> + +#endif /* __ASM_ARCH_TEGRA114_PWM_H */ diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h deleted file mode 100644 index e7b3cffd466..00000000000 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned x; /* Horizontal address offset (bytes) */ - unsigned y; /* Veritical address offset (bytes) */ - unsigned w; /* Width of source window */ - unsigned h; /* Height of source window */ - unsigned stride; /* Number of bytes per line */ - unsigned out_x; /* Left edge of output window (col) */ - unsigned out_y; /* Top edge of output window (row) */ - unsigned out_w; /* Width of output window in pixels */ - unsigned out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra30/display.h b/arch/arm/include/asm/arch-tegra30/display.h deleted file mode 100644 index 9411525799d..00000000000 --- a/arch/arm/include/asm/arch-tegra30/display.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -#include <asm/arch-tegra/dc.h> - -/* This holds information about a window which can be displayed */ -struct disp_ctl_win { - enum win_color_depth_id fmt; /* Color depth/format */ - unsigned int bpp; /* Bits per pixel */ - phys_addr_t phys_addr; /* Physical address in memory */ - unsigned int x; /* Horizontal address offset (bytes) */ - unsigned int y; /* Veritical address offset (bytes) */ - unsigned int w; /* Width of source window */ - unsigned int h; /* Height of source window */ - unsigned int stride; /* Number of bytes per line */ - unsigned int out_x; /* Left edge of output window (col) */ - unsigned int out_y; /* Top edge of output window (row) */ - unsigned int out_w; /* Width of output window in pixels */ - unsigned int out_h; /* Height of output window in pixels */ -}; - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra30/dsi.h b/arch/arm/include/asm/arch-tegra30/dsi.h deleted file mode 100644 index 7ade132613f..00000000000 --- a/arch/arm/include/asm/arch-tegra30/dsi.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - */ - -#ifndef __ASM_ARCH_TEGRA_DSI_H -#define __ASM_ARCH_TEGRA_DSI_H - -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -#endif - -/* Register definitions for the Tegra display serial interface */ - -/* DSI syncpoint register 0x000 ~ 0x002 */ -struct dsi_syncpt_reg { - /* Address 0x000 ~ 0x002 */ - uint incr_syncpt; /* _INCR_SYNCPT_0 */ - uint incr_syncpt_ctrl; /* _INCR_SYNCPT_CNTRL_0 */ - uint incr_syncpt_err; /* _INCR_SYNCPT_ERROR_0 */ -}; - -/* DSI misc register 0x008 ~ 0x015 */ -struct dsi_misc_reg { - /* Address 0x008 ~ 0x015 */ - uint ctxsw; /* _CTXSW_0 */ - uint dsi_rd_data; /* _DSI_RD_DATA_0 */ - uint dsi_wr_data; /* _DSI_WR_DATA_0 */ - uint dsi_pwr_ctrl; /* _DSI_POWER_CONTROL_0 */ - uint int_enable; /* _INT_ENABLE_0 */ - uint int_status; /* _INT_STATUS_0 */ - uint int_mask; /* _INT_MASK_0 */ - uint host_dsi_ctrl; /* _HOST_DSI_CONTROL_0 */ - uint dsi_ctrl; /* _DSI_CONTROL_0 */ - uint dsi_sol_delay; /* _DSI_SOL_DELAY_0 */ - uint dsi_max_threshold; /* _DSI_MAX_THRESHOLD_0 */ - uint dsi_trigger; /* _DSI_TRIGGER_0 */ - uint dsi_tx_crc; /* _DSI_TX_CRC_0 */ - uint dsi_status; /* _DSI_STATUS_0 */ -}; - -/* DSI init sequence register 0x01a ~ 0x022 */ -struct dsi_init_seq_reg { - /* Address 0x01a ~ 0x022 */ - uint dsi_init_seq_ctrl; /* _DSI_INIT_SEQ_CONTROL_0 */ - uint dsi_init_seq_data_0; /* _DSI_INIT_SEQ_DATA_0_0 */ - uint dsi_init_seq_data_1; /* _DSI_INIT_SEQ_DATA_1_0 */ - uint dsi_init_seq_data_2; /* _DSI_INIT_SEQ_DATA_2_0 */ - uint dsi_init_seq_data_3; /* _DSI_INIT_SEQ_DATA_3_0 */ - uint dsi_init_seq_data_4; /* _DSI_INIT_SEQ_DATA_4_0 */ - uint dsi_init_seq_data_5; /* _DSI_INIT_SEQ_DATA_5_0 */ - uint dsi_init_seq_data_6; /* _DSI_INIT_SEQ_DATA_6_0 */ - uint dsi_init_seq_data_7; /* _DSI_INIT_SEQ_DATA_7_0 */ -}; - -/* DSI packet sequence register 0x023 ~ 0x02e */ -struct dsi_pkt_seq_reg { - /* Address 0x023 ~ 0x02e */ - uint dsi_pkt_seq_0_lo; /* _DSI_PKT_SEQ_0_LO_0 */ - uint dsi_pkt_seq_0_hi; /* _DSI_PKT_SEQ_0_HI_0 */ - uint dsi_pkt_seq_1_lo; /* _DSI_PKT_SEQ_1_LO_0 */ - uint dsi_pkt_seq_1_hi; /* _DSI_PKT_SEQ_1_HI_0 */ - uint dsi_pkt_seq_2_lo; /* _DSI_PKT_SEQ_2_LO_0 */ - uint dsi_pkt_seq_2_hi; /* _DSI_PKT_SEQ_2_HI_0 */ - uint dsi_pkt_seq_3_lo; /* _DSI_PKT_SEQ_3_LO_0 */ - uint dsi_pkt_seq_3_hi; /* _DSI_PKT_SEQ_3_HI_0 */ - uint dsi_pkt_seq_4_lo; /* _DSI_PKT_SEQ_4_LO_0 */ - uint dsi_pkt_seq_4_hi; /* _DSI_PKT_SEQ_4_HI_0 */ - uint dsi_pkt_seq_5_lo; /* _DSI_PKT_SEQ_5_LO_0 */ - uint dsi_pkt_seq_5_hi; /* _DSI_PKT_SEQ_5_HI_0 */ -}; - -/* DSI packet length register 0x033 ~ 0x037 */ -struct dsi_pkt_len_reg { - /* Address 0x033 ~ 0x037 */ - uint dsi_dcs_cmds; /* _DSI_DCS_CMDS_0 */ - uint dsi_pkt_len_0_1; /* _DSI_PKT_LEN_0_1_0 */ - uint dsi_pkt_len_2_3; /* _DSI_PKT_LEN_2_3_0 */ - uint dsi_pkt_len_4_5; /* _DSI_PKT_LEN_4_5_0 */ - uint dsi_pkt_len_6_7; /* _DSI_PKT_LEN_6_7_0 */ -}; - -/* DSI PHY timing register 0x03c ~ 0x03f */ -struct dsi_timing_reg { - /* Address 0x03c ~ 0x03f */ - uint dsi_phy_timing_0; /* _DSI_PHY_TIMING_0_0 */ - uint dsi_phy_timing_1; /* _DSI_PHY_TIMING_1_0 */ - uint dsi_phy_timing_2; /* _DSI_PHY_TIMING_2_0 */ - uint dsi_bta_timing; /* _DSI_BTA_TIMING_0 */ -}; - -/* DSI timeout register 0x044 ~ 0x046 */ -struct dsi_timeout_reg { - /* Address 0x044 ~ 0x046 */ - uint dsi_timeout_0; /* _DSI_TIMEOUT_0_0 */ - uint dsi_timeout_1; /* _DSI_TIMEOUT_1_0 */ - uint dsi_to_tally; /* _DSI_TO_TALLY_0 */ -}; - -/* DSI PAD control register 0x04b ~ 0x04e */ -struct dsi_pad_ctrl_reg { - /* Address 0x04b ~ 0x04e */ - uint pad_ctrl; /* _PAD_CONTROL_0 */ - uint pad_ctrl_cd; /* _PAD_CONTROL_CD_0 */ - uint pad_cd_status; /* _PAD_CD_STATUS_0 */ - uint dsi_vid_mode_control; /* _DSI_VID_MODE_CONTROL_0 */ -}; - -/* Display Serial Interface (DSI_) regs */ -struct dsi_ctlr { - struct dsi_syncpt_reg syncpt; /* SYNCPT register 0x000 ~ 0x002 */ - uint reserved0[5]; /* reserved_0[5] */ - - struct dsi_misc_reg misc; /* MISC register 0x008 ~ 0x015 */ - uint reserved1[4]; /* reserved_1[4] */ - - struct dsi_init_seq_reg init; /* INIT register 0x01a ~ 0x022 */ - struct dsi_pkt_seq_reg pkt; /* PKT register 0x023 ~ 0x02e */ - uint reserved2[4]; /* reserved_2[4] */ - - struct dsi_pkt_len_reg len; /* LEN registers 0x033 ~ 0x037 */ - uint reserved3[4]; /* reserved_3[4] */ - - struct dsi_timing_reg ptiming; /* TIMING registers 0x03c ~ 0x03f */ - uint reserved4[4]; /* reserved_4[4] */ - - struct dsi_timeout_reg timeout; /* TIMEOUT registers 0x044 ~ 0x046 */ - uint reserved5[4]; /* reserved_5[4] */ - - struct dsi_pad_ctrl_reg pad; /* PAD registers 0x04b ~ 0x04e */ -}; - -#define DSI_POWER_CONTROL_ENABLE BIT(0) - -#define DSI_HOST_CONTROL_FIFO_RESET BIT(21) -#define DSI_HOST_CONTROL_CRC_RESET BIT(20) -#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) -#define DSI_HOST_CONTROL_RAW BIT(6) -#define DSI_HOST_CONTROL_HS BIT(5) -#define DSI_HOST_CONTROL_FIFO_SEL BIT(4) -#define DSI_HOST_CONTROL_IMM_BTA BIT(3) -#define DSI_HOST_CONTROL_PKT_BTA BIT(2) -#define DSI_HOST_CONTROL_CS BIT(1) -#define DSI_HOST_CONTROL_ECC BIT(0) - -#define DSI_CONTROL_HS_CLK_CTRL BIT(20) -#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) -#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) -#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) -#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) -#define DSI_CONTROL_DCS_ENABLE BIT(3) -#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) -#define DSI_CONTROL_VIDEO_ENABLE BIT(1) -#define DSI_CONTROL_HOST_ENABLE BIT(0) - -#define DSI_TRIGGER_HOST BIT(1) -#define DSI_TRIGGER_VIDEO BIT(0) - -#define DSI_STATUS_IDLE BIT(10) -#define DSI_STATUS_UNDERFLOW BIT(9) -#define DSI_STATUS_OVERFLOW BIT(8) - -#define DSI_TIMING_FIELD(value, period, hwinc) \ - ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff) - -#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) -#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) - -#define DSI_TALLY_TA(x) (((x) & 0xff) << 16) -#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) -#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) - -#define DSI_PAD_CONTROL_PAD_PULLDN_ENAB(x) (((x) & 0x1) << 28) -#define DSI_PAD_CONTROL_PAD_SLEWUPADJ(x) (((x) & 0x7) << 24) -#define DSI_PAD_CONTROL_PAD_SLEWDNADJ(x) (((x) & 0x7) << 20) -#define DSI_PAD_CONTROL_PAD_PREEMP_EN(x) (((x) & 0x1) << 19) -#define DSI_PAD_CONTROL_PAD_PDIO_CLK(x) (((x) & 0x1) << 18) -#define DSI_PAD_CONTROL_PAD_PDIO(x) (((x) & 0x3) << 16) -#define DSI_PAD_CONTROL_PAD_LPUPADJ(x) (((x) & 0x3) << 14) -#define DSI_PAD_CONTROL_PAD_LPDNADJ(x) (((x) & 0x3) << 12) - -/* - * pixel format as used in the DSI_CONTROL_FORMAT field - */ -enum tegra_dsi_format { - TEGRA_DSI_FORMAT_16P, - TEGRA_DSI_FORMAT_18NP, - TEGRA_DSI_FORMAT_18P, - TEGRA_DSI_FORMAT_24P, -}; - -/* DSI calibration in VI region */ -#define TEGRA_VI_BASE 0x54080000 - -#define CSI_CILA_MIPI_CAL_CONFIG_0 0x22a -#define MIPI_CAL_TERMOSA(x) (((x) & 0x1f) << 0) - -#define CSI_CILB_MIPI_CAL_CONFIG_0 0x22b -#define MIPI_CAL_TERMOSB(x) (((x) & 0x1f) << 0) - -#define CSI_CIL_PAD_CONFIG 0x229 -#define PAD_CIL_PDVREG(x) (((x) & 0x01) << 1) - -#define CSI_DSI_MIPI_CAL_CONFIG 0x234 -#define MIPI_CAL_HSPDOSD(x) (((x) & 0x1f) << 16) -#define MIPI_CAL_HSPUOSD(x) (((x) & 0x1f) << 8) - -#define CSI_MIPIBIAS_PAD_CONFIG 0x235 -#define PAD_DRIV_DN_REF(x) (((x) & 0x7) << 16) -#define PAD_DRIV_UP_REF(x) (((x) & 0x7) << 8) - -#endif /* __ASM_ARCH_TEGRA_DSI_H */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index b55167e9cc0..67275fba616 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -31,7 +31,7 @@ endif obj-$(CONFIG_CPU_V7M) += cmd_boot.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 22697a263a8..7c46914d9dd 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -50,7 +50,7 @@ void ti_secure_image_check_binary(void **p_image, size_t *p_size) if (get_device_type() == K3_DEVICE_TYPE_GP) { if (ti_secure_cert_detected(*p_image)) { - printf("Warning: Detected image signing certificate on GP device. " + debug("Warning: Detected image signing certificate on GP device. " "Skipping certificate to prevent boot failure. " "This will fail if the image was also encrypted\n"); @@ -60,6 +60,7 @@ void ti_secure_image_check_binary(void **p_image, size_t *p_size) return; } + printf("Skipping authentication on GP device\n"); *p_image += cert_length; *p_size -= cert_length; } diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index 2ac867612bf..aeb55da609b 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -14,6 +14,7 @@ config RCAR_64 imply CMD_GPT imply CMD_MMC_SWRITE if MMC imply CMD_UUID + imply OF_UPSTREAM imply SUPPORT_EMMC_RPMB if MMC choice diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f68a0a48949..4f22d9bde9f 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -180,6 +180,7 @@ config ROCKCHIP_RK3328 select SUPPORT_TPL select TPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 8f91db4b46b..589276282e4 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -17,6 +17,7 @@ config CMD_STM32PROG config CMD_STM32PROG_USB bool "support stm32prog over USB" depends on CMD_STM32PROG + depends on USB_GADGET_DOWNLOAD default y help activate the command "stm32prog usb" for STM32MP soc family diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index 857148747ef..ebae50f66c9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,7 +8,6 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..4f2379df45f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); bool iwdg1_wake = false; bool iwdg2_wake = false; bool other_wake = false; @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); } diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index afc56b02eea..d75ec99d6a1 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <linux/bitfield.h> /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* + * TAMP: Configure non-zero secure protection settings. This is + * checked by BootROM function 35ac on OTP-CLOSED device during + * CPU core 1 release from endless loop. If secure protection + * fields are zero, the core 1 is not released from endless + * loop on second SGI0. + */ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); @@ -322,8 +338,23 @@ void get_soc_name(char name[SOC_NAME_SIZE]) get_cpu_string_offsets(&type, &pkg, &rev); - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); + if (bsec_dbgswenable()) { + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); + } else { + /* + * SoC revision is only accessible via DBUMCU IDC register, + * which requires BSEC.DENABLE DBGSWENABLE bit to be set to + * make the register accessible, otherwise an access to the + * register triggers bus fault. As BSEC.DBGSWENABLE is zero + * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE + * bit as this might open a brief window for timing attacks. + * Instead, report that this system is OTP-CLOSED and do not + * report any SoC revision to avoid confusing users. + */ + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C", + soc_type[type], soc_pkg[pkg]); + } } static void setup_soc_type_pkg_rev(void) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index fe89aec6b9a..ddf9414b08e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1078,7 +1078,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 1d4c70ec352..3f83c0280ef 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -7,7 +7,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += board.o -obj-y += clock.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o @@ -31,6 +30,7 @@ obj-y += timer.o endif ifdef CONFIG_SPL_BUILD +obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index f4dbb2a740b..0140b07d32a 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -458,10 +458,8 @@ void board_init_f(ulong dummy) { sunxi_sram_init(); -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ tzpc_init(); -#endif clock_init(); timer_init(); diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index b6c68c94f67..5e9fa0d0748 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -23,10 +23,8 @@ __weak void gtbus_init(void) int clock_init(void) { -#ifdef CONFIG_SPL_BUILD clock_init_safe(); gtbus_init(); -#endif clock_init_uart(); clock_init_sec(); diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index ac3b7a801f4..6458d066f7e 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -43,7 +43,6 @@ void clock_init_safe(void) setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); #endif } -#endif void clock_init_uart(void) { @@ -77,7 +76,6 @@ int clock_twi_onoff(int port, int state) return 0; } -#ifdef CONFIG_SPL_BUILD #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ @@ -177,8 +175,9 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index dac3663e1be..cc2ee336416 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -51,7 +51,6 @@ void clock_init_safe(void) */ writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); } -#endif void clock_init_uart(void) { @@ -73,7 +72,6 @@ void clock_init_uart(void) 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -105,33 +103,6 @@ void clock_set_pll1(unsigned int clk) val |= CCM_CPU_AXI_MUX_PLL_CPUX; writel(val, &ccm->cpu_axi_cfg); } -#endif - -unsigned int clock_get_pll6(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; - int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> - CCM_PLL6_CTRL_DIV2_SHIFT) + 1; - int div1, m; - - if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { - div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> - CCM_PLL6_CTRL_P0_SHIFT) + 1; - m = 1; - } else { - div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> - CCM_PLL6_CTRL_DIV1_SHIFT) + 1; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) - m = 4; - else - m = 2; - } - - return 24000000U * n / m / div1 / div2; -} int clock_twi_onoff(int port, int state) { @@ -160,3 +131,31 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ + +/* PLL_PERIPH0 clock, used by the MMC driver */ +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + int div1, m; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >> + CCM_PLL6_CTRL_P0_SHIFT) + 1; + m = 1; + } else { + div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + m = 4; + else + m = 2; + } + + return 24000000U * n / m / div1 / div2; +} diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index aad9df282ec..59f7e15ffe8 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -62,7 +62,6 @@ void clock_init_safe(void) setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); #endif } -#endif /* CONFIG_SPL_BUILD */ void clock_init_sec(void) { @@ -124,7 +123,6 @@ void clock_init_uart(void) #endif } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -173,6 +171,7 @@ void clock_set_pll1(unsigned int clk) } #endif /* CONFIG_SPL_BUILD */ +/* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 198fe9dbd73..9eeba084f95 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -46,7 +46,6 @@ void clock_init_safe(void) /* timestamp */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -70,7 +69,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -102,8 +100,9 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif +#endif /* CONFIG_SPL_BUILD */ +/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) { struct sunxi_ccm_reg * const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index edaff9a28ce..5913e40cb65 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -17,6 +17,52 @@ #ifdef CONFIG_SPL_BUILD +static void clock_set_pll2(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch cluster 1 to 24MHz clock while changing PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_OSC24M); + + writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | + CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), + &ccm->pll2_c1_cfg); + + sdelay(2000); + + /* Switch cluster 1 back to PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, + C1_CPUX_CLK_SRC_PLL2); +} + +static void clock_set_pll4(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), + &ccm->pll4_periph0_cfg); + + sdelay(2000); +} + +static void clock_set_pll12(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) + return; + + writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), + &ccm->pll12_periph1_cfg); + + sdelay(2000); +} + void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -63,7 +109,6 @@ void clock_init_safe(void) /* set enable-bit in TSTAMP_CTRL_REG */ writel(1, 0x01720000); } -#endif void clock_init_uart(void) { @@ -80,7 +125,6 @@ void clock_init_uart(void) CONFIG_CONS_INDEX - 1)); } -#ifdef CONFIG_SPL_BUILD void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -108,27 +152,6 @@ void clock_set_pll1(unsigned int clk) C0_CPUX_CLK_SRC_PLL1); } -void clock_set_pll2(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int p = 0; - - /* Switch cluster 1 to 24MHz clock while changing PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_OSC24M); - - writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | - CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000), - &ccm->pll2_c1_cfg); - - sdelay(2000); - - /* Switch cluster 1 back to PLL2 */ - clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, - C1_CPUX_CLK_SRC_PLL2); -} - void clock_set_pll6(unsigned int clk) { struct sunxi_ccm_reg * const ccm = @@ -143,32 +166,6 @@ void clock_set_pll6(unsigned int clk) sdelay(2000); } -void clock_set_pll12(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) - return; - - writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), - &ccm->pll12_periph1_cfg); - - sdelay(2000); -} - - -void clock_set_pll4(unsigned int clk) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), - &ccm->pll4_periph0_cfg); - - sdelay(2000); -} -#endif int clock_twi_onoff(int port, int state) { @@ -193,7 +190,9 @@ int clock_twi_onoff(int port, int state) return 0; } +#endif /* CONFIG_SPL_BUILD */ +/* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 72faa7171c1..7acb44f52ae 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -72,18 +72,27 @@ #define SUN6I_CTL_ENABLE BIT(0) #define SUN6I_CTL_MASTER BIT(1) #define SUN6I_CTL_SRST BIT(31) +#define SUN6I_TCR_SDM BIT(13) #define SUN6I_TCR_XCH BIT(31) /*****************************************************************************/ -#define CCM_AHB_GATING0 (0x01C20000 + 0x60) -#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) -#ifdef CONFIG_SUN50I_GEN_H6 -#define CCM_SPI0_CLK (0x03001000 + 0x940) +#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) +#define CCM_BASE 0x03001000 +#elif IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) +#define CCM_BASE 0x02001000 #else -#define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#define CCM_BASE 0x01C20000 #endif -#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) + +#define CCM_AHB_GATING0 (CCM_BASE + 0x60) +#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c) +#if IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) +#define CCM_SPI0_CLK (CCM_BASE + 0x940) +#else +#define CCM_SPI0_CLK (CCM_BASE + 0xA0) +#endif +#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0) #define AHB_RESET_SPI0_SHIFT 20 #define AHB_GATE_OFFSET_SPI0 20 @@ -101,17 +110,22 @@ */ static void spi0_pinmux_setup(unsigned int pin_function) { - /* All chips use PC0 and PC2. */ - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + /* All chips use PC2. And all chips use PC0, except R528/T113 */ + if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - /* All chips except H6 and H616 use PC1. */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + /* All chips except H6/H616/R528/T113 use PC1. */ + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); /* Older generations use PC23 for CS, newer ones use PC3. */ @@ -125,7 +139,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6); + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2); } static uintptr_t spi0_base_address(void) @@ -136,6 +151,9 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) return 0x05010000; + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + return 0x04025000; + if (!is_sun6i_gen_spi() || IS_ENABLED(CONFIG_MACH_SUNIV)) return 0x01C05000; @@ -151,23 +169,30 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); if (IS_ENABLED(CONFIG_MACH_SUNIV)) { /* Divide by 32, clock source is AHB clock 200MHz */ writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL); } else { - /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + /* New SoCs do not have a clock divider inside */ + if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + /* Divide by 4 */ + writel(SPI0_CLK_DIV_BY_4, + base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : + SUN4I_SPI0_CCTL)); + } + /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); } @@ -179,6 +204,14 @@ static void spi0_enable_clock(void) /* Wait for completion */ while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; + + /* + * For new SoCs we should configure sample mode depending on + * input clock. As 24MHz from OSC24M is used, we could use + * normal sample mode by setting SDM bit in the TCR register + */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM); } else { /* Enable SPI in the master mode and reset FIFO */ setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | @@ -205,11 +238,13 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && + !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -223,7 +258,8 @@ static void spi0_init(void) if (IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6)) pin_function = SUN50I_GPC_SPI0; - else if (IS_ENABLED(CONFIG_MACH_SUNIV)) + else if (IS_ENABLED(CONFIG_MACH_SUNIV) || + IS_ENABLED(CONFIG_MACH_SUN8I_R528)) pin_function = SUNIV_GPC_SPI0; spi0_pinmux_setup(pin_function); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 05e194de082..04612895576 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -219,6 +219,10 @@ config TEGRA_ENABLE_UARTC config TEGRA_ENABLE_UARTD bool "Use UARTD" +config TEGRA_ENABLE_UARTE + bool "Use UARTE" + depends on TEGRA20 || TEGRA30 + endchoice config TEGRA_GPU diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index 5ccd9545cb5..6e1fd938f52 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -8,7 +8,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o obj-y += bdinfo.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += interrupts.o obj-y += time.o diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile index 2f234825f80..dfd8135f4f2 100644 --- a/arch/microblaze/lib/Makefile +++ b/arch/microblaze/lib/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-y += muldi3.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 4386eb4d6d1..1621cc9a1ff 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -10,7 +10,7 @@ obj-y += reloc.o obj-y += stack.o obj-y += traps.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile index 68a5ca007d5..a9f3c7100e7 100644 --- a/arch/nios2/lib/Makefile +++ b/arch/nios2/lib/Makefile @@ -4,5 +4,5 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += cache.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += libgcc.o diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index aac4203a6e4..d1abe8f00bf 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -92,6 +92,12 @@ void cpu_init_f(immap_t __iomem *immr) CONFIG_SYS_PLPRCR); #endif + /* Set SDMA configuration register */ + if (IS_ENABLED(CONFIG_MPC885)) + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040); + else + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); + /* * Memory Controller: */ diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts index 7b9566a0fa4..454ceb91ca0 100644 --- a/arch/powerpc/dts/cmpc885.dts +++ b/arch/powerpc/dts/cmpc885.dts @@ -83,13 +83,23 @@ spi: spi@aa0 { status = "okay"; #address-cells = <1>; - #size-cells = <1>; - cell-index = <0>; + #size-cells = <0>; compatible = "fsl,mpc8xx-spi"; - gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */ + gpios = <&CPM1_PIO_B 21 1 /* /EEPROM_CS ACTIVE_LOW */ + &CPM1_PIO_B 23 1 /* Temperature mother board */ + &CPM1_PIO_B 14 1>; /* Temperature CPU board */ eeprom@0 { - cell-index = <1>; + reg = <0>; + compatible = "atmel,at25", "cs,eeprom"; + }; + temp@1 { + reg = <1>; + compatible = "ti,lm74"; + }; + temp@2 { + reg = <2>; + compatible = "ti,lm74"; }; }; }; diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts index c27d9dba335..1dfa864ebba 100644 --- a/arch/powerpc/dts/cmpcpro.dts +++ b/arch/powerpc/dts/cmpcpro.dts @@ -140,11 +140,21 @@ compatible = "fsl,mpc832x-spi"; reg = <0x4c0 0x40>; mode = "cpu"; - gpios = <&qe_pio_d 3 1>; + gpios = <&qe_pio_d 3 1 + &qe_pio_c 5 1 /* TEMP mother board */ + &qe_pio_c 3 1>; /* TEMP CPU board */ clock-frequency = <0>; - eeprom@3 { + eeprom@0 { + reg = <0>; compatible = "atmel,at25", "cs,eeprom"; - cell-index = <1>; + }; + temp@1 { + reg = <1>; + compatible = "ti,lm74"; + }; + temp@2 { + reg = <2>; + compatible = "ti,lm74"; }; }; eth0: ucc@3000 { diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts index c4d7737bc67..aa46007b8d9 100644 --- a/arch/powerpc/dts/mcr3000.dts +++ b/arch/powerpc/dts/mcr3000.dts @@ -26,6 +26,47 @@ timeout-sec = <2>; hw_margin_ms = <1000>; }; + + spi: spi@aa0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8xx-spi"; + gpios = <&csspi 2 0 + &csspi 0 0>; + + temp@0 { + reg = <0>; + compatible = "ti,lm74"; + }; + fpga@1 { + reg = <1>; + }; + }; + }; + + localbus@ff000100 { + compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xff000100 0x40>; // ORx and BRx register + + ranges = <0 0 0x04000000 0x04000000 // BOOT + 1 0 0x00000000 0x04000000 // SDRAM + 2 0 0x08000000 0x04000000 // RAMDP + 3 0 0x0C000000 0x04000000 // NAND + 4 0 0x10000000 0x04000000 // Periphs + 5 0 0x14000000 0x04000000 // FPGA + 6 0 0x18000000 0x04000000 // mezzanine + 7 0 0x1c000000 0x04000000>; // DSP + + csspi: gpio-controller@2 { + #gpio-cells = <2>; + compatible = "s3k,mcr3000-cpld-csspi"; + reg = <4 0x802 2>; + gpio-controller; + }; }; SERIAL: smc@0 { diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index dcce9834927..bb819dcbb6c 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -34,7 +34,7 @@ obj-y += ticks.o endif obj-y += reloc.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o obj-y += interrupts.o diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 0b2c88db6ba..9a05b662fd6 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -6,7 +6,7 @@ # Copyright (C) 2017 Andes Technology Corporation # Rick Chen, Andes Technology Corporation <rick@andestech.com> -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index cbae5109e85..154a5d77490 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -188,7 +188,7 @@ int os_read_file(const char *fname, void **bufp, int *sizep) fd = os_open(fname, OS_O_RDONLY); if (fd < 0) { printf("Cannot open file '%s'\n", fname); - goto err; + return -EIO; } size = os_filesize(fd); if (size < 0) { diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index c4924b23c83..a2bc5a7ee60 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -7,5 +7,5 @@ obj-y += fdt_fixup.o interrupts.o sections.o obj-$(CONFIG_PCI) += pci_io.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 8c3c30293a3..e7520a328d5 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -6,7 +6,7 @@ extra-y += start.o obj-y += board.o -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += time.o obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 94aa335ede4..8fc35e1b51e 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_X86_32BIT_INIT) += string.o endif ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o endif obj-y += cmd_boot.o obj-$(CONFIG_$(SPL_)COREBOOT_SYSINFO) += coreboot/ diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 4e4cf18dec5..c15f11f8cdf 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -283,7 +283,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { int ret; - printf("Jumping to 64-bit U-Boot\n"); + printf("Jumping to 64-bit U-Boot: Note many features are missing\n"); ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); debug("ret=%d\n", ret); hang(); diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 12eae17c396..1095dc92c5a 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -98,6 +98,8 @@ int write_tables(void) int size = table->size ? : CONFIG_ROM_TABLE_SIZE; u32 rom_table_end; + rom_addr = ALIGN(rom_addr, 16); + if (!strcmp("smbios", table->name)) gd->arch.smbios_start = rom_addr; diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile index bb9157f30f0..ad4fe32cb69 100644 --- a/arch/xtensa/lib/Makefile +++ b/arch/xtensa/lib/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2007 - 2013 Tensilica Inc. # (C) Copyright 2014 - 2016 Cadence Design Systems Inc. -obj-$(CONFIG_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o misc.o relocate.o time.o |