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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi16
-rw-r--r--arch/arm/dts/imx8mp-debix-model-a.dts507
-rw-r--r--arch/arm/dts/tegra-u-boot.dtsi22
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra.h3
-rw-r--r--arch/arm/include/asm/arch-tegra/usb.h11
-rw-r--r--arch/arm/include/asm/arch-tegra30/funcmux.h1
-rw-r--r--arch/arm/include/asm/mach-imx/ele_api.h4
-rw-r--r--arch/arm/mach-imx/imx8/ahab.c8
-rw-r--r--arch/arm/mach-imx/imx8/cpu.c35
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig1
-rw-r--r--arch/arm/mach-tegra/ap.c11
-rw-r--r--arch/arm/mach-tegra/board.c2
-rw-r--r--arch/arm/mach-tegra/board2.c16
14 files changed, 94 insertions, 544 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 65176c8fb83..73efdcf9756 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -967,7 +967,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
- imx8mp-debix-model-a.dtb \
imx8mp-dhcom-drc02.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
index 33bd89a8434..d5bd9f591e5 100644
--- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi
@@ -20,6 +20,14 @@
};
};
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
+ bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
+ bootph-pre-ram;
+};
+
&crypto {
bootph-pre-ram;
};
@@ -88,14 +96,6 @@
bootph-pre-ram;
};
-&pmic {
- bootph-pre-ram;
-
- regulators {
- bootph-pre-ram;
- };
-};
-
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts
deleted file mode 100644
index 58dae612b4b..00000000000
--- a/arch/arm/dts/imx8mp-debix-model-a.dts
+++ /dev/null
@@ -1,507 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- * Copyright 2022 Ideas on Board Oy
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/usb/pd.h>
-
-#include "imx8mp.dtsi"
-
-/ {
- model = "Polyhex Debix Model A i.MX8MPlus board";
- compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_led>;
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-connection-type = "rgmii-id";
- phy-handle = <&ethphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 { /* RTL8211E */
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
- reset-assert-us = <20>;
- reset-deassert-us = <200000>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic: pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_EDGE_RISING>;
-
- regulators {
- buck1: BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4{
- regulator-name = "BUCK4";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5{
- regulator-name = "BUCK5";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: LDO2 {
- regulator-name = "LDO2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-name = "LDO4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5: LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- interrupt-parent = <&gpio2>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rtc_int>;
- };
-};
-
-&i2c6 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c6>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart2 {
- /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-/* SD Card */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&reg_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
- MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
- MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
- MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
- MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
- >;
- };
-
- pinctrl_gpio_led: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
- MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c6: i2c6grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
- MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
- >;
- };
-
- pinctrl_rtc_int: rtcintgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
- MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
- >;
- };
-};
-
diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi
index b3d0dec7757..c200f2d3a0b 100644
--- a/arch/arm/dts/tegra-u-boot.dtsi
+++ b/arch/arm/dts/tegra-u-boot.dtsi
@@ -19,6 +19,27 @@
};
};
+#ifdef CONFIG_MULTI_DTB_FIT
+ image2 {
+ filename = "u-boot-dtb-tegra.bin";
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+ u-boot-nodtb {
+ offset = <(U_BOOT_OFFSET)>;
+ };
+ fit-dtb {
+#ifdef CONFIG_MULTI_DTB_FIT_LZO
+ filename = "fit-dtb.blob.lzo";
+#elif CONFIG_MULTI_DTB_FIT_GZIP
+ filename = "fit-dtb.blob.gz";
+#else
+ filename = "fit-dtb.blob";
+#endif
+ type = "blob";
+ };
+ };
+#else
/* Same as image1 - some tools still expect the -dtb suffix */
image2 {
filename = "u-boot-dtb-tegra.bin";
@@ -29,6 +50,7 @@
offset = <(U_BOOT_OFFSET)>;
};
};
+#endif
image3 {
filename = "u-boot-nodtb-tegra.bin";
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 7a4e0972fb7..a399c94213b 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -68,8 +68,9 @@ struct timerus {
/* These are the available SKUs (product types) for Tegra */
enum {
- SKU_ID_T20_7 = 0x7,
+ SKU_ID_AP20 = 0x7,
SKU_ID_T20 = 0x8,
+ SKU_ID_AP20H = 0xf,
SKU_ID_T25SE = 0x14,
SKU_ID_AP25 = 0x17,
SKU_ID_T25 = 0x18,
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index 6e6ea1443cb..2ae109ab6c1 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -336,10 +336,13 @@ struct usb_ctlr {
#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
#define UTMIP_XCVR_HSSLEW_MSB_MASK \
(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
-#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_SHIFT 0
-#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
+#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
+#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
+#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
+#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
+#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
/* USBx_UTMIP_XCVR_CFG1_0 */
#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
index 2e8b3359161..05414061a23 100644
--- a/arch/arm/include/asm/arch-tegra30/funcmux.h
+++ b/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -16,5 +16,6 @@ enum {
/* UART configs */
FUNCMUX_UART1_ULPI = 0,
+ FUNCMUX_UART5_SDMMC1 = 1,
};
#endif /* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index d4ac567e7ed..19d12696a1e 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -47,6 +47,8 @@
#define ELE_ATTEST_REQ (0xDB)
#define ELE_RELEASE_PATCH_REQ (0xDC)
#define ELE_OTP_SEQ_SWITH_REQ (0xDD)
+#define ELE_WRITE_SHADOW_REQ (0xF2)
+#define ELE_READ_SHADOW_REQ (0xF3)
/* ELE failure indications */
#define ELE_ROM_PING_FAILURE_IND (0x0A)
@@ -154,4 +156,6 @@ int ele_release_m33_trout(void);
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
int ele_start_rng(void);
+int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response);
+int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response);
#endif
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index ed44df394b1..324e010bb2c 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -345,9 +345,9 @@ int ahab_close(void)
u16 lc;
err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
- if (err != SC_ERR_NONE) {
+ if (err) {
printf("Error in get lifecycle\n");
- return -EIO;
+ return err;
}
if (lc != 0x20) {
@@ -357,9 +357,9 @@ int ahab_close(void)
}
err = sc_seco_forward_lifecycle(-1, 16);
- if (err != SC_ERR_NONE) {
+ if (err) {
printf("Error in forward lifecycle to OEM closed\n");
- return -EIO;
+ return err;
}
return 0;
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2ff4ff35e49..37a5473ac7c 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -48,7 +48,7 @@ static char *get_reset_cause(void)
{
sc_pm_reset_reason_t reason;
- if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE)
+ if (sc_pm_reset_reason(-1, &reason))
return "Unknown reset";
switch (reason) {
@@ -160,6 +160,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
sc_faddr_t tcml_addr;
u32 tcml_size = SZ_128K;
ulong addr;
+ int ret;
switch (core_id) {
case 0:
@@ -187,10 +188,12 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
printf("Power on M4 and MU\n");
- if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
- return -EIO;
+ ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
+ return ret;
- if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
return -EIO;
printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
@@ -199,7 +202,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
memcpy((void *)tcml_addr, (void *)addr, tcml_size);
printf("Start M4 %u\n", core_id);
- if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+ ret = sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr);
+ if (ret)
return -EIO;
printf("bootaux complete\n");
@@ -214,6 +218,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
sc_faddr_t aux_core_ram;
u32 size;
ulong addr;
+ int ret;
switch (core_id) {
case 0:
@@ -242,20 +247,23 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
printf("Power on aux core %d\n", core_id);
- if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
- return -EIO;
+ ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
+ return ret;
if (mu_rsrc != SC_R_NONE) {
- if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+ ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON);
+ if (ret)
return -EIO;
}
if (core_id == 1) {
struct power_domain pd;
- if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
+ ret = sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false);
+ if (ret) {
printf("Error enable clock\n");
- return -EIO;
+ return ret;
}
if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) {
@@ -286,8 +294,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
- if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
- return -EIO;
+ ret = sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram);
+ if (ret)
+ return ret;
printf("bootaux complete\n");
return 0;
@@ -313,7 +322,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
return 0;
}
- if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
+ if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode))
return 0;
if (power_mode != SC_PM_PW_MODE_OFF)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d1fdaec7043..9d1fabe91c0 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -197,6 +197,7 @@ config TARGET_IMX8MP_DEBIX_MODEL_A
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index 1ea620e4ab5..f35bdba4d48 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -32,7 +32,7 @@ int tegra_get_chip(void)
* Tegra30, 0x35 for T114, and 0x40 for Tegra124.
*/
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
- debug("%s: CHIPID is 0x%02X\n", __func__, rev);
+ debug("%s: CHIPID is 0x%02x\n", __func__, rev);
return rev;
}
@@ -43,7 +43,7 @@ int tegra_get_sku_info(void)
struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
sku_id = readl(&fuse->sku_info) & 0xff;
- debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
+ debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id);
return sku_id;
}
@@ -58,8 +58,9 @@ int tegra_get_chip_sku(void)
switch (chip_id) {
case CHIPID_TEGRA20:
switch (sku_id) {
- case SKU_ID_T20_7:
+ case SKU_ID_AP20:
case SKU_ID_T20:
+ case SKU_ID_AP20H:
return TEGRA_SOC_T20;
case SKU_ID_T25SE:
case SKU_ID_AP25:
@@ -103,8 +104,8 @@ int tegra_get_chip_sku(void)
}
/* unknown chip/sku id */
- printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
- __func__, chip_id, sku_id);
+ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n",
+ __func__, chip_id, sku_id);
return TEGRA_SOC_UNKNOWN;
}
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index cc37878b8d1..7ca56a3b081 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -181,7 +181,7 @@ static int uart_configs[] = {
-1,
-1,
-1,
- -1,
+ FUNCMUX_UART5_SDMMC1, /* UARTE */
#elif defined(CONFIG_TEGRA114)
-1,
-1,
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 8e7fd7efc7b..6e9ef68caf9 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -6,6 +6,7 @@
#include <config.h>
#include <dm.h>
+#include <dm/root.h>
#include <env.h>
#include <errno.h>
#include <init.h>
@@ -457,3 +458,18 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
+
+#if IS_ENABLED(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ int ret, rescan;
+
+ ret = fdtdec_resetup(&rescan);
+ if (!ret && rescan) {
+ dm_uninit();
+ dm_init_and_scan(true);
+ }
+
+ return 0;
+}
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-19 07:54:54 +0000