diff options
Diffstat (limited to 'arch')
49 files changed, 1770 insertions, 134 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ada164d4bd8..8d9f7fcce78 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1675,6 +1675,10 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_PRESIDIO_ASIC + bool "Support Cortina Presidio ASIC Platform" + select ARM64 + endchoice config ARCH_SUPPORT_TFABOOT @@ -1823,6 +1827,7 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9303beb2f56..4fee5cc4894 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -718,6 +718,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ + imx8mm-verdin.dtb \ imx8mn-ddr4-evk.dtb \ imx8mq-evk.dtb \ imx8mp-evk.dtb @@ -909,6 +910,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/ca-presidio-engboard.dts b/arch/arm/dts/ca-presidio-engboard.dts new file mode 100644 index 00000000000..c03dacc54a2 --- /dev/null +++ b/arch/arm/dts/ca-presidio-engboard.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Cortina Access Inc. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + + mmc0: mmc@f4400000 { + compatible = "snps,dw-cortina"; + reg = <0x0 0xf4400000 0x1000>; + bus-width = <4>; + io_ds = <0x77>; + fifo-mode; + sd_dll_ctrl = <0xf43200e8>; + io_drv_ctrl = <0xf432004c>; + }; + + gpio0: gpio-controller@0xf4329280 { + compatible = "cortina,ca-gpio"; + reg = <0x0 0xf4329280 0x24>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + gpio1: gpio-controller@0xf43292a4 { + compatible = "cortina,ca-gpio"; + reg = <0x0 0xf43292a4 0x24>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + watchdog: watchdog@0xf432901c { + compatible = "cortina,ca-wdt"; + reg = <0x0 0xf432901c 0x34>, + <0x0 0xf4320020 0x04>; + status = "okay"; + }; + + uart0: serial@0xf4329148 { + u-boot,dm-pre-reloc; + compatible = "cortina,ca-uart"; + reg = <0x0 0xf4329148 0x30>; + status = "okay"; + }; + + i2c: i2c@f4329120 { + compatible = "cortina,ca-i2c"; + reg = <0x0 0xf4329120 0x28>; + clock-frequency = <400000>; + }; + + sflash: sflash-controller@f4324000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "cortina,ca-sflash"; + reg = <0x0 0xf4324000 0x50>; + reg-names = "sflash-regs"; + flash@0 { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <1>; + spi-max-frequency = <108000000>; + }; + }; +}; diff --git a/arch/arm/dts/imx28-xea.dts b/arch/arm/dts/imx28-xea.dts index 5de6774c5a4..de049042f83 100644 --- a/arch/arm/dts/imx28-xea.dts +++ b/arch/arm/dts/imx28-xea.dts @@ -38,6 +38,8 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; }; }; diff --git a/arch/arm/dts/imx53-ppd-uboot.dtsi b/arch/arm/dts/imx53-ppd-uboot.dtsi index 88dd7e29393..d38a1bc264c 100644 --- a/arch/arm/dts/imx53-ppd-uboot.dtsi +++ b/arch/arm/dts/imx53-ppd-uboot.dtsi @@ -9,4 +9,50 @@ compatible = "wdt-reboot"; wdt = <&wdog1>; }; + + bootcount { + compatible = "u-boot,bootcount-i2c-eeprom"; + i2c-eeprom = <&bootcount>; + }; + + panel-lvds0 { + compatible = "simple-panel"; + backlight = <&pwm_bl>; + }; +}; + +&eeprom { + partitions { + compatible = "fixed-partitions"; + + vpd { + offset = <0>; + size = <1022>; + }; + + bootcount: bootcount { + offset = <1022>; + size = <2>; + }; + }; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index ae98361f9ab..a6278476d37 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -43,7 +43,6 @@ /dts-v1/; #include "imx53.dtsi" -#include "imx53-ppd-uboot.dtsi" #include <dt-bindings/input/input.h> / { @@ -490,7 +489,7 @@ reg = <1>; rtc@30 { - compatible = "sii,s35390a"; + compatible = "sii,s35392a-rtc"; reg = <0x30>; }; @@ -1084,3 +1083,5 @@ >; }; }; + +#include "imx53-ppd-uboot.dtsi" diff --git a/arch/arm/dts/imx6q-b450v3.dts b/arch/arm/dts/imx6q-b450v3.dts index 7fca833cbf9..995caa8a331 100644 --- a/arch/arm/dts/imx6q-b450v3.dts +++ b/arch/arm/dts/imx6q-b450v3.dts @@ -158,3 +158,5 @@ }; }; }; + +#include "imx6q-bx50v3-uboot.dtsi" diff --git a/arch/arm/dts/imx6q-b650v3.dts b/arch/arm/dts/imx6q-b650v3.dts index ba12e9be5fb..95a61347da5 100644 --- a/arch/arm/dts/imx6q-b650v3.dts +++ b/arch/arm/dts/imx6q-b650v3.dts @@ -157,3 +157,5 @@ }; }; }; + +#include "imx6q-bx50v3-uboot.dtsi" diff --git a/arch/arm/dts/imx6q-b850v3.dts b/arch/arm/dts/imx6q-b850v3.dts index 0a985526912..6416825234b 100644 --- a/arch/arm/dts/imx6q-b850v3.dts +++ b/arch/arm/dts/imx6q-b850v3.dts @@ -300,3 +300,5 @@ phy-handle = <&switchphy4>; }; }; + +#include "imx6q-bx50v3-uboot.dtsi" diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi index 88dd7e29393..df446e0ed14 100644 --- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi +++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi @@ -5,8 +5,33 @@ */ / { + bootcount { + compatible = "u-boot,bootcount-i2c-eeprom"; + i2c-eeprom = <&bootcount>; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; }; + + panel-lvds0 { + compatible = "simple-panel"; + }; +}; + +&eeprom { + partitions { + compatible = "fixed-partitions"; + + vpd { + offset = <0>; + size = <1022>; + }; + + bootcount: bootcount { + offset = <1022>; + size = <2>; + }; + }; }; diff --git a/arch/arm/dts/imx6q-bx50v3.dtsi b/arch/arm/dts/imx6q-bx50v3.dtsi index bb8f5623079..19829613c04 100644 --- a/arch/arm/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/dts/imx6q-bx50v3.dtsi @@ -42,7 +42,6 @@ */ #include "imx6q-ba16.dtsi" -#include "imx6q-bx50v3-uboot.dtsi" / { mclk: clock-mclk { @@ -379,3 +378,5 @@ #interrupt-cells = <1>; }; }; + +#include "imx6q-bx50v3-uboot.dtsi" diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi index 05dd74eee10..b78358fa139 100644 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -1,3 +1,7 @@ &fec2 { status = "disable"; }; + +&usbotg1 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi new file mode 100644 index 00000000000..6319840b1ce --- /dev/null +++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi @@ -0,0 +1,10 @@ +/ { + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg1; + }; + + chosen { + stdout-path = &uart1; + }; +}; diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts index db5ef67eb13..f7ba2c0a24a 100644 --- a/arch/arm/dts/imx7s-warp.dts +++ b/arch/arm/dts/imx7s-warp.dts @@ -17,15 +17,6 @@ reg = <0x80000000 0x20000000>; }; - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - }; - - chosen { - stdout-path = &uart1; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&pinctrl_gpio>; diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h index e25f7fcd799..5ccc4cc9195 100644 --- a/arch/arm/dts/imx8mm-pinfunc.h +++ b/arch/arm/dts/imx8mm-pinfunc.h @@ -430,18 +430,26 @@ #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 #define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 @@ -462,23 +470,31 @@ #define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi new file mode 100644 index 00000000000..d091577a96f --- /dev/null +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts new file mode 100644 index 00000000000..2980053e82b --- /dev/null +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -0,0 +1,1007 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mm.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini Quad/DualLite"; + compatible = "toradex,verdin-imx8mm", "fsl,imx8mm"; + + chosen { + stdout-path = &uart1; + }; + + /* fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_ethphy: regulator-ethphy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "V3.3_ETH"; + startup-delay-us = <200000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB1_EN */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB2_EN */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-name = "V3.3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + }; + + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-name = "V3.3_WI-FI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + }; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +&clk { + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; + assigned-clock-rates = <786432000>, <722534400>; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev20: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* On-module CAN controller 1 & 2 */ +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, + <&gpio1 5 GPIO_ACTIVE_LOW>; + /* This property is required, even if marked as obsolete in the doku */ + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can1: can@0 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + microchip,clock-allways-on; + microchip,clock-out-div = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + can2: can@1 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_int>; + reg = <1>; + spi-max-frequency = <2000000>; + }; +}; + +&fec1 { + fsl,magic-packet; + fsl,rgmii_rxc_dly; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-supply = <®_ethphy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +&gpio4 { + /* + * The SE050 security element may be driven via I2C from user space. + * The element itself is enabled here as it has no kernel driver. + */ + se050_ena { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + line-name = "SE050_ENABLE"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_se050_ena>; + }; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71840", "rohm,bd71837"; + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x4b>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + buck1_reg: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck1"; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck2"; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck5_reg: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck5"; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + buck6_reg: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck6"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + buck7_reg: BUCK7 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck7"; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + }; + + buck8_reg: BUCK8 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck8"; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + ldo1_reg: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo1"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + ldo2_reg: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo2"; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + }; + + ldo3_reg: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo4"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + ldo5_reg: LDO5 { + regulator-compatible = "ldo5"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo6"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; + + /* Epson RX8130 real time clock on carrier board */ + rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + adc@34 { + compatible = "maxim,max11607"; + reg = <0x34>; + vcc-supply = <&ldo5_reg>; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +/* Verdin I2C_3_HDMI N/A */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + /* Audio Codec */ + wm8904_1a: codec@1a { + compatible = "wlf,wm8904"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + clock-names = "mclk"; + reg = <0x1a>; + }; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "okay"; + }; + + /* EEPROM on MIPI-DSI to HDMI adapter */ + eeprom_50: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + /* EEPROM on Verdin Development board */ + eeprom_57: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + }; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* Verdin UART_3, Console/Debug UART */ +&uart1 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* Verdin UART_4 */ +/* + * resource allocated to M4 by default, must not be accessed from A-35 or you + * get an OOPS + */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + dr_mode = "otg"; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + dr_mode = "host"; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pm-ignore-notify; + status = "okay"; + /* TODO Strobe */ +}; + +/* Verdin SD_1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>, + <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, + <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>; + + pinctrl_can1_int: can1intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 + >; + }; + + pinctrl_can2_int: can2intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 + >; + }; + + pinctrl_ctrl_force_off_moci: ctrlforceoffgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */ + >; + }; + + pinctrl_dsi_bkl_en: dsi_bkl_en { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + >; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ + >; + }; + + /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */ + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + >; + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + >; + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + >; + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + >; + }; + + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ + >; + }; + + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ + >; + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ + >; + }; + + /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */ + pinctrl_gpio_hpd: gpiohpdgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ + >; + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */ + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_pwm_1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */ + >; + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */ + >; + }; + + pinctrl_pwm_3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */ + >; + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 + >; + }; + + pinctrl_reg_usb1_en: regusb1engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + >; + }; + + pinctrl_reg_usb2_en: regusb2engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ + >; + }; + + pinctrl_se050_ena: se050enagrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 /* SODIMM 147 */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 /* SODIMM 149 */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4 /* SODIMM 129 */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + >; + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */ + >; + }; + + pinctrl_wifi_i2s: wifii2sgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 + >; + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + >; + }; +}; diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts index ec30f5c6eb3..f05c3fe14d7 100644 --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts @@ -178,3 +178,16 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 7dcca5c6af3..1e8ec9b48be 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -7,6 +7,9 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt7622-clk.h> +#include <dt-bindings/power/mt7629-power.h> +#include <dt-bindings/reset/mt7629-reset.h> +#include <dt-bindings/gpio/gpio.h> / { compatible = "mediatek,mt7622"; @@ -182,4 +185,46 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7622-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt7622-eth", "syscon"; + reg = <0x1b100000 0x20000>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <ðsys CLK_ETH_ESW_EN>, + <ðsys CLK_ETH_GP0_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_GP2_EN>, + <&sgmiisys CLK_SGMII_TX250M_EN>, + <&sgmiisys CLK_SGMII_RX250M_EN>, + <&sgmiisys CLK_SGMII_CDR_REF>, + <&sgmiisys CLK_SGMII_CDR_FB>, + <&topckgen CLK_TOP_SGMIIPLL>, + <&apmixedsys CLK_APMIXED_ETH2PLL>; + clock-names = "ethif", "esw", "gp0", "gp1", "gp2", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", + "eth2pll"; + power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; + resets = <ðsys ETHSYS_FE_RST>; + reset-names = "fe"; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys: sgmiisys@1b128000 { + compatible = "mediatek,mt7622-sgmiisys", "syscon"; + reg = <0x1b128000 0x3000>; + #clock-cells = <1>; + }; + }; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 44bedd8b673..2e4468e8d80 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -56,3 +56,7 @@ &portc { bank-name = "portc"; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 38855aecd7e..a903040d604 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -31,3 +31,7 @@ &sysmgr { u-boot,dm-pre-reloc; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 39ffc18e29e..84e5cb46e5a 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -4,8 +4,8 @@ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_LS1012A) && \ - !defined(CONFIG_ARCH_U8500) + !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_U8500) && \ + !defined(CONFIG_CORTINA_PLATFORM) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-cortina/Makefile b/arch/arm/mach-cortina/Makefile new file mode 100644 index 00000000000..ffb86922713 --- /dev/null +++ b/arch/arm/mach-cortina/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2020 Cortina Access Inc. +# +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 72affb1bdc1..58f1758ab6f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -50,11 +50,18 @@ config TARGET_IMX8MP_EVK select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_VERDIN_IMX8MM + bool "Support Toradex Verdin iMX8M Mini module" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + endchoice source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" +source "board/toradex/verdin-imx8mm/Kconfig" endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9d91f9ab44f..f9f576d4039 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -259,7 +259,16 @@ config TARGET_GW_VENTANA config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" select BOARD_LATE_INIT + select DM_ETH + select DM_GPIO + select DM_MMC + select DM_PCI + select DM_SCSI + select DM_USB + select DM_VIDEO + select OF_CONTROL select SUPPORT_SPL + imply CMD_DM config TARGET_MCCMON6 bool "mccmon6" diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index c41208591a1..8818a6b967f 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -146,24 +146,51 @@ struct socfpga_sdram_rw_mgr_config { u8 lfsr_wr_rd_dm_bank_0_nop; u8 lfsr_wr_rd_dm_bank_0_wait; u8 lfsr_wr_rd_dm_bank_0_wl_1; - u8 mrs0_dll_reset; - u8 mrs0_dll_reset_mirr; - u8 mrs0_user; - u8 mrs0_user_mirr; - u8 mrs1; + union { + u8 mrs0_dll_reset; + u8 mr_dll_reset; + }; + union { + u8 mrs0_dll_reset_mirr; + u8 emr_ocd_enable; + }; + union { + u8 mrs0_user; + u8 mr_user; + }; + union { + u8 mrs0_user_mirr; + u8 mr_calib; + }; + union { + u8 mrs1; + u8 emr; + }; + union { + u8 mrs2; + u8 emr2; + }; + union { + u8 mrs3; + u8 emr3; + }; u8 mrs1_mirr; - u8 mrs2; u8 mrs2_mirr; - u8 mrs3; u8 mrs3_mirr; u8 precharge_all; u8 read_b2b; u8 read_b2b_wait1; u8 read_b2b_wait2; - u8 refresh_all; + union { + u8 refresh; + u8 refresh_all; + }; u8 rreturn; u8 sgle_read; - u8 zqcl; + union { + u8 zqcl; + u8 nop; + }; u8 true_mem_data_mask_width; u8 mem_address_mirroring; @@ -199,6 +226,7 @@ struct socfpga_sdram_io_config { struct socfpga_sdram_misc_config { u32 reg_file_init_seq_signature; + u16 afi_clk_freq; u8 afi_rate_ratio; u8 calib_lfifo_offset; u8 calib_vfifo_offset; diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh index 3a442bc5d82..a49cd1b68a9 100755 --- a/arch/arm/mach-socfpga/qts-filter.sh +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -128,7 +128,7 @@ EOF # Filter out only the macros which are actually used by the code # grep_sdram_config() { - egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]" + egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]" } # diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 70f8455ddca..a01e2a5cb9f 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -138,10 +138,7 @@ void board_init_f(ulong dummy) debug("Reset init failed: %d\n", ret); #ifdef CONFIG_SPL_NAND_DENALI - struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; - - clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); + clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4)); #endif /* enable console uart printing */ diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 2b072cc65e5..4ea32e72c7c 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -80,13 +80,15 @@ static const struct socfpga_sdram_config sdram_config = { SDR_CTRLGRP_DRAMODT_READ_LSB) | (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << SDR_CTRLGRP_DRAMODT_WRITE_LSB), +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ .extratime1 = - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR << - SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC << - SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) | -(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP << - SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB), + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR << + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC << + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP << + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB), +#endif .dram_addrw = (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | @@ -190,7 +192,6 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1, .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1, .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2, - .activate_1 = RW_MGR_ACTIVATE_1, .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE, .guaranteed_read = RW_MGR_GUARANTEED_READ, .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT, @@ -199,11 +200,41 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1, .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2, .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3, - .idle = RW_MGR_IDLE, .idle_loop1 = RW_MGR_IDLE_LOOP1, .idle_loop2 = RW_MGR_IDLE_LOOP2, +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ + .emr = RW_MGR_EMR, + .emr2 = RW_MGR_EMR2, + .emr3 = RW_MGR_EMR3, + .init_reset_0_cke_0 = RW_MGR_INIT_CKE_0, + .nop = RW_MGR_NOP, + .refresh = RW_MGR_REFRESH, + .mr_calib = RW_MGR_MR_CALIB, + .mr_user = RW_MGR_MR_USER, + .mr_dll_reset = RW_MGR_MR_DLL_RESET, + .emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE, +#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ + .activate_1 = RW_MGR_ACTIVATE_1, + .idle = RW_MGR_IDLE, .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0, .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0, + .mrs1 = RW_MGR_MRS1, + .mrs1_mirr = RW_MGR_MRS1_MIRR, + .mrs2 = RW_MGR_MRS2, + .mrs2_mirr = RW_MGR_MRS2_MIRR, + .mrs3 = RW_MGR_MRS3, + .mrs3_mirr = RW_MGR_MRS3_MIRR, + .refresh_all = RW_MGR_REFRESH_ALL, + .rreturn = RW_MGR_RETURN, + .sgle_read = RW_MGR_SGLE_READ, + .zqcl = RW_MGR_ZQCL, + .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET, + .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR, + .mrs0_user = RW_MGR_MRS0_USER, + .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR, +#else +#error LPDDR2 and other DRAM types are not yet supported +#endif .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0, .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA, .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS, @@ -216,24 +247,10 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1, - .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET, - .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR, - .mrs0_user = RW_MGR_MRS0_USER, - .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR, - .mrs1 = RW_MGR_MRS1, - .mrs1_mirr = RW_MGR_MRS1_MIRR, - .mrs2 = RW_MGR_MRS2, - .mrs2_mirr = RW_MGR_MRS2_MIRR, - .mrs3 = RW_MGR_MRS3, - .mrs3_mirr = RW_MGR_MRS3_MIRR, .precharge_all = RW_MGR_PRECHARGE_ALL, .read_b2b = RW_MGR_READ_B2B, .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1, .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2, - .refresh_all = RW_MGR_REFRESH_ALL, - .rreturn = RW_MGR_RETURN, - .sgle_read = RW_MGR_SGLE_READ, - .zqcl = RW_MGR_ZQCL, .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH, .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING, @@ -270,6 +287,9 @@ static const struct socfpga_sdram_io_config io_config = { }; static const struct socfpga_sdram_misc_config misc_config = { +#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ + .afi_clk_freq = AFI_CLK_FREQ, +#endif .afi_rate_ratio = AFI_RATE_RATIO, .calib_lfifo_offset = CALIB_LFIFO_OFFSET, .calib_vfifo_offset = CALIB_VFIFO_OFFSET, diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c index d2bbf3e9968..899bcd86188 100644 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ b/arch/powerpc/cpu/mpc8xx/traps.c @@ -51,7 +51,7 @@ static void print_backtrace(unsigned long *sp) printf("\n"); } -static void show_regs(struct pt_regs *regs) +void show_regs(struct pt_regs *regs) { int i; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 85e15ebffa1..3338b788f84 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -222,6 +222,9 @@ config XIP from a NOR flash memory without copying the code to ram. Say yes here if U-Boot boots from flash directly. +config SHOW_REGS + bool "Show registers on unhandled exception" + config STACK_SIZE_SHIFT int default 14 diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 407ecfa9c07..e40c7bd3f4f 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -64,7 +64,8 @@ trap_entry: SREG x31, 31 * REGBYTES(sp) csrr a0, MODE_PREFIX(cause) csrr a1, MODE_PREFIX(epc) - mv a2, sp + csrr a2, MODE_PREFIX(tval) + mv a3, sp jal handle_trap csrw MODE_PREFIX(epc), a0 diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f3dccdbe4c5..6b3ff99c388 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -359,9 +359,8 @@ relocate_secondary_harts: call_board_init_r: jal invalidate_icache_all jal flush_dcache_all - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ + la t0, board_init_r /* offset of board_init_r() */ + add t4, t0, t6 /* real address of board_init_r() */ /* * setup parameters for board_init_r */ diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 838a8443999..c00d17c7369 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -32,7 +32,6 @@ SECTIONS . = ALIGN(4); .data : { - __global_pointer$ = . + 0x800; *(.data*) } . = ALIGN(4); diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 512dce06196..074c70ee77a 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -5,6 +5,8 @@ * * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick@andestech.com> + * + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> */ #include <common.h> @@ -14,7 +16,34 @@ #include <asm/system.h> #include <asm/encoding.h> -static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) +static void show_regs(struct pt_regs *regs) +{ +#ifdef CONFIG_SHOW_REGS + printf("RA: " REG_FMT " SP: " REG_FMT " GP: " REG_FMT "\n", + regs->ra, regs->sp, regs->gp); + printf("TP: " REG_FMT " T0: " REG_FMT " T1: " REG_FMT "\n", + regs->tp, regs->t0, regs->t1); + printf("T2: " REG_FMT " S0: " REG_FMT " S1: " REG_FMT "\n", + regs->t2, regs->s0, regs->s1); + printf("A0: " REG_FMT " A1: " REG_FMT " A2: " REG_FMT "\n", + regs->a0, regs->a1, regs->a2); + printf("A3: " REG_FMT " A4: " REG_FMT " A5: " REG_FMT "\n", + regs->a3, regs->a4, regs->a5); + printf("A6: " REG_FMT " A7: " REG_FMT " S2: " REG_FMT "\n", + regs->a6, regs->a7, regs->s2); + printf("S3: " REG_FMT " S4: " REG_FMT " S5: " REG_FMT "\n", + regs->s3, regs->s4, regs->s5); + printf("S6: " REG_FMT " S7: " REG_FMT " S8: " REG_FMT "\n", + regs->s6, regs->s7, regs->s8); + printf("S9: " REG_FMT " S10: " REG_FMT " S11: " REG_FMT "\n", + regs->s9, regs->s10, regs->s11); + printf("T3: " REG_FMT " T4: " REG_FMT " T5: " REG_FMT "\n", + regs->t3, regs->t4, regs->t5); + printf("T6: " REG_FMT "\n", regs->t6); +#endif +} + +static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) { static const char * const exception_code[] = { "Instruction address misaligned", @@ -35,14 +64,13 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) "Store/AMO page fault", }; - if (code < ARRAY_SIZE(exception_code)) { - printf("exception code: %ld , %s , epc %lx , ra %lx\n", - code, exception_code[code], epc, regs->ra); - } else { - printf("reserved exception code: %ld , epc %lx , ra %lx\n", - code, epc, regs->ra); - } + if (code < ARRAY_SIZE(exception_code)) + printf("Unhandled exception: %s\n", exception_code[code]); + else + printf("Unhandled exception code: %ld\n", code); + printf("EPC: " REG_FMT " TVAL: " REG_FMT "\n", epc, tval); + show_regs(regs); hang(); } @@ -66,7 +94,7 @@ int disable_interrupts(void) return 0; } -ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) +ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs) { ulong is_irq, irq; @@ -84,11 +112,11 @@ ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) timer_interrupt(0); /* handle timer interrupt */ break; default: - _exit_trap(cause, epc, regs); + _exit_trap(cause, epc, tval, regs); break; }; } else { - _exit_trap(cause, epc, regs); + _exit_trap(cause, epc, tval, regs); } return epc; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 347ea79077d..4a277934a71 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -93,6 +93,7 @@ <&gpio_b 9 0xc 3 2 1>; int-value = <1234>; uint-value = <(-1234)>; + interrupts-extended = <&irq 3 0>; }; junk { @@ -357,8 +358,10 @@ vss-microvolts = <0>; }; - irq { + irq: irq { compatible = "sandbox,irq"; + interrupt-controller; + #interrupt-cells = <2>; }; lcd { diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 92ff494453c..7f99d07c47f 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -45,6 +45,10 @@ #define PCI_EA_BAR2_MAGIC 0x72727272 #define PCI_EA_BAR4_MAGIC 0x74747474 +enum { + SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */ +}; + /* System controller driver data */ enum { SYSCON0 = 32, diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b733d2264ef..c8eae24c075 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -715,6 +715,13 @@ config HAVE_ITSS Select this to include the driver for the Interrupt Timer Subsystem (ITSS) which is found on several Intel devices. +config HAVE_P2SB + bool "Enable P2SB" + help + Select this to include the driver for the Primary to + Sideband Bridge (P2SB) which is found on several Intel + devices. + menu "System tables" depends on !EFI && !SYS_COREBOOT @@ -916,4 +923,37 @@ config X86_OFFSET_SPL depends on SPL && X86 default SPL_TEXT_BASE +config ACPI_GPE + bool "Support ACPI general-purpose events" + help + Enable a driver for ACPI GPEs to allow peripherals to send interrupts + via ACPI to the OS. In U-Boot this is only used when U-Boot itself + needs access to these interrupts. This can happen when it uses a + peripheral that is set up to use GPEs and so cannot use the normal + GPIO mechanism for polling an input. + + See https://queue.acm.org/blogposting.cfm?id=18977 for more info + +config SPL_ACPI_GPE + bool "Support ACPI general-purpose events in SPL" + help + Enable a driver for ACPI GPEs to allow peripherals to send interrupts + via ACPI to the OS. In U-Boot this is only used when U-Boot itself + needs access to these interrupts. This can happen when it uses a + peripheral that is set up to use GPEs and so cannot use the normal + GPIO mechanism for polling an input. + + See https://queue.acm.org/blogposting.cfm?id=18977 for more info + +config TPL_ACPI_GPE + bool "Support ACPI general-purpose events in TPL" + help + Enable a driver for ACPI GPEs to allow peripherals to send interrupts + via ACPI to the OS. In U-Boot this is only used when U-Boot itself + needs access to these interrupts. This can happen when it uses a + peripheral that is set up to use GPEs and so cannot use the normal + GPIO mechanism for polling an input. + + See https://queue.acm.org/blogposting.cfm?id=18977 for more info + endmenu diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 5b40838e60a..307267a8fb3 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o +obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o obj-$(CONFIG_QFW) += qfw_cpu.o ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c new file mode 100644 index 00000000000..55005455c09 --- /dev/null +++ b/arch/x86/cpu/acpi_gpe.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google, LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <dm.h> +#include <irq.h> +#include <asm/io.h> + +/** + * struct acpi_gpe_priv - private driver information + * + * @acpi_base: Base I/O address of ACPI registers + */ +struct acpi_gpe_priv { + ulong acpi_base; +}; + +#define GPE0_STS(x) (0x20 + ((x) * 4)) + +static int acpi_gpe_read_and_clear(struct irq *irq) +{ + struct acpi_gpe_priv *priv = dev_get_priv(irq->dev); + u32 mask, sts; + ulong start; + int ret = 0; + int bank; + + bank = irq->id / 32; + mask = 1 << (irq->id % 32); + + /* Wait up to 1ms for GPE status to clear */ + start = get_timer(0); + do { + if (get_timer(start) > 1) + return ret; + + sts = inl(priv->acpi_base + GPE0_STS(bank)); + if (sts & mask) { + outl(mask, priv->acpi_base + GPE0_STS(bank)); + ret = 1; + } + } while (sts & mask); + + return ret; +} + +static int acpi_gpe_ofdata_to_platdata(struct udevice *dev) +{ + struct acpi_gpe_priv *priv = dev_get_priv(dev); + + priv->acpi_base = dev_read_addr(dev); + if (!priv->acpi_base || priv->acpi_base == FDT_ADDR_T_NONE) + return log_msg_ret("acpi_base", -EINVAL); + + return 0; +} + +static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args) +{ + irq->id = args->args[0]; + + return 0; +} + +static const struct irq_ops acpi_gpe_ops = { + .read_and_clear = acpi_gpe_read_and_clear, + .of_xlate = acpi_gpe_of_xlate, +}; + +static const struct udevice_id acpi_gpe_ids[] = { + { .compatible = "intel,acpi-gpe", .data = X86_IRQT_ACPI_GPE }, + { } +}; + +U_BOOT_DRIVER(acpi_gpe_drv) = { + .name = "acpi_gpe", + .id = UCLASS_IRQ, + .of_match = acpi_gpe_ids, + .ops = &acpi_gpe_ops, + .ofdata_to_platdata = acpi_gpe_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct acpi_gpe_priv), +}; diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index a760e0ac68e..942f11f5665 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -40,6 +40,11 @@ config INTEL_APOLLOLAKE imply INTEL_GPIO imply SMP imply HAVE_ITSS + imply HAVE_P2SB + imply CLK + imply CMD_CLK + imply CLK_INTEL + imply ACPI_GPE if INTEL_APOLLOLAKE diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index f99f2c64739..578e15c4bf7 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -20,7 +20,6 @@ endif obj-y += hostbridge.o obj-y += lpc.o -obj-y += p2sb.o obj-y += pch.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 92ecacf98ac..1f22c1ea3c6 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -25,7 +25,6 @@ #define HIDE_BIT BIT(0) #define INTEL_GSPI_MAX 3 -#define INTEL_I2C_DEV_MAX 8 #define MAX_USB2_PORTS 8 enum { @@ -33,36 +32,6 @@ enum { CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ }; -enum i2c_speed { - I2C_SPEED_STANDARD = 100000, - I2C_SPEED_FAST = 400000, - I2C_SPEED_FAST_PLUS = 1000000, - I2C_SPEED_HIGH = 3400000, - I2C_SPEED_FAST_ULTRA = 5000000, -}; - -/* - * Timing values are in units of clock period, with the clock speed - * provided by the SOC - * - * TODO(sjg@chromium.org): Connect this up to the I2C driver - */ -struct dw_i2c_speed_config { - enum i2c_speed speed; - /* SCL high and low period count */ - u16 scl_lcnt; - u16 scl_hcnt; - /* - * SDA hold time should be 300ns in standard and fast modes - * and long enough for deterministic logic level change in - * fast-plus and high speed modes. - * - * [15:0] SDA TX Hold Time - * [23:16] SDA RX Hold Time - */ - u32 sda_hold; -}; - /* Serial IRQ control. SERIRQ_QUIET is the default (0) */ enum serirq_mode { SERIRQ_QUIET, @@ -70,32 +39,6 @@ enum serirq_mode { SERIRQ_OFF, }; -/* - * This I2C controller has support for 3 independent speed configs but can - * support both FAST_PLUS and HIGH speeds through the same set of speed - * config registers. These are treated separately so the speed config values - * can be provided via ACPI to the OS. - */ -#define DW_I2C_SPEED_CONFIG_COUNT 4 - -struct dw_i2c_bus_config { - /* Bus should be enabled in TPL with temporary base */ - int early_init; - /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ - enum i2c_speed speed; - /* - * If rise_time_ns is non-zero the calculations for lcnt and hcnt - * registers take into account the times of the bus. However, if - * there is a match in speed_config those register values take - * precedence - */ - int rise_time_ns; - int fall_time_ns; - int data_hold_time_ns; - /* Specific bus speed configuration */ - struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT]; -}; - struct gspi_cfg { /* Bus speed in MHz */ u32 speed_mhz; @@ -111,7 +54,6 @@ struct gspi_cfg { struct soc_intel_common_config { int chipset_lockdown; struct gspi_cfg gspi[INTEL_GSPI_MAX]; - struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX]; }; enum pnp_settings { @@ -594,7 +536,7 @@ int arch_fsps_preinit(void) struct udevice *itss; int ret; - ret = uclass_first_device_err(UCLASS_IRQ, &itss); + ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); /* @@ -635,7 +577,7 @@ int arch_fsp_init_r(void) if (ret) return ret; - ret = uclass_first_device_err(UCLASS_IRQ, &itss); + ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); /* Restore GPIO IRQ polarities back to previous settings */ diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index 70edbe06e4c..4c7e9ea2151 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -15,6 +15,7 @@ #include <efi_loader.h> #include <hang.h> #include <init.h> +#include <irq.h> #include <irq_func.h> #include <asm/control_regs.h> #include <asm/i8259.h> @@ -264,7 +265,7 @@ int interrupt_init(void) int ret; /* Try to set up the interrupt router, but don't require one */ - ret = uclass_first_device_err(UCLASS_IRQ, &dev); + ret = irq_first_device_type(X86_IRQT_BASE, &dev); if (ret && ret != -ENODEV) return ret; diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index e22c70781d6..1736bd2b530 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -28,6 +28,7 @@ endif endif obj-y += pch.o obj-$(CONFIG_HAVE_ITSS) += itss.o +obj-$(CONFIG_HAVE_P2SB) += p2sb.o ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index fb30984de3e..e4f785ce895 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -147,6 +147,15 @@ static int route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) return -ENOENT; } +static int itss_bind(struct udevice *dev) +{ + /* This is not set with of-platdata, so set it manually */ + if (CONFIG_IS_ENABLED(OF_PLATDATA)) + dev->driver_data = X86_IRQT_ITSS; + + return 0; +} + static int itss_ofdata_to_platdata(struct udevice *dev) { struct itss_priv *priv = dev_get_priv(dev); @@ -200,7 +209,7 @@ static const struct irq_ops itss_ops = { }; static const struct udevice_id itss_ids[] = { - { .compatible = "intel,itss"}, + { .compatible = "intel,itss", .data = X86_IRQT_ITSS }, { } }; @@ -209,6 +218,7 @@ U_BOOT_DRIVER(itss_drv) = { .id = UCLASS_IRQ, .of_match = itss_ids, .ops = &itss_ops, + .bind = itss_bind, .ofdata_to_platdata = itss_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct itss_platdata), .priv_auto_alloc_size = sizeof(struct itss_priv), diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index b72f50a6274..b72f50a6274 100644 --- a/arch/x86/cpu/apollolake/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index ed9938f7f7f..bafa0310822 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -7,6 +7,7 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <irq.h> #include <malloc.h> #include <asm/io.h> #include <asm/irq.h> @@ -351,7 +352,7 @@ int irq_router_probe(struct udevice *dev) } static const struct udevice_id irq_router_ids[] = { - { .compatible = "intel,irq-router" }, + { .compatible = "intel,irq-router", .data = X86_IRQT_BASE }, { } }; diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index a1820fa1870..44a4619a669 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -20,6 +20,7 @@ #include <asm/arch-apollolake/gpio.h> #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> +#include <dt-bindings/clock/intel-clock.h> / { model = "Google Coral"; @@ -29,6 +30,14 @@ cros-ec0 = &cros_ec; fsp = &fsp_s; spi0 = &spi; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; }; config { @@ -39,6 +48,11 @@ stdout-path = &serial; }; + clk: clock { + compatible = "intel,apl-clk"; + #clock-cells = <1>; + }; + cpus { u-boot,dm-pre-reloc; #address-cells = <1>; @@ -75,6 +89,13 @@ }; + acpi_gpe: general-purpose-events { + reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>; + compatible = "intel,acpi-gpe"; + interrupt-controller; + #interrupt-cells = <2>; + }; + keyboard { intel,duplicate-por; }; @@ -243,6 +264,78 @@ }; }; + i2c_0: i2c2@16,0 { + compatible = "intel,apl-i2c"; + reg = <0x0200b010 0 0 0 0>; + clocks = <&clk CLK_I2C>; + i2c-scl-rising-time-ns = <104>; + i2c-scl-falling-time-ns = <52>; + }; + + i2c_1: i2c2@16,1 { + compatible = "intel,apl-i2c"; + reg = <0x0200b110 0 0 0 0>; + clocks = <&clk CLK_I2C>; + status = "disabled"; + }; + + i2c_2: i2c2@16,2 { + compatible = "intel,apl-i2c"; + reg = <0x0200b210 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&clk CLK_I2C>; + i2c-scl-rising-time-ns = <57>; + i2c-scl-falling-time-ns = <28>; + tpm@50 { + reg = <0x50>; + compatible = "google,cr50"; + u-boot,i2c-offset-len = <0>; + ready-gpio = <&gpio_n 28 GPIO_ACTIVE_LOW>; + interrupts-extended = <&acpi_gpe 0x3c 0>; + }; + }; + + i2c_3: i2c2@16,3 { + compatible = "intel,apl-i2c"; + reg = <0x0200b110 0 0 0 0>; + clocks = <&clk CLK_I2C>; + i2c-scl-rising-time-ns = <76>; + i2c-scl-falling-time-ns = <164>; + }; + + i2c_4: i2c2@17,0 { + compatible = "intel,apl-i2c"; + reg = <0x0200b110 0 0 0 0>; + clocks = <&clk CLK_I2C>; + i2c-sda-hold-time-ns = <350>; + i2c-scl-rising-time-ns = <114>; + i2c-scl-falling-time-ns = <164>; + }; + + i2c_5: i2c2@17,1 { + compatible = "intel,apl-i2c"; + reg = <0x0200b110 0 0 0 0>; + clocks = <&clk CLK_I2C>; + i2c-scl-rising-time-ns = <76>; + i2c-scl-falling-time-ns = <164>; + }; + + i2c_6: i2c2@17,2 { + compatible = "intel,apl-i2c"; + reg = <0x0200b110 0 0 0 0>; + clocks = <&clk CLK_I2C>; + status = "disabled"; + }; + + i2c_7: i2c2@17,3 { + compatible = "intel,apl-i2c"; + reg = <0x0200b110 0 0 0 0>; + clocks = <&clk CLK_I2C>; + status = "disabled"; + }; + serial: serial@18,2 { reg = <0x0200c210 0 0 0 0>; u-boot,dm-pre-reloc; |