diff options
Diffstat (limited to 'arch')
247 files changed, 6272 insertions, 9012 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0118e22541..99264a64780 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -12,7 +12,7 @@ config ARM64 config ARM64_CRC32 bool "Enable support for CRC32 instruction" - depends on ARM64 + depends on ARM64 && CC_IS_GCC default y help ARMv8 implements dedicated crc32 instruction for crc32 calculation. @@ -357,7 +357,7 @@ config SYS_ARM_ARCH choice prompt "Select the ARM data write cache policy" - default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1 + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1 default SYS_ARM_CACHE_WRITEBACK config SYS_ARM_CACHE_WRITEBACK @@ -578,6 +578,16 @@ config ARCH_DAVINCI help Support for TI's DaVinci platform. +config ARCH_HISTB + bool "Hisilicon HiSTB SoCs" + select DM + select DM_SERIAL + select OF_CONTROL + select PL01X_SERIAL + imply CMD_DM + help + Support for HiSTB SoCs. + config ARCH_KIRKWOOD bool "Marvell Kirkwood" select ARCH_MISC_INIT @@ -671,6 +681,25 @@ config TARGET_BCMCYGNUS imply HASH_VERIFY imply NETDEVICES +config TARGET_BCMNS + bool "Support Broadcom Northstar" + select CPU_V7A + select DM + select DM_GPIO + select DM_SERIAL + select OF_CONTROL + select TIMER + select SYS_NS16550 + select ARM_GLOBAL_TIMER + imply SYS_THUMB_BUILD + imply MTD_RAW_NAND + imply NAND_BRCMNAND + imply NAND_BRCMNAND_IPROC + help + Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit + ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094, + BCM5301x etc. + config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 @@ -1956,8 +1985,7 @@ config ARCH_ROCKCHIP imply ADC imply CMD_DM imply DEBUG_UART_BOARD_INIT - imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399 - imply BOOTSTD_DEFAULTS if !DISTRO_DEFAULTS + imply BOOTSTD_DEFAULTS imply FAT_WRITE imply SARADC_ROCKCHIP imply SPL_SYSRESET @@ -2044,7 +2072,6 @@ config TARGET_XENGUEST_ARM64 select OF_CONTROL select LINUX_KERNEL_IMAGE_HEADER select XEN_SERIAL - select SSCANF imply OF_HAS_PRIOR_STAGE config ARCH_GXP @@ -2157,6 +2184,8 @@ source "arch/arm/mach-hpe/gxp/Kconfig" source "arch/arm/mach-highbank/Kconfig" +source "arch/arm/mach-histb/Kconfig" + source "arch/arm/mach-integrator/Kconfig" source "arch/arm/mach-ipq40xx/Kconfig" @@ -2268,6 +2297,7 @@ source "board/Marvell/octeontx2/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" +source "board/broadcom/bcmns/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/eets/pdu001/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac602aed9c9..5ebe0619d39 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -61,6 +61,7 @@ machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_GXP) += hpe machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_HISTB) += histb machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone diff --git a/arch/arm/config.mk b/arch/arm/config.mk index bf781f10262..5530d02b66c 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -3,7 +3,13 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \ +ifeq ($(CONFIG_ARM64),y) +FIXED_REG := -ffixed-x18 +else +FIXED_REG := -ffixed-r9 +endif + +CFLAGS_NON_EFI := -fno-pic $(FIXED_REG) -ffunction-sections -fdata-sections \ -fstack-protector-strong CFLAGS_EFI := -fpic -fshort-wchar @@ -15,7 +21,7 @@ ifneq ($(LTO_ENABLE),y) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections endif -PLATFORM_RELFLAGS += -fno-common -ffixed-r9 +PLATFORM_RELFLAGS += -fno-common $(FIXED_REG) PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ $(call cc-option,-mgeneral-regs-only) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7d7aac021e2..69e281b086a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -134,8 +134,8 @@ ENTRY(c_runtime_cpu_setup) */ #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb #endif bx lr @@ -188,8 +188,8 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb /* * disable MMU stuff and caches diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 697334086fd..cb1131a0480 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -93,10 +93,16 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) if (el == 1) { tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; + if (gd->arch.has_hafdbs) + tcr |= TCR_EL1_HA | TCR_EL1_HD; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); + if (gd->arch.has_hafdbs) + tcr |= TCR_EL2_HA | TCR_EL2_HD; } else { tcr = TCR_EL3_RSVD | (ips << 16); + if (gd->arch.has_hafdbs) + tcr |= TCR_EL3_HA | TCR_EL3_HD; } /* PTWs cacheable, inner/outer WBWA and inner shareable */ @@ -200,6 +206,9 @@ static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long), attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC)) continue; + if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM) + continue; + end = va + BIT(level2shift(level)) - 1; /* No intersection with RAM? */ @@ -309,7 +318,7 @@ static void map_range(u64 virt, u64 phys, u64 size, int level, for (i = idx; size; i++) { u64 next_size, *next_table; - if (level >= 1 && + if (level >= gd->arch.first_block_level && size >= map_size && !(virt & (map_size - 1))) { if (level == 3) table[i] = phys | attrs | PTE_TYPE_PAGE; @@ -348,6 +357,12 @@ static void add_map(struct mm_region *map) if (va_bits < 39) level = 1; + if (!gd->arch.first_block_level) + gd->arch.first_block_level = 1; + + if (gd->arch.has_hafdbs) + attrs |= PTE_DBM | PTE_RDONLY; + map_range(map->virt, map->phys, map->size, level, (u64 *)gd->arch.tlb_addr, attrs); } @@ -361,7 +376,7 @@ static void count_range(u64 virt, u64 size, int level, int *cntp) for (i = idx; size; i++) { u64 next_size; - if (level >= 1 && + if (level >= gd->arch.first_block_level && size >= map_size && !(virt & (map_size - 1))) { virt += map_size; size -= map_size; @@ -399,7 +414,16 @@ static int count_ranges(void) __weak u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); - u64 size; + u64 size, mmfr1; + + asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1)); + if ((mmfr1 & 0xf) == 2) { + gd->arch.has_hafdbs = true; + gd->arch.first_block_level = 2; + } else { + gd->arch.has_hafdbs = false; + gd->arch.first_block_level = 1; + } /* Account for all page tables we would need to cover our memory map */ size = one_pt * count_ranges(); diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk index ca06ed3d4f9..4d74b2a533e 100644 --- a/arch/arm/cpu/armv8/config.mk +++ b/arch/arm/cpu/armv8/config.mk @@ -2,7 +2,6 @@ # # (C) Copyright 2002 # Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -PLATFORM_RELFLAGS += -fno-common -ffixed-x18 PLATFORM_RELFLAGS += $(call cc-option,-mbranch-protection=none) PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4f91db49eeb..22ce6992165 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -387,6 +387,10 @@ void fdt_fixup_remove_jr(void *blob) u64 jr_offset, used_jr; fdt32_t *reg; + /* Return if crypto node not found */ + if (crypto_node < 0) + return; + used_jr = sec_firmware_used_jobring_offset(); fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3385948d22c..935b2f1517f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -961,6 +961,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ imx8qm-cgtqmx8.dtb \ + imx8qm-dmsse20-a1.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ @@ -1142,9 +1143,6 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \ omap4-sdp.dtb \ omap4-sdp-es23plus.dtb -dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \ - omap5-uevm.dtb - dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ at91-sama7g5ek.dtb @@ -1200,6 +1198,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2837-rpi-cm3-io3.dtb \ bcm2711-rpi-4-b.dtb +dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb + dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb @@ -1308,6 +1308,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7981-rfb.dtb \ mt7981-emmc-rfb.dtb \ mt7981-sd-rfb.dtb \ + mt7986a-bpi-r3-sd.dtb \ + mt7986a-bpi-r3-emmc.dtb \ mt7986a-rfb.dtb \ mt7986b-rfb.dtb \ mt7986a-sd-rfb.dtb \ diff --git a/arch/arm/dts/am335x-base0033.dts b/arch/arm/dts/am335x-base0033.dts index 29782be0760..89c00ce42c2 100644 --- a/arch/arm/dts/am335x-base0033.dts +++ b/arch/arm/dts/am335x-base0033.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION * * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "am335x-igep0033.dtsi" @@ -46,39 +43,39 @@ &am33xx_pinmux { nxp_hdmi_pins: pinmux_nxp_hdmi_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ >; }; leds_base_pins: pinmux_leds_base_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ >; }; }; diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 43fe03d096a..67dfcd8480c 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -371,7 +371,6 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; diff --git a/arch/arm/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/dts/am335x-boneblack-hdmi.dtsi index 7cfddada934..486f24deb87 100644 --- a/arch/arm/dts/am335x-boneblack-hdmi.dtsi +++ b/arch/arm/dts/am335x-boneblack-hdmi.dtsi @@ -85,8 +85,13 @@ audio-ports = < TDA998x_I2S 0x03>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { - hdmi_0: endpoint@0 { + reg = <0>; + + hdmi_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; diff --git a/arch/arm/dts/am335x-boneblack-wireless.dts b/arch/arm/dts/am335x-boneblack-wireless.dts index 8b2b24c8067..afa4fdc5dd2 100644 --- a/arch/arm/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/dts/am335x-boneblack-wireless.dts @@ -19,7 +19,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts index 9312197316f..b956e2f60fe 100644 --- a/arch/arm/dts/am335x-boneblack.dts +++ b/arch/arm/dts/am335x-boneblack.dts @@ -168,3 +168,7 @@ "NC", "NC"; }; + +&baseboard_eeprom { + vcc-supply = <&ldo4_reg>; +}; diff --git a/arch/arm/dts/am335x-boneblue.dts b/arch/arm/dts/am335x-boneblue.dts index 856fdf58b0f..f04f46d6e5e 100644 --- a/arch/arm/dts/am335x-boneblue.dts +++ b/arch/arm/dts/am335x-boneblue.dts @@ -107,7 +107,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; diff --git a/arch/arm/dts/am335x-bonegreen-wireless.dts b/arch/arm/dts/am335x-bonegreen-wireless.dts index 74db0fc3939..b363d032441 100644 --- a/arch/arm/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/dts/am335x-bonegreen-wireless.dts @@ -18,7 +18,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio0 26 0>; diff --git a/arch/arm/dts/am335x-chiliboard.dts b/arch/arm/dts/am335x-chiliboard.dts index 9c2a947aacf..129a02b597c 100644 --- a/arch/arm/dts/am335x-chiliboard.dts +++ b/arch/arm/dts/am335x-chiliboard.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ * Author: Rostislav Lisovy <lisovy@jablotron.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; #include "am335x-chilisom.dtsi" @@ -37,79 +34,79 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; usb1_drvvbus: usb1_drvvbus { pinctrl-single,pins = < - AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; sd_pins: pinmux_sd_card { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; led_gpio_pins: led_gpio_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ - AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ + AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ >; }; }; diff --git a/arch/arm/dts/am335x-chilisom.dtsi b/arch/arm/dts/am335x-chilisom.dtsi index 1b43ebd08b3..43b61e43ed1 100644 --- a/arch/arm/dts/am335x-chilisom.dtsi +++ b/arch/arm/dts/am335x-chilisom.dtsi @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ * Author: Rostislav Lisovy <lisovy@jablotron.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "am33xx.dtsi" #include <dt-bindings/interrupt-controller/irq.h> @@ -30,28 +27,28 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; nandflash_pins: nandflash_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0) + + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts index 2a2972f441f..6e799621678 100644 --- a/arch/arm/dts/am335x-evm.dts +++ b/arch/arm/dts/am335x-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -25,12 +22,16 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + chosen { + stdout-path = &uart0; + }; + + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -38,13 +39,13 @@ regulator-boot-on; }; - lis3_reg: fixedregulator@1 { + lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; - wlan_en_reg: fixedregulator@2 { + wlan_en_reg: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; @@ -78,18 +79,18 @@ 0x0201006c>; /* DOWN */ }; - gpio_keys: volume_keys@0 { + gpio_keys: volume-keys { compatible = "gpio-keys"; autorepeat; - switch@9 { + switch-9 { label = "volume-up"; linux,code = <115>; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; gpio-key,wakeup; }; - switch@10 { + switch-10 { label = "volume-down"; linux,code = <114>; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; @@ -158,206 +159,206 @@ matrix_keypad_s0: matrix_keypad_s0 { pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; volume_keys_s0: volume_keys_s0 { pinctrl-single,pins = < - 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ - 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ - 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; nandflash_pins_s0: nandflash_pins_s0 { pinctrl-single,pins = < - 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < - 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ - 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ - 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ - 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ - 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ - 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ >; }; wlan_pins: pinmux_wlan_pins { pinctrl-single,pins = < - 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ - 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ - 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < - 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - am335x_evm_audio_pins: am335x_evm_audio_pins { + mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < - 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; @@ -486,7 +487,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; @@ -534,7 +535,7 @@ #size-cells = <1>; partition@0 { label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; + reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; @@ -578,19 +579,19 @@ #include "tps65910.dtsi" &mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&am335x_evm_audio_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; - status = "okay"; + status = "okay"; - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; }; &tps { diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts index b14bf2ff1b3..5d962252b7d 100644 --- a/arch/arm/dts/am335x-evmsk.dts +++ b/arch/arm/dts/am335x-evmsk.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* @@ -32,12 +29,12 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -45,13 +42,13 @@ regulator-boot-on; }; - lis3_reg: fixedregulator@1 { + lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; - wl12xx_vmmc: fixedregulator@2 { + wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; @@ -63,7 +60,7 @@ enable-active-high; }; - vtt_fixed: fixedregulator@3 { + vtt_fixed: fixedregulator3 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; @@ -80,26 +77,26 @@ compatible = "gpio-leds"; - led@1 { + led1 { label = "evmsk:green:usr0"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "evmsk:green:usr1"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "evmsk:green:mmc0"; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@4 { + led4 { label = "evmsk:green:heartbeat"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -107,36 +104,38 @@ }; }; - gpio_buttons: gpio_buttons@0 { + gpio_buttons: gpio_buttons0 { compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; - switch@1 { + switch1 { label = "button0"; linux,code = <0x100>; gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; }; - switch@2 { + switch2 { label = "button1"; linux,code = <0x101>; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; - switch@3 { + switch3 { label = "button2"; linux,code = <0x102>; gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; wakeup-source; }; - switch@4 { + switch4 { label = "button3"; linux,code = <0x103>; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; }; }; - backlight { + lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 58 61 66 75 90 125 170 255>; @@ -207,234 +206,234 @@ lcd_pins_default: lcd_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; lcd_pins_sleep: lcd_pins_sleep { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ >; }; gpio_keys_s0: gpio_keys_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; ecap2_pins: backlight_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; mcasp1_pins_sleep: mcasp1_pins_sleep { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ >; }; wl12xx_gpio: pinmux_wl12xx_gpio { pinctrl-single,pins = < - AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; }; }; @@ -531,7 +530,7 @@ &epwmss2 { status = "okay"; - ecap2: ecap@100 { + ecap2: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; @@ -722,7 +721,7 @@ }; &lcdc { - status = "okay"; + status = "okay"; }; &rtc { diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts index 067c402885e..c2fd6101e32 100644 --- a/arch/arm/dts/am335x-guardian.dts +++ b/arch/arm/dts/am335x-guardian.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ /dts-v1/; @@ -29,10 +29,10 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - gpio_keys { - compatible = "gpio-keys"; + guardian_buttons: gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&guardian_button_pins>; + compatible = "gpio-keys"; select-button { label = "guardian-select-button"; @@ -49,10 +49,10 @@ }; }; - leds { - compatible = "gpio-leds"; + guardian_leds: gpio-leds { pinctrl-names = "default"; pinctrl-0 = <&guardian_led_pins>; + compatible = "gpio-leds"; life-led { label = "guardian:life-led"; @@ -98,7 +98,7 @@ }; - pwm7: dmtimer-pwm { + pwm7: pwm-7 { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer7>; pinctrl-names = "default"; diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts index 2a1b3a53e9b..a54272421cc 100644 --- a/arch/arm/dts/am335x-icev2.dts +++ b/arch/arm/dts/am335x-icev2.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ /* @@ -24,12 +21,12 @@ tick-timer = &timer2; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -37,7 +34,7 @@ regulator-boot-on; }; - vtt_fixed: fixedregulator@1 { + vtt_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; @@ -48,52 +45,51 @@ enable-active-high; }; - leds@0 { + leds-iio { compatible = "gpio-leds"; - - led@0 { + led-out0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@1 { + led-out1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led-out2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led-out3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@4 { + led-out4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led-out5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@6 { + led-out6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@7 { + led-out7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -101,44 +97,44 @@ }; /* Tricolor status LEDs */ - leds@1 { + leds1 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds>; - led@0 { + led0 { label = "status0:red:cpu0"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; - led@1 { + led1 { label = "status0:green:usr"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "status0:yellow:usr"; gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "status1:red:mmc0"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; - led@4 { + led4 { label = "status1:green:usr"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "status1:yellow:usr"; gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -149,31 +145,31 @@ &am33xx_pinmux { user_leds: user_leds { pinctrl-single,pins = < - AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ - AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ - AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ - AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ - AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ >; }; mmc0_pins_default: mmc0_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */ >; }; i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; @@ -188,71 +184,71 @@ uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1, RMII mode */ - AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */ - AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ /* Slave 2, RMII mode */ - AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */ - AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */ - AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */ - AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */ - AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */ - AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */ - AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */ - AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* Slave 2 reset value */ - AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7)) - AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; }; @@ -276,6 +272,56 @@ }; }; +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_default>; + + sn65hvs882@1 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + + reg = <1>; + spi-max-frequency = <1000000>; + spi-cpol; + }; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "u-boot"; + reg = <0x80000 0x100000>; + read-only; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + read-only; + }; + + partition@3 { + label = "misc"; + reg = <0x1A0000 0x660000>; + }; + }; +}; + #include "tps65910.dtsi" &tps { @@ -381,16 +427,17 @@ }; &gpio3 { - p4 { + pr1-mii-ctl-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_HIGH>; output-high; line-name = "PR1_MII_CTRL"; }; - p10 { + mux-mii-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; + /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ output-high; line-name = "MUX_MII_CTRL"; }; @@ -437,52 +484,3 @@ }; }; -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_default>; - - sn65hvs882@1 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - - reg = <1>; - spi-max-frequency = <1000000>; - spi-cpol; - }; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64", "jedec,spi-nor"; - spi-max-frequency = <80000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "u-boot"; - reg = <0x80000 0x100000>; - read-only; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - read-only; - }; - - partition@3 { - label = "misc"; - reg = <0x1A0000 0x660000>; - }; - }; -}; diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi index f102f6adad9..ad57c74fafc 100644 --- a/arch/arm/dts/am335x-igep0033.dtsi +++ b/arch/arm/dts/am335x-igep0033.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x * * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -57,41 +54,41 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ >; }; }; @@ -174,7 +171,7 @@ /* MTD partition table */ partition@0 { label = "SPL"; - reg = <0x00000000 0x000080000>; + reg = <0x00000000 0x00080000>; }; partition@1 { @@ -194,7 +191,7 @@ partition@4 { label = "File System"; - reg = <0x00780000 0x007880000>; + reg = <0x00780000 0x07880000>; }; }; }; diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi index 2b55b7d0f9c..7cf4e9fb39d 100644 --- a/arch/arm/dts/am335x-osd335x-common.dtsi +++ b/arch/arm/dts/am335x-osd335x-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Author: Robert Nelson <robertcnelson@gmail.com> */ @@ -36,8 +36,8 @@ &am33xx_pinmux { i2c0_pins: pinmux-i2c0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; diff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts index ae43d61f4e8..582032461e7 100644 --- a/arch/arm/dts/am335x-pdu001.dts +++ b/arch/arm/dts/am335x-pdu001.dts @@ -5,7 +5,7 @@ * * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ @@ -92,162 +92,162 @@ i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ >; }; spi1_pins: pinmux_spi1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ - AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ - AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */ - AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Port 1 (emac0) */ - AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */ - AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */ - AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */ - AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0) /* Port 2 (emac1) */ - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */ - AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */ - AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */ - AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ - AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ - AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ - AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */ - AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* mii2_txen.gpmc_a0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1) /* mii2_rxdv.gpmc_a1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* mii2_txd3.gpmc_a2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* mii2_txd2.gpmc_a3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* mii2_txd1.gpmc_a4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* mii2_txd0.gpmc_a5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1) /* mii2_txclk.gpmc_a6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1) /* mii2_rxclk.gpmc_a7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1) /* mii2_rxd3.gpmc_a8 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1) /* mii2_rxd2.gpmc_a9 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1) /* mii2_rxd1.gpmc_a10 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1) /* mii2_rxd0.gpmc_a11 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1) /* mii2_crs.gpmc_wait0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1) /* mii2_rxer.gpmc_wpn */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben1 */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; mmc1_pins: pinmux_mmc1_pins { /* eMMC */ pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; mmc2_pins: pinmux_mmc2_pins { /* SD cardcage */ pinctrl-single,pins = < - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ /* card change signal for frontpanel SD cardcage */ - AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; dcan0_pins: pinmux_dcan0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; }; @@ -353,7 +353,7 @@ }; }; - mcp79400: mcp79400@6f { + mcp79400: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi index 8d7c19e5e18..3f9a4eada39 100644 --- a/arch/arm/dts/am335x-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phycore-som.dtsi @@ -1,11 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Phytec Messtechnik GmbH * Author: Teresa Remmet <t.remmet@phytec.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "am33xx.dtsi" @@ -31,17 +27,13 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - regulators { - compatible = "simple-bus"; - - vcc5v: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; + vcc5v: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; }; }; @@ -58,22 +50,22 @@ &am33xx_pinmux { ethernet0_pins: pinmux_ethernet0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; mdio_pins: pinmux_mdio { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; @@ -105,8 +97,8 @@ &am33xx_pinmux { i2c0_pins: pinmux_i2c0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; }; @@ -145,20 +137,20 @@ &am33xx_pinmux { nandflash_pins: pinmux_nandflash { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; }; @@ -297,10 +289,10 @@ &am33xx_pinmux { spi0_pins: pinmux_spi0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; }; @@ -310,7 +302,7 @@ pinctrl-0 = <&spi0_pins>; status = "okay"; - serial_flash: m25p80@0 { + serial_flash: flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <48000000>; reg = <0x0>; diff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts index 62fe5cab9fa..b379e3a5570 100644 --- a/arch/arm/dts/am335x-pocketbeagle.dts +++ b/arch/arm/dts/am335x-pocketbeagle.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Author: Robert Nelson <robertcnelson@gmail.com> */ @@ -23,28 +23,28 @@ compatible = "gpio-leds"; - usr0 { + led-usr0 { label = "beaglebone:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; - usr1 { + led-usr1 { label = "beaglebone:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - usr2 { + led-usr2 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; - usr3 { + led-usr3 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -62,74 +62,74 @@ &am33xx_pinmux { i2c2_pins: pinmux-i2c2-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ >; }; ehrpwm0_pins: pinmux-ehrpwm0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ >; }; ehrpwm1_pins: pinmux-ehrpwm1-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ >; }; mmc0_pins: pinmux-mmc0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ >; }; spi0_pins: pinmux-spi0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; spi1_pins: pinmux-spi1-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ - AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ - AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ >; }; usr_leds_pins: pinmux-usr-leds-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ >; }; uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart4_pins: pinmux-uart4-pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ >; }; }; diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi index 645d221507b..a51d6aceb96 100644 --- a/arch/arm/dts/am335x-pxm2.dtsi +++ b/arch/arm/dts/am335x-pxm2.dtsi @@ -148,7 +148,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi index 86b3f074297..6fbf4ac739e 100644 --- a/arch/arm/dts/am335x-regor.dtsi +++ b/arch/arm/dts/am335x-regor.dtsi @@ -41,8 +41,8 @@ &am33xx_pinmux { user_leds_pins: pinmux_user_leds { pinctrl-single,pins = < - AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2_22 */ - AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ >; }; }; @@ -51,8 +51,8 @@ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; @@ -67,20 +67,20 @@ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ >; }; }; @@ -112,15 +112,15 @@ user_gpios_pins: pinmux_user_gpios { pinctrl-single,pins = < /* DIGIN 1-4 */ - AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7) /* gpmc_ad11.gpio0_27 */ - AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ - AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ - AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7) /* gpmc_ad8.gpio0_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */ /* DIGOUT 1-4 */ - AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad15.gpio1_15 */ - AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad14.gpio1_14 */ - AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad13.gpio1_13 */ - AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */ >; }; }; @@ -129,13 +129,13 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; @@ -158,15 +158,15 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart2_pins: pinmux_uart2 { pinctrl-single,pins = < - AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ - AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; }; @@ -187,9 +187,9 @@ &am33xx_pinmux { uart1_rs485_pins: pinmux_uart1_rs485_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; }; diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts index cc06f5d23ad..7760b9709a8 100644 --- a/arch/arm/dts/am335x-rut.dts +++ b/arch/arm/dts/am335x-rut.dts @@ -174,7 +174,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts index 246a1a9b3e4..a2676d10c24 100644 --- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -23,7 +23,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - startup-delay-us= <100000>; + startup-delay-us = <100000>; }; }; diff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts index a41a0606b1a..b44b15961bd 100644 --- a/arch/arm/dts/am335x-shc.dts +++ b/arch/arm/dts/am335x-shc.dts @@ -36,10 +36,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - back_button { + back-button { label = "Back Button"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; linux,code = <KEY_BACK>; @@ -47,7 +47,7 @@ wakeup-source; }; - front_button { + front-button { label = "Front Button"; gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; linux,code = <KEY_FRONT>; @@ -144,14 +144,14 @@ }; &gpio1 { - hmtc_rst { + hmtc-rst-hog { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; output-high; line-name = "homematic_reset"; }; - hmtc_prog { + hmtc-prog-hog { gpio-hog; gpios = <27 GPIO_ACTIVE_LOW>; output-high; @@ -160,14 +160,14 @@ }; &gpio3 { - zgb_rst { + zgb-rst-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_LOW>; output-low; line-name = "zigbee_reset"; }; - zgb_boot { + zgb-boot-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-high; @@ -383,193 +383,191 @@ clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ - AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; ehrpwm1_pins: pinmux_ehrpwm1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2) - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) >; }; mmc3_pins: pinmux_mmc3_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3) - AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart1_pins: pinmux_uart1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) - AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) >; }; user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) - AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) >; }; }; diff --git a/arch/arm/dts/am335x-sl50.dts b/arch/arm/dts/am335x-sl50.dts index ebb56bdaade..56c0943848a 100644 --- a/arch/arm/dts/am335x-sl50.dts +++ b/arch/arm/dts/am335x-sl50.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -34,25 +31,25 @@ pinctrl-0 = <&led_pins>; led0 { - label = "sl50:green:usr0"; + label = "sl50:red:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "off"; }; led1 { - label = "sl50:red:usr1"; + label = "sl50:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; led2 { - label = "sl50:green:usr2"; + label = "sl50:red:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; led3 { - label = "sl50:red:usr3"; + label = "sl50:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; @@ -78,7 +75,7 @@ #size-cells = <0>; /* audio external oscillator */ - tlv320aic3x_mclk: oscillator@0 { + audio_mclk_fixed: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; /* 24.576MHz */ @@ -91,7 +88,7 @@ ti,audio-codec = <&audio_codec>; ti,mcasp-controller = <&mcasp0>; - clocks = <&tlv320aic3x_mclk>; + clocks = <&audio_mclk_fixed>; clock-names = "mclk"; ti,audio-routing = @@ -122,126 +119,126 @@ led_pins: pinmux_led_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart4_pins: pinmux_uart4_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ - AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; @@ -264,11 +261,11 @@ spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MISO - spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CLK - spi0_clk.spi0_clk */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ >; }; @@ -276,13 +273,13 @@ pinctrl-single,pins = < AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ - AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ - AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ /* PDI Bus - Battery system */ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ - AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ >; }; }; @@ -433,7 +430,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - flash: n25q032@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q032"; diff --git a/arch/arm/dts/am335x-wega-rdk.dts b/arch/arm/dts/am335x-wega-rdk.dts index fe50f3041a1..2e04f6df825 100644 --- a/arch/arm/dts/am335x-wega-rdk.dts +++ b/arch/arm/dts/am335x-wega-rdk.dts @@ -1,11 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Phytec Messtechnik GmbH * Author: Teresa Remmet <t.remmet@phytec.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; diff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi index f3e045dfc4b..408034df011 100644 --- a/arch/arm/dts/am335x-wega.dtsi +++ b/arch/arm/dts/am335x-wega.dtsi @@ -1,11 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Phytec Messtechnik GmbH * Author: Teresa Remmet <t.remmet@phytec.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ / { @@ -16,16 +12,12 @@ compatible = "ti,da830-evm-audio"; }; - regulators { - compatible = "simple-bus"; - - vcc3v3: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; }; }; @@ -33,11 +25,11 @@ &am33xx_pinmux { mcasp0_pins: pinmux_mcasp0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ - AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ - AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ - AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; @@ -85,8 +77,8 @@ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ >; }; }; @@ -101,20 +93,20 @@ &am33xx_pinmux { ethernet1_pins: pinmux_ethernet1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ - AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ - AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */ >; }; }; @@ -142,13 +134,13 @@ &am33xx_pinmux { mmc1_pins: pinmux_mmc1 { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ >; }; }; @@ -172,17 +164,17 @@ &am33xx_pinmux { uart0_pins: pinmux_uart0 { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ - AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi index 44b6268ae32..2984b2f9f3c 100644 --- a/arch/arm/dts/am33xx-clocks.dtsi +++ b/arch/arm/dts/am33xx-clocks.dtsi @@ -1,14 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM33xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { + sys_clkin_ck: clock-sys-clkin-22@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; @@ -16,7 +13,7 @@ reg = <0x0040>; }; - adc_tsc_fck: adc_tsc_fck { + adc_tsc_fck: clock-adc-tsc-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -24,7 +21,7 @@ clock-div = <1>; }; - dcan0_fck: dcan0_fck { + dcan0_fck: clock-dcan0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -32,7 +29,7 @@ clock-div = <1>; }; - dcan1_fck: dcan1_fck { + dcan1_fck: clock-dcan1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -40,7 +37,7 @@ clock-div = <1>; }; - mcasp0_fck: mcasp0_fck { + mcasp0_fck: clock-mcasp0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -48,7 +45,7 @@ clock-div = <1>; }; - mcasp1_fck: mcasp1_fck { + mcasp1_fck: clock-mcasp1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -56,7 +53,7 @@ clock-div = <1>; }; - smartreflex0_fck: smartreflex0_fck { + smartreflex0_fck: clock-smartreflex0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -64,7 +61,7 @@ clock-div = <1>; }; - smartreflex1_fck: smartreflex1_fck { + smartreflex1_fck: clock-smartreflex1-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -72,7 +69,7 @@ clock-div = <1>; }; - sha0_fck: sha0_fck { + sha0_fck: clock-sha0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -80,7 +77,7 @@ clock-div = <1>; }; - aes0_fck: aes0_fck { + aes0_fck: clock-aes0-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -88,7 +85,7 @@ clock-div = <1>; }; - rng_fck: rng_fck { + rng_fck: clock-rng-fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin_ck>; @@ -121,62 +118,62 @@ }; }; &prcm_clocks { - clk_32768_ck: clk_32768_ck { + clk_32768_ck: clock-clk-32768 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; - clk_rc32k_ck: clk_rc32k_ck { + clk_rc32k_ck: clock-clk-rc32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; - virt_24000000_ck: virt_24000000_ck { + virt_24000000_ck: clock-virt-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - virt_25000000_ck: virt_25000000_ck { + virt_25000000_ck: clock-virt-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; - tclkin_ck: tclkin_ck { + tclkin_ck: clock-tclkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck@490 { + dpll_core_ck: clock@490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,am3-dpll-x2-clock"; clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck@480 { + dpll_core_m4_ck: clock-dpll-core-m4@480 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -185,7 +182,7 @@ ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck@484 { + dpll_core_m5_ck: clock-dpll-core-m5@484 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -194,7 +191,7 @@ ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck@4d8 { + dpll_core_m6_ck: clock-dpll-core-m6@4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -203,14 +200,14 @@ ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck@488 { + dpll_mpu_ck: clock@488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -219,14 +216,14 @@ ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck@494 { + dpll_ddr_ck: clock@494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; @@ -235,7 +232,7 @@ ti,index-starts-at-one; }; - dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { + dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_ddr_m2_ck>; @@ -243,14 +240,14 @@ clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck@498 { + dpll_disp_ck: clock@498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { + dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>; @@ -260,14 +257,14 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck@48c { + dpll_per_ck: clock@48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; - dpll_per_m2_ck: dpll_per_m2_ck@4ac { + dpll_per_m2_ck: clock-dpll-per-m2@4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -276,7 +273,7 @@ ti,index-starts-at-one; }; - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; @@ -284,7 +281,7 @@ clock-div = <4>; }; - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; @@ -292,7 +289,7 @@ clock-div = <4>; }; - clk_24mhz: clk_24mhz { + clk_24mhz: clock-clk-24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; @@ -300,7 +297,7 @@ clock-div = <8>; }; - clkdiv32k_ck: clkdiv32k_ck { + clkdiv32k_ck: clock-clkdiv32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&clk_24mhz>; @@ -308,7 +305,7 @@ clock-div = <732>; }; - l3_gclk: l3_gclk { + l3_gclk: clock-l3-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; @@ -316,14 +313,14 @@ clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk@530 { + pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck@914 { + mmu_fck: clock-mmu-fck-1@914 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_ck>; @@ -331,56 +328,56 @@ reg = <0x0914>; }; - timer1_fck: timer1_fck@528 { + timer1_fck: clock-timer1-fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck@508 { + timer2_fck: clock-timer2-fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; - timer3_fck: timer3_fck@50c { + timer3_fck: clock-timer3-fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; - timer4_fck: timer4_fck@510 { + timer4_fck: clock-timer4-fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; - timer5_fck: timer5_fck@518 { + timer5_fck: clock-timer5-fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; - timer6_fck: timer6_fck@51c { + timer6_fck: clock-timer6-fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; - timer7_fck: timer7_fck@504 { + timer7_fck: clock-timer7-fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck@47c { + usbotg_fck: clock-usbotg-fck-8@47c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_ck>; @@ -388,7 +385,7 @@ reg = <0x047c>; }; - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; @@ -396,7 +393,7 @@ clock-div = <2>; }; - ieee5000_fck: ieee5000_fck@e4 { + ieee5000_fck: clock-ieee5000-fck-1@e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_div2_ck>; @@ -404,14 +401,14 @@ reg = <0x00e4>; }; - wdt1_fck: wdt1_fck@538 { + wdt1_fck: clock-wdt1-fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; - l4_rtc_gclk: l4_rtc_gclk { + l4_rtc_gclk: clock-l4-rtc-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; @@ -419,7 +416,7 @@ clock-div = <2>; }; - l4hs_gclk: l4hs_gclk { + l4hs_gclk: clock-l4hs-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; @@ -427,7 +424,7 @@ clock-div = <1>; }; - l3s_gclk: l3s_gclk { + l3s_gclk: clock-l3s-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_div2_ck>; @@ -435,7 +432,7 @@ clock-div = <1>; }; - l4fw_gclk: l4fw_gclk { + l4fw_gclk: clock-l4fw-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_div2_ck>; @@ -443,7 +440,7 @@ clock-div = <1>; }; - l4ls_gclk: l4ls_gclk { + l4ls_gclk: clock-l4ls-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_div2_ck>; @@ -451,7 +448,7 @@ clock-div = <1>; }; - sysclk_div_ck: sysclk_div_ck { + sysclk_div_ck: clock-sysclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m4_ck>; @@ -459,7 +456,7 @@ clock-div = <1>; }; - cpsw_125mhz_gclk: cpsw_125mhz_gclk { + cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m5_ck>; @@ -467,21 +464,21 @@ clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { + cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { + gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; - lcd_gclk: lcd_gclk@534 { + lcd_gclk: clock-lcd-gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; @@ -489,7 +486,7 @@ ti,set-rate-parent; }; - mmc_clk: mmc_clk { + mmc_clk: clock-mmc { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; @@ -539,138 +536,138 @@ }; &prcm { - per_cm: per-cm@0 { + per_cm: clock@0 { compatible = "ti,omap4-cm"; reg = <0x0 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x400>; - l4ls_clkctrl: l4ls-clkctrl@38 { + l4ls_clkctrl: clock@38 { compatible = "ti,clkctrl"; reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; #clock-cells = <2>; }; - l3s_clkctrl: l3s-clkctrl@1c { + l3s_clkctrl: clock@1c { compatible = "ti,clkctrl"; reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; #clock-cells = <2>; }; - l3_clkctrl: l3-clkctrl@24 { + l3_clkctrl: clock@24 { compatible = "ti,clkctrl"; reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; #clock-cells = <2>; }; - l4hs_clkctrl: l4hs-clkctrl@120 { + l4hs_clkctrl: clock@120 { compatible = "ti,clkctrl"; reg = <0x120 0x4>; #clock-cells = <2>; }; - pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { + pruss_ocp_clkctrl: clock@e8 { compatible = "ti,clkctrl"; reg = <0xe8 0x4>; #clock-cells = <2>; }; - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { + cpsw_125mhz_clkctrl: clock@0 { compatible = "ti,clkctrl"; reg = <0x0 0x18>; #clock-cells = <2>; }; - lcdc_clkctrl: lcdc-clkctrl@18 { + lcdc_clkctrl: clock@18 { compatible = "ti,clkctrl"; reg = <0x18 0x4>; #clock-cells = <2>; }; - clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { + clk_24mhz_clkctrl: clock@14c { compatible = "ti,clkctrl"; reg = <0x14c 0x4>; #clock-cells = <2>; }; }; - wkup_cm: wkup-cm@400 { + wkup_cm: clock@400 { compatible = "ti,omap4-cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - l4_wkup_clkctrl: l4-wkup-clkctrl@0 { + l4_wkup_clkctrl: clock@0 { compatible = "ti,clkctrl"; reg = <0x0 0x10>, <0xb4 0x24>; #clock-cells = <2>; }; - l3_aon_clkctrl: l3-aon-clkctrl@14 { + l3_aon_clkctrl: clock@14 { compatible = "ti,clkctrl"; reg = <0x14 0x4>; #clock-cells = <2>; }; - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { + l4_wkup_aon_clkctrl: clock@b0 { compatible = "ti,clkctrl"; reg = <0xb0 0x4>; #clock-cells = <2>; }; }; - mpu_cm: mpu-cm@600 { + mpu_cm: clock@600 { compatible = "ti,omap4-cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - mpu_clkctrl: mpu-clkctrl@0 { + mpu_clkctrl: clock@0 { compatible = "ti,clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4-rtc-cm@800 { + l4_rtc_cm: clock@800 { compatible = "ti,omap4-cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; - l4_rtc_clkctrl: l4-rtc-clkctrl@0 { + l4_rtc_clkctrl: clock@0 { compatible = "ti,clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx-l3-cm@900 { + gfx_l3_cm: clock@900 { compatible = "ti,omap4-cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - gfx_l3_clkctrl: gfx-l3-clkctrl@0 { + gfx_l3_clkctrl: clock@0 { compatible = "ti,clkctrl"; reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_cefuse_cm: l4-cefuse-cm@a00 { + l4_cefuse_cm: clock@a00 { compatible = "ti,omap4-cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { + l4_cefuse_clkctrl: clock@0 { compatible = "ti,clkctrl"; reg = <0x0 0x24>; #clock-cells = <2>; diff --git a/arch/arm/dts/am33xx-l4.dtsi b/arch/arm/dts/am33xx-l4.dtsi index 5892612efa8..2264a1a80d0 100644 --- a/arch/arm/dts/am33xx-l4.dtsi +++ b/arch/arm/dts/am33xx-l4.dtsi @@ -1327,7 +1327,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; @@ -1621,7 +1621,7 @@ }; }; - target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ + target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0xae000 0x4>, <0xae010 0x4>, @@ -1798,7 +1798,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; @@ -1859,7 +1859,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; @@ -1920,7 +1920,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index 5871344edbf..3c7e0385f36 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM33XX SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/bus/ti-sysc.h> @@ -175,7 +172,7 @@ * for the moment, just use a fake OCP bus entry to represent * the whole bus hierarchy. */ - ocp { + ocp: ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -325,11 +322,11 @@ ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { - compatible = "ti,am335-sdhci"; - ti,needs-special-reset; - interrupts = <29>; - reg = <0x0 0x1000>; - status = "disabled"; + compatible = "ti,am335-sdhci"; + ti,needs-special-reset; + interrupts = <29>; + reg = <0x0 0x1000>; + status = "disabled"; }; }; diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi index 340e68178ce..75ad42179ae 100644 --- a/arch/arm/dts/am3517-evm-ui.dtsi +++ b/arch/arm/dts/am3517-evm-ui.dtsi @@ -70,61 +70,61 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - record { + key-record { label = "Record"; - linux,code = <KEY_RECORD>; + /* linux,code = <BTN_0>; */ gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; }; - play { + key-play { label = "Play"; linux,code = <KEY_PLAY>; gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; }; - Stop { + key-stop { label = "Stop"; linux,code = <KEY_STOP>; gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; }; - fwd { + key-fwd { label = "FWD"; linux,code = <KEY_FASTFORWARD>; gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; }; - rwd { + key-rwd { label = "RWD"; linux,code = <KEY_REWIND>; gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; }; - shift { + key-shift { label = "Shift"; linux,code = <KEY_LEFTSHIFT>; gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; }; - Mode { + key-mode { label = "Mode"; linux,code = <BTN_MODE>; gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; }; - Menu { + key-menu { label = "Menu"; linux,code = <KEY_MENU>; gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; }; - Up { + key-up { label = "Up"; linux,code = <KEY_UP>; gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; }; - Down { + key-down { label = "Down"; linux,code = <KEY_DOWN>; gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; @@ -137,14 +137,14 @@ tlv320aic23_1: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; tlv320aic23_2: codec@1b { compatible = "ti,tlv320aic23"; reg = <0x1b>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; }; @@ -154,7 +154,7 @@ tlv320aic23_3: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts index a01f9cf047d..d21bb2ccd0f 100644 --- a/arch/arm/dts/am3517-evm.dts +++ b/arch/arm/dts/am3517-evm.dts @@ -26,66 +26,66 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vmmc_fixed: vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + vmmc_fixed: vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; gpio-keys { compatible = "gpio-keys-polled"; poll-interval = <100>; - user_pb { + button-user { label = "User Push Button"; linux,code = <BTN_0>; gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; }; - user_sw_1 { + switch-1 { label = "User Switch 1"; linux,code = <BTN_1>; gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; }; - user_sw_2 { + switch-2 { label = "User Switch 2"; linux,code = <BTN_2>; gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; }; - user_sw_3 { + switch-3 { label = "User Switch 3"; linux,code = <BTN_3>; gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; }; - user_sw_4 { + switch-4 { label = "User Switch 4"; linux,code = <BTN_4>; gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; }; - user_sw_5 { + switch-5 { label = "User Switch 5"; linux,code = <BTN_5>; gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; }; - user_sw_6 { + switch-6 { label = "User Switch 6"; linux,code = <BTN_6>; gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; }; - user_sw_7 { + switch-7 { label = "User Switch 7"; linux,code = <BTN_7>; gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; }; - user_sw_8 { + switch-8 { label = "User Switch 8"; linux,code = <BTN_8>; gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; @@ -150,7 +150,7 @@ enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ }; - pwm11: dmtimer-pwm@11 { + pwm11: pwm-11 { compatible = "ti,omap-dmtimer-pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm_pins>; @@ -176,7 +176,7 @@ }; &davinci_mdio { - status = "okay"; + status = "okay"; }; &dss { @@ -223,7 +223,7 @@ }; &mmc3 { - status = "disabled"; + status = "disabled"; }; &usbhshost { diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi index 23ea381d363..2633fae14b3 100644 --- a/arch/arm/dts/am3517.dtsi +++ b/arch/arm/dts/am3517.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for am3517 SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap3.dtsi" @@ -43,7 +40,7 @@ clock-names = "ick"; }; - davinci_mdio: ethernet@5c030000 { + davinci_mdio: mdio@5c030000 { compatible = "ti,davinci_mdio"; ti,hwmods = "davinci_mdio"; status = "disabled"; diff --git a/arch/arm/dts/am35xx-clocks.dtsi b/arch/arm/dts/am35xx-clocks.dtsi index 00dd1f091be..220d0a52797 100644 --- a/arch/arm/dts/am35xx-clocks.dtsi +++ b/arch/arm/dts/am35xx-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &scm_clocks { emac_ick: emac_ick@32c { diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 6f60a32999a..42a0307559c 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM4372 SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts index 21f7691f493..bbd61f833dc 100644 --- a/arch/arm/dts/am437x-gp-evm.dts +++ b/arch/arm/dts/am437x-gp-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /* AM437x GP EVM */ @@ -138,139 +135,138 @@ i2c0_pins: i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: i2c1_pins { pinctrl-single,pins = < - 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < - 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; pixcir_ts_pins: pixcir_ts_pins { pinctrl-single,pins = < - 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ + AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ - 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ + AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ + AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; nand_flash_x8: nand_flash_x8 { pinctrl-single,pins = < - 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */ - 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ - 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; dss_pins: dss_pins { pinctrl-single,pins = < - 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ - 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) - 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) - 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) - 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) - 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) - 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) - 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ - 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ - 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) - 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ - 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ - 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ - 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ - 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ >; }; @@ -278,140 +274,140 @@ lcd_pins: lcd_pins { pinctrl-single,pins = < /* GPIO 5_8 to select LCD / HDMI */ - 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) + AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; dcan0_default: dcan0_default_pins { pinctrl-single,pins = < - 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ - 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; dcan1_default: dcan1_default_pins { pinctrl-single,pins = < - 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ - 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ + AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ + AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ >; }; vpfe0_pins_default: vpfe0_pins_default { pinctrl-single,pins = < - 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ + AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ + AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ + AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ + AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ + AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ + AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ + AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ + AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ + AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ + AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ + AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ >; }; vpfe0_pins_sleep: vpfe0_pins_sleep { pinctrl-single,pins = < - 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ - 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ - 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ - 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ - 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ - 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ - 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ - 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ - 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ - 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ - 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ - 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ - 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ + AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ + AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ + AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ + AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ + AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ + AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ + AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ + AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ + AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ + AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ + AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ + AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ + AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ >; }; vpfe1_pins_default: vpfe1_pins_default { pinctrl-single,pins = < - 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ - 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ - 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ - 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ - 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ - 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ - 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ - 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ - 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ - 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ - 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ - 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ - 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ + AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ + AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ + AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ + AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ + AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ >; }; vpfe1_pins_sleep: vpfe1_pins_sleep { pinctrl-single,pins = < - 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ - 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ - 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ - 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ - 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ - 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ - 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ - 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ - 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ - 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ - 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ - 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ - 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ + AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ + AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ + AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ + AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ + AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ + AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ + AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ + AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ + AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ + AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ + AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ + AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ + AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ >; }; mmc3_pins_default: pinmux_mmc3_pins_default { pinctrl-single,pins = < - 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ - 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ - 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ - 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ - 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ + AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ + AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ + AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ + AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ >; }; mmc3_pins_sleep: pinmux_mmc3_pins_sleep { pinctrl-single,pins = < - 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ - 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ - 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ - 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ - 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ + AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ + AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ + AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ + AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ + AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ + AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ >; }; wlan_pins_default: pinmux_wlan_pins_default { pinctrl-single,pins = < - 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ >; }; wlan_pins_sleep: pinmux_wlan_pins_sleep { pinctrl-single,pins = < - 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ - 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ - 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ + AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ + AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ >; }; uart3_pins: uart3_pins { pinctrl-single,pins = < - 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ - 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ - 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ - 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ + AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ + AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ + AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ + AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ >; }; }; diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts index 8f6824c198f..2c94c874740 100644 --- a/arch/arm/dts/am437x-idk-evm.dts +++ b/arch/arm/dts/am437x-idk-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts index 66a3bd1dfa1..f1bb009055a 100644 --- a/arch/arm/dts/am437x-sk-evm.dts +++ b/arch/arm/dts/am437x-sk-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ */ /* AM437x SK EVM */ @@ -140,250 +137,250 @@ &am43xx_pinmux { matrix_keypad_pins: matrix_keypad_pins { pinctrl-single,pins = < - 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ - 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ - 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ - 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ + AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ + AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ + AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ + AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ >; }; leds_pins: leds_pins { pinctrl-single,pins = < - 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ - 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ - 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ - 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ + AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ + AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ + AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ + AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ >; }; i2c0_pins: i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c1_pins: i2c1_pins { pinctrl-single,pins = < - 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ - 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ + AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ + AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ - 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ - 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ - 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ - 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ - 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ - 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; ecap0_pins: backlight_pins { pinctrl-single,pins = < - 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ >; }; edt_ft5306_ts_pins: edt_ft5306_ts_pins { pinctrl-single,pins = < - 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ + AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ >; }; vpfe0_pins_default: vpfe0_pins_default { pinctrl-single,pins = < - 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ - 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ - 0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ - 0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ - 0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ - 0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ - 0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ - 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ - 0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ - 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ - 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ - 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ - 0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ - 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ - 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ + AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ + AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ + AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ + AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ + AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ + AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ + AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ + AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ + AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ + AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ + AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ + AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ + AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ >; }; vpfe0_pins_sleep: vpfe0_pins_sleep { pinctrl-single,pins = < - 0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) - 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ - 0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - 0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - 0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - 0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ - 0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ - 0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ - 0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - 0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - 0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - 0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ - 0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ /* Slave 2 */ - 0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - 0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - 0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - 0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - 0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - 0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - 0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - 0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ - 0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - 0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - 0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - 0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ + AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) /* Slave 2 reset value */ - 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; dss_pins: dss_pins { pinctrl-single,pins = < - 0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ - 0x024 (PIN_OUTPUT | MUX_MODE1) - 0x028 (PIN_OUTPUT | MUX_MODE1) - 0x02c (PIN_OUTPUT | MUX_MODE1) - 0x030 (PIN_OUTPUT | MUX_MODE1) - 0x034 (PIN_OUTPUT | MUX_MODE1) - 0x038 (PIN_OUTPUT | MUX_MODE1) - 0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ - 0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ - 0x0a4 (PIN_OUTPUT | MUX_MODE0) - 0x0a8 (PIN_OUTPUT | MUX_MODE0) - 0x0ac (PIN_OUTPUT | MUX_MODE0) - 0x0b0 (PIN_OUTPUT | MUX_MODE0) - 0x0b4 (PIN_OUTPUT | MUX_MODE0) - 0x0b8 (PIN_OUTPUT | MUX_MODE0) - 0x0bc (PIN_OUTPUT | MUX_MODE0) - 0x0c0 (PIN_OUTPUT | MUX_MODE0) - 0x0c4 (PIN_OUTPUT | MUX_MODE0) - 0x0c8 (PIN_OUTPUT | MUX_MODE0) - 0x0cc (PIN_OUTPUT | MUX_MODE0) - 0x0d0 (PIN_OUTPUT | MUX_MODE0) - 0x0d4 (PIN_OUTPUT | MUX_MODE0) - 0x0d8 (PIN_OUTPUT | MUX_MODE0) - 0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ - 0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ - 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ - 0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ - 0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ + AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ >; }; qspi_pins: qspi_pins { pinctrl-single,pins = < - 0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ - 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ - 0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ - 0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ - 0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ - 0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ >; }; mcasp1_pins: mcasp1_pins { pinctrl-single,pins = < - 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; lcd_pins: lcd_pins { pinctrl-single,pins = < - 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ + AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ >; }; usb1_pins: usb1_pins { pinctrl-single,pins = < - 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; usb2_pins: usb2_pins { pinctrl-single,pins = < - 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ + AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; }; diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts index b940bc6ccf0..90455a660e0 100644 --- a/arch/arm/dts/am43x-epos-evm.dts +++ b/arch/arm/dts/am43x-epos-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /* AM43x EPOS EVM */ diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi index b1127b5b91f..07ed769e182 100644 --- a/arch/arm/dts/am43xx-clocks.dtsi +++ b/arch/arm/dts/am43xx-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM43xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &scm_clocks { sys_clkin_ck: sys_clkin_ck { diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts index 798fbfe19d4..b3592b22a0c 100644 --- a/arch/arm/dts/am571x-idk.dts +++ b/arch/arm/dts/am571x-idk.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -77,17 +74,17 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts index 34293034e36..f772aefb8f3 100644 --- a/arch/arm/dts/am5729-beagleboneai.dts +++ b/arch/arm/dts/am5729-beagleboneai.dts @@ -4,6 +4,7 @@ */ /dts-v1/; + #include "dra74x.dtsi" #include "dra74x-mmc-iodelay.dtsi" #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/am572x-idk-common.dtsi b/arch/arm/dts/am572x-idk-common.dtsi index c6d858b3101..c7dc8445d68 100644 --- a/arch/arm/dts/am572x-idk-common.dtsi +++ b/arch/arm/dts/am572x-idk-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> @@ -81,20 +81,20 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts index 42e88c1bc08..ed9b91205b1 100644 --- a/arch/arm/dts/am572x-idk.dts +++ b/arch/arm/dts/am572x-idk.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/am574x-idk.dts b/arch/arm/dts/am574x-idk.dts index 0de73616b56..dd3f2ac36c0 100644 --- a/arch/arm/dts/am574x-idk.dts +++ b/arch/arm/dts/am574x-idk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi index 1912ea9a157..22d8d3d0d53 100644 --- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -571,20 +568,20 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/dts/am57xx-beagle-x15-revb1.dts index 34c69965821..9f65d362c6c 100644 --- a/arch/arm/dts/am57xx-beagle-x15-revb1.dts +++ b/arch/arm/dts/am57xx-beagle-x15-revb1.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" diff --git a/arch/arm/dts/am57xx-beagle-x15-revc.dts b/arch/arm/dts/am57xx-beagle-x15-revc.dts index ccd99160bbd..803c7f4ec90 100644 --- a/arch/arm/dts/am57xx-beagle-x15-revc.dts +++ b/arch/arm/dts/am57xx-beagle-x15-revc.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" diff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts index 8d9bdf10a7b..637369744d3 100644 --- a/arch/arm/dts/am57xx-beagle-x15.dts +++ b/arch/arm/dts/am57xx-beagle-x15.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi index d0ce469f918..b07aea0048d 100644 --- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi +++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi @@ -3,7 +3,6 @@ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ */ #include "omap5-u-boot.dtsi" -#include "dra7-ipu-common-early-boot.dtsi" / { xtal25mhz: xtal25mhz { diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi index 590fb14caf7..b83c9e9e6e1 100644 --- a/arch/arm/dts/am57xx-idk-common.dtsi +++ b/arch/arm/dts/am57xx-idk-common.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-industrial-grade.dtsi" @@ -440,7 +437,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1", "jedec,spi-nor"; spi-max-frequency = <76800000>; reg = <0>; @@ -456,7 +453,7 @@ */ partition@0 { label = "QSPI.SPL"; - reg = <0x00000000 0x000040000>; + reg = <0x00000000 0x00040000>; }; partition@1 { label = "QSPI.u-boot"; diff --git a/arch/arm/dts/bcm5301x.dtsi b/arch/arm/dts/bcm5301x.dtsi new file mode 100644 index 00000000000..5fc1b847f4a --- /dev/null +++ b/arch/arm/dts/bcm5301x.dtsi @@ -0,0 +1,581 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs + * + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include <dt-bindings/clock/bcm-nsp.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + chipcommon-a-bus@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550"; + reg = <0x0300 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550"; + reg = <0x0400 0x100>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1>; + status = "disabled"; + }; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + a9pll: arm_clk@0 { + #clock-cells = <0>; + compatible = "brcm,nsp-armpll"; + clocks = <&osc>; + reg = <0x00000 0x1000>; + }; + + scu@20000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x20000 0x100>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; + clocks = <&periph_clk>; + }; + + timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>; + clocks = <&periph_clk>; + }; + + watchdog@20620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x20620 0x20>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; + cache-level = <2>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&a9pll>; + clock-div = <2>; + clock-mult = <1>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; + }; + + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + ehci: usb@21000 { + #usb-cells = <0>; + + compatible = "generic-ehci"; + reg = <0x00021000 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@22000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + }; + + usb3: usb3@23000 { + reg = <0x00023000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + xhci: usb@23000 { + #usb-cells = <0>; + + compatible = "generic-xhci"; + reg = <0x00023000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy>; + phy-names = "usb"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; + }; + + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; + + gmac1: ethernet@25000 { + reg = <0x25000 0x800>; + }; + + gmac2: ethernet@26000 { + reg = <0x26000 0x800>; + }; + + gmac3: ethernet@27000 { + reg = <0x27000 0x800>; + }; + }; + + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; + }; + + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c0: i2c@18009000 { + compatible = "brcm,iproc-i2c"; + reg = <0x18009000 0x50>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + lcpll0: clock-controller@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: clock-controller@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + + pinctrl: pinctrl@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + groups = "spi_grp"; + function = "spi"; + }; + + pinmux_i2c: i2c-pins { + groups = "i2c_grp"; + function = "i2c"; + }; + + pinmux_pwm: pwm-pins { + groups = "pwm0_grp", "pwm1_grp", + "pwm2_grp", "pwm3_grp"; + function = "pwm"; + }; + + pinmux_uart1: uart1-pins { + groups = "uart1_grp"; + function = "uart1"; + }; + }; + + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + }; + }; + + srab: ethernet-switch@18007000 { + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; + + nand_controller: nand-controller@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + spi@18029200 { + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; + reg = <0x18029200 0x184>, + <0x18029000 0x124>, + <0x1811b408 0x004>, + <0x180293a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overread"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "disabled"; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi index 4e46826f883..533dfdf8e1c 100644 --- a/arch/arm/dts/corstone1000.dtsi +++ b/arch/arm/dts/corstone1000.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 or MIT /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> * Copyright (c) 2022, Linaro Limited. All rights reserved. * */ @@ -38,6 +38,13 @@ reg = <0x88200000 0x77e00000>; }; + nvmxip-qspi@08000000 { + compatible = "nvmxip,qspi"; + reg = <0x08000000 0x2000000>; + lba_shift = <9>; + lba = <65536>; + }; + gic: interrupt-controller@1c000000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts index b331cefd18e..378af9f3445 100644 --- a/arch/arm/dts/da850-evm.dts +++ b/arch/arm/dts/da850-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree for DA850 EVM board * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation, version 2. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; #include "da850.dtsi" @@ -55,15 +52,15 @@ enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; }; display-timings { @@ -268,7 +265,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p64"; diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts index db8ae566f33..9c8e9f0e220 100644 --- a/arch/arm/dts/da850-lcdk.dts +++ b/arch/arm/dts/da850-lcdk.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016 BayLibre, Inc. - * - * Licensed under GPLv2. */ /dts-v1/; #include "da850.dtsi" diff --git a/arch/arm/dts/da850-lego-ev3.dts b/arch/arm/dts/da850-lego-ev3.dts index e281d039fd8..7207d126b38 100644 --- a/arch/arm/dts/da850-lego-ev3.dts +++ b/arch/arm/dts/da850-lego-ev3.dts @@ -1,12 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device tree for LEGO MINDSTORMS EV3 * * Copyright (C) 2017 David Lechner <david@lechnology.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * This is an absolute minimum device tree instead of using the one from Linux - * because the bootloader on the EV3 is limited to 256k. This saves us >10k. */ /dts-v1/; @@ -26,7 +22,7 @@ stdout-path = &serial1; }; - memory { + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x04000000>; }; diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi index 559659b399d..c96f64b9049 100644 --- a/arch/arm/dts/da850.dtsi +++ b/arch/arm/dts/da850.dtsi @@ -1,11 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 DENX Software Engineering GmbH * Heiko Schocher <hs@denx.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. */ #include <dt-bindings/interrupt-controller/irq.h> @@ -373,7 +369,7 @@ edma0: edma@0 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ - reg = <0x0 0x8000>; + reg = <0x0 0x8000>; reg-names = "edma3_cc"; interrupts = <11 12>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; @@ -384,14 +380,14 @@ }; edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; - reg = <0x8000 0x400>; + reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc0 1>; }; edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; - reg = <0x8400 0x400>; + reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc0 2>; @@ -399,7 +395,7 @@ edma1: edma@230000 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ - reg = <0x230000 0x8000>; + reg = <0x230000 0x8000>; reg-names = "edma3_cc"; interrupts = <93 94>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; @@ -410,7 +406,7 @@ }; edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; - reg = <0x238000 0x400>; + reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc1 21>; @@ -547,7 +543,7 @@ power-domains = <&psc1 17>; status = "disabled"; }; - ecap0: ecap@306000 { + ecap0: pwm@306000 { compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; @@ -557,7 +553,7 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap1: ecap@307000 { + ecap1: pwm@307000 { compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; @@ -567,7 +563,7 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap2: ecap@308000 { + ecap2: pwm@308000 { compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; @@ -631,7 +627,7 @@ cppi41dma: dma-controller@201000 { compatible = "ti,da830-cppi41"; - reg = <0x201000 0x1000 + reg = <0x201000 0x1000 0x202000 0x1000 0x204000 0x4000>; reg-names = "controller", diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts index 0bf55fa72de..70255ab2598 100644 --- a/arch/arm/dts/dm8168-evm.dts +++ b/arch/arm/dts/dm8168-evm.dts @@ -1,8 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0-only /dts-v1/; #include "dm816x.dtsi" @@ -120,19 +116,19 @@ label = "X-Loader"; reg = <0 0x80000>; }; - partition@0x80000 { + partition@80000 { label = "U-Boot"; reg = <0x80000 0x1c0000>; }; - partition@0x1c0000 { + partition@1c0000 { label = "Environment"; reg = <0x240000 0x40000>; }; - partition@0x280000 { + partition@280000 { label = "Kernel"; reg = <0x280000 0x500000>; }; - partition@0x780000 { + partition@780000 { label = "Filesystem"; reg = <0x780000 0xf880000>; }; @@ -143,7 +139,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - m25p80@0 { + flash@0 { compatible = "w25x32"; spi-max-frequency = <48000000>; reg = <0>; diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi index 51865eb84a8..f7a839dabf8 100644 --- a/arch/arm/dts/dm816x-clocks.dtsi +++ b/arch/arm/dts/dm816x-clocks.dtsi @@ -1,8 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0-only &scrm { main_fapll: main_fapll { diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi index fe58faf2f78..c4a8653b7f0 100644 --- a/arch/arm/dts/dm816x.dtsi +++ b/arch/arm/dts/dm816x.dtsi @@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/omap.h> @@ -67,8 +63,11 @@ ranges; prcm: prcm@48180000 { - compatible = "ti,dm816-prcm"; + compatible = "ti,dm816-prcm", "simple-bus"; reg = <0x48180000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48180000 0x4000>; prcm_clocks: clocks { #address-cells = <1>; @@ -90,6 +89,8 @@ dm816x_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x50a>; + #address-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xf>; @@ -125,6 +126,8 @@ }; scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; }; scrm_clockdomains: clockdomains { @@ -232,7 +235,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <0 0 0>; }; @@ -368,7 +371,7 @@ ti,timer-pwm; }; - uart1: uart@48020000 { + uart1: serial@48020000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart1"; reg = <0x48020000 0x2000>; @@ -378,7 +381,7 @@ dma-names = "tx", "rx"; }; - uart2: uart@48022000 { + uart2: serial@48022000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart2"; reg = <0x48022000 0x2000>; @@ -388,7 +391,7 @@ dma-names = "tx", "rx"; }; - uart3: uart@48024000 { + uart3: serial@48024000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart3"; reg = <0x48024000 0x2000>; diff --git a/arch/arm/dts/dra7-dspeve-thermal.dtsi b/arch/arm/dts/dra7-dspeve-thermal.dtsi index 1c39a8459b3..747ff0db90c 100644 --- a/arch/arm/dts/dra7-dspeve-thermal.dtsi +++ b/arch/arm/dts/dra7-dspeve-thermal.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7x SoC DSPEVE thermal * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi index 343e95f9a00..8f3a0058a38 100644 --- a/arch/arm/dts/dra7-evm-common.dtsi +++ b/arch/arm/dts/dra7-evm-common.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> @@ -132,7 +129,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; @@ -148,7 +145,7 @@ */ partition@0 { label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; + reg = <0x00000000 0x00010000>; }; partition@1 { label = "QSPI.SPL.backup1"; @@ -239,20 +236,20 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi index f1ff5f67331..87b2451a8e8 100644 --- a/arch/arm/dts/dra7-evm-u-boot.dtsi +++ b/arch/arm/dts/dra7-evm-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "omap5-u-boot.dtsi" -#include "dra7-ipu-common-early-boot.dtsi" &pcf_gpio_21{ u-boot,i2c-offset-len = <0>; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 8e9a1a80a8c..5333f171443 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -315,7 +312,7 @@ reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; @@ -419,7 +416,7 @@ #size-cells = <1>; partition@0 { label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; + reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; diff --git a/arch/arm/dts/dra7-iva-thermal.dtsi b/arch/arm/dts/dra7-iva-thermal.dtsi index dd74a5337d1..0a31313065d 100644 --- a/arch/arm/dts/dra7-iva-thermal.dtsi +++ b/arch/arm/dts/dra7-iva-thermal.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7x SoC IVA thermal * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/dts/dra7-mmc-iodelay.dtsi b/arch/arm/dts/dra7-mmc-iodelay.dtsi index 4acc215ba33..d46a1c00623 100644 --- a/arch/arm/dts/dra7-mmc-iodelay.dtsi +++ b/arch/arm/dts/dra7-mmc-iodelay.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * MMC IOdelay values for TI's DRA7xx SoCs. - * Copyright (C) 2019 Texas Instruments + * Copyright (C) 2018 Texas Instruments * Author: Faiz Abbas <faiz_abbas@ti.com> */ diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index e2e958b3662..b1aef6351a0 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1,9 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. * Based on "omap4.dtsi" */ @@ -134,7 +132,7 @@ * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ - ocp { + ocp: ocp { compatible = "ti,dra7-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -357,7 +355,13 @@ }; }; - axi@1 { + /* + * Register access seems to have complex dependencies and also + * seems to need an enabled phy. See the TRM chapter for "Table + * 26-678. Main Sequence PCIe Controller Global Initialization" + * and also dra7xx_pcie_probe(). + */ + axi1: target-module@51800000 { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; @@ -372,8 +376,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>, + <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; @@ -2112,4 +2116,4 @@ temperature = <120000>; /* milli Celsius */ }; -/include/ "dra7xx-clocks.dtsi" +#include "dra7xx-clocks.dtsi" diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi index f13eadf6b68..8e7dc719bf8 100644 --- a/arch/arm/dts/dra71-evm-u-boot.dtsi +++ b/arch/arm/dts/dra71-evm-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "omap5-u-boot.dtsi" -#include "dra7-ipu-common-early-boot.dtsi" &pcf_gpio_21{ u-boot,i2c-offset-len = <0>; diff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts index 9bf08294b27..b3225988e93 100644 --- a/arch/arm/dts/dra71-evm.dts +++ b/arch/arm/dts/dra71-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra72-evm-common.dtsi" @@ -160,7 +157,7 @@ }; &pcf_hdmi { - p0 { + hdmi-i2c-disable-hog { /* * PM_OEn to High: Disable routing I2C3 to PM_I2C * With this PM_SEL(p3) should not matter diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index 964e5e9b902..aa7a1c6744c 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -272,7 +269,7 @@ */ lines-initial-states = <0x0f2b>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; @@ -343,7 +340,7 @@ #size-cells = <1>; partition@0 { label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; + reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; @@ -441,7 +438,7 @@ status = "okay"; spi-max-frequency = <76800000>; - m25p80@0 { + flash@0 { compatible = "s25fl256s1"; spi-max-frequency = <76800000>; reg = <0>; @@ -457,7 +454,7 @@ */ partition@0 { label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; + reg = <0x00000000 0x00010000>; }; partition@1 { label = "QSPI.SPL.backup1"; @@ -549,17 +546,17 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi index f13eadf6b68..8e7dc719bf8 100644 --- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi +++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "omap5-u-boot.dtsi" -#include "dra7-ipu-common-early-boot.dtsi" &pcf_gpio_21{ u-boot,i2c-offset-len = <0>; diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts index fafc2a4d7bb..a6dbdd50344 100644 --- a/arch/arm/dts/dra72-evm-revc.dts +++ b/arch/arm/dts/dra72-evm-revc.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra72-evm-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" diff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi index 57bfe5caf5e..c7b4768dfd9 100644 --- a/arch/arm/dts/dra72-evm-tps65917.dtsi +++ b/arch/arm/dts/dra72-evm-tps65917.dtsi @@ -1,14 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf + * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf */ &tps65917 { diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index 154b0a0ceb1..2f244120463 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra72-evm-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" diff --git a/arch/arm/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/dts/dra72x-mmc-iodelay.dtsi index 088013c6dc6..98f2eacf9bf 100644 --- a/arch/arm/dts/dra72x-mmc-iodelay.dtsi +++ b/arch/arm/dts/dra72x-mmc-iodelay.dtsi @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi index 67107605fb4..481189d361b 100644 --- a/arch/arm/dts/dra72x.dtsi +++ b/arch/arm/dts/dra72x.dtsi @@ -1,9 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. * Based on "omap4.dtsi" */ @@ -31,12 +29,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -44,7 +42,7 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; diff --git a/arch/arm/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/dts/dra74x-mmc-iodelay.dtsi index 214b9e6de2c..b9d040135c5 100644 --- a/arch/arm/dts/dra74x-mmc-iodelay.dtsi +++ b/arch/arm/dts/dra74x-mmc-iodelay.dtsi @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi index 24e6746c5b2..9ade216cd45 100644 --- a/arch/arm/dts/dra74x.dtsi +++ b/arch/arm/dts/dra74x.dtsi @@ -1,9 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. * Based on "omap4.dtsi" */ @@ -100,12 +98,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -113,12 +111,12 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi index db5a466d84a..1216d93bdcd 100644 --- a/arch/arm/dts/dra76-evm-u-boot.dtsi +++ b/arch/arm/dts/dra76-evm-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "omap5-u-boot.dtsi" -#include "dra7-ipu-common-early-boot.dtsi" &cpsw_emac0 { phy-handle = <&dp83867_0>; diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts index e3da17ac97e..c131e7f7f06 100644 --- a/arch/arm/dts/dra76-evm.dts +++ b/arch/arm/dts/dra76-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -274,7 +271,7 @@ reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; @@ -382,7 +379,7 @@ &qspi { spi-max-frequency = <96000000>; - m25p80@0 { + flash@0 { spi-max-frequency = <96000000>; }; }; diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi index 1c88c581ff1..4f0e178bcf4 100644 --- a/arch/arm/dts/dra76x.dtsi +++ b/arch/arm/dts/dra76x.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra74x.dtsi" diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi index cf229dfabf6..b0cfe553afe 100644 --- a/arch/arm/dts/dra7xx-clocks.dtsi +++ b/arch/arm/dts/dra7xx-clocks.dtsi @@ -1,110 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &cm_core_aon_clocks { - atl_clkin0_ck: atl_clkin0_ck { + atl_clkin0_ck: clock-atl-clkin0 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_gfclk_mux>; }; - atl_clkin1_ck: atl_clkin1_ck { + atl_clkin1_ck: clock-atl-clkin1 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_gfclk_mux>; }; - atl_clkin2_ck: atl_clkin2_ck { + atl_clkin2_ck: clock-atl-clkin2 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_gfclk_mux>; }; - atl_clkin3_ck: atl_clkin3_ck { + atl_clkin3_ck: clock-atl-clkin3 { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; clocks = <&atl_gfclk_mux>; }; - hdmi_clkin_ck: hdmi_clkin_ck { + hdmi_clkin_ck: clock-hdmi-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - mlb_clkin_ck: mlb_clkin_ck { + mlb_clkin_ck: clock-mlb-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - mlbp_clkin_ck: mlbp_clkin_ck { + mlbp_clkin_ck: clock-mlbp-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - pciesref_acs_clk_ck: pciesref_acs_clk_ck { + pciesref_acs_clk_ck: clock-pciesref-acs { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <100000000>; }; - ref_clkin0_ck: ref_clkin0_ck { + ref_clkin0_ck: clock-ref-clkin0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - ref_clkin1_ck: ref_clkin1_ck { + ref_clkin1_ck: clock-ref-clkin1 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - ref_clkin2_ck: ref_clkin2_ck { + ref_clkin2_ck: clock-ref-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - ref_clkin3_ck: ref_clkin3_ck { + ref_clkin3_ck: clock-ref-clkin3 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - rmii_clk_ck: rmii_clk_ck { + rmii_clk_ck: clock-rmii { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - sdvenc_clkin_ck: sdvenc_clkin_ck { + sdvenc_clkin_ck: clock-sdvenc-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - secure_32k_clk_src_ck: secure_32k_clk_src_ck { + secure_32k_clk_src_ck: clock-secure-32k-clk-src { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; - sys_clk32_crystal_ck: sys_clk32_crystal_ck { + sys_clk32_crystal_ck: clock-sys-clk32-crystal { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; - sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { + sys_clk32_pseudo_ck: clock-sys-clk32-pseudo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin1>; @@ -112,104 +109,104 @@ clock-div = <610>; }; - virt_12000000_ck: virt_12000000_ck { + virt_12000000_ck: clock-virt-12000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12000000>; }; - virt_13000000_ck: virt_13000000_ck { + virt_13000000_ck: clock-virt-13000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; }; - virt_16800000_ck: virt_16800000_ck { + virt_16800000_ck: clock-virt-16800000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16800000>; }; - virt_19200000_ck: virt_19200000_ck { + virt_19200000_ck: clock-virt-19200000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <19200000>; }; - virt_20000000_ck: virt_20000000_ck { + virt_20000000_ck: clock-virt-20000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <20000000>; }; - virt_26000000_ck: virt_26000000_ck { + virt_26000000_ck: clock-virt-26000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; }; - virt_27000000_ck: virt_27000000_ck { + virt_27000000_ck: clock-virt-27000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <27000000>; }; - virt_38400000_ck: virt_38400000_ck { + virt_38400000_ck: clock-virt-38400000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <38400000>; }; - sys_clkin2: sys_clkin2 { + sys_clkin2: clock-sys-clkin2 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <22579200>; }; - usb_otg_clkin_ck: usb_otg_clkin_ck { + usb_otg_clkin_ck: clock-usb-otg-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - video1_clkin_ck: video1_clkin_ck { + video1_clkin_ck: clock-video1-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - video1_m2_clkin_ck: video1_m2_clkin_ck { + video1_m2_clkin_ck: clock-video1-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - video2_clkin_ck: video2_clkin_ck { + video2_clkin_ck: clock-video2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - video2_m2_clkin_ck: video2_m2_clkin_ck { + video2_m2_clkin_ck: clock-video2-m2-clkin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; - dpll_abe_ck: dpll_abe_ck@1e0 { + dpll_abe_ck: clock@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; - dpll_abe_x2_ck: dpll_abe_x2_ck { + dpll_abe_x2_ck: clock-dpll-abe-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { + dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -220,7 +217,7 @@ ti,invert-autoidle-bit; }; - abe_clk: abe_clk@108 { + abe_clk: clock-abe@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -229,7 +226,7 @@ ti,index-power-of-two; }; - dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { + dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_ck>; @@ -240,7 +237,7 @@ ti,invert-autoidle-bit; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { + dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -251,7 +248,7 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: dpll_core_byp_mux@12c { + dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -259,20 +256,20 @@ reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck@120 { + dpll_core_ck: clock@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; }; - dpll_core_x2_ck: dpll_core_x2_ck { + dpll_core_x2_ck: clock-dpll-core-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_core_ck>; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { + dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -283,7 +280,7 @@ ti,invert-autoidle-bit; }; - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; @@ -291,14 +288,14 @@ clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck@160 { + dpll_mpu_ck: clock@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { + dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -309,7 +306,7 @@ ti,invert-autoidle-bit; }; - mpu_dclk_div: mpu_dclk_div { + mpu_dclk_div: clock-mpu-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_mpu_m2_ck>; @@ -317,7 +314,7 @@ clock-div = <1>; }; - dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { + dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; @@ -325,7 +322,7 @@ clock-div = <1>; }; - dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { + dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; @@ -333,7 +330,7 @@ reg = <0x0240>; }; - dpll_dsp_ck: dpll_dsp_ck@234 { + dpll_dsp_ck: clock@234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; @@ -342,7 +339,7 @@ assigned-clock-rates = <600000000>; }; - dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { + dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_ck>; @@ -355,7 +352,7 @@ assigned-clock-rates = <600000000>; }; - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; @@ -363,7 +360,7 @@ clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { + dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; @@ -371,7 +368,7 @@ reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck@1a0 { + dpll_iva_ck: clock@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; @@ -380,7 +377,7 @@ assigned-clock-rates = <1165000000>; }; - dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { + dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_ck>; @@ -393,7 +390,7 @@ assigned-clock-rates = <388333334>; }; - iva_dclk: iva_dclk { + iva_dclk: clock-iva-dclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_iva_m2_ck>; @@ -401,7 +398,7 @@ clock-div = <1>; }; - dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { + dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -409,7 +406,7 @@ reg = <0x02e4>; }; - dpll_gpu_ck: dpll_gpu_ck@2d8 { + dpll_gpu_ck: clock@2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; @@ -418,7 +415,7 @@ assigned-clock-rates = <1277000000>; }; - dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { + dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_ck>; @@ -431,7 +428,7 @@ assigned-clock-rates = <425666667>; }; - dpll_core_m2_ck: dpll_core_m2_ck@130 { + dpll_core_m2_ck: clock-dpll-core-m2-8@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; @@ -442,7 +439,7 @@ ti,invert-autoidle-bit; }; - core_dpll_out_dclk_div: core_dpll_out_dclk_div { + core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_m2_ck>; @@ -450,7 +447,7 @@ clock-div = <1>; }; - dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { + dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -458,14 +455,14 @@ reg = <0x021c>; }; - dpll_ddr_ck: dpll_ddr_ck@210 { + dpll_ddr_ck: clock@210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { + dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; @@ -476,7 +473,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { + dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -484,14 +481,14 @@ reg = <0x02b4>; }; - dpll_gmac_ck: dpll_gmac_ck@2a8 { + dpll_gmac_ck: clock@2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; - dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { + dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_ck>; @@ -502,7 +499,7 @@ ti,invert-autoidle-bit; }; - video2_dclk_div: video2_dclk_div { + video2_dclk_div: clock-video2-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video2_m2_clkin_ck>; @@ -510,7 +507,7 @@ clock-div = <1>; }; - video1_dclk_div: video1_dclk_div { + video1_dclk_div: clock-video1-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video1_m2_clkin_ck>; @@ -518,7 +515,7 @@ clock-div = <1>; }; - hdmi_dclk_div: hdmi_dclk_div { + hdmi_dclk_div: clock-hdmi-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&hdmi_clkin_ck>; @@ -526,7 +523,7 @@ clock-div = <1>; }; - per_dpll_hs_clk_div: per_dpll_hs_clk_div { + per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; @@ -534,7 +531,7 @@ clock-div = <2>; }; - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_abe_m3x2_ck>; @@ -542,7 +539,7 @@ clock-div = <3>; }; - eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { + eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_core_h12x2_ck>; @@ -550,7 +547,7 @@ clock-div = <1>; }; - dpll_eve_byp_mux: dpll_eve_byp_mux@290 { + dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; @@ -558,14 +555,14 @@ reg = <0x0290>; }; - dpll_eve_ck: dpll_eve_ck@284 { + dpll_eve_ck: clock@284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; - dpll_eve_m2_ck: dpll_eve_m2_ck@294 { + dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_eve_ck>; @@ -576,7 +573,7 @@ ti,invert-autoidle-bit; }; - eve_dclk_div: eve_dclk_div { + eve_dclk_div: clock-eve-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_eve_m2_ck>; @@ -584,7 +581,7 @@ clock-div = <1>; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { + dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -595,7 +592,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { + dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -606,7 +603,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { + dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -617,7 +614,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { + dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -628,7 +625,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { + dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -639,13 +636,13 @@ ti,invert-autoidle-bit; }; - dpll_ddr_x2_ck: dpll_ddr_x2_ck { + dpll_ddr_x2_ck: clock-dpll-ddr-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_ddr_ck>; }; - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { + dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>; @@ -656,13 +653,13 @@ ti,invert-autoidle-bit; }; - dpll_dsp_x2_ck: dpll_dsp_x2_ck { + dpll_dsp_x2_ck: clock-dpll-dsp-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_dsp_ck>; }; - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { + dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_x2_ck>; @@ -675,13 +672,13 @@ assigned-clock-rates = <400000000>; }; - dpll_gmac_x2_ck: dpll_gmac_x2_ck { + dpll_gmac_x2_ck: clock-dpll-gmac-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_gmac_ck>; }; - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { + dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -692,7 +689,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { + dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -703,7 +700,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { + dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -714,7 +711,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { + dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -725,7 +722,7 @@ ti,invert-autoidle-bit; }; - gmii_m_clk_div: gmii_m_clk_div { + gmii_m_clk_div: clock-gmii-m-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_gmac_h11x2_ck>; @@ -733,7 +730,7 @@ clock-div = <2>; }; - hdmi_clk2_div: hdmi_clk2_div { + hdmi_clk2_div: clock-hdmi-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&hdmi_clkin_ck>; @@ -741,7 +738,7 @@ clock-div = <1>; }; - hdmi_div_clk: hdmi_div_clk { + hdmi_div_clk: clock-hdmi-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&hdmi_clkin_ck>; @@ -749,7 +746,7 @@ clock-div = <1>; }; - l3_iclk_div: l3_iclk_div@100 { + l3_iclk_div: clock-l3-iclk-div-4@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; @@ -759,7 +756,7 @@ ti,index-power-of-two; }; - l4_root_clk_div: l4_root_clk_div { + l4_root_clk_div: clock-l4-root-clk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&l3_iclk_div>; @@ -767,7 +764,7 @@ clock-div = <2>; }; - video1_clk2_div: video1_clk2_div { + video1_clk2_div: clock-video1-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video1_clkin_ck>; @@ -775,7 +772,7 @@ clock-div = <1>; }; - video1_div_clk: video1_div_clk { + video1_div_clk: clock-video1-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video1_clkin_ck>; @@ -783,7 +780,7 @@ clock-div = <1>; }; - video2_clk2_div: video2_clk2_div { + video2_clk2_div: clock-video2-clk2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video2_clkin_ck>; @@ -791,7 +788,7 @@ clock-div = <1>; }; - video2_div_clk: video2_div_clk { + video2_div_clk: clock-video2-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&video2_clkin_ck>; @@ -873,14 +870,14 @@ reg = <0x0580>; }; - dummy_ck: dummy_ck { + dummy_ck: clock-dummy { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; &prm_clocks { - sys_clkin1: sys_clkin1@110 { + sys_clkin1: clock-sys-clkin1@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; @@ -888,28 +885,28 @@ ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { + abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { + abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { + abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; - abe_24m_fclk: abe_24m_fclk@11c { + abe_24m_fclk: clock-abe-24m@11c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -917,7 +914,7 @@ ti,dividers = <8>, <16>; }; - aess_fclk: aess_fclk@178 { + aess_fclk: clock-aess@178 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>; @@ -925,7 +922,7 @@ ti,max-div = <2>; }; - abe_giclk_div: abe_giclk_div@174 { + abe_giclk_div: clock-abe-giclk-div@174 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>; @@ -933,7 +930,7 @@ ti,max-div = <2>; }; - abe_lp_clk_div: abe_lp_clk_div@1d8 { + abe_lp_clk_div: clock-abe-lp-clk-div@1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -941,7 +938,7 @@ ti,dividers = <16>, <32>; }; - abe_sys_clk_div: abe_sys_clk_div@120 { + abe_sys_clk_div: clock-abe-sys-clk-div@120 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -949,14 +946,14 @@ ti,max-div = <2>; }; - adc_gfclk_mux: adc_gfclk_mux@1dc { + adc_gfclk_mux: clock-adc-gfclk-mux@1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; - sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { + sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -965,7 +962,7 @@ ti,index-power-of-two; }; - sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { + sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin2>; @@ -974,7 +971,7 @@ ti,index-power-of-two; }; - per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { + per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; @@ -983,7 +980,7 @@ ti,index-power-of-two; }; - dsp_gclk_div: dsp_gclk_div@18c { + dsp_gclk_div: clock-dsp-gclk-div@18c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_m2_ck>; @@ -992,7 +989,7 @@ ti,index-power-of-two; }; - gpu_dclk: gpu_dclk@1a0 { + gpu_dclk: clock-gpu-dclk@1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_m2_ck>; @@ -1001,7 +998,7 @@ ti,index-power-of-two; }; - emif_phy_dclk_div: emif_phy_dclk_div@190 { + emif_phy_dclk_div: clock-emif-phy-dclk-div@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_m2_ck>; @@ -1010,7 +1007,7 @@ ti,index-power-of-two; }; - gmac_250m_dclk_div: gmac_250m_dclk_div@19c { + gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_m2_ck>; @@ -1019,7 +1016,7 @@ ti,index-power-of-two; }; - gmac_main_clk: gmac_main_clk { + gmac_main_clk: clock-gmac-main { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&gmac_250m_dclk_div>; @@ -1027,7 +1024,7 @@ clock-div = <2>; }; - l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { + l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; @@ -1036,7 +1033,7 @@ ti,index-power-of-two; }; - usb_otg_dclk_div: usb_otg_dclk_div@184 { + usb_otg_dclk_div: clock-usb-otg-dclk-div@184 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&usb_otg_clkin_ck>; @@ -1045,7 +1042,7 @@ ti,index-power-of-two; }; - sata_dclk_div: sata_dclk_div@1c0 { + sata_dclk_div: clock-sata-dclk-div@1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -1054,7 +1051,7 @@ ti,index-power-of-two; }; - pcie2_dclk_div: pcie2_dclk_div@1b8 { + pcie2_dclk_div: clock-pcie2-dclk-div@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_m2_ck>; @@ -1063,7 +1060,7 @@ ti,index-power-of-two; }; - pcie_dclk_div: pcie_dclk_div@1b4 { + pcie_dclk_div: clock-pcie-dclk-div@1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&apll_pcie_m2_ck>; @@ -1072,7 +1069,7 @@ ti,index-power-of-two; }; - emu_dclk_div: emu_dclk_div@194 { + emu_dclk_div: clock-emu-dclk-div@194 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -1081,7 +1078,7 @@ ti,index-power-of-two; }; - secure_32k_dclk_div: secure_32k_dclk_div@1c4 { + secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&secure_32k_clk_src_ck>; @@ -1090,28 +1087,28 @@ ti,index-power-of-two; }; - clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { + clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; - clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { + clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; - clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { + clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0160>; }; - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&sys_clkin1>; @@ -1119,21 +1116,21 @@ clock-div = <2>; }; - eve_clk: eve_clk@180 { + eve_clk: clock-eve@180 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { + hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; - mlb_clk: mlb_clk@134 { + mlb_clk: clock-mlb@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlb_clkin_ck>; @@ -1142,7 +1139,7 @@ ti,index-power-of-two; }; - mlbp_clk: mlbp_clk@130 { + mlbp_clk: clock-mlbp@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlbp_clkin_ck>; @@ -1151,7 +1148,7 @@ ti,index-power-of-two; }; - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { + per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; @@ -1160,7 +1157,7 @@ ti,index-power-of-two; }; - timer_sys_clk_div: timer_sys_clk_div@144 { + timer_sys_clk_div: clock-timer-sys-clk-div@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -1168,21 +1165,21 @@ ti,max-div = <2>; }; - video1_dpll_clk_mux: video1_dpll_clk_mux@168 { + video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; - video2_dpll_clk_mux: video2_dpll_clk_mux@16c { + video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { + wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; @@ -1222,14 +1219,14 @@ }; }; &cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { + dpll_pcie_ref_ck: clock@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { + dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>; @@ -1240,7 +1237,7 @@ ti,invert-autoidle-bit; }; - apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 { compatible = "ti,mux-clock"; clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; @@ -1248,7 +1245,7 @@ ti,bit-shift = <7>; }; - apll_pcie_ck: apll_pcie_ck@21c { + apll_pcie_ck: clock@21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; @@ -1271,7 +1268,7 @@ ti,bit-shift = <8>; }; - optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; @@ -1313,7 +1310,7 @@ ti,bit-shift = <10>; }; - apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { + apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; @@ -1321,7 +1318,7 @@ clock-div = <1>; }; - apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { + apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; @@ -1329,7 +1326,7 @@ clock-div = <1>; }; - apll_pcie_m2_ck: apll_pcie_m2_ck { + apll_pcie_m2_ck: clock-apll-pcie-m2 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; @@ -1337,7 +1334,7 @@ clock-div = <1>; }; - dpll_per_byp_mux: dpll_per_byp_mux@14c { + dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; @@ -1345,14 +1342,14 @@ reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck@140 { + dpll_per_ck: clock@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck@150 { + dpll_per_m2_ck: clock-dpll-per-m2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -1363,7 +1360,7 @@ ti,invert-autoidle-bit; }; - func_96m_aon_dclk_div: func_96m_aon_dclk_div { + func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; @@ -1371,7 +1368,7 @@ clock-div = <1>; }; - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { + dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; @@ -1379,14 +1376,14 @@ reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck@180 { + dpll_usb_ck: clock@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { + dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; @@ -1397,7 +1394,7 @@ ti,invert-autoidle-bit; }; - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { + dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>; @@ -1408,13 +1405,13 @@ ti,invert-autoidle-bit; }; - dpll_per_x2_ck: dpll_per_x2_ck { + dpll_per_x2_ck: clock-dpll-per-x2 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { + dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1425,7 +1422,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { + dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1436,7 +1433,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { + dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1447,7 +1444,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { + dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1458,7 +1455,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { + dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1469,7 +1466,7 @@ ti,invert-autoidle-bit; }; - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_usb_ck>; @@ -1477,7 +1474,7 @@ clock-div = <1>; }; - func_128m_clk: func_128m_clk { + func_128m_clk: clock-func-128m { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_h11x2_ck>; @@ -1485,7 +1482,7 @@ clock-div = <2>; }; - func_12m_fclk: func_12m_fclk { + func_12m_fclk: clock-func-12m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -1493,7 +1490,7 @@ clock-div = <16>; }; - func_24m_clk: func_24m_clk { + func_24m_clk: clock-func-24m { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2_ck>; @@ -1501,7 +1498,7 @@ clock-div = <4>; }; - func_48m_fclk: func_48m_fclk { + func_48m_fclk: clock-func-48m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -1509,7 +1506,7 @@ clock-div = <4>; }; - func_96m_fclk: func_96m_fclk { + func_96m_fclk: clock-func-96m-fclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -1517,7 +1514,7 @@ clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk@104 { + l3init_60m_fclk: clock-l3init-60m@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; @@ -1525,7 +1522,7 @@ ti,dividers = <1>, <8>; }; - clkout2_clk: clkout2_clk@6b0 { + clkout2_clk: clock-clkout2-8@6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkoutmux2_clk_mux>; @@ -1533,7 +1530,7 @@ reg = <0x06b0>; }; - l3init_960m_gfclk: l3init_960m_gfclk@6c0 { + l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_clkdcoldo>; @@ -1702,7 +1699,7 @@ reg = <0x1340>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { + usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1710,7 +1707,7 @@ reg = <0x0640>; }; - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { + usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1718,7 +1715,7 @@ reg = <0x0688>; }; - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { + usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1758,7 +1755,7 @@ reg = <0x13d0>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { + gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; @@ -1768,7 +1765,7 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { + gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; @@ -1778,7 +1775,7 @@ assigned-clock-parents = <&dpll_gpu_m2_ck>; }; - l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { + l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&wkupaon_iclk_mux>; @@ -2141,7 +2138,7 @@ reg = <0x18e8>; }; - vip1_gclk_mux: vip1_gclk_mux@1020 { + vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; @@ -2149,7 +2146,7 @@ reg = <0x1020>; }; - vip2_gclk_mux: vip2_gclk_mux@1028 { + vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts index 1722dce33ff..b4f057ac653 100644 --- a/arch/arm/dts/dragonboard845c.dts +++ b/arch/arm/dts/dragonboard845c.dts @@ -21,7 +21,7 @@ }; aliases { - serial0 = &debug_uart; + serial0 = &uart9; }; memory { diff --git a/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi new file mode 100644 index 00000000000..298adb849b3 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi new file mode 100644 index 00000000000..298adb849b3 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi new file mode 100644 index 00000000000..89566bf8493 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +#include "fsl-ls1088a-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + }; +}; + +&i2c0 { + uc: board-controller@7e { + compatible = "traverse,ten64-controller"; + reg = <0x7e>; + }; +}; + diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts index 55a7d41fb01..0d11440d88d 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ b/arch/arm/dts/fsl-ls1088a-ten64.dts @@ -1,9 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Device Tree file for Travese Ten64 (LS1088) board + * Device Tree file for Traverse Technologies Ten64 + * (LS1088A) board * Based on fsl-ls1088a-rdb.dts * Copyright 2017-2020 NXP - * Copyright 2019-2021 Traverse Technologies + * Copyright 2019-2023 Traverse Technologies * * Author: Mathew McBride <matt@traverse.com.au> */ @@ -22,7 +23,6 @@ aliases { serial0 = &duart0; serial1 = &duart1; - spi0 = &qspi; }; chosen { @@ -36,18 +36,16 @@ * external power off (e.g ATX Power Button) * asserted */ - powerdn { + button-powerdn { label = "External Power Down"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>; linux,code = <KEY_POWER>; }; /* Rear Panel 'ADMIN' button (GPIO_H) */ - admin { + button-admin { label = "ADMIN button"; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>; linux,code = <KEY_WPS_BUTTON>; }; }; @@ -55,17 +53,17 @@ leds { compatible = "gpio-leds"; - sfp1down { + led-0 { label = "ten64:green:sfp1:down"; gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; }; - sfp2up { + led-1 { label = "ten64:green:sfp2:up"; gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; }; - admin { + led-2 { label = "ten64:admin"; gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; }; @@ -95,17 +93,17 @@ /* XG1 - Upper SFP */ &dpmac1 { sfp = <&sfp_xg1>; + pcs-handle = <&pcs1>; phy-connection-type = "10gbase-r"; managed = "in-band-status"; - status = "okay"; }; /* XG0 - Lower SFP */ &dpmac2 { sfp = <&sfp_xg0>; + pcs-handle = <&pcs2>; phy-connection-type = "10gbase-r"; managed = "in-band-status"; - status = "okay"; }; /* DPMAC3..6 is GE4 to GE8 */ @@ -113,28 +111,28 @@ phy-handle = <&mdio1_phy5>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_0>; }; &dpmac4 { phy-handle = <&mdio1_phy6>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_1>; }; &dpmac5 { phy-handle = <&mdio1_phy7>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_2>; }; &dpmac6 { phy-handle = <&mdio1_phy8>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs3_3>; }; /* DPMAC7..10 is GE0 to GE3 */ @@ -142,28 +140,28 @@ phy-handle = <&mdio1_phy1>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_0>; }; &dpmac8 { phy-handle = <&mdio1_phy2>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_1>; }; &dpmac9 { phy-handle = <&mdio1_phy3>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_2>; }; &dpmac10 { phy-handle = <&mdio1_phy4>; phy-connection-type = "qsgmii"; managed = "in-band-status"; - status = "okay"; + pcs-handle = <&pcs7_3>; }; &duart0 { @@ -234,11 +232,6 @@ compatible = "atmel,at97sc3204t"; reg = <0x29>; }; - - uc: board-controller@7e { - compatible = "traverse,ten64-controller"; - reg = <0x7e>; - }; }; &i2c2 { @@ -253,7 +246,7 @@ &i2c3 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9540"; #address-cells = <1>; #size-cells = <0>; @@ -273,6 +266,22 @@ }; }; +&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi new file mode 100644 index 00000000000..efcfdd96aef --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <config.h> + +/{ + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; +}; + +&duart0 { + bootph-all; +}; + +&duart1 { + bootph-all; +}; + +/* MDIO controllers - U-Boot uses a different + * driver for the DPAA2 (LS/LX2) family, + * so must match fsl,ls-mdio first. + */ +&emdio1 { + compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; +}; + +&emdio2 { + compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio"; +}; + +/* DPAA2 Management Complex (MC) + * "simple-mfd" compatible used by U-Boot only, + * to allow driver model functionality. + */ +&fsl_mc { + compatible = "fsl,qoriq-mc", "simple-mfd"; + + dpmacs { + compatible = "simple-mfd"; + }; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&pcie3 { + status = "okay"; +}; + +&usb0 { + compatible = "fsl,layerscape-dwc3", "snps,dwc3"; +}; + +&usb1 { + compatible = "fsl,layerscape-dwc3", "snps,dwc3"; +}; + diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 4782b83515a..e5fb137ac02 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -1,39 +1,202 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * NXP ls1088a SOC common device tree source + * Device Tree Include file for NXP Layerscape-1088A family SoC. + * + * Copyright 2017-2020 NXP + * + * Harninder Rai <harninder.rai@nxp.com> * - * Copyright 2017, 2020-2021, 2023 NXP */ - #include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> + / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ + aliases { + crypto = &crypto; + rtc1 = &ftm_alarm0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* We have 2 clusters having 4 Cortex-A53 cores each */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + clocks = <&clockgen QORIQ_CLK_CMUX 1>; + cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; + }; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x0>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; }; gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ #interrupt-cells = <3>; interrupt-controller; - interrupts = <1 9 0x4>; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ + <0x0 0x0c0c0000 0 0x2000>, /* GICC */ + <0x0 0x0c0d0000 0 0x1000>, /* GICH */ + <0x0 0x0c0e0000 0 0x20000>; /* GICV */ + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + thermal-zones { + core-cluster { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ - <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ - <1 11 0x8>, /* Virtual PPI, active-low */ - <1 10 0x8>; /* Hypervisor PPI, active-low */ + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; }; sysclk: sysclk { @@ -43,6 +206,13 @@ clock-output-names = "sysclk"; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -57,6 +227,121 @@ clocks = <&sysclk>; }; + dcfg: dcfg@1e00000 { + compatible = "fsl,ls1088a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + + isc: syscon@1f70000 { + compatible = "fsl,ls1088a-isc", "syscon"; + reg = <0x0 0x1f70000 0x0 0x10000>; + little-endian; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1f70000 0x10000>; + + extirq: interrupt-controller@14 { + compatible = "fsl,ls1088a-extirq"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x14 4>; + interrupt-map = + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0xf 0x0>; + }; + }; + + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; + fsl,tmu-calibration = + /* Calibration data group 1 */ + <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000030 + 0x00000003 0x00000037 + 0x00000004 0x0000003d + 0x00000005 0x00000044 + 0x00000006 0x0000004a + 0x00000007 0x00000051 + 0x00000008 0x00000057 + 0x00000009 0x0000005e + 0x0000000a 0x00000064 + 0x0000000b 0x0000006b + /* Calibration data group 2 */ + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a + /* Calibration data group 3 */ + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x00000040 + 0x00020004 0x0000004a + 0x00020005 0x00000054 + 0x00020006 0x0000005e + /* Calibration data group 4 */ + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000027 + 0x00030003 0x00000032 + 0x00030004 0x0000003e + 0x00030005 0x00000049 + 0x00030006 0x00000054 + 0x00030007 0x00000060>; + little-endian; + #thermal-sensor-cells = <1>; + }; + + dspi: spi@2100000 { + compatible = "fsl,ls1088a-dspi", + "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + spi-num-chipselects = <6>; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; @@ -64,7 +349,6 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - bootph-all; }; duart1: serial@21c0600 { @@ -74,328 +358,694 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - bootph-all; }; - }; - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 4>; - }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 4>; - }; + gpio1: gpio@2310000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 4>; - }; + gpio2: gpio@2320000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 4>; - }; + gpio3: gpio@2330000 { + compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; - dspi: dspi@2100000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; /* Level high type */ - spi-num-chipselects = <6>; - }; + ifc: memory-controller@2240000 { + compatible = "fsl,ifc"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; - qspi: quadspi@1550000 { - compatible = "fsl,ls1088a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - status = "disabled"; - }; + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - esdhc: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - little-endian; - bus-width = <4>; - }; + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - gpio0: gpio@2300000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - gpio1: gpio@2310000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + status = "disabled"; + }; - gpio2: gpio@2320000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + qspi: spi@20c0000 { + compatible = "fsl,ls2080a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + status = "disabled"; + }; - gpio3: gpio@2330000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; + esdhc: esdhc@2140000 { + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clock-frequency = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + status = "disabled"; + }; - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 0x4>; /* Level high type */ - }; + usb0: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; - usb0: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - }; + usb1: usb@3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; - usb1: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - }; + sata: sata@3200000 { + compatible = "fsl,ls1088a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x7 0x100520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + dma-coherent; + status = "disabled"; + }; - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - dma-coherent; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; }; - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + pcie1: pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <256>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; }; - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x20 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <24>; + num-ob-windows = <256>; + max-functions = /bits/ 8 <2>; + status = "disabled"; }; - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + pcie2: pcie@3500000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; }; - }; - pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ - 0x00 0x03480000 0x0 0x80000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x20 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x28 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; - pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ - 0x00 0x03580000 0x0 0x80000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x28 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + pcie3: pcie@3600000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <6>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; - pcie3: pcie@3600000 { - compatible = "fsl,ls-pcie", "snps,dw-pcie"; - reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ - 0x00 0x03680000 0x0 0x80000 /* lut registers */ - 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ - 0x30 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x30 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; - sata: sata@3200000 { - compatible = "fsl,ls1088a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "ahci", "sata-ecc"; - interrupts = <0 133 4>; - status = "disabled"; - }; + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + stream-match-mask = <0x7C00>; + dma-coherent; + #global-interrupts = <12>; + // global secure fault + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + // combined secure + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + // global non-secure fault + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + // combined non-secure + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + // performance counter interrupts 0-7 + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + // per context interrupt, 64 interrupts + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + }; - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; + console@8340020 { + compatible = "fsl,dpaa2-console"; + reg = <0x00000000 0x08340020 0 0x2>; + }; + + ptp-timer@8b95000 { + compatible = "fsl,dpaa2-ptp"; + reg = <0x0 0x8b95000 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + little-endian; + fsl,extts-fifo; + }; + + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <2500000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + status = "disabled"; + }; - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc", "simple-mfd"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - compatible = "simple-mfd"; + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; #address-cells = <1>; #size-cells = <0>; + clock-frequency = <2500000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; + status = "disabled"; + }; - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - status = "disabled"; + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - status = "disabled"; + pcs2: ethernet-phy@0 { + reg = <0>; }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - status = "disabled"; + pcs3_0: ethernet-phy@0 { + reg = <0>; }; - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - status = "disabled"; + pcs3_1: ethernet-phy@1 { + reg = <1>; }; - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - status = "disabled"; + pcs3_2: ethernet-phy@2 { + reg = <2>; }; - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - status = "disabled"; + pcs3_3: ethernet-phy@3 { + reg = <3>; }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - status = "disabled"; + pcs7_0: ethernet-phy@0 { + reg = <0>; }; - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - status = "disabled"; + pcs7_1: ethernet-phy@1 { + reg = <1>; }; - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - status = "disabled"; + pcs7_2: ethernet-phy@2 { + reg = <2>; }; - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - status = "disabled"; + pcs7_3: ethernet-phy@3 { + reg = <3>; }; }; - }; - emdio1: mdio@8B96000 { - compatible = "fsl,ls-mdio"; - reg = <0x0 0x8B96000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core1_watchdog: wdt@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core2_watchdog: wdt@c020000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc020000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core3_watchdog: wdt@c030000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc030000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core0_watchdog: wdt@c100000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core1_watchdog: wdt@c110000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core2_watchdog: wdt@c120000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc120000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster2_core3_watchdog: wdt@c130000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc130000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + msi-parent = <&its>; + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ + dma-coherent; + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: ethernet@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <1>; + }; + + dpmac2: ethernet@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <2>; + }; + + dpmac3: ethernet@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <3>; + }; + + dpmac4: ethernet@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <4>; + }; + + dpmac5: ethernet@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <5>; + }; + + dpmac6: ethernet@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <6>; + }; + + dpmac7: ethernet@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <7>; + }; + + dpmac8: ethernet@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <8>; + }; + + dpmac9: ethernet@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <9>; + }; + + dpmac10: ethernet@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + }; + }; + }; + + rcpm: power-controller@1e34040 { + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x18>; + #fsl,rcpm-wakeup-cells = <6>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1088a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; }; - emdio2: mdio@8B97000 { - compatible = "fsl,ls-mdio"; - reg = <0x0 0x8B97000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; }; }; diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi new file mode 100644 index 00000000000..eb320761f2f --- /dev/null +++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "hi3798mv200-u-boot.dtsi" + +/* The clock driver is missing */ +&sd0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts new file mode 100644 index 00000000000..c4ca5ed2354 --- /dev/null +++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS File for Skyworth HC2910 with board label 2AGHD05 set-top box. + * + * Released under the GPLv2 only. + */ + +/dts-v1/; + +#include "hi3798mv200.dtsi" + +/ { + // Usually known as Henan Guangdian HC2910 + model = "Skyworth HC2910 with board label 2AGHD05"; + compatible = "skyworth,hc2910-2aghd05", "hisilicon,hi3798mv200"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&ehci { + status = "okay"; +}; + +&emmc { + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&gmac { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ð_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + + eth_phy1: phy@3 { + reg = <3>; + }; +}; + +&ohci { + status = "okay"; +}; + +&sd0 { + bus-width = <4>; + cap-sd-highspeed; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/hi3798mv200-u-boot.dtsi b/arch/arm/dts/hi3798mv200-u-boot.dtsi new file mode 100644 index 00000000000..8917bcf33d3 --- /dev/null +++ b/arch/arm/dts/hi3798mv200-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot addition to: + * 1) use platform data for the console + * + */ + +#include <dt-bindings/reset/ti-syscon.h> + +/* The driver in U-Boot does not support "snps,dw-mshc" compatible. */ +&sd0 { + compatible = "hisilicon,hi3798mv200-dw-mshc"; +}; + +&sd1 { + compatible = "hisilicon,hi3798mv200-dw-mshc"; +}; + +/* The clock driver is missing */ +&uart0 { + clock = <75000000>; +}; diff --git a/arch/arm/dts/hi3798mv200.dtsi b/arch/arm/dts/hi3798mv200.dtsi new file mode 100644 index 00000000000..fedf87ac679 --- /dev/null +++ b/arch/arm/dts/hi3798mv200.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTS File for HiSilicon Hi3798mv200 SoC. + * + * Released under the GPLv2 only. + */ + +#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/ti-syscon.h> + +/ { + compatible = "hisilicon,hi3798mv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ + <0x0 0xf1002000 0x0 0x100>; /* GICC */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + /* Initialization is done in boot loader */ + usb2_phy1: hsusb1_phy { + compatible = "usb-nop-xceiv"; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + clock-names = "main"; + #phy-cells = <0>; + }; + + soc: soc@f0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xf0000000 0x10000000>; + + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + sysctrl: system-controller@8000000 { + compatible = "hisilicon,hi3798mv200-sysctrl", "syscon"; + reg = <0x8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798mv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798mv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = <PHY_TYPE_USB3>; + }; + }; + + pmx0: pinconf@8a21000 { + compatible = "pinconf-single"; + reg = <0x8a21000 0x180>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + }; + + uart0: serial@8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b00000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + sd0: mmc@9820000 { + compatible = "snps,dw-mshc"; + reg = <0x9820000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_SDIO0_CIU_CLK>, + <&crg HISTB_SDIO0_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x9c 4>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798mv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + resets = <&crg 0xa0 4>; + reset-names = "reset"; + status = "disabled"; + }; + + gmac: ethernet@9840000 { + compatible = "hisilicon,hi3798mv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9840000 0x1000>, + <0x984300c 0x4>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 0>, + <&crg 0xcc 2>, + <&crg 0xcc 5>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + ohci: ohci@9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "bus", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + status = "disabled"; + }; + + ehci: ehci@9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>, + <&crg HISTB_USB2_UTMI_CLK>; + clock-names = "bus", "phy", "utmi"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>, + <&crg 0xb8 13>; + reset-names = "bus", "phy", "utmi"; + phys = <&usb2_phy1>; + phy-names = "usb"; + status = "disabled"; + }; + + sd1: mmc@9c40000 { + compatible = "snps,dw-mshc"; + reg = <0x9c40000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_SDIO1_CIU_CLK>, + <&crg HISTB_SDIO1_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x28c 4>; + reset-names = "reset"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi new file mode 100644 index 00000000000..46a4dfe4e8a --- /dev/null +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "imx8mq-u-boot.dtsi" + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&uart1 { /* console */ + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts new file mode 100644 index 00000000000..cff150de07c --- /dev/null +++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2017-2018 NXP + * Copyright 2019-2023 Kococonnector GmbH + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" + +/ { + model = "Advantech iMX8QM DMSSE20"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_rtc_mc_8803: rtc-mc-8803-grp{ + fsl,pins = < + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c + SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020 + SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-names = "default","state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec1 { + fsl,ar8031-phy-fixup; + fsl,magic-packet; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&fec2 { + fsl,ar8031-phy-fixup; + fsl,magic-packet; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_mc_8803>; + status = "okay"; + + rv8803@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + 24c02@50 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,24c04"; + reg = <0x50>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index dad46704a2d..78df7cec3f9 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -47,7 +47,8 @@ compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; clocks = <&k3_clks 61 0>; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index c953a82c7a5..cc4b179e27f 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -47,7 +47,8 @@ compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; clocks = <&k3_clks 61 0>; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index ca5ce4a35a5..e870492a690 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -32,7 +32,8 @@ compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; clocks = <&k3_clks 61 0>; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 9ff4dd3dd36..32d4c317284 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -34,7 +34,8 @@ compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; clocks = <&k3_clks 61 0>; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi index e7e0ca41597..e73458ca690 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi @@ -49,5 +49,3 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; }; - -#include "k3-am65-iot2050-common-pg2-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi index 0d215b4d668..4a9bf7d7c07 100644 --- a/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm/dts/k3-am6528-iot2050-basic-common.dtsi @@ -11,9 +11,6 @@ #include "k3-am65-iot2050-common.dtsi" -#include "k3-am65-iot2050-common-u-boot.dtsi" -#include "k3-am65-iot2050-boot-image.dtsi" - / { memory@80000000 { device_type = "memory"; diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi new file mode 100644 index 00000000000..1e393042ac0 --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic-pg2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +#include "k3-am65-iot2050-common-u-boot.dtsi" +#include "k3-am65-iot2050-common-pg2-u-boot.dtsi" +#include "k3-am65-iot2050-boot-image.dtsi" diff --git a/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi b/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi new file mode 100644 index 00000000000..64afe25e38f --- /dev/null +++ b/arch/arm/dts/k3-am6528-iot2050-basic-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +#include "k3-am65-iot2050-common-u-boot.dtsi" +#include "k3-am65-iot2050-boot-image.dtsi" diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi index 816a4cb4a68..d25e8b26187 100644 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-common.dtsi @@ -13,9 +13,6 @@ #include "k3-am65-iot2050-common.dtsi" -#include "k3-am65-iot2050-common-u-boot.dtsi" -#include "k3-am65-iot2050-boot-image.dtsi" - / { memory@80000000 { device_type = "memory"; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi new file mode 120000 index 00000000000..859776d3ffe --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi new file mode 120000 index 00000000000..859776d3ffe --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-pg2-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-pg2-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi b/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi new file mode 120000 index 00000000000..ac30e4ef46e --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-u-boot.dtsi @@ -0,0 +1 @@ +k3-am6528-iot2050-basic-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi index 42ac8c5c89c..9ec8dff44be 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0 - * This file was generated on 08/07/2020 - * Includes hand-edits - */ + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0 + * This file was generated on 06/01/2021 +*/ #define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 666500000 #define DDRSS_PLL_FREQUENCY_2 666500000 @@ -17,10 +17,10 @@ #define DDRSS_CTL_04_DATA 0x00000000 #define DDRSS_CTL_05_DATA 0x00000000 #define DDRSS_CTL_06_DATA 0x00000000 -#define DDRSS_CTL_07_DATA 0x00002710 -#define DDRSS_CTL_08_DATA 0x000186A0 +#define DDRSS_CTL_07_DATA 0x00002AF8 +#define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 -#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_10_DATA 0x0000006E #define DDRSS_CTL_11_DATA 0x000411AB #define DDRSS_CTL_12_DATA 0x0028B0AB #define DDRSS_CTL_13_DATA 0x00000005 @@ -33,11 +33,11 @@ #define DDRSS_CTL_20_DATA 0x02011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 -#define DDRSS_CTL_23_DATA 0x0000000A -#define DDRSS_CTL_24_DATA 0x00000019 +#define DDRSS_CTL_23_DATA 0x0000000B +#define DDRSS_CTL_24_DATA 0x0000001C #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 -#define DDRSS_CTL_27_DATA 0x02020200 +#define DDRSS_CTL_27_DATA 0x03020200 #define DDRSS_CTL_28_DATA 0x00003636 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 @@ -54,7 +54,7 @@ #define DDRSS_CTL_41_DATA 0x113C0057 #define DDRSS_CTL_42_DATA 0x2000291B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x040006DB +#define DDRSS_CTL_44_DATA 0x0400078A #define DDRSS_CTL_45_DATA 0x130E0B04 #define DDRSS_CTL_46_DATA 0x0A00B6D0 #define DDRSS_CTL_47_DATA 0x130E0B0A @@ -62,7 +62,7 @@ #define DDRSS_CTL_49_DATA 0x0203040A #define DDRSS_CTL_50_DATA 0x1C040500 #define DDRSS_CTL_51_DATA 0x081D1C1D -#define DDRSS_CTL_52_DATA 0x14000D0A +#define DDRSS_CTL_52_DATA 0x14000E0A #define DDRSS_CTL_53_DATA 0x02010A0A #define DDRSS_CTL_54_DATA 0x01010002 #define DDRSS_CTL_55_DATA 0x04383808 @@ -70,15 +70,15 @@ #define DDRSS_CTL_57_DATA 0x00001F1F #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 -#define DDRSS_CTL_60_DATA 0x00000E08 -#define DDRSS_CTL_61_DATA 0x000000BB +#define DDRSS_CTL_60_DATA 0x00001008 +#define DDRSS_CTL_61_DATA 0x000000CE #define DDRSS_CTL_62_DATA 0x00000176 #define DDRSS_CTL_63_DATA 0x00001448 #define DDRSS_CTL_64_DATA 0x00000176 #define DDRSS_CTL_65_DATA 0x00001448 #define DDRSS_CTL_66_DATA 0x00000005 -#define DDRSS_CTL_67_DATA 0x00030000 -#define DDRSS_CTL_68_DATA 0x005D0010 +#define DDRSS_CTL_67_DATA 0x00040000 +#define DDRSS_CTL_68_DATA 0x005D0012 #define DDRSS_CTL_69_DATA 0x005D0282 #define DDRSS_CTL_70_DATA 0x00400282 #define DDRSS_CTL_71_DATA 0x00120103 @@ -89,7 +89,7 @@ #define DDRSS_CTL_76_DATA 0x03130A07 #define DDRSS_CTL_77_DATA 0x0A070301 #define DDRSS_CTL_78_DATA 0x00010313 -#define DDRSS_CTL_79_DATA 0x000F000F +#define DDRSS_CTL_79_DATA 0x00100010 #define DDRSS_CTL_80_DATA 0x01800180 #define DDRSS_CTL_81_DATA 0x01800180 #define DDRSS_CTL_82_DATA 0x03050505 @@ -112,13 +112,13 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00002EC0 -#define DDRSS_CTL_103_DATA 0x00002EC0 -#define DDRSS_CTL_104_DATA 0x00002EC0 -#define DDRSS_CTL_105_DATA 0x00002EC0 -#define DDRSS_CTL_106_DATA 0x00002EC0 +#define DDRSS_CTL_102_DATA 0x00003380 +#define DDRSS_CTL_103_DATA 0x00003380 +#define DDRSS_CTL_104_DATA 0x00003380 +#define DDRSS_CTL_105_DATA 0x00003380 +#define DDRSS_CTL_106_DATA 0x00003380 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x0000051D +#define DDRSS_CTL_108_DATA 0x000005A2 #define DDRSS_CTL_109_DATA 0x00051200 #define DDRSS_CTL_110_DATA 0x00051200 #define DDRSS_CTL_111_DATA 0x00051200 @@ -174,9 +174,9 @@ #define DDRSS_CTL_161_DATA 0x00000000 #define DDRSS_CTL_162_DATA 0x00000000 #define DDRSS_CTL_163_DATA 0x00000000 -#define DDRSS_CTL_164_DATA 0x000A0000 -#define DDRSS_CTL_165_DATA 0x000D0005 -#define DDRSS_CTL_166_DATA 0x000D0404 +#define DDRSS_CTL_164_DATA 0x000B0000 +#define DDRSS_CTL_165_DATA 0x000E0006 +#define DDRSS_CTL_166_DATA 0x000E0404 #define DDRSS_CTL_167_DATA 0x0086010B #define DDRSS_CTL_168_DATA 0x0A0A014E #define DDRSS_CTL_169_DATA 0x010B014E @@ -191,7 +191,7 @@ #define DDRSS_CTL_178_DATA 0x36000000 #define DDRSS_CTL_179_DATA 0x27270036 #define DDRSS_CTL_180_DATA 0x0F0F0000 -#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_181_DATA 0x15000000 #define DDRSS_CTL_182_DATA 0x00841515 #define DDRSS_CTL_183_DATA 0x24C424C4 #define DDRSS_CTL_184_DATA 0x2B2B2B00 @@ -199,7 +199,7 @@ #define DDRSS_CTL_186_DATA 0x00363600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F -#define DDRSS_CTL_189_DATA 0x15150000 +#define DDRSS_CTL_189_DATA 0x15151500 #define DDRSS_CTL_190_DATA 0x00000020 #define DDRSS_CTL_191_DATA 0x00000000 #define DDRSS_CTL_192_DATA 0x00000001 @@ -268,7 +268,7 @@ #define DDRSS_CTL_255_DATA 0x00000000 #define DDRSS_CTL_256_DATA 0x00000000 #define DDRSS_CTL_257_DATA 0x01000200 -#define DDRSS_CTL_258_DATA 0x00320040 +#define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 #define DDRSS_CTL_261_DATA 0x00280536 @@ -399,13 +399,13 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x2E2E1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x00000176 +#define DDRSS_CTL_389_DATA 0x0000019C #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x00000462 -#define DDRSS_CTL_395_DATA 0x00000E9C +#define DDRSS_CTL_394_DATA 0x000004D4 +#define DDRSS_CTL_395_DATA 0x00001018 #define DDRSS_CTL_396_DATA 0x00000204 #define DDRSS_CTL_397_DATA 0x00002890 #define DDRSS_CTL_398_DATA 0x00000200 @@ -432,7 +432,7 @@ #define DDRSS_CTL_419_DATA 0x00000000 #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 -#define DDRSS_CTL_422_DATA 0x0006001E +#define DDRSS_CTL_422_DATA 0x0007001F #define DDRSS_CTL_423_DATA 0x0013002B #define DDRSS_CTL_424_DATA 0x0013002B #define DDRSS_CTL_425_DATA 0x00000000 @@ -633,14 +633,14 @@ #define DDRSS_PI_160_DATA 0x00000000 #define DDRSS_PI_161_DATA 0x00010000 #define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x1B1B0100 +#define DDRSS_PI_163_DATA 0x1B1B0200 #define DDRSS_PI_164_DATA 0x00000034 #define DDRSS_PI_165_DATA 0x00000051 #define DDRSS_PI_166_DATA 0x00020051 #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x300C0C04 -#define DDRSS_PI_169_DATA 0x000E300C -#define DDRSS_PI_170_DATA 0x000000BB +#define DDRSS_PI_169_DATA 0x0010300C +#define DDRSS_PI_170_DATA 0x000000CE #define DDRSS_PI_171_DATA 0x00000176 #define DDRSS_PI_172_DATA 0x00001448 #define DDRSS_PI_173_DATA 0x00000176 @@ -658,14 +658,14 @@ #define DDRSS_PI_185_DATA 0x0E040100 #define DDRSS_PI_186_DATA 0x0808020E #define DDRSS_PI_187_DATA 0x00040402 -#define DDRSS_PI_188_DATA 0x000C8034 +#define DDRSS_PI_188_DATA 0x000D0035 #define DDRSS_PI_189_DATA 0x00198041 #define DDRSS_PI_190_DATA 0x00198041 #define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0002000D +#define DDRSS_PI_192_DATA 0x0002000E #define DDRSS_PI_193_DATA 0x0002014E #define DDRSS_PI_194_DATA 0x0100014E -#define DDRSS_PI_195_DATA 0x000E000E +#define DDRSS_PI_195_DATA 0x000F000F #define DDRSS_PI_196_DATA 0x014F0100 #define DDRSS_PI_197_DATA 0x0100014F #define DDRSS_PI_198_DATA 0x014F014F @@ -678,7 +678,7 @@ #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x001C000D +#define DDRSS_PI_208_DATA 0x001C000E #define DDRSS_PI_209_DATA 0x001C014E #define DDRSS_PI_210_DATA 0x0011014E #define DDRSS_PI_211_DATA 0x32000056 @@ -689,7 +689,7 @@ #define DDRSS_PI_216_DATA 0x3212005A #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x0400062B +#define DDRSS_PI_219_DATA 0x040006C9 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x1C1F0B0A #define DDRSS_PI_222_DATA 0x00001D12 @@ -699,43 +699,43 @@ #define DDRSS_PI_226_DATA 0x00001D12 #define DDRSS_PI_227_DATA 0x3C00A488 #define DDRSS_PI_228_DATA 0x13142005 -#define DDRSS_PI_229_DATA 0x0001760E -#define DDRSS_PI_230_DATA 0x00000E9C +#define DDRSS_PI_229_DATA 0x00019C0E +#define DDRSS_PI_230_DATA 0x00001018 #define DDRSS_PI_231_DATA 0x00002890 #define DDRSS_PI_232_DATA 0x000195A0 #define DDRSS_PI_233_DATA 0x00002890 #define DDRSS_PI_234_DATA 0x000195A0 -#define DDRSS_PI_235_DATA 0x0180000F +#define DDRSS_PI_235_DATA 0x01800010 #define DDRSS_PI_236_DATA 0x03030180 -#define DDRSS_PI_237_DATA 0x00271003 -#define DDRSS_PI_238_DATA 0x000186A0 +#define DDRSS_PI_237_DATA 0x002AF803 +#define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 -#define DDRSS_PI_240_DATA 0x00000064 -#define DDRSS_PI_241_DATA 0x0000000F +#define DDRSS_PI_240_DATA 0x0000006E +#define DDRSS_PI_241_DATA 0x00000010 #define DDRSS_PI_242_DATA 0x000411AB -#define DDRSS_PI_243_DATA 0x000186A0 +#define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 #define DDRSS_PI_245_DATA 0x00000A6B #define DDRSS_PI_246_DATA 0x00000180 #define DDRSS_PI_247_DATA 0x000411AB -#define DDRSS_PI_248_DATA 0x000186A0 +#define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 #define DDRSS_PI_250_DATA 0x00000A6B #define DDRSS_PI_251_DATA 0x01000180 -#define DDRSS_PI_252_DATA 0x00320040 +#define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 #define DDRSS_PI_254_DATA 0x05360040 #define DDRSS_PI_255_DATA 0x00010028 #define DDRSS_PI_256_DATA 0x05360040 #define DDRSS_PI_257_DATA 0x00000328 #define DDRSS_PI_258_DATA 0x00430043 -#define DDRSS_PI_259_DATA 0x00040404 +#define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 -#define DDRSS_PI_261_DATA 0x55003C5A +#define DDRSS_PI_261_DATA 0x55083C5A #define DDRSS_PI_262_DATA 0x5A000000 -#define DDRSS_PI_263_DATA 0x0055003C +#define DDRSS_PI_263_DATA 0x0055083C #define DDRSS_PI_264_DATA 0x3C5A0000 -#define DDRSS_PI_265_DATA 0x00005500 +#define DDRSS_PI_265_DATA 0x00005508 #define DDRSS_PI_266_DATA 0x0C3C5A00 #define DDRSS_PI_267_DATA 0x080F0E0D #define DDRSS_PI_268_DATA 0x000B0A09 @@ -879,7 +879,7 @@ #define DDRSS_PHY_105_DATA 0x0F0C2701 #define DDRSS_PHY_106_DATA 0x01000140 #define DDRSS_PHY_107_DATA 0x04000420 -#define DDRSS_PHY_108_DATA 0x00000255 +#define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 @@ -1135,7 +1135,7 @@ #define DDRSS_PHY_361_DATA 0x0F0C2701 #define DDRSS_PHY_362_DATA 0x01000140 #define DDRSS_PHY_363_DATA 0x04000420 -#define DDRSS_PHY_364_DATA 0x00000255 +#define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 @@ -1391,7 +1391,7 @@ #define DDRSS_PHY_617_DATA 0x0F0C2701 #define DDRSS_PHY_618_DATA 0x01000140 #define DDRSS_PHY_619_DATA 0x04000420 -#define DDRSS_PHY_620_DATA 0x00000255 +#define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 @@ -1647,7 +1647,7 @@ #define DDRSS_PHY_873_DATA 0x0F0C2701 #define DDRSS_PHY_874_DATA 0x01000140 #define DDRSS_PHY_875_DATA 0x04000420 -#define DDRSS_PHY_876_DATA 0x00000255 +#define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 @@ -2081,7 +2081,7 @@ #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00050000 +#define DDRSS_PHY_1310_DATA 0x00052000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 55ad6153dd6..e62f9218e83 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -30,7 +30,8 @@ compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index ca05e06e933..5a6f9b11b8e 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0 - * This file was generated on 09/25/2020 + * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1 + * This file was generated on 07/17/2022 */ #define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,10 +17,10 @@ #define DDRSS_CTL_04_DATA 0x00000000 #define DDRSS_CTL_05_DATA 0x00000000 #define DDRSS_CTL_06_DATA 0x00000000 -#define DDRSS_CTL_07_DATA 0x00002710 -#define DDRSS_CTL_08_DATA 0x000186A0 +#define DDRSS_CTL_07_DATA 0x00002AF8 +#define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 -#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_10_DATA 0x0000006E #define DDRSS_CTL_11_DATA 0x000681C8 #define DDRSS_CTL_12_DATA 0x004111C9 #define DDRSS_CTL_13_DATA 0x00000005 @@ -32,11 +33,11 @@ #define DDRSS_CTL_20_DATA 0x02011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 -#define DDRSS_CTL_23_DATA 0x0000000A -#define DDRSS_CTL_24_DATA 0x00000019 +#define DDRSS_CTL_23_DATA 0x0000000B +#define DDRSS_CTL_24_DATA 0x0000001C #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 -#define DDRSS_CTL_27_DATA 0x02020200 +#define DDRSS_CTL_27_DATA 0x03020200 #define DDRSS_CTL_28_DATA 0x00005656 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 @@ -53,7 +54,7 @@ #define DDRSS_CTL_41_DATA 0x1B60008B #define DDRSS_CTL_42_DATA 0x2000422B #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x040006DB +#define DDRSS_CTL_44_DATA 0x0400078A #define DDRSS_CTL_45_DATA 0x1E161104 #define DDRSS_CTL_46_DATA 0x10012458 #define DDRSS_CTL_47_DATA 0x1E161110 @@ -61,7 +62,7 @@ #define DDRSS_CTL_49_DATA 0x02030410 #define DDRSS_CTL_50_DATA 0x2C040500 #define DDRSS_CTL_51_DATA 0x082D2C2D -#define DDRSS_CTL_52_DATA 0x14000D0A +#define DDRSS_CTL_52_DATA 0x14000E0A #define DDRSS_CTL_53_DATA 0x04010A0A #define DDRSS_CTL_54_DATA 0x01010004 #define DDRSS_CTL_55_DATA 0x04585808 @@ -69,15 +70,15 @@ #define DDRSS_CTL_57_DATA 0x00003131 #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 -#define DDRSS_CTL_60_DATA 0x00000E08 -#define DDRSS_CTL_61_DATA 0x000000BB +#define DDRSS_CTL_60_DATA 0x00001008 +#define DDRSS_CTL_61_DATA 0x000000CE #define DDRSS_CTL_62_DATA 0x00000256 #define DDRSS_CTL_63_DATA 0x00002073 #define DDRSS_CTL_64_DATA 0x00000256 #define DDRSS_CTL_65_DATA 0x00002073 #define DDRSS_CTL_66_DATA 0x00000005 -#define DDRSS_CTL_67_DATA 0x00030000 -#define DDRSS_CTL_68_DATA 0x00950010 +#define DDRSS_CTL_67_DATA 0x00040000 +#define DDRSS_CTL_68_DATA 0x00950012 #define DDRSS_CTL_69_DATA 0x00950408 #define DDRSS_CTL_70_DATA 0x00400408 #define DDRSS_CTL_71_DATA 0x00120103 @@ -88,7 +89,7 @@ #define DDRSS_CTL_76_DATA 0x041E100B #define DDRSS_CTL_77_DATA 0x100B0401 #define DDRSS_CTL_78_DATA 0x0001041E -#define DDRSS_CTL_79_DATA 0x000F000F +#define DDRSS_CTL_79_DATA 0x00100010 #define DDRSS_CTL_80_DATA 0x02660266 #define DDRSS_CTL_81_DATA 0x02660266 #define DDRSS_CTL_82_DATA 0x03050505 @@ -111,13 +112,13 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00002EC0 -#define DDRSS_CTL_103_DATA 0x00002EC0 -#define DDRSS_CTL_104_DATA 0x00002EC0 -#define DDRSS_CTL_105_DATA 0x00002EC0 -#define DDRSS_CTL_106_DATA 0x00002EC0 +#define DDRSS_CTL_102_DATA 0x00003380 +#define DDRSS_CTL_103_DATA 0x00003380 +#define DDRSS_CTL_104_DATA 0x00003380 +#define DDRSS_CTL_105_DATA 0x00003380 +#define DDRSS_CTL_106_DATA 0x00003380 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x0000051D +#define DDRSS_CTL_108_DATA 0x000005A2 #define DDRSS_CTL_109_DATA 0x00081CC0 #define DDRSS_CTL_110_DATA 0x00081CC0 #define DDRSS_CTL_111_DATA 0x00081CC0 @@ -173,9 +174,9 @@ #define DDRSS_CTL_161_DATA 0x00000000 #define DDRSS_CTL_162_DATA 0x00000000 #define DDRSS_CTL_163_DATA 0x00000000 -#define DDRSS_CTL_164_DATA 0x000A0000 -#define DDRSS_CTL_165_DATA 0x000D0005 -#define DDRSS_CTL_166_DATA 0x000D0404 +#define DDRSS_CTL_164_DATA 0x000B0000 +#define DDRSS_CTL_165_DATA 0x000E0006 +#define DDRSS_CTL_166_DATA 0x000E0404 #define DDRSS_CTL_167_DATA 0x00D601AB #define DDRSS_CTL_168_DATA 0x10100216 #define DDRSS_CTL_169_DATA 0x01AB0216 @@ -190,15 +191,15 @@ #define DDRSS_CTL_178_DATA 0x56000000 #define DDRSS_CTL_179_DATA 0x27270056 #define DDRSS_CTL_180_DATA 0x0F0F0000 -#define DDRSS_CTL_181_DATA 0x00000000 -#define DDRSS_CTL_182_DATA 0x00840606 +#define DDRSS_CTL_181_DATA 0x16000000 +#define DDRSS_CTL_182_DATA 0x00841616 #define DDRSS_CTL_183_DATA 0x3FF43FF4 #define DDRSS_CTL_184_DATA 0x33333300 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00565600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F -#define DDRSS_CTL_189_DATA 0x06060000 +#define DDRSS_CTL_189_DATA 0x16161600 #define DDRSS_CTL_190_DATA 0x00000020 #define DDRSS_CTL_191_DATA 0x00000000 #define DDRSS_CTL_192_DATA 0x00000001 @@ -238,17 +239,17 @@ #define DDRSS_CTL_226_DATA 0x00000000 #define DDRSS_CTL_227_DATA 0x15110000 #define DDRSS_CTL_228_DATA 0x00040C18 -#define DDRSS_CTL_229_DATA 0x00000000 -#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0xF000C000 +#define DDRSS_CTL_230_DATA 0x0000F000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 -#define DDRSS_CTL_233_DATA 0x00000000 -#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0xC0000000 +#define DDRSS_CTL_234_DATA 0xF000F000 #define DDRSS_CTL_235_DATA 0x00000000 #define DDRSS_CTL_236_DATA 0x00000000 #define DDRSS_CTL_237_DATA 0x00000000 -#define DDRSS_CTL_238_DATA 0x00000000 -#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0xF000C000 +#define DDRSS_CTL_239_DATA 0x0000F000 #define DDRSS_CTL_240_DATA 0x00000000 #define DDRSS_CTL_241_DATA 0x00000000 #define DDRSS_CTL_242_DATA 0x00030000 @@ -267,7 +268,7 @@ #define DDRSS_CTL_255_DATA 0x00000000 #define DDRSS_CTL_256_DATA 0x00000000 #define DDRSS_CTL_257_DATA 0x01000200 -#define DDRSS_CTL_258_DATA 0x00320040 +#define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 #define DDRSS_CTL_261_DATA 0x00400855 @@ -276,7 +277,7 @@ #define DDRSS_CTL_264_DATA 0x00000040 #define DDRSS_CTL_265_DATA 0x006B0003 #define DDRSS_CTL_266_DATA 0x0100006B -#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_267_DATA 0x03030303 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 #define DDRSS_CTL_270_DATA 0x00000FFF @@ -398,13 +399,13 @@ #define DDRSS_CTL_386_DATA 0x00000000 #define DDRSS_CTL_387_DATA 0x3A3A1B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x00000176 +#define DDRSS_CTL_389_DATA 0x0000019C #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x00000462 -#define DDRSS_CTL_395_DATA 0x00000E9C +#define DDRSS_CTL_394_DATA 0x000004D4 +#define DDRSS_CTL_395_DATA 0x00001018 #define DDRSS_CTL_396_DATA 0x00000204 #define DDRSS_CTL_397_DATA 0x000040E6 #define DDRSS_CTL_398_DATA 0x00000200 @@ -431,7 +432,7 @@ #define DDRSS_CTL_419_DATA 0x00000000 #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 -#define DDRSS_CTL_422_DATA 0x0006001E +#define DDRSS_CTL_422_DATA 0x0007001F #define DDRSS_CTL_423_DATA 0x001B0033 #define DDRSS_CTL_424_DATA 0x001B0033 #define DDRSS_CTL_425_DATA 0x00000000 @@ -632,14 +633,14 @@ #define DDRSS_PI_160_DATA 0x00000000 #define DDRSS_PI_161_DATA 0x00010000 #define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x2B2B0100 +#define DDRSS_PI_163_DATA 0x2B2B0200 #define DDRSS_PI_164_DATA 0x00000034 #define DDRSS_PI_165_DATA 0x00000064 #define DDRSS_PI_166_DATA 0x00020064 #define DDRSS_PI_167_DATA 0x02000200 #define DDRSS_PI_168_DATA 0x48120C04 -#define DDRSS_PI_169_DATA 0x000E4812 -#define DDRSS_PI_170_DATA 0x000000BB +#define DDRSS_PI_169_DATA 0x00104812 +#define DDRSS_PI_170_DATA 0x000000CE #define DDRSS_PI_171_DATA 0x00000256 #define DDRSS_PI_172_DATA 0x00002073 #define DDRSS_PI_173_DATA 0x00000256 @@ -657,14 +658,14 @@ #define DDRSS_PI_185_DATA 0x15040000 #define DDRSS_PI_186_DATA 0x0E0E0215 #define DDRSS_PI_187_DATA 0x00040402 -#define DDRSS_PI_188_DATA 0x000C8034 +#define DDRSS_PI_188_DATA 0x000D0035 #define DDRSS_PI_189_DATA 0x00218049 #define DDRSS_PI_190_DATA 0x00218049 #define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0004000D +#define DDRSS_PI_192_DATA 0x0004000E #define DDRSS_PI_193_DATA 0x00040216 #define DDRSS_PI_194_DATA 0x01000216 -#define DDRSS_PI_195_DATA 0x000E000E +#define DDRSS_PI_195_DATA 0x000F000F #define DDRSS_PI_196_DATA 0x02170100 #define DDRSS_PI_197_DATA 0x01000217 #define DDRSS_PI_198_DATA 0x02170217 @@ -677,7 +678,7 @@ #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x0024000D +#define DDRSS_PI_208_DATA 0x0024000E #define DDRSS_PI_209_DATA 0x00240216 #define DDRSS_PI_210_DATA 0x00110216 #define DDRSS_PI_211_DATA 0x32000056 @@ -688,7 +689,7 @@ #define DDRSS_PI_216_DATA 0x3212005B #define DDRSS_PI_217_DATA 0x09000301 #define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x0400062B +#define DDRSS_PI_219_DATA 0x040006C9 #define DDRSS_PI_220_DATA 0x0A032001 #define DDRSS_PI_221_DATA 0x2C31110A #define DDRSS_PI_222_DATA 0x00002D1C @@ -698,43 +699,43 @@ #define DDRSS_PI_226_DATA 0x00002D1C #define DDRSS_PI_227_DATA 0x6001071C #define DDRSS_PI_228_DATA 0x1E202008 -#define DDRSS_PI_229_DATA 0x00017616 -#define DDRSS_PI_230_DATA 0x00000E9C +#define DDRSS_PI_229_DATA 0x00019C16 +#define DDRSS_PI_230_DATA 0x00001018 #define DDRSS_PI_231_DATA 0x000040E6 #define DDRSS_PI_232_DATA 0x000288FC #define DDRSS_PI_233_DATA 0x000040E6 #define DDRSS_PI_234_DATA 0x000288FC -#define DDRSS_PI_235_DATA 0x0266000F +#define DDRSS_PI_235_DATA 0x02660010 #define DDRSS_PI_236_DATA 0x03030266 -#define DDRSS_PI_237_DATA 0x00271003 -#define DDRSS_PI_238_DATA 0x000186A0 +#define DDRSS_PI_237_DATA 0x002AF803 +#define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 -#define DDRSS_PI_240_DATA 0x00000064 -#define DDRSS_PI_241_DATA 0x0000000F +#define DDRSS_PI_240_DATA 0x0000006E +#define DDRSS_PI_241_DATA 0x00000010 #define DDRSS_PI_242_DATA 0x000681C8 -#define DDRSS_PI_243_DATA 0x000186A0 +#define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 #define DDRSS_PI_245_DATA 0x000010A9 #define DDRSS_PI_246_DATA 0x00000266 #define DDRSS_PI_247_DATA 0x000681C8 -#define DDRSS_PI_248_DATA 0x000186A0 +#define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 #define DDRSS_PI_250_DATA 0x000010A9 #define DDRSS_PI_251_DATA 0x01000266 -#define DDRSS_PI_252_DATA 0x00320040 +#define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 #define DDRSS_PI_254_DATA 0x08550040 #define DDRSS_PI_255_DATA 0x00010040 #define DDRSS_PI_256_DATA 0x08550040 #define DDRSS_PI_257_DATA 0x00000340 #define DDRSS_PI_258_DATA 0x006B006B -#define DDRSS_PI_259_DATA 0x00040404 +#define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 -#define DDRSS_PI_261_DATA 0x55003C5A +#define DDRSS_PI_261_DATA 0x55083C5A #define DDRSS_PI_262_DATA 0x5A000000 -#define DDRSS_PI_263_DATA 0x0055003C +#define DDRSS_PI_263_DATA 0x0055083C #define DDRSS_PI_264_DATA 0x3C5A0000 -#define DDRSS_PI_265_DATA 0x00005500 +#define DDRSS_PI_265_DATA 0x00005508 #define DDRSS_PI_266_DATA 0x0C3C5A00 #define DDRSS_PI_267_DATA 0x080F0E0D #define DDRSS_PI_268_DATA 0x000B0A09 @@ -802,8 +803,8 @@ #define DDRSS_PHY_29_DATA 0x00000808 #define DDRSS_PHY_30_DATA 0x0F000000 #define DDRSS_PHY_31_DATA 0x00000F0F -#define DDRSS_PHY_32_DATA 0x10200000 -#define DDRSS_PHY_33_DATA 0x0C002007 +#define DDRSS_PHY_32_DATA 0x10400000 +#define DDRSS_PHY_33_DATA 0x0C002006 #define DDRSS_PHY_34_DATA 0x00000000 #define DDRSS_PHY_35_DATA 0x00000000 #define DDRSS_PHY_36_DATA 0x55555555 @@ -878,7 +879,7 @@ #define DDRSS_PHY_105_DATA 0x0F0C3701 #define DDRSS_PHY_106_DATA 0x01000140 #define DDRSS_PHY_107_DATA 0x0C000420 -#define DDRSS_PHY_108_DATA 0x00000322 +#define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 @@ -1058,8 +1059,8 @@ #define DDRSS_PHY_285_DATA 0x00000808 #define DDRSS_PHY_286_DATA 0x0F000000 #define DDRSS_PHY_287_DATA 0x00000F0F -#define DDRSS_PHY_288_DATA 0x10200000 -#define DDRSS_PHY_289_DATA 0x0C002007 +#define DDRSS_PHY_288_DATA 0x10400000 +#define DDRSS_PHY_289_DATA 0x0C002006 #define DDRSS_PHY_290_DATA 0x00000000 #define DDRSS_PHY_291_DATA 0x00000000 #define DDRSS_PHY_292_DATA 0x55555555 @@ -1134,7 +1135,7 @@ #define DDRSS_PHY_361_DATA 0x0F0C3701 #define DDRSS_PHY_362_DATA 0x01000140 #define DDRSS_PHY_363_DATA 0x0C000420 -#define DDRSS_PHY_364_DATA 0x00000322 +#define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 @@ -1314,8 +1315,8 @@ #define DDRSS_PHY_541_DATA 0x00000808 #define DDRSS_PHY_542_DATA 0x0F000000 #define DDRSS_PHY_543_DATA 0x00000F0F -#define DDRSS_PHY_544_DATA 0x10200000 -#define DDRSS_PHY_545_DATA 0x0C002007 +#define DDRSS_PHY_544_DATA 0x10400000 +#define DDRSS_PHY_545_DATA 0x0C002006 #define DDRSS_PHY_546_DATA 0x00000000 #define DDRSS_PHY_547_DATA 0x00000000 #define DDRSS_PHY_548_DATA 0x55555555 @@ -1390,7 +1391,7 @@ #define DDRSS_PHY_617_DATA 0x0F0C3701 #define DDRSS_PHY_618_DATA 0x01000140 #define DDRSS_PHY_619_DATA 0x0C000420 -#define DDRSS_PHY_620_DATA 0x00000322 +#define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 @@ -1570,8 +1571,8 @@ #define DDRSS_PHY_797_DATA 0x00000808 #define DDRSS_PHY_798_DATA 0x0F000000 #define DDRSS_PHY_799_DATA 0x00000F0F -#define DDRSS_PHY_800_DATA 0x10200000 -#define DDRSS_PHY_801_DATA 0x0C002007 +#define DDRSS_PHY_800_DATA 0x10400000 +#define DDRSS_PHY_801_DATA 0x0C002006 #define DDRSS_PHY_802_DATA 0x00000000 #define DDRSS_PHY_803_DATA 0x00000000 #define DDRSS_PHY_804_DATA 0x55555555 @@ -1646,7 +1647,7 @@ #define DDRSS_PHY_873_DATA 0x0F0C3701 #define DDRSS_PHY_874_DATA 0x01000140 #define DDRSS_PHY_875_DATA 0x0C000420 -#define DDRSS_PHY_876_DATA 0x00000322 +#define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 @@ -2080,7 +2081,7 @@ #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00050000 +#define DDRSS_PHY_1310_DATA 0x00052000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index e9e50538cb5..1b40cf25808 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -25,7 +25,8 @@ compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index 8d6eaa4fbbe..6986292e37c 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -159,7 +159,8 @@ compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index bc617022c18..e02b334d10e 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -30,7 +30,8 @@ compatible = "ti,am654-rproc"; reg = <0x0 0x00a90000 0x0 0x10>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, - <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; + <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi index 0c334b25781..457515b0736 100644 --- a/arch/arm/dts/keystone-clocks.dtsi +++ b/arch/arm/dts/keystone-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 clock tree * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -51,7 +48,7 @@ clocks { clock-output-names = "gemtraceclk"; }; - chipstmxptclk: chipstmxptclk { + chipstmxptclk: chipstmxptclk@2310164 { #clock-cells = <0>; compatible = "ti,keystone,pll-divider-clock"; clocks = <&mainmuxclk>; @@ -160,7 +157,7 @@ clocks { clock-output-names = "chipclk1rstiso112"; }; - clkmodrst0: clkmodrst0 { + clkmodrst0: clkmodrst0@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -171,7 +168,7 @@ clocks { }; - clkusb: clkusb { + clkusb: clkusb@2350008 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -181,7 +178,7 @@ clocks { domain-id = <0>; }; - clkaemifspi: clkaemifspi { + clkaemifspi: clkaemifspi@235000c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -192,7 +189,7 @@ clocks { }; - clkdebugsstrc: clkdebugsstrc { + clkdebugsstrc: clkdebugsstrc@2350014 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -202,7 +199,7 @@ clocks { domain-id = <1>; }; - clktetbtrc: clktetbtrc { + clktetbtrc: clktetbtrc@2350018 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -212,7 +209,7 @@ clocks { domain-id = <1>; }; - clkpa: clkpa { + clkpa: clkpa@235001c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&paclk13>; @@ -222,7 +219,7 @@ clocks { domain-id = <2>; }; - clkcpgmac: clkcpgmac { + clkcpgmac: clkcpgmac@2350020 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkpa>; @@ -232,7 +229,7 @@ clocks { domain-id = <2>; }; - clksa: clksa { + clksa: clksa@2350024 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkpa>; @@ -242,7 +239,7 @@ clocks { domain-id = <2>; }; - clkpcie: clkpcie { + clkpcie: clkpcie@2350028 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -252,7 +249,7 @@ clocks { domain-id = <3>; }; - clksr: clksr { + clksr: clksr@2350034 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1rstiso112>; @@ -262,7 +259,7 @@ clocks { domain-id = <6>; }; - clkgem0: clkgem0 { + clkgem0: clkgem0@235003c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -272,7 +269,7 @@ clocks { domain-id = <8>; }; - clkddr30: clkddr30 { + clkddr30: clkddr30@235005c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -282,7 +279,7 @@ clocks { domain-id = <16>; }; - clkwdtimer0: clkwdtimer0 { + clkwdtimer0: clkwdtimer0@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -292,7 +289,7 @@ clocks { domain-id = <0>; }; - clkwdtimer1: clkwdtimer1 { + clkwdtimer1: clkwdtimer1@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -302,7 +299,7 @@ clocks { domain-id = <0>; }; - clkwdtimer2: clkwdtimer2 { + clkwdtimer2: clkwdtimer2@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -312,7 +309,7 @@ clocks { domain-id = <0>; }; - clkwdtimer3: clkwdtimer3 { + clkwdtimer3: clkwdtimer3@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -322,7 +319,7 @@ clocks { domain-id = <0>; }; - clktimer15: clktimer15 { + clktimer15: clktimer15@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -332,7 +329,7 @@ clocks { domain-id = <0>; }; - clkuart0: clkuart0 { + clkuart0: clkuart0@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -342,7 +339,7 @@ clocks { domain-id = <0>; }; - clkuart1: clkuart1 { + clkuart1: clkuart1@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -352,7 +349,7 @@ clocks { domain-id = <0>; }; - clkaemif: clkaemif { + clkaemif: clkaemif@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkaemifspi>; @@ -362,7 +359,7 @@ clocks { domain-id = <0>; }; - clkusim: clkusim { + clkusim: clkusim@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -372,7 +369,7 @@ clocks { domain-id = <0>; }; - clki2c: clki2c { + clki2c: clki2c@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -382,7 +379,7 @@ clocks { domain-id = <0>; }; - clkspi: clkspi { + clkspi: clkspi@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkaemifspi>; @@ -392,7 +389,7 @@ clocks { domain-id = <0>; }; - clkgpio: clkgpio { + clkgpio: clkgpio@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -402,7 +399,7 @@ clocks { domain-id = <0>; }; - clkkeymgr: clkkeymgr { + clkkeymgr: clkkeymgr@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi index d56d68fe7ff..f7592155a74 100644 --- a/arch/arm/dts/keystone-k2e-clocks.dtsi +++ b/arch/arm/dts/keystone-k2e-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Keystone 2 Edison SoC specific device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -35,7 +32,7 @@ clocks { reg-names = "control"; }; - clkusb1: clkusb1 { + clkusb1: clkusb1@2350004 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -45,7 +42,7 @@ clocks { domain-id = <0>; }; - clkhyperlink0: clkhyperlink0 { + clkhyperlink0: clkhyperlink0@2350030 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -55,7 +52,7 @@ clocks { domain-id = <5>; }; - clkpcie1: clkpcie1 { + clkpcie1: clkpcie1@235006c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -65,7 +62,7 @@ clocks { domain-id = <18>; }; - clkxge: clkxge { + clkxge: clkxge@23500c8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts index bb197e133eb..ed76e56369f 100644 --- a/arch/arm/dts/keystone-k2e-evm.dts +++ b/arch/arm/dts/keystone-k2e-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Edison EVM device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -13,7 +10,7 @@ #include "keystone-k2e.dtsi" / { - compatible = "ti,k2e-evm","ti,keystone"; + compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; model = "Texas Instruments Keystone 2 Edison EVM"; soc { @@ -120,7 +117,7 @@ &spi0 { status = "okay"; - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "Micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi index b13b3c94e7f..45ebb0ac4f5 100644 --- a/arch/arm/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/dts/keystone-k2e-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 Edison Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@2a40000 { @@ -15,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; qmgrs { #address-cells = <1>; @@ -138,40 +135,40 @@ netcp: netcp@24000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; + link-interface = <1>; + phy-handle = <ðphy0>; }; gbe1: interface-1 { slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; + link-interface = <1>; + phy-handle = <ðphy1>; }; }; secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; port-4 { slave-port = <4>; - link-interface = <2>; + link-interface = <2>; }; port-5 { slave-port = <5>; - link-interface = <2>; + link-interface = <2>; }; port-6 { slave-port = <6>; - link-interface = <2>; + link-interface = <2>; }; port-7 { slave-port = <7>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi index b5d906184c1..496bb310c7d 100644 --- a/arch/arm/dts/keystone-k2e.dtsi +++ b/arch/arm/dts/keystone-k2e.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Edison soc device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ / { @@ -45,7 +42,7 @@ usb: usb@2680000 { interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - dwc3@2690000 { + usb@2690000 { interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; }; }; @@ -71,7 +68,7 @@ dma-ranges; status = "disabled"; - dwc3@25010000 { + usb@25010000 { compatible = "synopsys,dwc3"; reg = <0x25010000 0x70000>; interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; @@ -92,7 +89,7 @@ clock-names = "pcie"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; @@ -133,14 +130,14 @@ }; mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x24200f00 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2e-netcp.dtsi" }; diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts index b5b511cbd61..6376c62b6d0 100644 --- a/arch/arm/dts/keystone-k2g-evm.dts +++ b/arch/arm/dts/keystone-k2g-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Device Tree Source for K2G EVM * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -93,8 +90,8 @@ &qspi { status = "okay"; - flash0: m25p80@0 { - compatible = "s25fl512s","jedec,spi-nor"; + flash0: flash@0 { + compatible = "s25fl512s", "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts index ecca2dfac1a..cbdb6bfca8c 100644 --- a/arch/arm/dts/keystone-k2g-ice.dts +++ b/arch/arm/dts/keystone-k2g-ice.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for K2G Industrial Communication Engine EVM * @@ -38,7 +38,7 @@ &qspi { status = "okay"; - flash0: m25p80@0 { + flash0: flash@0 { compatible = "s25fl256s1", "jedec,spi-nor"; reg = <0>; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi index d76f2a1ba54..136cd20b76e 100644 --- a/arch/arm/dts/keystone-k2g-netcp.dtsi +++ b/arch/arm/dts/keystone-k2g-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for K2G Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@4020000 { @@ -17,8 +14,8 @@ qmss: qmss@4020000 { /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ clock-names = "nss_vclk"; ranges; - queue-range = <0 0x80>; - linkram0 = <0x4020000 0x7ff>; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; qmgrs { #address-cells = <1>; @@ -80,12 +77,12 @@ knav_dmas: knav_dmas@0 { dma_gbe: dma_gbe@0 { reg = <0x4010000 0x100>, - <0x4011000 0x2a0>, /* 21 Tx channels */ - <0x4012000 0x400>, /* 32 Rx channels */ - <0x4010100 0x80>, - <0x4013000 0x400>; /* 32 Rx flows */ + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; + "txsched", "rxflow"; }; }; @@ -99,9 +96,9 @@ netcp: netcp@4000000 { reg = <0x2620110 0x8>; reg-names = "efuse"; compatible = "ti,netcp-1.0"; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ clock-names = "ethss_clk"; @@ -130,7 +127,7 @@ netcp: netcp@4000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <5>; + link-interface = <5>; }; }; }; diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi index ede71181206..f12af433bb1 100644 --- a/arch/arm/dts/keystone-k2g.dtsi +++ b/arch/arm/dts/keystone-k2g.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Device Tree Source for K2G SOC * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -43,7 +40,7 @@ }; }; - gic: interrupt-controller { + gic: interrupt-controller@2561000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi index af9b7190533..4ba6912176e 100644 --- a/arch/arm/dts/keystone-k2hk-clocks.dtsi +++ b/arch/arm/dts/keystone-k2hk-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Kepler/Hawking SoC clock nodes * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -53,7 +50,7 @@ clocks { reg-names = "control"; }; - clktsip: clktsip { + clktsip: clktsip@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk16>; @@ -63,7 +60,7 @@ clocks { domain-id = <0>; }; - clksrio: clksrio { + clksrio: clksrio@235002c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1rstiso13>; @@ -73,7 +70,7 @@ clocks { domain-id = <4>; }; - clkhyperlink0: clkhyperlink0 { + clkhyperlink0: clkhyperlink0@2350030 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -83,7 +80,7 @@ clocks { domain-id = <5>; }; - clkgem1: clkgem1 { + clkgem1: clkgem1@2350040 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -93,7 +90,7 @@ clocks { domain-id = <9>; }; - clkgem2: clkgem2 { + clkgem2: clkgem2@2350044 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -103,7 +100,7 @@ clocks { domain-id = <10>; }; - clkgem3: clkgem3 { + clkgem3: clkgem3@2350048 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -113,7 +110,7 @@ clocks { domain-id = <11>; }; - clkgem4: clkgem4 { + clkgem4: clkgem4@235004c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -123,7 +120,7 @@ clocks { domain-id = <12>; }; - clkgem5: clkgem5 { + clkgem5: clkgem5@2350050 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -133,7 +130,7 @@ clocks { domain-id = <13>; }; - clkgem6: clkgem6 { + clkgem6: clkgem6@2350054 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -143,7 +140,7 @@ clocks { domain-id = <14>; }; - clkgem7: clkgem7 { + clkgem7: clkgem7@2350058 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -153,7 +150,7 @@ clocks { domain-id = <15>; }; - clkddr31: clkddr31 { + clkddr31: clkddr31@2350060 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -163,7 +160,7 @@ clocks { domain-id = <16>; }; - clktac: clktac { + clktac: clktac@2350064 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -173,7 +170,7 @@ clocks { domain-id = <17>; }; - clkrac01: clkrac01 { + clkrac01: clkrac01@2350068 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -183,7 +180,7 @@ clocks { domain-id = <17>; }; - clkrac23: clkrac23 { + clkrac23: clkrac23@235006c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -193,7 +190,7 @@ clocks { domain-id = <18>; }; - clkfftc0: clkfftc0 { + clkfftc0: clkfftc0@2350070 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -203,7 +200,7 @@ clocks { domain-id = <19>; }; - clkfftc1: clkfftc1 { + clkfftc1: clkfftc1@2350074 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -213,7 +210,7 @@ clocks { domain-id = <19>; }; - clkfftc2: clkfftc2 { + clkfftc2: clkfftc2@2350078 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -223,7 +220,7 @@ clocks { domain-id = <20>; }; - clkfftc3: clkfftc3 { + clkfftc3: clkfftc3@235007c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -233,7 +230,7 @@ clocks { domain-id = <20>; }; - clkfftc4: clkfftc4 { + clkfftc4: clkfftc4@2350080 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -243,7 +240,7 @@ clocks { domain-id = <20>; }; - clkfftc5: clkfftc5 { + clkfftc5: clkfftc5@2350084 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -253,7 +250,7 @@ clocks { domain-id = <20>; }; - clkaif: clkaif { + clkaif: clkaif@2350088 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -263,7 +260,7 @@ clocks { domain-id = <21>; }; - clktcp3d0: clktcp3d0 { + clktcp3d0: clktcp3d0@235008c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -273,7 +270,7 @@ clocks { domain-id = <22>; }; - clktcp3d1: clktcp3d1 { + clktcp3d1: clktcp3d1@2350090 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -283,7 +280,7 @@ clocks { domain-id = <22>; }; - clktcp3d2: clktcp3d2 { + clktcp3d2: clktcp3d2@2350094 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -293,7 +290,7 @@ clocks { domain-id = <23>; }; - clktcp3d3: clktcp3d3 { + clktcp3d3: clktcp3d3@2350098 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -303,7 +300,7 @@ clocks { domain-id = <23>; }; - clkvcp0: clkvcp0 { + clkvcp0: clkvcp0@235009c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -313,7 +310,7 @@ clocks { domain-id = <24>; }; - clkvcp1: clkvcp1 { + clkvcp1: clkvcp1@23500a0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -323,7 +320,7 @@ clocks { domain-id = <24>; }; - clkvcp2: clkvcp2 { + clkvcp2: clkvcp2@23500a4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -333,7 +330,7 @@ clocks { domain-id = <24>; }; - clkvcp3: clkvcp3 { + clkvcp3: clkvcp3@23500a8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -343,7 +340,7 @@ clocks { domain-id = <24>; }; - clkvcp4: clkvcp4 { + clkvcp4: clkvcp4@23500ac { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -353,7 +350,7 @@ clocks { domain-id = <25>; }; - clkvcp5: clkvcp5 { + clkvcp5: clkvcp5@23500b0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -363,7 +360,7 @@ clocks { domain-id = <25>; }; - clkvcp6: clkvcp6 { + clkvcp6: clkvcp6@23500b4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -373,7 +370,7 @@ clocks { domain-id = <25>; }; - clkvcp7: clkvcp7 { + clkvcp7: clkvcp7@23500b8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -383,7 +380,7 @@ clocks { domain-id = <25>; }; - clkbcp: clkbcp { + clkbcp: clkbcp@23500bc { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -393,7 +390,7 @@ clocks { domain-id = <26>; }; - clkdxb: clkdxb { + clkdxb: clkdxb@23500c0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -403,7 +400,7 @@ clocks { domain-id = <27>; }; - clkhyperlink1: clkhyperlink1 { + clkhyperlink1: clkhyperlink1@23500c4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -413,7 +410,7 @@ clocks { domain-id = <28>; }; - clkxge: clkxge { + clkxge: clkxge@23500c8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts index acfcaff0a84..ea53f3f6b86 100644 --- a/arch/arm/dts/keystone-k2hk-evm.dts +++ b/arch/arm/dts/keystone-k2hk-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Kepler/Hawking EVM device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -57,22 +54,22 @@ leds { compatible = "gpio-leds"; - debug1_1 { + led-debug-1-1 { label = "keystone:green:debug1"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ }; - debug1_2 { + led-debug-1-2 { label = "keystone:red:debug1"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ }; - debug2 { + led-debug-2 { label = "keystone:blue:debug2"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ }; - debug3 { + led-debug-3 { label = "keystone:blue:debug3"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ }; @@ -148,7 +145,7 @@ &spi0 { status = "okay"; - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "Micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi index 77a32c3c17e..580af633df1 100644 --- a/arch/arm/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/dts/keystone-k2hk-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 Hawking Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@2a40000 { @@ -15,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; qmgrs { #address-cells = <1>; @@ -47,6 +44,7 @@ qmss: qmss@2a40000 { "region", "push", "pop"; }; }; + queue-pools { qpend { qpend-0 { @@ -89,6 +87,7 @@ qmss: qmss@2a40000 { }; }; }; + descriptor-regions { #address-cells = <1>; #size-cells = <1>; @@ -129,7 +128,7 @@ netcp: netcp@2000000 { #size-cells = <1>; /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; + ranges = <0 0x2000000 0x100000>; clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; dma-coherent; @@ -169,11 +168,11 @@ netcp: netcp@2000000 { secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi index fc786968379..ef02f23c320 100644 --- a/arch/arm/dts/keystone-k2hk.dtsi +++ b/arch/arm/dts/keystone-k2hk.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 Kepler/Hawking soc specific device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ / { diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi index ef8464bb11f..635528064de 100644 --- a/arch/arm/dts/keystone-k2l-clocks.dtsi +++ b/arch/arm/dts/keystone-k2l-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013-2014 Texas Instruments, Inc. - * * Keystone 2 lamarr SoC clock nodes * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ clocks { @@ -44,7 +41,7 @@ clocks { reg-names = "control"; }; - clkdfeiqnsys: clkdfeiqnsys { + clkdfeiqnsys: clkdfeiqnsys@2350004 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -54,7 +51,7 @@ clocks { domain-id = <0>; }; - clkpcie1: clkpcie1 { + clkpcie1: clkpcie1@235002c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk12>; @@ -64,7 +61,7 @@ clocks { domain-id = <4>; }; - clkgem1: clkgem1 { + clkgem1: clkgem1@2350040 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -74,7 +71,7 @@ clocks { domain-id = <9>; }; - clkgem2: clkgem2 { + clkgem2: clkgem2@2350044 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -84,7 +81,7 @@ clocks { domain-id = <10>; }; - clkgem3: clkgem3 { + clkgem3: clkgem3@2350048 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk1>; @@ -94,7 +91,7 @@ clocks { domain-id = <11>; }; - clktac: clktac { + clktac: clktac@2350064 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -104,7 +101,7 @@ clocks { domain-id = <17>; }; - clkrac: clkrac { + clkrac: clkrac@2350068 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -114,7 +111,7 @@ clocks { domain-id = <17>; }; - clkdfepd0: clkdfepd0 { + clkdfepd0: clkdfepd0@235006c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -124,7 +121,7 @@ clocks { domain-id = <18>; }; - clkfftc0: clkfftc0 { + clkfftc0: clkfftc0@2350070 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -134,7 +131,7 @@ clocks { domain-id = <19>; }; - clkosr: clkosr { + clkosr: clkosr@2350088 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -144,7 +141,7 @@ clocks { domain-id = <21>; }; - clktcp3d0: clktcp3d0 { + clktcp3d0: clktcp3d0@235008c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -154,7 +151,7 @@ clocks { domain-id = <22>; }; - clktcp3d1: clktcp3d1 { + clktcp3d1: clktcp3d1@2350094 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -164,7 +161,7 @@ clocks { domain-id = <23>; }; - clkvcp0: clkvcp0 { + clkvcp0: clkvcp0@235009c { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -174,7 +171,7 @@ clocks { domain-id = <24>; }; - clkvcp1: clkvcp1 { + clkvcp1: clkvcp1@23500a0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -184,7 +181,7 @@ clocks { domain-id = <24>; }; - clkvcp2: clkvcp2 { + clkvcp2: clkvcp2@23500a4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -194,7 +191,7 @@ clocks { domain-id = <24>; }; - clkvcp3: clkvcp3 { + clkvcp3: clkvcp3@23500a8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -204,7 +201,7 @@ clocks { domain-id = <24>; }; - clkbcp: clkbcp { + clkbcp: clkbcp@23500bc { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -214,7 +211,7 @@ clocks { domain-id = <26>; }; - clkdfepd1: clkdfepd1 { + clkdfepd1: clkdfepd1@23500c0 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -224,7 +221,7 @@ clocks { domain-id = <27>; }; - clkfftc1: clkfftc1 { + clkfftc1: clkfftc1@23500c4 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -234,7 +231,7 @@ clocks { domain-id = <28>; }; - clkiqnail: clkiqnail { + clkiqnail: clkiqnail@23500c8 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&chipclk13>; @@ -244,7 +241,7 @@ clocks { domain-id = <29>; }; - clkuart2: clkuart2 { + clkuart2: clkuart2@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; @@ -254,7 +251,7 @@ clocks { domain-id = <0>; }; - clkuart3: clkuart3 { + clkuart3: clkuart3@2350000 { #clock-cells = <0>; compatible = "ti,keystone,psc-clock"; clocks = <&clkmodrst0>; diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts index ca049ba81bd..187f2caa6d3 100644 --- a/arch/arm/dts/keystone-k2l-evm.dts +++ b/arch/arm/dts/keystone-k2l-evm.dts @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Keystone 2 Lamarr EVM device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ /dts-v1/; @@ -97,7 +94,7 @@ &spi0 { status ="okay"; - nor_flash: n25q128a11@0 { + nor_flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "Micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi index 6b95284d11d..54c11288191 100644 --- a/arch/arm/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/dts/keystone-k2l-netcp.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for Keystone 2 Lamarr Netcp driver * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ */ qmss: qmss@2a40000 { @@ -15,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ qmgrs { #address-cells = <1>; @@ -73,6 +70,7 @@ qmss: qmss@2a40000 { }; }; }; + descriptor-regions { #address-cells = <1>; #size-cells = <1>; @@ -137,24 +135,24 @@ netcp: netcp@26000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; + link-interface = <1>; + phy-handle = <ðphy0>; }; gbe1: interface-1 { slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; + link-interface = <1>; + phy-handle = <ðphy1>; }; }; secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi index d681cab2594..dcc83a7ee44 100644 --- a/arch/arm/dts/keystone-k2l.dtsi +++ b/arch/arm/dts/keystone-k2l.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2014 Texas Instruments, Inc. - * * Keystone 2 Lamarr SoC specific device tree * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ */ / { @@ -31,23 +28,23 @@ soc { /include/ "keystone-k2l-clocks.dtsi" - uart2: serial@02348400 { + uart2: serial@2348400 { compatible = "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; reg = <0x02348400 0x100>; - clocks = <&clkuart2>; + clocks = <&clkuart2>; interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; }; - uart3: serial@02348800 { + uart3: serial@2348800 { compatible = "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; reg = <0x02348800 0x100>; - clocks = <&clkuart3>; + clocks = <&clkuart3>; interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; }; @@ -80,14 +77,14 @@ }; mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x26200f00 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2l-netcp.dtsi" }; diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi index 9a2e1f69bba..2afcab76d22 100644 --- a/arch/arm/dts/keystone.dtsi +++ b/arch/arm/dts/keystone.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -94,23 +91,23 @@ /include/ "keystone-clocks.dtsi" - uart0: serial@02530c00 { + uart0: serial@2530c00 { compatible = "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; + clocks = <&clkuart0>; interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; - uart1: serial@02531000 { + uart1: serial@2531000 { compatible = "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; reg = <0x02531000 0x100>; - clocks = <&clkuart1>; + clocks = <&clkuart1>; interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; }; @@ -198,7 +195,7 @@ dma-ranges; status = "disabled"; - dwc3@2690000 { + usb@2690000 { compatible = "synopsys,dwc3"; reg = <0x2690000 0x70000>; interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; @@ -206,7 +203,7 @@ }; }; - wdt: wdt@022f0080 { + wdt: wdt@22f0080 { compatible = "ti,keystone-wdt","ti,davinci-wdt"; reg = <0x022f0080 0x80>; clocks = <&clkwdtimer0>; @@ -290,7 +287,7 @@ clock-names = "pcie"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; ranges = <0x81000000 0 0 0x23250000 0 0x4000 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; diff --git a/arch/arm/dts/mt7986a-bpi-r3-emmc.dts b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts new file mode 100644 index 00000000000..4e2e5262f53 --- /dev/null +++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986a-bpi-r3-sd.dts" +#include <dt-bindings/gpio/gpio.h> +/ { + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts new file mode 100644 index 00000000000..4d12440fa3c --- /dev/null +++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "BananaPi BPi-R3"; + compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory { + label = "reset"; + gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: green { + label = "green:status"; + gpios = <&gpio 69 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: blue { + label = "blue:status"; + gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pinctrl { + spic_pins: spi1-pins-func-1 { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: spi1-pins-func-3 { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; + + pwm_pins: pwm0-pins-func-1 { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_51"; + }; + + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + conf-clk { + pins = "EMMC_CK"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-dsl { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + spi_flash_pins: spi0-pins-func-1 { + mux { + function = "flash"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_00>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_00>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <1>; + sample_sel = <0>; + + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + }; + }; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "factory"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; +}; + +&watchdog { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; diff --git a/arch/arm/dts/ns-board.dts b/arch/arm/dts/ns-board.dts new file mode 100644 index 00000000000..bc2a0dd1c96 --- /dev/null +++ b/arch/arm/dts/ns-board.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "bcm5301x.dtsi" + +/ { + /* + * The Northstar does not have a proper fallback compatible, but + * these basic chips will suffice. + */ + model = "Northstar model"; + compatible = "brcm,bcm47094", "brcm,bcm4708"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + nand-controller@18028000 { + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Same as using the bcm5301x-nand-cs0-bch1.dtsi + * include from the Linux kernel. + */ + nand-ecc-algo = "bch"; + nand-ecc-strength = <1>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "brcm,bcm947xx-cfe-partitions"; + }; + }; + }; +}; + +&uart0 { + clock-frequency = <125000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/dts/omap-gpmc-smsc911x.dtsi index ded7e8fec9e..9cf52650f07 100644 --- a/arch/arm/dts/omap-gpmc-smsc911x.dtsi +++ b/arch/arm/dts/omap-gpmc-smsc911x.dtsi @@ -8,9 +8,9 @@ / { vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a { diff --git a/arch/arm/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/dts/omap-gpmc-smsc9221.dtsi index 73e272fadc2..ac81793209c 100644 --- a/arch/arm/dts/omap-gpmc-smsc9221.dtsi +++ b/arch/arm/dts/omap-gpmc-smsc9221.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Common file for GPMC connected smsc9221 on omaps * @@ -11,9 +12,9 @@ / { vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a { diff --git a/arch/arm/dts/omap3-beagle-xm-ab.dts b/arch/arm/dts/omap3-beagle-xm-ab.dts index 7ac3bcf59d5..cb6968a8bce 100644 --- a/arch/arm/dts/omap3-beagle-xm-ab.dts +++ b/arch/arm/dts/omap3-beagle-xm-ab.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap3-beagle-xm.dts" diff --git a/arch/arm/dts/omap3-beagle-xm.dts b/arch/arm/dts/omap3-beagle-xm.dts index 8461159baf2..73152f6fa82 100644 --- a/arch/arm/dts/omap3-beagle-xm.dts +++ b/arch/arm/dts/omap3-beagle-xm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -30,26 +27,26 @@ ethernet = ðernet; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - heartbeat { + led-1 { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; - mmc { + led-2 { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - pmu_stat { + led-3 { label = "beagleboard::pmu_stat"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; @@ -360,7 +357,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/dts/omap3-beagle.dts b/arch/arm/dts/omap3-beagle.dts index 4ceee2ba199..321b6d7448a 100644 --- a/arch/arm/dts/omap3-beagle.dts +++ b/arch/arm/dts/omap3-beagle.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -31,18 +28,18 @@ leds { compatible = "gpio-leds"; - pmu_stat { + led-pmu-stat { label = "beagleboard::pmu_stat"; gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ }; - heartbeat { + led-heartbeat { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; - mmc { + led-mmc { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; diff --git a/arch/arm/dts/omap3-cpu-thermal.dtsi b/arch/arm/dts/omap3-cpu-thermal.dtsi index 235ecfd61e2..e677d1d656b 100644 --- a/arch/arm/dts/omap3-cpu-thermal.dtsi +++ b/arch/arm/dts/omap3-cpu-thermal.dtsi @@ -1,16 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC CPU thermal * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/thermal/thermal.h> -cpu_thermal: cpu_thermal { +cpu_thermal: cpu-thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ coefficients = <0 20000>; diff --git a/arch/arm/dts/omap3-evm-37xx.dts b/arch/arm/dts/omap3-evm-37xx.dts index a14303b09ae..abd403c228c 100644 --- a/arch/arm/dts/omap3-evm-37xx.dts +++ b/arch/arm/dts/omap3-evm-37xx.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -63,7 +60,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "hynix,h8kds0un0mer-4em"; + linux,mtd-name = "hynix,h8kds0un0mer-4em"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/dts/omap3-evm-processor-common.dtsi b/arch/arm/dts/omap3-evm-processor-common.dtsi index b4109f48ec1..e6ba30a2116 100644 --- a/arch/arm/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/dts/omap3-evm-processor-common.dtsi @@ -195,7 +195,7 @@ * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. */ &gpio2 { - en_usb2_port { + en-usb2-port-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ output-low; diff --git a/arch/arm/dts/omap3-evm.dts b/arch/arm/dts/omap3-evm.dts index 21a3b88aef0..f95eea63b35 100644 --- a/arch/arm/dts/omap3-evm.dts +++ b/arch/arm/dts/omap3-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -63,7 +60,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16abdhc"; + linux,mtd-name = "micron,mt29f2g16abdhc"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/dts/omap3-igep.dtsi b/arch/arm/dts/omap3-igep.dtsi index f33cc80c9db..21920261046 100644 --- a/arch/arm/dts/omap3-igep.dtsi +++ b/arch/arm/dts/omap3-igep.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Common device tree for IGEP boards based on AM/DM37x * - * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com> + * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; @@ -114,7 +111,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29c4g96maz"; + linux,mtd-name = "micron,mt29c4g96maz"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi index d62481dacda..73d8f471b9e 100644 --- a/arch/arm/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/dts/omap3-igep0020-common.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Common Device Tree Source for IGEPv2 * - * Copyright (C) 2014 Javier Martinez Canillas <javier@osg.samsung.com> + * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org> * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "omap3-igep.dtsi" diff --git a/arch/arm/dts/omap3-igep0020.dts b/arch/arm/dts/omap3-igep0020.dts index 33d6b4ead09..cf3ac847431 100644 --- a/arch/arm/dts/omap3-igep0020.dts +++ b/arch/arm/dts/omap3-igep0020.dts @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) * - * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com> + * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include "omap3-igep0020-common.dtsi" diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi index 4043ecb3801..622ee458b60 100644 --- a/arch/arm/dts/omap3.dtsi +++ b/arch/arm/dts/omap3.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> @@ -356,7 +353,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; diff --git a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi index 858aa0796ec..5e9d1afcd42 100644 --- a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP34XX/OMAP36XX clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &cm_clocks { security_l4_ick2: security_l4_ick2 { diff --git a/arch/arm/dts/omap34xx.dtsi b/arch/arm/dts/omap34xx.dtsi index a703d09736c..28ca9c3897c 100644 --- a/arch/arm/dts/omap34xx.dtsi +++ b/arch/arm/dts/omap34xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP34xx/OMAP35xx SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/media/omap3-isp.h> diff --git a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 15d18669000..9974d522697 100644 --- a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &prm_clocks { corex2_d3_fck: corex2_d3_fck { diff --git a/arch/arm/dts/omap36xx-clocks.dtsi b/arch/arm/dts/omap36xx-clocks.dtsi index a21d1f02126..e66fc57ec35 100644 --- a/arch/arm/dts/omap36xx-clocks.dtsi +++ b/arch/arm/dts/omap36xx-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP36xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &cm_clocks { dpll4_ck: dpll4_ck@d00 { diff --git a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi index 1a4fbdf0d9c..945537aee3c 100644 --- a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP34xx/OMAP36xx clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &cm_clocks { ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { diff --git a/arch/arm/dts/omap36xx.dtsi b/arch/arm/dts/omap36xx.dtsi index 52e1b8ce0f5..e5f0207a474 100644 --- a/arch/arm/dts/omap36xx.dtsi +++ b/arch/arm/dts/omap36xx.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/bus/ti-sysc.h> diff --git a/arch/arm/dts/omap3xxx-clocks.dtsi b/arch/arm/dts/omap3xxx-clocks.dtsi index 9bd91641aa7..685c82a9d03 100644 --- a/arch/arm/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/dts/omap3xxx-clocks.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 clock data * * Copyright (C) 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ &prm_clocks { virt_16_8m_ck: virt_16_8m_ck { diff --git a/arch/arm/dts/omap4-cpu-thermal.dtsi b/arch/arm/dts/omap4-cpu-thermal.dtsi index ab7f87ae96f..801b4f10350 100644 --- a/arch/arm/dts/omap4-cpu-thermal.dtsi +++ b/arch/arm/dts/omap4-cpu-thermal.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4/5 SoC CPU thermal * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> @@ -16,20 +13,20 @@ cpu_thermal: cpu_thermal { polling-delay = <1000>; /* milliseconds */ /* sensor ID */ - thermal-sensors = <&bandgap 0>; + thermal-sensors = <&bandgap 0>; cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; + cpu_alert0: cpu_alert { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <125000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; cpu_cooling_maps: cooling-maps { map0 { diff --git a/arch/arm/dts/omap4-l4.dtsi b/arch/arm/dts/omap4-l4.dtsi index 424a6946608..84d92b8d11c 100644 --- a/arch/arm/dts/omap4-l4.dtsi +++ b/arch/arm/dts/omap4-l4.dtsi @@ -599,11 +599,11 @@ #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { + mbox_ipu: mbox-ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; diff --git a/arch/arm/dts/omap4-panda-common.dtsi b/arch/arm/dts/omap4-panda-common.dtsi index c124b20d463..6174fbe2803 100644 --- a/arch/arm/dts/omap4-panda-common.dtsi +++ b/arch/arm/dts/omap4-panda-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/input/input.h> #include "elpida_ecb240abacn.dtsi" @@ -29,13 +29,13 @@ &led_wkgpio_pins >; - heartbeat { + led-heartbeat { label = "pandaboard::status1"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - mmc { + led-mmc { label = "pandaboard::status2"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; @@ -538,7 +538,7 @@ #address-cells = <1>; #size-cells = <0>; - ethernet: usbether@1 { + ethernet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; }; diff --git a/arch/arm/dts/omap4-panda-es.dts b/arch/arm/dts/omap4-panda-es.dts index 9dd307b5260..35e4f345a13 100644 --- a/arch/arm/dts/omap4-panda-es.dts +++ b/arch/arm/dts/omap4-panda-es.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -63,10 +63,10 @@ &led_wkgpio_pins >; - heartbeat { + led-heartbeat { gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; }; - mmc { + led-mmc { gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/dts/omap4-panda.dts b/arch/arm/dts/omap4-panda.dts index fb2f47717b4..529d5bcceaa 100644 --- a/arch/arm/dts/omap4-panda.dts +++ b/arch/arm/dts/omap4-panda.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/omap4-sdp-es23plus.dts b/arch/arm/dts/omap4-sdp-es23plus.dts index 42154520d38..869f6279b5b 100644 --- a/arch/arm/dts/omap4-sdp-es23plus.dts +++ b/arch/arm/dts/omap4-sdp-es23plus.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap4-sdp.dts" diff --git a/arch/arm/dts/omap4-sdp.dts b/arch/arm/dts/omap4-sdp.dts index 28b989cfdb4..9e976140f34 100644 --- a/arch/arm/dts/omap4-sdp.dts +++ b/arch/arm/dts/omap4-sdp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -45,58 +45,60 @@ regulator-boot-on; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - debug0 { + + led-1 { label = "omap4:green:debug0"; gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ }; - debug1 { + led-2 { label = "omap4:green:debug1"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ }; - debug2 { + led-3 { label = "omap4:green:debug2"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ }; - debug3 { + led-4 { label = "omap4:green:debug3"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ }; - debug4 { + led-5 { label = "omap4:green:debug4"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ }; - user1 { + led-6 { label = "omap4:blue:user"; gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ }; - user2 { + led-7 { label = "omap4:red:user"; gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ }; - user3 { + led-8 { label = "omap4:green:user"; gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - kpad { + + led-9 { label = "omap4::keypad"; pwms = <&twl_pwm 0 7812500>; max-brightness = <127>; }; - charging { + led-10 { label = "omap4:green:chrg"; pwms = <&twl_pwmled 0 7812500>; max-brightness = <255>; @@ -428,7 +430,7 @@ /* * Temperature Sensor - * http://www.ti.com/lit/ds/symlink/tmp105.pdf + * https://www.ti.com/lit/ds/symlink/tmp105.pdf */ tmp105@48 { compatible = "ti,tmp105"; @@ -453,7 +455,7 @@ /* * 3-Axis Digital Compass - * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf + * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf */ hmc5843@1e { compatible = "honeywell,hmc5843"; @@ -662,8 +664,9 @@ }; }; - lcd0: display { + lcd0: panel@0 { compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; label = "lcd0"; reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ @@ -687,8 +690,9 @@ }; }; - lcd1: display { + lcd1: panel@0 { compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; label = "lcd1"; reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ diff --git a/arch/arm/dts/omap4.dtsi b/arch/arm/dts/omap4.dtsi index 763bdea8c82..d1ab5f4db83 100644 --- a/arch/arm/dts/omap4.dtsi +++ b/arch/arm/dts/omap4.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/bus/ti-sysc.h> @@ -71,7 +71,7 @@ interrupt-parent = <&gic>; }; - L2: l2-cache-controller@48242000 { + L2: cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; cache-unified; @@ -389,7 +389,7 @@ status = "disabled"; }; - target-module@56000000 { + sgx_module: target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5600fe00 0x4>, <0x5600fe10 0x4>; @@ -551,6 +551,9 @@ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; @@ -583,6 +586,9 @@ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/dts/omap443x-clocks.dtsi b/arch/arm/dts/omap443x-clocks.dtsi index 39297868ec8..581e088231b 100644 --- a/arch/arm/dts/omap443x-clocks.dtsi +++ b/arch/arm/dts/omap443x-clocks.dtsi @@ -8,6 +8,7 @@ bandgap_fclk: bandgap_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; + clock-output-names = "bandgap_fclk"; clocks = <&sys_32k_ck>; ti,bit-shift = <8>; reg = <0x1888>; diff --git a/arch/arm/dts/omap443x.dtsi b/arch/arm/dts/omap443x.dtsi index cbcdcb4e7d1..a7ee13b946c 100644 --- a/arch/arm/dts/omap443x.dtsi +++ b/arch/arm/dts/omap443x.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP443x SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap4.dtsi" diff --git a/arch/arm/dts/omap4460.dtsi b/arch/arm/dts/omap4460.dtsi index 2223dc0d63c..21ddff965c8 100644 --- a/arch/arm/dts/omap4460.dtsi +++ b/arch/arm/dts/omap4460.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4460 SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap4.dtsi" diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi deleted file mode 100644 index 1eedd8d706a..00000000000 --- a/arch/arm/dts/omap5-board-common.dtsi +++ /dev/null @@ -1,762 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -#include "omap5.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - aliases { - display0 = &hdmi0; - }; - - chosen { - stdout-path = &uart3; - }; - - vmain: fixedregulator-vmain { - compatible = "regulator-fixed"; - regulator-name = "vmain"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vsys_cobra: fixedregulator-vsys_cobra { - compatible = "regulator-fixed"; - regulator-name = "vsys_cobra"; - vin-supply = <&vmain>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdds_1v8_main: fixedregulator-vdds_1v8_main { - compatible = "regulator-fixed"; - regulator-name = "vdds_1v8_main"; - vin-supply = <&smps7_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vmmcsd_fixed: fixedregulator-mmcsd { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - mmc3_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&clk32kgaudio>; - clock-names = "ext_clock"; - }; - - vmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "vmmcsdio_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */ - enable-active-high; - startup-delay-us = <70000>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_pins>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ - clocks = <&auxclk1_ck>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; - - /* HS USB Host PHY on PORT 3 */ - hsusb3_phy: hsusb3_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ - #phy-cells = <0>; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - /* gpios defined in the board specific dts */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "b"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "omap5-uevm"; - - ti,jack-detection; - ti,mclk-freq = <19200000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; -}; - -&gpio8 { - /* TI trees use GPIO instead of msecure, see also muxing */ - p234 { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "gpio8_234/msecure"; - }; -}; - -&omap5_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_pins - &led_gpio_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ - OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ - OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ - OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ - OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ - OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ - OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ - OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ - OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ - OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ - OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ - OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ - OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ - OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ - OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ - OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ - OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ - OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ - OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ - OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ - OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ - OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ - >; - }; - - /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas_msecure_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ - >; - }; - - usbhost_pins: pinmux_usbhost_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ - OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ - - OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ - OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ - - OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ - OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ - >; - }; - - led_gpio_pins: pinmux_led_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ - OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ - OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ - OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ - >; - }; - - uart5_pins: pinmux_uart5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ - OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ - OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ - OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ - OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ - OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ - >; - }; -}; - -&omap5_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = < - &usbhost_wkup_pins - >; - - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { - pinctrl-single,pins = < - /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ - OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) - >; - }; - - usbhost_wkup_pins: pinmux_usbhost_wkup_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ - >; - }; - - wlcore_irq_pin: pinmux_wlcore_irq_pin { - pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ - >; - }; -}; - -&mmc1 { - vmmc-supply = <&ldo9_reg>; - bus-width = <4>; -}; - -&mmc2 { - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - vmmc-supply = <&vmmcsdio_fixed>; - mmc-pwrseq = <&mmc3_pwrseq>; - bus-width = <4>; - non-removable; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x16a>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wlcore_irq_pin>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ - ref-clock-frequency = <26000000>; - }; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - status = "disabled"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - palmas: palmas@48 { - compatible = "ti,palmas"; - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; - reg = <0x48>; - interrupt-controller; - #interrupt-cells = <2>; - ti,system-power-controller; - ti,mux-pad1 = <0xa1>; - ti,mux-pad2 = <0x1b>; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; - - palmas_gpio: gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb3: palmas_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - ti,wakeup; - id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; - }; - - clk32kgaudio: palmas_clk32k@1 { - compatible = "ti,palmas-clk32kgaudio"; - #clock-cells = <0>; - }; - - rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 IRQ_TYPE_NONE>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - - gpadc: gpadc { - compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; - #io-channel-cells = <1>; - ti,channel0-current-microamp = <5>; - ti,channel3-current-microamp = <10>; - }; - - palmas_pmic { - compatible = "ti,palmas-pmic"; - interrupt-parent = <&palmas>; - interrupts = <14 IRQ_TYPE_NONE>; - interrupt-names = "short-irq"; - - ti,ldo6-vibrator; - - smps123-in-supply = <&vsys_cobra>; - smps45-in-supply = <&vsys_cobra>; - smps6-in-supply = <&vsys_cobra>; - smps7-in-supply = <&vsys_cobra>; - smps8-in-supply = <&vsys_cobra>; - smps9-in-supply = <&vsys_cobra>; - smps10_out2-in-supply = <&vsys_cobra>; - smps10_out1-in-supply = <&vsys_cobra>; - ldo1-in-supply = <&vsys_cobra>; - ldo2-in-supply = <&vsys_cobra>; - ldo3-in-supply = <&vdds_1v8_main>; - ldo4-in-supply = <&vdds_1v8_main>; - ldo5-in-supply = <&vsys_cobra>; - ldo6-in-supply = <&vdds_1v8_main>; - ldo7-in-supply = <&vsys_cobra>; - ldo8-in-supply = <&vsys_cobra>; - ldo9-in-supply = <&vmmcsd_fixed>; - ldoln-in-supply = <&vsys_cobra>; - ldousb-in-supply = <&vsys_cobra>; - - regulators { - smps123_reg: smps123 { - /* VDD_OPP_MPU */ - regulator-name = "smps123"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_OPP_MM */ - regulator-name = "smps45"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_DDR3 - over VDD_SMPS6 */ - regulator-name = "smps6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps7_reg: smps7 { - /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ - regulator-name = "smps7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps8_reg: smps8 { - /* VDD_OPP_CORE */ - regulator-name = "smps8"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1310000>; - regulator-always-on; - regulator-boot-on; - }; - - smps9_reg: smps9 { - /* VDDA_2v1_AUD over VDD_2v1 */ - regulator-name = "smps9"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - ti,smps-range = <0x80>; - }; - - smps10_out2_reg: smps10_out2 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - smps10_out1_reg: smps10_out1 { - /* VBUS_5V_OTG */ - regulator-name = "smps10_out1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ldo1_reg: ldo1 { - /* VDDAPHY_CAM: vdda_csiport */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2_reg: ldo2 { - /* VCC_2V8_DISP: Does not go anywhere */ - regulator-name = "ldo2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - /* Unused */ - status = "disabled"; - }; - - ldo3_reg: ldo3 { - /* VDDAPHY_MDM: vdda_lli */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - /* Only if Modem is used */ - status = "disabled"; - }; - - ldo4_reg: ldo4 { - /* VDDAPHY_DISP: vdda_dsiport/hdmi */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PHY: usb/sata/hdmi.. */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6_reg: ldo6 { - /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ - regulator-name = "ldo6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo7_reg: ldo7 { - /* VDD_VPP: vpp1 */ - regulator-name = "ldo7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - /* Only for efuse reprograming! */ - status = "disabled"; - }; - - ldo8_reg: ldo8 { - /* VDD_3v0: Does not go anywhere */ - regulator-name = "ldo8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - /* Unused */ - status = "disabled"; - }; - - ldo9_reg: ldo9 { - /* VCC_DV_SDIO: vdds_sdcard */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3250000>; - regulator-max-microvolt = <3250000>; - regulator-always-on; - regulator-boot-on; - }; - - regen3_reg: regen3 { - /* REGEN3 controls LDO9 supply to card */ - regulator-name = "regen3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - palmas_power_button: palmas_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&palmas>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - #clock-cells = <0>; - reg = <0x4b>; - - pinctrl-names = "default"; - pinctrl-0 = <&twl6040_pins>; - - /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */ - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>; - - /* audpwron gpio defined in the board specific dts */ - - vio-supply = <&smps7_reg>; - v2v1-supply = <&smps9_reg>; - enable-active-high; - - clocks = <&clk32kgaudio>, <&fref_xtal_ck>; - clock-names = "clk32k", "mclk"; - }; -}; - -&mcpdm_module { - /* Module on the SoC needs external clock from the PMIC */ - pinctrl-names = "default"; - pinctrl-0 = <&mcpdm_pins>; - status = "okay"; -}; - -&mcpdm { - clocks = <&twl6040>; - clock-names = "pdmclk"; -}; - -&mcbsp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp1_pins>; - status = "okay"; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&usbhshost { - port2-mode = "ehci-hsic"; - port3-mode = "ehci-hsic"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy &hsusb3_phy>; -}; - -&usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; -}; - -&dwc3 { - extcon = <&extcon_usb3>; - dr_mode = "otg"; -}; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&omap5_pmx_core 0x19c>; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; -}; - -&cpu0 { - cpu0-supply = <&smps123_reg>; -}; - -&dss { - status = "okay"; -}; - -&hdmi { - status = "okay"; - - /* vdda-supply populated in board specific dts file */ - - pinctrl-names = "default"; - pinctrl-0 = <&dss_hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; diff --git a/arch/arm/dts/omap5-core-thermal.dtsi b/arch/arm/dts/omap5-core-thermal.dtsi index de8a3d456cf..e0d8e39a001 100644 --- a/arch/arm/dts/omap5-core-thermal.dtsi +++ b/arch/arm/dts/omap5-core-thermal.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP543x SoC CORE thermal * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/dts/omap5-gpu-thermal.dtsi b/arch/arm/dts/omap5-gpu-thermal.dtsi index bc3090f2e84..1b4b7d9136c 100644 --- a/arch/arm/dts/omap5-gpu-thermal.dtsi +++ b/arch/arm/dts/omap5-gpu-thermal.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP543x SoC GPU thermal * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h> diff --git a/arch/arm/dts/omap5-l4-abe.dtsi b/arch/arm/dts/omap5-l4-abe.dtsi deleted file mode 100644 index f73eea0b434..00000000000 --- a/arch/arm/dts/omap5-l4-abe.dtsi +++ /dev/null @@ -1,449 +0,0 @@ -&l4_abe { /* 0x40100000 */ - compatible = "ti,omap5-l4-abe", "simple-bus"; - reg = <0x40100000 0x400>, - <0x40100400 0x400>; - reg-names = "la", "ap"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ - <0x49000000 0x49000000 0x100000>; - segment@0 { /* 0x40100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = - /* CPU to L4 ABE mapping */ - <0x00000000 0x00000000 0x000400>, /* ap 0 */ - <0x00000400 0x00000400 0x000400>, /* ap 1 */ - <0x00022000 0x00022000 0x001000>, /* ap 2 */ - <0x00023000 0x00023000 0x001000>, /* ap 3 */ - <0x00024000 0x00024000 0x001000>, /* ap 4 */ - <0x00025000 0x00025000 0x001000>, /* ap 5 */ - <0x00026000 0x00026000 0x001000>, /* ap 6 */ - <0x00027000 0x00027000 0x001000>, /* ap 7 */ - <0x00028000 0x00028000 0x001000>, /* ap 8 */ - <0x00029000 0x00029000 0x001000>, /* ap 9 */ - <0x0002a000 0x0002a000 0x001000>, /* ap 10 */ - <0x0002b000 0x0002b000 0x001000>, /* ap 11 */ - <0x0002e000 0x0002e000 0x001000>, /* ap 12 */ - <0x0002f000 0x0002f000 0x001000>, /* ap 13 */ - <0x00030000 0x00030000 0x001000>, /* ap 14 */ - <0x00031000 0x00031000 0x001000>, /* ap 15 */ - <0x00032000 0x00032000 0x001000>, /* ap 16 */ - <0x00033000 0x00033000 0x001000>, /* ap 17 */ - <0x00038000 0x00038000 0x001000>, /* ap 18 */ - <0x00039000 0x00039000 0x001000>, /* ap 19 */ - <0x0003a000 0x0003a000 0x001000>, /* ap 20 */ - <0x0003b000 0x0003b000 0x001000>, /* ap 21 */ - <0x0003c000 0x0003c000 0x001000>, /* ap 22 */ - <0x0003d000 0x0003d000 0x001000>, /* ap 23 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 24 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 25 */ - <0x00080000 0x00080000 0x010000>, /* ap 26 */ - <0x00080000 0x00080000 0x001000>, /* ap 27 */ - <0x000a0000 0x000a0000 0x010000>, /* ap 28 */ - <0x000a0000 0x000a0000 0x001000>, /* ap 29 */ - <0x000c0000 0x000c0000 0x010000>, /* ap 30 */ - <0x000c0000 0x000c0000 0x001000>, /* ap 31 */ - <0x000f1000 0x000f1000 0x001000>, /* ap 32 */ - <0x000f2000 0x000f2000 0x001000>, /* ap 33 */ - - /* L3 to L4 ABE mapping */ - <0x49000000 0x49000000 0x000400>, /* ap 0 */ - <0x49000400 0x49000400 0x000400>, /* ap 1 */ - <0x49022000 0x49022000 0x001000>, /* ap 2 */ - <0x49023000 0x49023000 0x001000>, /* ap 3 */ - <0x49024000 0x49024000 0x001000>, /* ap 4 */ - <0x49025000 0x49025000 0x001000>, /* ap 5 */ - <0x49026000 0x49026000 0x001000>, /* ap 6 */ - <0x49027000 0x49027000 0x001000>, /* ap 7 */ - <0x49028000 0x49028000 0x001000>, /* ap 8 */ - <0x49029000 0x49029000 0x001000>, /* ap 9 */ - <0x4902a000 0x4902a000 0x001000>, /* ap 10 */ - <0x4902b000 0x4902b000 0x001000>, /* ap 11 */ - <0x4902e000 0x4902e000 0x001000>, /* ap 12 */ - <0x4902f000 0x4902f000 0x001000>, /* ap 13 */ - <0x49030000 0x49030000 0x001000>, /* ap 14 */ - <0x49031000 0x49031000 0x001000>, /* ap 15 */ - <0x49032000 0x49032000 0x001000>, /* ap 16 */ - <0x49033000 0x49033000 0x001000>, /* ap 17 */ - <0x49038000 0x49038000 0x001000>, /* ap 18 */ - <0x49039000 0x49039000 0x001000>, /* ap 19 */ - <0x4903a000 0x4903a000 0x001000>, /* ap 20 */ - <0x4903b000 0x4903b000 0x001000>, /* ap 21 */ - <0x4903c000 0x4903c000 0x001000>, /* ap 22 */ - <0x4903d000 0x4903d000 0x001000>, /* ap 23 */ - <0x4903e000 0x4903e000 0x001000>, /* ap 24 */ - <0x4903f000 0x4903f000 0x001000>, /* ap 25 */ - <0x49080000 0x49080000 0x010000>, /* ap 26 */ - <0x49080000 0x49080000 0x001000>, /* ap 27 */ - <0x490a0000 0x490a0000 0x010000>, /* ap 28 */ - <0x490a0000 0x490a0000 0x001000>, /* ap 29 */ - <0x490c0000 0x490c0000 0x010000>, /* ap 30 */ - <0x490c0000 0x490c0000 0x001000>, /* ap 31 */ - <0x490f1000 0x490f1000 0x001000>, /* ap 32 */ - <0x490f2000 0x490f2000 0x001000>; /* ap 33 */ - - target-module@22000 { /* 0x40122000, ap 2 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2208c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>, - <0x49022000 0x49022000 0x1000>; - - mcbsp1: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49022000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@24000 { /* 0x40124000, ap 4 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2408c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>, - <0x49024000 0x49024000 0x1000>; - - mcbsp2: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49024000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@26000 { /* 0x40126000, ap 6 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2608c 0x4>; - reg-names = "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>, - <0x49026000 0x49026000 0x1000>; - - mcbsp3: mcbsp@0 { - compatible = "ti,omap4-mcbsp"; - reg = <0x0 0xff>, /* MPU private access */ - <0x49026000 0xff>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common"; - ti,buffer-size = <128>; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - }; - - target-module@28000 { /* 0x40128000, ap 8 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>, - <0x49028000 0x49028000 0x1000>; - }; - - target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>, - <0x4902a000 0x4902a000 0x1000>; - }; - - target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2e000 0x4>, - <0x2e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2e000 0x1000>, - <0x4902e000 0x4902e000 0x1000>; - - dmic: dmic@0 { - compatible = "ti,omap4-dmic"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 67>; - dma-names = "up_link"; - status = "disabled"; - }; - }; - - target-module@30000 { /* 0x40130000, ap 14 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x30000 0x1000>, - <0x49030000 0x49030000 0x1000>; - }; - - mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>, - <0x49032000 0x49032000 0x1000>; - - /* Must be only enabled for boards with pdmclk wired */ - status = "disabled"; - - mcpdm: mcpdm@0 { - compatible = "ti,omap4-mcpdm"; - reg = <0x0 0x7f>, /* MPU private access */ - <0x49032000 0x7f>; /* L3 Interconnect */ - reg-names = "mpu", "dma"; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; - }; - }; - - target-module@38000 { /* 0x40138000, ap 18 12.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x38000 0x4>, - <0x38010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x38000 0x1000>, - <0x49038000 0x49038000 0x1000>; - - timer5: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3a000 0x4>, - <0x3a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3a000 0x1000>, - <0x4903a000 0x4903a000 0x1000>; - - timer6: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3c000 0x4>, - <0x3c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3c000 0x1000>, - <0x4903c000 0x4903c000 0x1000>; - - timer7: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - }; - }; - - target-module@3e000 { /* 0x4013e000, ap 24 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>, - <0x4903e000 0x4903e000 0x1000>; - - timer8: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>, - <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-dsp; - ti,timer-pwm; - }; - }; - - target-module@80000 { /* 0x40180000, ap 26 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x10000>, - <0x49080000 0x49080000 0x10000>; - }; - - target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa0000 0x10000>, - <0x490a0000 0x490a0000 0x10000>; - }; - - target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc0000 0x10000>, - <0x490c0000 0x490c0000 0x10000>; - }; - - target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xf1000 0x4>, - <0xf1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ - clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf1000 0x1000>, - <0x490f1000 0x490f1000 0x1000>; - }; - }; -}; diff --git a/arch/arm/dts/omap5-l4.dtsi b/arch/arm/dts/omap5-l4.dtsi deleted file mode 100644 index 8582016d65d..00000000000 --- a/arch/arm/dts/omap5-l4.dtsi +++ /dev/null @@ -1,2437 +0,0 @@ -&l4_cfg { /* 0x4a000000 */ - compatible = "ti,omap5-l4-cfg", "simple-bus"; - reg = <0x4a000000 0x800>, - <0x4a000800 0x800>, - <0x4a001000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ - <0x00080000 0x4a080000 0x080000>, /* segment 1 */ - <0x00100000 0x4a100000 0x080000>, /* segment 2 */ - <0x00180000 0x4a180000 0x080000>, /* segment 3 */ - <0x00200000 0x4a200000 0x080000>, /* segment 4 */ - <0x00280000 0x4a280000 0x080000>, /* segment 5 */ - <0x00300000 0x4a300000 0x080000>; /* segment 6 */ - - segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00002000 0x00002000 0x001000>, /* ap 3 */ - <0x00003000 0x00003000 0x001000>, /* ap 4 */ - <0x00004000 0x00004000 0x001000>, /* ap 5 */ - <0x00005000 0x00005000 0x001000>, /* ap 6 */ - <0x00056000 0x00056000 0x001000>, /* ap 7 */ - <0x00057000 0x00057000 0x001000>, /* ap 8 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ - <0x00058000 0x00058000 0x001000>, /* ap 10 */ - <0x00062000 0x00062000 0x001000>, /* ap 11 */ - <0x00063000 0x00063000 0x001000>, /* ap 12 */ - <0x00008000 0x00008000 0x002000>, /* ap 21 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ - <0x00066000 0x00066000 0x001000>, /* ap 23 */ - <0x00067000 0x00067000 0x001000>, /* ap 24 */ - <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ - <0x00060000 0x00060000 0x001000>, /* ap 70 */ - <0x00064000 0x00064000 0x001000>, /* ap 71 */ - <0x00065000 0x00065000 0x001000>, /* ap 72 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ - <0x00070000 0x00070000 0x004000>, /* ap 79 */ - <0x00074000 0x00074000 0x001000>, /* ap 80 */ - <0x00075000 0x00075000 0x001000>, /* ap 81 */ - <0x00076000 0x00076000 0x001000>, /* ap 82 */ - <0x00020000 0x00020000 0x020000>, /* ap 109 */ - <0x00040000 0x00040000 0x001000>, /* ap 110 */ - <0x00059000 0x00059000 0x001000>; /* ap 111 */ - - target-module@2000 { /* 0x4a002000, ap 3 44.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x2000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - - scm_core: scm@0 { - compatible = "ti,omap5-scm-core", "simple-bus"; - reg = <0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - scm_padconf_core: scm@800 { - compatible = "ti,omap5-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x800>; - - omap5_pmx_core: pinmux@40 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x40 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0xec>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0xec>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap5", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - }; - - target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x4000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - cm_core_aon: cm_core_aon@0 { - compatible = "ti,omap5-cm-core-aon", - "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - }; - - target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x8000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x2000>; - - cm_core: cm_core@0 { - compatible = "ti,omap5-cm-core", "simple-bus"; - reg = <0x0 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - }; - - target-module@20000 { /* 0x4a020000, ap 109 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss"; - reg = <0x20000 0x4>, - <0x20010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x20000>; - - usb3: omap_dwc3@0 { - compatible = "ti,dwc3"; - reg = <0x0 0x10000>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges = <0 0 0x20000>; - dwc3: dwc3@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "peripheral"; - }; - }; - }; - - target-module@56000 { /* 0x4a056000, ap 7 02.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x56000 0x4>, - <0x5602c 0x4>, - <0x56028 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ - clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x56000 0x1000>; - - sdma: dma-controller@0 { - compatible = "ti,omap4430-sdma", "ti,omap-sdma"; - reg = <0x0 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - }; - }; - - target-module@58000 { /* 0x4a058000, ap 10 06.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00058000 0x00001000>, - <0x00001000 0x00059000 0x00001000>, - <0x00002000 0x0005a000 0x00001000>, - <0x00003000 0x0005b000 0x00001000>; - }; - - target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5e000 0x2000>; - }; - - target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_tll_hs"; - reg = <0x62000 0x4>, - <0x62010 0x4>, - <0x62014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x62000 0x1000>; - - usbhstll: usbhstll@0 { - compatible = "ti,usbhs-tll"; - reg = <0x0 0x1000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_host_hs"; - reg = <0x64000 0x4>, - <0x64010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x64000 0x1000>; - - usbhshost: usbhshost@0 { - compatible = "ti,usbhs-host"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000>; - clocks = <&l3init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@800 { - compatible = "ti,ohci-omap3"; - reg = <0x800 0x400>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - remote-wakeup-connected; - }; - - usbhsehci: ehci@c00 { - compatible = "ti,ehci-omap"; - reg = <0xc00 0x400>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - - target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66000 0x4>, - <0x66010 0x4>, - <0x66014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ - clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_dsp 1>; - reset-names = "rstctrl"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - mmu_dsp: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <0>; - }; - }; - - target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x4000>; - }; - - target-module@75000 { /* 0x4a075000, ap 81 32.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x75000 0x1000>; - }; - }; - - segment@80000 { /* 0x4a080000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ - <0x0005a000 0x000da000 0x001000>, /* ap 14 */ - <0x0005b000 0x000db000 0x001000>, /* ap 15 */ - <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ - <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ - <0x0005e000 0x000de000 0x001000>, /* ap 18 */ - <0x00060000 0x000e0000 0x001000>, /* ap 19 */ - <0x00061000 0x000e1000 0x001000>, /* ap 20 */ - <0x00074000 0x000f4000 0x001000>, /* ap 25 */ - <0x00075000 0x000f5000 0x001000>, /* ap 26 */ - <0x00076000 0x000f6000 0x001000>, /* ap 27 */ - <0x00077000 0x000f7000 0x001000>, /* ap 28 */ - <0x00036000 0x000b6000 0x001000>, /* ap 65 */ - <0x00037000 0x000b7000 0x001000>, /* ap 66 */ - <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ - <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ - <0x00000000 0x00080000 0x004000>, /* ap 83 */ - <0x00004000 0x00084000 0x001000>, /* ap 84 */ - <0x00005000 0x00085000 0x001000>, /* ap 85 */ - <0x00006000 0x00086000 0x001000>, /* ap 86 */ - <0x00007000 0x00087000 0x001000>, /* ap 87 */ - <0x00008000 0x00088000 0x001000>, /* ap 88 */ - <0x00010000 0x00090000 0x004000>, /* ap 89 */ - <0x00014000 0x00094000 0x001000>, /* ap 90 */ - <0x00015000 0x00095000 0x001000>, /* ap 91 */ - <0x00016000 0x00096000 0x001000>, /* ap 92 */ - <0x00017000 0x00097000 0x001000>, /* ap 93 */ - <0x00018000 0x00098000 0x001000>, /* ap 94 */ - <0x00020000 0x000a0000 0x004000>, /* ap 95 */ - <0x00024000 0x000a4000 0x001000>, /* ap 96 */ - <0x00025000 0x000a5000 0x001000>, /* ap 97 */ - <0x00026000 0x000a6000 0x001000>, /* ap 98 */ - <0x00027000 0x000a7000 0x001000>, /* ap 99 */ - <0x00028000 0x000a8000 0x001000>; /* ap 100 */ - - target-module@0 { /* 0x4a080000, ap 83 28.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x14 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x00004000>, - <0x00004000 0x00004000 0x00001000>, - <0x00005000 0x00005000 0x00001000>, - <0x00006000 0x00006000 0x00001000>, - <0x00007000 0x00007000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x20>; - }; - - usb2_phy: usb2phy@4000 { - compatible = "ti,omap-usb2"; - reg = <0x4000 0x7c>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4400 { - compatible = "ti,omap-usb3"; - reg = <0x4400 0x80>, - <0x4800 0x64>, - <0x4c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@10000 { /* 0x4a090000, ap 89 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x10000 0x4>, - <0x10010 0x4>, - <0x10014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x00004000>, - <0x00004000 0x00014000 0x00001000>, - <0x00005000 0x00015000 0x00001000>, - <0x00006000 0x00016000 0x00001000>, - <0x00007000 0x00017000 0x00001000>; - - ocp2scp@0 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x20>; - }; - - sata_phy: phy@6000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x6400 0x64>, /* phy_tx */ - <0x6800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00020000 0x00004000>, - <0x00004000 0x00024000 0x00001000>, - <0x00005000 0x00025000 0x00001000>, - <0x00006000 0x00026000 0x00001000>, - <0x00007000 0x00027000 0x00001000>; - }; - - target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - }; - - target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4d000 0x1000>; - }; - - target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - }; - - target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - }; - - target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - }; - - target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - }; - - target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x74000 0x4>, - <0x74010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x74000 0x1000>; - - mailbox: mailbox@0 { - compatible = "ti,omap4-mailbox"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - }; - - target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x76000 0x4>, - <0x76010 0x4>, - <0x76014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ - clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x76000 0x1000>; - - hwspinlock: spinlock@0 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x0 0x1000>; - #hwlock-cells = <1>; - }; - }; - }; - - segment@100000 { /* 0x4a100000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ - <0x00003000 0x00103000 0x001000>, /* ap 60 */ - <0x00008000 0x00108000 0x001000>, /* ap 61 */ - <0x00009000 0x00109000 0x001000>, /* ap 62 */ - <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ - <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ - <0x00040000 0x00140000 0x010000>, /* ap 101 */ - <0x00050000 0x00150000 0x001000>; /* ap 102 */ - - target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@8000 { /* 0x4a108000, ap 61 26.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@40000 { /* 0x4a140000, ap 101 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000 0x10000>; - }; - }; - - segment@180000 { /* 0x4a180000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@200000 { /* 0x4a200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ - <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ - <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ - <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ - <0x00006000 0x00206000 0x001000>, /* ap 33 */ - <0x00007000 0x00207000 0x001000>, /* ap 34 */ - <0x00004000 0x00204000 0x001000>, /* ap 35 */ - <0x00005000 0x00205000 0x001000>, /* ap 36 */ - <0x00012000 0x00212000 0x001000>, /* ap 37 */ - <0x00013000 0x00213000 0x001000>, /* ap 38 */ - <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ - <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ - <0x00010000 0x00210000 0x001000>, /* ap 41 */ - <0x00011000 0x00211000 0x001000>, /* ap 42 */ - <0x00016000 0x00216000 0x001000>, /* ap 43 */ - <0x00017000 0x00217000 0x001000>, /* ap 44 */ - <0x00014000 0x00214000 0x001000>, /* ap 45 */ - <0x00015000 0x00215000 0x001000>, /* ap 46 */ - <0x00018000 0x00218000 0x001000>, /* ap 47 */ - <0x00019000 0x00219000 0x001000>, /* ap 48 */ - <0x00020000 0x00220000 0x001000>, /* ap 49 */ - <0x00021000 0x00221000 0x001000>, /* ap 50 */ - <0x00026000 0x00226000 0x001000>, /* ap 51 */ - <0x00027000 0x00227000 0x001000>, /* ap 52 */ - <0x00028000 0x00228000 0x001000>, /* ap 53 */ - <0x00029000 0x00229000 0x001000>, /* ap 54 */ - <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ - <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ - <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ - <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ - <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ - <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ - <0x00024000 0x00224000 0x001000>, /* ap 75 */ - <0x00025000 0x00225000 0x001000>, /* ap 76 */ - <0x00002000 0x00202000 0x001000>, /* ap 103 */ - <0x00003000 0x00203000 0x001000>, /* ap 104 */ - <0x00008000 0x00208000 0x001000>, /* ap 105 */ - <0x00009000 0x00209000 0x001000>, /* ap 106 */ - <0x00022000 0x00222000 0x001000>, /* ap 107 */ - <0x00023000 0x00223000 0x001000>; /* ap 108 */ - - target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@4000 { /* 0x4a204000, ap 35 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - }; - - target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x1000>; - }; - - target-module@8000 { /* 0x4a208000, ap 105 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - }; - - target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - }; - - target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - }; - - target-module@10000 { /* 0x4a210000, ap 41 56.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10000 0x1000>; - }; - - target-module@12000 { /* 0x4a212000, ap 37 52.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x12000 0x1000>; - }; - - target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x14000 0x1000>; - }; - - target-module@16000 { /* 0x4a216000, ap 43 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x16000 0x1000>; - }; - - target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000 0x1000>; - }; - - target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1c000 0x1000>; - }; - - target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e000 0x1000>; - }; - - target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - }; - - target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x22000 0x1000>; - }; - - target-module@24000 { /* 0x4a224000, ap 75 48.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x24000 0x1000>; - }; - - target-module@26000 { /* 0x4a226000, ap 51 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x26000 0x1000>; - }; - - target-module@28000 { /* 0x4a228000, ap 53 38.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x28000 0x1000>; - }; - - target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2a000 0x1000>; - }; - }; - - segment@280000 { /* 0x4a280000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; - - segment@300000 { /* 0x4a300000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_per { /* 0x48000000 */ - compatible = "ti,omap5-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ - <0x00200000 0x48200000 0x200000>; /* segment 1 */ - - segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x000400>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00020000 0x00020000 0x001000>, /* ap 3 */ - <0x00021000 0x00021000 0x001000>, /* ap 4 */ - <0x00032000 0x00032000 0x001000>, /* ap 5 */ - <0x00033000 0x00033000 0x001000>, /* ap 6 */ - <0x00034000 0x00034000 0x001000>, /* ap 7 */ - <0x00035000 0x00035000 0x001000>, /* ap 8 */ - <0x00036000 0x00036000 0x001000>, /* ap 9 */ - <0x00037000 0x00037000 0x001000>, /* ap 10 */ - <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ - <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ - <0x00055000 0x00055000 0x001000>, /* ap 13 */ - <0x00056000 0x00056000 0x001000>, /* ap 14 */ - <0x00057000 0x00057000 0x001000>, /* ap 15 */ - <0x00058000 0x00058000 0x001000>, /* ap 16 */ - <0x00059000 0x00059000 0x001000>, /* ap 17 */ - <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ - <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ - <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ - <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ - <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ - <0x00060000 0x00060000 0x001000>, /* ap 23 */ - <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ - <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ - <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ - <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ - <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ - <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ - <0x00070000 0x00070000 0x001000>, /* ap 30 */ - <0x00071000 0x00071000 0x001000>, /* ap 31 */ - <0x00072000 0x00072000 0x001000>, /* ap 32 */ - <0x00073000 0x00073000 0x001000>, /* ap 33 */ - <0x00061000 0x00061000 0x001000>, /* ap 34 */ - <0x00053000 0x00053000 0x001000>, /* ap 35 */ - <0x00054000 0x00054000 0x001000>, /* ap 36 */ - <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ - <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ - <0x00078000 0x00078000 0x001000>, /* ap 39 */ - <0x00079000 0x00079000 0x001000>, /* ap 40 */ - <0x00086000 0x00086000 0x001000>, /* ap 41 */ - <0x00087000 0x00087000 0x001000>, /* ap 42 */ - <0x00088000 0x00088000 0x001000>, /* ap 43 */ - <0x00089000 0x00089000 0x001000>, /* ap 44 */ - <0x00051000 0x00051000 0x001000>, /* ap 45 */ - <0x00052000 0x00052000 0x001000>, /* ap 46 */ - <0x00098000 0x00098000 0x001000>, /* ap 47 */ - <0x00099000 0x00099000 0x001000>, /* ap 48 */ - <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ - <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ - <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ - <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ - <0x00068000 0x00068000 0x001000>, /* ap 53 */ - <0x00069000 0x00069000 0x001000>, /* ap 54 */ - <0x00090000 0x00090000 0x002000>, /* ap 55 */ - <0x00092000 0x00092000 0x001000>, /* ap 56 */ - <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ - <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ - <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ - <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ - <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ - <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ - <0x00066000 0x00066000 0x001000>, /* ap 63 */ - <0x00067000 0x00067000 0x001000>, /* ap 64 */ - <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ - <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ - <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ - <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ - <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ - <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ - <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ - <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ - <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ - <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ - <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ - <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ - <0x00001400 0x00001400 0x000400>, /* ap 77 */ - <0x00001800 0x00001800 0x000400>, /* ap 78 */ - <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ - <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ - <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ - <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ - <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ - <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ - - target-module@20000 { /* 0x48020000, ap 3 04.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x20050 0x4>, - <0x20054 0x4>, - <0x20058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x20000 0x1000>; - - uart3: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@32000 { /* 0x48032000, ap 5 3e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x32000 0x4>, - <0x32010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x32000 0x1000>; - - timer2: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@34000 { /* 0x48034000, ap 7 46.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x34000 0x4>, - <0x34010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x34000 0x1000>; - - timer3: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@36000 { /* 0x48036000, ap 9 4e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x36000 0x4>, - <0x36010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x36000 0x1000>; - - timer4: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x3e000 0x4>, - <0x3e010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x3e000 0x1000>; - - timer9: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - }; - }; - - target-module@51000 { /* 0x48051000, ap 45 2e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x51000 0x4>, - <0x51010 0x4>, - <0x51114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x51000 0x1000>; - - gpio7: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@53000 { /* 0x48053000, ap 35 36.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x53000 0x4>, - <0x53010 0x4>, - <0x53114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x53000 0x1000>; - - gpio8: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55000 0x4>, - <0x55010 0x4>, - <0x55114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x55000 0x1000>; - - gpio2: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@57000 { /* 0x48057000, ap 15 06.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x57000 0x4>, - <0x57010 0x4>, - <0x57114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x57000 0x1000>; - - gpio3: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@59000 { /* 0x48059000, ap 17 16.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x59000 0x4>, - <0x59010 0x4>, - <0x59114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x59000 0x1000>; - - gpio4: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5b000 0x4>, - <0x5b010 0x4>, - <0x5b114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5b000 0x1000>; - - gpio5: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5d000 0x4>, - <0x5d010 0x4>, - <0x5d114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, - <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x5d000 0x1000>; - - gpio6: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@60000 { /* 0x48060000, ap 23 24.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x60000 0x8>, - <0x60010 0x8>, - <0x60090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x60000 0x1000>; - - i2c3: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@66000 { /* 0x48066000, ap 63 4c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x66050 0x4>, - <0x66054 0x4>, - <0x66058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x66000 0x1000>; - - uart5: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@68000 { /* 0x48068000, ap 53 54.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x68050 0x4>, - <0x68054 0x4>, - <0x68058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x68000 0x1000>; - - uart6: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6a050 0x4>, - <0x6a054 0x4>, - <0x6a058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6a000 0x1000>; - - uart1: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6c050 0x4>, - <0x6c054 0x4>, - <0x6c058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6c000 0x1000>; - - uart2: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x6e050 0x4>, - <0x6e054 0x4>, - <0x6e058 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6e000 0x1000>; - - uart4: serial@0 { - compatible = "ti,omap4-uart"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <48000000>; - }; - }; - - target-module@70000 { /* 0x48070000, ap 30 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x70000 0x8>, - <0x70010 0x8>, - <0x70090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x70000 0x1000>; - - i2c1: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@72000 { /* 0x48072000, ap 32 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x72000 0x8>, - <0x72010 0x8>, - <0x72090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x72000 0x1000>; - - i2c2: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@78000 { /* 0x48078000, ap 39 12.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x78000 0x1000>; - }; - - target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7a000 0x8>, - <0x7a010 0x8>, - <0x7a090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7a000 0x1000>; - - i2c4: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x7c000 0x8>, - <0x7c010 0x8>, - <0x7c090 0x8>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7c000 0x1000>; - - i2c5: i2c@0 { - compatible = "ti,omap4-i2c"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - target-module@86000 { /* 0x48086000, ap 41 5e.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x86000 0x4>, - <0x86010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x86000 0x1000>; - - timer10: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - }; - }; - - target-module@88000 { /* 0x48088000, ap 43 66.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - reg = <0x88000 0x4>, - <0x88010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x88000 0x1000>; - - timer11: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-pwm; - }; - }; - - rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x91fe0 0x4>, - <0x91fe4 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>; - /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ - clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x90000 0x2000>; - - rng: rng@0 { - compatible = "ti,omap4-rng"; - reg = <0x0 0x2000>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@98000 { /* 0x48098000, ap 47 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x98000 0x4>, - <0x98010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000 0x1000>; - - mcspi1: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - }; - - target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9a000 0x4>, - <0x9a010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9a000 0x1000>; - - mcspi2: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - }; - - target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x9c000 0x4>, - <0x9c010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x9c000 0x1000>; - - mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - }; - - target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa2000 0x1000>; - }; - - target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x000a4000 0x00001000>, - <0x00001000 0x000a5000 0x00001000>; - }; - - target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa8000 0x4000>; - }; - - target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xad000 0x4>, - <0xad010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xad000 0x1000>; - - mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb2000 0x1000>; - }; - - target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb4000 0x4>, - <0xb4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb4000 0x1000>; - - mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - }; - - target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xb8000 0x4>, - <0xb8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xb8000 0x1000>; - - mcspi3: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xba000 0x4>, - <0xba010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xba000 0x1000>; - - mcspi4: spi@0 { - compatible = "ti,omap4-mcspi"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - }; - - target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd1000 0x4>, - <0xd1010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd1000 0x1000>; - - mmc4: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - }; - - target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xd5000 0x4>, - <0xd5010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xd5000 0x1000>; - - mmc5: mmc@0 { - compatible = "ti,omap4-hsmmc"; - reg = <0x0 0x400>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - }; - }; - - segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&l4_wkup { /* 0x4ae00000 */ - compatible = "ti,omap5-l4-wkup", "simple-bus"; - reg = <0x4ae00000 0x800>, - <0x4ae00800 0x800>, - <0x4ae01000 0x1000>; - reg-names = "ap", "la", "ia0"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ - <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ - <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ - - segment@0 { /* 0x4ae00000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ - <0x00001000 0x00001000 0x001000>, /* ap 1 */ - <0x00000800 0x00000800 0x000800>, /* ap 2 */ - <0x00006000 0x00006000 0x002000>, /* ap 3 */ - <0x00008000 0x00008000 0x001000>, /* ap 4 */ - <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ - <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ - <0x00004000 0x00004000 0x001000>, /* ap 17 */ - <0x00005000 0x00005000 0x001000>, /* ap 18 */ - <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ - <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ - - target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; - reg = <0x4000 0x4>, - <0x4010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - counter32k: counter@0 { - compatible = "ti,omap-counter32k"; - reg = <0x0 0x40>; - }; - }; - - target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x6000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x6000 0x2000>; - - prm: prm@0 { - compatible = "ti,omap5-prm", "simple-bus"; - reg = <0x0 0x2000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x2000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - }; - - target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xa000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xa000 0x1000>; - - scrm: scrm@0 { - compatible = "ti,omap5-scrm"; - reg = <0x0 0x1000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - }; - - target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0xc000 0x4>; - reg-names = "rev"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - omap5_pmx_wkup: pinmux@840 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x840 0x003c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { - compatible = "ti,omap5-scm-wkup-pad-conf", - "simple-bus"; - reg = <0xda0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60>; - - scm_wkup_pad_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x60>; - - scm_wkup_pad_conf_clocks: clocks@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - }; - }; - - segment@10000 { /* 0x4ae10000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ - <0x00001000 0x00011000 0x001000>, /* ap 6 */ - <0x00004000 0x00014000 0x001000>, /* ap 7 */ - <0x00005000 0x00015000 0x001000>, /* ap 8 */ - <0x00008000 0x00018000 0x001000>, /* ap 9 */ - <0x00009000 0x00019000 0x001000>, /* ap 10 */ - <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ - <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ - - target-module@0 { /* 0x4ae10000, ap 5 10.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x0 0x4>, - <0x10 0x4>, - <0x114 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, - <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; - clock-names = "fck", "dbclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - - gpio1: gpio@0 { - compatible = "ti,omap4-gpio"; - reg = <0x0 0x200>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x4000 0x4>, - <0x4010 0x4>, - <0x4014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x4000 0x1000>; - - wdt2: wdt@0 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x0 0x80>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ - compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; - reg = <0x8000 0x4>, - <0x8010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP4_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8000 0x1000>; - - timer1: timer@0 { - compatible = "ti,omap5430-timer"; - reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - ti,timer-alwon; - }; - }; - - target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0xc000 0x4>, - <0xc010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | - SYSC_OMAP2_SOFTRESET)>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ - clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xc000 0x1000>; - - keypad: keypad@0 { - compatible = "ti,omap4-keypad"; - reg = <0x0 0x400>; - }; - }; - }; - - segment@20000 { /* 0x4ae20000 */ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ - <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ - <0x00000000 0x00020000 0x001000>, /* ap 21 */ - <0x00001000 0x00021000 0x001000>, /* ap 22 */ - <0x00002000 0x00022000 0x001000>, /* ap 23 */ - <0x00003000 0x00023000 0x001000>, /* ap 24 */ - <0x00007000 0x00027000 0x000400>, /* ap 25 */ - <0x00008000 0x00028000 0x000800>, /* ap 26 */ - <0x00009000 0x00029000 0x000100>, /* ap 27 */ - <0x00008800 0x00028800 0x000200>, /* ap 28 */ - <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ - - target-module@0 { /* 0x4ae20000, ap 21 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2000 0x1000>; - }; - - target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00006000 0x00001000>, - <0x00001000 0x00007000 0x00000400>, - <0x00002000 0x00008000 0x00000800>, - <0x00002800 0x00008800 0x00000200>, - <0x00002a00 0x00008a00 0x00000100>, - <0x00003000 0x00009000 0x00000100>; - }; - }; -}; diff --git a/arch/arm/dts/omap5-uevm.dts b/arch/arm/dts/omap5-uevm.dts deleted file mode 100644 index 9441e9a572a..00000000000 --- a/arch/arm/dts/omap5-uevm.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ -/dts-v1/; - -#include "omap5-board-common.dtsi" - -/ { - model = "TI OMAP5 uEVM board"; - compatible = "ti,omap5-uevm", "ti,omap5"; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ - }; - - aliases { - ethernet = ðernet; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - evm_keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&evm_keys_pins>; - - #address-cells = <7>; - #size-cells = <0>; - - btn1 { - label = "BTN1"; - linux,code = <169>; - gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */ - wakeup-source; - autorepeat; - debounce-interval = <50>; - }; - }; - - evm_leds { - compatible = "gpio-leds"; - - led1 { - label = "omap5:red:led"; - gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led2 { - label = "omap5:green:led"; - gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led3 { - label = "omap5:blue:led"; - gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc2"; - default-state = "off"; - }; - - led4 { - label = "omap5:green:led1"; - gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led5 { - label = "omap5:green:led2"; - gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led6 { - label = "omap5:green:led3"; - gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led7 { - label = "omap5:green:led4"; - gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - default-state = "off"; - }; - - led8 { - label = "omap5:green:led5"; - gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; -}; - -&hdmi { - vdda-supply = <&ldo4_reg>; -}; - -&i2c1 { - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; - - gpio9: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - - cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */ -}; - -&omap5_pmx_core { - evm_keys_pins: pinmux_evm_keys_gpio_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ - OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ - >; - }; -}; - -&tpd12s015 { - gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */ - <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ - <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ -}; - -&twl6040 { - ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */ -}; - -&twl6040_pins { - pinctrl-single,pins = < - OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ - >; -}; - -&usbhsehci { - #address-cells = <1>; - #size-cells = <0>; - - hub@2 { - compatible = "usb424,3503"; - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ethernet: usbether@3 { - compatible = "usb424,9730"; - reg = <3>; - }; -}; - -&wlcore { - compatible = "ti,wl1837"; -}; diff --git a/arch/arm/dts/omap5.dtsi b/arch/arm/dts/omap5.dtsi deleted file mode 100644 index 2ac7f021c28..00000000000 --- a/arch/arm/dts/omap5.dtsi +++ /dev/null @@ -1,583 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on "omap4.dtsi" - */ - -#include <dt-bindings/bus/ti-sysc.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/omap.h> -#include <dt-bindings/clock/omap5.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "ti,omap5"; - interrupt-parent = <&wakeupgen>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1500000 1250000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - #cooling-cells = <2>; /* min followed by max */ - }; - }; - - thermal-zones { - #include "omap4-cpu-thermal.dtsi" - #include "omap5-gpu-thermal.dtsi" - #include "omap5-core-thermal.dtsi" - }; - - timer { - compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ */ - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-parent = <&gic>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48211000 0 0x1000>, - <0 0x48212000 0 0x2000>, - <0 0x48214000 0 0x2000>, - <0 0x48216000 0 0x2000>; - interrupt-parent = <&gic>; - }; - - wakeupgen: interrupt-controller@48281000 { - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0 0x48281000 0 0x1000>; - interrupt-parent = <&gic>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - sram = <&ocmcram>; - }; - }; - - /* - * XXX: Use a flat representation of the OMAP3 interconnect. - * The real OMAP interconnect network is quite complex. - * Since it will not bring real advantage to represent that in DT for - * the moment, just use a fake OCP bus entry to represent the whole bus - * hierarchy. - */ - ocp { - compatible = "ti,omap5-l3-noc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xc0000000>; - dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; - ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0 0x44000000 0 0x2000>, - <0 0x44800000 0 0x3000>, - <0 0x45000000 0 0x4000>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - - l4_wkup: interconnect@4ae00000 { - }; - - l4_cfg: interconnect@4a000000 { - }; - - l4_per: interconnect@48000000 { - }; - - l4_abe: interconnect@40100000 { - }; - - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x20000>; /* 128k */ - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - target-module@55082000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x55082000 0x4>, - <0x55082010 0x4>, - <0x55082014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; - clock-names = "fck"; - resets = <&prm_core 2>; - reset-names = "rstctrl"; - ranges = <0x0 0x55082000 0x100>; - #size-cells = <1>; - #address-cells = <1>; - - mmu_ipu: mmu@0 { - compatible = "ti,omap4-iommu"; - reg = <0x0 0x100>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <0>; - ti,iommu-bus-err-back; - }; - }; - - dmm@4e000000 { - compatible = "ti,omap5-dmm"; - reg = <0x4e000000 0x800>; - interrupts = <0 113 0x4>; - ti,hwmods = "dmm"; - }; - - emif1: emif@4c000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif1"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4c000000 0x400>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - emif2: emif@4d000000 { - compatible = "ti,emif-4d5"; - ti,hwmods = "emif2"; - ti,no-idle-on-init; - phy-type = <2>; /* DDR PHY type: Intelli PHY */ - reg = <0x4d000000 0x400>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - hw-caps-read-idle-ctrl; - hw-caps-ll-interface; - hw-caps-temp-alert; - }; - - bandgap: bandgap@4a0021e0 { - reg = <0x4a0021e0 0xc - 0x4a00232c 0xc - 0x4a002380 0x2c - 0x4a0023C0 0x3c>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - compatible = "ti,omap5430-bandgap"; - - #thermal-sensor-cells = <1>; - }; - - /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; - }; - - target-module@56000000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x5600fe00 0x4>, - <0x5600fe10 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x56000000 0x2000000>; - - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ - }; - - target-module@58000000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x58000000 4>, - <0x58000014 4>; - reg-names = "rev", "syss"; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; - clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x58000000 0x1000000>; - - dss: dss@0 { - compatible = "ti,omap5-dss"; - reg = <0 0x80>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x1000000>; - - target-module@1000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x1000 0x4>, - <0x1010 0x4>, - <0x1014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x1000>; - - dispc@0 { - compatible = "ti,omap5-dispc"; - reg = <0 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@2000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x2000 0x4>, - <0x2010 0x4>, - <0x2014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x1000>; - - rfbi: encoder@0 { - compatible = "ti,omap5-rfbi"; - reg = <0 0x100>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; - clock-names = "fck", "ick"; - }; - }; - - target-module@5000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x5000 0x4>, - <0x5010 0x4>, - <0x5014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5000 0x1000>; - - dsi1: encoder@0 { - compatible = "ti,omap5-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@9000 { - compatible = "ti,sysc-omap2", "ti,sysc"; - reg = <0x9000 0x4>, - <0x9010 0x4>, - <0x9014 0x4>; - reg-names = "rev", "sysc", "syss"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | - SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x9000 0x1000>; - - dsi2: encoder@0 { - compatible = "ti,omap5-dsi"; - reg = <0 0x200>, - <0x200 0x40>, - <0x300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - }; - - target-module@40000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x40000 0x4>, - <0x40010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck", "dss_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x40000 0x40000>; - - hdmi: encoder@0 { - compatible = "ti,omap5-hdmi"; - reg = <0 0x200>, - <0x200 0x80>, - <0x300 0x80>, - <0x20000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; - }; - }; - }; - }; - - abb_mpu: regulator-abb-mpu { - compatible = "ti,abb-v2"; - regulator-name = "abb_mpu"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, - <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80>; - /* LDOVBBMPU_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMPU_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1060000 0 0x0 0 0x02000000 0x01F00000 - 1250000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - - abb_mm: regulator-abb-mm { - compatible = "ti,abb-v2"; - regulator-name = "abb_mm"; - #address-cells = <0>; - #size-cells = <0>; - clocks = <&sys_clkin>; - ti,settling-time = <50>; - ti,clock-cycles = <16>; - - reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, - <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; - reg-names = "base-address", "int-address", - "efuse-address", "ldo-address"; - ti,tranxdone-status-mask = <0x80000000>; - /* LDOVBBMM_MUX_CTRL */ - ti,ldovbb-override-mask = <0x400>; - /* LDOVBBMM_VSET_OUT */ - ti,ldovbb-vset-mask = <0x1F>; - - /* - * NOTE: only FBB mode used but actual vset will - * determine final biasing - */ - ti,abb_info = < - /*uV ABB efuse rbb_m fbb_m vset_m*/ - 1025000 0 0x0 0 0x02000000 0x01F00000 - 1120000 0 0x4 0 0x02000000 0x01F00000 - >; - }; - }; -}; - -&cpu_thermal { - polling-delay = <500>; /* milliseconds */ - coefficients = <65 (-1791)>; -}; - -#include "omap5-l4.dtsi" -#include "omap54xx-clocks.dtsi" - -&gpu_thermal { - coefficients = <117 (-2992)>; -}; - -&core_thermal { - coefficients = <0 2000>; -}; - -#include "omap5-l4-abe.dtsi" -#include "omap54xx-clocks.dtsi" - -&prm { - prm_dsp: prm@400 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x400 0x100>; - #reset-cells = <1>; - }; - - prm_core: prm@700 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x700 0x100>; - #reset-cells = <1>; - }; - - prm_iva: prm@1200 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1200 0x100>; - #reset-cells = <1>; - }; - - prm_device: prm@1c00 { - compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; - reg = <0x1c00 0x100>; - #reset-cells = <1>; - }; -}; diff --git a/arch/arm/dts/omap54xx-clocks.dtsi b/arch/arm/dts/omap54xx-clocks.dtsi deleted file mode 100644 index 42f2c447727..00000000000 --- a/arch/arm/dts/omap54xx-clocks.dtsi +++ /dev/null @@ -1,1208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP5 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_core_aon_clocks { - pad_clks_src_ck: pad_clks_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - pad_clks_ck: pad_clks_ck@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pad_clks_src_ck>; - ti,bit-shift = <8>; - reg = <0x0108>; - }; - - secure_32k_clk_src_ck: secure_32k_clk_src_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - slimbus_src_clk: slimbus_src_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - slimbus_clk: slimbus_clk@108 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_src_clk>; - ti,bit-shift = <10>; - reg = <0x0108>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_12000000_ck: virt_12000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12000000>; - }; - - virt_13000000_ck: virt_13000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <13000000>; - }; - - virt_16800000_ck: virt_16800000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16800000>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - virt_27000000_ck: virt_27000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - virt_38400000_ck: virt_38400000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <38400000>; - }; - - xclk60mhsp1_ck: xclk60mhsp1_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - xclk60mhsp2_ck: xclk60mhsp2_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <60000000>; - }; - - dpll_abe_ck: dpll_abe_ck@1e0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-m4xen-clock"; - clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; - reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; - }; - - dpll_abe_x2_ck: dpll_abe_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_abe_ck>; - }; - - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f0>; - ti,index-starts-at-one; - }; - - abe_24m_fclk: abe_24m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - abe_clk: abe_clk@108 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_m2x2_ck>; - ti,max-div = <4>; - reg = <0x0108>; - ti,index-power-of-two; - }; - - abe_iclk: abe_iclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&aess_fclk>; - ti,bit-shift = <24>; - reg = <0x0528>; - ti,dividers = <2>, <1>; - }; - - abe_lp_clk_div: abe_lp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_abe_x2_ck>; - ti,max-div = <31>; - reg = <0x01f4>; - ti,index-starts-at-one; - }; - - dpll_core_byp_mux: dpll_core_byp_mux@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; - }; - - dpll_core_ck: dpll_core_ck@120 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-core-clock"; - clocks = <&sys_clkin>, <&dpll_core_byp_mux>; - reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - c2c_fclk: c2c_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h21x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - c2c_iclk: c2c_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&c2c_fclk>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0138>; - ti,index-starts-at-one; - }; - - dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x013c>; - ti,index-starts-at-one; - }; - - dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0140>; - ti,index-starts-at-one; - }; - - dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0144>; - ti,index-starts-at-one; - }; - - dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_core_m2_ck: dpll_core_m2_ck@130 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_ck>; - ti,max-div = <31>; - reg = <0x0130>; - ti,index-starts-at-one; - }; - - dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; - }; - - iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; - }; - - dpll_iva_ck: dpll_iva_ck@1a0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; - reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; - assigned-clocks = <&dpll_iva_ck>; - assigned-clock-rates = <1165000000>; - }; - - dpll_iva_x2_ck: dpll_iva_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_iva_ck>; - }; - - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01b8>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h11x2_ck>; - assigned-clock-rates = <465920000>; - }; - - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_iva_x2_ck>; - ti,max-div = <63>; - reg = <0x01bc>; - ti,index-starts-at-one; - assigned-clocks = <&dpll_iva_h12x2_ck>; - assigned-clock-rates = <388300000>; - }; - - mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_h12x2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_mpu_ck: dpll_mpu_ck@160 { - #clock-cells = <0>; - compatible = "ti,omap5-mpu-dpll-clock"; - clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; - reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - reg = <0x0170>; - ti,index-starts-at-one; - }; - - per_dpll_hs_clk_div: per_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_abe_m3x2_ck>; - clock-mult = <1>; - clock-div = <3>; - }; - - l3_iclk_div: l3_iclk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; - }; - - gpu_l3_iclk: gpu_l3_iclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l3_iclk_div>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4_root_clk_div: l4_root_clk_div@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - ti,max-div = <2>; - ti,bit-shift = <8>; - reg = <0x100>; - clocks = <&l3_iclk_div>; - ti,index-power-of-two; - }; - - slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&slimbus_clk>; - ti,bit-shift = <11>; - reg = <0x0560>; - }; - - aess_fclk: aess_fclk@528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x0528>; - }; - - mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; - ti,bit-shift = <26>; - reg = <0x0540>; - }; - - mcasp_gfclk: mcasp_gfclk@540 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; - ti,bit-shift = <24>; - reg = <0x0540>; - }; - - dummy_ck: dummy_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; -&prm_clocks { - sys_clkin: sys_clkin@110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; - }; - - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x0108>; - }; - - abe_dpll_clk_mux: abe_dpll_clk_mux@10c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&sys_32k_ck>; - reg = <0x010c>; - }; - - custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <2>; - }; - - dss_syc_gfclk_div: dss_syc_gfclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin>; - clock-mult = <1>; - clock-div = <1>; - }; - - wkupaon_iclk_mux: wkupaon_iclk_mux@108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&abe_lp_clk_div>; - reg = <0x0108>; - }; - - l3instr_ts_gclk_div: l3instr_ts_gclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&wkupaon_iclk_mux>; - clock-mult = <1>; - clock-div = <1>; - }; -}; - -&cm_core_clocks { - - dpll_per_byp_mux: dpll_per_byp_mux@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; - }; - - dpll_per_ck: dpll_per_ck@140 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&dpll_per_byp_mux>; - reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; - }; - - dpll_per_x2_ck: dpll_per_x2_ck { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-x2-clock"; - clocks = <&dpll_per_ck>; - }; - - dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0158>; - ti,index-starts-at-one; - }; - - dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x015c>; - ti,index-starts-at-one; - }; - - dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <63>; - reg = <0x0164>; - ti,index-starts-at-one; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0150>; - ti,index-starts-at-one; - }; - - dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_x2_ck>; - ti,max-div = <31>; - reg = <0x0154>; - ti,index-starts-at-one; - }; - - dpll_unipro1_ck: dpll_unipro1_ck@200 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; - }; - - dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro1_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro1_ck>; - ti,max-div = <127>; - reg = <0x0210>; - ti,index-starts-at-one; - }; - - dpll_unipro2_ck: dpll_unipro2_ck@1c0 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&sys_clkin>, <&sys_clkin>; - reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; - }; - - dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_unipro2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_unipro2_ck>; - ti,max-div = <127>; - reg = <0x01d0>; - ti,index-starts-at-one; - }; - - dpll_usb_byp_mux: dpll_usb_byp_mux@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; - }; - - dpll_usb_ck: dpll_usb_ck@180 { - #clock-cells = <0>; - compatible = "ti,omap4-dpll-j-type-clock"; - clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; - reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; - }; - - dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_usb_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_usb_m2_ck: dpll_usb_m2_ck@190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x0190>; - ti,index-starts-at-one; - }; - - func_128m_clk: func_128m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_h11x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - func_12m_fclk: func_12m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - func_24m_clk: func_24m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_48m_fclk: func_48m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - func_96m_fclk: func_96m_fclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2x2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - l3init_60m_fclk: l3init_60m_fclk@104 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_m2_ck>; - reg = <0x0104>; - ti,dividers = <1>, <8>; - }; - - iss_ctrlclk: iss_ctrlclk@1320 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&func_96m_fclk>; - ti,bit-shift = <8>; - reg = <0x1320>; - }; - - lli_txphy_clk: lli_txphy_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_clkdcoldo>; - ti,bit-shift = <8>; - reg = <0x0f20>; - }; - - lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_unipro1_m2_ck>; - ti,bit-shift = <9>; - reg = <0x0f20>; - }; - - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_32k_ck>; - ti,bit-shift = <8>; - reg = <0x0640>; - }; - - fdif_fclk: fdif_fclk@1328 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_h11x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1328>; - }; - - gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <24>; - reg = <0x1520>; - }; - - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; - ti,bit-shift = <25>; - reg = <0x1520>; - }; - - hsi_fclk: hsi_fclk@1638 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_m2x2_ck>; - ti,bit-shift = <24>; - ti,max-div = <2>; - reg = <0x1638>; - }; -}; - -&cm_core_clockdomains { - l3init_clkdm: l3init_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dpll_usb_ck>; - }; -}; - -&scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0310>; - }; - - auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0310>; - }; - - auxclk0_src_ck: auxclk0_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; - }; - - auxclk0_ck: auxclk0_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk0_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0310>; - }; - - auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0314>; - }; - - auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0314>; - }; - - auxclk1_src_ck: auxclk1_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; - }; - - auxclk1_ck: auxclk1_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk1_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0314>; - }; - - auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0318>; - }; - - auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0318>; - }; - - auxclk2_src_ck: auxclk2_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; - }; - - auxclk2_ck: auxclk2_ck@318 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk2_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0318>; - }; - - auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x031c>; - }; - - auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x031c>; - }; - - auxclk3_src_ck: auxclk3_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; - }; - - auxclk3_ck: auxclk3_ck@31c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk3_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x031c>; - }; - - auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&dpll_core_m3x2_ck>; - ti,bit-shift = <8>; - reg = <0x0320>; - }; - - auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; - ti,bit-shift = <1>; - reg = <0x0320>; - }; - - auxclk4_src_ck: auxclk4_src_ck { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; - }; - - auxclk4_ck: auxclk4_ck@320 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&auxclk4_src_ck>; - ti,bit-shift = <16>; - ti,max-div = <16>; - reg = <0x0320>; - }; - - auxclkreq0_ck: auxclkreq0_ck@210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0210>; - }; - - auxclkreq1_ck: auxclkreq1_ck@214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0214>; - }; - - auxclkreq2_ck: auxclkreq2_ck@218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x0218>; - }; - - auxclkreq3_ck: auxclkreq3_ck@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; - ti,bit-shift = <2>; - reg = <0x021c>; - }; -}; - -&cm_core_aon { - mpu_cm: mpu_cm@300 { - compatible = "ti,omap4-cm"; - reg = <0x300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x300 0x100>; - - mpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dsp_cm: dsp_cm@400 { - compatible = "ti,omap4-cm"; - reg = <0x400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x400 0x100>; - - dsp_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - abe_cm: abe_cm@500 { - compatible = "ti,omap4-cm"; - reg = <0x500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x500 0x100>; - - abe_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x64>; - #clock-cells = <2>; - }; - }; - -}; - -&cm_core { - l3main1_cm: l3main1_cm@700 { - compatible = "ti,omap4-cm"; - reg = <0x700 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x700 0x100>; - - l3main1_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3main2_cm: l3main2_cm@800 { - compatible = "ti,omap4-cm"; - reg = <0x800 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x800 0x100>; - - l3main2_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - ipu_cm: ipu_cm@900 { - compatible = "ti,omap4-cm"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x900 0x100>; - - ipu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - dma_cm: dma_cm@a00 { - compatible = "ti,omap4-cm"; - reg = <0xa00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xa00 0x100>; - - dma_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - emif_cm: emif_cm@b00 { - compatible = "ti,omap4-cm"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xb00 0x100>; - - emif_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x1c>; - #clock-cells = <2>; - }; - }; - - l4cfg_cm: l4cfg_cm@d00 { - compatible = "ti,omap4-cm"; - reg = <0xd00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xd00 0x100>; - - l4cfg_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x14>; - #clock-cells = <2>; - }; - }; - - l3instr_cm: l3instr_cm@e00 { - compatible = "ti,omap4-cm"; - reg = <0xe00 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe00 0x100>; - - l3instr_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xc>; - #clock-cells = <2>; - }; - }; - - l4per_cm: l4per_cm@1000 { - compatible = "ti,omap4-cm"; - reg = <0x1000 0x200>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000 0x200>; - - l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl-l4per", "ti,clkctrl"; - reg = <0x20 0x15c>; - #clock-cells = <2>; - }; - - l4sec_clkctrl: clock@1a0 { - compatible = "ti,clkctrl-l4sec", "ti,clkctrl"; - reg = <0x1a0 0x3c>; - #clock-cells = <2>; - }; - }; - - dss_cm: dss_cm@1400 { - compatible = "ti,omap4-cm"; - reg = <0x1400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1400 0x100>; - - dss_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gpu_cm: gpu_cm@1500 { - compatible = "ti,omap4-cm"; - reg = <0x1500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1500 0x100>; - - gpu_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l3init_cm: l3init_cm@1600 { - compatible = "ti,omap4-cm"; - reg = <0x1600 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1600 0x100>; - - l3init_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0xd4>; - #clock-cells = <2>; - }; - }; -}; - -&prm { - wkupaon_cm: wkupaon_cm@1900 { - compatible = "ti,omap4-cm"; - reg = <0x1900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1900 0x100>; - - wkupaon_clkctrl: clk@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x5c>; - #clock-cells = <2>; - }; - }; -}; - -&scm_wkup_pad_conf_clocks { - fref_xtal_ck: fref_xtal_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin>; - ti,bit-shift = <28>; - reg = <0x14>; - }; -}; diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 607af277f8b..3b86b9328fc 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -51,16 +51,21 @@ }; }; - debug_uart: serial@a84000 { - compatible = "qcom,msm-geni-uart"; - reg = <0xa84000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9>; - qcom,wrapper-core = <0x8a>; - status = "disabled"; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x00ac0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart9: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9>; + }; }; spmi@c440000 { diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts index 34a4f59cbd1..eec51d165f9 100644 --- a/arch/arm/dts/starqltechn.dts +++ b/arch/arm/dts/starqltechn.dts @@ -9,6 +9,8 @@ /dts-v1/; #include "sdm845.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Samsung S9 (SM-G9600)"; @@ -21,7 +23,7 @@ }; aliases { - serial0 = &debug_uart; + serial0 = &uart9; }; memory { @@ -43,6 +45,22 @@ format = "a8r8g8b8"; }; + gpio-keys { + compatible = "gpio-keys"; + + key-pwr { + label = "Power"; + linux,code = <KEY_ENTER>; + gpios = <&pm8998_pon 0 GPIO_ACTIVE_LOW>; + }; + + key-vol-down { + label = "Volume Down"; + linux,code = <KEY_DOWN>; + gpios = <&pm8998_pon 1 GPIO_ACTIVE_LOW>; + }; + }; + soc: soc { serial@a84000 { status = "okay"; diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index e959eb2a405..af419c7e590 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -29,6 +29,11 @@ pad-byte = <0xff>; blob { + /* + * This value matches SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * and SYS_SPI_U_BOOT_OFFS if those are defined. + */ + min-size = <0x8000>; filename = "spl/sunxi-spl.bin"; }; @@ -105,7 +110,6 @@ }; #else u-boot-img { - offset = <CONFIG_SPL_PAD_TO>; }; #endif }; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 8ae49715789..81af89c631f 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -41,6 +41,8 @@ enum mxc_clock { MXC_SATA_CLK, MXC_NFC_CLK, MXC_I2C_CLK, + MXC_LCDIF1_CLK, + MXC_LCDIF2_CLK, }; enum ldb_di_clock { diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 437e86479ce..6eaeece4e24 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -209,7 +209,6 @@ enum sunxi_gpio_number { /* Virtual AXP0 GPIOs */ #define SUNXI_GPIO_AXP0_PREFIX "AXP0-" -#define SUNXI_GPIO_AXP0_VBUS_DETECT 4 #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 #define SUNXI_GPIO_AXP0_GPIO_COUNT 6 diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 9f58cedb650..19a9e112a43 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -49,10 +49,13 @@ #define PTE_TYPE_BLOCK (1 << 0) #define PTE_TYPE_VALID (1 << 0) -#define PTE_TABLE_PXN (1UL << 59) -#define PTE_TABLE_XN (1UL << 60) -#define PTE_TABLE_AP (1UL << 61) -#define PTE_TABLE_NS (1UL << 63) +#define PTE_RDONLY BIT(7) +#define PTE_DBM BIT(51) + +#define PTE_TABLE_PXN BIT(59) +#define PTE_TABLE_XN BIT(60) +#define PTE_TABLE_AP BIT(61) +#define PTE_TABLE_NS BIT(63) /* * Block @@ -99,6 +102,15 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) +#define TCR_EL1_HA BIT(39) +#define TCR_EL1_HD BIT(40) + +#define TCR_EL2_HA BIT(21) +#define TCR_EL2_HD BIT(22) + +#define TCR_EL3_HA BIT(21) +#define TCR_EL3_HD BIT(22) + #define TCR_EL1_RSVD (1U << 31) #define TCR_EL2_RSVD (1U << 31 | 1 << 23) #define TCR_EL3_RSVD (1U << 31 | 1 << 23) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 86987838f46..0c130757110 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -52,6 +52,8 @@ struct arch_global_data { #if defined(CONFIG_ARM64) unsigned long tlb_fillptr; unsigned long tlb_emerg; + unsigned int first_block_level; + bool has_hafdbs; #endif #endif #ifdef CFG_SYS_MEM_RESERVE_SECURE diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 2e091415a46..125dc0bb390 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -37,6 +37,40 @@ static void show_efi_loaded_images(struct pt_regs *regs) efi_print_image_infos((void *)regs->elr); } +static void dump_far(unsigned long esr) +{ + unsigned long el, far; + + switch ((esr >> 26) & 0b111111) { + case 0x20: + case 0x21: + case 0x24: + case 0x25: + case 0x22: + case 0x34: + case 0x35: + break; + default: + return; + } + + asm("mrs %0, CurrentEl": "=r" (el)); + + switch (el >> 2) { + case 1: + asm("mrs %0, FAR_EL1": "=r" (far)); + break; + case 2: + asm("mrs %0, FAR_EL2": "=r" (far)); + break; + default: + /* don't print anything to make output pretty */ + return; + } + + printf(", far 0x%lx", far); +} + static void dump_instr(struct pt_regs *regs) { u32 *addr = (u32 *)(regs->elr & ~3UL); @@ -165,7 +199,9 @@ void do_sync(struct pt_regs *pt_regs) smh_emulate_trap(pt_regs)) return; efi_restore_gd(); - printf("\"Synchronous Abort\" handler, esr 0x%08lx\n", pt_regs->esr); + printf("\"Synchronous Abort\" handler, esr 0x%08lx", pt_regs->esr); + dump_far(pt_regs->esr); + printf("\n"); show_regs(pt_regs); show_efi_loaded_images(pt_regs); panic("Resetting CPU ...\n"); diff --git a/arch/arm/mach-histb/Kconfig b/arch/arm/mach-histb/Kconfig new file mode 100644 index 00000000000..012dbfe8bc6 --- /dev/null +++ b/arch/arm/mach-histb/Kconfig @@ -0,0 +1,39 @@ +if ARCH_HISTB + +choice + prompt "Select a HiSTB SoC" + +config ARCH_HI3798MV2X + bool "Hi3798M V2XX series SoC" + select ARM64 + help + Support for Hi3798MV2XX series SoCs. + +endchoice + +if ARCH_HI3798MV2X + +choice + prompt "Select a Hi3798M V2XX based board" + +config TARGET_HC2910_2AGHD05 + bool "Skyworth HC2910 with board label 2AGHD05" + help + Support for Skyworth HC2910 with board label 2AGHD05. This board features: + - Hisilicon Hi3798MV200 SoC (4xCortex-A53, Mali MP-450) + - 2GiB DRAM + - 8GiB eMMC, uSD slot + - Wifi and Bluetooth module + - 1x USB 2.0, 1x USB 3.0 host port + - HDMI + - SCI + - 3 LED - power, Wifi, Lock(?) + - 1x Fast Ethernet Controller, 1x GBe Ethernet Controller + +endchoice + +endif + +source "board/skyworth/hc2910-2aghd05/Kconfig" + +endif diff --git a/arch/arm/mach-histb/Makefile b/arch/arm/mach-histb/Makefile new file mode 100644 index 00000000000..7975c0f2a03 --- /dev/null +++ b/arch/arm/mach-histb/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += sysmap-histb.o +obj-y += board_common.o diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c new file mode 100644 index 00000000000..a26c2066e02 --- /dev/null +++ b/arch/arm/mach-histb/board_common.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for all histb boards + * + * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <asm/system.h> + +int __weak board_init(void) +{ + return 0; +} + +int __weak dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int __weak dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +void __weak reset_cpu(void) +{ + psci_system_reset(); +} diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c new file mode 100644 index 00000000000..83a2bb94179 --- /dev/null +++ b/arch/arm/mach-histb/sysmap-histb.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hisilicon HiSTB memory map + * + * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com> + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region histb_mem_map[] = { + { + .virt = 0x0UL, /* DRAM */ + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, /* Peripheral block */ + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Terminator */ + 0, + } +}; + +struct mm_region *mem_map = histb_mem_map; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 018b87b85b7..15f844f5030 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -91,6 +91,13 @@ config TARGET_IMX8QM_ROM7720_A1 select SUPPORT_SPL select IMX8QM +config TARGET_IMX8QM_DMSSE20_A1 + bool "Support i.MX8QM DMS-SE20-A1 board" + select BINMAN + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BINMAN @@ -105,6 +112,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/congatec/cgtqmx8/Kconfig" +source "board/advantech/imx8qm_dmsse20_a1/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index dc51f971d45..7639439bdc9 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MQ_REFORM2 + bool "imx8mq_reform2" + select BINMAN + select IMX8MQ + select IMX8M_LPDDR4 + config TARGET_IMX8MM_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Mini" select BINMAN @@ -362,6 +368,7 @@ source "board/kontron/pitx_imx8m/Kconfig" source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" +source "board/mntre/imx8mq_reform2/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/purism/librem5/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index df865e997d3..4705e6c1192 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -914,6 +914,8 @@ static int low_drive_gpu_freq(void *blob) if (cnt != 7) printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt); + if (cnt < 2) + return -1; assignedclks[cnt - 1] = 200000000; assignedclks[cnt - 2] = 200000000; @@ -1395,40 +1397,6 @@ usb_modify_speed: } #endif -#ifdef CONFIG_OF_BOARD_FIXUP -#ifndef CONFIG_SPL_BUILD -int board_fix_fdt(void *fdt) -{ - if (is_imx8mpul()) { - int i = 0; - int nodeoff, ret; - const char *status = "disabled"; - static const char * const dsi_nodes[] = { - "/soc@0/bus@32c00000/mipi_dsi@32e60000", - "/soc@0/bus@32c00000/lcd-controller@32e80000", - "/dsi-host" - }; - - for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) { - nodeoff = fdt_path_offset(fdt, dsi_nodes[i]); - if (nodeoff > 0) { -set_status: - ret = fdt_setprop(fdt, nodeoff, "status", status, - strlen(status) + 1); - if (ret == -FDT_ERR_NOSPACE) { - ret = fdt_increase_size(fdt, 512); - if (!ret) - goto set_status; - } - } - } - } - - return 0; -} -#endif -#endif - #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index cb9d629be40..1bdc568f9b1 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num) static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div, test_div, pll_num, pll_denom; + u64 temp64; switch (pll) { case PLL_SYS: @@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } test_div = 1 << (2 - test_div); - return infreq * (div + pll_num / pll_denom) / test_div; + temp64 = (u64)infreq; + temp64 *= pll_num; + do_div(temp64, pll_denom); + return infreq * div + (unsigned long)temp64; default: return 0; } @@ -414,6 +418,60 @@ static u32 get_uart_clk(void) return freq / (uart_podf + 1); } +static u32 get_lcd_clk(unsigned int ifnum) +{ + u32 pll_rate; + u32 pred, postd; + + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() && + !is_mx6sll()) { + debug("This chip does't support lcd\n"); + return 0; + } + + pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK); + if (ifnum == 1) { + if (!is_mx6sl()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cbcmr); + postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } else { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } + } else if (ifnum == 2) { + if (is_mx6sx()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK; + postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET; + + } else { + goto if_err; + } + } else { + goto if_err; + } + + return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1)); + +if_err: + debug("This chip not support lcd iterface %d\n", ifnum); + return 0; +} + static u32 get_cspi_clk(void) { u32 reg, cspi_podf; @@ -744,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) } enable_lcdif_clock(base_addr, 1); + debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK)); } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) @@ -765,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET)); enable_lcdif_clock(base_addr, 1); + debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK)); } } @@ -1269,6 +1329,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_usdhc_clk(3); case MXC_SATA_CLK: return get_ahb_clk(); + case MXC_LCDIF1_CLK: + return get_lcd_clk(1); + case MXC_LCDIF2_CLK: + return get_lcd_clk(2); default: printf("Unsupported MXC CLK: %d\n", clk); break; diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c index b49e7f80a28..ff0522c2d11 100644 --- a/arch/arm/mach-imx/romapi.c +++ b/arch/arm/mach-imx/romapi.c @@ -70,6 +70,8 @@ enum boot_device get_boot_device(void) boot_dev = SPI_NOR_BOOT; break; case BT_DEV_TYPE_USB: + if (!is_imx8ulp() && !is_imx9()) + boot_instance = 0; boot_dev = boot_instance + USB_BOOT; break; default: diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 7edbac26ccc..0ffbbf9168e 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -52,7 +52,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE config SYS_K3_MCU_SCRATCHPAD_BASE hex default 0x40280000 if SOC_K3_AM654 - default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2 + default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 help Describes the base address of MCU Scratchpad RAM. @@ -187,11 +187,6 @@ config K3_X509_SWRV help SWRV for X509 certificate used for boot images -config K3_BOARD_DETECT - bool "Support for Board detection" - help - Support for board detection. - source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/am62x/Kconfig" diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index a91c15ca4e1..026c4f9c02d 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -9,7 +9,7 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/sysfw-loader.h> +#include "sysfw-loader.h" #include "common.h" #include <dm.h> #include <dm/uclass-internal.h> diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index 02da24a3d6f..1f51b040896 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -8,7 +8,7 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/sysfw-loader.h> +#include "sysfw-loader.h" #include "common.h" #include <dm.h> #include <dm/uclass-internal.h> @@ -65,6 +65,20 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +#if (IS_ENABLED(CONFIG_CPU_V7R)) +static void setup_qos(void) +{ + u32 i; + + for (i = 0; i < am62a_qos_count; i++) + writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg); +} +#else +static void setup_qos(void) +{ +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -158,6 +172,8 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif + setup_qos(); + printf("am62a_init: %s done\n", __func__); } diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile index c58e52df1fa..02a941805e9 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -4,3 +4,4 @@ obj-y += clk-data.o obj-y += dev-data.o +obj-y += am62a_qos_data.o diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c new file mode 100644 index 00000000000..01b76f7493c --- /dev/null +++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am62a Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include "common.h" + +struct k3_qos_data am62a_qos_data[] = { + /* modules_qosConfig0 - 1 endpoints, 4 channels */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ORDERID_8, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, +}; + +uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]); diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 1bf7e163cc4..c871e92330b 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -12,19 +12,23 @@ #include <spl.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/sysfw-loader.h> -#include <asm/arch/sys_proto.h> +#include "sysfw-loader.h" #include "common.h" -#include <asm/arch/sys_proto.h> #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> #include <mmc.h> #include <dm/root.h> +#include <command.h> #define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) +#define COLD_BOOT 0 +#define SW_POR_MCU BIT(24) +#define SW_POR_MAIN BIT(25) + static void ctrl_mmr_unlock(void) { /* Unlock all PADCFG_MMR1 module registers */ @@ -100,8 +104,8 @@ void do_dt_magic(void) { int ret, rescan; - if (IS_ENABLED(CONFIG_K3_BOARD_DETECT)) - do_board_detect(); + /* Perform board detection */ + do_board_detect(); /* * Board detection has been done. @@ -166,6 +170,7 @@ void board_init_f(ulong dummy) #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3) struct udevice *dev; int ret; + int rst_src; #endif #if defined(CONFIG_CPU_V7R) @@ -185,8 +190,6 @@ void board_init_f(ulong dummy) preloader_console_init(); - do_dt_magic(); - #if defined(CONFIG_K3_LOAD_SYSFW) /* * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue @@ -210,9 +213,37 @@ void board_init_f(ulong dummy) k3_mmc_restart_clock); #endif +#if defined(CONFIG_CPU_V7R) + /* + * Errata ID i2331 CPSW: A device lockup can occur during the second + * read of any CPSW subsystem register after any MAIN domain power on + * reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz + * signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or + * CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor + * and internal bus structures may get into a state which is only + * recoverable with full device reset using MCU_PORz. + * Workaround(s): To avoid the lockup, a warm reset should be issued + * after a MAIN domain POR and before any access to the CPSW registers. + * The warm reset realigns internal clocks and prevents the lockup from + * happening. + */ + ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); + if (ret) + printf("\n%s:uclass device error [%d]\n",__func__,ret); + + rst_src = readl(CTRLMMR_MCU_RST_SRC); + if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) { + printf("Resetting on cold boot to workaround ErrataID:i2331\n"); + printf("Please resend tiboot3.bin in case of UART/DFU boot\n"); + do_reset(NULL, 0, 0, NULL); + } +#endif + /* Output System Firmware version info */ k3_sysfw_print_ver(); + do_dt_magic(); + #if defined(CONFIG_ESM_K3) /* Probe/configure ESM0 */ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); @@ -346,54 +377,3 @@ u32 spl_boot_device(void) else return __get_backup_bootmedia(devstat); } - -#if defined(CONFIG_SYS_K3_SPL_ATF) - -#define AM64X_DEV_RTI8 127 -#define AM64X_DEV_RTI9 128 -#define AM64X_DEV_R5FSS0_CORE0 121 -#define AM64X_DEV_R5FSS0_CORE1 122 - -void release_resources_for_core_shutdown(void) -{ - struct ti_sci_handle *ti_sci = get_ti_sci_handle(); - struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; - struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; - int ret; - u32 i; - - const u32 put_device_ids[] = { - AM64X_DEV_RTI9, - AM64X_DEV_RTI8, - }; - - /* Iterate through list of devices to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { - u32 id = put_device_ids[i]; - - ret = dev_ops->put_device(ti_sci, id); - if (ret) - panic("Failed to put device %u (%d)\n", id, ret); - } - - const u32 put_core_ids[] = { - AM64X_DEV_R5FSS0_CORE1, - AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */ - }; - - /* Iterate through list of cores to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { - u32 id = put_core_ids[i]; - - /* - * Queue up the core shutdown request. Note that this call - * needs to be followed up by an actual invocation of an WFE - * or WFI CPU instruction. - */ - ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); - if (ret) - panic("Failed sending core %u shutdown message (%d)\n", - id, ret); - } -} -#endif diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c index 70059edb039..0d3889cde2b 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am654_init.c @@ -13,8 +13,7 @@ #include <asm/io.h> #include <spl.h> #include <asm/arch/hardware.h> -#include <asm/arch/sysfw-loader.h> -#include <asm/arch/sys_proto.h> +#include "sysfw-loader.h" #include "common.h" #include <dm.h> #include <dm/uclass-internal.h> @@ -245,8 +244,8 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); - if (IS_ENABLED(CONFIG_K3_BOARD_DETECT)) - do_board_detect(); + /* Perform board detection */ + do_board_detect(); #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), @@ -353,54 +352,3 @@ u32 spl_boot_device(void) else return __get_backup_bootmedia(devstat); } - -#ifdef CONFIG_SYS_K3_SPL_ATF - -#define AM6_DEV_MCU_RTI0 134 -#define AM6_DEV_MCU_RTI1 135 -#define AM6_DEV_MCU_ARMSS0_CPU0 159 -#define AM6_DEV_MCU_ARMSS0_CPU1 245 - -void release_resources_for_core_shutdown(void) -{ - struct ti_sci_handle *ti_sci = get_ti_sci_handle(); - struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; - struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; - int ret; - u32 i; - - const u32 put_device_ids[] = { - AM6_DEV_MCU_RTI0, - AM6_DEV_MCU_RTI1, - }; - - /* Iterate through list of devices to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { - u32 id = put_device_ids[i]; - - ret = dev_ops->put_device(ti_sci, id); - if (ret) - panic("Failed to put device %u (%d)\n", id, ret); - } - - const u32 put_core_ids[] = { - AM6_DEV_MCU_ARMSS0_CPU1, - AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ - }; - - /* Iterate through list of cores to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { - u32 id = put_core_ids[i]; - - /* - * Queue up the core shutdown request. Note that this call - * needs to be followed up by an actual invocation of an WFE - * or WFI CPU instruction. - */ - ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); - if (ret) - panic("Failed sending core %u shutdown message (%d)\n", - id, ret); - } -} -#endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index a2adb791f6c..3c85caee579 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -19,7 +19,6 @@ #include <asm/cache.h> #include <linux/soc/ti/ti_sci_protocol.h> #include <fdt_support.h> -#include <asm/arch/sys_proto.h> #include <asm/hardware.h> #include <asm/io.h> #include <fs_loader.h> @@ -189,9 +188,37 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) return size; } -__weak void release_resources_for_core_shutdown(void) +void release_resources_for_core_shutdown(void) { - debug("%s not implemented...\n", __func__); + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; + struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; + int ret; + u32 i; + + /* Iterate through list of devices to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { + u32 id = put_device_ids[i]; + + ret = dev_ops->put_device(ti_sci, id); + if (ret) + panic("Failed to put device %u (%d)\n", id, ret); + } + + /* Iterate through list of cores to put (shutdown) */ + for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { + u32 id = put_core_ids[i]; + + /* + * Queue up the core shutdown request. Note that this call + * needs to be followed up by an actual invocation of an WFE + * or WFI CPU instruction. + */ + ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); + if (ret) + panic("Failed sending core %u shutdown message (%d)\n", + id, ret); + } } void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) @@ -227,6 +254,31 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) if (ret) panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); +#if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) + /* Authenticate ATF */ + void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start; + + debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, + fit_image_info[IMAGE_ID_ATF].image_start, + fit_image_info[IMAGE_ID_ATF].image_len, + image_os_match[IMAGE_ID_ATF]); + + ti_secure_image_post_process(&image_addr, + (size_t *)&fit_image_info[IMAGE_ID_ATF].image_len); + + /* Authenticate OPTEE */ + image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start; + + debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__, + fit_image_info[IMAGE_ID_OPTEE].image_start, + fit_image_info[IMAGE_ID_OPTEE].image_len, + image_os_match[IMAGE_ID_OPTEE]); + + ti_secure_image_post_process(&image_addr, + (size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len); + +#endif + if (!fit_image_info[IMAGE_ID_DM_FW].image_len && !(size > 0 && valid_elf_image(loadaddr))) { shut_cpu = 1; @@ -288,9 +340,15 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, break; } } + /* + * Only DM and the DTBs are being authenticated here, + * rest will be authenticated when A72 cluster is up + */ + if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE)) #endif - - ti_secure_image_post_process(p_image, p_size); + { + ti_secure_image_post_process(p_image, p_size); + } } #endif @@ -367,24 +425,21 @@ int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name) return 0; } -int fdt_disable_node(void *blob, char *node_path) +#if defined(CONFIG_OF_SYSTEM_SETUP) +int ft_system_setup(void *blob, struct bd_info *bd) { - int offs; int ret; - offs = fdt_path_offset(blob, node_path); - if (offs < 0) { - printf("Node %s not found.\n", node_path); - return offs; - } - ret = fdt_setprop_string(blob, offs, "status", "disabled"); - if (ret < 0) { - printf("Could not add status property to node %s: %s\n", - node_path, fdt_strerror(ret)); - return ret; - } - return 0; + ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000"); + if (ret < 0) + ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", + "sram@70000000"); + if (ret) + printf("%s: fixing up msmc ram failed %d\n", __func__, ret); + + return ret; } +#endif #endif @@ -472,26 +527,6 @@ int print_cpuinfo(void) } #endif -bool soc_is_j721e(void) -{ - u32 soc; - - soc = (readl(CTRLMMR_WKUP_JTAG_ID) & - JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; - - return soc == J721E; -} - -bool soc_is_j7200(void) -{ - u32 soc; - - soc = (readl(CTRLMMR_WKUP_JTAG_ID) & - JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; - - return soc == J7200; -} - #ifdef CONFIG_ARM64 void board_prep_linux(struct bootm_headers *images) { @@ -545,7 +580,10 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) fwl_ops->get_fwl_region(ti_sci, ®ion); - if (region.control != 0) { + /* Don't disable the background regions */ + if (region.control != 0 && + ((region.control & K3_BACKGROUND_FIREWALL_BIT) == + 0)) { pr_debug("Attempting to disable firewall %5d (%25s)\n", region.fwl_id, fwl_data[i].name); region.control = 0; @@ -606,9 +644,19 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } - /* Default FIT boot on non-GP devices */ - if (get_device_type() != K3_DEVICE_TYPE_GP) + /* Default FIT boot on HS-SE devices */ + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) env_set("boot_fit", "1"); return 0; } + +/** + * do_board_detect() - Detect board description + * + * Function to detect board description. This is expected to be + * overridden in the SoC family board file where desired. + */ +void __weak do_board_detect(void) +{ +} diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 8f38fcef7f0..e7e59f533b7 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -11,6 +11,7 @@ #define J721E 0xbb64 #define J7200 0xbb6d +#define K3_BACKGROUND_FIREWALL_BIT BIT(8) struct fwl_data { const char *name; @@ -38,3 +39,5 @@ void mmr_unlock(phys_addr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); enum k3_device_type get_device_type(void); void ti_secure_image_post_process(void **p_image, size_t *p_size); +struct ti_sci_handle *get_ti_sci_handle(void); +void do_board_detect(void); diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index db4a32cd461..88d58947269 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -57,4 +57,12 @@ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +static const u32 put_device_ids[] = {}; + +static const u32 put_core_ids[] = {}; + +#endif + #endif /* __ASM_ARCH_AM62_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h index 13bf50f147b..11080801c4c 100644 --- a/arch/arm/mach-k3/include/mach/am62a_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -86,4 +86,12 @@ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001 #endif /* CONFIG_CPU_V7R */ +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +static const u32 put_device_ids[] = {}; + +static const u32 put_core_ids[] = {}; + +#endif + #endif /* __ASM_ARCH_AM62A_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/include/mach/am62a_qos.h new file mode 100644 index 00000000000..c74d69a28f8 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_qos.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0) + +#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4) + +#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8) + +#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12) + +#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16) + +#define ATYPE_0 (0 << 28) +#define ATYPE_1 (1 << 28) +#define ATYPE_2 (2 << 28) +#define ATYPE_3 (3 << 28) + +#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 +#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 +#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800 +#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000 +#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400 +#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800 +#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400 +#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00 +#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000 +#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400 +#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800 +#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00 +#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000 +#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400 +#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800 +#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00 +#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000 +#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400 +#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800 +#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400 +#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800 +#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000 diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 207ef95f218..44df887d5df 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -7,6 +7,11 @@ #ifndef __ASM_ARCH_AM64_HARDWARE_H #define __ASM_ARCH_AM64_HARDWARE_H +#include <config.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + #define PADCFG_MMR1_BASE 0x000f0000 #define MCU_PADCFG_MMR1_BASE 0x04080000 #define WKUP_CTRL_MMR0_BASE 0x43000000 @@ -41,4 +46,23 @@ /* Use Last 2K as Scratch pad */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +#define AM64X_DEV_RTI8 127 +#define AM64X_DEV_RTI9 128 +#define AM64X_DEV_R5FSS0_CORE0 121 +#define AM64X_DEV_R5FSS0_CORE1 122 + +static const u32 put_device_ids[] = { + AM64X_DEV_RTI9, + AM64X_DEV_RTI8, +}; + +static const u32 put_core_ids[] = { + AM64X_DEV_R5FSS0_CORE1, + AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */ +}; + +#endif + #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index f9f32918f7c..029041f415c 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -39,4 +39,23 @@ #define NAVSS_NBSS_THREADMAP 0x10 +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +#define AM6_DEV_MCU_RTI0 134 +#define AM6_DEV_MCU_RTI1 135 +#define AM6_DEV_MCU_ARMSS0_CPU0 159 +#define AM6_DEV_MCU_ARMSS0_CPU1 245 + +static const u32 put_device_ids[] = { + AM6_DEV_MCU_RTI0, + AM6_DEV_MCU_RTI1, +}; + +static const u32 put_core_ids[] = { + AM6_DEV_MCU_ARMSS0_CPU1, + AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ +}; + +#endif + #endif /* __ASM_ARCH_AM6_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 2c60ef85432..65742c4b7c8 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H_ #define _ASM_ARCH_HARDWARE_H_ +#include <asm/io.h> + #ifdef CONFIG_SOC_K3_AM654 #include "am6_hardware.h" #endif @@ -28,6 +30,7 @@ #ifdef CONFIG_SOC_K3_AM62A7 #include "am62a_hardware.h" +#include "am62a_qos.h" #endif /* Assuming these addresses and definitions stay common across K3 devices */ @@ -36,6 +39,29 @@ #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 #define JTAG_ID_PARTNO_MASK (0xffff << 12) +#define JTAG_ID_PARTNO_AM65X 0xbb5a +#define JTAG_ID_PARTNO_J721E 0xbb64 +#define JTAG_ID_PARTNO_J7200 0xbb6d +#define JTAG_ID_PARTNO_AM64X 0xbb38 +#define JTAG_ID_PARTNO_J721S2 0xbb75 +#define JTAG_ID_PARTNO_AM62X 0xbb7e +#define JTAG_ID_PARTNO_AM62AX 0xbb8d + +#define K3_SOC_ID(id, ID) \ +static inline bool soc_is_##id(void) \ +{ \ + u32 soc = (readl(CTRLMMR_WKUP_JTAG_ID) & \ + JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \ + return soc == JTAG_ID_PARTNO_##ID; \ +} +K3_SOC_ID(am65x, AM65X) +K3_SOC_ID(j721e, J721E) +K3_SOC_ID(j7200, J7200) +K3_SOC_ID(am64x, AM64X) +K3_SOC_ID(j721s2, J721S2) +K3_SOC_ID(am62x, AM62X) +K3_SOC_ID(am62ax, AM62AX) + #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 #define SYS_STATUS_DEV_TYPE_MASK (0xf) @@ -71,4 +97,12 @@ struct rom_extended_boot_data { u32 num_components; }; +struct k3_qos_data { + u32 reg; + u32 val; +}; + +extern struct k3_qos_data am62a_qos_data[]; +extern u32 am62a_qos_count; + #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 247dee99ce5..376db389ba1 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -38,4 +38,23 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +#define J721E_DEV_MCU_RTI0 262 +#define J721E_DEV_MCU_RTI1 263 +#define J721E_DEV_MCU_ARMSS0_CPU0 250 +#define J721E_DEV_MCU_ARMSS0_CPU1 251 + +static const u32 put_device_ids[] = { + J721E_DEV_MCU_RTI0, + J721E_DEV_MCU_RTI1, +}; + +static const u32 put_core_ids[] = { + J721E_DEV_MCU_ARMSS0_CPU1, + J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ +}; + +#endif + #endif /* __ASM_ARCH_J721E_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 2e155ed9ec4..7948bcf4789 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -38,4 +38,23 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) + +#define J721S2_DEV_MCU_RTI0 295 +#define J721S2_DEV_MCU_RTI1 296 +#define J721S2_DEV_MCU_ARMSS0_CPU0 284 +#define J721S2_DEV_MCU_ARMSS0_CPU1 285 + +static const u32 put_device_ids[] = { + J721S2_DEV_MCU_RTI0, + J721S2_DEV_MCU_RTI1, +}; + +static const u32 put_core_ids[] = { + J721S2_DEV_MCU_ARMSS0_CPU1, + J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ +}; + +#endif + #endif /* __ASM_ARCH_J721S2_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h deleted file mode 100644 index 3d3d90d02d6..00000000000 --- a/arch/arm/mach-k3/include/mach/sys_proto.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ - * Andreas Dannenberg <dannenberg@ti.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -void sdelay(unsigned long loops); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, - u32 bound); -struct ti_sci_handle *get_ti_sci_handle(void); -int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name); -int do_board_detect(void); -void release_resources_for_core_shutdown(void); -int fdt_disable_node(void *blob, char *node_path); - -bool soc_is_j721e(void); -bool soc_is_j7200(void); - -void k3_spl_init(void); -void k3_mem_init(void); -bool check_rom_loaded_sysfw(void); -#endif diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 9cae3ac67e9..0c5d41a77e6 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -12,9 +12,8 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include <asm/arch/sysfw-loader.h> +#include "sysfw-loader.h" #include "common.h" -#include <asm/arch/sys_proto.h> #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -26,6 +25,7 @@ #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { +#if defined(CONFIG_TARGET_J721E_R5_EVM) { "PCIE0_CFG", 2560, 8 }, { "PCIE1_CFG", 2561, 8 }, { "USB3SS0_CORE", 2568, 4 }, @@ -34,11 +34,16 @@ struct fwl_data cbass_hc_cfg0_fwls[] = { { "UFS_HCI0_CFG", 2580, 4 }, { "SERDES0", 2584, 1 }, { "SERDES1", 2585, 1 }, +#elif defined(CONFIG_TARGET_J7200_R5_EVM) + { "PCIE1_CFG", 2561, 7 }, +#endif }, cbass_hc0_fwls[] = { +#if defined(CONFIG_TARGET_J721E_R5_EVM) { "PCIE0_HP", 2528, 24 }, { "PCIE0_LP", 2529, 24 }, { "PCIE1_HP", 2530, 24 }, { "PCIE1_LP", 2531, 24 }, +#endif }, cbass_rc_cfg0_fwls[] = { { "EMMCSD4SS0_CFG", 2380, 4 }, }, cbass_rc0_fwls[] = { @@ -140,8 +145,8 @@ void do_dt_magic(void) int ret, rescan, mmc_dev = -1; static struct mmc *mmc; - if (IS_ENABLED(CONFIG_K3_BOARD_DETECT)) - do_board_detect(); + /* Perform board detection */ + do_board_detect(); /* * Board detection has been done. @@ -267,8 +272,8 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); - if (IS_ENABLED(CONFIG_K3_BOARD_DETECT)) - do_board_detect(); + /* Perform board detection */ + do_board_detect(); #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), @@ -378,58 +383,3 @@ u32 spl_boot_device(void) else return __get_backup_bootmedia(main_devstat); } - -#ifdef CONFIG_SYS_K3_SPL_ATF - -#define J721E_DEV_MCU_RTI0 262 -#define J721E_DEV_MCU_RTI1 263 -#define J721E_DEV_MCU_ARMSS0_CPU0 250 -#define J721E_DEV_MCU_ARMSS0_CPU1 251 - -void release_resources_for_core_shutdown(void) -{ - struct ti_sci_handle *ti_sci; - struct ti_sci_dev_ops *dev_ops; - struct ti_sci_proc_ops *proc_ops; - int ret; - u32 i; - - const u32 put_device_ids[] = { - J721E_DEV_MCU_RTI0, - J721E_DEV_MCU_RTI1, - }; - - ti_sci = get_ti_sci_handle(); - dev_ops = &ti_sci->ops.dev_ops; - proc_ops = &ti_sci->ops.proc_ops; - - /* Iterate through list of devices to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { - u32 id = put_device_ids[i]; - - ret = dev_ops->put_device(ti_sci, id); - if (ret) - panic("Failed to put device %u (%d)\n", id, ret); - } - - const u32 put_core_ids[] = { - J721E_DEV_MCU_ARMSS0_CPU1, - J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ - }; - - /* Iterate through list of cores to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { - u32 id = put_core_ids[i]; - - /* - * Queue up the core shutdown request. Note that this call - * needs to be followed up by an actual invocation of an WFE - * or WFI CPU instruction. - */ - ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); - if (ret) - panic("Failed sending core %u shutdown message (%d)\n", - id, ret); - } -} -#endif diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 09e55ed4566..712a7e253fa 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -12,16 +12,61 @@ #include <asm/io.h> #include <asm/armv7_mpu.h> #include <asm/arch/hardware.h> -#include <asm/arch/sysfw-loader.h> +#include "sysfw-loader.h" #include "common.h" -#include <asm/arch/sys_proto.h> #include <linux/soc/ti/ti_sci_protocol.h> #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include <dm/root.h> #include <mmc.h> #include <remoteproc.h> +struct fwl_data cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2577, 7 }, + { "EMMC8SS0_CFG", 2579, 4 }, + { "USB3SS0_CORE", 2580, 4 }, + { "USB3SS1_CORE", 2581, 1 }, +}, cbass_hc2_fwls[] = { + { "PCIE0", 2547, 24 }, + { "HC2_WIZ16B8M4CT2", 2552, 1 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2400, 4 }, +}, infra_cbass0_fwls[] = { + { "PSC0", 5, 1 }, + { "PLL_CTRL0", 6, 1 }, + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, + { "GPIO0", 16, 1 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 3 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_R5FSS0_CORE1_CFG", 1029, 1 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_MSRAM128KX64_CFG", 1051, 1 }, + { "MCU_TIMER0", 1056, 1 }, + { "MCU_TIMER9", 1065, 1 }, + { "MCU_USART0", 1120, 1 }, + { "MCU_I2C0", 1152, 1 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_PSC0", 129, 1 }, + { "WKUP_PLL_CTRL0", 130, 1 }, + { "WKUP_CTRL_MMR0", 131, 16 }, + { "WKUP_GPIO0", 132, 1 }, + { "WKUP_I2C0", 144, 1 }, + { "WKUP_USART0", 160, 1 }, +}, navss_cbass0_fwls[] = { + { "NACSS_VIRT0", 6253, 1 }, +}; + static void ctrl_mmr_unlock(void) { /* Unlock all WKUP_CTRL_MMR0 module registers */ @@ -150,6 +195,14 @@ void k3_spl_init(void) if (ret) panic("Failed to initialize clk-k3!\n"); } + + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); + remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls)); } /* Output System Firmware version info */ @@ -182,6 +235,69 @@ void k3_mem_init(void) spl_enable_dcache(); } +/* Support for the various EVM / SK families */ +#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT) +void do_dt_magic(void) +{ + int ret, rescan, mmc_dev = -1; + static struct mmc *mmc; + + do_board_detect(); + + /* + * Board detection has been done. + * Let us see if another dtb wouldn't be a better match + * for our board + */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } + } + + /* + * Because of multi DTB configuration, the MMC device has + * to be re-initialized after reconfiguring FDT inorder to + * boot from MMC. Do this when boot mode is MMC and ROM has + * not loaded SYSFW. + */ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + mmc_dev = 0; + break; + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: + mmc_dev = 1; + break; + } + + if (mmc_dev > 0 && !check_rom_loaded_sysfw()) { + ret = mmc_init_device(mmc_dev); + if (!ret) { + mmc = find_mmc_device(mmc_dev); + if (mmc) { + ret = mmc_init(mmc); + if (ret) + printf("mmc init failed with error: %d\n", ret); + } + } + } +} +#endif + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + k3_spl_init(); +#if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT) + do_dt_magic(); +#endif + k3_mem_init(); +} +#endif + u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { @@ -264,57 +380,3 @@ u32 spl_boot_device(void) else return __get_backup_bootmedia(main_devstat); } - -#define J721S2_DEV_MCU_RTI0 295 -#define J721S2_DEV_MCU_RTI1 296 -#define J721S2_DEV_MCU_ARMSS0_CPU0 284 -#define J721S2_DEV_MCU_ARMSS0_CPU1 285 - -void release_resources_for_core_shutdown(void) -{ - if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) { - struct ti_sci_handle *ti_sci; - struct ti_sci_dev_ops *dev_ops; - struct ti_sci_proc_ops *proc_ops; - int ret; - u32 i; - - const u32 put_device_ids[] = { - J721S2_DEV_MCU_RTI0, - J721S2_DEV_MCU_RTI1, - }; - - ti_sci = get_ti_sci_handle(); - dev_ops = &ti_sci->ops.dev_ops; - proc_ops = &ti_sci->ops.proc_ops; - - /* Iterate through list of devices to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { - u32 id = put_device_ids[i]; - - ret = dev_ops->put_device(ti_sci, id); - if (ret) - panic("Failed to put device %u (%d)\n", id, ret); - } - - const u32 put_core_ids[] = { - J721S2_DEV_MCU_ARMSS0_CPU1, - J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ - }; - - /* Iterate through list of cores to put (shutdown) */ - for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { - u32 id = put_core_ids[i]; - - /* - * Queue up the core shutdown request. Note that this call - * needs to be followed up by an actual invocation of an WFE - * or WFI CPU instruction. - */ - ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); - if (ret) - panic("Failed sending core %u shutdown message (%d)\n", - id, ret); - } - } -} diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 092588f4b5e..6179f7373aa 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -17,7 +17,6 @@ #include <linux/soc/ti/ti_sci_protocol.h> #include <mach/spl.h> #include <spl.h> -#include <asm/arch/sys_proto.h> #include <linux/dma-mapping.h> #include "common.h" diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index c4c5c371100..9be2d9eaea2 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -23,7 +23,6 @@ #include <spi_flash.h> #include <asm/io.h> -#include <asm/arch/sys_proto.h> #include "common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-k3/include/mach/sysfw-loader.h b/arch/arm/mach-k3/sysfw-loader.h index b23a9e821ed..b23a9e821ed 100644 --- a/arch/arm/mach-k3/include/mach/sysfw-loader.h +++ b/arch/arm/mach-k3/sysfw-loader.h diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S index ab7cdcf3d42..1ab9472e198 100644 --- a/arch/arm/mach-omap2/omap3/lowlevel_init.S +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -15,13 +15,14 @@ #include <asm/arch/clocks_omap3.h> #include <linux/linkage.h> +.arch_extension sec + /* * Funtion for making PPA HAL API calls in secure devices * Input: * R0 - Service ID * R1 - paramer list */ -/* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */ ENTRY(do_omap3_emu_romcode_call) PUSH {r4-r12, lr} @ Save all registers from ROM code! MOV r12, r0 @ Copy the Secure Service ID in R12 @@ -32,8 +33,7 @@ ENTRY(do_omap3_emu_romcode_call) MOV r6, #0xFF @ Indicate new Task call mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled - @ because we use -march=armv5 + SMC #1 @ Call PPA service POP {r4-r12, pc} ENDPROC(do_omap3_emu_romcode_call) diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 0787d192b69..5394529658b 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -17,9 +17,6 @@ choice config TARGET_CM_T54 bool "CompuLab CM-T54" -config TARGET_OMAP5_UEVM - bool "TI OMAP5 uEVM board" - config TARGET_DRA7XX_EVM bool "TI DRA7XX" select BOARD_LATE_INIT @@ -162,7 +159,6 @@ endchoice endmenu endif -source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" source "board/ti/am57xx/Kconfig" diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index bee59c3bea4..f20d58b4de6 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -31,7 +31,7 @@ config MPC8xx select CREATE_ARCH_SYMLINK select BOARD_EARLY_INIT_F imply CMD_REGINFO - imply WDT_MPC8xx + imply WDT_MPC8xxx endchoice diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b695c7e4d81..582e1412211 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -20,6 +20,10 @@ choice prompt "Target select" optional +config TARGET_CMPCPRO + bool "Support CMPCPRO board from CSSI" + select ARCH_MPC832X + config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -205,5 +209,6 @@ config NEVER_ASSERT_ODT_TO_CPU source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" +source "board/cssi/cmpcpro/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig index 218920cfc9a..1cdb390e79b 100644 --- a/arch/powerpc/cpu/mpc83xx/bats/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig @@ -65,18 +65,12 @@ config BAT0_ACCESS_RW endchoice -config BAT0_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT0_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT0_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT0_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT0_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -120,22 +114,10 @@ config BAT0_PAGE_PROTECTION config BAT0_WIMG_ICACHE hex - default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x0 if !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE config BAT0_WIMG_DCACHE hex @@ -228,18 +210,12 @@ config BAT1_ACCESS_RW endchoice -config BAT1_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT1_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT1_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT1_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT1_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -283,22 +259,10 @@ config BAT1_PAGE_PROTECTION config BAT1_WIMG_ICACHE hex - default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x0 if !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE config BAT1_WIMG_DCACHE hex @@ -391,18 +355,12 @@ config BAT2_ACCESS_RW endchoice -config BAT2_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT2_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT2_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT2_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT2_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -446,22 +404,10 @@ config BAT2_PAGE_PROTECTION config BAT2_WIMG_ICACHE hex - default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x0 if !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE config BAT2_WIMG_DCACHE hex @@ -554,18 +500,12 @@ config BAT3_ACCESS_RW endchoice -config BAT3_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT3_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT3_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT3_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT3_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -609,22 +549,10 @@ config BAT3_PAGE_PROTECTION config BAT3_WIMG_ICACHE hex - default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x0 if !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE config BAT3_WIMG_DCACHE hex @@ -719,18 +647,12 @@ config BAT4_ACCESS_RW endchoice -config BAT4_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT4_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT4_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT4_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT4_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -774,22 +696,10 @@ config BAT4_PAGE_PROTECTION config BAT4_WIMG_ICACHE hex - default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x0 if !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE config BAT4_WIMG_DCACHE hex @@ -882,18 +792,12 @@ config BAT5_ACCESS_RW endchoice -config BAT5_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT5_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT5_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT5_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT5_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -937,22 +841,10 @@ config BAT5_PAGE_PROTECTION config BAT5_WIMG_ICACHE hex - default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x0 if !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE config BAT5_WIMG_DCACHE hex @@ -1045,18 +937,12 @@ config BAT6_ACCESS_RW endchoice -config BAT6_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT6_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT6_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT6_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT6_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -1100,22 +986,10 @@ config BAT6_PAGE_PROTECTION config BAT6_WIMG_ICACHE hex - default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x0 if !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE config BAT6_WIMG_DCACHE hex @@ -1208,18 +1082,12 @@ config BAT7_ACCESS_RW endchoice -config BAT7_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT7_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT7_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT7_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT7_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -1263,22 +1131,10 @@ config BAT7_PAGE_PROTECTION config BAT7_WIMG_ICACHE hex - default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x0 if !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE config BAT7_WIMG_DCACHE hex diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index a6c063556e8..f6ffe295b8e 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -165,7 +165,7 @@ unsigned long get_tbclk(void) } #endif -#if defined(CONFIG_WATCHDOG) +#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT) void watchdog_reset (void) { int re_enable = disable_interrupts(); diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index b67ccd661d3..44f66cd5287 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -539,8 +539,7 @@ config DDR_MC_CLOCK_MODE config SYSTEM_PLL_VCO_DIV int - default 0 if ARCH_MPC832X - default 2 if ARCH_MPC8313 + default 2 if ARCH_MPC8313 || ARCH_MPC832X default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index e3878e431fb..6749263da8a 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -215,6 +215,7 @@ in_flash: * gt-regs BAT can be reused after board_init_f calls * board_early_init_f (EVB only). */ +#ifdef CONFIG_SYS_INIT_RAM_LOCK /* enable address translation */ bl enable_addr_trans sync @@ -222,7 +223,6 @@ in_flash: /* enable the data cache */ bl dcache_enable sync -#ifdef CONFIG_SYS_INIT_RAM_LOCK bl lock_ram_in_cache sync #endif @@ -483,6 +483,7 @@ init_e300_core: /* time t 10 */ lis r3, CONFIG_SYS_IMMR@h +#ifndef CONFIG_WDT_MPC8xxx #if defined(CONFIG_WATCHDOG) /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ @@ -508,6 +509,7 @@ init_e300_core: /* time t 10 */ stw r4, SWCRR(r3) 1: #endif /* CONFIG_WATCHDOG */ +#endif #if defined(CONFIG_MASK_AER_AO) /* Write the Arbiter Event Enable to mask Address Only traps. */ diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 628d3617bc8..bfd903bc107 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -30,9 +30,6 @@ config MPC885 endchoice -config 8xx_GCLK_FREQ - int "CPU GCLK Frequency" - comment "Specific commands" config CMD_IMMAP @@ -51,7 +48,8 @@ config SYS_SIUMCR SIU Module Configuration (11-6) config SYS_SYPCR - hex "SYPCR register" + hex "SYPCR register" if !WDT_MPC8xxx + default 0 help System Protection Control (11-9) diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 86b08a61749..feef792ee77 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -26,10 +26,9 @@ void cpu_init_f(immap_t __iomem *immr) /* SYPCR - contains watchdog control (11-9) */ -#ifndef CONFIG_HW_WATCHDOG /* deactivate watchdog if not enabled in config */ - out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); -#endif + if (!IS_ENABLED(CONFIG_WDT_MPC8xxx)) + out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); schedule(); diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index ad3d3f9101c..1a882a38820 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; /* - * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ + * get_clocks() fills in gd->cpu_clk depending on CONFIG_SYS_CLK_FREQ */ int get_clocks(void) { @@ -28,7 +28,7 @@ int get_clocks(void) * (For example, the cogent CMA286-60 CPU module has no * separate oscillator for PITRTCLK) */ - gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; if ((sccr & SCCR_EBDF11) == 0) { /* No Bus Divider active */ diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 26b592b85db..bb436f02bcf 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb +dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts index adda0f3e9dd..7b9566a0fa4 100644 --- a/arch/powerpc/dts/cmpc885.dts +++ b/arch/powerpc/dts/cmpc885.dts @@ -18,11 +18,6 @@ stdout-path = &SERIAL; }; - WDT: watchdog@0 { - device_type = "watchdog"; - compatible = "fsl,pq1-wdt"; - }; - SERIAL: serial { compatible = "fsl,pq1-smc"; }; @@ -43,6 +38,13 @@ ranges = <0 0xff000000 0x4000>; reg = <0xff000000 0x00000200>; + WDT: watchdog@0 { + compatible = "fsl,pq1-wdt"; + reg = <0x0 0x10>; + timeout-sec = <2>; + hw_margin_ms = <1000>; + }; + CPM1_PIO_B: gpio-controller@ab8 { #gpio-cells = <2>; compatible = "fsl,cpm1-pario-bank-b"; diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts new file mode 100644 index 00000000000..c27d9dba335 --- /dev/null +++ b/arch/powerpc/dts/cmpcpro.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CMPC885 Device Tree Source + * + * Copyright 2020 CS GROUP France + * + */ + +/dts-v1/; + +#include <dt-bindings/clk/mpc83xx-clk.h> + +/ { + model = "CMPCPRO"; + compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + stdout-path = &serial0; + }; + WDT: watchdog@0 { + device_type = "watchdog"; + compatible = "fsl,pq1-wdt"; + }; + + aliases { + ethernet0 = ð0; + etehrnet1 = ð1; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + PowerPC,8321@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <0x20>; // 32 bytes + i-cache-line-size = <0x20>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + soc8321@b0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xb0000000 0x00100000>; + reg = <0xb0000000 0x00000200>; + bus-frequency = <0>; + pmc: power@b00 { + compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + serial0: serial@4500 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + ipic:pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + compatible = "fsl,mpc8323-qe-pario","simple-bus"; + device_type = "par_io"; + num-ports = <7>; + qe_pio_a: gpio-controller@1400 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1400 0x18>; + gpio-controller; + }; + qe_pio_b: gpio-controller@1418 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1418 0x18>; + gpio-controller; + }; + qe_pio_c: gpio-controller@1430 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1430 0x18>; + gpio-controller; + }; + qe_pio_d: gpio-controller@1448 { + #gpio-cells = <2>; + compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; + reg = <0x1448 0x18>; + gpio-controller; + }; + }; + }; + socclocks: clocks { + bootph-all; + compatible = "fsl,mpc832x-clk"; + #clock-cells = <1>; + }; + qe@b0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe","simple-bus"; + ranges = <0x0 0xb0100000 0x00100000>; + reg = <0xb0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <198000000>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + spi@4c0 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc832x-spi"; + reg = <0x4c0 0x40>; + mode = "cpu"; + gpios = <&qe_pio_d 3 1>; + clock-frequency = <0>; + eeprom@3 { + compatible = "atmel,at25", "cs,eeprom"; + cell-index = <1>; + }; + }; + eth0: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + rx-clock-name = "clk17"; + tx-clock-name = "clk17"; + phy-handle = <&phy1>; + phy-connection-type = "rmii"; + }; + eth1: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + rx-clock-name = "clk12"; + tx-clock-name = "clk12"; + phy-handle = <&phy2>; + phy-connection-type = "rmii"; + }; + mdio@3120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3120 0x18>; + compatible = "fsl,ucc-mdio"; + phy1:ethernet-phy@1 { + interrupt-parent = <&ipic>; + reg = <0x1>; + interrupts = <17 8>; + device_type = "ethernet-phy"; + }; + phy2:ethernet-phy@2 { + interrupt-parent = <&ipic>; + reg = <0x2>; + interrupts = <17 8>; + device_type = "ethernet-phy"; + }; + }; + }; +}; diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts index 5f32d8a2e55..c4d7737bc67 100644 --- a/arch/powerpc/dts/mcr3000.dts +++ b/arch/powerpc/dts/mcr3000.dts @@ -9,9 +9,25 @@ /dts-v1/; / { - WDT: watchdog@0 { - compatible = "fsl,pq1-wdt"; + #address-cells = <1>; + #size-cells = <1>; + + soc: immr@ff000000 { + #address-cells = <1>; + #size-cells = <1>; + device-type = "soc"; + compatible = "simple-bus"; + ranges = <0 0xff000000 0x4000>; + reg = <0xff000000 0x00000200>; + + WDT: watchdog@0 { + compatible = "fsl,pq1-wdt"; + reg = <0x0 0x10>; + timeout-sec = <2>; + hw_margin_ms = <1000>; + }; }; + SERIAL: smc@0 { compatible = "fsl,pq1-smc"; }; diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts index 2e7c8f103c3..3db5ececaec 100644 --- a/arch/powerpc/dts/mpc8379erdb.dts +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -13,6 +13,11 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -60,6 +65,28 @@ clock-frequency = <0>; }; + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <333333000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + bootph-all; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <333333000>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + bootph-all; + }; + ipic: interrupt-controller@700 { compatible = "fsl,ipic"; interrupt-controller; diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 19c2506c9b1..df95d2238fd 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -22,6 +22,11 @@ struct mpc8xxx_gpio_plat { uint ngpios; }; +struct qe_gpio_plat { + ulong addr; + unsigned long size; +}; + #ifndef DM_GPIO void mpc83xx_gpio_init_f(void); void mpc83xx_gpio_init_r(void); diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h index 39bf7d5a7f9..ce54f9bebbe 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h @@ -18,14 +18,14 @@ enum soc_type { SOC_MPC8379, }; -bool mpc83xx_has_sdhc(int type) +static inline bool mpc83xx_has_sdhc(int type) { return (type == SOC_MPC8308) || (type == SOC_MPC8309) || (type == SOC_MPC8379); } -bool mpc83xx_has_tsec(int type) +static inline bool mpc83xx_has_tsec(int type) { return (type == SOC_MPC8308) || (type == SOC_MPC8313) || @@ -34,37 +34,37 @@ bool mpc83xx_has_tsec(int type) (type == SOC_MPC8379); } -bool mpc83xx_has_pcie1(int type) +static inline bool mpc83xx_has_pcie1(int type) { return (type == SOC_MPC8308) || (type == SOC_MPC8315) || (type == SOC_MPC8379); } -bool mpc83xx_has_pcie2(int type) +static inline bool mpc83xx_has_pcie2(int type) { return (type == SOC_MPC8315) || (type == SOC_MPC8379); } -bool mpc83xx_has_sata(int type) +static inline bool mpc83xx_has_sata(int type) { return (type == SOC_MPC8315) || (type == SOC_MPC8379); } -bool mpc83xx_has_pci(int type) +static inline bool mpc83xx_has_pci(int type) { return type != SOC_MPC8308; } -bool mpc83xx_has_second_i2c(int type) +static inline bool mpc83xx_has_second_i2c(int type) { return (type != SOC_MPC8315) && (type != SOC_MPC832X); } -bool mpc83xx_has_quicc_engine(int type) +static inline bool mpc83xx_has_quicc_engine(int type) { return (type == SOC_MPC8309) || (type == SOC_MPC832X) || diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 83cfe23b4e7..8e9411aefb3 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -12,6 +12,7 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8313) || \ + defined(CONFIG_ARCH_MPC832X) || \ defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_ARCH_MPC837X) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 636d3545b95..51496338ad6 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -31,7 +31,7 @@ static struct udevice *map_dev; unsigned long map_len; #endif -void sandbox_exit(void) +void __noreturn sandbox_exit(void) { /* Do this here while it still has an effect */ os_fd_restore(); @@ -230,7 +230,7 @@ phys_addr_t map_to_sysmem(const void *ptr) return mentry->tag; } -unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size) +unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size) { struct sandbox_state *state = state_get_current(); diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 5e66304e2b9..9e93a0fa571 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -166,7 +166,7 @@ int os_write_file(const char *fname, const void *buf, int size) return 0; } -int os_filesize(int fd) +off_t os_filesize(int fd) { off_t size; @@ -218,7 +218,7 @@ err: int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep) { void *ptr; - int size; + off_t size; int ifd; ifd = os_open(pathname, os_flags); @@ -231,6 +231,10 @@ int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep) printf("Cannot get file size of '%s'\n", pathname); return -EIO; } + if ((unsigned long long)size > (unsigned long long)SIZE_MAX) { + printf("File '%s' too large to map\n", pathname); + return -EIO; + } ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0); if (ptr == MAP_FAILED) { diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 69da378ab59..d67834988fd 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -10,6 +10,7 @@ #include <fdtdec.h> #include <log.h> #include <os.h> +#include <trace.h> #include <asm/malloc.h> #include <asm/state.h> #include <asm/test.h> @@ -525,6 +526,10 @@ int state_uninit(void) if (state->jumped_fname) os_unlink(state->jumped_fname); + /* Disable tracing before unmapping RAM */ + if (IS_ENABLED(CONFIG_TRACE)) + trace_set_enabled(0); + os_free(state->state_fdt); os_free(state->ram_buf); memset(state, '\0', sizeof(*state)); diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index f21fc181f37..195365580a7 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -89,6 +89,19 @@ cs-gpios = <0>, <&gpio_a 0>; }; + nvmxip-qspi1@08000000 { + compatible = "nvmxip,qspi"; + reg = /bits/ 64 <0x08000000 0x00200000>; + lba_shift = <9>; + lba = <4096>; + }; + + nvmxip-qspi2@08200000 { + compatible = "nvmxip,qspi"; + reg = /bits/ 64 <0x08200000 0x00100000>; + lba_shift = <9>; + lba = <2048>; + }; }; #include "sandbox.dtsi" diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 7c1ee71cb7c..453e53db71a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1802,6 +1802,24 @@ compatible = "u-boot,fwu-mdata-gpt"; fwu-mdata-store = <&mmc0>; }; + + nvmxip-qspi1@08000000 { + compatible = "nvmxip,qspi"; + reg = <0x08000000 0x00200000>; + lba_shift = <9>; + lba = <4096>; + }; + + nvmxip-qspi2@08200000 { + compatible = "nvmxip,qspi"; + reg = <0x08200000 0x00100000>; + lba_shift = <9>; + lba = <2048>; + }; + + extcon { + compatible = "sandbox,extcon"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index ad6c29a4e26..31ab7289b4b 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -45,7 +45,7 @@ static inline void unmap_sysmem(const void *vaddr) /* Map from a pointer to our RAM buffer */ phys_addr_t map_to_sysmem(const void *ptr); -unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size); +unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size); void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); #define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8) diff --git a/arch/sandbox/include/asm/posix_types.h b/arch/sandbox/include/asm/posix_types.h index ec18ed7e3c2..e1442c455bd 100644 --- a/arch/sandbox/include/asm/posix_types.h +++ b/arch/sandbox/include/asm/posix_types.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * linux/include/asm-arm/posix_types.h + * Based on linux/include/asm-arm/posix_types.h * * Copyright (C) 1996-1998 Russell King. * @@ -10,8 +11,8 @@ * Changelog: * 27-06-1996 RMK Created */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H +#ifndef __ARCH_SANDBOX_POSIX_TYPES_H +#define __ARCH_SANDBOX_POSIX_TYPES_H /* * This file is generally used by user-level software, so you need to diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h index 9eb19323ecf..e7027747b37 100644 --- a/arch/sandbox/include/asm/u-boot-sandbox.h +++ b/arch/sandbox/include/asm/u-boot-sandbox.h @@ -87,6 +87,6 @@ void sandbox_set_enable_pci_map(int enable); void sandbox_reset(void); /* Exit sandbox (quit U-Boot) */ -void sandbox_exit(void); +void __noreturn sandbox_exit(void); #endif /* _U_BOOT_SANDBOX_H_ */ |