summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/am335x-icev2.dts50
-rw-r--r--arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi28
-rw-r--r--arch/arm/dts/k3-j7200-common-proc-board.dts7
-rw-r--r--arch/arm/dts/k3-j7200-main.dtsi40
-rw-r--r--arch/arm/dts/k3-j7200-mcu-wakeup.dtsi40
-rw-r--r--arch/arm/dts/k3-j7200-r5-common-proc-board.dts46
-rw-r--r--arch/arm/dts/k3-j721e-main.dtsi2
-rw-r--r--arch/arm/mach-k3/arm64-mmu.c59
-rw-r--r--arch/arm/mach-k3/include/mach/j721e_spl.h1
-rw-r--r--arch/arm/mach-omap2/am33xx/board.c18
10 files changed, 289 insertions, 2 deletions
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index 37484cb6f56..2a1b3a53e9b 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -436,3 +436,53 @@
reg = <3>;
};
};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_default>;
+
+ sn65hvs882@1 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+
+ spi_nor: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q64", "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "u-boot";
+ reg = <0x80000 0x100000>;
+ read-only;
+ };
+
+ partition@2 {
+ label = "u-boot-env";
+ reg = <0x180000 0x20000>;
+ read-only;
+ };
+
+ partition@3 {
+ label = "misc";
+ reg = <0x1A0000 0x660000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 4972a7559f0..0a5faa21349 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -131,3 +131,31 @@
dr_mode = "peripheral";
u-boot,dm-spl;
};
+
+&wkup_gpio_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_gpio0 {
+ u-boot,dm-spl;
+};
+
+&mcu_fss0_hpb0_pins_default {
+ u-boot,dm-spl;
+};
+
+&fss {
+ u-boot,dm-spl;
+};
+
+&hbmc {
+ u-boot,dm-spl;
+
+ flash@0,0 {
+ u-boot,dm-spl;
+ };
+};
+
+&hbmc_mux {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 3f1d03c9603..cc3d933cbb5 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -13,6 +13,13 @@
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
+
+ aliases {
+ remoteproc0 = &mcu_r5fss0_core0;
+ remoteproc1 = &mcu_r5fss0_core1;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
+ };
};
&wkup_pmx0 {
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index aaa1fdd5a3c..c25f03cf23d 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -340,4 +340,44 @@
dr_mode = "otg";
};
};
+
+ main_r5fss0: r5fss@5c00000 {
+ compatible = "ti,j7200-r5fss";
+ lockstep-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+ <0x5d00000 0x00 0x5d00000 0x20000>;
+ power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@5c00000 {
+ compatible = "ti,j7200-r5f";
+ reg = <0x5c00000 0x00010000>,
+ <0x5c10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <245>;
+ ti,sci-proc-ids = <0x06 0xFF>;
+ resets = <&k3_reset 245 1>;
+ firmware-name = "j7200-main-r5f0_0-fw";
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@5d00000 {
+ compatible = "ti,j7200-r5f";
+ reg = <0x5d00000 0x00008000>,
+ <0x5d10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <246>;
+ ti,sci-proc-ids = <0x07 0xFF>;
+ resets = <&k3_reset 246 1>;
+ firmware-name = "j7200-main-r5f0_1-fw";
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 4c899c8aca5..75c0c8597dc 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -269,4 +269,44 @@
ti,cpts-periodic-outputs = <2>;
};
};
+
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,j7200-r5fss";
+ lockstep-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,j7200-r5f";
+ reg = <0x41000000 0x00010000>,
+ <0x41010000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <250>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 250 1>;
+ firmware-name = "j7200-mcu-r5f0_0-fw";
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,j7200-r5f";
+ reg = <0x41400000 0x00008000>,
+ <0x41410000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <251>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 251 1>;
+ firmware-name = "j7200-mcu-r5f0_1-fw";
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index f5e4166926d..db63d93777e 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -18,6 +18,12 @@
chosen {
stdout-path = &main_uart0;
tick-timer = &timer1;
+ firmware-loader = &fs_loader0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
};
a72_0: a72@0 {
@@ -107,6 +113,31 @@
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
+
+ mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+ J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+ J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+ >;
+ };
+
+ wkup_gpio_pins_default: wkup-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
+ >;
+ };
};
&main_pmx0 {
@@ -214,4 +245,19 @@
maximum-speed = "high-speed";
};
+&hbmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+ ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
+ <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
+
+ flash@0,0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ };
+};
+
#include "k3-j7200-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index a285b1afa84..33db74a267a 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -302,7 +302,7 @@
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721e-r5fss";
- lockstep-mode = <1>;
+ lockstep-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 95f830b7ffe..a0da3df5938 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -2,8 +2,9 @@
/*
* K3: ARM64 MMU setup
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
+ * Suman Anna <s-anna@ti.com>
* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
*
*/
@@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map;
#endif /* CONFIG_SOC_K3_AM6 */
#ifdef CONFIG_SOC_K3_J721E
+
+#ifdef CONFIG_TARGET_J721E_A72_EVM
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
@@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
};
struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_TARGET_J721E_A72_EVM */
+
+#ifdef CONFIG_TARGET_J7200_A72_EVM
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xa0000000UL,
+ .phys = 0xa0000000UL,
+ .size = 0x04800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0xa4800000UL,
+ .phys = 0xa4800000UL,
+ .size = 0x5b800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = j7200_mem_map;
+#endif /* CONFIG_TARGET_J7200_A72_EVM */
+
#endif /* CONFIG_SOC_K3_J721E */
diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index 3fa85ca3b67..e8947917a6b 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -15,6 +15,7 @@
#define BOOT_DEVICE_ETHERNET 0x04
#define BOOT_DEVICE_I2C 0x06
#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
/* With BootMode B = 1 */
#define BOOT_DEVICE_MMC2 0x10
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index a7b56b6bb3d..2888390d240 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -14,6 +14,7 @@
#include <init.h>
#include <net.h>
#include <ns16550.h>
+#include <omap3_spi.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
@@ -49,6 +50,12 @@
#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
#define AM43XX_RDWRLVLFULL_START 0x80000000
+/* SPI flash. */
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+#define AM33XX_SPI0_BASE 0x48030000
+#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
@@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
#endif
};
#endif
+#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap3_spi_plat omap3_spi_pdata = {
+ .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
+ .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
+};
+
+U_BOOT_DEVICE(am33xx_spi) = {
+ .name = "omap3_spi",
+ .platdata = &omap3_spi_pdata,
+};
+#endif
#endif
#if !CONFIG_IS_ENABLED(DM_GPIO)
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 19:03:50 +0000