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-rw-r--r--arch/arm/dts/k3-j721e-main.dtsi19
-rw-r--r--arch/arm/dts/sunxi-u-boot.dtsi4
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h11
-rw-r--r--arch/arm/mach-sunxi/Kconfig1
-rw-r--r--arch/arm/mach-sunxi/dram_sunxi_dw.c149
-rw-r--r--arch/sandbox/dts/test.dts72
6 files changed, 221 insertions, 35 deletions
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index e47b6c0eb70..07b489679ed 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -1078,13 +1078,12 @@
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
bus-width = <8>;
- mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
mmc-ddr-1_8v;
ti,otap-del-sel-legacy = <0xf>;
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
- ti,otap-del-sel-hs400 = <0x0>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
@@ -1102,14 +1101,20 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+ sdhci-caps-mask = <0x2 0x0>;
};
main_sdhci2: sdhci@4f98000 {
@@ -1122,14 +1127,20 @@
assigned-clocks = <&k3_clks 93 0>;
assigned-clock-parents = <&k3_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
+ sdhci-caps-mask = <0x2 0x0>;
};
usbss0: cdns-usb@4104000 {
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index cd096bf2a06..a4227a3c22d 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -42,7 +42,7 @@
os = "u-boot";
arch = "arm64";
compression = "none";
- load = <0x4a000000>;
+ load = <CONFIG_SYS_TEXT_BASE>;
u-boot-nodtb {
};
@@ -86,7 +86,7 @@
};
configurations {
- default = "config-1";
+ default = "@config-DEFAULT-SEQ";
@config-SEQ {
description = "NAME";
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
index a5a7ebde44e..e843c14202b 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS and DQSN */
#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
-struct dram_para {
+
+struct rank_para {
u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
u8 row_bits;
u8 bank_bits;
+};
+
+struct dram_para {
+ u8 dual_rank;
+ u8 bus_full_width;
+ struct rank_para ranks[2];
const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 ac_delays[31];
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index a29d11505aa..8e9012dbbfe 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -973,6 +973,7 @@ config VIDEO_DE2
depends on SUNXI_DE2
select DM_VIDEO
select DISPLAY
+ select VIDEO_DW_HDMI
imply VIDEO_DT_SIMPLEFB
default y
---help---
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index d0600011ffa..9107b114df5 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -399,18 +399,24 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
#else
#error Unsupported DRAM type!
#endif
- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
+ (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
- MCTL_CR_PAGE_SIZE(para->page_size) |
- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+ MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) |
+ MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr);
+
+ if (para->dual_rank && (socid == SOCID_A64 || socid == SOCID_R40)) {
+ writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
+ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
+ MCTL_CR_DUAL_RANK |
+ MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) |
+ MCTL_CR_ROW_BITS(para->ranks[1].row_bits), &mctl_com->cr_r1);
+ }
if (socid == SOCID_R40) {
- if (para->dual_rank)
- panic("Dual rank memory not supported\n");
-
/* Mux pin to A15 address line for single rank memory. */
- setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
+ if (!para->dual_rank)
+ setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
}
}
@@ -646,35 +652,105 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
return 0;
}
-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
+/*
+ * Test if memory at offset offset matches memory at a certain base
+ */
+static bool mctl_mem_matches_base(u32 offset, ulong base)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, base);
+ writel(0xaa55aa55, base + offset);
+ dsb();
+ /* Check if the same value is actually observed when reading back */
+ return readl(base) ==
+ readl(base + offset);
+}
+
+static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank)
{
/* detect row address bits */
- para->page_size = 512;
- para->row_bits = 16;
- para->bank_bits = 2;
+ rank->page_size = 512;
+ rank->row_bits = 16;
+ rank->bank_bits = 2;
mctl_set_cr(socid, para);
- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
- if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
+ for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++)
+ if (mctl_mem_matches_base((1 << (rank->row_bits + rank->bank_bits)) * rank->page_size, base))
break;
/* detect bank address bits */
- para->bank_bits = 3;
+ rank->bank_bits = 3;
mctl_set_cr(socid, para);
- for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
- if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
+ for (rank->bank_bits = 2; rank->bank_bits < 3; rank->bank_bits++)
+ if (mctl_mem_matches_base((1 << rank->bank_bits) * rank->page_size, base))
break;
/* detect page size */
- para->page_size = 8192;
+ rank->page_size = 8192;
mctl_set_cr(socid, para);
- for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
- if (mctl_mem_matches(para->page_size))
+ for (rank->page_size = 512; rank->page_size < 8192; rank->page_size *= 2)
+ if (mctl_mem_matches_base(rank->page_size, base))
break;
}
+static unsigned long mctl_calc_rank_size(struct rank_para *rank)
+{
+ return (1UL << (rank->row_bits + rank->bank_bits)) * rank->page_size;
+}
+
+/*
+ * Because we cannot do mctl_phy_init(PIR_QSGATE) on R40 now (which leads
+ * to failure), it's needed to detect the rank count of R40 in another way.
+ *
+ * The code here is modelled after time_out_detect() in BSP, which tries to
+ * access the memory and check for error code.
+ *
+ * TODO: auto detect half DQ width here
+ */
+static void mctl_r40_detect_rank_count(struct dram_para *para)
+{
+ ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
+ mctl_calc_rank_size(&para->ranks[0]);
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ /* Enable read time out */
+ setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 25);
+
+ (void) readl((void *) rank1_base);
+ udelay(10);
+
+ if (readl(&mctl_ctl->pgsr[0]) & (0x1 << 13)) {
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
+ para->dual_rank = 0;
+ }
+
+ /* Reset PHY FIFO to clear it */
+ clrbits_le32(&mctl_ctl->pgcr[0], 0x1 << 26);
+ udelay(100);
+ setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 26);
+
+ /* Clear error status */
+ setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 24);
+
+ /* Clear time out flag */
+ clrbits_le32(&mctl_ctl->pgsr[0], 0x1 << 13);
+
+ /* Disable read time out */
+ clrbits_le32(&mctl_ctl->pgcr[0], 0x1 << 25);
+}
+
+static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
+{
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, &para->ranks[0]);
+
+ if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(&para->ranks[0]), &para->ranks[1]);
+ }
+}
+
/*
* The actual values used here are taken from Allwinner provided boot0
* binaries, though they are probably board specific, so would likely benefit
@@ -769,12 +845,23 @@ unsigned long sunxi_dram_init(void)
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ unsigned long size;
+
struct dram_para para = {
.dual_rank = 1,
.bus_full_width = 1,
- .row_bits = 15,
- .bank_bits = 3,
- .page_size = 4096,
+ .ranks = {
+ {
+ .row_bits = 15,
+ .bank_bits = 3,
+ .page_size = 4096,
+ },
+ {
+ .row_bits = 15,
+ .bank_bits = 3,
+ .page_size = 4096,
+ }
+ },
#if defined(CONFIG_MACH_SUN8I_H3)
.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
@@ -807,8 +894,6 @@ unsigned long sunxi_dram_init(void)
uint16_t socid = SOCID_H3;
#elif defined(CONFIG_MACH_SUN8I_R40)
uint16_t socid = SOCID_R40;
- /* Currently we cannot support R40 with dual rank memory */
- para.dual_rank = 0;
#elif defined(CONFIG_MACH_SUN8I_V3S)
uint16_t socid = SOCID_V3S;
#elif defined(CONFIG_MACH_SUN50I)
@@ -843,9 +928,21 @@ unsigned long sunxi_dram_init(void)
setbits_le32(&mctl_com->cccr, 1 << 31);
udelay(10);
+ if (socid == SOCID_R40) {
+ mctl_r40_detect_rank_count(&para);
+ mctl_set_cr(SOCID_R40, &para);
+ }
+
mctl_auto_detect_dram_size(socid, &para);
mctl_set_cr(socid, &para);
- return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
- (para.dual_rank ? 2 : 1);
+ size = mctl_calc_rank_size(&para.ranks[0]);
+ if (socid == SOCID_A64 || socid == SOCID_R40) {
+ if (para.dual_rank)
+ size += mctl_calc_rank_size(&para.ranks[1]);
+ } else if (para.dual_rank) {
+ size *= 2;
+ }
+
+ return size;
}
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index dde4efb9334..48240aa26f6 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -634,6 +634,9 @@
reg = <0 1>;
compatible = "sandbox,i2c";
clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_i2c0_pins>;
+
eeprom@2c {
reg = <0x2c>;
compatible = "i2c-eeprom";
@@ -714,6 +717,8 @@
lcd {
u-boot,dm-pre-reloc;
compatible = "sandbox,lcd-sdl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_lcd_pins>;
xres = <1366>;
yres = <768>;
};
@@ -964,6 +969,8 @@
pwm: pwm {
compatible = "sandbox,pwm";
#pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_pwm_pins>;
};
pwm2 {
@@ -1035,6 +1042,9 @@
reg = <0 1>;
compatible = "sandbox,spi";
cs-gpios = <0>, <0>, <&gpio_a 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_spi0_pins>;
+
spi.bin@0 {
reg = <0>;
compatible = "spansion,m25p16", "jedec,spi-nor";
@@ -1124,6 +1134,8 @@
uart0: serial {
compatible = "sandbox,serial";
u-boot,dm-pre-reloc;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_uart0_pins>;
};
usb_0: usb@0 {
@@ -1392,6 +1404,66 @@
};
};
+ pinctrl-single-no-width {
+ compatible = "pinctrl-single";
+ reg = <0x0000 0x238>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,function-mask = <0x7f>;
+ };
+
+ pinctrl-single-pins {
+ compatible = "pinctrl-single";
+ reg = <0x0000 0x238>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x7f>;
+
+ pinmux_pwm_pins: pinmux_pwm_pins {
+ pinctrl-single,pins = < 0x48 0x06 >;
+ };
+
+ pinmux_spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins = <
+ 0x190 0x0c
+ 0x194 0x0c
+ 0x198 0x23
+ 0x19c 0x0c
+ >;
+ };
+
+ pinmux_uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x70 0x30
+ 0x74 0x00
+ >;
+ };
+ };
+
+ pinctrl-single-bits {
+ compatible = "pinctrl-single";
+ reg = <0x0000 0x50>;
+ #pinctrl-cells = <2>;
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xf>;
+
+ pinmux_i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,bits = <
+ 0x10 0x00002200 0x0000ff00
+ >;
+ };
+
+ pinmux_lcd_pins: pinmux_lcd_pins {
+ pinctrl-single,bits = <
+ 0x40 0x22222200 0xffffff00
+ 0x44 0x22222222 0xffffffff
+ 0x48 0x00000022 0x000000ff
+ 0x48 0x02000000 0x0f000000
+ 0x4c 0x02000022 0x0f0000ff
+ >;
+ };
+ };
+
hwspinlock@0 {
compatible = "sandbox,hwspinlock";
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-24 22:15:55 +0000