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-rw-r--r--arch/mips/Kconfig26
-rw-r--r--arch/mips/mach-jz47xx/include/mach/jz4780.h2
-rw-r--r--arch/mips/mach-jz47xx/jz4780/pll.c6
3 files changed, 20 insertions, 14 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2e0793a7a7b..9af0133f106 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -14,6 +14,7 @@ choice
config TARGET_MALTA
bool "Support malta"
+ select HAS_FIXED_TIMER_FREQUENCY
select BOARD_EARLY_INIT_R
select DM
select DM_SERIAL
@@ -39,27 +40,22 @@ config TARGET_MALTA
select SWAP_IO_SPACE
imply CMD_DM
-config TARGET_VCT
- bool "Support vct"
- select ROM_EXCEPTION_VECTORS
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select SYS_MIPS_CACHE_INIT_RAM_LOAD
-
config ARCH_ATH79
bool "Support QCA/Atheros ath79"
+ select HAS_FIXED_TIMER_FREQUENCY
select DM
select OF_CONTROL
imply CMD_DM
config ARCH_MSCC
bool "Support MSCC VCore-III"
+ select HAS_FIXED_TIMER_FREQUENCY
select OF_CONTROL
select DM
config ARCH_BMIPS
bool "Support BMIPS SoCs"
+ select HAS_FIXED_TIMER_FREQUENCY
select CLK
select CPU
select DM
@@ -70,6 +66,7 @@ config ARCH_BMIPS
config ARCH_MTMIPS
bool "Support MediaTek MIPS platforms"
+ select HAS_FIXED_TIMER_FREQUENCY
select CLK
imply CMD_DM
select DISPLAY_CPUINFO
@@ -96,6 +93,7 @@ config ARCH_MTMIPS
config ARCH_JZ47XX
bool "Support Ingenic JZ47xx"
select SUPPORT_SPL
+ select HAS_FIXED_TIMER_FREQUENCY
select OF_CONTROL
select DM
@@ -124,12 +122,14 @@ config ARCH_OCTEON
config MACH_PIC32
bool "Support Microchip PIC32"
+ select HAS_FIXED_TIMER_FREQUENCY
select DM
select OF_CONTROL
imply CMD_DM
config TARGET_BOSTON
bool "Support Boston"
+ select HAS_FIXED_TIMER_FREQUENCY
select DM
imply DM_EVENT
select DM_SERIAL
@@ -151,6 +151,7 @@ config TARGET_BOSTON
config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
+ select HAS_FIXED_TIMER_FREQUENCY
select DM
select DM_ETH
select DM_GPIO
@@ -254,6 +255,12 @@ config ROM_EXCEPTION_VECTORS
Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
In that case the image size will be reduced by 0x500 bytes.
+config SYS_MIPS_TIMER_FREQ
+ int "Fixed MIPS CPU timer frequency in Hz"
+ depends on HAS_FIXED_TIMER_FREQUENCY
+ help
+ Configures a fixed CPU timer frequency.
+
config MIPS_CM_BASE
hex "MIPS CM GCR Base Address"
depends on MIPS_CM
@@ -435,6 +442,9 @@ config SUPPORTS_CPU_MIPS64_R6
config SUPPORTS_CPU_MIPS64_OCTEON
bool
+config HAS_FIXED_TIMER_FREQUENCY
+ bool
+
config CPU_CAVIUM_OCTEON
bool
diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h b/arch/mips/mach-jz47xx/include/mach/jz4780.h
index 4422e503ed2..880445dac39 100644
--- a/arch/mips/mach-jz47xx/include/mach/jz4780.h
+++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h
@@ -60,7 +60,7 @@
/* PLL setup */
#define JZ4780_SYS_EXTAL 48000000
-#define JZ4780_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 1000000)
+#define JZ4780_SYS_MEM_SPEED (1200 * 1000000)
#define JZ4780_SYS_MEM_DIV 3
#define JZ4780_SYS_AUDIO_SPEED (768 * 1000000)
diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c
index 323c634fb32..4519b478ccb 100644
--- a/arch/mips/mach-jz47xx/jz4780/pll.c
+++ b/arch/mips/mach-jz47xx/jz4780/pll.c
@@ -399,11 +399,7 @@ static void cpu_mux_select(int pll)
((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
((1 - 1) << CPM_CPCCR_CDIV_BIT);
- if (CONFIG_SYS_MHZ >= 1000)
- clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
- else
- clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
-
+ clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |