diff options
Diffstat (limited to 'arch')
60 files changed, 1511 insertions, 228 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 35e2712fce9..2f3d07c13a1 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -61,6 +61,7 @@ config PPC config RISCV bool "RISC-V architecture" + select CREATE_ARCH_SYMLINK select SUPPORT_OF_CONTROL select OF_CONTROL select DM @@ -117,6 +118,7 @@ config SANDBOX imply VIRTIO_BLK imply VIRTIO_NET imply DM_SOUND + imply PCH config SH bool "SuperH architecture" @@ -160,6 +162,7 @@ config X86 imply USB_ETHER_ASIX imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER + imply PCH config XTENSA bool "Xtensa architecture" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 455f06cfee7..ded7c11a4c2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1083,6 +1083,32 @@ config TARGET_LS2081ARDB development platform that supports the QorIQ LS2081A/LS2041A Layerscape Architecture processor. +config TARGET_LX2160ARDB + bool "Support lx2160ardb" + select ARCH_LX2160A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_LATE_INIT + help + Support for NXP LX2160ARDB platform. + The lx2160ardb (LX2160A Reference design board (RDB) + is a high-performance development platform that supports the + QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. + +config TARGET_LX2160AQDS + bool "Support lx2160aqds" + select ARCH_LX2160A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_LATE_INIT + help + Support for NXP LX2160AQDS platform. + The lx2160aqds (LX2160A QorIQ Development System (QDS) + is a high-performance development platform that supports the + QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 @@ -1237,6 +1263,7 @@ config TARGET_LS1043AQDS select BOARD_LATE_INIT select SUPPORT_SPL imply SCSI + imply SCSI_AHCI help Support for Freescale LS1043AQDS platform. @@ -1248,7 +1275,6 @@ config TARGET_LS1043ARDB select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SUPPORT_SPL - imply SCSI help Support for Freescale LS1043ARDB platform. @@ -1555,6 +1581,7 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" +source "board/freescale/lx2160a/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 1c12bbde75a..f0536038d68 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -106,7 +106,8 @@ config PSCI_RESET !TARGET_LS1012AFRWY && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ - !TARGET_LS2081ARDB && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ + !TARGET_LX2160AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 01c5068ab6d..f48481f465a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -2,6 +2,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -23,6 +24,7 @@ config ARCH_LS1043A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -49,13 +51,12 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C2 select SYS_I2C_MXC_I2C3 select SYS_I2C_MXC_I2C4 - imply SCSI - imply SCSI_AHCI imply CMD_PCI config ARCH_LS1046A bool select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -90,6 +91,7 @@ config ARCH_LS1088A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT + select FSL_LAYERSCAPE select FSL_LSCH3 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -113,6 +115,8 @@ config ARCH_LS1088A select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_2 select FSL_TZASC_1 + select FSL_TZASC_400 + select FSL_TZPC_BP147 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC @@ -130,6 +134,7 @@ config ARCH_LS2080A select ARM_ERRATA_828024 select ARM_ERRATA_829520 select ARM_ERRATA_833471 + select FSL_LAYERSCAPE select FSL_LSCH3 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -145,6 +150,8 @@ config ARCH_LS2080A select SYS_FSL_SRDS_2 select FSL_TZASC_1 select FSL_TZASC_2 + select FSL_TZASC_400 + select FSL_TZPC_BP147 select SYS_FSL_ERRATUM_A008336 if !TFABOOT select SYS_FSL_ERRATUM_A008511 if !TFABOOT select SYS_FSL_ERRATUM_A008514 if !TFABOOT @@ -230,6 +237,9 @@ config FSL_MC_ENET menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 +config FSL_LAYERSCAPE + bool + config FSL_PCIE_COMPAT string "PCIe compatible of Kernel DT" depends on PCIE_LAYERSCAPE @@ -346,6 +356,12 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config EMC2305 + bool "Fan controller" + help + Enable the EMC2305 fan controller for configuration of fan + speed. + config SECURE_BOOT bool "Secure Boot" help @@ -404,6 +420,11 @@ config FSL_TZASC_1 config FSL_TZASC_2 bool +config FSL_TZASC_400 + bool + +config FSL_TZPC_BP147 + bool endmenu menu "Layerscape clock tree configuration" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index be21685eaa8..978d46b32fc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1099,15 +1099,29 @@ int arch_early_init_r(void) printf("Did not wake secondary cores\n"); } -#ifdef CONFIG_SYS_FSL_HAS_RGMII - fsl_rgmii_init(); -#endif - config_core_prefetch(); #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif +#ifdef CONFIG_SYS_FSL_HAS_RGMII + /* some dpmacs in armv8a based freescale layerscape SOCs can be + * configured via both serdes(sgmii, xfi, xlaui etc) bits and via + * EC*_PMUX(rgmii) bits in RCW. + * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from + * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits + * Now if a dpmac is enabled by serdes bits then it takes precedence + * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol + * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, + * then the dpmac is SGMII and not RGMII. + * + * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in + * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled + * or not? if it is (fsl_serdes_init has already enabled the dpmac), + * then don't enable it. + */ + fsl_rgmii_init(); +#endif #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index ab1be3fa54c..1a747a9e3d6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -548,12 +548,32 @@ void fsl_serdes_init(void) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int i , j; +#ifdef CONFIG_ARCH_LX2160A + for (i = XFI1, j = 1; i <= XFI14; i++, j++) + xfi_dpmac[i] = j; + + for (i = SGMII1, j = 1; i <= SGMII18; i++, j++) + sgmii_dpmac[i] = j; + + for (i = _25GE1, j = 1; i <= _25GE10; i++, j++) + a25gaui_dpmac[i] = j; + + for (i = _40GE1, j = 1; i <= _40GE2; i++, j++) + xlaui_dpmac[i] = j; + + for (i = _50GE1, j = 1; i <= _50GE2; i++, j++) + caui2_dpmac[i] = j; + + for (i = _100GE1, j = 1; i <= _100GE2; i++, j++) + caui4_dpmac[i] = j; +#else for (i = XFI1, j = 1; i <= XFI8; i++, j++) xfi_dpmac[i] = j; for (i = SGMII1, j = 1; i <= SGMII16; i++, j++) sgmii_dpmac[i] = j; #endif +#endif #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fbc0f8afea7..2a040b20a53 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -246,7 +246,9 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ - fsl-ls1088a-qds.dtb + fsl-ls1088a-qds.dtb \ + fsl-lx2160a-rdb.dtb \ + fsl-lx2160a-qds.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/am335x-brxre1.dts b/arch/arm/dts/am335x-brxre1.dts new file mode 100644 index 00000000000..708407daf2e --- /dev/null +++ b/arch/arm/dts/am335x-brxre1.dts @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 B&R Industrial Automation GmbH + * http://www.br-automation.com + * + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "BRXRE1 Panel"; + compatible = "ti,am33xx"; + + fset: factory-settings { + bl-version = " "; + order-no = " "; + cpu-order-no = " "; + hw-revision = " "; + serial-no = <0>; + device-id = <0xE681>; + parent-id = <0xE681>; + hw-variant = <0x3>; + hw-platform = <0x0>; + fram-offset = <0x1000>; + fram-size = <0x3000>; + cache-disable = <0x0>; + cpu-clock = <0x0>; + }; + chosen { + #address-cells = <1>; + #size-cells = <1>; + + bootargs = "console=ttyO0,115200 earlyprintk"; + stdout-path = &uart0; + + framebuffer: framebuffer@8fbe0000 { + display = <&lcdscreen0>; + compatible = "simple-framebuffer"; + status = "okay"; + reg = <0x8fbef000 (1024 * 600 * 4)>; + width = <1024>; + height = <600>; + stride = <(1024 * 4)>; + format = "a8r8g8b8"; + clocks = <&dpll_disp_m2_ck>, <&dpll_per_m2_ck>; + }; + }; + + aliases { + fset = &fset; + mmc = &mmc2; + spi0 = &spi0; + spi1 = &spi1; + touch0 = &burtouch0; + screen0 = &lcdscreen0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + panel { + compatible = "ti,tilcdc,panel"; + status = "okay"; + }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lcdscreen0: lcdscreen@0 { + status = "okay"; + compatible = "ti,tilcdc,panel"; + + backlight = <&tps_bl>; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: lcd { + clock-frequency = <9142857>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <43>; + hsync-len = <2>; + vfront-porch = <4>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <1>; + vsync-active = <1>; + pupdelay = <10>; + pondelay = <10>; + }; + }; + }; +}; + +&uart0 { /* console uart */ + u-boot,dm-spl; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&i2c0 { + u-boot,dm-spl; + status = "okay"; + clock-frequency = <100000>; + + tps: tps@24 { /* PMIC controller */ + u-boot,dm-spl; + reg = <0x24>; + compatible = "ti,tps65217"; + + tps_bl: backlight { + compatible = "ti,tps65217-bl"; + isel = <1>; /* 1 - ISET1, 2 ISET2 */ + fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */ + default-brightness = <50>; + }; + }; + resetc: rstpsc@75 { /* reset controller */ + compatible = "bur,rstpsc"; + reg = <0x75>; + + cooling-min-state = <0>; + cooling-max-state = <1>; /* reset gets fired */ + #cooling-cells = <2>; /* min followed by max */ + }; + rtc0: rv3029c2@56 { + status = "okay"; + #thermal-sensor-cells = <0>; + compatible = "rv3029c2"; + reg = <0x56>; + }; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&edma { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&mac { + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "mii"; +}; + +&mmc1 { + u-boot,dm-pre-reloc; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <0x4>; + ti,non-removable; + ti,needs-special-hs-handling; + ti,vcc-aux-disable-is-sleep; + status = "okay"; +}; + +&mmc2 { + u-boot,dm-pre-reloc; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <0x8>; + ti,non-removable; + ti,needs-special-hs-handling; + ti,vcc-aux-disable-is-sleep; + status = "okay"; +}; + +&lcdc { + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&elm { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + u-boot,dm-spl; + ti,no-reset-on-init; +}; + +&gpio1 { + u-boot,dm-spl; + ti,no-reset-on-init; +}; + +&gpio2 { + u-boot,dm-spl; + ti,no-reset-on-init; +}; + +&gpio3 { + u-boot,dm-spl; + ti,no-reset-on-init; +}; + +&timer1 { /* today unused */ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&timer2 { /* used for vxworks primary timer device */ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&timer3 { /* used sysdelay and hal tsc counter*/ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&timer4 { /* used for PWM beeper */ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&timer5 { /* used for PWM backlight */ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&timer6 { /* used for cpsw end device */ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&timer7 { /* used for cpsw end device */ + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&wdt2 { + status = "okay"; + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&epwmss0 { + status = "okay"; +}; + +&tscadc { + status = "okay"; + + tsc { + burtouch0: burtouch@0 { + status = "okay"; + compatible = "bur,DdVxSfTouchXXX"; + bur,hwtree = "IF7"; + bur,KX0 = <0x0>; + bur,KX1 = <0x0>; + bur,KX2 = <0x0>; + bur,KY0 = <0x0>; + bur,KY1 = <0x0>; + bur,KY2 = <0x0>; + }; + }; +}; + +&dcan0 { + status = "okay"; +}; + +&dcan1 { + status = "okay"; +}; + +&sham { + status = "disabled"; +}; + +&aes { + status = "disabled"; +}; + +&rng { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts new file mode 100644 index 00000000000..6192156fc37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source + * + * Copyright 2018-2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; +}; + diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts new file mode 100644 index 00000000000..4b526449a19 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160ARDB device tree source + * + * Author: Priyanka Jain <priyanka.jain@nxp.com> + * Sriram Dash <sriram.dash@nxp.com> + * + * Copyright 2018 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ARDB Board"; + compatible = "fsl,lx2160ardb", "fsl,lx2160a"; + +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index b407dc6e136..510b070582d 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -89,7 +89,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <0 240 0x4>; /* Level high type */ + interrupts = <0 26 0x4>; /* Level high type */ num-cs = <6>; }; @@ -115,4 +115,65 @@ interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 63 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + non-removable; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + + sata0: sata@3200000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata1: sata@3210000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata2: sata@3220000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3220000 0x0 0x10000>; + interrupts = <0 97 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata3: sata@3230000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3230000 0x0 0x10000>; + interrupts = <0 100 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; }; diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi index 6445048fe00..b3da8b1a732 100644 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi @@ -4,6 +4,8 @@ * Logic PD - http://www.logicpd.com */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart1; diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index 6445048fe00..956199a2b42 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -4,6 +4,8 @@ * Logic PD - http://www.logicpd.com */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart1; @@ -18,10 +20,6 @@ clock-frequency = <400000>; }; -&mmc1 { - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ -}; - &mmc2 { status = "disabled"; }; diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi index 41ed5d7e179..2c599f1c51b 100644 --- a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi @@ -4,6 +4,8 @@ * Logic PD - http://www.logicpd.com */ +#include "omap3-u-boot.dtsi" + &i2c1 { clock-frequency = <400000>; }; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 41ed5d7e179..2c599f1c51b 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -4,6 +4,8 @@ * Logic PD - http://www.logicpd.com */ +#include "omap3-u-boot.dtsi" + &i2c1 { clock-frequency = <400000>; }; diff --git a/arch/arm/dts/omap3-beagle-u-boot.dtsi b/arch/arm/dts/omap3-beagle-u-boot.dtsi index 41beaf0900c..2c03701c896 100644 --- a/arch/arm/dts/omap3-beagle-u-boot.dtsi +++ b/arch/arm/dts/omap3-beagle-u-boot.dtsi @@ -5,20 +5,10 @@ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart3; }; }; - -&uart1 { - reg-shift = <2>; -}; - -&uart2 { - reg-shift = <2>; -}; - -&uart3 { - reg-shift = <2>; -}; diff --git a/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi b/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi index 41beaf0900c..2c03701c896 100644 --- a/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi +++ b/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi @@ -5,20 +5,10 @@ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart3; }; }; - -&uart1 { - reg-shift = <2>; -}; - -&uart2 { - reg-shift = <2>; -}; - -&uart3 { - reg-shift = <2>; -}; diff --git a/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi b/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi index 41beaf0900c..2c03701c896 100644 --- a/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi +++ b/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi @@ -5,20 +5,10 @@ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart3; }; }; - -&uart1 { - reg-shift = <2>; -}; - -&uart2 { - reg-shift = <2>; -}; - -&uart3 { - reg-shift = <2>; -}; diff --git a/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi b/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi index de411316d83..b9e433f873b 100644 --- a/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi +++ b/arch/arm/dts/omap3-evm-37xx-u-boot.dtsi @@ -5,20 +5,10 @@ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart1; }; }; - -&uart1 { - reg-shift = <2>; -}; - -&uart2 { - reg-shift = <2>; -}; - -&uart3 { - reg-shift = <2>; -}; diff --git a/arch/arm/dts/omap3-evm-u-boot.dtsi b/arch/arm/dts/omap3-evm-u-boot.dtsi index de411316d83..b9e433f873b 100644 --- a/arch/arm/dts/omap3-evm-u-boot.dtsi +++ b/arch/arm/dts/omap3-evm-u-boot.dtsi @@ -5,20 +5,10 @@ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> */ +#include "omap3-u-boot.dtsi" + / { chosen { stdout-path = &uart1; }; }; - -&uart1 { - reg-shift = <2>; -}; - -&uart2 { - reg-shift = <2>; -}; - -&uart3 { - reg-shift = <2>; -}; diff --git a/arch/arm/dts/omap3-u-boot.dtsi b/arch/arm/dts/omap3-u-boot.dtsi new file mode 100644 index 00000000000..32bea6b6d9b --- /dev/null +++ b/arch/arm/dts/omap3-u-boot.dtsi @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap5-u-boot.dtsi" + */ + +/{ + ocp@68000000 { + u-boot,dm-spl; + + bandgap@48002524 { + u-boot,dm-spl; + }; + }; +}; + +&uart1 { + u-boot,dm-spl; + reg-shift = <2>; +}; + +&uart2 { + u-boot,dm-spl; + reg-shift = <2>; +}; + +&uart3 { + u-boot,dm-spl; + reg-shift = <2>; +}; + +&mmc1 { + u-boot,dm-spl; +}; + +&mmc2 { + u-boot,dm-spl; +}; + +&l4_core { + u-boot,dm-spl; +}; + +&scm { + u-boot,dm-spl; +}; + +&scm_conf { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index 3ff2f67c1ad..ddfeba806ce 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -15,7 +15,7 @@ }; spi@7000d400 { - spi-deactivate-delay = <200>; + spi-deactivate-delay = <500>; spi-max-frequency = <3000000>; cros_ec: cros-ec@0 { diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 51895e4816c..2b28fe14970 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -414,6 +414,7 @@ usb@7d000000 { /* Rear external USB port. */ status = "okay"; + dr_mode = "otg"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index d4f80a24cd7..903d5096c71 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -26,7 +26,6 @@ #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) -#define CONFIG_FSL_TZASC_400 #endif #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -121,8 +120,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_GICV3 -#define CONFIG_FSL_TZPC_BP147 -#define CONFIG_FSL_TZASC_400 #define CONFIG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index eaa9ed251ee..d62754e0451 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -42,7 +42,11 @@ #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#ifndef CONFIG_ARCH_LX2160A #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#else +#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 +#endif #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 #ifdef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0535224646b..9fab88ab2ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -350,6 +350,14 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 #define FSL_CHASSIS3_SRDS3_REGSR 29 +#define FSL_CHASSIS3_RCWSR12_REGSR 12 +#define FSL_CHASSIS3_RCWSR13_REGSR 13 +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 +#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 +#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 +#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 +#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 1296ba6efda..bbaaaa4157a 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg) /* Invalidate all ways */ writel(way_mask, op_reg); /* Wait for all ways to be invalidated */ - while (readl(op_reg) && way_mask) + while (readl(op_reg) & way_mask) ; pl310_cache_sync(); } diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 171d094c334..7603f527748 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -85,6 +85,7 @@ relocate_done: isb sy 4: ldp x0, x1, [sp, #16] bl __asm_flush_dcache_range + bl __asm_flush_l3_dcache 5: ldp x29, x30, [sp],#32 ret ENDPROC(relocate_code) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index d9e0b33c601..42beaecdd6b 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -10,8 +10,6 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); -int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, - const u8 phymode)); #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 78fbe287244..e1adea143cf 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -120,71 +120,6 @@ int arch_cpu_init(void) return 0; } -#ifdef CONFIG_ETH_DESIGNWARE -static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, - const u8 phymode)) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - resetfn(args.args[0], phy_modereg); - } - - return 0; -} -#endif - #ifndef CONFIG_SPL_BUILD static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 04f237d100c..6e11ba6cb24 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -54,48 +54,6 @@ static Altera_desc altera_fpga[] = { }, }; -/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode) -{ - u32 physhift, reset; - - if (of_reset_id == EMAC0_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - reset = SOCFPGA_RESET(EMAC0); - } else if (of_reset_id == EMAC1_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - reset = SOCFPGA_RESET(EMAC1); - } else { - printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); - return; - } - - /* configure to PHY interface select choosed */ - clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, - phymode << physhift); - - /* Release the EMAC controller from reset */ - socfpga_per_reset(reset, 0); -} - -static int socfpga_eth_reset(void) -{ - /* Put all GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - return socfpga_eth_reset_common(gen5_dwmac_reset); -}; -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; -#endif - static const struct { const u16 pn; const char *name; @@ -178,7 +136,7 @@ int arch_misc_init(void) env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) env_set("fpgatype", socfpga_fpga_model[fpga_id].var); - return socfpga_eth_reset(); + return 0; } #endif diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c45e4d73a8c..36512a89950 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,15 +14,19 @@ config TARGET_AX25_AE350 config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" +config TARGET_SIFIVE_FU540 + bool "Support SiFive FU540 Board" + endchoice # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" +source "board/sifive/fu540/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" -source "arch/riscv/cpu/qemu/Kconfig" +source "arch/riscv/cpu/generic/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig index f48751e6de7..1d6ab5032da 100644 --- a/arch/riscv/cpu/qemu/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -2,7 +2,7 @@ # # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> -config QEMU_RISCV +config GENERIC_RISCV bool select ARCH_EARLY_INIT_R imply CPU diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile index 258e4620dd4..258e4620dd4 100644 --- a/arch/riscv/cpu/qemu/Makefile +++ b/arch/riscv/cpu/generic/Makefile diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c index ad2950ce40a..ad2950ce40a 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/generic/cpu.c diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c new file mode 100644 index 00000000000..b7b12072351 --- /dev/null +++ b/arch/riscv/cpu/generic/dram.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +ulong board_get_usable_ram_top(ulong total_size) +{ +#ifdef CONFIG_64BIT + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (gd->ram_top > SZ_4G) + return SZ_4G; +#endif + return gd->ram_top; +} diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/qemu/dram.c deleted file mode 100644 index 84d87d2a7f6..00000000000 --- a/arch/riscv/cpu/qemu/dram.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - */ - -#include <common.h> -#include <fdtdec.h> - -int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} diff --git a/arch/riscv/include/asm/arch-generic/clk.h b/arch/riscv/include/asm/arch-generic/clk.h new file mode 100644 index 00000000000..1631f5f0bd0 --- /dev/null +++ b/arch/riscv/include/asm/arch-generic/clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel <anup.patel@wdc.com> + */ + +#ifndef __ASM_RISCV_ARCH_CLK_H +#define __ASM_RISCV_ARCH_CLK_H + +/* Note: This is a placeholder header for driver compilation. */ + +#endif diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h index 81bc975d2e8..156cb94dc04 100644 --- a/arch/riscv/include/asm/config.h +++ b/arch/riscv/include/asm/config.h @@ -8,5 +8,6 @@ #define _ASM_CONFIG_H_ #define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH #endif diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h new file mode 100644 index 00000000000..3d930c90ece --- /dev/null +++ b/arch/riscv/include/asm/dma-mapping.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel <anup.patel@wdc.com> + */ + +#ifndef __ASM_RISCV_DMA_MAPPING_H +#define __ASM_RISCV_DMA_MAPPING_H + +#include <linux/dma-direction.h> + +#define dma_mapping_error(x, y) 0 + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +#endif /* __ASM_RISCV_DMA_MAPPING_H */ diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 1d011ded7cc..87d8e5bcc98 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -203,6 +203,14 @@ #clock-cells = <0>; clock-frequency = <1234>; }; + + clk_fixed_factor: clk-fixed-factor { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <2>; + clocks = <&clk_fixed>; + }; }; clk_sandbox: clk-sbox { @@ -389,6 +397,7 @@ i2s: i2s { compatible = "sandbox,i2s"; #sound-dai-cells = <1>; + sandbox,silent; /* Don't emit sounds while testing */ }; misc-test { @@ -407,6 +416,10 @@ compatible = "sandbox,mmc"; }; + pch { + compatible = "sandbox,pch"; + }; + pci0: pci-controller0 { compatible = "sandbox,pci"; device_type = "pci"; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index c724827f6cf..2d773d3fa6b 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -102,6 +102,15 @@ struct sandbox_state { ulong next_tag; /* Next address tag to allocate */ struct list_head mapmem_head; /* struct sandbox_mapmem_entry */ bool hwspinlock; /* Hardware Spinlock status */ + + /* + * This struct is getting large. + * + * Consider putting test data in driver-private structs, like + * sandbox_pch.c. + * + * If you add new members, please put them above this comment. + */ }; /* Minimum space we guarantee in the state FDT when calling read/write*/ diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 74f96188220..fc52f47f821 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -161,4 +161,28 @@ int sandbox_get_setup_called(struct udevice *dev); */ int sandbox_get_sound_sum(struct udevice *dev); +/** + * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported + * + * @dev: Device to update + * @allow: true to allow the start_beep() method, false to disallow it + */ +void sandbox_set_allow_beep(struct udevice *dev, bool allow); + +/** + * sandbox_get_beep_frequency() - Get the frequency of the current beep + * + * @dev: Device to check + * @return frequency of beep, if there is an active beep, else 0 + */ +int sandbox_get_beep_frequency(struct udevice *dev); + +/** + * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status + * + * @dev: Device to check + * @return 0 if not protected, 1 if protected + */ +int sandbox_get_pch_spi_protect(struct udevice *dev); + #endif diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index a032861e57c..d3785aabdf2 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -2,6 +2,7 @@ # # Copyright (c) 2016 Google, Inc +obj-y += adsp.o obj-y += cpu.o obj-y += iobp.o obj-y += lpc.o diff --git a/arch/x86/cpu/broadwell/adsp.c b/arch/x86/cpu/broadwell/adsp.c new file mode 100644 index 00000000000..2ac8cea7c33 --- /dev/null +++ b/arch/x86/cpu/broadwell/adsp.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for Intel Application Digital Signal Processor + * + * Copyright 2019 Google LLC + * + * Modified from coreboot file of the same name + */ + +#define LOG_CATEGORY UCLASS_SYSCON + +#include <common.h> +#include <dm.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/cpu.h> +#include <asm/intel_regs.h> +#include <asm/arch/adsp.h> +#include <asm/arch/pch.h> +#include <asm/arch/rcb.h> + +enum pci_type_t { + LYNX_POINT, + WILDCAT_POINT, +}; + +struct broadwell_adsp_priv { + bool adsp_d3_pg_enable; + bool adsp_sram_pg_enable; + bool sio_acpi_mode; +}; + +static int broadwell_adsp_probe(struct udevice *dev) +{ + struct broadwell_adsp_priv *priv = dev_get_priv(dev); + enum pci_type_t type; + u32 bar0, bar1; + u32 tmp32; + + /* Find BAR0 and BAR1 */ + bar0 = dm_pci_read_bar32(dev, 0); + if (!bar0) + return -EINVAL; + bar1 = dm_pci_read_bar32(dev, 1); + if (!bar1) + return -EINVAL; + + /* + * Set LTR value in DSP shim LTR control register to 3ms + * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h + */ + type = dev_get_driver_data(dev); + tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; + writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32); + + /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ + dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); + + /* Program ADSP IOBP VDLDAT1 to 0x040100 */ + pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE); + + /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ + dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32); + if (type == WILDCAT_POINT) { + if (priv->adsp_d3_pg_enable) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; + if (priv->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; + } else { + tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; + } + } else { + if (priv->adsp_d3_pg_enable) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; + if (priv->adsp_sram_pg_enable) + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + else + tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; + } else { + tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; + } + } + dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); + + /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */ + setbits_le32(RCB_REG(0x3350), 1 << 10); + + /* Set DSP IOBP PMCTL 0x1e0=0x3f */ + pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); + + if (priv->sio_acpi_mode) { + /* Configure for ACPI mode */ + log_info("ADSP: Enable ACPI Mode IRQ3\n"); + + /* Set interrupt de-assert/assert opcode override to IRQ3 */ + pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3); + + /* Enable IRQ3 in RCBA */ + setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN); + + /* Set ACPI Interrupt Enable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD, + ADSP_PCICFGCTL_ACPIIE); + + /* Put ADSP in D3hot */ + clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); + } else { + log_info("ADSP: Enable PCI Mode IRQ23\n"); + + /* Configure for PCI mode */ + dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + + /* Clear ACPI Interrupt Enable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, + ~(ADSP_PCICFGCTL_SPCBAD | + ADSP_PCICFGCTL_ACPIIE), 0); + } + + return 0; +} + +static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev) +{ + struct broadwell_adsp_priv *priv = dev_get_priv(dev); + + priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable"); + priv->adsp_sram_pg_enable = dev_read_bool(dev, + "intel,adsp-sram-pg-enable"); + priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode"); + + return 0; +} + +static const struct udevice_id broadwell_adsp_ids[] = { + { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT }, + { } +}; + +U_BOOT_DRIVER(broadwell_adsp_drv) = { + .name = "adsp", + .id = UCLASS_SYSCON, + .ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata, + .of_match = broadwell_adsp_ids, + .bind = dm_scan_fdt_dev, + .probe = broadwell_adsp_probe, +}; + +static struct pci_device_id broadwell_adsp_supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) }, + { }, +}; + +U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported); diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 82506ba35e3..73d3d3b5154 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -20,7 +20,9 @@ #include <asm/arch/pch.h> #include <asm/arch/pm.h> #include <asm/arch/rcb.h> +#include <asm/arch/serialio.h> #include <asm/arch/spi.h> +#include <dm/uclass-internal.h> #define BIOS_CTRL 0xdc @@ -456,6 +458,111 @@ static void systemagent_init(void) cpu_set_power_limits(28); } +/* Enable LTR Auto Mode for D21:F1-F6 */ +static void serialio_d21_ltr(u32 bar0) +{ + /* 1. Program BAR0 + 808h[2] = 0b */ + clrbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_LTR_MODE_MASK); + + /* 2. Program BAR0 + 804h[1:0] = 00b */ + clrbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT); + + /* 3. Program BAR0 + 804h[1:0] = 11b */ + setbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT); + + /* 4. Program BAR0 + 814h[31:0] = 00000000h */ + writel(0, bar0 + SIO_REG_AUTO_LTR); +} + +/* Select I2C voltage of 1.8V or 3.3V */ +static void serialio_i2c_voltage_sel(u32 bar0, uint voltage) +{ + clrsetbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_VOLTAGE_MASK, + SIO_REG_PPR_GEN_VOLTAGE(voltage)); +} + +/* Put Serial IO D21:F0-F6 device into desired mode */ +static void serialio_d21_mode(int sio_index, int int_pin, bool acpi_mode) +{ + u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; + + /* Snoop select 1 */ + portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); + + /* Set interrupt pin */ + portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); + + if (acpi_mode) { + /* Enable ACPI interrupt mode */ + portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; + } + + pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); +} + +/* Init sequence to be run once, done as part of D21:F0 (SDMA) init */ +static void serialio_init_once(bool acpi_mode) +{ + if (acpi_mode) { + /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA */ + setbits_le32(RCB_REG(ACPIIRQEN), + 1 << 13 | 1 << 7 | 1 << 6 | 1 << 5); + } + + /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ + pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); + + /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ + pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); +} + +/** + * pch_serialio_init() - set up serial I/O devices + * + * @return 0 if OK, -ve on error + */ +static int pch_serialio_init(void) +{ + struct udevice *dev, *hda; + bool acpi_mode = true; + u32 bar0, bar1; + int ret; + + ret = uclass_find_first_device(UCLASS_I2C, &dev); + if (ret) + return ret; + bar0 = dm_pci_read_bar32(dev, 0); + if (!bar0) + return -EINVAL; + bar1 = dm_pci_read_bar32(dev, 1); + if (!bar1) + return -EINVAL; + + serialio_init_once(acpi_mode); + serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB, acpi_mode); + + serialio_d21_ltr(bar0); + serialio_i2c_voltage_sel(bar0, 1); /* Select 1.8V always */ + serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, acpi_mode); + setbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); + + clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT); + + setbits_le32(bar0 + SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN); + + /* Manually find the High-definition audio, to turn it off */ + ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1b, 0), &hda); + if (ret) + return -ENOENT; + dm_pci_clrset_config8(hda, 0x43, 0, 0x6f); + + /* Route I/O buffers to ADSP function */ + dm_pci_clrset_config8(hda, 0x42, 0, 1 << 7 | 1 << 6); + log_debug("HDA disabled, I/O buffers routed to ADSP\n"); + + return 0; +} + static int broadwell_pch_init(struct udevice *dev) { int ret; @@ -482,6 +589,9 @@ static int broadwell_pch_init(struct udevice *dev) return ret; pch_pm_init(dev); pch_cg_init(dev); + ret = pch_serialio_init(); + if (ret) + return ret; systemagent_init(); return 0; diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c index 914ecfb3144..aa83abbf855 100644 --- a/arch/x86/cpu/broadwell/pinctrl_broadwell.c +++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c @@ -16,6 +16,7 @@ #include <asm/arch/gpio.h> #include <dt-bindings/gpio/x86-gpio.h> #include <dm/pinctrl.h> +#include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; @@ -214,7 +215,7 @@ static int broadwell_pinctrl_probe(struct udevice *dev) u32 gpiobase; int ret; - ret = uclass_first_device(UCLASS_PCH, &pch); + ret = uclass_find_first_device(UCLASS_PCH, &pch); if (ret) return ret; if (!pch) diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 5f0e60837ca..2f423937864 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE imply USB_EHCI_HCD imply USB_XHCI_HCD imply VIDEO_VESA + imply SOUND_IVYBRIDGE if NORTHBRIDGE_INTEL_IVYBRIDGE diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index a78bb025440..ed9bce64168 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -20,8 +20,12 @@ DECLARE_GLOBAL_DATA_PTR; -#define GPIO_BASE 0x48 -#define BIOS_CTRL 0xdc +#define GPIO_BASE 0x48 +#define BIOS_CTRL 0xdc + +#define RCBA_AUDIO_CONFIG 0x2030 +#define RCBA_AUDIO_CONFIG_HDA BIT(31) +#define RCBA_AUDIO_CONFIG_MASK 0xfe #ifndef CONFIG_HAVE_FSP static int pch_revision_id = -1; @@ -212,10 +216,29 @@ static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep) return 0; } +static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data, + int size) +{ + u32 rcba, val; + + switch (req) { + case PCH_REQ_HDA_CONFIG: + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + val = readl(rcba + RCBA_AUDIO_CONFIG); + if (!(val & RCBA_AUDIO_CONFIG_HDA)) + return -ENOENT; + + return val & RCBA_AUDIO_CONFIG_MASK; + default: + return -ENOSYS; + } +} + static const struct pch_ops bd82x6x_pch_ops = { .get_spi_base = bd82x6x_pch_get_spi_base, .set_spi_protect = bd82x6x_set_spi_protect, .get_gpio_base = bd82x6x_get_gpio_base, + .ioctl = bd82x6x_ioctl, }; static const struct udevice_id bd82x6x_ids[] = { diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 39bab7bdf34..a809b823b3b 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -177,6 +177,35 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev) dm_pci_write_config8(dev, PAM6, 0x33); } +/** + * sandybridge_init_iommu() - Set up IOMMU so that azalia can be used + * + * It is not obvious where these values come from. They may be undocumented. + */ +static void sandybridge_init_iommu(struct udevice *dev) +{ + u32 capid0_a; + + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 23)) { + log_debug("capid0_a not needed\n"); + return; + } + + /* setup BARs */ + writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404)); + writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400)); + writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414)); + writel(IOMMU_BASE2 | 1, MCHBAR_REG(0x5410)); + + /* lock policies */ + writel(0x80000000, IOMMU_BASE1 + 0xff0); + + /* Enable azalia sound */ + writel(0x20000000, IOMMU_BASE2 + 0xff0); + writel(0xa0000000, IOMMU_BASE2 + 0xff0); +} + static int bd82x6x_northbridge_early_init(struct udevice *dev) { const int chipset_type = SANDYBRIDGE_MOBILE; @@ -197,6 +226,9 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev) sandybridge_setup_northbridge_bars(dev); + /* Setup IOMMU BARs */ + sandybridge_init_iommu(dev); + /* Device Enable */ dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index f9f09797302..c5653feac72 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -1,6 +1,8 @@ /dts-v1/; #include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/sound/azalia.h> +#include <pci_ids.h> /include/ "skeleton.dtsi" /include/ "keyboard.dtsi" @@ -372,6 +374,32 @@ compatible = "ehci-pci"; }; + hda@1b,0 { + reg = <0x0000d800 0 0 0 0>; + compatible = "intel,bd82x6x-hda"; + + /* These correspond to the Intel HDA specification */ + beep-verbs = < + 0x00170500 /* power up codec */ + 0x00270500 /* power up DAC */ + 0x00b70500 /* power up speaker */ + 0x00b70740 /* enable speaker out */ + 0x00b78d00 /* enable EAPD pin */ + 0x00b70c02 /* set EAPD pin */ + 0x0143b013>; /* beep volume */ + + codecs { + creative_codec: creative-ca0132 { + vendor-id = <PCI_VENDOR_ID_CREATIVE>; + device-id = <PCI_DEVICE_ID_CREATIVE_CA01322>; + }; + intel_hdmi: hdmi { + vendor-id = <PCI_VENDOR_ID_INTEL>; + device-id = <PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI>; + }; + }; + }; + usb_0: usb@1d,0 { reg = <0x0000e800 0 0 0 0>; compatible = "ehci-pci"; @@ -492,3 +520,71 @@ }; }; + +&creative_codec { + verbs = < + /** + * Malcolm Setup. These correspond to the Intel HDA + * specification. + */ + 0x01570d09 0x01570c23 0x01570a01 0x01570df0 + 0x01570efe 0x01570775 0x015707d3 0x01570709 + 0x01570753 0x015707d4 0x015707ef 0x01570775 + 0x015707d3 0x01570709 0x01570702 0x01570737 + 0x01570778 0x01553cce 0x015575c9 0x01553dce + 0x0155b7c9 0x01570de8 0x01570efe 0x01570702 + 0x01570768 0x01570762 0x01553ace 0x015546c9 + 0x01553bce 0x0155e8c9 0x01570d49 0x01570c88 + 0x01570d20 0x01570e19 0x01570700 0x01571a05 + 0x01571b29 0x01571a04 0x01571b29 0x01570a01 + + /* Pin Widget Verb Table */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */ + AZALIA_SUBVENDOR(0x0, 0x144dc0c2) + + /* + * Pin Complex (NID 0x0B) Port-G Analog Unknown + * Speaker at Int N/A + */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x901700f0) + + /* Pin Complex (NID 0x0C) N/C */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x70f000f0) + + /* Pin Complex (NID 0x0D) N/C */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x70f000f0) + + /* Pin Complex (NID 0x0E) N/C */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x70f000f0) + + /* Pin Complex (NID 0x0F) N/C */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x70f000f0) + + /* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */ + AZALIA_PIN_CFG(0x0, 0x10, 0x032110f0) + + /* Pin Complex (NID 0x11) Port-B Click Mic */ + AZALIA_PIN_CFG(0x0, 0x11, 0x90a700f0) + + /* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */ + AZALIA_PIN_CFG(0x0, 0x12, 0x03a110f0) + + /* Pin Complex (NID 0x13) What you hear */ + AZALIA_PIN_CFG(0x0, 0x13, 0x90d600f0)>; +}; + +&intel_hdmi { + verbs = < + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x3, 0x80860101) + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010) + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020) + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)>; +}; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index b58936b4ac9..ad687ce2cc3 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -494,10 +494,20 @@ intel,pre-graphics-delay = <200>; }; - me@16,0 { - reg = <0x0000b000 0 0 0 0>; - compatible = "intel,me"; - u-boot,dm-pre-reloc; + adsp@13,0 { + reg = <0x00009800 0 0 0 0>; + compatible = "intel,wildcatpoint-adsp"; + intel,adsp-d3-pg-enable = <0>; + intel,adsp-sram-pg-enable = <0>; + intel,sio-acpi-mode; + #address-cells = <1>; + #size-cells = <0>; + + i2s: shim { + compatible = "intel,broadwell-i2s"; + #sound-dai-cells = <1>; + reg = <0xfb000 0xfc000 0xfd000>; + }; }; usb_1: usb@14,0 { @@ -505,6 +515,25 @@ compatible = "xhci-pci"; }; + i2c0: i2c@15,1 { + reg = <0x0000a900 0 0 0 0>; + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + + rt5677: rt5677@2c { + compatible = "realtek,rt5677"; + #sound-dai-cells = <1>; + reg = <0x2c>; + }; + }; + + me@16,0 { + reg = <0x0000b000 0 0 0 0>; + compatible = "intel,me"; + u-boot,dm-pre-reloc; + }; + usb_0: usb@1d,0 { status = "disabled"; reg = <0x0000e800 0 0 0 0>; @@ -626,4 +655,16 @@ }; }; + sound { + compatible = "google,samus-sound"; + codec-enable-gpio = <&gpio_b 11 GPIO_ACTIVE_HIGH>; + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&rt5677 0>; + }; + }; + }; diff --git a/arch/x86/include/asm/arch-broadwell/adsp.h b/arch/x86/include/asm/arch-broadwell/adsp.h new file mode 100644 index 00000000000..eb825ce1c06 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell/adsp.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Intel Application Digital Signal Processor + * + * Copyright 2019 Google LLC + * + * Modified from coreboot file of the same name + */ + +#ifndef __ASM_ARCH_BROADWELL_ADSP_H +#define __ASM_ARCH_BROADWELL_ADSP_H + +#define ADSP_PCI_IRQ 23 +#define ADSP_ACPI_IRQ 3 +#define ADSP_ACPI_IRQEN BIT(3) + +#define ADSP_SHIM_BASE_LPT 0xe7000 +#define ADSP_SHIM_BASE_WPT 0xfb000 +#define ADSP_SHIM_LTRC 0xe0 +#define ADSP_SHIM_LTRC_VALUE 0x3003 +#define ADSP_SHIM_IMC 0x28 +#define ADSP_SHIM_IPCD 0x40 + +#define ADSP_PCI_VDRTCTL0 0xa0 +#define ADSP_VDRTCTL0_D3PGD_LPT BIT(1) +#define ADSP_VDRTCTL0_D3PGD_WPT BIT(0) +#define ADSP_VDRTCTL0_D3SRAMPGD_LPT BIT(2) +#define ADSP_VDRTCTL0_D3SRAMPGD_WPT BIT(1) +#define ADSP_PCI_VDRTCTL1 0xa4 +#define ADSP_PCI_VDRTCTL2 0xa8 +#define ADSP_VDRTCTL2_VALUE 0x00000fff + +#define ADSP_IOBP_VDLDAT1 0xd7000624 +#define ADSP_VDLDAT1_VALUE 0x00040100 +#define ADSP_IOBP_VDLDAT2 0xd7000628 +#define ADSP_IOBP_ACPI_IRQ3 0xd9d8 +#define ADSP_IOBP_ACPI_IRQ3I 0xd8d9 +#define ADSP_IOBP_ACPI_IRQ4 0xdbda +#define ADSP_IOBP_PMCTL 0xd70001e0 +#define ADSP_PMCTL_VALUE 0x3f +#define ADSP_IOBP_PCICFGCTL 0xd7000500 +#define ADSP_PCICFGCTL_PCICD BIT(0) +#define ADSP_PCICFGCTL_ACPIIE BIT(1) +#define ADSP_PCICFGCTL_SPCBAD BIT(7) + +#endif /* __ASM_ARCH_BROADWELL_ADSP_H */ diff --git a/arch/x86/include/asm/arch-broadwell/pch.h b/arch/x86/include/asm/arch-broadwell/pch.h index 23ccd684842..23153a040fa 100644 --- a/arch/x86/include/asm/arch-broadwell/pch.h +++ b/arch/x86/include/asm/arch-broadwell/pch.h @@ -109,6 +109,9 @@ #define SATA_DTLE_EDGE_SHIFT 16 /* Power Management */ +#define PCH_PCS 0x84 +#define PCH_PCS_PS_D3HOT 3 + #define GEN_PMCON_1 0xa0 #define SMI_LOCK (1 << 4) #define GEN_PMCON_2 0xa2 diff --git a/arch/x86/include/asm/arch-broadwell/rcb.h b/arch/x86/include/asm/arch-broadwell/rcb.h index e7340c1e5a6..b7ce8746c85 100644 --- a/arch/x86/include/asm/arch-broadwell/rcb.h +++ b/arch/x86/include/asm/arch-broadwell/rcb.h @@ -6,6 +6,8 @@ #ifndef __asm_arch_rcba_h #define __asm_arch_rcba_h +#define ACPIIRQEN 0x31e0 /* 32bit */ + #define PMSYNC_CONFIG 0x33c4 /* 32bit */ #define PMSYNC_CONFIG2 0x33cc /* 32bit */ diff --git a/arch/x86/include/asm/arch-broadwell/serialio.h b/arch/x86/include/asm/arch-broadwell/serialio.h new file mode 100644 index 00000000000..5e98eaf53fd --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell/serialio.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Serial IO defintiions (taken from coreboot file of same name) + * + * Copyright 2019 Google LLC + */ + +#ifndef __ARCH_BROADWELL_SERIALIO_H_ +#define __ARCH_BROADWELL_SERIALIO_H_ + +/* Serial IO IOBP Registers */ +#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ +#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN BIT(5) +#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS BIT(4) +#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */ +#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13) +#define SIO_IOBP_GPIODF 0xcb000154 +#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN BIT(4) +#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN BIT(3) +#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN BIT(2) +#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN BIT(1) +#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN BIT(0) +#define SIO_IOBP_GPIODF_UART0_BYTE_ACCESS BIT(10) +#define SIO_IOBP_GPIODF_UART1_BYTE_ACCESS BIT(11) +#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */ +#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */ +#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */ +#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */ +#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */ +#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */ +#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */ +#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8)) +/* PORTCTRL 2-8 have the same layout */ +#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN BIT(21) +#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS BIT(20) +#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18) +#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2) +#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT BIT(1) +#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */ +#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */ +#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */ +#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */ +#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */ +#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */ +#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */ +#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */ +#define SIO_IOBP_FUNCDIS_DIS BIT(8) + +/* Serial IO Devices */ +#define SIO_ID_SDMA 0 /* D21:F0 */ +#define SIO_ID_I2C0 1 /* D21:F1 */ +#define SIO_ID_I2C1 2 /* D21:F2 */ +#define SIO_ID_SPI0 3 /* D21:F3 */ +#define SIO_ID_SPI1 4 /* D21:F4 */ +#define SIO_ID_UART0 5 /* D21:F5 */ +#define SIO_ID_UART1 6 /* D21:F6 */ +#define SIO_ID_SDIO 7 /* D23:F0 */ + +#define SIO_REG_PPR_CLOCK 0x800 +#define SIO_REG_PPR_CLOCK_EN BIT(0) +#define SIO_REG_PPR_CLOCK_UPDATE BIT(31) +#define SIO_REG_PPR_CLOCK_M_DIV 0x25a +#define SIO_REG_PPR_CLOCK_N_DIV 0x7fff +#define SIO_REG_PPR_RST 0x804 +#define SIO_REG_PPR_RST_ASSERT 0x3 +#define SIO_REG_PPR_GEN 0x808 +#define SIO_REG_PPR_GEN_LTR_MODE_MASK BIT(2) +#define SIO_REG_PPR_GEN_VOLTAGE_MASK BIT(3) +#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3) +#define SIO_REG_AUTO_LTR 0x814 + +#define SIO_REG_SDIO_PPR_GEN 0x1008 +#define SIO_REG_SDIO_PPR_SW_LTR 0x1010 +#define SIO_REG_SDIO_PPR_CMD12 0x3c +#define SIO_REG_SDIO_PPR_CMD12_B30 BIT(30) + +#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */ +#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */ +#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */ +#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */ + +#endif /* __ARCH_BROADWELL_SERIALIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index a96c951c85e..a3a507f2b36 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -43,6 +43,9 @@ /* 4 KB per PCIe device */ #define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE +#define IOMMU_BASE1 0xfed90000ULL +#define IOMMU_BASE2 0xfed91000ULL + /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define EPBAR 0x40 #define MCHBAR 0x48 diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h index 65c97614d3e..d769daf85dc 100644 --- a/arch/x86/include/asm/i8254.h +++ b/arch/x86/include/asm/i8254.h @@ -35,4 +35,22 @@ /* The clock frequency of the i8253/i8254 PIT */ #define PIT_TICK_RATE 1193182 +/** + * i8254_enable_beep() - Start a beep using the PCAT timer + * + * This starts beeping using the legacy i8254 timer. The beep may be silenced + * after a delay with i8254_disable_beep(). + * + * @frequency_hz: Frequency of beep in Hz + * @return 0 if OK, -EINVAL if frequency_hz is 0 + */ +int i8254_enable_beep(uint frequency_hz); + +/** + * i8254_disable_beep() - Disable the bepper + * + * This stops any existing beep + */ +void i8254_disable_beep(void); + #endif /* _ASMI386_I8954_H_ */ diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 81def0afd30..cf6c33cbe3a 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -57,19 +57,19 @@ * memory location directly. */ -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) -#define readq(addr) (*(volatile unsigned long long *) (addr)) +#define readb(addr) (*(volatile u8 *)(uintptr_t)(addr)) +#define readw(addr) (*(volatile u16 *)(uintptr_t)(addr)) +#define readl(addr) (*(volatile u32 *)(uintptr_t)(addr)) +#define readq(addr) (*(volatile u64 *)(uintptr_t)(addr)) #define __raw_readb readb #define __raw_readw readw #define __raw_readl readl #define __raw_readq readq -#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b)) -#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b)) -#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b)) -#define writeq(b,addr) (*(volatile unsigned long long *) (addr) = (b)) +#define writeb(b, addr) (*(volatile u8 *)(addr) = (b)) +#define writew(b, addr) (*(volatile u16 *)(addr) = (b)) +#define writel(b, addr) (*(volatile u32 *)(addr) = (b)) +#define writeq(b, addr) (*(volatile u64 *)(addr) = (b)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c index 1f1012488cb..d0227954b16 100644 --- a/arch/x86/lib/i8254.c +++ b/arch/x86/lib/i8254.c @@ -8,8 +8,20 @@ #include <asm/io.h> #include <asm/i8254.h> -#define TIMER1_VALUE 18 /* 15.6us */ -#define TIMER2_VALUE 0x0a8e /* 440Hz */ +#define TIMER1_VALUE 18 /* 15.6us */ +#define BEEP_FREQUENCY_HZ 440 +#define SYSCTL_PORTB 0x61 +#define PORTB_BEEP_ENABLE 0x3 + +static void i8254_set_beep_freq(uint frequency_hz) +{ + uint countdown; + + countdown = PIT_TICK_RATE / frequency_hz; + + outb(countdown & 0xff, PIT_BASE + PIT_T2); + outb((countdown >> 8) & 0xff, PIT_BASE + PIT_T2); +} int i8254_init(void) { @@ -29,8 +41,23 @@ int i8254_init(void) */ outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND); - outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); - outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); + i8254_set_beep_freq(BEEP_FREQUENCY_HZ); + + return 0; +} + +int i8254_enable_beep(uint frequency_hz) +{ + if (!frequency_hz) + return -EINVAL; + + i8254_set_beep_freq(frequency_hz); + setio_8(SYSCTL_PORTB, PORTB_BEEP_ENABLE); return 0; } + +void i8254_disable_beep(void) +{ + clrio_8(SYSCTL_PORTB, PORTB_BEEP_ENABLE); +} |