diff options
Diffstat (limited to 'arch')
86 files changed, 3295 insertions, 12922 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 1a77779db4d..02f61fcc3cb 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -68,8 +68,8 @@ endif checkgcc6: @if test "$(call cc-name)" = "gcc" -a \ "$(call cc-version)" -lt "0600"; then \ - echo -n '*** Your GCC is older than 6.0 and will not be '; \ - echo 'supported starting in v2018.01.'; \ + echo '*** Your GCC is older than 6.0 and is not supported'; \ + false; \ fi diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index adc7e1746f5..6548f3c9121 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -230,7 +230,10 @@ static void add_map(struct mm_region *map) /* Page fits, create block PTE */ debug("Setting PTE %p to block virt=%llx\n", pte, virt); - *pte = phys | attrs; + if (level == 3) + *pte = phys | attrs | PTE_TYPE_PAGE; + else + *pte = phys | attrs; virt += blocksize; phys += blocksize; size -= blocksize; diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index 4f4f526f932..8c7c1d3eb80 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -12,12 +12,65 @@ #include <linux/linkage.h> /* + * Exception vectors. + */ + .align 11 + .globl vectors +vectors: + .align 7 /* Current EL Synchronous Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_sync + b exception_exit + + .align 7 /* Current EL IRQ Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_irq + b exception_exit + + .align 7 /* Current EL FIQ Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_fiq + b exception_exit + + .align 7 /* Current EL Error Thread */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_bad_error + b exception_exit + + .align 7 /* Current EL Synchronous Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_sync + b exception_exit + + .align 7 /* Current EL IRQ Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_irq + b exception_exit + + .align 7 /* Current EL FIQ Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_fiq + b exception_exit + + .align 7 /* Current EL Error Handler */ + stp x29, x30, [sp, #-16]! + bl _exception_entry + bl do_error + b exception_exit + +/* * Enter Exception. * This will save the processor state that is ELR/X0~X30 * to the stack frame. */ -.macro exception_entry - stp x29, x30, [sp, #-16]! +_exception_entry: stp x27, x28, [sp, #-16]! stp x25, x26, [sp, #-16]! stp x23, x24, [sp, #-16]! @@ -46,78 +99,8 @@ 0: stp x2, x0, [sp, #-16]! mov x0, sp -.endm + ret -/* - * Exception vectors. - */ - .align 11 - .globl vectors -vectors: - .align 7 - b _do_bad_sync /* Current EL Synchronous Thread */ - - .align 7 - b _do_bad_irq /* Current EL IRQ Thread */ - - .align 7 - b _do_bad_fiq /* Current EL FIQ Thread */ - - .align 7 - b _do_bad_error /* Current EL Error Thread */ - - .align 7 - b _do_sync /* Current EL Synchronous Handler */ - - .align 7 - b _do_irq /* Current EL IRQ Handler */ - - .align 7 - b _do_fiq /* Current EL FIQ Handler */ - - .align 7 - b _do_error /* Current EL Error Handler */ - - -_do_bad_sync: - exception_entry - bl do_bad_sync - b exception_exit - -_do_bad_irq: - exception_entry - bl do_bad_irq - b exception_exit - -_do_bad_fiq: - exception_entry - bl do_bad_fiq - b exception_exit - -_do_bad_error: - exception_entry - bl do_bad_error - b exception_exit - -_do_sync: - exception_entry - bl do_sync - b exception_exit - -_do_irq: - exception_entry - bl do_irq - b exception_exit - -_do_fiq: - exception_entry - bl do_fiq - b exception_exit - -_do_error: - exception_entry - bl do_error - b exception_exit exception_exit: ldp x2, x0, [sp],#16 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0d055e3abbc..ed85349d3fc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-sdk.dtb \ + rk3128-evb.dtb \ rk3188-radxarock.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ @@ -55,7 +56,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb \ - meson-gxl-s905x-p212.dtb + meson-gxl-s905x-p212.dtb \ + meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-khadas-vim.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -427,6 +430,9 @@ dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ logicpd-torpedo-37xx-devkit.dtb \ logicpd-som-lv-37xx-devkit.dtb +dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ + at91-sama5d2_ptc_ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index dc8a1a66c1f..5e5a1585518 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -258,6 +258,19 @@ marvell,function = "i2c0"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", + "mpp38", "mpp28", "mpp40", "mpp42", + "mpp35", "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp41"; + marvell,function = "nand"; + }; + mdio_pins: mdio-pins { marvell,pins = "mpp4", "mpp5"; marvell,function = "ge"; @@ -545,7 +558,7 @@ }; flash@d0000 { - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts new file mode 100644 index 00000000000..ab5ab21895d --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts @@ -0,0 +1,215 @@ +/* + * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board + * + * Copyright (C) 2017 Microchip Technology Inc, + * Ludovic Desroches <ludovic.desroches@microchip.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" + +/ { + model = "Atmel SAMA5D2 PTC EK"; + compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart0; + }; + + ahb { + usb0: gadget@00300000 { + atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00400000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PB12 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@00500000 { + status = "okay"; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + status = "disabled"; /* conflicts with nand and qspi0*/ + u-boot,dm-pre-reloc; + }; + + apb { + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + uart0: serial@f801c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + i2c1: i2c@fc028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + i2c_eeprom: i2c_eeprom@50 { + compatible = "atmel,24mac402"; + reg = <0x50>; + }; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PC6__TWD1>, + <PIN_PC7__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; + + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA10__SDMMC0_RSTN>, + <PIN_PA11__SDMMC0_VDDSEL>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB12__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PB11__GPIO>; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/bcm2835-rpi-zero-w.dts b/arch/arm/dts/bcm2835-rpi-zero-w.dts new file mode 100644 index 00000000000..78170547752 --- /dev/null +++ b/arch/arm/dts/bcm2835-rpi-zero-w.dts @@ -0,0 +1,26 @@ +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; + model = "Raspberry Pi Zero W"; + + leds { + act { + gpios = <&gpio 47 0>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 85cb5487713..d46ecdbc566 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -6,6 +6,8 @@ */ / { + model = "LogicPD Zoom OMAP3 Development Kit"; + chosen { stdout-path = &uart1; }; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts new file mode 100644 index 00000000000..94567eb1787 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "meson-gxl-s905x-p212.dtsi" + +/ { + compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Khadas VIM"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Function"; + linux,code = <KEY_FN>; + press-threshold-microvolt = <10000>; + }; + }; + + aliases { + serial2 = &uart_AO_B; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "power"; + linux,code = <KEY_POWER>; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + power { + label = "vim:red:power"; + pwms = <&pwm_AO_ab 1 7812500 0>; + max-brightness = <255>; + linux,default-trigger = "default-on"; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + /* has to be enabled manually when a battery is connected: */ + status = "disabled"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&ir { + linux,rc-map-name = "rc-geekbox"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; + pinctrl-names = "default"; + clocks = <&xtal> , <&xtal>; + clock-names = "clkin0", "clkin1" ; +}; + +&pwm_ef { + pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; +}; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ +&uart_AO { + status = "okay"; +}; + +/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts new file mode 100644 index 00000000000..266fbcf3e47 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * Author: Jerome Brunet <jbrunet@baylibre.com> + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Libre Technology CC"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + system { + label = "librecomputer:system-status"; + gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + panic-indicator; + }; + + blue { + label = "librecomputer:blue"; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_card: regulator-vcc-card { + compatible = "regulator-gpio"; + + regulator-name = "VCC_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +ðmac { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <50000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index 615b6521314..405ae9c7818 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -394,6 +394,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; }; sysc: system-controller@e6180000 { diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 9e6a5f231e9..6a6bfd4e194 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -377,6 +377,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + u-boot,dm-pre-reloc; }; sysc: system-controller@e6180000 { diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts new file mode 100644 index 00000000000..6940af9a5c1 --- /dev/null +++ b/arch/arm/dts/rk3128-evb.dts @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rk3128.dtsi" + +/ { + model = "Rockchip RK3128 Evaluation board"; + compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; + + chosen { + stdout-path = &uart2; + }; + + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-drv { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&emmc { + fifo-mode; + status = "okay"; +}; + +&pinctrl { + usb_otg { + otg_vbus_drv: host-vbus-drv { + rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi new file mode 100644 index 00000000000..3ef2737f5b5 --- /dev/null +++ b/arch/arm/dts/rk3128.dtsi @@ -0,0 +1,804 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3128-cru.h> +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk3128"; + rockchip,sram = <&sram>; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &spi0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3128-smp"; + + cpu0:cpu@0x000 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x000>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1:cpu@0x001 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x001>; + }; + + cpu2:cpu@0x002 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x002>; + }; + + cpu3:cpu@0x003 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x003>; + }; + }; + + cpu_axi_bus: cpu_axi_bus { + compatible = "rockchip,cpu_axi_bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qos { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + crypto { + reg = <0x10128080 0x20>; + }; + + core { + reg = <0x1012a000 0x20>; + }; + + peri { + reg = <0x1012c000 0x20>; + }; + + gpu { + reg = <0x1012d000 0x20>; + }; + + vpu { + reg = <0x1012e000 0x20>; + }; + + rga { + reg = <0x1012f000 0x20>; + }; + ebc { + reg = <0x1012f080 0x20>; + }; + + iep { + reg = <0x1012f100 0x20>; + }; + + lcdc { + reg = <0x1012f180 0x20>; + rockchip,priority = <3 3>; + }; + + vip { + reg = <0x1012f200 0x20>; + rockchip,priority = <3 3>; + }; + }; + + msch { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + msch@10128000 { + reg = <0x10128000 0x20>; + rockchip,read-latency = <0x3f>; + }; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + migrate = <0x84000005>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + pdma: pdma@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + arm,pl330-broken-no-flushp;//2 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin12m: xin12m { + compatible = "fixed-clock"; + clocks = <&xin24m>; + clock-frequency = <12000000>; + clock-output-names = "xin12m"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + timer@20044000 { + compatible = "arm,armv7-timer"; + reg = <0x20044000 0xb8>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + rockchip,broadcast = <1>; + }; + + watchdog: wdt@2004c000 { + compatible = "rockchip,watch dog"; + reg = <0x2004c000 0x100>; + clock-names = "pclk_wdt"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + rockchip,irq = <1>; + rockchip,timeout = <60>; + rockchip,atboot = <1>; + rockchip,debug = <0>; + }; + + reset: reset@20000110 { + compatible = "rockchip,reset"; + reg = <0x20000110 0x24>; + #reset-cells = <1>; + }; + + nandc: nandc@10500000 { + compatible = "rockchip,rk-nandc"; + reg = <0x10500000 0x4000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; + nandc_id = <0>; + clocks = <&cru SCLK_NANDC>, + <&cru HCLK_NANDC>, + <&cru SRST_NANDC>; + clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; + }; + + dmc: dmc@20004000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-dmc", "syscon"; + reg = <0x0 0x20004000 0x0 0x1000>; + }; + + cru: clock-controller@20000000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + uart0: serial0@20060000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + dmas = <&pdma 2>, <&pdma 3>; + #dma-cells = <2>; + }; + + uart1: serial1@20064000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + dmas = <&pdma 4>, <&pdma 5>; + #dma-cells = <2>; + }; + + uart2: serial2@20068000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + dmas = <&pdma 6>, <&pdma 7>; + #dma-cells = <2>; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pwm0: pwm0@20050000 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050000 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + pwm1: pwm1@20050010 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050010 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + pwm2: pwm2@20050020 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + pwm3: pwm3@20050030 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + }; + + sram: sram@10080400 { + compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; + reg = <0x10080400 0x1C00>; + map-exec; + map-cacheable; + }; + + pmu: syscon@100a0000 { + compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; + reg = <0x100a0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + u2phy: usb2-phy { + compatible = "rockchip,rk3128-usb2phy"; + reg = <0x017c 0x0c>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usb480m_phy"; + #phy-cells = <1>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", + "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + g-use-dma; + hnp-srp-disable; + phys = <&u2phy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ehci: usb@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x20000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2phy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@101e0000 { + compatible = "generic-ohci"; + reg = <0x101e0000 0x20000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2phy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + sdmmc: dwmmc@10214000 { + compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10214000 0x4000>; + max-frequency = <150000000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + bus-width = <4>; + status = "disabled"; + }; + + emmc: dwmmc@1021c000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x1021c000 0x4000>; + max-frequency = <150000000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + bus-width = <8>; + default-sample-phase = <158>; + num-slots = <1>; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + i2c0: i2c0@20072000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <20072000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + }; + + i2c1: i2c1@20056000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + }; + + i2c2: i2c2@2005a000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + }; + + i2c3: i2c3@2005e000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + }; + + spi0: spi@20074000 { + compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; + reg = <0x20074000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; + rockchip,spi-src-clk = <0>; + num-cs = <2>; + clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spi","pclk_spi0"; + dmas = <&pdma 8>, <&pdma 9>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + }; + + grf: syscon@20008000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3128-grf", "syscon"; + reg = <0x20008000 0x1000>; + }; + + pinctrl: pinctrl@20008000 { + compatible = "rockchip,rk3128-pinctrl"; + reg = <0x20008000 0xA8>, + <0x200080A8 0x4C>, + <0x20008118 0x20>, + <0x20008100 0x04>; + reg-names = "base", "mux", "pull", "drv"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio2@20088000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20088000 0x100>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + + emmc_clk: emmc-clk { + rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, + <1 25 RK_FUNC_2 &pcfg_pull_none>, + <1 26 RK_FUNC_2 &pcfg_pull_none>, + <1 27 RK_FUNC_2 &pcfg_pull_none>, + <1 28 RK_FUNC_2 &pcfg_pull_none>, + <1 29 RK_FUNC_2 &pcfg_pull_none>, + <1 30 RK_FUNC_2 &pcfg_pull_none>, + <1 31 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + nandc{ + nandc_ale:nandc-ale { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_cle:nandc-cle { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_wrn:nandc-wrn { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_rdn:nandc-rdn { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_rdy:nandc-rdy { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_cs0:nandc-cs0 { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + nandc_data: nandc-data { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + <1 19 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, + <1 RK_PC3 1 &pcfg_pull_up>, + <1 RK_PC4 1 &pcfg_pull_up>, + <1 RK_PC5 1 &pcfg_pull_up>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 1 2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 27 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, + <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 20 3 &pcfg_pull_none>, + <2 21 3 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_txd_mux0:spi0-txd-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_rxd_mux0:spi0-rxd-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_clk_mux0:spi0-clk-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_cs0_mux0:spi0-cs0-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + + spi0_cs1_mux0:spi0-cs1-mux0 { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + }; +}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 96bd4fec01d..d2c961e3178 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -16,6 +16,7 @@ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ u-boot,boot-led = "module_led"; + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; }; chosen { @@ -544,12 +545,17 @@ &dwc3_typec1 { status = "okay"; + tsd,usb-port-power = "usbhub_enable"; }; &vopb { status = "okay"; }; +&gpio1 { + u-boot,dm-pre-reloc; +}; + &gpio3 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 7520446dc1a..6645a553646 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -302,6 +302,7 @@ #clock-cells = <0>; reg = <24>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; uart1_clk: uart1_clk@25 { @@ -315,6 +316,7 @@ #clock-cells = <0>; reg = <26>; atmel,clk-output-range = <0 83000000>; + u-boot,dm-pre-reloc; }; uart3_clk: uart3_clk@27 { @@ -635,6 +637,14 @@ status = "disabled"; }; + uart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x100>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + uart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; @@ -643,6 +653,14 @@ status = "disabled"; }; + uart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + clocks = <&uart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + i2c0: i2c@f8028000 { compatible = "atmel,sama5d2-i2c"; reg = <0xf8028000 0x100>; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 5f77f578af8..a56ae931210 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -22,3 +22,7 @@ u-boot,dm-pre-reloc; }; }; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 783d4e734e5..f62360f0db5 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -99,12 +99,19 @@ status = "disabled"; u-boot,dm-pre-reloc; }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + rcc: rcc@40023810 { #reset-cells = <1>; #clock-cells = <2>; - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + compatible = "st,stm32f746-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; clocks = <&clk_hse>; + st,syscfg = <&pwrcfg>; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index e21cf332c9b..59fcf711825 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -24,6 +24,15 @@ stdout-path = "serial0:115200n8"; }; + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; + audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> @@ -190,6 +199,10 @@ }; }; +&i2c_dvfs { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -247,7 +260,7 @@ sdhi2_pins: sd2 { groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; - power-source = <3300>; + power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h new file mode 100644 index 00000000000..3089f13ba00 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MESON_ETH_H__ +#define __MESON_ETH_H__ + +#include <phy.h> + +enum { + /* Use GXL Internal RMII PHY */ + MESON_GXL_USE_INTERNAL_RMII_PHY = 1, +}; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); + +#endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h index 95a6fe6998e..ef63dea4496 100644 --- a/arch/arm/include/asm/arch-meson/gxbb.h +++ b/arch/arm/include/asm/arch-meson/gxbb.h @@ -7,10 +7,27 @@ #ifndef __GXBB_H__ #define __GXBB_H__ +#define GXBB_FIRMWARE_MEM_SIZE 0x1000000 + +#define GXBB_AOBUS_BASE 0xc8100000 #define GXBB_PERIPHS_BASE 0xc8834400 #define GXBB_HIU_BASE 0xc883c000 #define GXBB_ETH_BASE 0xc9410000 +/* Always-On Peripherals registers */ +#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2)) + +#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90) +#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93) +#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94) +#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95) + +#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000 +#define GXBB_AO_MEM_SIZE_SHIFT 16 +#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + /* Peripherals registers */ #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h new file mode 100644 index 00000000000..86a84170347 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/mem.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MESON_MEM_H__ +#define __MESON_MEM_H__ + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_gx_init_reserved_memory(void *fdt); + +#endif /* __MESON_MEM_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h new file mode 100644 index 00000000000..90012c7fce0 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_CRU_RK3128_H +#define _ASM_ARCH_CRU_RK3128_H + +#include <common.h> + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3128_clk_priv { + struct rk3128_cru *cru; +}; + +struct rk3128_cru { + struct rk3128_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[11]; + unsigned int reserved; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int reserved1[2]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved2[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved3[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved5[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved6[4]; + unsigned int cru_pll_prg_en; +}; +check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + GPLL_MODE_DEEP, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_CPLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_GPLL_DIV2, + BUS_ACLK_PLL_SEL_GPLL_DIV3, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL_DIV2, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLK_SEL2_CON */ + NANDC_PLL_SEL_SHIFT = 14, + NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, + NANDC_PLL_SEL_CPLL = 0, + NANDC_PLL_SEL_GPLL, + NANDC_CLK_DIV_SHIFT = 8, + NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, + PVTM_CLK_DIV_SHIFT = 0, + PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT, + PERI_PLL_APLL = 0, + PERI_PLL_DPLL, + PERI_PLL_GPLL, + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + MMC0_PLL_SHIFT = 6, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_GPLL, + MMC0_SEL_GPLL_DIV2, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_PLL_SHIFT = 14, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_GPLL, + EMMC_SEL_GPLL_DIV2, + EMMC_SEL_24M, + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, + + /* CLKSEL_CON24 */ + SARADC_DIV_CON_SHIFT = 8, + SARADC_DIV_CON_MASK = GENMASK(15, 8), + SARADC_DIV_CON_WIDTH = 8, + + /* CRU_CLKSEL27_CON*/ + DCLK_VOP_SEL_SHIFT = 0, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_PLL_SEL_CPLL = 0, + DCLK_VOP_DIV_CON_SHIFT = 8, + DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, + + /* CRU_CLKSEL31_CON */ + VIO0_PLL_SHIFT = 5, + VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, + VI00_SEL_CPLL = 0, + VIO0_SEL_GPLL, + VIO0_DIV_SHIFT = 0, + VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, + VIO1_PLL_SHIFT = 13, + VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, + VI01_SEL_CPLL = 0, + VIO1_SEL_GPLL, + VIO1_DIV_SHIFT = 8, + VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h new file mode 100644 index 00000000000..aa6b693520d --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h @@ -0,0 +1,551 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3128_H +#define _ASM_ARCH_GRF_RK3128_H + +#include <common.h> + +struct rk3128_grf { + unsigned int reserved[0x2a]; + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + unsigned int gpio2c_iomux2; + unsigned int grf_cif_iomux; + unsigned int grf_cif_iomux1; + unsigned int reserved1[(0x118 - 0xf0) / 4 - 1]; + unsigned int gpio0l_pull; + unsigned int gpio0h_pull; + unsigned int gpio1l_pull; + unsigned int gpio1h_pull; + unsigned int gpio2l_pull; + unsigned int gpio2h_pull; + unsigned int gpio3l_pull; + unsigned int gpio3h_pull; + unsigned int reserved2; + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int soc_status0; + unsigned int reserved3[6]; + unsigned int mac_con0; + unsigned int mac_con1; + unsigned int reserved4[4]; + unsigned int uoc0_con0; + unsigned int reserved5; + unsigned int uoc1_con1; + unsigned int uoc1_con2; + unsigned int uoc1_con3; + unsigned int uoc1_con4; + unsigned int uoc1_con5; + unsigned int reserved6; + unsigned int ddrc_stat; + unsigned int reserved9; + unsigned int soc_status1; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int cpu_con2; + unsigned int cpu_con3; + unsigned int reserved10; + unsigned int reserved11; + unsigned int cpu_status0; + unsigned int cpu_status1; + unsigned int os_reg[8]; + unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1]; + unsigned int usbphy0_con[8]; + unsigned int usbphy1_con[8]; + unsigned int uoc_status0; + unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1]; + unsigned int chip_tag; + unsigned int sdmmc_det_cnt; +}; +check_member(rk3128_grf, sdmmc_det_cnt, 0x304); + +struct rk3128_pmu { + unsigned int wakeup_cfg; + unsigned int pwrdn_con; + unsigned int pwrdn_st; + unsigned int idle_req; + unsigned int idle_st; + unsigned int pwrmode_con; + unsigned int pwr_state; + unsigned int osc_cnt; + unsigned int core_pwrdwn_cnt; + unsigned int core_pwrup_cnt; + unsigned int sft_con; + unsigned int ddr_sref_st; + unsigned int int_con; + unsigned int int_st; + unsigned int sys_reg[4]; +}; +check_member(rk3128_pmu, int_st, 0x34); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 1 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 1 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 1 << GPIO0B4_SHIFT, + GPIO0B4_GPIO = 0, + GPIO0B4_I2S_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S1_MCLK, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 1 << GPIO0D1_SHIFT, + GPIO0D1_GPIO = 0, + GPIO0D1_UART2_CTSN, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, + GPIO0D0_GPIO = 0, + GPIO0D0_UART2_RTSN, + GPIO0D0_PMIC_SLEEP, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + GPIO1A5_SDMMC_DATA3, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + GPIO1A4_SDMMC_DATA2, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_SDMMC_DATA1, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 3 << GPIO1A1_SHIFT, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + GPIO1A1_SDMMC_DATA0, + GPIO1A1_PMIC_SLEEP, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 3, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + GPIO1A0_SDMMC_CLKOUT, + GPIO1A0_XIN32K, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 1 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_MMC_PWREN, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_SPI_RXD, + GPIO1B2_UART1_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_SPI_TXD, + GPIO1B1_UART1_SOUT, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3 << GPIO1B0_SHIFT, + GPIO1B0_GPIO = 0, + GPIO1B0_SPI_CLK, + GPIO1B0_UART1_CTSN +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_RX, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_TX, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD1, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD1, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_LCDC0_D13, + GPIO2B7_EBC_SDCE5, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_LCDC0_D12, + GPIO2B6_EBC_SDCE4, + GPIO2B6_GMAC_CLK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_LCDC0_D11, + GPIO2B5_EBC_SDCE3, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_LCDC0_D10, + GPIO2B4_EBC_SDCE2, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_LCDC0_DEN, + GPIO2B3_EBC_GDCLK, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_LCDC0_VSYNC, + GPIO2B2_EBC_SDOE, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_LCDC0_HSYNC, + GPIO2B1_EBC_SDLE, + GPIO2B1_GMAC_TXCLK, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_LCDC0_DCLK, + GPIO2B0_EBC_SDCLK, + GPIO2B0_GMAC_RXDV, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_LCDC0_D17, + GPIO2C3_EBC_GDPWR0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_LCDC0_D16, + GPIO2C2_EBC_GDSP, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_LCDC0_D15, + GPIO2C1_EBC_GDOE, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_LCDC0_D14, + GPIO2C0_EBC_VCOM, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_LCDC0_D22, + GPIO2D6_GMAC_COL = 4, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC = 3, +}; + +/* GRF_GPIO2C_IOMUX2 */ +enum { + GPIO2C7_SHIFT = 12, + GPIO2C7_MASK = 7 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3 = 4, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 7 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2 = 4, + + GPIO2C5_SHIFT = 4, + GPIO2C5_MASK = 7 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL = 3, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 0, + GPIO2C4_MASK = 7 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA = 3, + GPIO2C4_GMAC_RXD2, +}; +#endif diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 6cc19664dd3..e9f3aabb6fc 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -42,41 +42,6 @@ struct stm32_u_id_regs { u32 u_id_high; }; -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 pllcfgr; /* RCC PLL configuration */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 ahb1rstr; /* RCC AHB1 peripheral reset */ - u32 ahb2rstr; /* RCC AHB2 peripheral reset */ - u32 ahb3rstr; /* RCC AHB3 peripheral reset */ - u32 rsv0; - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 rsv1[2]; - u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ - u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ - u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ - u32 rsv2; - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 rsv3[2]; - u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ - u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ - u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ - u32 rsv4; - u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ - u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ - u32 rsv5[2]; - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ - u32 rsv6[2]; - u32 sscgr; /* RCC spread spectrum clock generation */ - u32 plli2scfgr; /* RCC PLLI2S configuration */ - u32 pllsaicfgr; - u32 dckcfgr; -}; - struct stm32_pwr_regs { u32 cr; u32 csr; diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h new file mode 100644 index 00000000000..bfe54698b34 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_PWR_H_ + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ +}; + +#endif /* __STM32_PWR_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h deleted file mode 100644 index 6475f9d5c89..00000000000 --- a/arch/arm/include/asm/arch-stm32f7/rcc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _STM32_RCC_H -#define _STM32_RCC_H - -#include <dt-bindings/mfd/stm32f7-rcc.h> - -/* - * RCC AHB1ENR specific definitions - */ -#define RCC_AHB1ENR_ETHMAC_EN BIT(25) -#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) -#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) - -/* - * RCC APB1ENR specific definitions - */ -#define RCC_APB1ENR_TIM2EN BIT(0) -#define RCC_APB1ENR_PWREN BIT(28) - -/* - * RCC APB2ENR specific definitions - */ -#define RCC_APB2ENR_SYSCFGEN BIT(14) - -#endif diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index d6412a00cc6..f54e6f19557 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -59,49 +59,8 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { #define STM32_BUS_MASK GENMASK(31, 16) -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 pllcfgr; /* RCC PLL configuration */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 ahb1rstr; /* RCC AHB1 peripheral reset */ - u32 ahb2rstr; /* RCC AHB2 peripheral reset */ - u32 ahb3rstr; /* RCC AHB3 peripheral reset */ - u32 rsv0; - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 rsv1[2]; - u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ - u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ - u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ - u32 rsv2; - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 rsv3[2]; - u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ - u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ - u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ - u32 rsv4; - u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ - u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ - u32 rsv5[2]; - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ - u32 rsv6[2]; - u32 sscgr; /* RCC spread spectrum clock generation */ - u32 plli2scfgr; /* RCC PLLI2S configuration */ - u32 pllsaicfgr; /* PLLSAI configuration */ - u32 dckcfgr; /* dedicated clocks configuration register */ -}; #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) -struct stm32_pwr_regs { - u32 cr1; /* power control register 1 */ - u32 csr1; /* power control/status register 2 */ - u32 cr2; /* power control register 2 */ - u32 csr2; /* power control/status register 2 */ -}; -#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE) void stm32_flash_latency_cfg(int latency); diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h new file mode 100644 index 00000000000..917dd46d985 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_PWR_H_ + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ + u32 cr2; /* power control register 2 */ + u32 csr2; /* power control/status register 2 */ +}; + +#endif /* __STM32_PWR_H_ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 6121aab547f..765914c7e26 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -43,6 +43,7 @@ #define PTE_TYPE_MASK (3 << 0) #define PTE_TYPE_FAULT (0 << 0) #define PTE_TYPE_TABLE (3 << 0) +#define PTE_TYPE_PAGE (3 << 0) #define PTE_TYPE_BLOCK (1 << 0) #define PTE_TYPE_VALID (1 << 0) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 7c9cfce69fa..cbcfeec2b03 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <efi_loader.h> +DECLARE_GLOBAL_DATA_PTR; int interrupt_init(void) { @@ -29,8 +30,13 @@ void show_regs(struct pt_regs *regs) { int i; - printf("ELR: %lx\n", regs->elr); - printf("LR: %lx\n", regs->regs[30]); + if (gd->flags & GD_FLG_RELOC) { + printf("ELR: %lx\n", regs->elr - gd->reloc_off); + printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); + } else { + printf("ELR: %lx\n", regs->elr); + printf("LR: %lx\n", regs->regs[30]); + } for (i = 0; i < 29; i += 2) printf("x%-2d: %016lx x%-2d: %016lx\n", i, regs->regs[i], i+1, regs->regs[i+1]); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7e85b69679d..69072635392 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -143,10 +143,9 @@ config TARGET_AT91SAM9X5EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT -config TARGET_SAMA5D2_PTC - bool "SAMA5D2 PTC board" +config TARGET_SAMA5D2_PTC_EK + bool "SAMA5D2 PTC EK board" select SAMA5D2 - select SUPPORT_SPL select BOARD_EARLY_INIT_F config TARGET_SAMA5D2_XPLAINED @@ -237,6 +236,18 @@ config TARGET_VINCO select SAMA5D4 select SUPPORT_SPL +config TARGET_WB45N + bool "Support Laird WB45N" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_WB50N + bool "Support Laird WB50N" + select BOARD_LATE_INIT + select CPU_V7 + select SUPPORT_SPL + select BOARD_EARLY_INIT_F + endchoice config SYS_SOC @@ -251,7 +262,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" -source "board/atmel/sama5d2_ptc/Kconfig" +source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" @@ -271,6 +282,8 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" +source "board/laird/wb45n/Kconfig" +source "board/laird/wb50n/Kconfig" config SPL_LDSCRIPT default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index df0f71975ad..e2063167359 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin) at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_B_periph(x, y) \ at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) +#define at91_set_gpio_deglitch(x, y) \ + at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_output(x, y) \ at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_input(x, y) \ diff --git a/arch/arm/mach-at91/include/mach/sama5d2_smc.h b/arch/arm/mach-at91/include/mach/sama5d2_smc.h new file mode 100644 index 00000000000..7ddb728cf3e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2_smc.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 Microchip Corporation. + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on SAMA5D2 datasheet. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SAMA5D2_SMC_H +#define SAMA5D2_SMC_H + +#ifdef __ASSEMBLY__ +#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700) +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704) +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708) +#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710) +#else +struct at91_cs { + u32 setup; /* 0x600 SMC Setup Register */ + u32 pulse; /* 0x604 SMC Pulse Register */ + u32 cycle; /* 0x608 SMC Cycle Register */ + u32 timings; /* 0x60C SMC Cycle Register */ + u32 mode; /* 0x610 SMC Mode Register */ +}; + +struct at91_smc { + struct at91_cs cs[4]; +}; +#endif /* __ASSEMBLY__ */ + +#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) +#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) +#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) +#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) + +#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) +#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) +#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) +#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) + +#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) +#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) + +#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) +#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) +#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) +#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) +#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) +#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) +#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) +#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) + +#define AT91_SMC_MODE_RM_NCS 0x00000000 +#define AT91_SMC_MODE_RM_NRD 0x00000001 +#define AT91_SMC_MODE_WM_NCS 0x00000000 +#define AT91_SMC_MODE_WM_NWE 0x00000002 + +#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 +#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 +#define AT91_SMC_MODE_EXNW_READY 0x00000030 + +#define AT91_SMC_MODE_BAT 0x00000100 +#define AT91_SMC_MODE_DBW_8 0x00000000 +#define AT91_SMC_MODE_DBW_16 0x00001000 +#define AT91_SMC_MODE_DBW_32 0x00002000 +#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) +#define AT91_SMC_MODE_TDF 0x00100000 +#define AT91_SMC_MODE_PMEN 0x01000000 +#define AT91_SMC_MODE_PS_4 0x00000000 +#define AT91_SMC_MODE_PS_8 0x10000000 +#define AT91_SMC_MODE_PS_16 0x20000000 +#define AT91_SMC_MODE_PS_32 0x30000000 + +#endif diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 69f7a4663cf..a78239d63e4 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -44,6 +44,22 @@ config TARGET_RPI This option creates a build targetting the ARM1176 ISA. select BCM2835 +config TARGET_RPI_0_W + bool "Raspberry Pi Zero W" + help + Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as + the RPi Zero model W. + + This option assumes the VideoCore firmware is configured to use the + mini UART (rather than PL011) for the serial console. This is the + default on the RPi Zero W. To enable the UART console, the following + non-default option must be present in config.txt: enable_uart=1. + This is required for U-Boot to operate correctly, even if you only + care about the HDMI/usbkbd console. + + This option creates a build targetting the ARMv7/AArch32 ISA. + select BCM2835 + config TARGET_RPI_2 bool "Raspberry Pi 2" help diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index d4bd230be3b..0350787daa7 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -38,6 +38,20 @@ config TARGET_P212 with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. +config TARGET_LIBRETECH_CC + bool "LIBRETECH-CC" + help + LibreTech CC is a single board computer based on Meson GXL + with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, + eMMC, IR receiver and a 40-pin GPIO header. + +config TARGET_KHADAS_VIM + bool "KHADAS-VIM" + help + Khadas VIM is a single board computer based on Meson GXL + with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, + eMMC, IR receiver and a 40-pin GPIO header. + endif config SYS_SOC @@ -50,4 +64,8 @@ source "board/amlogic/odroid-c2/Kconfig" source "board/amlogic/p212/Kconfig" +source "board/amlogic/libretech-cc/Kconfig" + +source "board/amlogic/khadas-vim/Kconfig" + endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index bf49b8b1e57..b4e8dded14c 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o sm.o +obj-y += board.o sm.o eth.o diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c index e89c6aace98..908a0cae560 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board.c @@ -11,6 +11,9 @@ #include <asm/arch/sm.h> #include <asm/armv8/mmu.h> #include <asm/unaligned.h> +#include <linux/sizes.h> +#include <efi_loader.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,15 +37,70 @@ int dram_init(void) return 0; } -int dram_init_banksize(void) +phys_size_t get_effective_memsize(void) { - /* Reserve first 16 MiB of RAM for firmware */ - gd->bd->bi_dram[0].start = 0x1000000; - gd->bd->bi_dram[0].size = 0xf000000; - /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */ - gd->bd->bi_dram[1].start = 0x10000000; - gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000; - return 0; + /* Size is reported in MiB, convert it in bytes */ + return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK) + >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) +{ + int ret; + + ret = fdt_add_mem_rsv(fdt, start, size); + if (ret) + printf("Could not reserve zone @ 0x%llx\n", start); + + if (IS_ENABLED(CONFIG_EFI_LOADER)) { + efi_add_memory_map(start, + ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, + EFI_RESERVED_MEMORY_TYPE, false); + } +} + +void meson_gx_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + + reg = readl(GXBB_AO_SEC_GP_CFG3); + + bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK) + >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(GXBB_AO_SEC_GP_CFG5); + bl32_start = readl(GXBB_AO_SEC_GP_CFG4); + + /* + * Early Meson GXBB Firmware revisions did not provide the reserved + * memory zones in the registers, keep fixed memory zone handling. + */ + if (IS_ENABLED(CONFIG_MESON_GXBB) && + !reg && !bl31_start && !bl32_start) { + bl31_start = 0x10000000; + bl31_size = 0x200000; + } + + /* Add first 16MiB reserved zone */ + meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); } void reset_cpu(ulong addr) diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c new file mode 100644 index 00000000000..2debe93952c --- /dev/null +++ b/arch/arm/mach-meson/eth.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/eth.h> +#include <phy.h> + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | + GXBB_ETH_REG_0_TX_PHASE(1) | + GXBB_ETH_REG_0_TX_RATIO(4) | + GXBB_ETH_REG_0_PHY_CLK_EN | + GXBB_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK | + GXBB_ETH_REG_0_CLK_EN); + + /* Use GXL RMII Internal PHY */ + if (IS_ENABLED(CONFIG_MESON_GXL) && + (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { + writel(GXBB_ETH_REG_2, 0x10110181); + writel(GXBB_ETH_REG_3, 0xe40908ff); + } + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power and clock gate */ + setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); + clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1d302761f09..1a06a1e8760 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -111,10 +111,16 @@ #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) /* BootROM error register (also includes some status infos) */ +#if defined(CONFIG_ARMADA_38X) +#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) +#define BOOTROM_ERR_MODE_OFFS 0 +#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) +#else #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) #define BOOTROM_ERR_MODE_OFFS 28 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) #define BOOTROM_ERR_MODE_UART 0x6 +#endif #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ @@ -141,6 +147,7 @@ #define BOOT_DEV_SEL_OFFS 4 #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) +#define BOOT_FROM_NAND 0x0A #define BOOT_FROM_UART 0x28 #define BOOT_FROM_UART_ALT 0x3f #define BOOT_FROM_SPI 0x32 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index a72a769f7c7..d16a62d2dd3 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -26,7 +26,16 @@ static u32 get_boot_device(void) val = readl(CONFIG_BOOTROM_ERR_REG); boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); +#if defined(CONFIG_ARMADA_38X) + /* + * If the bootrom error register contains any else than zeros + * in the first 8 bits it's an error condition. And in that case + * try to boot from UART. + */ + if (boot_device) +#else if (boot_device == BOOTROM_ERR_MODE_UART) +#endif return BOOT_DEVICE_UART; /* @@ -36,6 +45,10 @@ static u32 get_boot_device(void) boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); switch (boot_device) { +#if defined(CONFIG_ARMADA_38X) + case BOOT_FROM_NAND: + return BOOT_DEVICE_NAND; +#endif #ifdef CONFIG_SPL_MMC_SUPPORT case BOOT_FROM_MMC: case BOOT_FROM_MMC_ALT: @@ -119,7 +132,15 @@ void board_init_f(ulong dummy) * SPL has no chance to receive this information. So we * need to return to the BootROM to enable this xmodem * UART download. + * + * If booting from NAND lets let the BootROM load the + * rest of the bootloader. */ - if (get_boot_device() == BOOT_DEVICE_UART) - return_to_bootrom(); + switch (get_boot_device()) { + case BOOT_DEVICE_UART: +#if defined(CONFIG_ARMADA_38X) + case BOOT_DEVICE_NAND: +#endif + return_to_bootrom(); + } } diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 2e8778043b7..d11670c0eee 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -215,6 +215,9 @@ void omap_die_id_usbethaddr(void) mac[5] = (die_id[0] >> 8) & 0xff; eth_env_set_enetaddr("usbethaddr", mac); + + if (!env_get("ethaddr")) + eth_env_set_enetaddr("ethaddr", mac); } } diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 2aea527bae2..39493788061 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o -obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o -obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o +obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c index d91bc26703a..bdb353062fe 100644 --- a/arch/arm/mach-rmobile/board.c +++ b/arch/arm/mach-rmobile/board.c @@ -8,8 +8,10 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> +#ifndef CONFIG_RCAR_GEN3 int checkboard(void) { printf("Board: %s\n", sysinfo.board_string); return 0; } +#endif diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index c373eef73d4..b443611cbb3 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -8,19 +8,20 @@ #include <common.h> #include <asm/io.h> -#define PRR 0xFF000044 #define PRR_MASK 0x7fff #define R8A7796_REV_1_0 0x5200 #define R8A7796_REV_1_1 0x5210 +static u32 rmobile_get_prr(void); + u32 rmobile_get_cpu_type(void) { - return (readl(PRR) & 0x00007F00) >> 8; + return (rmobile_get_prr() & 0x00007F00) >> 8; } u32 rmobile_get_cpu_rev_integer(void) { - const u32 prr = readl(PRR); + const u32 prr = rmobile_get_prr(); if ((prr & PRR_MASK) == R8A7796_REV_1_1) return 1; @@ -30,10 +31,62 @@ u32 rmobile_get_cpu_rev_integer(void) u32 rmobile_get_cpu_rev_fraction(void) { - const u32 prr = readl(PRR); + const u32 prr = rmobile_get_prr(); if ((prr & PRR_MASK) == R8A7796_REV_1_1) return 1; else return prr & 0x0000000F; } + +#if !CONFIG_IS_ENABLED(DM) || !CONFIG_IS_ENABLED(SYSCON) +static u32 rmobile_get_prr(void) +{ + /* + * On RCar/RMobile Gen2 and older systems, the PRR is always + * located at the address below. On newer systems, the PRR + * may be located at different address, but that information + * is obtained from DT. This code will be removed when all + * of the older systems get converted to DM and OF control. + */ + return readl(0xFF000044); +} +#else + +#include <dm.h> +#include <syscon.h> +#include <regmap.h> + +struct renesas_prr_priv { + fdt_addr_t regs; +}; + +enum { + PRR_RCAR, +}; + +static u32 rmobile_get_prr(void) +{ + struct regmap *map; + + map = syscon_get_regmap_by_driver_data(PRR_RCAR); + if (!map) { + printf("PRR regmap failed!\n"); + hang(); + } + + return readl(map->base); +} + +static const struct udevice_id renesas_prr_ids[] = { + { .compatible = "renesas,prr", .data = PRR_RCAR }, + { } +}; + +U_BOOT_DRIVER(renesas_prr) = { + .name = "renesas_prr", + .id = UCLASS_SYSCON, + .of_match = renesas_prr_ids, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index faa53197d5b..5c8cb3f666a 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -18,6 +18,9 @@ int arch_cpu_init(void) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { +#if defined(CONFIG_RCAR_GEN3) + rcar_gen3_memmap_fixup(); +#endif dcache_enable(); } #endif @@ -49,15 +52,15 @@ static const struct { u16 cpu_type; u8 cpu_name[10]; } rmobile_cpuinfo[] = { - { 0x37, "SH73A0" }, - { 0x40, "R8A7740" }, - { 0x45, "R8A7790" }, - { 0x47, "R8A7791" }, - { 0x4A, "R8A7792" }, - { 0x4B, "R8A7793" }, - { 0x4C, "R8A7794" }, - { 0x4F, "R8A7795" }, - { 0x52, "R8A7796" }, + { RMOBILE_CPU_TYPE_SH73A0, "SH73A0" }, + { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" }, + { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" }, + { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" }, + { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" }, + { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" }, + { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" }, + { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" }, + { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h index 02b29364c54..448d189e926 100644 --- a/arch/arm/mach-rmobile/include/mach/gpio.h +++ b/arch/arm/mach-rmobile/include/mach/gpio.h @@ -22,12 +22,6 @@ void r8a7793_pinmux_init(void); #elif defined(CONFIG_R8A7794) #include "r8a7794-gpio.h" void r8a7794_pinmux_init(void); -#elif defined(CONFIG_R8A7795) -#include "r8a7795-gpio.h" -void r8a7795_pinmux_init(void); -#elif defined(CONFIG_R8A7796) -#include "r8a7796-gpio.h" -void r8a7796_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h deleted file mode 100644 index 554063ab8fe..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h +++ /dev/null @@ -1,1016 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h - * This file defines pin function control of gpio. - * - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_R8A7795_GPIO_H__ -#define __ASM_R8A7795_GPIO_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ - -/* V2(ES2.0) */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - - /* GPSR0 */ - GPIO_GFN_D15, - GPIO_GFN_D14, - GPIO_GFN_D13, - GPIO_GFN_D12, - GPIO_GFN_D11, - GPIO_GFN_D10, - GPIO_GFN_D9, - GPIO_GFN_D8, - GPIO_GFN_D7, - GPIO_GFN_D6, - GPIO_GFN_D5, - GPIO_GFN_D4, - GPIO_GFN_D3, - GPIO_GFN_D2, - GPIO_GFN_D1, - GPIO_GFN_D0, - - /* GPSR1 */ - GPIO_GFN_CLKOUT, - GPIO_GFN_EX_WAIT0_A, - GPIO_GFN_WE1x, - GPIO_GFN_WE0x, - GPIO_GFN_RD_WRx, - GPIO_GFN_RDx, - GPIO_GFN_BSx, - GPIO_GFN_CS1x_A26, - GPIO_GFN_CS0x, - GPIO_GFN_A19, - GPIO_GFN_A18, - GPIO_GFN_A17, - GPIO_GFN_A16, - GPIO_GFN_A15, - GPIO_GFN_A14, - GPIO_GFN_A13, - GPIO_GFN_A12, - GPIO_GFN_A11, - GPIO_GFN_A10, - GPIO_GFN_A9, - GPIO_GFN_A8, - GPIO_GFN_A7, - GPIO_GFN_A6, - GPIO_GFN_A5, - GPIO_GFN_A4, - GPIO_GFN_A3, - GPIO_GFN_A2, - GPIO_GFN_A1, - GPIO_GFN_A0, - - /* GPSR2 */ - GPIO_GFN_AVB_AVTP_CAPTURE_A, - GPIO_GFN_AVB_AVTP_MATCH_A, - GPIO_GFN_AVB_LINK, - GPIO_GFN_AVB_PHY_INT, - GPIO_GFN_AVB_MAGIC, - GPIO_GFN_AVB_MDC, - GPIO_GFN_PWM2_A, - GPIO_GFN_PWM1_A, - GPIO_GFN_PWM0, - GPIO_GFN_IRQ5, - GPIO_GFN_IRQ4, - GPIO_GFN_IRQ3, - GPIO_GFN_IRQ2, - GPIO_GFN_IRQ1, - GPIO_GFN_IRQ0, - - /* GPSR3 */ - GPIO_GFN_SD1_WP, - GPIO_GFN_SD1_CD, - GPIO_GFN_SD0_WP, - GPIO_GFN_SD0_CD, - GPIO_GFN_SD1_DAT3, - GPIO_GFN_SD1_DAT2, - GPIO_GFN_SD1_DAT1, - GPIO_GFN_SD1_DAT0, - GPIO_GFN_SD1_CMD, - GPIO_GFN_SD1_CLK, - GPIO_GFN_SD0_DAT3, - GPIO_GFN_SD0_DAT2, - GPIO_GFN_SD0_DAT1, - GPIO_GFN_SD0_DAT0, - GPIO_GFN_SD0_CMD, - GPIO_GFN_SD0_CLK, - - /* GPSR4 */ - GPIO_GFN_SD3_DS, - GPIO_GFN_SD3_DAT7, - GPIO_GFN_SD3_DAT6, - GPIO_GFN_SD3_DAT5, - GPIO_GFN_SD3_DAT4, - GPIO_GFN_SD3_DAT3, - GPIO_GFN_SD3_DAT2, - GPIO_GFN_SD3_DAT1, - GPIO_GFN_SD3_DAT0, - GPIO_GFN_SD3_CMD, - GPIO_GFN_SD3_CLK, - GPIO_GFN_SD2_DS, - GPIO_GFN_SD2_DAT3, - GPIO_GFN_SD2_DAT2, - GPIO_GFN_SD2_DAT1, - GPIO_GFN_SD2_DAT0, - GPIO_GFN_SD2_CMD, - GPIO_GFN_SD2_CLK, - - /* GPSR5 */ - GPIO_GFN_MLB_DAT, - GPIO_GFN_MLB_SIG, - GPIO_GFN_MLB_CLK, - GPIO_FN_MSIOF0_RXD, - GPIO_GFN_MSIOF0_SS2, - GPIO_FN_MSIOF0_TXD, - GPIO_GFN_MSIOF0_SS1, - GPIO_GFN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_SCK, - GPIO_GFN_HRTS0x, - GPIO_GFN_HCTS0x, - GPIO_GFN_HTX0, - GPIO_GFN_HRX0, - GPIO_GFN_HSCK0, - GPIO_GFN_RX2_A, - GPIO_GFN_TX2_A, - GPIO_GFN_SCK2, - GPIO_GFN_RTS1x_TANS, - GPIO_GFN_CTS1x, - GPIO_GFN_TX1_A, - GPIO_GFN_RX1_A, - GPIO_GFN_RTS0x_TANS, - GPIO_GFN_CTS0x, - GPIO_GFN_TX0, - GPIO_GFN_RX0, - GPIO_GFN_SCK0, - - /* GPSR6 */ - GPIO_GFN_USB3_OVC, - GPIO_GFN_USB3_PWEN, - GPIO_GFN_USB30_OVC, - GPIO_GFN_USB30_PWEN, - GPIO_GFN_USB1_OVC, - GPIO_GFN_USB1_PWEN, - GPIO_GFN_USB0_OVC, - GPIO_GFN_USB0_PWEN, - GPIO_GFN_AUDIO_CLKB_B, - GPIO_GFN_AUDIO_CLKA_A, - GPIO_GFN_SSI_SDATA9_A, - GPIO_GFN_SSI_SDATA8, - GPIO_GFN_SSI_SDATA7, - GPIO_GFN_SSI_WS78, - GPIO_GFN_SSI_SCK78, - GPIO_GFN_SSI_SDATA6, - GPIO_GFN_SSI_WS6, - GPIO_GFN_SSI_SCK6, - GPIO_FN_SSI_SDATA5, - GPIO_FN_SSI_WS5, - GPIO_FN_SSI_SCK5, - GPIO_GFN_SSI_SDATA4, - GPIO_GFN_SSI_WS4, - GPIO_GFN_SSI_SCK4, - GPIO_GFN_SSI_SDATA3, - GPIO_GFN_SSI_WS34, - GPIO_GFN_SSI_SCK34, - GPIO_GFN_SSI_SDATA2_A, - GPIO_GFN_SSI_SDATA1_A, - GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS01239, - GPIO_GFN_SSI_SCK01239, - - /* GPSR7 */ - GPIO_FN_HDMI1_CEC, - GPIO_FN_HDMI0_CEC, - GPIO_FN_AVS2, - GPIO_FN_AVS1, - - /* IPSR0 */ - GPIO_IFN_AVB_MDC, - GPIO_FN_MSIOF2_SS2_C, - GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_SS1_C, - GPIO_FN_SCK4_A, - GPIO_IFN_AVB_PHY_INT, - GPIO_FN_MSIOF2_SYNC_C, - GPIO_FN_RX4_A, - GPIO_IFN_AVB_LINK, - GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_TX4_A, - GPIO_IFN_AVB_AVTP_MATCH_A, - GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_CTS4x_A, - GPIO_FN_FSCLKST2x_A, - GPIO_IFN_AVB_AVTP_CAPTURE_A, - GPIO_FN_MSIOF2_TXD_C, - GPIO_FN_RTS4x_TANS_A, - GPIO_IFN_IRQ0, - GPIO_FN_QPOLB, - GPIO_FN_DU_CDE, - GPIO_FN_VI4_DATA0_B, - GPIO_FN_CAN0_TX_B, - GPIO_FN_CANFD0_TX_B, - GPIO_FN_MSIOF3_SS2_E, - GPIO_IFN_IRQ1, - GPIO_FN_QPOLA, - GPIO_FN_DU_DISP, - GPIO_FN_VI4_DATA1_B, - GPIO_FN_CAN0_RX_B, - GPIO_FN_CANFD0_RX_B, - GPIO_FN_MSIOF3_SS1_E, - - /* IPSR1 */ - GPIO_IFN_IRQ2, - GPIO_FN_QCPV_QDE, - GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, - GPIO_FN_VI4_DATA2_B, - GPIO_FN_MSIOF3_SYNC_E, - GPIO_FN_PWM3_B, - GPIO_IFN_IRQ3, - GPIO_FN_QSTVB_QVE, - GPIO_FN_A25, - GPIO_FN_DU_DOTCLKOUT1, - GPIO_FN_VI4_DATA3_B, - GPIO_FN_MSIOF3_SCK_E, - GPIO_FN_PWM4_B, - GPIO_IFN_IRQ4, - GPIO_FN_QSTH_QHS, - GPIO_FN_A24, - GPIO_FN_DU_EXHSYNC_DU_HSYNC, - GPIO_FN_VI4_DATA4_B, - GPIO_FN_MSIOF3_RXD_E, - GPIO_FN_PWM5_B, - GPIO_IFN_IRQ5, - GPIO_FN_QSTB_QHE, - GPIO_FN_A23, - GPIO_FN_DU_EXVSYNC_DU_VSYNC, - GPIO_FN_VI4_DATA5_B, - GPIO_FN_FSCLKST2x_B, - GPIO_FN_MSIOF3_TXD_E, - GPIO_FN_PWM6_B, - GPIO_IFN_PWM0, - GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_VI4_DATA6_B, - GPIO_FN_IECLK_B, - GPIO_IFN_PWM1_A, - GPIO_FN_HRX3_D, - GPIO_FN_VI4_DATA7_B, - GPIO_FN_IERX_B, - GPIO_IFN_PWM2_A, - GPIO_FN_HTX3_D, - GPIO_FN_IETX_B, - GPIO_IFN_A0, - GPIO_FN_LCDOUT16, - GPIO_FN_MSIOF3_SYNC_B, - GPIO_FN_VI4_DATA8, - GPIO_FN_DU_DB0, - GPIO_FN_PWM3_A, - - /* IPSR2 */ - GPIO_IFN_A1, - GPIO_FN_LCDOUT17, - GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI4_DATA9, - GPIO_FN_DU_DB1, - GPIO_FN_PWM4_A, - GPIO_IFN_A2, - GPIO_FN_LCDOUT18, - GPIO_FN_MSIOF3_SCK_B, - GPIO_FN_VI4_DATA10, - GPIO_FN_DU_DB2, - GPIO_FN_PWM5_A, - GPIO_IFN_A3, - GPIO_FN_LCDOUT19, - GPIO_FN_MSIOF3_RXD_B, - GPIO_FN_VI4_DATA11, - GPIO_FN_DU_DB3, - GPIO_FN_PWM6_A, - GPIO_IFN_A4, - GPIO_FN_LCDOUT20, - GPIO_FN_MSIOF3_SS1_B, - GPIO_FN_VI4_DATA12, - GPIO_FN_VI5_DATA12, - GPIO_FN_DU_DB4, - GPIO_IFN_A5, - GPIO_FN_LCDOUT21, - GPIO_FN_MSIOF3_SS2_B, - GPIO_FN_SCK4_B, - GPIO_FN_VI4_DATA13, - GPIO_FN_VI5_DATA13, - GPIO_FN_DU_DB5, - GPIO_IFN_A6, - GPIO_FN_LCDOUT22, - GPIO_FN_MSIOF2_SS1_A, - GPIO_FN_RX4_B, - GPIO_FN_VI4_DATA14, - GPIO_FN_VI5_DATA14, - GPIO_FN_DU_DB6, - GPIO_IFN_A7, - GPIO_FN_LCDOUT23, - GPIO_FN_MSIOF2_SS2_A, - GPIO_FN_TX4_B, - GPIO_FN_VI4_DATA15, - GPIO_FN_V15_DATA15, - GPIO_FN_DU_DB7, - GPIO_IFN_A8, - GPIO_FN_RX3_B, - GPIO_FN_MSIOF2_SYNC_A, - GPIO_FN_HRX4_B, - GPIO_FN_SDA6_A, - GPIO_FN_AVB_AVTP_MATCH_B, - GPIO_FN_PWM1_B, - - /* IPSR3 */ - GPIO_IFN_A9, - GPIO_FN_MSIOF2_SCK_A, - GPIO_FN_CTS4x_B, - GPIO_FN_VI5_VSYNCx, - GPIO_IFN_A10, - GPIO_FN_MSIOF2_RXD_A, - GPIO_FN_RTS4n_TANS_B, - GPIO_FN_VI5_HSYNCx, - GPIO_IFN_A11, - GPIO_FN_TX3_B, - GPIO_FN_MSIOF2_TXD_A, - GPIO_FN_HTX4_B, - GPIO_FN_HSCK4, - GPIO_FN_VI5_FIELD, - GPIO_FN_SCL6_A, - GPIO_FN_AVB_AVTP_CAPTURE_B, - GPIO_FN_PWM2_B, - GPIO_IFN_A12, - GPIO_FN_LCDOUT12, - GPIO_FN_MSIOF3_SCK_C, - GPIO_FN_HRX4_A, - GPIO_FN_VI5_DATA8, - GPIO_FN_DU_DG4, - GPIO_IFN_A13, - GPIO_FN_LCDOUT13, - GPIO_FN_MSIOF3_SYNC_C, - GPIO_FN_HTX4_A, - GPIO_FN_VI5_DATA9, - GPIO_FN_DU_DG5, - GPIO_IFN_A14, - GPIO_FN_LCDOUT14, - GPIO_FN_MSIOF3_RXD_C, - GPIO_FN_HCTS4x, - GPIO_FN_VI5_DATA10, - GPIO_FN_DU_DG6, - GPIO_IFN_A15, - GPIO_FN_LCDOUT15, - GPIO_FN_MSIOF3_TXD_C, - GPIO_FN_HRTS4x, - GPIO_FN_VI5_DATA11, - GPIO_FN_DU_DG7, - GPIO_IFN_A16, - GPIO_FN_LCDOUT8, - GPIO_FN_VI4_FIELD, - GPIO_FN_DU_DG0, - - /* IPSR4 */ - GPIO_IFN_A17, - GPIO_FN_LCDOUT9, - GPIO_FN_VI4_VSYNCx, - GPIO_FN_DU_DG1, - GPIO_IFN_A18, - GPIO_FN_LCDOUT10, - GPIO_FN_VI4_HSYNCx, - GPIO_FN_DU_DG2, - GPIO_IFN_A19, - GPIO_FN_LCDOUT11, - GPIO_FN_VI4_CLKENB, - GPIO_FN_DU_DG3, - GPIO_IFN_CS0x, - GPIO_FN_VI5_CLKENB, - GPIO_IFN_CS1x_A26, - GPIO_FN_VI5_CLK, - GPIO_FN_EX_WAIT0_B, - GPIO_IFN_BSx, - GPIO_FN_QSTVA_QVS, - GPIO_FN_MSIOF3_SCK_D, - GPIO_FN_SCK3, - GPIO_FN_HSCK3, - GPIO_FN_CAN1_TX, - GPIO_FN_CANFD1_TX, - GPIO_FN_IETX_A, - GPIO_IFN_RDx, - GPIO_FN_MSIOF3_SYNC_D, - GPIO_FN_RX3_A, - GPIO_FN_HRX3_A, - GPIO_FN_CAN0_TX_A, - GPIO_FN_CANFD0_TX_A, - GPIO_IFN_RD_WRx, - GPIO_FN_MSIOF3_RXD_D, - GPIO_FN_TX3_A, - GPIO_FN_HTX3_A, - GPIO_FN_CAN0_RX_A, - GPIO_FN_CANFD0_RX_A, - - /* IPSR5 */ - GPIO_IFN_WE0x, - GPIO_FN_MSIIOF3_TXD_D, - GPIO_FN_CTS3x, - GPIO_FN_HCTS3x, - GPIO_FN_SCL6_B, - GPIO_FN_CAN_CLK, - GPIO_FN_IECLK_A, - GPIO_IFN_WE1x, - GPIO_FN_MSIOF3_SS1_D, - GPIO_FN_RTS3x_TANS, - GPIO_FN_HRTS3x, - GPIO_FN_SDA6_B, - GPIO_FN_CAN1_RX, - GPIO_FN_CANFD1_RX, - GPIO_FN_IERX_A, - GPIO_IFN_EX_WAIT0_A, - GPIO_FN_QCLK, - GPIO_FN_VI4_CLK, - GPIO_FN_DU_DOTCLKOUT0, - GPIO_IFN_D0, - GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_MSIOF3_SCK_A, - GPIO_FN_VI4_DATA16, - GPIO_FN_VI5_DATA0, - GPIO_IFN_D1, - GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_MSIOF3_SYNC_A, - GPIO_FN_VI4_DATA17, - GPIO_FN_VI5_DATA1, - GPIO_IFN_D2, - GPIO_FN_MSIOF3_RXD_A, - GPIO_FN_VI4_DATA18, - GPIO_FN_VI5_DATA2, - GPIO_IFN_D3, - GPIO_FN_MSIOF3_TXD_A, - GPIO_FN_VI4_DATA19, - GPIO_FN_VI5_DATA3, - GPIO_IFN_D4, - GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_VI4_DATA20, - GPIO_FN_VI5_DATA4, - - /* IPSR6 */ - GPIO_IFN_D5, - GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_VI4_DATA21, - GPIO_FN_VI5_DATA5, - GPIO_IFN_D6, - GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_VI4_DATA22, - GPIO_FN_VI5_DATA6, - GPIO_IFN_D7, - GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_VI4_DATA23, - GPIO_FN_VI5_DATA7, - GPIO_IFN_D8, - GPIO_FN_LCDOUT0, - GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SCK4_C, - GPIO_FN_VI4_DATA0_A, - GPIO_FN_DU_DR0, - GPIO_IFN_D9, - GPIO_FN_LCDOUT1, - GPIO_FN_MSIOF2_SYNC_D, - GPIO_FN_VI4_DATA1_A, - GPIO_FN_DU_DR1, - GPIO_IFN_D10, - GPIO_FN_LCDOUT2, - GPIO_FN_MSIOF2_RXD_D, - GPIO_FN_HRX3_B, - GPIO_FN_VI4_DATA2_A, - GPIO_FN_CTS4x_C, - GPIO_FN_DU_DR2, - GPIO_IFN_D11, - GPIO_FN_LCDOUT3, - GPIO_FN_MSIOF2_TXD_D, - GPIO_FN_HTX3_B, - GPIO_FN_VI4_DATA3_A, - GPIO_FN_RTS4x_TANS_C, - GPIO_FN_DU_DR3, - GPIO_IFN_D12, - GPIO_FN_LCDOUT4, - GPIO_FN_MSIOF2_SS1_D, - GPIO_FN_RX4_C, - GPIO_FN_VI4_DATA4_A, - GPIO_FN_DU_DR4, - - /* IPSR7 */ - GPIO_IFN_D13, - GPIO_FN_LCDOUT5, - GPIO_FN_MSIOF2_SS2_D, - GPIO_FN_TX4_C, - GPIO_FN_VI4_DATA5_A, - GPIO_FN_DU_DR5, - GPIO_IFN_D14, - GPIO_FN_LCDOUT6, - GPIO_FN_MSIOF3_SS1_A, - GPIO_FN_HRX3_C, - GPIO_FN_VI4_DATA6_A, - GPIO_FN_DU_DR6, - GPIO_FN_SCL6_C, - GPIO_IFN_D15, - GPIO_FN_LCDOUT7, - GPIO_FN_MSIOF3_SS2_A, - GPIO_FN_HTX3_C, - GPIO_FN_VI4_DATA7_A, - GPIO_FN_DU_DR7, - GPIO_FN_SDA6_C, - GPIO_FN_FSCLKST, - GPIO_IFN_SD0_CLK, - GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_STP_OPWM_0_B, - GPIO_IFN_SD0_CMD, - GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_STP_IVCXO27_0_B, - GPIO_IFN_SD0_DAT0, - GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_TS_SCK0_B, - GPIO_FN_STP_ISCLK_0_B, - GPIO_IFN_SD0_DAT1, - GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - GPIO_IFN_SD0_DAT2, - GPIO_FN_MSIOF1_SS1_E, - GPIO_FN_TS_SDAT0_B, - GPIO_FN_STP_ISD_0_B, - GPIO_IFN_SD0_DAT3, - GPIO_FN_MSIOF1_SS2_E, - GPIO_FN_TS_SDEN0_B, - GPIO_FN_STP_ISEN_0_B, - GPIO_IFN_SD1_CLK, - GPIO_FN_MSIOF1_SCK_G, - GPIO_FN_SIM0_CLK_A, - GPIO_IFN_SD1_CMD, - GPIO_FN_MSIOF1_SYNC_G, - GPIO_FN_NFCEx_B, - GPIO_FN_SIM0_D_A, - GPIO_FN_STP_IVCXO27_1_B, - GPIO_IFN_SD1_DAT0, - GPIO_FN_SD2_DAT4, - GPIO_FN_MSIOF1_RXD_G, - GPIO_FN_NFWPx_B, - GPIO_FN_TS_SCK1_B, - GPIO_FN_STP_ISCLK_1_B, - GPIO_IFN_SD1_DAT1, - GPIO_FN_SD2_DAT5, - GPIO_FN_MSIOF1_TXD_G, - GPIO_FN_NFDATA14_B, - GPIO_FN_TS_SPSYNC1_B, - GPIO_FN_STP_ISSYNC_1_B, - GPIO_IFN_SD1_DAT2, - GPIO_FN_SD2_DAT6, - GPIO_FN_MSIOF1_SS1_G, - GPIO_FN_NFDATA15_B, - GPIO_FN_TS_SDAT1_B, - GPIO_FN_STP_IOD_1_B, - GPIO_IFN_SD1_DAT3, - GPIO_FN_SD2_DAT7, - GPIO_FN_MSIOF1_SS2_G, - GPIO_FN_NFRBx_B, - GPIO_FN_TS_SDEN1_B, - GPIO_FN_STP_ISEN_1_B, - - /* IPSR9 */ - GPIO_IFN_SD2_CLK, - GPIO_FN_NFDATA8, - GPIO_IFN_SD2_CMD, - GPIO_FN_NFDATA9, - GPIO_IFN_SD2_DAT0, - GPIO_FN_NFDATA10, - GPIO_IFN_SD2_DAT1, - GPIO_FN_NFDATA11, - GPIO_IFN_SD2_DAT2, - GPIO_FN_NFDATA12, - GPIO_IFN_SD2_DAT3, - GPIO_FN_NFDATA13, - GPIO_IFN_SD2_DS, - GPIO_FN_NFALE, - GPIO_FN_SATA_DEVSLP_B, - GPIO_IFN_SD3_CLK, - GPIO_FN_NFWEx, - - /* IPSR10 */ - GPIO_IFN_SD3_CMD, - GPIO_FN_NFREx, - GPIO_IFN_SD3_DAT0, - GPIO_FN_NFDATA0, - GPIO_IFN_SD3_DAT1, - GPIO_FN_NFDATA1, - GPIO_IFN_SD3_DAT2, - GPIO_FN_NFDATA2, - GPIO_IFN_SD3_DAT3, - GPIO_FN_NFDATA3, - GPIO_IFN_SD3_DAT4, - GPIO_FN_SD2_CD_A, - GPIO_FN_NFDATA4, - GPIO_IFN_SD3_DAT5, - GPIO_FN_SD2_WP_A, - GPIO_FN_NFDATA5, - GPIO_IFN_SD3_DAT6, - GPIO_FN_SD3_CD, - GPIO_FN_NFDATA6, - - /* IPSR11 */ - GPIO_IFN_SD3_DAT7, - GPIO_FN_SD3_WP, - GPIO_FN_NFDATA7, - GPIO_IFN_SD3_DS, - GPIO_FN_NFCLE, - GPIO_IFN_SD0_CD, - GPIO_FN_NFDATA14_A, - GPIO_FN_SCL2_B, - GPIO_FN_SIM0_RST_A, - GPIO_IFN_SD0_WP, - GPIO_FN_NFDATA15_A, - GPIO_FN_SDA2_B, - GPIO_IFN_SD1_CD, - GPIO_FN_NFRBx_A, - GPIO_FN_SIM0_CLK_B, - GPIO_IFN_SD1_WP, - GPIO_FN_NFCEx_A, - GPIO_FN_SIM0_D_B, - GPIO_IFN_SCK0, - GPIO_FN_HSCK1_B, - GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_AUDIO_CLKC_B, - GPIO_FN_SDA2_A, - GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM_0_C, - GPIO_FN_RIF0_CLK_B, - GPIO_FN_ADICHS2, - GPIO_FN_SCK5_B, - GPIO_IFN_RX0, - GPIO_FN_HRX1_B, - GPIO_FN_TS_SCK0_C, - GPIO_FN_STP_ISCLK_0_C, - GPIO_FN_RIF0_D0_B, - - /* IPSR12 */ - GPIO_IFN_TX0, - GPIO_FN_HTX1_B, - GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_RIF0_D1_B, - GPIO_IFN_CTS0x, - GPIO_FN_HCTS1x_B, - GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_TS_SPSYNC1_C, - GPIO_FN_STP_ISSYNC_1_C, - GPIO_FN_RIF1_SYNC_B, - GPIO_FN_AUDIO_CLKOUT_C, - GPIO_FN_ADICS_SAMP, - GPIO_IFN_RTS0x_TANS, - GPIO_FN_HRTS1x_B, - GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_AUDIO_CLKA_B, - GPIO_FN_SCL2_A, - GPIO_FN_STP_IVCXO27_1_C, - GPIO_FN_RIF0_SYNC_B, - GPIO_FN_ADICHS1, - GPIO_IFN_RX1_A, - GPIO_FN_HRX1_A, - GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_ISD_0_C, - GPIO_FN_RIF1_CLK_C, - GPIO_IFN_TX1_A, - GPIO_FN_HTX1_A, - GPIO_FN_TS_SDEN0_C, - GPIO_FN_STP_ISEN_0_C, - GPIO_FN_RIF1_D0_C, - GPIO_IFN_CTS1x, - GPIO_FN_HCTS1x_A, - GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_TS_SDEN1_C, - GPIO_FN_STP_ISEN_1_C, - GPIO_FN_RIF1_D0_B, - GPIO_FN_ADIDATA, - GPIO_IFN_RTS1x_TANS, - GPIO_FN_HRTS1x_A, - GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TS_SDAT1_C, - GPIO_FN_STP_ISD_1_C, - GPIO_FN_RIF1_D1_B, - GPIO_FN_ADICHS0, - GPIO_IFN_SCK2, - GPIO_FN_SCIF_CLK_B, - GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_TS_SCK1_C, - GPIO_FN_STP_ISCLK_1_C, - GPIO_FN_RIF1_CLK_B, - GPIO_FN_ADICLK, - - /* IPSR13 */ - GPIO_IFN_TX2_A, - GPIO_FN_SD2_CD_B, - GPIO_FN_SCL1_A, - GPIO_FN_FMCLK_A, - GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0x, - GPIO_IFN_RX2_A, - GPIO_FN_SD2_WP_B, - GPIO_FN_SDA1_A, - GPIO_FN_FMIN_A, - GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CFE_1x, - GPIO_IFN_HSCK0, - GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_AUDIO_CLKB_A, - GPIO_FN_SSI_SDATA1_B, - GPIO_FN_TS_SCK0_D, - GPIO_FN_STP_ISCLK_0_D, - GPIO_FN_RIF0_CLK_C, - GPIO_FN_RX5_B, - GPIO_IFN_HRX0, - GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SSI_SDATA2_B, - GPIO_FN_TS_SDEN0_D, - GPIO_FN_STP_ISEN_0_D, - GPIO_FN_RIF0_D0_C, - GPIO_IFN_HTX0, - GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_SSI_SDATA9_B, - GPIO_FN_TS_SDAT0_D, - GPIO_FN_STP_ISD_0_D, - GPIO_FN_RIF0_D1_C, - GPIO_IFN_HCTS0x, - GPIO_FN_RX2_B, - GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_SSI_SCK9_A, - GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_STP_ISSYNC_0_D, - GPIO_FN_RIF0_SYNC_C, - GPIO_FN_AUDIO_CLKOUT1_A, - GPIO_IFN_HRTS0x, - GPIO_FN_TX2_B, - GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_SSI_WS9_A, - GPIO_FN_STP_IVCXO27_0_D, - GPIO_FN_BPFCLK_A, - GPIO_FN_AUDIO_CLKOUT2_A, - GPIO_IFN_MSIOF0_SYNC, - GPIO_FN_AUDIO_CLKOUT_A, - GPIO_FN_TX5_B, - GPIO_FN_BPFCLK_D, - - /* IPSR14 */ - GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5_A, - GPIO_FN_NFWPx_A, - GPIO_FN_AUDIO_CLKA_C, - GPIO_FN_SSI_SCK2_A, - GPIO_FN_STP_IVCXO27_0_C, - GPIO_FN_AUDIO_CLKOUT3_A, - GPIO_FN_TCLK1_B, - GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5_A, - GPIO_FN_MSIOF1_SS2_D, - GPIO_FN_AUDIO_CLKC_A, - GPIO_FN_SSI_WS2_A, - GPIO_FN_STP_OPWM_0_D, - GPIO_FN_AUDIO_CLKOUT_D, - GPIO_FN_SPEEDIN_B, - GPIO_IFN_MLB_CLK, - GPIO_FN_MSIOF1_SCK_F, - GPIO_FN_SCL1_B, - GPIO_IFN_MLB_SIG, - GPIO_FN_RX1_B, - GPIO_FN_MSIOF1_SYNC_F, - GPIO_FN_SDA1_B, - GPIO_IFN_MLB_DAT, - GPIO_FN_TX1_B, - GPIO_FN_MSIOF1_RXD_F, - GPIO_IFN_SSI_SCK01239, - GPIO_FN_MSIOF1_TXD_F, - GPIO_FN_MOUT0, - GPIO_IFN_SSI_WS01239, - GPIO_FN_MSIOF1_SS1_F, - GPIO_FN_MOUT1, - GPIO_IFN_SSI_SDATA0, - GPIO_FN_MSIOF1_SS2_F, - GPIO_FN_MOUT2, - - /* IPSR15 */ - GPIO_IFN_SSI_SDATA1_A, - GPIO_FN_MOUT5, - GPIO_IFN_SSI_SDATA2_A, - GPIO_FN_SSI_SCK1_B, - GPIO_FN_MOUT6, - GPIO_IFN_SSI_SCK34, - GPIO_FN_MSIOF1_SS1_A, - GPIO_FN_STP_OPWM_0_A, - GPIO_IFN_SSI_WS34, - GPIO_FN_HCTS2x_A, - GPIO_FN_MSIOF1_SS2_A, - GPIO_FN_STP_IVCXO27_0_A, - GPIO_IFN_SSI_SDATA3, - GPIO_FN_HRTS2x_A, - GPIO_FN_MSIOF1_TXD_A, - GPIO_FN_TS_SCK0_A, - GPIO_FN_STP_ISCLK_0_A, - GPIO_FN_RIF0_D1_A, - GPIO_FN_RIF2_D0_A, - GPIO_IFN_SSI_SCK4, - GPIO_FN_HRX2_A, - GPIO_FN_MSIOF1_SCK_A, - GPIO_FN_TS_SDAT0_A, - GPIO_FN_STP_ISD_0_A, - GPIO_FN_RIF0_CLK_A, - GPIO_FN_RIF2_CLK_A, - GPIO_IFN_SSI_WS4, - GPIO_FN_HTX2_A, - GPIO_FN_MSIOF1_SYNC_A, - GPIO_FN_TS_SDEN0_A, - GPIO_FN_STP_ISEN_0_A, - GPIO_FN_RIF0_SYNC_A, - GPIO_FN_RIF2_SYNC_A, - GPIO_IFN_SSI_SDATA4, - GPIO_FN_HSCK2_A, - GPIO_FN_MSIOF1_RXD_A, - GPIO_FN_TS_SPSYNC0_A, - GPIO_FN_STP_ISSYNC_0_A, - GPIO_FN_RIF0_D0_A, - GPIO_FN_RIF2_D1_A, - - /* IPSR16 */ - GPIO_IFN_SSI_SCK6, - GPIO_FN_SIM0_RST_D, - GPIO_IFN_SSI_WS6, - GPIO_FN_SIM0_D_D, - GPIO_IFN_SSI_SDATA6, - GPIO_FN_SIM0_CLK_D, - GPIO_FN_SATA_DEVSLP_A, - GPIO_IFN_SSI_SCK78, - GPIO_FN_HRX2_B, - GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SCK1_A, - GPIO_FN_STP_ISCLK_1_A, - GPIO_FN_RIF1_CLK_A, - GPIO_FN_RIF3_CLK_A, - GPIO_IFN_SSI_WS78, - GPIO_FN_HTX2_B, - GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDAT1_A, - GPIO_FN_STP_ISD_1_A, - GPIO_FN_RIF1_SYNC_A, - GPIO_FN_RIF3_SYNC_A, - GPIO_IFN_SSI_SDATA7, - GPIO_FN_HCTS2x_B, - GPIO_FN_MSIOF1_RXD_C, - GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_ISEN_1_A, - GPIO_FN_RIF1_D0_A, - GPIO_FN_RIF3_D0_A, - GPIO_FN_TCLK2_A, - GPIO_IFN_SSI_SDATA8, - GPIO_FN_HRTS2x_B, - GPIO_FN_MSIOF1_TXD_C, - GPIO_FN_TS_SPSYNC1_A, - GPIO_FN_STP_ISSYNC_1_A, - GPIO_FN_RIF1_D1_A, - GPIO_FN_RIF3_D1_A, - GPIO_IFN_SSI_SDATA9_A, - GPIO_FN_HSCK2_B, - GPIO_FN_MSIOF1_SS1_C, - GPIO_FN_HSCK1_A, - GPIO_FN_SSI_WS1_B, - GPIO_FN_SCK1, - GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5_A, - - /* IPSR17 */ - GPIO_IFN_AUDIO_CLKA_A, - GPIO_FN_CC5_OSCOUT, - GPIO_IFN_AUDIO_CLKB_B, - GPIO_FN_SCIF_CLK_A, - GPIO_FN_STP_IVCXO27_1_D, - GPIO_FN_REMOCON_A, - GPIO_FN_TCLK1_A, - GPIO_IFN_USB0_PWEN, - GPIO_FN_SIM0_RST_C, - GPIO_FN_TS_SCK1_D, - GPIO_FN_STP_ISCLK_1_D, - GPIO_FN_BPFCLK_B, - GPIO_FN_RIF3_CLK_B, - GPIO_FN_HSCK2_C, - GPIO_IFN_USB0_OVC, - GPIO_FN_SIM0_D_C, - GPIO_FN_TS_SDAT1_D, - GPIO_FN_STP_ISD_1_D, - GPIO_FN_RIF3_SYNC_B, - GPIO_FN_HRX2_C, - GPIO_IFN_USB1_PWEN, - GPIO_FN_SIM0_CLK_C, - GPIO_FN_SSI_SCK1_A, - GPIO_FN_TS_SCK0_E, - GPIO_FN_STP_ISCLK_0_E, - GPIO_FN_FMCLK_B, - GPIO_FN_RIF2_CLK_B, - GPIO_FN_SPEEDIN_A, - GPIO_FN_HTX2_C, - GPIO_IFN_USB1_OVC, - GPIO_FN_MSIOF1_SS2_C, - GPIO_FN_SSI_WS1_A, - GPIO_FN_TS_SDAT0_E, - GPIO_FN_STP_ISD_0_E, - GPIO_FN_FMIN_B, - GPIO_FN_RIF2_SYNC_B, - GPIO_FN_REMOCON_B, - GPIO_FN_HCTS2x_C, - GPIO_IFN_USB30_PWEN, - GPIO_FN_AUDIO_CLKOUT_B, - GPIO_FN_SSI_SCK2_B, - GPIO_FN_TS_SDEN1_D, - GPIO_FN_STP_ISEN_1_D, - GPIO_FN_STP_OPWM_0_E, - GPIO_FN_RIF3_D0_B, - GPIO_FN_TCLK2_B, - GPIO_FN_TPU0TO0, - GPIO_FN_BPFCLK_C, - GPIO_FN_HRTS2x_C, - GPIO_IFN_USB30_OVC, - GPIO_FN_AUDIO_CLKOUT1_B, - GPIO_FN_SSI_WS2_B, - GPIO_FN_TS_SPSYNC1_D, - GPIO_FN_STP_ISSYNC_1_D, - GPIO_FN_STP_IVCXO27_0_E, - GPIO_FN_RIF3_D1_B, - GPIO_FN_FSO_TOEx, - GPIO_FN_TPU0TO1, - - /* IPSR18 */ - GPIO_IFN_USB3_PWEN, - GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SSI_SCK9_B, - GPIO_FN_TS_SDEN0_E, - GPIO_FN_STP_ISEN_0_E, - GPIO_FN_RIF2_D0_B, - GPIO_FN_TPU0TO2, - GPIO_FN_FMCLK_C, - GPIO_FN_FMCLK_D, - GPIO_IFN_USB3_OVC, - GPIO_FN_AUDIO_CLKOUT3_B, - GPIO_FN_SSI_WS9_B, - GPIO_FN_TS_SPSYNC0_E, - GPIO_FN_STP_ISSYNC_0_E, - GPIO_FN_RIF2_D1_B, - GPIO_FN_TPU0TO3, - GPIO_FN_FMIN_C, - GPIO_FN_FMIN_D, -}; - -#endif /* __ASM_R8A7795_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795.h b/arch/arm/mach-rmobile/include/mach/r8a7795.h deleted file mode 100644 index 2d004b6a540..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7795.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-rmobile/include/mach/r8a7795.h - * This file defines registers and value for r8a7795. - * - * Copyright (C) 2015 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_R8A7795_H -#define __ASM_ARCH_R8A7795_H - -#include "rcar-gen3-base.h" - -/* Module stop control/status register bits */ -#define MSTP0_BITS 0x00640800 -#define MSTP1_BITS 0xF3EE9390 -#define MSTP2_BITS 0x340FAFDC -#define MSTP3_BITS 0xD80C7CDF -#define MSTP4_BITS 0x80000184 -#define MSTP5_BITS 0x40BFFF46 -#define MSTP6_BITS 0xE5FBEECF -#define MSTP7_BITS 0x39FFFF0E -#define MSTP8_BITS 0x01F19FF4 -#define MSTP9_BITS 0xFFDFFFFF -#define MSTP10_BITS 0xFFFEFFE0 -#define MSTP11_BITS 0x00000000 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 - -#endif /* __ASM_ARCH_R8A7795_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h deleted file mode 100644 index 2359e36a14d..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h +++ /dev/null @@ -1,1084 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7796-gpio.h - * This file defines pin function control of gpio. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_R8A7796_GPIO_H__ -#define __ASM_R8A7796_GPIO_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU - */ -enum { - GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, - GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, - GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, - GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, - - GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, - GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, - GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, - GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, - GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, - GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, - GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, - GPIO_GP_1_28, - - GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, - GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, - GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, - GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, - - GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, - GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, - GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, - GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, - - GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, - GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, - GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, - GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, - GPIO_GP_4_16, GPIO_GP_4_17, - - GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, - GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, - GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, - GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, - GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, - GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, - GPIO_GP_5_24, GPIO_GP_5_25, - - GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, - GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, - GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, - GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, - GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, - GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, - GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, - GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, - - GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, - - /* GPSR0 */ - GPIO_GFN_D15, - GPIO_GFN_D14, - GPIO_GFN_D13, - GPIO_GFN_D12, - GPIO_GFN_D11, - GPIO_GFN_D10, - GPIO_GFN_D9, - GPIO_GFN_D8, - GPIO_GFN_D7, - GPIO_GFN_D6, - GPIO_GFN_D5, - GPIO_GFN_D4, - GPIO_GFN_D3, - GPIO_GFN_D2, - GPIO_GFN_D1, - GPIO_GFN_D0, - - /* GPSR1 */ - GPIO_GFN_CLKOUT, - GPIO_GFN_EX_WAIT0_A, - GPIO_GFN_WE1x, - GPIO_GFN_WE0x, - GPIO_GFN_RD_WRx, - GPIO_GFN_RDx, - GPIO_GFN_BSx, - GPIO_GFN_CS1x_A26, - GPIO_GFN_CS0x, - GPIO_GFN_A19, - GPIO_GFN_A18, - GPIO_GFN_A17, - GPIO_GFN_A16, - GPIO_GFN_A15, - GPIO_GFN_A14, - GPIO_GFN_A13, - GPIO_GFN_A12, - GPIO_GFN_A11, - GPIO_GFN_A10, - GPIO_GFN_A9, - GPIO_GFN_A8, - GPIO_GFN_A7, - GPIO_GFN_A6, - GPIO_GFN_A5, - GPIO_GFN_A4, - GPIO_GFN_A3, - GPIO_GFN_A2, - GPIO_GFN_A1, - GPIO_GFN_A0, - - /* GPSR2 */ - GPIO_GFN_AVB_AVTP_CAPTURE_A, - GPIO_GFN_AVB_AVTP_MATCH_A, - GPIO_GFN_AVB_LINK, - GPIO_GFN_AVB_PHY_INT, - GPIO_GFN_AVB_MAGIC, - GPIO_GFN_AVB_MDC, - GPIO_GFN_PWM2_A, - GPIO_GFN_PWM1_A, - GPIO_GFN_PWM0, - GPIO_GFN_IRQ5, - GPIO_GFN_IRQ4, - GPIO_GFN_IRQ3, - GPIO_GFN_IRQ2, - GPIO_GFN_IRQ1, - GPIO_GFN_IRQ0, - - /* GPSR3 */ - GPIO_GFN_SD1_WP, - GPIO_GFN_SD1_CD, - GPIO_GFN_SD0_WP, - GPIO_GFN_SD0_CD, - GPIO_GFN_SD1_DAT3, - GPIO_GFN_SD1_DAT2, - GPIO_GFN_SD1_DAT1, - GPIO_GFN_SD1_DAT0, - GPIO_GFN_SD1_CMD, - GPIO_GFN_SD1_CLK, - GPIO_GFN_SD0_DAT3, - GPIO_GFN_SD0_DAT2, - GPIO_GFN_SD0_DAT1, - GPIO_GFN_SD0_DAT0, - GPIO_GFN_SD0_CMD, - GPIO_GFN_SD0_CLK, - - /* GPSR4 */ - GPIO_GFN_SD3_DS, - GPIO_GFN_SD3_DAT7, - GPIO_GFN_SD3_DAT6, - GPIO_GFN_SD3_DAT5, - GPIO_GFN_SD3_DAT4, - GPIO_FN_SD3_DAT3, - GPIO_FN_SD3_DAT2, - GPIO_FN_SD3_DAT1, - GPIO_FN_SD3_DAT0, - GPIO_FN_SD3_CMD, - GPIO_FN_SD3_CLK, - GPIO_GFN_SD2_DS, - GPIO_GFN_SD2_DAT3, - GPIO_GFN_SD2_DAT2, - GPIO_GFN_SD2_DAT1, - GPIO_GFN_SD2_DAT0, - GPIO_FN_SD2_CMD, - GPIO_GFN_SD2_CLK, - - /* GPSR5 */ - GPIO_GFN_MLB_DAT, - GPIO_GFN_MLB_SIG, - GPIO_GFN_MLB_CLK, - GPIO_FN_MSIOF0_RXD, - GPIO_GFN_MSIOF0_SS2, - GPIO_FN_MSIOF0_TXD, - GPIO_GFN_MSIOF0_SS1, - GPIO_GFN_MSIOF0_SYNC, - GPIO_FN_MSIOF0_SCK, - GPIO_GFN_HRTS0x, - GPIO_GFN_HCTS0x, - GPIO_GFN_HTX0, - GPIO_GFN_HRX0, - GPIO_GFN_HSCK0, - GPIO_GFN_RX2_A, - GPIO_GFN_TX2_A, - GPIO_GFN_SCK2, - GPIO_GFN_RTS1x_TANS, - GPIO_GFN_CTS1x, - GPIO_GFN_TX1_A, - GPIO_GFN_RX1_A, - GPIO_GFN_RTS0x_TANS, - GPIO_GFN_CTS0x, - GPIO_GFN_TX0, - GPIO_GFN_RX0, - GPIO_GFN_SCK0, - - /* GPSR6 */ - GPIO_GFN_GP6_31, - GPIO_GFN_GP6_30, - GPIO_GFN_USB30_OVC, - GPIO_GFN_USB30_PWEN, - GPIO_GFN_USB1_OVC, - GPIO_GFN_USB1_PWEN, - GPIO_GFN_USB0_OVC, - GPIO_GFN_USB0_PWEN, - GPIO_GFN_AUDIO_CLKB_B, - GPIO_GFN_AUDIO_CLKA_A, - GPIO_GFN_SSI_SDATA9_A, - GPIO_GFN_SSI_SDATA8, - GPIO_GFN_SSI_SDATA7, - GPIO_GFN_SSI_WS78, - GPIO_GFN_SSI_SCK78, - GPIO_GFN_SSI_SDATA6, - GPIO_GFN_SSI_WS6, - GPIO_GFN_SSI_SCK6, - GPIO_FN_SSI_SDATA5, - GPIO_FN_SSI_WS5, - GPIO_FN_SSI_SCK5, - GPIO_GFN_SSI_SDATA4, - GPIO_GFN_SSI_WS4, - GPIO_GFN_SSI_SCK4, - GPIO_GFN_SSI_SDATA3, - GPIO_GFN_SSI_WS34, - GPIO_GFN_SSI_SCK34, - GPIO_GFN_SSI_SDATA2_A, - GPIO_GFN_SSI_SDATA1_A, - GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS01239, - GPIO_GFN_SSI_SCK01239, - - /* GPSR7 */ - GPIO_FN_HDMI1_CEC, - GPIO_FN_HDMI0_CEC, - GPIO_FN_AVS2, - GPIO_FN_AVS1, - - /* IPSR0 */ - GPIO_IFN_AVB_MDC, - GPIO_FN_MSIOF2_SS2_C, - GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_SS1_C, - GPIO_FN_SCK4_A, - GPIO_IFN_AVB_PHY_INT, - GPIO_FN_MSIOF2_SYNC_C, - GPIO_FN_RX4_A, - GPIO_IFN_AVB_LINK, - GPIO_FN_MSIOF2_SCK_C, - GPIO_FN_TX4_A, - GPIO_IFN_AVB_AVTP_MATCH_A, - GPIO_FN_MSIOF2_RXD_C, - GPIO_FN_CTS4x_A, - GPIO_IFN_AVB_AVTP_CAPTURE_A, - GPIO_FN_MSIOF2_TXD_C, - GPIO_FN_RTS4x_TANS_A, - GPIO_IFN_IRQ0, - GPIO_FN_QPOLB, - GPIO_FN_DU_CDE, - GPIO_FN_VI4_DATA0_B, - GPIO_FN_CAN0_TX_B, - GPIO_FN_CANFD0_TX_B, - GPIO_FN_MSIOF3_SS2_E, - GPIO_IFN_IRQ1, - GPIO_FN_QPOLA, - GPIO_FN_DU_DISP, - GPIO_FN_VI4_DATA1_B, - GPIO_FN_CAN0_RX_B, - GPIO_FN_CANFD0_RX_B, - GPIO_FN_MSIOF3_SS1_E, - - /* IPSR1 */ - GPIO_IFN_IRQ2, - GPIO_FN_QCPV_QDE, - GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, - GPIO_FN_VI4_DATA2_B, - GPIO_FN_MSIOF3_SYNC_E, - GPIO_FN_PWM3_B, - GPIO_IFN_IRQ3, - GPIO_FN_QSTVB_QVE, - GPIO_FN_DU_DOTCLKOUT1, - GPIO_FN_VI4_DATA3_B, - GPIO_FN_MSIOF3_SCK_E, - GPIO_FN_PWM4_B, - GPIO_IFN_IRQ4, - GPIO_FN_QSTH_QHS, - GPIO_FN_DU_EXHSYNC_DU_HSYNC, - GPIO_FN_VI4_DATA4_B, - GPIO_FN_MSIOF3_RXD_E, - GPIO_FN_PWM5_B, - GPIO_IFN_IRQ5, - GPIO_FN_QSTB_QHE, - GPIO_FN_DU_EXVSYNC_DU_VSYNC, - GPIO_FN_VI4_DATA5_B, - GPIO_FN_MSIOF3_TXD_E, - GPIO_FN_PWM6_B, - GPIO_IFN_PWM0, - GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_VI4_DATA6_B, - GPIO_FN_IECLK_B, - GPIO_IFN_PWM1_A, - GPIO_FN_HRX3_D, - GPIO_FN_VI4_DATA7_B, - GPIO_FN_IERX_B, - GPIO_IFN_PWM2_A, - GPIO_FN_PWMFSW0, - GPIO_FN_HTX3_D, - GPIO_FN_IETX_B, - GPIO_IFN_A0, - GPIO_FN_LCDOUT16, - GPIO_FN_MSIOF3_SYNC_B, - GPIO_FN_VI4_DATA8, - GPIO_FN_DU_DB0, - GPIO_FN_PWM3_A, - - /* IPSR2 */ - GPIO_IFN_A1, - GPIO_FN_LCDOUT17, - GPIO_FN_MSIOF3_TXD_B, - GPIO_FN_VI4_DATA9, - GPIO_FN_DU_DB1, - GPIO_FN_PWM4_A, - GPIO_IFN_A2, - GPIO_FN_LCDOUT18, - GPIO_FN_MSIOF3_SCK_B, - GPIO_FN_VI4_DATA10, - GPIO_FN_DU_DB2, - GPIO_FN_PWM5_A, - GPIO_IFN_A3, - GPIO_FN_LCDOUT19, - GPIO_FN_MSIOF3_RXD_B, - GPIO_FN_VI4_DATA11, - GPIO_FN_DU_DB3, - GPIO_FN_PWM6_A, - GPIO_IFN_A4, - GPIO_FN_LCDOUT20, - GPIO_FN_MSIOF3_SS1_B, - GPIO_FN_VI4_DATA12, - GPIO_FN_VI5_DATA12, - GPIO_FN_DU_DB4, - GPIO_IFN_A5, - GPIO_FN_LCDOUT21, - GPIO_FN_MSIOF3_SS2_B, - GPIO_FN_SCK4_B, - GPIO_FN_VI4_DATA13, - GPIO_FN_VI5_DATA13, - GPIO_FN_DU_DB5, - GPIO_IFN_A6, - GPIO_FN_LCDOUT22, - GPIO_FN_MSIOF2_SS1_A, - GPIO_FN_RX4_B, - GPIO_FN_VI4_DATA14, - GPIO_FN_VI5_DATA14, - GPIO_FN_DU_DB6, - GPIO_IFN_A7, - GPIO_FN_LCDOUT23, - GPIO_FN_MSIOF2_SS2_A, - GPIO_FN_TX4_B, - GPIO_FN_VI4_DATA15, - GPIO_FN_V15_DATA15, - GPIO_FN_DU_DB7, - GPIO_IFN_A8, - GPIO_FN_RX3_B, - GPIO_FN_MSIOF2_SYNC_A, - GPIO_FN_HRX4_B, - GPIO_FN_SDA6_A, - GPIO_FN_AVB_AVTP_MATCH_B, - GPIO_FN_PWM1_B, - - /* IPSR3 */ - GPIO_IFN_A9, - GPIO_FN_MSIOF2_SCK_A, - GPIO_FN_CTS4x_B, - GPIO_FN_VI5_VSYNCx, - GPIO_IFN_A10, - GPIO_FN_MSIOF2_RXD_A, - GPIO_FN_RTS4n_TANS_B, - GPIO_FN_VI5_HSYNCx, - GPIO_IFN_A11, - GPIO_FN_TX3_B, - GPIO_FN_MSIOF2_TXD_A, - GPIO_FN_HTX4_B, - GPIO_FN_HSCK4, - GPIO_FN_VI5_FIELD, - GPIO_FN_SCL6_A, - GPIO_FN_AVB_AVTP_CAPTURE_B, - GPIO_FN_PWM2_B, - GPIO_FN_SPV_EVEN, - GPIO_IFN_A12, - GPIO_FN_LCDOUT12, - GPIO_FN_MSIOF3_SCK_C, - GPIO_FN_HRX4_A, - GPIO_FN_VI5_DATA8, - GPIO_FN_DU_DG4, - GPIO_IFN_A13, - GPIO_FN_LCDOUT13, - GPIO_FN_MSIOF3_SYNC_C, - GPIO_FN_HTX4_A, - GPIO_FN_VI5_DATA9, - GPIO_FN_DU_DG5, - GPIO_IFN_A14, - GPIO_FN_LCDOUT14, - GPIO_FN_MSIOF3_RXD_C, - GPIO_FN_HCTS4x, - GPIO_FN_VI5_DATA10, - GPIO_FN_DU_DG6, - GPIO_IFN_A15, - GPIO_FN_LCDOUT15, - GPIO_FN_MSIOF3_TXD_C, - GPIO_FN_HRTS4x, - GPIO_FN_VI5_DATA11, - GPIO_FN_DU_DG7, - GPIO_IFN_A16, - GPIO_FN_LCDOUT8, - GPIO_FN_VI4_FIELD, - GPIO_FN_DU_DG0, - - /* IPSR4 */ - GPIO_IFN_A17, - GPIO_FN_LCDOUT9, - GPIO_FN_VI4_VSYNCx, - GPIO_FN_DU_DG1, - GPIO_IFN_A18, - GPIO_FN_LCDOUT10, - GPIO_FN_VI4_HSYNCx, - GPIO_FN_DU_DG2, - GPIO_IFN_A19, - GPIO_FN_LCDOUT11, - GPIO_FN_VI4_CLKENB, - GPIO_FN_DU_DG3, - GPIO_IFN_CS0x, - GPIO_FN_VI5_CLKENB, - GPIO_IFN_CS1x_A26, - GPIO_FN_VI5_CLK, - GPIO_FN_EX_WAIT0_B, - GPIO_IFN_BSx, - GPIO_FN_QSTVA_QVS, - GPIO_FN_MSIOF3_SCK_D, - GPIO_FN_SCK3, - GPIO_FN_HSCK3, - GPIO_FN_CAN1_TX, - GPIO_FN_CANFD1_TX, - GPIO_FN_IETX_A, - GPIO_IFN_RDx, - GPIO_FN_MSIOF3_SYNC_D, - GPIO_FN_RX3_A, - GPIO_FN_HRX3_A, - GPIO_FN_CAN0_TX_A, - GPIO_FN_CANFD0_TX_A, - GPIO_IFN_RD_WRx, - GPIO_FN_MSIOF3_RXD_D, - GPIO_FN_TX3_A, - GPIO_FN_HTX3_A, - GPIO_FN_CAN0_RX_A, - GPIO_FN_CANFD0_RX_A, - - /* IPSR5 */ - GPIO_IFN_WE0x, - GPIO_FN_MSIIOF3_TXD_D, - GPIO_FN_CTS3x, - GPIO_FN_HCTS3x, - GPIO_FN_SCL6_B, - GPIO_FN_CAN_CLK, - GPIO_FN_IECLK_A, - GPIO_IFN_WE1x, - GPIO_FN_MSIOF3_SS1_D, - GPIO_FN_RTS3x_TANS, - GPIO_FN_HRTS3x, - GPIO_FN_SDA6_B, - GPIO_FN_CAN1_RX, - GPIO_FN_CANFD1_RX, - GPIO_FN_IERX_A, - GPIO_IFN_EX_WAIT0_A, - GPIO_FN_QCLK, - GPIO_FN_VI4_CLK, - GPIO_FN_DU_DOTCLKOUT0, - GPIO_IFN_D0, - GPIO_FN_MSIOF2_SS1_B, - GPIO_FN_MSIOF3_SCK_A, - GPIO_FN_VI4_DATA16, - GPIO_FN_VI5_DATA0, - GPIO_IFN_D1, - GPIO_FN_MSIOF2_SS2_B, - GPIO_FN_MSIOF3_SYNC_A, - GPIO_FN_VI4_DATA17, - GPIO_FN_VI5_DATA1, - GPIO_IFN_D2, - GPIO_FN_MSIOF3_RXD_A, - GPIO_FN_VI4_DATA18, - GPIO_FN_VI5_DATA2, - GPIO_IFN_D3, - GPIO_FN_MSIOF3_TXD_A, - GPIO_FN_VI4_DATA19, - GPIO_FN_VI5_DATA3, - GPIO_IFN_D4, - GPIO_FN_MSIOF2_SCK_B, - GPIO_FN_VI4_DATA20, - GPIO_FN_VI5_DATA4, - - /* IPSR6 */ - GPIO_IFN_D5, - GPIO_FN_MSIOF2_SYNC_B, - GPIO_FN_VI4_DATA21, - GPIO_FN_VI5_DATA5, - GPIO_IFN_D6, - GPIO_FN_MSIOF2_RXD_B, - GPIO_FN_VI4_DATA22, - GPIO_FN_VI5_DATA6, - GPIO_IFN_D7, - GPIO_FN_MSIOF2_TXD_B, - GPIO_FN_VI4_DATA23, - GPIO_FN_VI5_DATA7, - GPIO_IFN_D8, - GPIO_FN_LCDOUT0, - GPIO_FN_MSIOF2_SCK_D, - GPIO_FN_SCK4_C, - GPIO_FN_VI4_DATA0_A, - GPIO_FN_DU_DR0, - GPIO_IFN_D9, - GPIO_FN_LCDOUT1, - GPIO_FN_MSIOF2_SYNC_D, - GPIO_FN_VI4_DATA1_A, - GPIO_FN_DU_DR1, - GPIO_IFN_D10, - GPIO_FN_LCDOUT2, - GPIO_FN_MSIOF2_RXD_D, - GPIO_FN_HRX3_B, - GPIO_FN_VI4_DATA2_A, - GPIO_FN_CTS4x_C, - GPIO_FN_DU_DR2, - GPIO_IFN_D11, - GPIO_FN_LCDOUT3, - GPIO_FN_MSIOF2_TXD_D, - GPIO_FN_HTX3_B, - GPIO_FN_VI4_DATA3_A, - GPIO_FN_RTS4x_TANS_C, - GPIO_FN_DU_DR3, - GPIO_IFN_D12, - GPIO_FN_LCDOUT4, - GPIO_FN_MSIOF2_SS1_D, - GPIO_FN_RX4_C, - GPIO_FN_VI4_DATA4_A, - GPIO_FN_DU_DR4, - - /* IPSR7 */ - GPIO_IFN_D13, - GPIO_FN_LCDOUT5, - GPIO_FN_MSIOF2_SS2_D, - GPIO_FN_TX4_C, - GPIO_FN_VI4_DATA5_A, - GPIO_FN_DU_DR5, - GPIO_IFN_D14, - GPIO_FN_LCDOUT6, - GPIO_FN_MSIOF3_SS1_A, - GPIO_FN_HRX3_C, - GPIO_FN_VI4_DATA6_A, - GPIO_FN_DU_DR6, - GPIO_FN_SCL6_C, - GPIO_IFN_D15, - GPIO_FN_LCDOUT7, - GPIO_FN_MSIOF3_SS2_A, - GPIO_FN_HTX3_C, - GPIO_FN_VI4_DATA7_A, - GPIO_FN_DU_DR7, - GPIO_FN_SDA6_C, - GPIO_FN_FSCLKST, - GPIO_IFN_SD0_CLK, - GPIO_FN_MSIOF1_SCK_E, - GPIO_FN_STP_OPWM_0_B, - GPIO_IFN_SD0_CMD, - GPIO_FN_MSIOF1_SYNC_E, - GPIO_FN_STP_IVCXO27_0_B, - GPIO_IFN_SD0_DAT0, - GPIO_FN_MSIOF1_RXD_E, - GPIO_FN_TS_SCK0_B, - GPIO_FN_STP_ISCLK_0_B, - GPIO_IFN_SD0_DAT1, - GPIO_FN_MSIOF1_TXD_E, - GPIO_FN_TS_SPSYNC0_B, - GPIO_FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - GPIO_IFN_SD0_DAT2, - GPIO_FN_MSIOF1_SS1_E, - GPIO_FN_TS_SDAT0_B, - GPIO_FN_STP_ISD_0_B, - - GPIO_IFN_SD0_DAT3, - GPIO_FN_MSIOF1_SS2_E, - GPIO_FN_TS_SDEN0_B, - GPIO_FN_STP_ISEN_0_B, - - GPIO_IFN_SD1_CLK, - GPIO_FN_MSIOF1_SCK_G, - GPIO_FN_SIM0_CLK_A, - - GPIO_IFN_SD1_CMD, - GPIO_FN_MSIOF1_SYNC_G, - GPIO_FN_NFCEx_B, - GPIO_FN_SIM0_D_A, - GPIO_FN_STP_IVCXO27_1_B, - - GPIO_IFN_SD1_DAT0, - GPIO_FN_SD2_DAT4, - GPIO_FN_MSIOF1_RXD_G, - GPIO_FN_NFWPx_B, - GPIO_FN_TS_SCK1_B, - GPIO_FN_STP_ISCLK_1_B, - - GPIO_IFN_SD1_DAT1, - GPIO_FN_SD2_DAT5, - GPIO_FN_MSIOF1_TXD_G, - GPIO_FN_NFDATA14_B, - GPIO_FN_TS_SPSYNC1_B, - GPIO_FN_STP_ISSYNC_1_B, - - GPIO_IFN_SD1_DAT2, - GPIO_FN_SD2_DAT6, - GPIO_FN_MSIOF1_SS1_G, - GPIO_FN_NFDATA15_B, - GPIO_FN_TS_SDAT1_B, - GPIO_FN_STP_IOD_1_B, - - GPIO_IFN_SD1_DAT3, - GPIO_FN_SD2_DAT7, - GPIO_FN_MSIOF1_SS2_G, - GPIO_FN_NFRBx_B, - GPIO_FN_TS_SDEN1_B, - GPIO_FN_STP_ISEN_1_B, - - /* IPSR9 */ - GPIO_IFN_SD2_CLK, - GPIO_FN_NFDATA8, - - GPIO_IFN_SD2_CMD, - GPIO_FN_NFDATA9, - - GPIO_IFN_SD2_DAT0, - GPIO_FN_NFDATA10, - - GPIO_IFN_SD2_DAT1, - GPIO_FN_NFDATA11, - - GPIO_IFN_SD2_DAT2, - GPIO_FN_NFDATA12, - - GPIO_IFN_SD2_DAT3, - GPIO_FN_NFDATA13, - - GPIO_IFN_SD2_DS, - GPIO_FN_NFALE, - - GPIO_IFN_SD3_CLK, - GPIO_FN_NFWEx, - - /* IPSR10 */ - GPIO_IFN_SD3_CMD, - GPIO_FN_NFREx, - - GPIO_IFN_SD3_DAT0, - GPIO_FN_NFDATA0, - - GPIO_IFN_SD3_DAT1, - GPIO_FN_NFDATA1, - - GPIO_IFN_SD3_DAT2, - GPIO_FN_NFDATA2, - - GPIO_IFN_SD3_DAT3, - GPIO_FN_NFDATA3, - - GPIO_IFN_SD3_DAT4, - GPIO_FN_SD2_CD_A, - GPIO_FN_NFDATA4, - - GPIO_IFN_SD3_DAT5, - GPIO_FN_SD2_WP_A, - GPIO_FN_NFDATA5, - - GPIO_IFN_SD3_DAT6, - GPIO_FN_SD3_CD, - GPIO_FN_NFDATA6, - - /* IPSR11 */ - GPIO_IFN_SD3_DAT7, - GPIO_FN_SD3_WP, - GPIO_FN_NFDATA7, - - GPIO_IFN_SD3_DS, - GPIO_FN_NFCLE, - - GPIO_IFN_SD0_CD, - GPIO_FN_NFDATA14_A, - GPIO_FN_SCL2_B, - GPIO_FN_SIM0_RST_A, - - GPIO_IFN_SD0_WP, - GPIO_FN_NFDATA15_A, - GPIO_FN_SDA2_B, - - GPIO_IFN_SD1_CD, - GPIO_FN_NFRBx_A, - GPIO_FN_SIM0_CLK_B, - - GPIO_IFN_SD1_WP, - GPIO_FN_NFCEx_A, - GPIO_FN_SIM0_D_B, - - GPIO_IFN_SCK0, - GPIO_FN_HSCK1_B, - GPIO_FN_MSIOF1_SS2_B, - GPIO_FN_AUDIO_CLKC_B, - GPIO_FN_SDA2_A, - GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM_0_C, - GPIO_FN_RIF0_CLK_B, - GPIO_FN_ADICHS2, - GPIO_FN_SCK5_B, - - GPIO_IFN_RX0, - GPIO_FN_HRX1_B, - GPIO_FN_TS_SCK0_C, - GPIO_FN_STP_ISCLK_0_C, - GPIO_FN_RIF0_D0_B, - - /* IPSR12 */ - GPIO_IFN_TX0, - GPIO_FN_HTX1_B, - GPIO_FN_TS_SPSYNC0_C, - GPIO_FN_STP_ISSYNC_0_C, - GPIO_FN_RIF0_D1_B, - - GPIO_IFN_CTS0x, - GPIO_FN_HCTS1x_B, - GPIO_FN_MSIOF1_SYNC_B, - GPIO_FN_TS_SPSYNC1_C, - GPIO_FN_STP_ISSYNC_1_C, - GPIO_FN_RIF1_SYNC_B, - GPIO_FN_AUDIO_CLKOUT_C, - GPIO_FN_ADICS_SAMP, - - GPIO_IFN_RTS0x_TANS, - GPIO_FN_HRTS1x_B, - GPIO_FN_MSIOF1_SS1_B, - GPIO_FN_AUDIO_CLKA_B, - GPIO_FN_SCL2_A, - GPIO_FN_STP_IVCXO27_1_C, - GPIO_FN_RIF0_SYNC_B, - GPIO_FN_ADICHS1, - - GPIO_IFN_RX1_A, - GPIO_FN_HRX1_A, - GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_ISD_0_C, - GPIO_FN_RIF1_CLK_C, - - GPIO_IFN_TX1_A, - GPIO_FN_HTX1_A, - GPIO_FN_TS_SDEN0_C, - GPIO_FN_STP_ISEN_0_C, - GPIO_FN_RIF1_D0_C, - - GPIO_IFN_CTS1x, - GPIO_FN_HCTS1x_A, - GPIO_FN_MSIOF1_RXD_B, - GPIO_FN_TS_SDEN1_C, - GPIO_FN_STP_ISEN_1_C, - GPIO_FN_RIF1_D0_B, - GPIO_FN_ADIDATA, - - GPIO_IFN_RTS1x_TANS, - GPIO_FN_HRTS1x_A, - GPIO_FN_MSIOF1_TXD_B, - GPIO_FN_TS_SDAT1_C, - GPIO_FN_STP_ISD_1_C, - GPIO_FN_RIF1_D1_B, - GPIO_FN_ADICHS0, - - GPIO_IFN_SCK2, - GPIO_FN_SCIF_CLK_B, - GPIO_FN_MSIOF1_SCK_B, - GPIO_FN_TS_SCK1_C, - GPIO_FN_STP_ISCLK_1_C, - GPIO_FN_RIF1_CLK_B, - GPIO_FN_ADICLK, - - /* IPSR13 */ - GPIO_IFN_TX2_A, - GPIO_FN_SD2_CD_B, - GPIO_FN_SCL1_A, - GPIO_FN_FMCLK_A, - GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0_B, - - GPIO_IFN_RX2_A, - GPIO_FN_SD2_WP_B, - GPIO_FN_SDA1_A, - GPIO_FN_FMIN_A, - GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CEF_1_B, - - GPIO_IFN_HSCK0, - GPIO_FN_MSIOF1_SCK_D, - GPIO_FN_AUDIO_CLKB_A, - GPIO_FN_SSI_SDATA1_B, - GPIO_FN_TS_SCK0_D, - GPIO_FN_STP_ISCLK_0_D, - GPIO_FN_RIF0_CLK_C, - GPIO_FN_RX5_B, - - GPIO_IFN_HRX0, - GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SS1_SDATA2_B, - GPIO_FN_TS_SDEN0_D, - GPIO_FN_STP_ISEN_0_D, - GPIO_FN_RIF0_D0_C, - - GPIO_IFN_HTX0, - GPIO_FN_MSIOF1_TXD_D, - GPIO_FN_SSI_SDATA9_B, - GPIO_FN_TS_SDAT0_D, - GPIO_FN_STP_ISD_0_D, - GPIO_FN_RIF0_D1_C, - - GPIO_IFN_HCTS0x, - GPIO_FN_RX2_B, - GPIO_FN_MSIOF1_SYNC_D, - GPIO_FN_SSI_SCK9_A, - GPIO_FN_TS_SPSYNC0_D, - GPIO_FN_STP_ISSYNC_0_D, - GPIO_FN_RIF0_SYNC_C, - GPIO_FN_AUDIO_CLKOUT1_A, - - GPIO_IFN_HRTS0x, - GPIO_FN_TX2_B, - GPIO_FN_MSIOF1_SS1_D, - GPIO_FN_SSI_WS9_A, - GPIO_FN_STP_IVCXO27_0_D, - GPIO_FN_BPFCLK_A, - GPIO_FN_AUDIO_CLKOUT2_A, - - GPIO_IFN_MSIOF0_SYNC, - GPIO_FN_AUDIO_CLKOUT_A, - GPIO_FN_TX5_B, - GPIO_FN_BPFCLK_D, - - /* IPSR14 */ - GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5_A, - GPIO_FN_NFWPx_A, - GPIO_FN_AUDIO_CLKA_C, - GPIO_FN_SSI_SCK2_A, - GPIO_FN_STP_IVCXO27_0_C, - GPIO_FN_AUDIO_CLKOUT3_A, - GPIO_FN_TCLK1_B, - - GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5_A, - GPIO_FN_MSIOF1_SS2_D, - GPIO_FN_AUDIO_CLKC_A, - GPIO_FN_SSI_WS2_A, - GPIO_FN_STP_OPWM_0_D, - GPIO_FN_AUDIO_CLKOUT_D, - GPIO_FN_SPEEDIN_B, - - GPIO_IFN_MLB_CLK, - GPIO_FN_MSIOF1_SCK_F, - GPIO_FN_SCL1_B, - - GPIO_IFN_MLB_SIG, - GPIO_FN_RX1_B, - GPIO_FN_MSIOF1_SYNC_F, - GPIO_FN_SDA1_B, - - GPIO_IFN_MLB_DAT, - GPIO_FN_TX1_B, - GPIO_FN_MSIOF1_RXD_F, - - GPIO_IFN_SSI_SCK0129, - GPIO_FN_MSIOF1_TXD_F, - GPIO_FN_MOUT0, - - GPIO_IFN_SSI_WS0129, - GPIO_FN_MSIOF1_SS1_F, - GPIO_FN_MOUT1, - - GPIO_IFN_SSI_SDATA0, - GPIO_FN_MSIOF1_SS2_F, - GPIO_FN_MOUT2, - - /* IPSR15 */ - GPIO_IFN_SSI_SDATA1_A, - GPIO_FN_MOUT5, - - GPIO_IFN_SSI_SDATA2_A, - GPIO_FN_SSI_SCK1_B, - GPIO_FN_MOUT6, - - GPIO_IFN_SSI_SCK34, - GPIO_FN_MSIOF1_SS1_A, - GPIO_FN_STP_OPWM_0_A, - - GPIO_IFN_SSI_WS34, - GPIO_FN_HCTS2x_A, - GPIO_FN_MSIOF1_SS2_A, - GPIO_FN_STP_IVCXO27_0_A, - - GPIO_IFN_SSI_SDATA3, - GPIO_FN_HRTS2x_A, - GPIO_FN_MSIOF1_TXD_A, - GPIO_FN_TS_SCK0_A, - GPIO_FN_STP_ISCLK_0_A, - GPIO_FN_RIF0_D1_A, - GPIO_FN_RIF2_D0_A, - - GPIO_IFN_SSI_SCK4, - GPIO_FN_HRX2_A, - GPIO_FN_MSIOF1_SCK_A, - GPIO_FN_TS_SDAT0_A, - GPIO_FN_STP_ISD_0_A, - GPIO_FN_RIF0_CLK_A, - GPIO_FN_RIF2_CLK_A, - - GPIO_IFN_SSI_WS4, - GPIO_FN_HTX2_A, - GPIO_FN_MSIOF1_SYNC_A, - GPIO_FN_TS_SDEN0_A, - GPIO_FN_STP_ISEN_0_A, - GPIO_FN_RIF0_SYNC_A, - GPIO_FN_RIF2_SYNC_A, - - GPIO_IFN_SSI_SDATA4, - GPIO_FN_HSCK2_A, - GPIO_FN_MSIOF1_RXD_A, - GPIO_FN_TS_SPSYNC0_A, - GPIO_FN_STP_ISSYNC_0_A, - GPIO_FN_RIF0_D0_A, - GPIO_FN_RIF2_D1_A, - - /* IPSR16 */ - GPIO_IFN_SSI_SCK6, - GPIO_FN_SIM0_RST_D, - GPIO_FN_FSO_TOE_A, - - GPIO_IFN_SSI_WS6, - GPIO_FN_SIM0_D_D, - - GPIO_IFN_SSI_SDATA6, - GPIO_FN_SIM0_CLK_D, - - GPIO_IFN_SSI_SCK78, - GPIO_FN_HRX2_B, - GPIO_FN_MSIOF1_SCK_C, - GPIO_FN_TS_SCK1_A, - GPIO_FN_STP_ISCLK_1_A, - GPIO_FN_RIF1_CLK_A, - GPIO_FN_RIF3_CLK_A, - - GPIO_IFN_SSI_WS78, - GPIO_FN_HTX2_B, - GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDAT1_A, - GPIO_FN_STP_ISD_1_A, - GPIO_FN_RIF1_SYNC_A, - GPIO_FN_RIF3_SYNC_A, - - GPIO_IFN_SSI_SDATA7, - GPIO_FN_HCTS2x_B, - GPIO_FN_MSIOF1_RXD_C, - GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_IEN_1_A, - GPIO_FN_RIF1_D0_A, - GPIO_FN_RIF3_D0_A, - GPIO_FN_TCLK2_A, - - GPIO_IFN_SSI_SDATA8, - GPIO_FN_HRTS2x_B, - GPIO_FN_MSIOF1_TXD_C, - GPIO_FN_TS_SPSYNC1_A, - GPIO_FN_STP_ISSYNC_1_A, - GPIO_FN_RIF1_D1_A, - GPIO_FN_EIF3_D1_A, - - GPIO_IFN_SSI_SDATA9_A, - GPIO_FN_HSCK2_B, - GPIO_FN_MSIOF1_SS1_C, - GPIO_FN_HSCK1_A, - GPIO_FN_SSI_WS1_B, - GPIO_FN_SCK1, - GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5, - - /* IPSR17 */ - GPIO_IFN_AUDIO_CLKA_A, - GPIO_FN_CC5_OSCOUT, - - GPIO_IFN_AUDIO_CLKB_B, - GPIO_FN_SCIF_CLK_A, - GPIO_FN_STP_IVCXO27_1_D, - GPIO_FN_REMOCON_A, - GPIO_FN_TCLK1_A, - - GPIO_IFN_USB0_PWEN, - GPIO_FN_SIM0_RST_C, - GPIO_FN_TS_SCK1_D, - GPIO_FN_STP_ISCLK_1_D, - GPIO_FN_BPFCLK_B, - GPIO_FN_RIF3_CLK_B, - GPIO_FN_FSO_CFE_1_A, - GPIO_FN_HSCK2_C, - - GPIO_IFN_USB0_OVC, - GPIO_FN_SIM0_D_C, - GPIO_FN_TS_SDAT1_D, - GPIO_FN_STP_ISD_1_D, - GPIO_FN_RIF3_SYNC_B, - GPIO_FN_HRX2_C, - - GPIO_IFN_USB1_PWEN, - GPIO_FN_SIM0_CLK_C, - GPIO_FN_SSI_SCK1_A, - GPIO_FN_TS_SCK0_E, - GPIO_FN_STP_ISCLK_0_E, - GPIO_FN_FMCLK_B, - GPIO_FN_RIF2_CLK_B, - GPIO_FN_SPEEDIN_A, - GPIO_FN_HTX2_C, - - GPIO_IFN_USB1_OVC, - GPIO_FN_MSIOF1_SS2_C, - GPIO_FN_SSI_WS1_A, - GPIO_FN_TS_SDAT0_E, - GPIO_FN_STP_ISD_0_E, - GPIO_FN_FMIN_B, - GPIO_FN_RIF2_SYNC_B, - GPIO_FN_REMOCON_B, - GPIO_FN_HCTS2x_C, - - GPIO_IFN_USB30_PWEN, - GPIO_FN_AUDIO_CLKOUT_B, - GPIO_FN_SSI_SCK2_B, - GPIO_FN_TS_SDEN1_D, - GPIO_FN_STP_ISEN_1_D, - GPIO_FN_STP_OPWM_0_E, - GPIO_FN_RIF3_D0_B, - GPIO_FN_TCLK2_B, - GPIO_FN_TPU0TO0, - GPIO_FN_BPFCLK_C, - GPIO_FN_HRTS2x_C, - - GPIO_IFN_USB30_OVC, - GPIO_FN_AUDIO_CLKOUT1_B, - GPIO_FN_SSI_WS2_B, - GPIO_FN_TS_SPSYNC1_D, - GPIO_FN_STP_ISSYNC_1_D, - GPIO_FN_STP_IVCXO27_0_E, - GPIO_FN_RIF3_D1_B, - GPIO_FN_FSO_TOE_B, - GPIO_FN_TPU0TO1, - - /* IPSR18 */ - GPIO_IFN_GP6_30, - GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SSI_SCK9_B, - GPIO_FN_TS_SDEN0_E, - GPIO_FN_STP_ISEN_0_E, - GPIO_FN_RIF2_D0_B, - GPIO_FN_FSO_CFE_0_A, - GPIO_FN_TPU0TO2, - GPIO_FN_FMCLK_C, - GPIO_FN_FMCLK_D, - - GPIO_IFN_GP6_31, - GPIO_FN_AUDIO_CLKOUT3_B, - GPIO_FN_SSI_WS9_B, - GPIO_FN_TS_SPSYNC0_E, - GPIO_FN_STP_ISSYNC_0_E, - GPIO_FN_RIF2_D1_B, - GPIO_FN_TPU0TO3, - GPIO_FN_FMIN_C, - GPIO_FN_FMIN_D, - -}; - -#endif /* __ASM_R8A7796_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796.h b/arch/arm/mach-rmobile/include/mach/r8a7796.h deleted file mode 100644 index dab60820124..00000000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7796.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h - * This file defines registers and value for r8a7796. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_R8A7796_H -#define __ASM_ARCH_R8A7796_H - -#include "rcar-gen3-base.h" - -/* Module stop control/status register bits */ -#define MSTP0_BITS 0x00200000 -#define MSTP1_BITS 0xFFFFFFFF -#define MSTP2_BITS 0x340E2FDC -#define MSTP3_BITS 0xFFFFFFDF -#define MSTP4_BITS 0x80000184 -#define MSTP5_BITS 0xC3FFFFFF -#define MSTP6_BITS 0xFFFFFFFF -#define MSTP7_BITS 0xFFFFFFFF -#define MSTP8_BITS 0x01F1FFF7 -#define MSTP9_BITS 0xFFFFFFFE -#define MSTP10_BITS 0xFFFEFFE0 -#define MSTP11_BITS 0x000000B7 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 - -#endif /* __ASM_ARCH_R8A7796_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index 39726355e67..507859342c1 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -68,12 +68,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 - /* PFC */ #define PFC_PUEN5 0xE6060414 #define PUEN_SSI_SDATA4 BIT(17) diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 654349b0b3d..b413859a4d0 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -16,19 +16,29 @@ #include <asm/arch/r8a7793.h> #elif defined(CONFIG_R8A7794) #include <asm/arch/r8a7794.h> -#elif defined(CONFIG_R8A7795) -#include <asm/arch/r8a7795.h> -#elif defined(CONFIG_R8A7796) -#include <asm/arch/r8a7796.h> +#elif defined(CONFIG_RCAR_GEN3) +#include <asm/arch/rcar-gen3-base.h> #else #error "SOC Name not defined" #endif #endif /* CONFIG_ARCH_RMOBILE */ +/* PRR CPU IDs */ +#define RMOBILE_CPU_TYPE_SH73A0 0x37 +#define RMOBILE_CPU_TYPE_R8A7740 0x40 +#define RMOBILE_CPU_TYPE_R8A7790 0x45 +#define RMOBILE_CPU_TYPE_R8A7791 0x47 +#define RMOBILE_CPU_TYPE_R8A7792 0x4A +#define RMOBILE_CPU_TYPE_R8A7793 0x4B +#define RMOBILE_CPU_TYPE_R8A7794 0x4C +#define RMOBILE_CPU_TYPE_R8A7795 0x4F +#define RMOBILE_CPU_TYPE_R8A7796 0x52 + #ifndef __ASSEMBLY__ u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void); u32 rmobile_get_cpu_rev_fraction(void); +void rcar_gen3_memmap_fixup(void); #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c new file mode 100644 index 00000000000..f3156ab01a8 --- /dev/null +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -0,0 +1,66 @@ +/* + * Renesas RCar Gen3 memory map tables + * + * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region r8a7795_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +static struct mm_region r8a7796_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe0000000UL, + .phys = 0xe0000000UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = r8a7795_mem_map; + +void rcar_gen3_memmap_fixup(void) +{ + u32 cpu_type = rmobile_get_cpu_type(); + + switch (cpu_type) { + case RMOBILE_CPU_TYPE_R8A7795: + mem_map = r8a7795_mem_map; + break; + case RMOBILE_CPU_TYPE_R8A7796: + mem_map = r8a7796_mem_map; + break; + } +} diff --git a/arch/arm/mach-rmobile/memmap-r8a7795.c b/arch/arm/mach-rmobile/memmap-r8a7795.c deleted file mode 100644 index c2c5e48aaf7..00000000000 --- a/arch/arm/mach-rmobile/memmap-r8a7795.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region r8a7795_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = r8a7795_mem_map; diff --git a/arch/arm/mach-rmobile/memmap-r8a7796.c b/arch/arm/mach-rmobile/memmap-r8a7796.c deleted file mode 100644 index 648743d51e0..00000000000 --- a/arch/arm/mach-rmobile/memmap-r8a7796.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/armv8/mmu.h> - -static struct mm_region r8a7796_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe0000000UL, - .phys = 0xe0000000UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = r8a7796_mem_map; diff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c deleted file mode 100644 index 93aaf31ed96..00000000000 --- a/arch/arm/mach-rmobile/pfc-r8a7795.c +++ /dev/null @@ -1,5005 +0,0 @@ -/* - * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c - * This file is r8a7795 processor support - PFC hardware block. - * - * Copyright (C) 2015-2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <sh_pfc.h> -#include <asm/gpio.h> - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT_29(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT_28(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx) - -#define CPU_32_PORT_26(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx) - -#define CPU_32_PORT_18(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##17, sfx) - -#define CPU_32_PORT_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx) - -#define CPU_32_PORT_15(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx) - -#define CPU_32_PORT_4(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), \ - PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##3, sfx) - - -/* --gen3-- */ -/* GP_0_0_DATA -> GP_7_4_DATA */ -/* except for GP0[16] - [31], - GP1[28] - [31], - GP2[15] - [31], - GP3[16] - [31], - GP4[18] - [31], - GP5[26] - [31], - GP7[4] - [31] */ - -#define ES_CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_28(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_29(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - GP_ALL(IN), - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - - /* GPSR0 */ - GFN_D15, - GFN_D14, - GFN_D13, - GFN_D12, - GFN_D11, - GFN_D10, - GFN_D9, - GFN_D8, - GFN_D7, - GFN_D6, - GFN_D5, - GFN_D4, - GFN_D3, - GFN_D2, - GFN_D1, - GFN_D0, - - /* GPSR1 */ - GFN_CLKOUT, - GFN_EX_WAIT0_A, - GFN_WE1x, - GFN_WE0x, - GFN_RD_WRx, - GFN_RDx, - GFN_BSx, - GFN_CS1x_A26, - GFN_CS0x, - GFN_A19, - GFN_A18, - GFN_A17, - GFN_A16, - GFN_A15, - GFN_A14, - GFN_A13, - GFN_A12, - GFN_A11, - GFN_A10, - GFN_A9, - GFN_A8, - GFN_A7, - GFN_A6, - GFN_A5, - GFN_A4, - GFN_A3, - GFN_A2, - GFN_A1, - GFN_A0, - - /* GPSR2 */ - GFN_AVB_AVTP_CAPTURE_A, - GFN_AVB_AVTP_MATCH_A, - GFN_AVB_LINK, - GFN_AVB_PHY_INT, - GFN_AVB_MAGIC, - GFN_AVB_MDC, - GFN_PWM2_A, - GFN_PWM1_A, - GFN_PWM0, - GFN_IRQ5, - GFN_IRQ4, - GFN_IRQ3, - GFN_IRQ2, - GFN_IRQ1, - GFN_IRQ0, - - /* GPSR3 */ - GFN_SD1_WP, - GFN_SD1_CD, - GFN_SD0_WP, - GFN_SD0_CD, - GFN_SD1_DAT3, - GFN_SD1_DAT2, - GFN_SD1_DAT1, - GFN_SD1_DAT0, - GFN_SD1_CMD, - GFN_SD1_CLK, - GFN_SD0_DAT3, - GFN_SD0_DAT2, - GFN_SD0_DAT1, - GFN_SD0_DAT0, - GFN_SD0_CMD, - GFN_SD0_CLK, - - /* GPSR4 */ - GFN_SD3_DS, - GFN_SD3_DAT7, - GFN_SD3_DAT6, - GFN_SD3_DAT5, - GFN_SD3_DAT4, - GFN_SD3_DAT3, - GFN_SD3_DAT2, - GFN_SD3_DAT1, - GFN_SD3_DAT0, - GFN_SD3_CMD, - GFN_SD3_CLK, - GFN_SD2_DS, - GFN_SD2_DAT3, - GFN_SD2_DAT2, - GFN_SD2_DAT1, - GFN_SD2_DAT0, - GFN_SD2_CMD, - GFN_SD2_CLK, - - /* GPSR5 */ - GFN_MLB_DAT, - GFN_MLB_SIG, - GFN_MLB_CLK, - FN_MSIOF0_RXD, - GFN_MSIOF0_SS2, - FN_MSIOF0_TXD, - GFN_MSIOF0_SS1, - GFN_MSIOF0_SYNC, - FN_MSIOF0_SCK, - GFN_HRTS0x, - GFN_HCTS0x, - GFN_HTX0, - GFN_HRX0, - GFN_HSCK0, - GFN_RX2_A, - GFN_TX2_A, - GFN_SCK2, - GFN_RTS1x_TANS, - GFN_CTS1x, - GFN_TX1_A, - GFN_RX1_A, - GFN_RTS0x_TANS, - GFN_CTS0x, - GFN_TX0, - GFN_RX0, - GFN_SCK0, - - /* GPSR6 */ - GFN_USB3_OVC, - GFN_USB3_PWEN, - GFN_USB30_OVC, - GFN_USB30_PWEN, - GFN_USB1_OVC, - GFN_USB1_PWEN, - GFN_USB0_OVC, - GFN_USB0_PWEN, - GFN_AUDIO_CLKB_B, - GFN_AUDIO_CLKA_A, - GFN_SSI_SDATA9_A, - GFN_SSI_SDATA8, - GFN_SSI_SDATA7, - GFN_SSI_WS78, - GFN_SSI_SCK78, - GFN_SSI_SDATA6, - GFN_SSI_WS6, - GFN_SSI_SCK6, - FN_SSI_SDATA5, - FN_SSI_WS5, - FN_SSI_SCK5, - GFN_SSI_SDATA4, - GFN_SSI_WS4, - GFN_SSI_SCK4, - GFN_SSI_SDATA3, - GFN_SSI_WS34, - GFN_SSI_SCK34, - GFN_SSI_SDATA2_A, - GFN_SSI_SDATA1_A, - GFN_SSI_SDATA0, - GFN_SSI_WS01239, - GFN_SSI_SCK01239, - - /* GPSR7 */ - FN_HDMI1_CEC, - FN_HDMI0_CEC, - FN_AVS2, - FN_AVS1, - - /* IPSR0 */ - IFN_AVB_MDC, - FN_MSIOF2_SS2_C, - IFN_AVB_MAGIC, - FN_MSIOF2_SS1_C, - FN_SCK4_A, - IFN_AVB_PHY_INT, - FN_MSIOF2_SYNC_C, - FN_RX4_A, - IFN_AVB_LINK, - FN_MSIOF2_SCK_C, - FN_TX4_A, - IFN_AVB_AVTP_MATCH_A, - FN_MSIOF2_RXD_C, - FN_CTS4x_A, - FN_FSCLKST2x_A, - IFN_AVB_AVTP_CAPTURE_A, - FN_MSIOF2_TXD_C, - FN_RTS4x_TANS_A, - IFN_IRQ0, - FN_QPOLB, - FN_DU_CDE, - FN_VI4_DATA0_B, - FN_CAN0_TX_B, - FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - IFN_IRQ1, - FN_QPOLA, - FN_DU_DISP, - FN_VI4_DATA1_B, - FN_CAN0_RX_B, - FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - - /* IPSR1 */ - IFN_IRQ2, - FN_QCPV_QDE, - FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, - FN_MSIOF3_SYNC_E, - FN_PWM3_B, - IFN_IRQ3, - FN_QSTVB_QVE, - FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, - FN_MSIOF3_SCK_E, - FN_PWM4_B, - IFN_IRQ4, - FN_QSTH_QHS, - FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, - FN_MSIOF3_RXD_E, - FN_PWM5_B, - IFN_IRQ5, - FN_QSTB_QHE, - FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, - FN_FSCLKST2x_B, - FN_MSIOF3_TXD_E, - FN_PWM6_B, - IFN_PWM0, - FN_AVB_AVTP_PPS, - FN_VI4_DATA6_B, - FN_IECLK_B, - IFN_PWM1_A, - FN_HRX3_D, - FN_VI4_DATA7_B, - FN_IERX_B, - IFN_PWM2_A, - FN_HTX3_D, - FN_IETX_B, - IFN_A0, - FN_LCDOUT16, - FN_MSIOF3_SYNC_B, - FN_VI4_DATA8, - FN_DU_DB0, - FN_PWM3_A, - - /* IPSR2 */ - IFN_A1, - FN_LCDOUT17, - FN_MSIOF3_TXD_B, - FN_VI4_DATA9, - FN_DU_DB1, - FN_PWM4_A, - IFN_A2, - FN_LCDOUT18, - FN_MSIOF3_SCK_B, - FN_VI4_DATA10, - FN_DU_DB2, - FN_PWM5_A, - IFN_A3, - FN_LCDOUT19, - FN_MSIOF3_RXD_B, - FN_VI4_DATA11, - FN_DU_DB3, - FN_PWM6_A, - IFN_A4, - FN_LCDOUT20, - FN_MSIOF3_SS1_B, - FN_VI4_DATA12, - FN_VI5_DATA12, - FN_DU_DB4, - IFN_A5, - FN_LCDOUT21, - FN_MSIOF3_SS2_B, - FN_SCK4_B, - FN_VI4_DATA13, - FN_VI5_DATA13, - FN_DU_DB5, - IFN_A6, - FN_LCDOUT22, - FN_MSIOF2_SS1_A, - FN_RX4_B, - FN_VI4_DATA14, - FN_VI5_DATA14, - FN_DU_DB6, - IFN_A7, - FN_LCDOUT23, - FN_MSIOF2_SS2_A, - FN_TX4_B, - FN_VI4_DATA15, - FN_V15_DATA15, - FN_DU_DB7, - IFN_A8, - FN_RX3_B, - FN_MSIOF2_SYNC_A, - FN_HRX4_B, - FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, - FN_PWM1_B, - - /* IPSR3 */ - IFN_A9, - FN_MSIOF2_SCK_A, - FN_CTS4x_B, - FN_VI5_VSYNCx, - IFN_A10, - FN_MSIOF2_RXD_A, - FN_RTS4n_TANS_B, - FN_VI5_HSYNCx, - IFN_A11, - FN_TX3_B, - FN_MSIOF2_TXD_A, - FN_HTX4_B, - FN_HSCK4, - FN_VI5_FIELD, - FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, - FN_PWM2_B, - IFN_A12, - FN_LCDOUT12, - FN_MSIOF3_SCK_C, - FN_HRX4_A, - FN_VI5_DATA8, - FN_DU_DG4, - IFN_A13, - FN_LCDOUT13, - FN_MSIOF3_SYNC_C, - FN_HTX4_A, - FN_VI5_DATA9, - FN_DU_DG5, - IFN_A14, - FN_LCDOUT14, - FN_MSIOF3_RXD_C, - FN_HCTS4x, - FN_VI5_DATA10, - FN_DU_DG6, - IFN_A15, - FN_LCDOUT15, - FN_MSIOF3_TXD_C, - FN_HRTS4x, - FN_VI5_DATA11, - FN_DU_DG7, - IFN_A16, - FN_LCDOUT8, - FN_VI4_FIELD, - FN_DU_DG0, - - /* IPSR4 */ - IFN_A17, - FN_LCDOUT9, - FN_VI4_VSYNCx, - FN_DU_DG1, - IFN_A18, - FN_LCDOUT10, - FN_VI4_HSYNCx, - FN_DU_DG2, - IFN_A19, - FN_LCDOUT11, - FN_VI4_CLKENB, - FN_DU_DG3, - IFN_CS0x, - FN_VI5_CLKENB, - IFN_CS1x_A26, - FN_VI5_CLK, - FN_EX_WAIT0_B, - IFN_BSx, - FN_QSTVA_QVS, - FN_MSIOF3_SCK_D, - FN_SCK3, - FN_HSCK3, - FN_CAN1_TX, - FN_CANFD1_TX, - FN_IETX_A, - IFN_RDx, - FN_MSIOF3_SYNC_D, - FN_RX3_A, - FN_HRX3_A, - FN_CAN0_TX_A, - FN_CANFD0_TX_A, - IFN_RD_WRx, - FN_MSIOF3_RXD_D, - FN_TX3_A, - FN_HTX3_A, - FN_CAN0_RX_A, - FN_CANFD0_RX_A, - - /* IPSR5 */ - IFN_WE0x, - FN_MSIIOF3_TXD_D, - FN_CTS3x, - FN_HCTS3x, - FN_SCL6_B, - FN_CAN_CLK, - FN_IECLK_A, - IFN_WE1x, - FN_MSIOF3_SS1_D, - FN_RTS3x_TANS, - FN_HRTS3x, - FN_SDA6_B, - FN_CAN1_RX, - FN_CANFD1_RX, - FN_IERX_A, - IFN_EX_WAIT0_A, - FN_QCLK, - FN_VI4_CLK, - FN_DU_DOTCLKOUT0, - IFN_D0, - FN_MSIOF2_SS1_B, - FN_MSIOF3_SCK_A, - FN_VI4_DATA16, - FN_VI5_DATA0, - IFN_D1, - FN_MSIOF2_SS2_B, - FN_MSIOF3_SYNC_A, - FN_VI4_DATA17, - FN_VI5_DATA1, - IFN_D2, - FN_MSIOF3_RXD_A, - FN_VI4_DATA18, - FN_VI5_DATA2, - IFN_D3, - FN_MSIOF3_TXD_A, - FN_VI4_DATA19, - FN_VI5_DATA3, - IFN_D4, - FN_MSIOF2_SCK_B, - FN_VI4_DATA20, - FN_VI5_DATA4, - - /* IPSR6 */ - IFN_D5, - FN_MSIOF2_SYNC_B, - FN_VI4_DATA21, - FN_VI5_DATA5, - IFN_D6, - FN_MSIOF2_RXD_B, - FN_VI4_DATA22, - FN_VI5_DATA6, - IFN_D7, - FN_MSIOF2_TXD_B, - FN_VI4_DATA23, - FN_VI5_DATA7, - IFN_D8, - FN_LCDOUT0, - FN_MSIOF2_SCK_D, - FN_SCK4_C, - FN_VI4_DATA0_A, - FN_DU_DR0, - IFN_D9, - FN_LCDOUT1, - FN_MSIOF2_SYNC_D, - FN_VI4_DATA1_A, - FN_DU_DR1, - IFN_D10, - FN_LCDOUT2, - FN_MSIOF2_RXD_D, - FN_HRX3_B, - FN_VI4_DATA2_A, - FN_CTS4x_C, - FN_DU_DR2, - IFN_D11, - FN_LCDOUT3, - FN_MSIOF2_TXD_D, - FN_HTX3_B, - FN_VI4_DATA3_A, - FN_RTS4x_TANS_C, - FN_DU_DR3, - IFN_D12, - FN_LCDOUT4, - FN_MSIOF2_SS1_D, - FN_RX4_C, - FN_VI4_DATA4_A, - FN_DU_DR4, - - /* IPSR7 */ - IFN_D13, - FN_LCDOUT5, - FN_MSIOF2_SS2_D, - FN_TX4_C, - FN_VI4_DATA5_A, - FN_DU_DR5, - IFN_D14, - FN_LCDOUT6, - FN_MSIOF3_SS1_A, - FN_HRX3_C, - FN_VI4_DATA6_A, - FN_DU_DR6, - FN_SCL6_C, - IFN_D15, - FN_LCDOUT7, - FN_MSIOF3_SS2_A, - FN_HTX3_C, - FN_VI4_DATA7_A, - FN_DU_DR7, - FN_SDA6_C, - FN_FSCLKST, - IFN_SD0_CLK, - FN_MSIOF1_SCK_E, - FN_STP_OPWM_0_B, - IFN_SD0_CMD, - FN_MSIOF1_SYNC_E, - FN_STP_IVCXO27_0_B, - IFN_SD0_DAT0, - FN_MSIOF1_RXD_E, - FN_TS_SCK0_B, - FN_STP_ISCLK_0_B, - IFN_SD0_DAT1, - FN_MSIOF1_TXD_E, - FN_TS_SPSYNC0_B, - FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - IFN_SD0_DAT2, - FN_MSIOF1_SS1_E, - FN_TS_SDAT0_B, - FN_STP_ISD_0_B, - IFN_SD0_DAT3, - FN_MSIOF1_SS2_E, - FN_TS_SDEN0_B, - FN_STP_ISEN_0_B, - IFN_SD1_CLK, - FN_MSIOF1_SCK_G, - FN_SIM0_CLK_A, - IFN_SD1_CMD, - FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - FN_SIM0_D_A, - FN_STP_IVCXO27_1_B, - IFN_SD1_DAT0, - FN_SD2_DAT4, - FN_MSIOF1_RXD_G, - FN_NFWPx_B, - FN_TS_SCK1_B, - FN_STP_ISCLK_1_B, - IFN_SD1_DAT1, - FN_SD2_DAT5, - FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - FN_TS_SPSYNC1_B, - FN_STP_ISSYNC_1_B, - IFN_SD1_DAT2, - FN_SD2_DAT6, - FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - FN_TS_SDAT1_B, - FN_STP_IOD_1_B, - IFN_SD1_DAT3, - FN_SD2_DAT7, - FN_MSIOF1_SS2_G, - FN_NFRBx_B, - FN_TS_SDEN1_B, - FN_STP_ISEN_1_B, - - /* IPSR9 */ - IFN_SD2_CLK, - FN_NFDATA8, - IFN_SD2_CMD, - FN_NFDATA9, - IFN_SD2_DAT0, - FN_NFDATA10, - IFN_SD2_DAT1, - FN_NFDATA11, - IFN_SD2_DAT2, - FN_NFDATA12, - IFN_SD2_DAT3, - FN_NFDATA13, - IFN_SD2_DS, - FN_NFALE, - FN_SATA_DEVSLP_B, - IFN_SD3_CLK, - FN_NFWEx, - - /* IPSR10 */ - IFN_SD3_CMD, - FN_NFREx, - IFN_SD3_DAT0, - FN_NFDATA0, - IFN_SD3_DAT1, - FN_NFDATA1, - IFN_SD3_DAT2, - FN_NFDATA2, - IFN_SD3_DAT3, - FN_NFDATA3, - IFN_SD3_DAT4, - FN_SD2_CD_A, - FN_NFDATA4, - IFN_SD3_DAT5, - FN_SD2_WP_A, - FN_NFDATA5, - IFN_SD3_DAT6, - FN_SD3_CD, - FN_NFDATA6, - - /* IPSR11 */ - IFN_SD3_DAT7, - FN_SD3_WP, - FN_NFDATA7, - IFN_SD3_DS, - FN_NFCLE, - IFN_SD0_CD, - FN_NFDATA14_A, - FN_SCL2_B, - FN_SIM0_RST_A, - IFN_SD0_WP, - FN_NFDATA15_A, - FN_SDA2_B, - IFN_SD1_CD, - FN_NFRBx_A, - FN_SIM0_CLK_B, - IFN_SD1_WP, - FN_NFCEx_A, - FN_SIM0_D_B, - IFN_SCK0, - FN_HSCK1_B, - FN_MSIOF1_SS2_B, - FN_AUDIO_CLKC_B, - FN_SDA2_A, - FN_SIM0_RST_B, - FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - FN_ADICHS2, - FN_SCK5_B, - IFN_RX0, - FN_HRX1_B, - FN_TS_SCK0_C, - FN_STP_ISCLK_0_C, - FN_RIF0_D0_B, - - /* IPSR12 */ - IFN_TX0, - FN_HTX1_B, - FN_TS_SPSYNC0_C, - FN_STP_ISSYNC_0_C, - FN_RIF0_D1_B, - IFN_CTS0x, - FN_HCTS1x_B, - FN_MSIOF1_SYNC_B, - FN_TS_SPSYNC1_C, - FN_STP_ISSYNC_1_C, - FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, - FN_ADICS_SAMP, - IFN_RTS0x_TANS, - FN_HRTS1x_B, - FN_MSIOF1_SS1_B, - FN_AUDIO_CLKA_B, - FN_SCL2_A, - FN_STP_IVCXO27_1_C, - FN_RIF0_SYNC_B, - FN_ADICHS1, - IFN_RX1_A, - FN_HRX1_A, - FN_TS_SDAT0_C, - FN_STP_ISD_0_C, - FN_RIF1_CLK_C, - IFN_TX1_A, - FN_HTX1_A, - FN_TS_SDEN0_C, - FN_STP_ISEN_0_C, - FN_RIF1_D0_C, - IFN_CTS1x, - FN_HCTS1x_A, - FN_MSIOF1_RXD_B, - FN_TS_SDEN1_C, - FN_STP_ISEN_1_C, - FN_RIF1_D0_B, - FN_ADIDATA, - IFN_RTS1x_TANS, - FN_HRTS1x_A, - FN_MSIOF1_TXD_B, - FN_TS_SDAT1_C, - FN_STP_ISD_1_C, - FN_RIF1_D1_B, - FN_ADICHS0, - IFN_SCK2, - FN_SCIF_CLK_B, - FN_MSIOF1_SCK_B, - FN_TS_SCK1_C, - FN_STP_ISCLK_1_C, - FN_RIF1_CLK_B, - FN_ADICLK, - - /* IPSR13 */ - IFN_TX2_A, - FN_SD2_CD_B, - FN_SCL1_A, - FN_FMCLK_A, - FN_RIF1_D1_C, - FN_FSO_CFE_0x, - IFN_RX2_A, - FN_SD2_WP_B, - FN_SDA1_A, - FN_FMIN_A, - FN_RIF1_SYNC_C, - FN_FSO_CFE_1x, - IFN_HSCK0, - FN_MSIOF1_SCK_D, - FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, - FN_TS_SCK0_D, - FN_STP_ISCLK_0_D, - FN_RIF0_CLK_C, - FN_RX5_B, - IFN_HRX0, - FN_MSIOF1_RXD_D, - FN_SSI_SDATA2_B, - FN_TS_SDEN0_D, - FN_STP_ISEN_0_D, - FN_RIF0_D0_C, - IFN_HTX0, - FN_MSIOF1_TXD_D, - FN_SSI_SDATA9_B, - FN_TS_SDAT0_D, - FN_STP_ISD_0_D, - FN_RIF0_D1_C, - IFN_HCTS0x, - FN_RX2_B, - FN_MSIOF1_SYNC_D, - FN_SSI_SCK9_A, - FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, - IFN_HRTS0x, - FN_TX2_B, - FN_MSIOF1_SS1_D, - FN_SSI_WS9_A, - FN_STP_IVCXO27_0_D, - FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, - IFN_MSIOF0_SYNC, - FN_AUDIO_CLKOUT_A, - FN_TX5_B, - FN_BPFCLK_D, - - /* IPSR14 */ - IFN_MSIOF0_SS1, - FN_RX5_A, - FN_NFWPx_A, - FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, - FN_STP_IVCXO27_0_C, - FN_AUDIO_CLKOUT3_A, - FN_TCLK1_B, - IFN_MSIOF0_SS2, - FN_TX5_A, - FN_MSIOF1_SS2_D, - FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, - FN_STP_OPWM_0_D, - FN_AUDIO_CLKOUT_D, - FN_SPEEDIN_B, - IFN_MLB_CLK, - FN_MSIOF1_SCK_F, - FN_SCL1_B, - IFN_MLB_SIG, - FN_RX1_B, - FN_MSIOF1_SYNC_F, - FN_SDA1_B, - IFN_MLB_DAT, - FN_TX1_B, - FN_MSIOF1_RXD_F, - IFN_SSI_SCK01239, - FN_MSIOF1_TXD_F, - FN_MOUT0, - IFN_SSI_WS01239, - FN_MSIOF1_SS1_F, - FN_MOUT1, - IFN_SSI_SDATA0, - FN_MSIOF1_SS2_F, - FN_MOUT2, - - /* IPSR15 */ - IFN_SSI_SDATA1_A, - FN_MOUT5, - IFN_SSI_SDATA2_A, - FN_SSI_SCK1_B, - FN_MOUT6, - IFN_SSI_SCK34, - FN_MSIOF1_SS1_A, - FN_STP_OPWM_0_A, - IFN_SSI_WS34, - FN_HCTS2x_A, - FN_MSIOF1_SS2_A, - FN_STP_IVCXO27_0_A, - IFN_SSI_SDATA3, - FN_HRTS2x_A, - FN_MSIOF1_TXD_A, - FN_TS_SCK0_A, - FN_STP_ISCLK_0_A, - FN_RIF0_D1_A, - FN_RIF2_D0_A, - IFN_SSI_SCK4, - FN_HRX2_A, - FN_MSIOF1_SCK_A, - FN_TS_SDAT0_A, - FN_STP_ISD_0_A, - FN_RIF0_CLK_A, - FN_RIF2_CLK_A, - IFN_SSI_WS4, - FN_HTX2_A, - FN_MSIOF1_SYNC_A, - FN_TS_SDEN0_A, - FN_STP_ISEN_0_A, - FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, - IFN_SSI_SDATA4, - FN_HSCK2_A, - FN_MSIOF1_RXD_A, - FN_TS_SPSYNC0_A, - FN_STP_ISSYNC_0_A, - FN_RIF0_D0_A, - FN_RIF2_D1_A, - - /* IPSR16 */ - IFN_SSI_SCK6, - FN_SIM0_RST_D, - IFN_SSI_WS6, - FN_SIM0_D_D, - IFN_SSI_SDATA6, - FN_SIM0_CLK_D, - FN_SATA_DEVSLP_A, - IFN_SSI_SCK78, - FN_HRX2_B, - FN_MSIOF1_SCK_C, - FN_TS_SCK1_A, - FN_STP_ISCLK_1_A, - FN_RIF1_CLK_A, - FN_RIF3_CLK_A, - IFN_SSI_WS78, - FN_HTX2_B, - FN_MSIOF1_SYNC_C, - FN_TS_SDAT1_A, - FN_STP_ISD_1_A, - FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, - IFN_SSI_SDATA7, - FN_HCTS2x_B, - FN_MSIOF1_RXD_C, - FN_TS_SDEN1_A, - FN_STP_ISEN_1_A, - FN_RIF1_D0_A, - FN_RIF3_D0_A, - FN_TCLK2_A, - IFN_SSI_SDATA8, - FN_HRTS2x_B, - FN_MSIOF1_TXD_C, - FN_TS_SPSYNC1_A, - FN_STP_ISSYNC_1_A, - FN_RIF1_D1_A, - FN_RIF3_D1_A, - IFN_SSI_SDATA9_A, - FN_HSCK2_B, - FN_MSIOF1_SS1_C, - FN_HSCK1_A, - FN_SSI_WS1_B, - FN_SCK1, - FN_STP_IVCXO27_1_A, - FN_SCK5_A, - - /* IPSR17 */ - IFN_AUDIO_CLKA_A, - FN_CC5_OSCOUT, - IFN_AUDIO_CLKB_B, - FN_SCIF_CLK_A, - FN_STP_IVCXO27_1_D, - FN_REMOCON_A, - FN_TCLK1_A, - IFN_USB0_PWEN, - FN_SIM0_RST_C, - FN_TS_SCK1_D, - FN_STP_ISCLK_1_D, - FN_BPFCLK_B, - FN_RIF3_CLK_B, - FN_HSCK2_C, - IFN_USB0_OVC, - FN_SIM0_D_C, - FN_TS_SDAT1_D, - FN_STP_ISD_1_D, - FN_RIF3_SYNC_B, - FN_HRX2_C, - IFN_USB1_PWEN, - FN_SIM0_CLK_C, - FN_SSI_SCK1_A, - FN_TS_SCK0_E, - FN_STP_ISCLK_0_E, - FN_FMCLK_B, - FN_RIF2_CLK_B, - FN_SPEEDIN_A, - FN_HTX2_C, - IFN_USB1_OVC, - FN_MSIOF1_SS2_C, - FN_SSI_WS1_A, - FN_TS_SDAT0_E, - FN_STP_ISD_0_E, - FN_FMIN_B, - FN_RIF2_SYNC_B, - FN_REMOCON_B, - FN_HCTS2x_C, - IFN_USB30_PWEN, - FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, - FN_TS_SDEN1_D, - FN_STP_ISEN_1_D, - FN_STP_OPWM_0_E, - FN_RIF3_D0_B, - FN_TCLK2_B, - FN_TPU0TO0, - FN_BPFCLK_C, - FN_HRTS2x_C, - IFN_USB30_OVC, - FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, - FN_TS_SPSYNC1_D, - FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, - FN_FSO_TOEx, - FN_TPU0TO1, - - /* IPSR18 */ - IFN_USB3_PWEN, - FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, - FN_TS_SDEN0_E, - FN_STP_ISEN_0_E, - FN_RIF2_D0_B, - FN_TPU0TO2, - FN_FMCLK_C, - FN_FMCLK_D, - IFN_USB3_OVC, - FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, - FN_TS_SPSYNC0_E, - FN_STP_ISSYNC_0_E, - FN_RIF2_D1_B, - FN_TPU0TO3, - FN_FMIN_C, - FN_FMIN_D, - - /* MOD_SEL0 */ - /* sel_msiof3[3](0,1,2,3,4) */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, - /* sel_msiof2[2](0,1,2,3) */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* sel_msiof1[3](0,1,2,3,4,5,6) */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, - /* sel_lbsc[1](0,1) */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* sel_iebus[1](0,1) */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* sel_i2c2[1](0,1) */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* sel_i2c1[1](0,1) */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* sel_hscif4[1](0,1) */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* sel_hscif3[2](0,1,2,3) */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* sel_hscif1[1](0,1) */ - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* reserved[1] */ - /* sel_hscif2[2](0,1,2) */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, - /* sel_etheravb[1](0,1) */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* sel_drif3[1](0,1) */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* sel_drif2[1](0,1) */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* sel_drif1[2](0,1,2) */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, - /* sel_drif0[2](0,1,2) */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, - /* sel_canfd0[1](0,1) */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* sel_adg_a[2](0,1,2) */ - FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, - FN_SEL_ADG_A_2, - /* reserved[3]*/ - - /* MOD_SEL1 */ - /* sel_tsif1[2](0,1,2,3) */ - FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, - /* sel_tsif0[3](0,1,2,3,4) */ - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - /* sel_timer_tmu1[1](0,1) */ - FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, - /* sel_ssp1_1[2](0,1,2,3) */ - FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, - /* sel_ssp1_0[3](0,1,2,3,4) */ - FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - /* sel_ssi1[1](0,1) */ - FN_SEL_SSI_0, FN_SEL_SSI_1, - /* sel_speed_pulse_if[1](0,1) */ - FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, - /* sel_simcard[2](0,1,2,3) */ - FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, - /* sel_sdhi2[1](0,1) */ - FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, - /* sel_scif4[2](0,1,2) */ - FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - /* sel_scif3[1](0,1) */ - FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, - /* sel_scif2[1](0,1) */ - FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, - /* sel_scif1[1](0,1) */ - FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, - /* sel_scif[1](0,1) */ - FN_SEL_SCIF_0, FN_SEL_SCIF_1, - /* sel_remocon[1](0,1) */ - FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, - /* reserved[8..7] */ - /* sel_rcan0[1](0,1) */ - FN_SEL_RCAN_0, FN_SEL_RCAN_1, - /* sel_pwm6[1](0,1) */ - FN_SEL_PWM6_0, FN_SEL_PWM6_1, - /* sel_pwm5[1](0,1) */ - FN_SEL_PWM5_0, FN_SEL_PWM5_1, - /* sel_pwm4[1](0,1) */ - FN_SEL_PWM4_0, FN_SEL_PWM4_1, - /* sel_pwm3[1](0,1) */ - FN_SEL_PWM3_0, FN_SEL_PWM3_1, - /* sel_pwm2[1](0,1) */ - FN_SEL_PWM2_0, FN_SEL_PWM2_1, - /* sel_pwm1[1](0,1) */ - FN_SEL_PWM1_0, FN_SEL_PWM1_1, - - /* MOD_SEL2 */ - /* i2c_sel_5[1](0,1) */ - FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, - /* i2c_sel_3[1](0,1) */ - FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, - /* i2c_sel_0[1](0,1) */ - FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, - /* sel_fm[2](0,1,2,3) */ - FN_SEL_FM_0, FN_SEL_FM_1, - FN_SEL_FM_2, FN_SEL_FM_3, - /* sel_scif5[1](0,1) */ - FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* sel_i2c6[3](0,1,2) */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - /* sel_ndfc[1](0,1) */ - FN_SEL_NDFC_0, FN_SEL_NDFC_1, - /* sel_ssi2[1](0,1) */ - FN_SEL_SSI2_0, FN_SEL_SSI2_1, - /* sel_ssi9[1](0,1) */ - FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* sel_timer_tmu2[1](0,1) */ - FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, - /* sel_adg_b[1](0,1) */ - FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, - /* sel_adg_c[1](0,1) */ - FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, - /* reserved[16..16] */ - /* reserved[15..8] */ - /* reserved[7..1] */ - /* sel_vin4[1](0,1) */ - FN_SEL_VIN4_0, FN_SEL_VIN4_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* GPSR0 */ - D15_GMARK, - D14_GMARK, - D13_GMARK, - D12_GMARK, - D11_GMARK, - D10_GMARK, - D9_GMARK, - D8_GMARK, - D7_GMARK, - D6_GMARK, - D5_GMARK, - D4_GMARK, - D3_GMARK, - D2_GMARK, - D1_GMARK, - D0_GMARK, - - /* GPSR1 */ - CLKOUT_GMARK, - EX_WAIT0_A_GMARK, - WE1x_GMARK, - WE0x_GMARK, - RD_WRx_GMARK, - RDx_GMARK, - BSx_GMARK, - CS1x_A26_GMARK, - CS0x_GMARK, - A19_GMARK, - A18_GMARK, - A17_GMARK, - A16_GMARK, - A15_GMARK, - A14_GMARK, - A13_GMARK, - A12_GMARK, - A11_GMARK, - A10_GMARK, - A9_GMARK, - A8_GMARK, - A7_GMARK, - A6_GMARK, - A5_GMARK, - A4_GMARK, - A3_GMARK, - A2_GMARK, - A1_GMARK, - A0_GMARK, - - /* GPSR2 */ - AVB_AVTP_CAPTURE_A_GMARK, - AVB_AVTP_MATCH_A_GMARK, - AVB_LINK_GMARK, - AVB_PHY_INT_GMARK, - AVB_MAGIC_GMARK, - AVB_MDC_GMARK, - PWM2_A_GMARK, - PWM1_A_GMARK, - PWM0_GMARK, - IRQ5_GMARK, - IRQ4_GMARK, - IRQ3_GMARK, - IRQ2_GMARK, - IRQ1_GMARK, - IRQ0_GMARK, - - /* GPSR3 */ - SD1_WP_GMARK, - SD1_CD_GMARK, - SD0_WP_GMARK, - SD0_CD_GMARK, - SD1_DAT3_GMARK, - SD1_DAT2_GMARK, - SD1_DAT1_GMARK, - SD1_DAT0_GMARK, - SD1_CMD_GMARK, - SD1_CLK_GMARK, - SD0_DAT3_GMARK, - SD0_DAT2_GMARK, - SD0_DAT1_GMARK, - SD0_DAT0_GMARK, - SD0_CMD_GMARK, - SD0_CLK_GMARK, - - /* GPSR4 */ - SD3_DS_GMARK, - SD3_DAT7_GMARK, - SD3_DAT6_GMARK, - SD3_DAT5_GMARK, - SD3_DAT4_GMARK, - SD3_DAT3_GMARK, - SD3_DAT2_GMARK, - SD3_DAT1_GMARK, - SD3_DAT0_GMARK, - SD3_CMD_GMARK, - SD3_CLK_GMARK, - SD2_DS_GMARK, - SD2_DAT3_GMARK, - SD2_DAT2_GMARK, - SD2_DAT1_GMARK, - SD2_DAT0_GMARK, - SD2_CMD_GMARK, - SD2_CLK_GMARK, - - /* GPSR5 */ - MLB_DAT_GMARK, - MLB_SIG_GMARK, - MLB_CLK_GMARK, - MSIOF0_RXD_MARK, - MSIOF0_SS2_GMARK, - MSIOF0_TXD_MARK, - MSIOF0_SS1_GMARK, - MSIOF0_SYNC_GMARK, - MSIOF0_SCK_MARK, - HRTS0x_GMARK, - HCTS0x_GMARK, - HTX0_GMARK, - HRX0_GMARK, - HSCK0_GMARK, - RX2_A_GMARK, - TX2_A_GMARK, - SCK2_GMARK, - RTS1x_TANS_GMARK, - CTS1x_GMARK, - TX1_A_GMARK, - RX1_A_GMARK, - RTS0x_TANS_GMARK, - CTS0x_GMARK, - TX0_GMARK, - RX0_GMARK, - SCK0_GMARK, - - /* GPSR6 */ - USB3_OVC_GMARK, - USB3_PWEN_GMARK, - USB30_OVC_GMARK, - USB30_PWEN_GMARK, - USB1_OVC_GMARK, - USB1_PWEN_GMARK, - USB0_OVC_GMARK, - USB0_PWEN_GMARK, - AUDIO_CLKB_B_GMARK, - AUDIO_CLKA_A_GMARK, - SSI_SDATA9_A_GMARK, - SSI_SDATA8_GMARK, - SSI_SDATA7_GMARK, - SSI_WS78_GMARK, - SSI_SCK78_GMARK, - SSI_SDATA6_GMARK, - SSI_WS6_GMARK, - SSI_SCK6_GMARK, - SSI_SDATA5_MARK, - SSI_WS5_MARK, - SSI_SCK5_MARK, - SSI_SDATA4_GMARK, - SSI_WS4_GMARK, - SSI_SCK4_GMARK, - SSI_SDATA3_GMARK, - SSI_WS34_GMARK, - SSI_SCK34_GMARK, - SSI_SDATA2_A_GMARK, - SSI_SDATA1_A_GMARK, - SSI_SDATA0_GMARK, - SSI_WS01239_GMARK, - SSI_SCK01239_GMARK, - - /* GPSR7 */ - HDMI1_CEC_MARK, - HDMI0_CEC_MARK, - AVS2_MARK, - AVS1_MARK, - - /* IPSR0 */ - AVB_MDC_IMARK, - MSIOF2_SS2_C_MARK, - AVB_MAGIC_IMARK, - MSIOF2_SS1_C_MARK, - SCK4_A_MARK, - AVB_PHY_INT_IMARK, - MSIOF2_SYNC_C_MARK, - RX4_A_MARK, - AVB_LINK_IMARK, - MSIOF2_SCK_C_MARK, - TX4_A_MARK, - AVB_AVTP_MATCH_A_IMARK, - MSIOF2_RXD_C_MARK, - CTS4x_A_MARK, - FSCLKST2x_A_MARK, - AVB_AVTP_CAPTURE_A_IMARK, - MSIOF2_TXD_C_MARK, - RTS4x_TANS_A_MARK, - IRQ0_IMARK, - QPOLB_MARK, - DU_CDE_MARK, - VI4_DATA0_B_MARK, - CAN0_TX_B_MARK, - CANFD0_TX_B_MARK, - MSIOF3_SS2_E_MARK, - IRQ1_IMARK, - QPOLA_MARK, - DU_DISP_MARK, - VI4_DATA1_B_MARK, - CAN0_RX_B_MARK, - CANFD0_RX_B_MARK, - MSIOF3_SS1_E_MARK, - - /* IPSR1 */ - IRQ2_IMARK, - QCPV_QDE_MARK, - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, - VI4_DATA2_B_MARK, - MSIOF3_SYNC_E_MARK, - PWM3_B_MARK, - IRQ3_IMARK, - QSTVB_QVE_MARK, - DU_DOTCLKOUT1_MARK, - VI4_DATA3_B_MARK, - MSIOF3_SCK_E_MARK, - PWM4_B_MARK, - IRQ4_IMARK, - QSTH_QHS_MARK, - DU_EXHSYNC_DU_HSYNC_MARK, - VI4_DATA4_B_MARK, - MSIOF3_RXD_E_MARK, - PWM5_B_MARK, - IRQ5_IMARK, - QSTB_QHE_MARK, - DU_EXVSYNC_DU_VSYNC_MARK, - VI4_DATA5_B_MARK, - FSCLKST2x_B_MARK, - MSIOF3_TXD_E_MARK, - PWM6_B_MARK, - PWM0_IMARK, - AVB_AVTP_PPS_MARK, - VI4_DATA6_B_MARK, - IECLK_B_MARK, - PWM1_A_IMARK, - HRX3_D_MARK, - VI4_DATA7_B_MARK, - IERX_B_MARK, - PWM2_A_IMARK, - PWMFSW0_MARK, - HTX3_D_MARK, - IETX_B_MARK, - A0_IMARK, - LCDOUT16_MARK, - MSIOF3_SYNC_B_MARK, - VI4_DATA8_MARK, - DU_DB0_MARK, - PWM3_A_MARK, - - /* IPSR2 */ - A1_IMARK, - LCDOUT17_MARK, - MSIOF3_TXD_B_MARK, - VI4_DATA9_MARK, - DU_DB1_MARK, - PWM4_A_MARK, - A2_IMARK, - LCDOUT18_MARK, - MSIOF3_SCK_B_MARK, - VI4_DATA10_MARK, - DU_DB2_MARK, - PWM5_A_MARK, - A3_IMARK, - LCDOUT19_MARK, - MSIOF3_RXD_B_MARK, - VI4_DATA11_MARK, - DU_DB3_MARK, - PWM6_A_MARK, - A4_IMARK, - LCDOUT20_MARK, - MSIOF3_SS1_B_MARK, - VI4_DATA12_MARK, - VI5_DATA12_MARK, - DU_DB4_MARK, - A5_IMARK, - LCDOUT21_MARK, - MSIOF3_SS2_B_MARK, - SCK4_B_MARK, - VI4_DATA13_MARK, - VI5_DATA13_MARK, - DU_DB5_MARK, - A6_IMARK, - LCDOUT22_MARK, - MSIOF2_SS1_A_MARK, - RX4_B_MARK, - VI4_DATA14_MARK, - VI5_DATA14_MARK, - DU_DB6_MARK, - A7_IMARK, - LCDOUT23_MARK, - MSIOF2_SS2_A_MARK, - TX4_B_MARK, - VI4_DATA15_MARK, - V15_DATA15_MARK, - DU_DB7_MARK, - A8_IMARK, - RX3_B_MARK, - MSIOF2_SYNC_A_MARK, - HRX4_B_MARK, - SDA6_A_MARK, - AVB_AVTP_MATCH_B_MARK, - PWM1_B_MARK, - - /* IPSR3 */ - A9_IMARK, - MSIOF2_SCK_A_MARK, - CTS4x_B_MARK, - VI5_VSYNCx_MARK, - A10_IMARK, - MSIOF2_RXD_A_MARK, - RTS4n_TANS_B_MARK, - VI5_HSYNCx_MARK, - A11_IMARK, - TX3_B_MARK, - MSIOF2_TXD_A_MARK, - HTX4_B_MARK, - HSCK4_MARK, - VI5_FIELD_MARK, - SCL6_A_MARK, - AVB_AVTP_CAPTURE_B_MARK, - PWM2_B_MARK, - A12_IMARK, - LCDOUT12_MARK, - MSIOF3_SCK_C_MARK, - HRX4_A_MARK, - VI5_DATA8_MARK, - DU_DG4_MARK, - A13_IMARK, - LCDOUT13_MARK, - MSIOF3_SYNC_C_MARK, - HTX4_A_MARK, - VI5_DATA9_MARK, - DU_DG5_MARK, - A14_IMARK, - LCDOUT14_MARK, - MSIOF3_RXD_C_MARK, - HCTS4x_MARK, - VI5_DATA10_MARK, - DU_DG6_MARK, - A15_IMARK, - LCDOUT15_MARK, - MSIOF3_TXD_C_MARK, - HRTS4x_MARK, - VI5_DATA11_MARK, - DU_DG7_MARK, - A16_IMARK, - LCDOUT8_MARK, - VI4_FIELD_MARK, - DU_DG0_MARK, - - /* IPSR4 */ - A17_IMARK, - LCDOUT9_MARK, - VI4_VSYNCx_MARK, - DU_DG1_MARK, - A18_IMARK, - LCDOUT10_MARK, - VI4_HSYNCx_MARK, - DU_DG2_MARK, - A19_IMARK, - LCDOUT11_MARK, - VI4_CLKENB_MARK, - DU_DG3_MARK, - CS0x_IMARK, - VI5_CLKENB_MARK, - CS1x_A26_IMARK, - VI5_CLK_MARK, - EX_WAIT0_B_MARK, - BSx_IMARK, - QSTVA_QVS_MARK, - MSIOF3_SCK_D_MARK, - SCK3_MARK, - HSCK3_MARK, - CAN1_TX_MARK, - CANFD1_TX_MARK, - IETX_A_MARK, - RDx_IMARK, - MSIOF3_SYNC_D_MARK, - RX3_A_MARK, - HRX3_A_MARK, - CAN0_TX_A_MARK, - CANFD0_TX_A_MARK, - RD_WRx_IMARK, - MSIOF3_RXD_D_MARK, - TX3_A_MARK, - HTX3_A_MARK, - CAN0_RX_A_MARK, - CANFD0_RX_A_MARK, - - /* IPSR5 */ - WE0x_IMARK, - MSIIOF3_TXD_D_MARK, - CTS3x_MARK, - HCTS3x_MARK, - SCL6_B_MARK, - CAN_CLK_MARK, - IECLK_A_MARK, - WE1x_IMARK, - MSIOF3_SS1_D_MARK, - RTS3x_TANS_MARK, - HRTS3x_MARK, - SDA6_B_MARK, - CAN1_RX_MARK, - CANFD1_RX_MARK, - IERX_A_MARK, - EX_WAIT0_A_IMARK, - QCLK_MARK, - VI4_CLK_MARK, - DU_DOTCLKOUT0_MARK, - D0_IMARK, - MSIOF2_SS1_B_MARK, - MSIOF3_SCK_A_MARK, - VI4_DATA16_MARK, - VI5_DATA0_MARK, - D1_IMARK, - MSIOF2_SS2_B_MARK, - MSIOF3_SYNC_A_MARK, - VI4_DATA17_MARK, - VI5_DATA1_MARK, - D2_IMARK, - MSIOF3_RXD_A_MARK, - VI4_DATA18_MARK, - VI5_DATA2_MARK, - D3_IMARK, - MSIOF3_TXD_A_MARK, - VI4_DATA19_MARK, - VI5_DATA3_MARK, - D4_IMARK, - MSIOF2_SCK_B_MARK, - VI4_DATA20_MARK, - VI5_DATA4_MARK, - - /* IPSR6 */ - D5_IMARK, - MSIOF2_SYNC_B_MARK, - VI4_DATA21_MARK, - VI5_DATA5_MARK, - D6_IMARK, - MSIOF2_RXD_B_MARK, - VI4_DATA22_MARK, - VI5_DATA6_MARK, - D7_IMARK, - MSIOF2_TXD_B_MARK, - VI4_DATA23_MARK, - VI5_DATA7_MARK, - D8_IMARK, - LCDOUT0_MARK, - MSIOF2_SCK_D_MARK, - SCK4_C_MARK, - VI4_DATA0_A_MARK, - DU_DR0_MARK, - D9_IMARK, - LCDOUT1_MARK, - MSIOF2_SYNC_D_MARK, - VI4_DATA1_A_MARK, - DU_DR1_MARK, - D10_IMARK, - LCDOUT2_MARK, - MSIOF2_RXD_D_MARK, - HRX3_B_MARK, - VI4_DATA2_A_MARK, - CTS4x_C_MARK, - DU_DR2_MARK, - D11_IMARK, - LCDOUT3_MARK, - MSIOF2_TXD_D_MARK, - HTX3_B_MARK, - VI4_DATA3_A_MARK, - RTS4x_TANS_C_MARK, - DU_DR3_MARK, - D12_IMARK, - LCDOUT4_MARK, - MSIOF2_SS1_D_MARK, - RX4_C_MARK, - VI4_DATA4_A_MARK, - DU_DR4_MARK, - - /* IPSR7 */ - D13_IMARK, - LCDOUT5_MARK, - MSIOF2_SS2_D_MARK, - TX4_C_MARK, - VI4_DATA5_A_MARK, - DU_DR5_MARK, - D14_IMARK, - LCDOUT6_MARK, - MSIOF3_SS1_A_MARK, - HRX3_C_MARK, - VI4_DATA6_A_MARK, - DU_DR6_MARK, - SCL6_C_MARK, - D15_IMARK, - LCDOUT7_MARK, - MSIOF3_SS2_A_MARK, - HTX3_C_MARK, - VI4_DATA7_A_MARK, - DU_DR7_MARK, - SDA6_C_MARK, - FSCLKST_MARK, - SD0_CLK_IMARK, - MSIOF1_SCK_E_MARK, - STP_OPWM_0_B_MARK, - SD0_CMD_IMARK, - MSIOF1_SYNC_E_MARK, - STP_IVCXO27_0_B_MARK, - SD0_DAT0_IMARK, - MSIOF1_RXD_E_MARK, - TS_SCK0_B_MARK, - STP_ISCLK_0_B_MARK, - SD0_DAT1_IMARK, - MSIOF1_TXD_E_MARK, - TS_SPSYNC0_B_MARK, - STP_ISSYNC_0_B_MARK, - - /* IPSR8 */ - SD0_DAT2_IMARK, - MSIOF1_SS1_E_MARK, - TS_SDAT0_B_MARK, - STP_ISD_0_B_MARK, - SD0_DAT3_IMARK, - MSIOF1_SS2_E_MARK, - TS_SDEN0_B_MARK, - STP_ISEN_0_B_MARK, - SD1_CLK_IMARK, - MSIOF1_SCK_G_MARK, - SIM0_CLK_A_MARK, - SD1_CMD_IMARK, - MSIOF1_SYNC_G_MARK, - NFCEx_B_MARK, - SIM0_D_A_MARK, - STP_IVCXO27_1_B_MARK, - SD1_DAT0_IMARK, - SD2_DAT4_MARK, - MSIOF1_RXD_G_MARK, - NFWPx_B_MARK, - TS_SCK1_B_MARK, - STP_ISCLK_1_B_MARK, - SD1_DAT1_IMARK, - SD2_DAT5_MARK, - MSIOF1_TXD_G_MARK, - NFDATA14_B_MARK, - TS_SPSYNC1_B_MARK, - STP_ISSYNC_1_B_MARK, - SD1_DAT2_IMARK, - SD2_DAT6_MARK, - MSIOF1_SS1_G_MARK, - NFDATA15_B_MARK, - TS_SDAT1_B_MARK, - STP_IOD_1_B_MARK, - SD1_DAT3_IMARK, - SD2_DAT7_MARK, - MSIOF1_SS2_G_MARK, - NFRBx_B_MARK, - TS_SDEN1_B_MARK, - STP_ISEN_1_B_MARK, - - /* IPSR9 */ - SD2_CLK_IMARK, - NFDATA8_MARK, - SD2_CMD_IMARK, - NFDATA9_MARK, - SD2_DAT0_IMARK, - NFDATA10_MARK, - SD2_DAT1_IMARK, - NFDATA11_MARK, - SD2_DAT2_IMARK, - NFDATA12_MARK, - SD2_DAT3_IMARK, - NFDATA13_MARK, - SD2_DS_IMARK, - NFALE_MARK, - SATA_DEVSLP_B_MARK, - SD3_CLK_IMARK, - NFWEx_MARK, - - /* IPSR10 */ - SD3_CMD_IMARK, - NFREx_MARK, - SD3_DAT0_IMARK, - NFDATA0_MARK, - SD3_DAT1_IMARK, - NFDATA1_MARK, - SD3_DAT2_IMARK, - NFDATA2_MARK, - SD3_DAT3_IMARK, - NFDATA3_MARK, - SD3_DAT4_IMARK, - SD2_CD_A_MARK, - NFDATA4_MARK, - SD3_DAT5_IMARK, - SD2_WP_A_MARK, - NFDATA5_MARK, - SD3_DAT6_IMARK, - SD3_CD_MARK, - NFDATA6_MARK, - - /* IPSR11 */ - SD3_DAT7_IMARK, - SD3_WP_MARK, - NFDATA7_MARK, - SD3_DS_IMARK, - NFCLE_MARK, - SD0_CD_IMARK, - NFDATA14_A_MARK, - SCL2_B_MARK, - SIM0_RST_A_MARK, - SD0_WP_IMARK, - NFDATA15_A_MARK, - SDA2_B_MARK, - SD1_CD_IMARK, - NFRBx_A_MARK, - SIM0_CLK_B_MARK, - SD1_WP_IMARK, - NFCEx_A_MARK, - SIM0_D_B_MARK, - SCK0_IMARK, - HSCK1_B_MARK, - MSIOF1_SS2_B_MARK, - AUDIO_CLKC_B_MARK, - SDA2_A_MARK, - SIM0_RST_B_MARK, - STP_OPWM_0_C_MARK, - RIF0_CLK_B_MARK, - ADICHS2_MARK, - SCK5_B_MARK, - RX0_IMARK, - HRX1_B_MARK, - TS_SCK0_C_MARK, - STP_ISCLK_0_C_MARK, - RIF0_D0_B_MARK, - - /* IPSR12 */ - TX0_IMARK, - HTX1_B_MARK, - TS_SPSYNC0_C_MARK, - STP_ISSYNC_0_C_MARK, - RIF0_D1_B_MARK, - CTS0x_IMARK, - HCTS1x_B_MARK, - MSIOF1_SYNC_B_MARK, - TS_SPSYNC1_C_MARK, - STP_ISSYNC_1_C_MARK, - RIF1_SYNC_B_MARK, - AUDIO_CLKOUT_C_MARK, - ADICS_SAMP_MARK, - RTS0x_TANS_IMARK, - HRTS1x_B_MARK, - MSIOF1_SS1_B_MARK, - AUDIO_CLKA_B_MARK, - SCL2_A_MARK, - STP_IVCXO27_1_C_MARK, - RIF0_SYNC_B_MARK, - ADICHS1_MARK, - RX1_A_IMARK, - HRX1_A_MARK, - TS_SDAT0_C_MARK, - STP_ISD_0_C_MARK, - RIF1_CLK_C_MARK, - TX1_A_IMARK, - HTX1_A_MARK, - TS_SDEN0_C_MARK, - STP_ISEN_0_C_MARK, - RIF1_D0_C_MARK, - CTS1x_IMARK, - HCTS1x_A_MARK, - MSIOF1_RXD_B_MARK, - TS_SDEN1_C_MARK, - STP_ISEN_1_C_MARK, - RIF1_D0_B_MARK, - ADIDATA_MARK, - RTS1x_TANS_IMARK, - HRTS1x_A_MARK, - MSIOF1_TXD_B_MARK, - TS_SDAT1_C_MARK, - STP_ISD_1_C_MARK, - RIF1_D1_B_MARK, - ADICHS0_MARK, - SCK2_IMARK, - SCIF_CLK_B_MARK, - MSIOF1_SCK_B_MARK, - TS_SCK1_C_MARK, - STP_ISCLK_1_C_MARK, - RIF1_CLK_B_MARK, - ADICLK_MARK, - - /* IPSR13 */ - TX2_A_IMARK, - SD2_CD_B_MARK, - SCL1_A_MARK, - FMCLK_A_MARK, - RIF1_D1_C_MARK, - FSO_CFE_0x_MARK, - RX2_A_IMARK, - SD2_WP_B_MARK, - SDA1_A_MARK, - FMIN_A_MARK, - RIF1_SYNC_C_MARK, - FSO_CFE_1x_MARK, - HSCK0_IMARK, - MSIOF1_SCK_D_MARK, - AUDIO_CLKB_A_MARK, - SSI_SDATA1_B_MARK, - TS_SCK0_D_MARK, - STP_ISCLK_0_D_MARK, - RIF0_CLK_C_MARK, - RX5_B_MARK, - HRX0_IMARK, - MSIOF1_RXD_D_MARK, - SSI_SDATA2_B_MARK, - TS_SDEN0_D_MARK, - STP_ISEN_0_D_MARK, - RIF0_D0_C_MARK, - HTX0_IMARK, - MSIOF1_TXD_D_MARK, - SSI_SDATA9_B_MARK, - TS_SDAT0_D_MARK, - STP_ISD_0_D_MARK, - RIF0_D1_C_MARK, - HCTS0x_IMARK, - RX2_B_MARK, - MSIOF1_SYNC_D_MARK, - SSI_SCK9_A_MARK, - TS_SPSYNC0_D_MARK, - STP_ISSYNC_0_D_MARK, - RIF0_SYNC_C_MARK, - AUDIO_CLKOUT1_A_MARK, - HRTS0x_IMARK, - TX2_B_MARK, - MSIOF1_SS1_D_MARK, - SSI_WS9_A_MARK, - STP_IVCXO27_0_D_MARK, - BPFCLK_A_MARK, - AUDIO_CLKOUT2_A_MARK, - MSIOF0_SYNC_IMARK, - AUDIO_CLKOUT_A_MARK, - TX5_B_MARK, - BPFCLK_D_MARK, - - /* IPSR14 */ - MSIOF0_SS1_IMARK, - RX5_A_MARK, - NFWPx_A_MARK, - AUDIO_CLKA_C_MARK, - SSI_SCK2_A_MARK, - STP_IVCXO27_0_C_MARK, - AUDIO_CLKOUT3_A_MARK, - TCLK1_B_MARK, - MSIOF0_SS2_IMARK, - TX5_A_MARK, - MSIOF1_SS2_D_MARK, - AUDIO_CLKC_A_MARK, - SSI_WS2_A_MARK, - STP_OPWM_0_D_MARK, - AUDIO_CLKOUT_D_MARK, - SPEEDIN_B_MARK, - MLB_CLK_IMARK, - MSIOF1_SCK_F_MARK, - SCL1_B_MARK, - MLB_SIG_IMARK, - RX1_B_MARK, - MSIOF1_SYNC_F_MARK, - SDA1_B_MARK, - MLB_DAT_IMARK, - TX1_B_MARK, - MSIOF1_RXD_F_MARK, - SSI_SCK01239_IMARK, - MSIOF1_TXD_F_MARK, - MOUT0_MARK, - SSI_WS01239_IMARK, - MSIOF1_SS1_F_MARK, - MOUT1_MARK, - SSI_SDATA0_IMARK, - MSIOF1_SS2_F_MARK, - MOUT2_MARK, - - /* IPSR15 */ - SSI_SDATA1_A_IMARK, - MOUT5_MARK, - SSI_SDATA2_A_IMARK, - SSI_SCK1_B_MARK, - MOUT6_MARK, - SSI_SCK34_IMARK, - MSIOF1_SS1_A_MARK, - STP_OPWM_0_A_MARK, - SSI_WS34_IMARK, - HCTS2x_A_MARK, - MSIOF1_SS2_A_MARK, - STP_IVCXO27_0_A_MARK, - SSI_SDATA3_IMARK, - HRTS2x_A_MARK, - MSIOF1_TXD_A_MARK, - TS_SCK0_A_MARK, - STP_ISCLK_0_A_MARK, - RIF0_D1_A_MARK, - RIF2_D0_A_MARK, - SSI_SCK4_IMARK, - HRX2_A_MARK, - MSIOF1_SCK_A_MARK, - TS_SDAT0_A_MARK, - STP_ISD_0_A_MARK, - RIF0_CLK_A_MARK, - RIF2_CLK_A_MARK, - SSI_WS4_IMARK, - HTX2_A_MARK, - MSIOF1_SYNC_A_MARK, - TS_SDEN0_A_MARK, - STP_ISEN_0_A_MARK, - RIF0_SYNC_A_MARK, - RIF2_SYNC_A_MARK, - SSI_SDATA4_IMARK, - HSCK2_A_MARK, - MSIOF1_RXD_A_MARK, - TS_SPSYNC0_A_MARK, - STP_ISSYNC_0_A_MARK, - RIF0_D0_A_MARK, - RIF2_D1_A_MARK, - - /* IPSR16 */ - SSI_SCK6_IMARK, - SIM0_RST_D_MARK, - SSI_WS6_IMARK, - SIM0_D_D_MARK, - SSI_SDATA6_IMARK, - SIM0_CLK_D_MARK, - SATA_DEVSLP_A_MARK, - SSI_SCK78_IMARK, - HRX2_B_MARK, - MSIOF1_SCK_C_MARK, - TS_SCK1_A_MARK, - STP_ISCLK_1_A_MARK, - RIF1_CLK_A_MARK, - RIF3_CLK_A_MARK, - SSI_WS78_IMARK, - HTX2_B_MARK, - MSIOF1_SYNC_C_MARK, - TS_SDAT1_A_MARK, - STP_ISD_1_A_MARK, - RIF1_SYNC_A_MARK, - RIF3_SYNC_A_MARK, - SSI_SDATA7_IMARK, - HCTS2x_B_MARK, - MSIOF1_RXD_C_MARK, - TS_SDEN1_A_MARK, - STP_ISEN_1_A_MARK, - RIF1_D0_A_MARK, - RIF3_D0_A_MARK, - TCLK2_A_MARK, - SSI_SDATA8_IMARK, - HRTS2x_B_MARK, - MSIOF1_TXD_C_MARK, - TS_SPSYNC1_A_MARK, - STP_ISSYNC_1_A_MARK, - RIF1_D1_A_MARK, - RIF3_D1_A_MARK, - SSI_SDATA9_A_IMARK, - HSCK2_B_MARK, - MSIOF1_SS1_C_MARK, - HSCK1_A_MARK, - SSI_WS1_B_MARK, - SCK1_MARK, - STP_IVCXO27_1_A_MARK, - SCK5_A_MARK, - - /* IPSR17 */ - AUDIO_CLKA_A_IMARK, - CC5_OSCOUT_MARK, - AUDIO_CLKB_B_IMARK, - SCIF_CLK_A_MARK, - STP_IVCXO27_1_D_MARK, - REMOCON_A_MARK, - TCLK1_A_MARK, - USB0_PWEN_IMARK, - SIM0_RST_C_MARK, - TS_SCK1_D_MARK, - STP_ISCLK_1_D_MARK, - BPFCLK_B_MARK, - RIF3_CLK_B_MARK, - HSCK2_C_MARK, - USB0_OVC_IMARK, - SIM0_D_C_MARK, - TS_SDAT1_D_MARK, - STP_ISD_1_D_MARK, - RIF3_SYNC_B_MARK, - HRX2_C_MARK, - USB1_PWEN_IMARK, - SIM0_CLK_C_MARK, - SSI_SCK1_A_MARK, - TS_SCK0_E_MARK, - STP_ISCLK_0_E_MARK, - FMCLK_B_MARK, - RIF2_CLK_B_MARK, - SPEEDIN_A_MARK, - HTX2_C_MARK, - USB1_OVC_IMARK, - MSIOF1_SS2_C_MARK, - SSI_WS1_A_MARK, - TS_SDAT0_E_MARK, - STP_ISD_0_E_MARK, - FMIN_B_MARK, - RIF2_SYNC_B_MARK, - REMOCON_B_MARK, - HCTS2x_C_MARK, - USB30_PWEN_IMARK, - AUDIO_CLKOUT_B_MARK, - SSI_SCK2_B_MARK, - TS_SDEN1_D_MARK, - STP_ISEN_1_D_MARK, - STP_OPWM_0_E_MARK, - RIF3_D0_B_MARK, - TCLK2_B_MARK, - TPU0TO0_MARK, - BPFCLK_C_MARK, - HRTS2x_C_MARK, - USB30_OVC_IMARK, - AUDIO_CLKOUT1_B_MARK, - SSI_WS2_B_MARK, - TS_SPSYNC1_D_MARK, - STP_ISSYNC_1_D_MARK, - STP_IVCXO27_0_E_MARK, - RIF3_D1_B_MARK, - FSO_TOEx_MARK, - TPU0TO1_MARK, - - /* IPSR18 */ - USB3_PWEN_IMARK, - AUDIO_CLKOUT2_B_MARK, - SSI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - TPU0TO2_MARK, - FMCLK_C_MARK, - FMCLK_D_MARK, - - USB3_OVC_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - FMIN_C_MARK, - FMIN_D_MARK, - - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - - /* GPSR0 */ - PINMUX_DATA(D15_GMARK, GFN_D15), - PINMUX_DATA(D14_GMARK, GFN_D14), - PINMUX_DATA(D13_GMARK, GFN_D13), - PINMUX_DATA(D12_GMARK, GFN_D12), - PINMUX_DATA(D11_GMARK, GFN_D11), - PINMUX_DATA(D10_GMARK, GFN_D10), - PINMUX_DATA(D9_GMARK, GFN_D9), - PINMUX_DATA(D8_GMARK, GFN_D8), - PINMUX_DATA(D7_GMARK, GFN_D7), - PINMUX_DATA(D6_GMARK, GFN_D6), - PINMUX_DATA(D5_GMARK, GFN_D5), - PINMUX_DATA(D4_GMARK, GFN_D4), - PINMUX_DATA(D3_GMARK, GFN_D3), - PINMUX_DATA(D2_GMARK, GFN_D2), - PINMUX_DATA(D1_GMARK, GFN_D1), - PINMUX_DATA(D0_GMARK, GFN_D0), - - /* GPSR1 */ - PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), - PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), - PINMUX_DATA(WE1x_GMARK, GFN_WE1x), - PINMUX_DATA(WE0x_GMARK, GFN_WE0x), - PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), - PINMUX_DATA(RDx_GMARK, GFN_RDx), - PINMUX_DATA(BSx_GMARK, GFN_BSx), - PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), - PINMUX_DATA(CS0x_GMARK, GFN_CS0x), - PINMUX_DATA(A19_GMARK, GFN_A19), - PINMUX_DATA(A18_GMARK, GFN_A18), - PINMUX_DATA(A17_GMARK, GFN_A17), - PINMUX_DATA(A16_GMARK, GFN_A16), - PINMUX_DATA(A15_GMARK, GFN_A15), - PINMUX_DATA(A14_GMARK, GFN_A14), - PINMUX_DATA(A13_GMARK, GFN_A13), - PINMUX_DATA(A12_GMARK, GFN_A12), - PINMUX_DATA(A11_GMARK, GFN_A11), - PINMUX_DATA(A10_GMARK, GFN_A10), - PINMUX_DATA(A9_GMARK, GFN_A9), - PINMUX_DATA(A8_GMARK, GFN_A8), - PINMUX_DATA(A7_GMARK, GFN_A7), - PINMUX_DATA(A6_GMARK, GFN_A6), - PINMUX_DATA(A5_GMARK, GFN_A5), - PINMUX_DATA(A4_GMARK, GFN_A4), - PINMUX_DATA(A3_GMARK, GFN_A3), - PINMUX_DATA(A2_GMARK, GFN_A2), - PINMUX_DATA(A1_GMARK, GFN_A1), - PINMUX_DATA(A0_GMARK, GFN_A0), - - /* GPSR2 */ - PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), - PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), - PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), - PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), - PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), - PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), - PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), - PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), - PINMUX_DATA(PWM0_GMARK, GFN_PWM0), - PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), - PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), - PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), - PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), - PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), - PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), - - /* GPSR3 */ - PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), - PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), - PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), - PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), - PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), - PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), - PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), - PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), - PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), - PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), - PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), - PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), - PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), - PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), - PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), - PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), - - /* GPSR4 */ - PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), - PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), - PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), - PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), - PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD), - PINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK), - PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), - PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), - PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), - PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), - PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD), - PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), - - /* GPSR5 */ - PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), - PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), - PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), - PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), - PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), - PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), - PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), - PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), - PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), - PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), - PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), - PINMUX_DATA(HTX0_GMARK, GFN_HTX0), - PINMUX_DATA(HRX0_GMARK, GFN_HRX0), - PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), - PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), - PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), - PINMUX_DATA(SCK2_GMARK, GFN_SCK2), - PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), - PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), - PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), - PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), - PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), - PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), - PINMUX_DATA(TX0_GMARK, GFN_TX0), - PINMUX_DATA(RX0_GMARK, GFN_RX0), - PINMUX_DATA(SCK0_GMARK, GFN_SCK0), - - /* GPSR6 */ - PINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC), - PINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN), - PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), - PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), - PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), - PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), - PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), - PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), - PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), - PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), - PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), - PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), - PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), - PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), - PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), - PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), - PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), - PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), - PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), - PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), - PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), - PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), - PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), - PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), - PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), - PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), - PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), - PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), - PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), - PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), - PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), - - /* GPSR7 */ - PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), - PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(AVS1_MARK, FN_AVS1), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - PINMUX_GPIO_GP_ALL(), - /* GPSR0 */ - GPIO_GFN(D15), - GPIO_GFN(D14), - GPIO_GFN(D13), - GPIO_GFN(D12), - GPIO_GFN(D11), - GPIO_GFN(D10), - GPIO_GFN(D9), - GPIO_GFN(D8), - GPIO_GFN(D7), - GPIO_GFN(D6), - GPIO_GFN(D5), - GPIO_GFN(D4), - GPIO_GFN(D3), - GPIO_GFN(D2), - GPIO_GFN(D1), - GPIO_GFN(D0), - /* GPSR1 */ - GPIO_GFN(CLKOUT), - GPIO_GFN(EX_WAIT0_A), - GPIO_GFN(WE1x), - GPIO_GFN(WE0x), - GPIO_GFN(RD_WRx), - GPIO_GFN(RDx), - GPIO_GFN(BSx), - GPIO_GFN(CS1x_A26), - GPIO_GFN(CS0x), - GPIO_GFN(A19), - GPIO_GFN(A18), - GPIO_GFN(A17), - GPIO_GFN(A16), - GPIO_GFN(A15), - GPIO_GFN(A14), - GPIO_GFN(A13), - GPIO_GFN(A12), - GPIO_GFN(A11), - GPIO_GFN(A10), - GPIO_GFN(A9), - GPIO_GFN(A8), - GPIO_GFN(A7), - GPIO_GFN(A6), - GPIO_GFN(A5), - GPIO_GFN(A4), - GPIO_GFN(A3), - GPIO_GFN(A2), - GPIO_GFN(A1), - GPIO_GFN(A0), - - /* GPSR2 */ - GPIO_GFN(AVB_AVTP_CAPTURE_A), - GPIO_GFN(AVB_AVTP_MATCH_A), - GPIO_GFN(AVB_LINK), - GPIO_GFN(AVB_PHY_INT), - GPIO_GFN(AVB_MAGIC), - GPIO_GFN(AVB_MDC), - GPIO_GFN(PWM2_A), - GPIO_GFN(PWM1_A), - GPIO_GFN(PWM0), - GPIO_GFN(IRQ5), - GPIO_GFN(IRQ4), - GPIO_GFN(IRQ3), - GPIO_GFN(IRQ2), - GPIO_GFN(IRQ1), - GPIO_GFN(IRQ0), - - /* GPSR3 */ - GPIO_GFN(SD1_WP), - GPIO_GFN(SD1_CD), - GPIO_GFN(SD0_WP), - GPIO_GFN(SD0_CD), - GPIO_GFN(SD1_DAT3), - GPIO_GFN(SD1_DAT2), - GPIO_GFN(SD1_DAT1), - GPIO_GFN(SD1_DAT0), - GPIO_GFN(SD1_CMD), - GPIO_GFN(SD1_CLK), - GPIO_GFN(SD0_DAT3), - GPIO_GFN(SD0_DAT2), - GPIO_GFN(SD0_DAT1), - GPIO_GFN(SD0_DAT0), - GPIO_GFN(SD0_CMD), - GPIO_GFN(SD0_CLK), - - /* GPSR4 */ - GPIO_GFN(SD3_DS), - GPIO_GFN(SD3_DAT7), - GPIO_GFN(SD3_DAT6), - GPIO_GFN(SD3_DAT5), - GPIO_GFN(SD3_DAT4), - GPIO_GFN(SD3_DAT3), - GPIO_GFN(SD3_DAT2), - GPIO_GFN(SD3_DAT1), - GPIO_GFN(SD3_DAT0), - GPIO_GFN(SD3_CMD), - GPIO_GFN(SD3_CLK), - GPIO_GFN(SD2_DS), - GPIO_GFN(SD2_DAT3), - GPIO_GFN(SD2_DAT2), - GPIO_GFN(SD2_DAT1), - GPIO_GFN(SD2_DAT0), - GPIO_GFN(SD2_CMD), - GPIO_GFN(SD2_CLK), - - /* GPSR5 */ - GPIO_GFN(MLB_DAT), - GPIO_GFN(MLB_SIG), - GPIO_GFN(MLB_CLK), - GPIO_FN(MSIOF0_RXD), - GPIO_GFN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - GPIO_GFN(MSIOF0_SS1), - GPIO_GFN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_SCK), - GPIO_GFN(HRTS0x), - GPIO_GFN(HCTS0x), - GPIO_GFN(HTX0), - GPIO_GFN(HRX0), - GPIO_GFN(HSCK0), - GPIO_GFN(RX2_A), - GPIO_GFN(TX2_A), - GPIO_GFN(SCK2), - GPIO_GFN(RTS1x_TANS), - GPIO_GFN(CTS1x), - GPIO_GFN(TX1_A), - GPIO_GFN(RX1_A), - GPIO_GFN(RTS0x_TANS), - GPIO_GFN(CTS0x), - GPIO_GFN(TX0), - GPIO_GFN(RX0), - GPIO_GFN(SCK0), - - /* GPSR6 */ - GPIO_GFN(USB3_OVC), - GPIO_GFN(USB3_PWEN), - GPIO_GFN(USB30_OVC), - GPIO_GFN(USB30_PWEN), - GPIO_GFN(USB1_OVC), - GPIO_GFN(USB1_PWEN), - GPIO_GFN(USB0_OVC), - GPIO_GFN(USB0_PWEN), - GPIO_GFN(AUDIO_CLKB_B), - GPIO_GFN(AUDIO_CLKA_A), - GPIO_GFN(SSI_SDATA9_A), - GPIO_GFN(SSI_SDATA8), - GPIO_GFN(SSI_SDATA7), - GPIO_GFN(SSI_WS78), - GPIO_GFN(SSI_SCK78), - GPIO_GFN(SSI_SDATA6), - GPIO_GFN(SSI_WS6), - GPIO_GFN(SSI_SCK6), - GPIO_FN(SSI_SDATA5), - GPIO_FN(SSI_WS5), - GPIO_FN(SSI_SCK5), - GPIO_GFN(SSI_SDATA4), - GPIO_GFN(SSI_WS4), - GPIO_GFN(SSI_SCK4), - GPIO_GFN(SSI_SDATA3), - GPIO_GFN(SSI_WS34), - GPIO_GFN(SSI_SCK34), - GPIO_GFN(SSI_SDATA2_A), - GPIO_GFN(SSI_SDATA1_A), - GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS01239), - GPIO_GFN(SSI_SCK01239), - - /* GPSR7 */ - GPIO_FN(HDMI1_CEC), - GPIO_FN(HDMI0_CEC), - GPIO_FN(AVS2), - GPIO_FN(AVS1), - - /* IPSR0 */ - GPIO_IFN(AVB_MDC), - GPIO_FN(MSIOF2_SS2_C), - GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_SS1_C), - GPIO_FN(SCK4_A), - GPIO_IFN(AVB_PHY_INT), - GPIO_FN(MSIOF2_SYNC_C), - GPIO_FN(RX4_A), - GPIO_IFN(AVB_LINK), - GPIO_FN(MSIOF2_SCK_C), - GPIO_FN(TX4_A), - GPIO_IFN(AVB_AVTP_MATCH_A), - GPIO_FN(MSIOF2_RXD_C), - GPIO_FN(CTS4x_A), - GPIO_FN(FSCLKST2x_A), - GPIO_IFN(AVB_AVTP_CAPTURE_A), - GPIO_FN(MSIOF2_TXD_C), - GPIO_FN(RTS4x_TANS_A), - GPIO_IFN(IRQ0), - GPIO_FN(QPOLB), - GPIO_FN(DU_CDE), - GPIO_FN(VI4_DATA0_B), - GPIO_FN(CAN0_TX_B), - GPIO_FN(CANFD0_TX_B), - GPIO_FN(MSIOF3_SS2_E), - GPIO_IFN(IRQ1), - GPIO_FN(QPOLA), - GPIO_FN(DU_DISP), - GPIO_FN(VI4_DATA1_B), - GPIO_FN(CAN0_RX_B), - GPIO_FN(CANFD0_RX_B), - GPIO_FN(MSIOF3_SS1_E), - - /* IPSR1 */ - GPIO_IFN(IRQ2), - GPIO_FN(QCPV_QDE), - GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), - GPIO_FN(VI4_DATA2_B), - GPIO_FN(MSIOF3_SYNC_E), - GPIO_FN(PWM3_B), - GPIO_IFN(IRQ3), - GPIO_FN(QSTVB_QVE), - GPIO_FN(DU_DOTCLKOUT1), - GPIO_FN(VI4_DATA3_B), - GPIO_FN(MSIOF3_SCK_E), - GPIO_FN(PWM4_B), - GPIO_IFN(IRQ4), - GPIO_FN(QSTH_QHS), - GPIO_FN(DU_EXHSYNC_DU_HSYNC), - GPIO_FN(VI4_DATA4_B), - GPIO_FN(MSIOF3_RXD_E), - GPIO_FN(PWM5_B), - GPIO_IFN(IRQ5), - GPIO_FN(QSTB_QHE), - GPIO_FN(DU_EXVSYNC_DU_VSYNC), - GPIO_FN(VI4_DATA5_B), - GPIO_FN(FSCLKST2x_B), - GPIO_FN(MSIOF3_TXD_E), - GPIO_FN(PWM6_B), - GPIO_IFN(PWM0), - GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(VI4_DATA6_B), - GPIO_FN(IECLK_B), - GPIO_IFN(PWM1_A), - GPIO_FN(HRX3_D), - GPIO_FN(VI4_DATA7_B), - GPIO_FN(IERX_B), - GPIO_IFN(PWM2_A), - GPIO_FN(HTX3_D), - GPIO_FN(IETX_B), - GPIO_IFN(A0), - GPIO_FN(LCDOUT16), - GPIO_FN(MSIOF3_SYNC_B), - GPIO_FN(VI4_DATA8), - GPIO_FN(DU_DB0), - GPIO_FN(PWM3_A), - - /* IPSR2 */ - GPIO_IFN(A1), - GPIO_FN(LCDOUT17), - GPIO_FN(MSIOF3_TXD_B), - GPIO_FN(VI4_DATA9), - GPIO_FN(DU_DB1), - GPIO_FN(PWM4_A), - GPIO_IFN(A2), - GPIO_FN(LCDOUT18), - GPIO_FN(MSIOF3_SCK_B), - GPIO_FN(VI4_DATA10), - GPIO_FN(DU_DB2), - GPIO_FN(PWM5_A), - GPIO_IFN(A3), - GPIO_FN(LCDOUT19), - GPIO_FN(MSIOF3_RXD_B), - GPIO_FN(VI4_DATA11), - GPIO_FN(DU_DB3), - GPIO_FN(PWM6_A), - GPIO_IFN(A4), - GPIO_FN(LCDOUT20), - GPIO_FN(MSIOF3_SS1_B), - GPIO_FN(VI4_DATA12), - GPIO_FN(VI5_DATA12), - GPIO_FN(DU_DB4), - GPIO_IFN(A5), - GPIO_FN(LCDOUT21), - GPIO_FN(MSIOF3_SS2_B), - GPIO_FN(SCK4_B), - GPIO_FN(VI4_DATA13), - GPIO_FN(VI5_DATA13), - GPIO_FN(DU_DB5), - GPIO_IFN(A6), - GPIO_FN(LCDOUT22), - GPIO_FN(MSIOF2_SS1_A), - GPIO_FN(RX4_B), - GPIO_FN(VI4_DATA14), - GPIO_FN(VI5_DATA14), - GPIO_FN(DU_DB6), - GPIO_IFN(A7), - GPIO_FN(LCDOUT23), - GPIO_FN(MSIOF2_SS2_A), - GPIO_FN(TX4_B), - GPIO_FN(VI4_DATA15), - GPIO_FN(V15_DATA15), - GPIO_FN(DU_DB7), - GPIO_IFN(A8), - GPIO_FN(RX3_B), - GPIO_FN(MSIOF2_SYNC_A), - GPIO_FN(HRX4_B), - GPIO_FN(SDA6_A), - GPIO_FN(AVB_AVTP_MATCH_B), - GPIO_FN(PWM1_B), - - /* IPSR3 */ - GPIO_IFN(A9), - GPIO_FN(MSIOF2_SCK_A), - GPIO_FN(CTS4x_B), - GPIO_FN(VI5_VSYNCx), - GPIO_IFN(A10), - GPIO_FN(MSIOF2_RXD_A), - GPIO_FN(RTS4n_TANS_B), - GPIO_FN(VI5_HSYNCx), - GPIO_IFN(A11), - GPIO_FN(TX3_B), - GPIO_FN(MSIOF2_TXD_A), - GPIO_FN(HTX4_B), - GPIO_FN(HSCK4), - GPIO_FN(VI5_FIELD), - GPIO_FN(SCL6_A), - GPIO_FN(AVB_AVTP_CAPTURE_B), - GPIO_FN(PWM2_B), - GPIO_IFN(A12), - GPIO_FN(LCDOUT12), - GPIO_FN(MSIOF3_SCK_C), - GPIO_FN(HRX4_A), - GPIO_FN(VI5_DATA8), - GPIO_FN(DU_DG4), - GPIO_IFN(A13), - GPIO_FN(LCDOUT13), - GPIO_FN(MSIOF3_SYNC_C), - GPIO_FN(HTX4_A), - GPIO_FN(VI5_DATA9), - GPIO_FN(DU_DG5), - GPIO_IFN(A14), - GPIO_FN(LCDOUT14), - GPIO_FN(MSIOF3_RXD_C), - GPIO_FN(HCTS4x), - GPIO_FN(VI5_DATA10), - GPIO_FN(DU_DG6), - GPIO_IFN(A15), - GPIO_FN(LCDOUT15), - GPIO_FN(MSIOF3_TXD_C), - GPIO_FN(HRTS4x), - GPIO_FN(VI5_DATA11), - GPIO_FN(DU_DG7), - GPIO_IFN(A16), - GPIO_FN(LCDOUT8), - GPIO_FN(VI4_FIELD), - GPIO_FN(DU_DG0), - - /* IPSR4 */ - GPIO_IFN(A17), - GPIO_FN(LCDOUT9), - GPIO_FN(VI4_VSYNCx), - GPIO_FN(DU_DG1), - GPIO_IFN(A18), - GPIO_FN(LCDOUT10), - GPIO_FN(VI4_HSYNCx), - GPIO_FN(DU_DG2), - GPIO_IFN(A19), - GPIO_FN(LCDOUT11), - GPIO_FN(VI4_CLKENB), - GPIO_FN(DU_DG3), - GPIO_IFN(CS0x), - GPIO_FN(VI5_CLKENB), - GPIO_IFN(CS1x_A26), - GPIO_FN(VI5_CLK), - GPIO_FN(EX_WAIT0_B), - GPIO_IFN(BSx), - GPIO_FN(QSTVA_QVS), - GPIO_FN(MSIOF3_SCK_D), - GPIO_FN(SCK3), - GPIO_FN(HSCK3), - GPIO_FN(CAN1_TX), - GPIO_FN(CANFD1_TX), - GPIO_FN(IETX_A), - GPIO_IFN(RDx), - GPIO_FN(MSIOF3_SYNC_D), - GPIO_FN(RX3_A), - GPIO_FN(HRX3_A), - GPIO_FN(CAN0_TX_A), - GPIO_FN(CANFD0_TX_A), - GPIO_IFN(RD_WRx), - GPIO_FN(MSIOF3_RXD_D), - GPIO_FN(TX3_A), - GPIO_FN(HTX3_A), - GPIO_FN(CAN0_RX_A), - GPIO_FN(CANFD0_RX_A), - - /* IPSR5 */ - GPIO_IFN(WE0x), - GPIO_FN(MSIIOF3_TXD_D), - GPIO_FN(CTS3x), - GPIO_FN(HCTS3x), - GPIO_FN(SCL6_B), - GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_A), - GPIO_IFN(WE1x), - GPIO_FN(MSIOF3_SS1_D), - GPIO_FN(RTS3x_TANS), - GPIO_FN(HRTS3x), - GPIO_FN(SDA6_B), - GPIO_FN(CAN1_RX), - GPIO_FN(CANFD1_RX), - GPIO_FN(IERX_A), - GPIO_IFN(EX_WAIT0_A), - GPIO_FN(QCLK), - GPIO_FN(VI4_CLK), - GPIO_FN(DU_DOTCLKOUT0), - GPIO_IFN(D0), - GPIO_FN(MSIOF2_SS1_B), - GPIO_FN(MSIOF3_SCK_A), - GPIO_FN(VI4_DATA16), - GPIO_FN(VI5_DATA0), - GPIO_IFN(D1), - GPIO_FN(MSIOF2_SS2_B), - GPIO_FN(MSIOF3_SYNC_A), - GPIO_FN(VI4_DATA17), - GPIO_FN(VI5_DATA1), - GPIO_IFN(D2), - GPIO_FN(MSIOF3_RXD_A), - GPIO_FN(VI4_DATA18), - GPIO_FN(VI5_DATA2), - GPIO_IFN(D3), - GPIO_FN(MSIOF3_TXD_A), - GPIO_FN(VI4_DATA19), - GPIO_FN(VI5_DATA3), - GPIO_IFN(D4), - GPIO_FN(MSIOF2_SCK_B), - GPIO_FN(VI4_DATA20), - GPIO_FN(VI5_DATA4), - - /* IPSR6 */ - GPIO_IFN(D5), - GPIO_FN(MSIOF2_SYNC_B), - GPIO_FN(VI4_DATA21), - GPIO_FN(VI5_DATA5), - GPIO_IFN(D6), - GPIO_FN(MSIOF2_RXD_B), - GPIO_FN(VI4_DATA22), - GPIO_FN(VI5_DATA6), - GPIO_IFN(D7), - GPIO_FN(MSIOF2_TXD_B), - GPIO_FN(VI4_DATA23), - GPIO_FN(VI5_DATA7), - GPIO_IFN(D8), - GPIO_FN(LCDOUT0), - GPIO_FN(MSIOF2_SCK_D), - GPIO_FN(SCK4_C), - GPIO_FN(VI4_DATA0_A), - GPIO_FN(DU_DR0), - GPIO_IFN(D9), - GPIO_FN(LCDOUT1), - GPIO_FN(MSIOF2_SYNC_D), - GPIO_FN(VI4_DATA1_A), - GPIO_FN(DU_DR1), - GPIO_IFN(D10), - GPIO_FN(LCDOUT2), - GPIO_FN(MSIOF2_RXD_D), - GPIO_FN(HRX3_B), - GPIO_FN(VI4_DATA2_A), - GPIO_FN(CTS4x_C), - GPIO_FN(DU_DR2), - GPIO_IFN(D11), - GPIO_FN(LCDOUT3), - GPIO_FN(MSIOF2_TXD_D), - GPIO_FN(HTX3_B), - GPIO_FN(VI4_DATA3_A), - GPIO_FN(RTS4x_TANS_C), - GPIO_FN(DU_DR3), - GPIO_IFN(D12), - GPIO_FN(LCDOUT4), - GPIO_FN(MSIOF2_SS1_D), - GPIO_FN(RX4_C), - GPIO_FN(VI4_DATA4_A), - GPIO_FN(DU_DR4), - - /* IPSR7 */ - GPIO_IFN(D13), - GPIO_FN(LCDOUT5), - GPIO_FN(MSIOF2_SS2_D), - GPIO_FN(TX4_C), - GPIO_FN(VI4_DATA5_A), - GPIO_FN(DU_DR5), - GPIO_IFN(D14), - GPIO_FN(LCDOUT6), - GPIO_FN(MSIOF3_SS1_A), - GPIO_FN(HRX3_C), - GPIO_FN(VI4_DATA6_A), - GPIO_FN(DU_DR6), - GPIO_FN(SCL6_C), - GPIO_IFN(D15), - GPIO_FN(LCDOUT7), - GPIO_FN(MSIOF3_SS2_A), - GPIO_FN(HTX3_C), - GPIO_FN(VI4_DATA7_A), - GPIO_FN(DU_DR7), - GPIO_FN(SDA6_C), - GPIO_FN(FSCLKST), - GPIO_IFN(SD0_CLK), - GPIO_FN(MSIOF1_SCK_E), - GPIO_FN(STP_OPWM_0_B), - GPIO_IFN(SD0_CMD), - GPIO_FN(MSIOF1_SYNC_E), - GPIO_FN(STP_IVCXO27_0_B), - GPIO_IFN(SD0_DAT0), - GPIO_FN(MSIOF1_RXD_E), - GPIO_FN(TS_SCK0_B), - GPIO_FN(STP_ISCLK_0_B), - GPIO_IFN(SD0_DAT1), - GPIO_FN(MSIOF1_TXD_E), - GPIO_FN(TS_SPSYNC0_B), - GPIO_FN(STP_ISSYNC_0_B), - - /* IPSR8 */ - GPIO_IFN(SD0_DAT2), - GPIO_FN(MSIOF1_SS1_E), - GPIO_FN(TS_SDAT0_B), - GPIO_FN(STP_ISD_0_B), - GPIO_IFN(SD0_DAT3), - GPIO_FN(MSIOF1_SS2_E), - GPIO_FN(TS_SDEN0_B), - GPIO_FN(STP_ISEN_0_B), - GPIO_IFN(SD1_CLK), - GPIO_FN(MSIOF1_SCK_G), - GPIO_FN(SIM0_CLK_A), - GPIO_IFN(SD1_CMD), - GPIO_FN(MSIOF1_SYNC_G), - GPIO_FN(NFCEx_B), - GPIO_FN(SIM0_D_A), - GPIO_FN(STP_IVCXO27_1_B), - GPIO_IFN(SD1_DAT0), - GPIO_FN(SD2_DAT4), - GPIO_FN(MSIOF1_RXD_G), - GPIO_FN(NFWPx_B), - GPIO_FN(TS_SCK1_B), - GPIO_FN(STP_ISCLK_1_B), - GPIO_IFN(SD1_DAT1), - GPIO_FN(SD2_DAT5), - GPIO_FN(MSIOF1_TXD_G), - GPIO_FN(NFDATA14_B), - GPIO_FN(TS_SPSYNC1_B), - GPIO_FN(STP_ISSYNC_1_B), - GPIO_IFN(SD1_DAT2), - GPIO_FN(SD2_DAT6), - GPIO_FN(MSIOF1_SS1_G), - GPIO_FN(NFDATA15_B), - GPIO_FN(TS_SDAT1_B), - GPIO_FN(STP_IOD_1_B), - GPIO_IFN(SD1_DAT3), - GPIO_FN(SD2_DAT7), - GPIO_FN(MSIOF1_SS2_G), - GPIO_FN(NFRBx_B), - GPIO_FN(TS_SDEN1_B), - GPIO_FN(STP_ISEN_1_B), - - /* IPSR9 */ - GPIO_IFN(SD2_CLK), - GPIO_FN(NFDATA8), - GPIO_IFN(SD2_CMD), - GPIO_FN(NFDATA9), - GPIO_IFN(SD2_DAT0), - GPIO_FN(NFDATA10), - GPIO_IFN(SD2_DAT1), - GPIO_FN(NFDATA11), - GPIO_IFN(SD2_DAT2), - GPIO_FN(NFDATA12), - GPIO_IFN(SD2_DAT3), - GPIO_FN(NFDATA13), - GPIO_IFN(SD2_DS), - GPIO_FN(NFALE), - GPIO_FN(SATA_DEVSLP_B), - GPIO_IFN(SD3_CLK), - GPIO_FN(NFWEx), - - /* IPSR10 */ - GPIO_IFN(SD3_CMD), - GPIO_FN(NFREx), - GPIO_IFN(SD3_DAT0), - GPIO_FN(NFDATA0), - GPIO_IFN(SD3_DAT1), - GPIO_FN(NFDATA1), - GPIO_IFN(SD3_DAT2), - GPIO_FN(NFDATA2), - GPIO_IFN(SD3_DAT3), - GPIO_FN(NFDATA3), - GPIO_IFN(SD3_DAT4), - GPIO_FN(SD2_CD_A), - GPIO_FN(NFDATA4), - GPIO_IFN(SD3_DAT5), - GPIO_FN(SD2_WP_A), - GPIO_FN(NFDATA5), - GPIO_IFN(SD3_DAT6), - GPIO_FN(SD3_CD), - GPIO_FN(NFDATA6), - - /* IPSR11 */ - GPIO_IFN(SD3_DAT7), - GPIO_FN(SD3_WP), - GPIO_FN(NFDATA7), - GPIO_IFN(SD3_DS), - GPIO_FN(NFCLE), - GPIO_IFN(SD0_CD), - GPIO_FN(NFDATA14_A), - GPIO_FN(SCL2_B), - GPIO_FN(SIM0_RST_A), - GPIO_IFN(SD0_WP), - GPIO_FN(NFDATA15_A), - GPIO_FN(SDA2_B), - GPIO_IFN(SD1_CD), - GPIO_FN(NFRBx_A), - GPIO_FN(SIM0_CLK_B), - GPIO_IFN(SD1_WP), - GPIO_FN(NFCEx_A), - GPIO_FN(SIM0_D_B), - GPIO_IFN(SCK0), - GPIO_FN(HSCK1_B), - GPIO_FN(MSIOF1_SS2_B), - GPIO_FN(AUDIO_CLKC_B), - GPIO_FN(SDA2_A), - GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM_0_C), - GPIO_FN(RIF0_CLK_B), - GPIO_FN(ADICHS2), - GPIO_FN(SCK5_B), - GPIO_IFN(RX0), - GPIO_FN(HRX1_B), - GPIO_FN(TS_SCK0_C), - GPIO_FN(STP_ISCLK_0_C), - GPIO_FN(RIF0_D0_B), - - /* IPSR12 */ - GPIO_IFN(TX0), - GPIO_FN(HTX1_B), - GPIO_FN(TS_SPSYNC0_C), - GPIO_FN(STP_ISSYNC_0_C), - GPIO_FN(RIF0_D1_B), - GPIO_IFN(CTS0x), - GPIO_FN(HCTS1x_B), - GPIO_FN(MSIOF1_SYNC_B), - GPIO_FN(TS_SPSYNC1_C), - GPIO_FN(STP_ISSYNC_1_C), - GPIO_FN(RIF1_SYNC_B), - GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(ADICS_SAMP), - GPIO_IFN(RTS0x_TANS), - GPIO_FN(HRTS1x_B), - GPIO_FN(MSIOF1_SS1_B), - GPIO_FN(AUDIO_CLKA_B), - GPIO_FN(SCL2_A), - GPIO_FN(STP_IVCXO27_1_C), - GPIO_FN(RIF0_SYNC_B), - GPIO_FN(ADICHS1), - GPIO_IFN(RX1_A), - GPIO_FN(HRX1_A), - GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_ISD_0_C), - GPIO_FN(RIF1_CLK_C), - GPIO_IFN(TX1_A), - GPIO_FN(HTX1_A), - GPIO_FN(TS_SDEN0_C), - GPIO_FN(STP_ISEN_0_C), - GPIO_FN(RIF1_D0_C), - GPIO_IFN(CTS1x), - GPIO_FN(HCTS1x_A), - GPIO_FN(MSIOF1_RXD_B), - GPIO_FN(TS_SDEN1_C), - GPIO_FN(STP_ISEN_1_C), - GPIO_FN(RIF1_D0_B), - GPIO_FN(ADIDATA), - GPIO_IFN(RTS1x_TANS), - GPIO_FN(HRTS1x_A), - GPIO_FN(MSIOF1_TXD_B), - GPIO_FN(TS_SDAT1_C), - GPIO_FN(STP_ISD_1_C), - GPIO_FN(RIF1_D1_B), - GPIO_FN(ADICHS0), - GPIO_IFN(SCK2), - GPIO_FN(SCIF_CLK_B), - GPIO_FN(MSIOF1_SCK_B), - GPIO_FN(TS_SCK1_C), - GPIO_FN(STP_ISCLK_1_C), - GPIO_FN(RIF1_CLK_B), - GPIO_FN(ADICLK), - - /* IPSR13 */ - GPIO_IFN(TX2_A), - GPIO_FN(SD2_CD_B), - GPIO_FN(SCL1_A), - GPIO_FN(FMCLK_A), - GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0x), - GPIO_IFN(RX2_A), - GPIO_FN(SD2_WP_B), - GPIO_FN(SDA1_A), - GPIO_FN(FMIN_A), - GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CFE_1x), - GPIO_IFN(HSCK0), - GPIO_FN(MSIOF1_SCK_D), - GPIO_FN(AUDIO_CLKB_A), - GPIO_FN(SSI_SDATA1_B), - GPIO_FN(TS_SCK0_D), - GPIO_FN(STP_ISCLK_0_D), - GPIO_FN(RIF0_CLK_C), - GPIO_FN(RX5_B), - GPIO_IFN(HRX0), - GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SSI_SDATA2_B), - GPIO_FN(TS_SDEN0_D), - GPIO_FN(STP_ISEN_0_D), - GPIO_FN(RIF0_D0_C), - GPIO_IFN(HTX0), - GPIO_FN(MSIOF1_TXD_D), - GPIO_FN(SSI_SDATA9_B), - GPIO_FN(TS_SDAT0_D), - GPIO_FN(STP_ISD_0_D), - GPIO_FN(RIF0_D1_C), - GPIO_IFN(HCTS0x), - GPIO_FN(RX2_B), - GPIO_FN(MSIOF1_SYNC_D), - GPIO_FN(SSI_SCK9_A), - GPIO_FN(TS_SPSYNC0_D), - GPIO_FN(STP_ISSYNC_0_D), - GPIO_FN(RIF0_SYNC_C), - GPIO_FN(AUDIO_CLKOUT1_A), - GPIO_IFN(HRTS0x), - GPIO_FN(TX2_B), - GPIO_FN(MSIOF1_SS1_D), - GPIO_FN(SSI_WS9_A), - GPIO_FN(STP_IVCXO27_0_D), - GPIO_FN(BPFCLK_A), - GPIO_FN(AUDIO_CLKOUT2_A), - GPIO_IFN(MSIOF0_SYNC), - GPIO_FN(AUDIO_CLKOUT_A), - GPIO_FN(TX5_B), - GPIO_FN(BPFCLK_D), - - /* IPSR14 */ - GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5_A), - GPIO_FN(NFWPx_A), - GPIO_FN(AUDIO_CLKA_C), - GPIO_FN(SSI_SCK2_A), - GPIO_FN(STP_IVCXO27_0_C), - GPIO_FN(AUDIO_CLKOUT3_A), - GPIO_FN(TCLK1_B), - GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5_A), - GPIO_FN(MSIOF1_SS2_D), - GPIO_FN(AUDIO_CLKC_A), - GPIO_FN(SSI_WS2_A), - GPIO_FN(STP_OPWM_0_D), - GPIO_FN(AUDIO_CLKOUT_D), - GPIO_FN(SPEEDIN_B), - GPIO_IFN(MLB_CLK), - GPIO_FN(MSIOF1_SCK_F), - GPIO_FN(SCL1_B), - GPIO_IFN(MLB_SIG), - GPIO_FN(RX1_B), - GPIO_FN(MSIOF1_SYNC_F), - GPIO_FN(SDA1_B), - GPIO_IFN(MLB_DAT), - GPIO_FN(TX1_B), - GPIO_FN(MSIOF1_RXD_F), - GPIO_IFN(SSI_SCK01239), - GPIO_FN(MSIOF1_TXD_F), - GPIO_FN(MOUT0), - GPIO_IFN(SSI_WS01239), - GPIO_FN(MSIOF1_SS1_F), - GPIO_FN(MOUT1), - GPIO_IFN(SSI_SDATA0), - GPIO_FN(MSIOF1_SS2_F), - GPIO_FN(MOUT2), - - /* IPSR15 */ - GPIO_IFN(SSI_SDATA1_A), - GPIO_FN(MOUT5), - GPIO_IFN(SSI_SDATA2_A), - GPIO_FN(SSI_SCK1_B), - GPIO_FN(MOUT6), - GPIO_IFN(SSI_SCK34), - GPIO_FN(MSIOF1_SS1_A), - GPIO_FN(STP_OPWM_0_A), - GPIO_IFN(SSI_WS34), - GPIO_FN(HCTS2x_A), - GPIO_FN(MSIOF1_SS2_A), - GPIO_FN(STP_IVCXO27_0_A), - GPIO_IFN(SSI_SDATA3), - GPIO_FN(HRTS2x_A), - GPIO_FN(MSIOF1_TXD_A), - GPIO_FN(TS_SCK0_A), - GPIO_FN(STP_ISCLK_0_A), - GPIO_FN(RIF0_D1_A), - GPIO_FN(RIF2_D0_A), - GPIO_IFN(SSI_SCK4), - GPIO_FN(HRX2_A), - GPIO_FN(MSIOF1_SCK_A), - GPIO_FN(TS_SDAT0_A), - GPIO_FN(STP_ISD_0_A), - GPIO_FN(RIF0_CLK_A), - GPIO_FN(RIF2_CLK_A), - GPIO_IFN(SSI_WS4), - GPIO_FN(HTX2_A), - GPIO_FN(MSIOF1_SYNC_A), - GPIO_FN(TS_SDEN0_A), - GPIO_FN(STP_ISEN_0_A), - GPIO_FN(RIF0_SYNC_A), - GPIO_FN(RIF2_SYNC_A), - GPIO_IFN(SSI_SDATA4), - GPIO_FN(HSCK2_A), - GPIO_FN(MSIOF1_RXD_A), - GPIO_FN(TS_SPSYNC0_A), - GPIO_FN(STP_ISSYNC_0_A), - GPIO_FN(RIF0_D0_A), - GPIO_FN(RIF2_D1_A), - - /* IPSR16 */ - GPIO_IFN(SSI_SCK6), - GPIO_FN(SIM0_RST_D), - GPIO_IFN(SSI_WS6), - GPIO_FN(SIM0_D_D), - GPIO_IFN(SSI_SDATA6), - GPIO_FN(SIM0_CLK_D), - GPIO_FN(SATA_DEVSLP_A), - GPIO_IFN(SSI_SCK78), - GPIO_FN(HRX2_B), - GPIO_FN(MSIOF1_SCK_C), - GPIO_FN(TS_SCK1_A), - GPIO_FN(STP_ISCLK_1_A), - GPIO_FN(RIF1_CLK_A), - GPIO_FN(RIF3_CLK_A), - GPIO_IFN(SSI_WS78), - GPIO_FN(HTX2_B), - GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDAT1_A), - GPIO_FN(STP_ISD_1_A), - GPIO_FN(RIF1_SYNC_A), - GPIO_FN(RIF3_SYNC_A), - GPIO_IFN(SSI_SDATA7), - GPIO_FN(HCTS2x_B), - GPIO_FN(MSIOF1_RXD_C), - GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_ISEN_1_A), - GPIO_FN(RIF1_D0_A), - GPIO_FN(RIF3_D0_A), - GPIO_FN(TCLK2_A), - GPIO_IFN(SSI_SDATA8), - GPIO_FN(HRTS2x_B), - GPIO_FN(MSIOF1_TXD_C), - GPIO_FN(TS_SPSYNC1_A), - GPIO_FN(STP_ISSYNC_1_A), - GPIO_FN(RIF1_D1_A), - GPIO_FN(RIF3_D1_A), - GPIO_IFN(SSI_SDATA9_A), - GPIO_FN(HSCK2_B), - GPIO_FN(MSIOF1_SS1_C), - GPIO_FN(HSCK1_A), - GPIO_FN(SSI_WS1_B), - GPIO_FN(SCK1), - GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5_A), - - /* IPSR17 */ - GPIO_IFN(AUDIO_CLKA_A), - GPIO_FN(CC5_OSCOUT), - GPIO_IFN(AUDIO_CLKB_B), - GPIO_FN(SCIF_CLK_A), - GPIO_FN(STP_IVCXO27_1_D), - GPIO_FN(REMOCON_A), - GPIO_FN(TCLK1_A), - GPIO_IFN(USB0_PWEN), - GPIO_FN(SIM0_RST_C), - GPIO_FN(TS_SCK1_D), - GPIO_FN(STP_ISCLK_1_D), - GPIO_FN(BPFCLK_B), - GPIO_FN(RIF3_CLK_B), - GPIO_FN(HSCK2_C), - GPIO_IFN(USB0_OVC), - GPIO_FN(SIM0_D_C), - GPIO_FN(TS_SDAT1_D), - GPIO_FN(STP_ISD_1_D), - GPIO_FN(RIF3_SYNC_B), - GPIO_FN(HRX2_C), - GPIO_IFN(USB1_PWEN), - GPIO_FN(SIM0_CLK_C), - GPIO_FN(SSI_SCK1_A), - GPIO_FN(TS_SCK0_E), - GPIO_FN(STP_ISCLK_0_E), - GPIO_FN(FMCLK_B), - GPIO_FN(RIF2_CLK_B), - GPIO_FN(SPEEDIN_A), - GPIO_FN(HTX2_C), - GPIO_IFN(USB1_OVC), - GPIO_FN(MSIOF1_SS2_C), - GPIO_FN(SSI_WS1_A), - GPIO_FN(TS_SDAT0_E), - GPIO_FN(STP_ISD_0_E), - GPIO_FN(FMIN_B), - GPIO_FN(RIF2_SYNC_B), - GPIO_FN(REMOCON_B), - GPIO_FN(HCTS2x_C), - GPIO_IFN(USB30_PWEN), - GPIO_FN(AUDIO_CLKOUT_B), - GPIO_FN(SSI_SCK2_B), - GPIO_FN(TS_SDEN1_D), - GPIO_FN(STP_ISEN_1_D), - GPIO_FN(STP_OPWM_0_E), - GPIO_FN(RIF3_D0_B), - GPIO_FN(TCLK2_B), - GPIO_FN(TPU0TO0), - GPIO_FN(BPFCLK_C), - GPIO_FN(HRTS2x_C), - GPIO_IFN(USB30_OVC), - GPIO_FN(AUDIO_CLKOUT1_B), - GPIO_FN(SSI_WS2_B), - GPIO_FN(TS_SPSYNC1_D), - GPIO_FN(STP_ISSYNC_1_D), - GPIO_FN(STP_IVCXO27_0_E), - GPIO_FN(RIF3_D1_B), - GPIO_FN(FSO_TOEx), - GPIO_FN(TPU0TO1), - - /* IPSR18 */ - GPIO_IFN(USB3_PWEN), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(TPU0TO2), - GPIO_FN(FMCLK_C), - GPIO_FN(FMCLK_D), - - GPIO_IFN(USB3_OVC), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), - GPIO_FN(FMIN_C), - GPIO_FN(FMIN_D), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - /* GPSR0(0xE6060100) md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0000FFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_FN, GFN_D15, - GP_0_14_FN, GFN_D14, - GP_0_13_FN, GFN_D13, - GP_0_12_FN, GFN_D12, - GP_0_11_FN, GFN_D11, - GP_0_10_FN, GFN_D10, - GP_0_9_FN, GFN_D9, - GP_0_8_FN, GFN_D8, - GP_0_7_FN, GFN_D7, - GP_0_6_FN, GFN_D6, - GP_0_5_FN, GFN_D5, - GP_0_4_FN, GFN_D4, - GP_0_3_FN, GFN_D3, - GP_0_2_FN, GFN_D2, - GP_0_1_FN, GFN_D1, - GP_0_0_FN, GFN_D0 } - }, - /* GPSR1(0xE6060104) is md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0EFFFFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_FN, GFN_CLKOUT, - GP_1_27_FN, GFN_EX_WAIT0_A, - GP_1_26_FN, GFN_WE1x, - GP_1_25_FN, GFN_WE0x, - GP_1_24_FN, GFN_RD_WRx, - GP_1_23_FN, GFN_RDx, - GP_1_22_FN, GFN_BSx, - GP_1_21_FN, GFN_CS1x_A26, - GP_1_20_FN, GFN_CS0x, - GP_1_19_FN, GFN_A19, - GP_1_18_FN, GFN_A18, - GP_1_17_FN, GFN_A17, - GP_1_16_FN, GFN_A16, - GP_1_15_FN, GFN_A15, - GP_1_14_FN, GFN_A14, - GP_1_13_FN, GFN_A13, - GP_1_12_FN, GFN_A12, - GP_1_11_FN, GFN_A11, - GP_1_10_FN, GFN_A10, - GP_1_9_FN, GFN_A9, - GP_1_8_FN, GFN_A8, - GP_1_7_FN, GFN_A7, - GP_1_6_FN, GFN_A6, - GP_1_5_FN, GFN_A5, - GP_1_4_FN, GFN_A4, - GP_1_3_FN, GFN_A3, - GP_1_2_FN, GFN_A2, - GP_1_1_FN, GFN_A1, - GP_1_0_FN, GFN_A0 } - }, - /* GPSR2(0xE6060108) is md[3:1] controls */ - /* md[3:1] .. 0 : 0x000003C0 */ - /* .. other : 0x00000200 */ - { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, - GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, - GP_2_12_FN, GFN_AVB_LINK, - GP_2_11_FN, GFN_AVB_PHY_INT, - GP_2_10_FN, GFN_AVB_MAGIC, - GP_2_9_FN, GFN_AVB_MDC, - GP_2_8_FN, GFN_PWM2_A, - GP_2_7_FN, GFN_PWM1_A, - GP_2_6_FN, GFN_PWM0, - GP_2_5_FN, GFN_IRQ5, - GP_2_4_FN, GFN_IRQ4, - GP_2_3_FN, GFN_IRQ3, - GP_2_2_FN, GFN_IRQ2, - GP_2_1_FN, GFN_IRQ1, - GP_2_0_FN, GFN_IRQ0 } - }, - - /* GPSR3 */ - { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_FN, GFN_SD1_WP, - GP_3_14_FN, GFN_SD1_CD, - GP_3_13_FN, GFN_SD0_WP, - GP_3_12_FN, GFN_SD0_CD, - GP_3_11_FN, GFN_SD1_DAT3, - GP_3_10_FN, GFN_SD1_DAT2, - GP_3_9_FN, GFN_SD1_DAT1, - GP_3_8_FN, GFN_SD1_DAT0, - GP_3_7_FN, GFN_SD1_CMD, - GP_3_6_FN, GFN_SD1_CLK, - GP_3_5_FN, GFN_SD0_DAT3, - GP_3_4_FN, GFN_SD0_DAT2, - GP_3_3_FN, GFN_SD0_DAT1, - GP_3_2_FN, GFN_SD0_DAT0, - GP_3_1_FN, GFN_SD0_CMD, - GP_3_0_FN, GFN_SD0_CLK } - }, - /* GPSR4 */ - { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_FN, GFN_SD3_DS, - GP_4_16_FN, GFN_SD3_DAT7, - - GP_4_15_FN, GFN_SD3_DAT6, - GP_4_14_FN, GFN_SD3_DAT5, - GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, GFN_SD3_DAT3, - GP_4_11_FN, GFN_SD3_DAT2, - GP_4_10_FN, GFN_SD3_DAT1, - GP_4_9_FN, GFN_SD3_DAT0, - GP_4_8_FN, GFN_SD3_CMD, - GP_4_7_FN, GFN_SD3_CLK, - GP_4_6_FN, GFN_SD2_DS, - GP_4_5_FN, GFN_SD2_DAT3, - GP_4_4_FN, GFN_SD2_DAT2, - GP_4_3_FN, GFN_SD2_DAT1, - GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, GFN_SD2_CMD, - GP_4_0_FN, GFN_SD2_CLK } - }, - /* GPSR5 */ - { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GFN_MLB_DAT, - GP_5_24_FN, GFN_MLB_SIG, - GP_5_23_FN, GFN_MLB_CLK, - GP_5_22_FN, FN_MSIOF0_RXD, - GP_5_21_FN, GFN_MSIOF0_SS2, - GP_5_20_FN, FN_MSIOF0_TXD, - GP_5_19_FN, GFN_MSIOF0_SS1, - GP_5_18_FN, GFN_MSIOF0_SYNC, - GP_5_17_FN, FN_MSIOF0_SCK, - GP_5_16_FN, GFN_HRTS0x, - GP_5_15_FN, GFN_HCTS0x, - GP_5_14_FN, GFN_HTX0, - GP_5_13_FN, GFN_HRX0, - GP_5_12_FN, GFN_HSCK0, - GP_5_11_FN, GFN_RX2_A, - GP_5_10_FN, GFN_TX2_A, - GP_5_9_FN, GFN_SCK2, - GP_5_8_FN, GFN_RTS1x_TANS, - GP_5_7_FN, GFN_CTS1x, - GP_5_6_FN, GFN_TX1_A, - GP_5_5_FN, GFN_RX1_A, - GP_5_4_FN, GFN_RTS0x_TANS, - GP_5_3_FN, GFN_CTS0x, - GP_5_2_FN, GFN_TX0, - GP_5_1_FN, GFN_RX0, - GP_5_0_FN, GFN_SCK0 } - }, - /* GPSR6 */ - { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_USB3_OVC, - GP_6_30_FN, GFN_USB3_PWEN, - GP_6_29_FN, GFN_USB30_OVC, - GP_6_28_FN, GFN_USB30_PWEN, - GP_6_27_FN, GFN_USB1_OVC, - GP_6_26_FN, GFN_USB1_PWEN, - GP_6_25_FN, GFN_USB0_OVC, - GP_6_24_FN, GFN_USB0_PWEN, - GP_6_23_FN, GFN_AUDIO_CLKB_B, - GP_6_22_FN, GFN_AUDIO_CLKA_A, - GP_6_21_FN, GFN_SSI_SDATA9_A, - GP_6_20_FN, GFN_SSI_SDATA8, - GP_6_19_FN, GFN_SSI_SDATA7, - GP_6_18_FN, GFN_SSI_WS78, - GP_6_17_FN, GFN_SSI_SCK78, - GP_6_16_FN, GFN_SSI_SDATA6, - GP_6_15_FN, GFN_SSI_WS6, - GP_6_14_FN, GFN_SSI_SCK6, - GP_6_13_FN, FN_SSI_SDATA5, - GP_6_12_FN, FN_SSI_WS5, - GP_6_11_FN, FN_SSI_SCK5, - GP_6_10_FN, GFN_SSI_SDATA4, - GP_6_9_FN, GFN_SSI_WS4, - GP_6_8_FN, GFN_SSI_SCK4, - GP_6_7_FN, GFN_SSI_SDATA3, - GP_6_6_FN, GFN_SSI_WS34, - GP_6_5_FN, GFN_SSI_SCK34, - GP_6_4_FN, GFN_SSI_SDATA2_A, - GP_6_3_FN, GFN_SSI_SDATA1_A, - GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS01239, - GP_6_0_FN, GFN_SSI_SCK01239 } - }, - /* GPSR7 */ - { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_7_3_FN, FN_HDMI1_CEC, - GP_7_2_FN, FN_HDMI0_CEC, - GP_7_1_FN, FN_AVS2, - GP_7_0_FN, FN_AVS1 } - }, - { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR0_31_28 [4] */ - IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_27_24 [4] */ - IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_23_20 [4] */ - IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_19_16 [4] */ - IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, FN_FSCLKST2x_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_15_12 [4] */ - IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_11_8 [4] */ - IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_3_0 [4] */ - IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR1_31_28 [4] */ - IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, - FN_VI4_DATA8, 0, FN_DU_DB0, 0, - 0, FN_PWM3_A, 0, 0, - 0, 0, 0, 0, - /* IPSR1_27_24 [4] */ - IFN_PWM2_A, 0, 0, FN_HTX3_D, - 0, 0, 0, 0, - 0, FN_IETX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, 0, FN_HRX3_D, - FN_VI4_DATA7_B, 0, 0, 0, - 0, FN_IERX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, - FN_VI4_DATA6_B, 0, 0, 0, - 0, FN_IECLK_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E, - 0, FN_PWM6_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, - 0, FN_PWM5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, - 0, FN_PWM4_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_3_0 [4] */ - IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, - 0, FN_PWM3_B, 0, 0, - 0, 0, 0, 0 - } - }, - { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR2_31_28 [4] */ - IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, - 0, 0, 0, FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR2_27_24 [4] */ - IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, - FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_23_20 [4] */ - IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, - FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_19_16 [4] */ - IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, - FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_15_12 [4] */ - IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, - FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_11_8 [4] */ - IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, - FN_VI4_DATA11, 0, FN_DU_DB3, 0, - 0, FN_PWM6_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_7_4 [4] */ - IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, - FN_VI4_DATA10, 0, FN_DU_DB2, 0, - 0, FN_PWM5_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_3_0 [4] */ - IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, - FN_VI4_DATA9, 0, FN_DU_DB1, 0, - 0, FN_PWM4_A, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR3_31_28 [4] */ - IFN_A16, FN_LCDOUT8, 0, 0, - FN_VI4_FIELD, 0, FN_DU_DG0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_27_24 [4] */ - IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, - FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_23_20 [4] */ - IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, - FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_19_16 [4] */ - IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, - FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_15_12 [4] */ - IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, - FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_11_8 [4] */ - IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, - FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0, - 0, 0, 0, 0, - /* IPSR3_7_4 [4] */ - IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, - 0, FN_VI5_HSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_3_0 [4] */ - IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, - 0, FN_VI5_VSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR4_31_28 [4] */ - IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, - FN_HTX3_A, 0, 0, 0, - FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_27_24 [4] */ - IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, - FN_HRX3_A, 0, 0, 0, - FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_23_20 [4] */ - IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, - FN_HSCK3, 0, 0, 0, - FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, - 0, 0, 0, 0, - /* IPSR4_19_16 [4] */ - IFN_CS1x_A26, 0, 0, 0, - 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_15_12 [4] */ - IFN_CS0x, 0, 0, 0, - 0, FN_VI5_CLKENB, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_11_8 [4] */ - IFN_A19, FN_LCDOUT11, 0, 0, - FN_VI4_CLKENB, 0, FN_DU_DG3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_7_4 [4] */ - IFN_A18, FN_LCDOUT10, 0, 0, - FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_3_0 [4] */ - IFN_A17, FN_LCDOUT9, 0, 0, - FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR5_31_28 [4] */ - IFN_D4, FN_MSIOF2_SCK_B, 0, 0, - FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_27_24 [4] */ - IFN_D3, 0, FN_MSIOF3_TXD_A, 0, - FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_23_20 [4] */ - IFN_D2, 0, FN_MSIOF3_RXD_A, 0, - FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_19_16 [4] */ - IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, - FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_15_12 [4] */ - IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, - FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_11_8 [4] */ - IFN_EX_WAIT0_A, FN_QCLK, 0, 0, - FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_7_4 [4] */ - IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, - FN_HRTS3x, 0, 0, FN_SDA6_B, - FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, - 0, 0, 0, 0, - /* IPSR5_3_0 [4] */ - IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, - FN_HCTS3x, 0, 0, FN_SCL6_B, - FN_CAN_CLK, 0, FN_IECLK_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR6_31_28 [4] */ - IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, - FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_27_24 [4] */ - IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, - FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_23_20 [4] */ - IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, - FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_19_16 [4] */ - IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, - FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_15_12 [4] */ - IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, - FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_11_8 [4] */ - IFN_D7, FN_MSIOF2_TXD_B, 0, 0, - FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_7_4 [4] */ - IFN_D6, FN_MSIOF2_RXD_B, 0, 0, - FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_3_0 [4] */ - IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, - FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR7_31_28 [4] */ - IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, - 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_27_24 [4] */ - IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, - 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_23_20 [4] */ - IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, - 0, 0, FN_STP_IVCXO27_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_19_16 [4] */ - IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, - 0, 0, FN_STP_OPWM_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_15_12 [4] */ - FN_FSCLKST, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_11_8 [4] */ - IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, - FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_7_4 [4] */ - IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, - FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_3_0 [4] */ - IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, - FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B, - 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B, - 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B, - 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B, - 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B, - 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_11_8 [4] */ - IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, - 0, FN_SIM0_CLK_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_7_4 [4] */ - IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, - 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_3_0 [4] */ - IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, - 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR9_31_28 [4] */ - IFN_SD3_CLK, 0, FN_NFWEx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_27_24 [4] */ - IFN_SD2_DS, 0, FN_NFALE, 0, - 0, 0, 0, 0, - FN_SATA_DEVSLP_B, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_23_20 [4] */ - IFN_SD2_DAT3, 0, FN_NFDATA13, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_19_16 [4] */ - IFN_SD2_DAT2, 0, FN_NFDATA12, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_15_12 [4] */ - IFN_SD2_DAT1, 0, FN_NFDATA11, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_11_8 [4] */ - IFN_SD2_DAT0, 0, FN_NFDATA10, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_7_4 [4] */ - IFN_SD2_CMD, 0, FN_NFDATA9, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_3_0 [4] */ - IFN_SD2_CLK, 0, FN_NFDATA8, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR10_31_28 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_27_24 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_23_20 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_19_16 [4] */ - IFN_SD3_DAT3, 0, FN_NFDATA3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_15_12 [4] */ - IFN_SD3_DAT2, 0, FN_NFDATA2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_11_8 [4] */ - IFN_SD3_DAT1, 0, FN_NFDATA1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_7_4 [4] */ - IFN_SD3_DAT0, 0, FN_NFDATA0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_3_0 [4] */ - IFN_SD3_CMD, 0, FN_NFREx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR11_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B, - FN_ADICHS2, FN_SCK5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ - IFN_SD1_WP, 0, FN_NFCEx_A, 0, - 0, FN_SIM0_D_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_19_16 [4] */ - IFN_SD1_CD, 0, FN_NFRBx_A, 0, - 0, FN_SIM0_CLK_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ - IFN_SD0_WP, 0, FN_NFDATA15_A, 0, - FN_SDA2_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ - IFN_SD0_CD, 0, FN_NFDATA14_A, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ - IFN_SD3_DS, 0, FN_NFCLE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ - IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, - 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, - 0, FN_ADICLK, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ - IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, - 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, - 0, FN_ADICHS0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ - IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, - 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, - 0, FN_ADIDATA, 0, 0, - 0, 0, 0, 0, - /* IPSR12_19_16 [4] */ - IFN_TX1_A, FN_HTX1_A, 0, 0, - 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ - IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ - IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, - FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, - 0, FN_ADICHS1, 0, 0, - 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ - IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, - 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, - 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ - IFN_TX0, FN_HTX1_B, 0, 0, - 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ - IFN_MSIOF0_SYNC, 0, 0, 0, - 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, - 0, FN_BPFCLK_D, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, - FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ - IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, - FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ - IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ - IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, 0, FN_RX5_B, 0, - 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CFE_1x, 0, 0, - 0, 0, 0, 0, - /* IPSR13_3_0 [4] */ - IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0x, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ - IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, - 0, 0, 0, FN_MOUT2, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ - IFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, 0, FN_MOUT1, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ - IFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0, - 0, 0, 0, FN_MOUT0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ - IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ - IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, - FN_SDA1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ - IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, - FN_SCL1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, - FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - 0, 0, 0, 0, - /* IPSR14_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, - FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ - IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, - 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, - FN_RIF2_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ - IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, - 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ - IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, - 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, - FN_RIF2_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_19_16 [4] */ - IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, - 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, - FN_RIF2_D0_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ - IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, - 0, 0, FN_STP_IVCXO27_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ - IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, - 0, 0, FN_STP_OPWM_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_SDATA2_A, 0, 0, 0, - FN_SSI_SCK1_B, 0, 0, FN_MOUT6, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SDATA1_A, 0, 0, 0, - 0, 0, 0, FN_MOUT5, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ - IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, - 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_RIF3_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ - IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A, - FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - 0, 0, 0, 0, - /* IPSR16_19_16 [4] */ - IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ - IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, - 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, - FN_RIF3_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ - IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, 0, 0, - FN_SATA_DEVSLP_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ - IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ - IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR17_31_28 [4] */ - IFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1, - 0, 0, 0, 0, - /* IPSR17_27_24 [4] */ - IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, - FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, - /* IPSR17_23_20 [4] */ - IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, - FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, - 0, FN_HCTS2x_C, 0, 0, - /* IPSR17_19_16 [4] */ - IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, - FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, - 0, FN_HTX2_C, 0, 0, - /* IPSR17_15_12 [4] */ - IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, - 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, 0, - 0, FN_HRX2_C, 0, 0, - /* IPSR17_11_8 [4] */ - IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, - 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, 0, 0, 0, - 0, FN_HSCK2_C, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, 0, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_AUDIO_CLKA_A, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, FN_CC5_OSCOUT, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 4, 4) { - /* reserved [31..24] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [23..16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* IPSR18_7_4 [4] */ - IFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, - FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - FN_FMIN_C, FN_FMIN_D, 0, 0, - /* IPSR18_3_0 [4] */ - IFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, - FN_RIF2_D0_B, 0, 0, FN_TPU0TO2, - FN_FMCLK_C, FN_FMCLK_D, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) { - /* MOD_SEL0 */ - /* sel_msiof3[3](0,1,2,3,4) */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, 0, - 0, 0, - /* sel_msiof2[2](0,1,2,3) */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* sel_msiof1[3](0,1,2,3,4,5,6) */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, 0, - /* sel_lbsc[1](0,1) */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* sel_iebus[1](0,1) */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* sel_i2c2[1](0,1) */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* sel_i2c1[1](0,1) */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* sel_hscif4[1](0,1) */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* sel_hscif3[2](0,1,2,3) */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* sel_hscif1[1](0,1) */ - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* reserved[1] */ - 0, 0, - /* sel_hscif2[2](0,1,2) */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, 0, - /* sel_etheravb[1](0,1) */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* sel_drif3[1](0,1) */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* sel_drif2[1](0,1) */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* sel_drif1[2](0,1,2) */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, 0, - /* sel_drif0[2](0,1,2) */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, 0, - /* sel_canfd0[1](0,1) */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* sel_adg_a[2](0,1,2) */ - FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, - FN_SEL_ADG_A_2, 0, - /* reserved[3]*/ - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, - 2, 3, 1, 2, - 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* sel_tsif1[2](0,1,2,3) */ - FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, - /* sel_tsif0[3](0,1,2,3,4) */ - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, 0, - 0, 0, - /* sel_timer_tmu1[1](0,1) */ - FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, - /* sel_ssp1_1[2](0,1,2,3) */ - FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, - /* sel_ssp1_0[3](0,1,2,3,4) */ - FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, 0, - 0, 0, - /* sel_ssi1[1](0,1) */ - FN_SEL_SSI_0, FN_SEL_SSI_1, - /* sel_speed_pulse_if[1](0,1) */ - FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, - /* sel_simcard[2](0,1,2,3) */ - FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, - /* sel_sdhi2[1](0,1) */ - FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, - /* sel_scif4[2](0,1,2) */ - FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, 0, - /* sel_scif3[1](0,1) */ - FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, - /* sel_scif2[1](0,1) */ - FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, - /* sel_scif1[1](0,1) */ - FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, - /* sel_scif[1](0,1) */ - FN_SEL_SCIF_0, FN_SEL_SCIF_1, - /* sel_remocon[1](0,1) */ - FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, - /* reserved[8..7] */ - 0, 0, - 0, 0, - /* sel_rcan0[1](0,1) */ - FN_SEL_RCAN_0, FN_SEL_RCAN_1, - /* sel_pwm6[1](0,1) */ - FN_SEL_PWM6_0, FN_SEL_PWM6_1, - /* sel_pwm5[1](0,1) */ - FN_SEL_PWM5_0, FN_SEL_PWM5_1, - /* sel_pwm4[1](0,1) */ - FN_SEL_PWM4_0, FN_SEL_PWM4_1, - /* sel_pwm3[1](0,1) */ - FN_SEL_PWM3_0, FN_SEL_PWM3_1, - /* sel_pwm2[1](0,1) */ - FN_SEL_PWM2_0, FN_SEL_PWM2_1, - /* sel_pwm1[1](0,1) */ - FN_SEL_PWM1_0, FN_SEL_PWM1_1, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* i2c_sel_5[1](0,1) */ - FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, - /* i2c_sel_3[1](0,1) */ - FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, - /* i2c_sel_0[1](0,1) */ - FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, - /* sel_fm[2](0,1,2,3) */ - FN_SEL_FM_0, FN_SEL_FM_1, - FN_SEL_FM_2, FN_SEL_FM_3, - /* sel_scif5[1](0,1) */ - FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - /* sel_i2c6[3](0,1,2) */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, 0, - /* sel_ndfc[1](0,1) */ - FN_SEL_NDFC_0, FN_SEL_NDFC_1, - /* sel_ssi2[1](0,1) */ - FN_SEL_SSI2_0, FN_SEL_SSI2_1, - /* sel_ssi9[1](0,1) */ - FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* sel_timer_tmu2[1](0,1) */ - FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, - /* sel_adg_b[1](0,1) */ - FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, - /* sel_adg_c[1](0,1) */ - FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, - /* reserved[16..16] */ - 0, 0, - /* reserved[15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved[7..1] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* sel_vin4[1](0,1) */ - FN_SEL_VIN4_0, FN_SEL_VIN4_1, - } - }, - { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_IN, GP_0_15_OUT, - GP_0_14_IN, GP_0_14_OUT, - GP_0_13_IN, GP_0_13_OUT, - GP_0_12_IN, GP_0_12_OUT, - GP_0_11_IN, GP_0_11_OUT, - GP_0_10_IN, GP_0_10_OUT, - GP_0_9_IN, GP_0_9_OUT, - GP_0_8_IN, GP_0_8_OUT, - GP_0_7_IN, GP_0_7_OUT, - GP_0_6_IN, GP_0_6_OUT, - GP_0_5_IN, GP_0_5_OUT, - GP_0_4_IN, GP_0_4_OUT, - GP_0_3_IN, GP_0_3_OUT, - GP_0_2_IN, GP_0_2_OUT, - GP_0_1_IN, GP_0_1_OUT, - GP_0_0_IN, GP_0_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_IN, GP_1_28_OUT, - GP_1_27_IN, GP_1_27_OUT, - GP_1_26_IN, GP_1_26_OUT, - GP_1_25_IN, GP_1_25_OUT, - GP_1_24_IN, GP_1_24_OUT, - GP_1_23_IN, GP_1_23_OUT, - GP_1_22_IN, GP_1_22_OUT, - GP_1_21_IN, GP_1_21_OUT, - GP_1_20_IN, GP_1_20_OUT, - GP_1_19_IN, GP_1_19_OUT, - GP_1_18_IN, GP_1_18_OUT, - GP_1_17_IN, GP_1_17_OUT, - GP_1_16_IN, GP_1_16_OUT, - GP_1_15_IN, GP_1_15_OUT, - GP_1_14_IN, GP_1_14_OUT, - GP_1_13_IN, GP_1_13_OUT, - GP_1_12_IN, GP_1_12_OUT, - GP_1_11_IN, GP_1_11_OUT, - GP_1_10_IN, GP_1_10_OUT, - GP_1_9_IN, GP_1_9_OUT, - GP_1_8_IN, GP_1_8_OUT, - GP_1_7_IN, GP_1_7_OUT, - GP_1_6_IN, GP_1_6_OUT, - GP_1_5_IN, GP_1_5_OUT, - GP_1_4_IN, GP_1_4_OUT, - GP_1_3_IN, GP_1_3_OUT, - GP_1_2_IN, GP_1_2_OUT, - GP_1_1_IN, GP_1_1_OUT, - GP_1_0_IN, GP_1_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_IN, GP_2_14_OUT, - GP_2_13_IN, GP_2_13_OUT, - GP_2_12_IN, GP_2_12_OUT, - GP_2_11_IN, GP_2_11_OUT, - GP_2_10_IN, GP_2_10_OUT, - GP_2_9_IN, GP_2_9_OUT, - GP_2_8_IN, GP_2_8_OUT, - GP_2_7_IN, GP_2_7_OUT, - GP_2_6_IN, GP_2_6_OUT, - GP_2_5_IN, GP_2_5_OUT, - GP_2_4_IN, GP_2_4_OUT, - GP_2_3_IN, GP_2_3_OUT, - GP_2_2_IN, GP_2_2_OUT, - GP_2_1_IN, GP_2_1_OUT, - GP_2_0_IN, GP_2_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_IN, GP_3_15_OUT, - GP_3_14_IN, GP_3_14_OUT, - GP_3_13_IN, GP_3_13_OUT, - GP_3_12_IN, GP_3_12_OUT, - GP_3_11_IN, GP_3_11_OUT, - GP_3_10_IN, GP_3_10_OUT, - GP_3_9_IN, GP_3_9_OUT, - GP_3_8_IN, GP_3_8_OUT, - GP_3_7_IN, GP_3_7_OUT, - GP_3_6_IN, GP_3_6_OUT, - GP_3_5_IN, GP_3_5_OUT, - GP_3_4_IN, GP_3_4_OUT, - GP_3_3_IN, GP_3_3_OUT, - GP_3_2_IN, GP_3_2_OUT, - GP_3_1_IN, GP_3_1_OUT, - GP_3_0_IN, GP_3_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_IN, GP_4_17_OUT, - GP_4_16_IN, GP_4_16_OUT, - - GP_4_15_IN, GP_4_15_OUT, - GP_4_14_IN, GP_4_14_OUT, - GP_4_13_IN, GP_4_13_OUT, - GP_4_12_IN, GP_4_12_OUT, - GP_4_11_IN, GP_4_11_OUT, - GP_4_10_IN, GP_4_10_OUT, - GP_4_9_IN, GP_4_9_OUT, - GP_4_8_IN, GP_4_8_OUT, - GP_4_7_IN, GP_4_7_OUT, - GP_4_6_IN, GP_4_6_OUT, - GP_4_5_IN, GP_4_5_OUT, - GP_4_4_IN, GP_4_4_OUT, - GP_4_3_IN, GP_4_3_OUT, - GP_4_2_IN, GP_4_2_OUT, - GP_4_1_IN, GP_4_1_OUT, - GP_4_0_IN, GP_4_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_IN, GP_5_25_OUT, - GP_5_24_IN, GP_5_24_OUT, - - GP_5_23_IN, GP_5_23_OUT, - GP_5_22_IN, GP_5_22_OUT, - GP_5_21_IN, GP_5_21_OUT, - GP_5_20_IN, GP_5_20_OUT, - GP_5_19_IN, GP_5_19_OUT, - GP_5_18_IN, GP_5_18_OUT, - GP_5_17_IN, GP_5_17_OUT, - GP_5_16_IN, GP_5_16_OUT, - - GP_5_15_IN, GP_5_15_OUT, - GP_5_14_IN, GP_5_14_OUT, - GP_5_13_IN, GP_5_13_OUT, - GP_5_12_IN, GP_5_12_OUT, - GP_5_11_IN, GP_5_11_OUT, - GP_5_10_IN, GP_5_10_OUT, - GP_5_9_IN, GP_5_9_OUT, - GP_5_8_IN, GP_5_8_OUT, - GP_5_7_IN, GP_5_7_OUT, - GP_5_6_IN, GP_5_6_OUT, - GP_5_5_IN, GP_5_5_OUT, - GP_5_4_IN, GP_5_4_OUT, - GP_5_3_IN, GP_5_3_OUT, - GP_5_2_IN, GP_5_2_OUT, - GP_5_1_IN, GP_5_1_OUT, - GP_5_0_IN, GP_5_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { - GP_INOUTSEL(6) - } - }, - { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - /* use OUTDT registers? */ - { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, - GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, - GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, - GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } - }, - { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, GP_1_28_DATA, - GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, - GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, - GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, - GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, - GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, - GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, - GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } - }, - { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, - GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, - GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, - GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } - }, - { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, - GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, - GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, - GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } - }, - { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, - GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, - GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, - GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, - GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } - }, - { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { - 0, 0, 0, 0, - 0, 0, GP_5_25_DATA, GP_5_24_DATA, - GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, - GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, - GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, - GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, - GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, - GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } - }, - { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { - GP_INDT(6) } - }, - { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } - }, - { }, -}; - - -static struct pinmux_info r8a7795_pinmux_info = { - .name = "r8a7795_pfc", - - .unlock_reg = 0xe6060000, /* PMMR */ - - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_FMIN_D, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), -}; - -void r8a7795_pinmux_init(void) -{ - register_pinmux(&r8a7795_pinmux_info); -} diff --git a/arch/arm/mach-rmobile/pfc-r8a7796.c b/arch/arm/mach-rmobile/pfc-r8a7796.c deleted file mode 100644 index f734f96dd08..00000000000 --- a/arch/arm/mach-rmobile/pfc-r8a7796.c +++ /dev/null @@ -1,5253 +0,0 @@ -/* - * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7796.c - * This file is r8a7796 processor support - PFC hardware block. - * - * Copyright (C) 2016 Renesas Electronics Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <sh_pfc.h> -#include <asm/gpio.h> - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#define CPU_32_PORT_29(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), \ - PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT_26(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), \ - PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##25, sfx) - -#define CPU_32_PORT_18(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##17, sfx) - -#define CPU_32_PORT_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), \ - PORT_1(fn, pfx##15, sfx) - -#define CPU_32_PORT_15(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), \ - PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx) - -#define CPU_32_PORT_4(fn, pfx, sfx) \ - PORT_1(fn, pfx##0, sfx), \ - PORT_1(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##3, sfx) - - -/* --gen3-- */ -/* GP_0_0_DATA -> GP_7_4_DATA */ -/* except for GP0[16] - [31], - GP1[28] - [31], - GP2[15] - [31], - GP3[16] - [31], - GP4[18] - [31], - GP5[26] - [31], - GP7[4] - [31] */ - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT_16(fn, pfx##_0_, sfx), \ - CPU_32_PORT_29(fn, pfx##_1_, sfx), \ - CPU_32_PORT_15(fn, pfx##_2_, sfx), \ - CPU_32_PORT_16(fn, pfx##_3_, sfx), \ - CPU_32_PORT_18(fn, pfx##_4_, sfx), \ - CPU_32_PORT_26(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT_4(fn, pfx##_7_, sfx) - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - GP_ALL(DATA), - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - GP_ALL(IN), - PINMUX_INPUT_END, - - PINMUX_OUTPUT_BEGIN, - GP_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - GP_ALL(FN), - - /* GPSR0 */ - GFN_D15, - GFN_D14, - GFN_D13, - GFN_D12, - GFN_D11, - GFN_D10, - GFN_D9, - GFN_D8, - GFN_D7, - GFN_D6, - GFN_D5, - GFN_D4, - GFN_D3, - GFN_D2, - GFN_D1, - GFN_D0, - - /* GPSR1 */ - GFN_CLKOUT, - GFN_EX_WAIT0_A, - GFN_WE1x, - GFN_WE0x, - GFN_RD_WRx, - GFN_RDx, - GFN_BSx, - GFN_CS1x_A26, - GFN_CS0x, - GFN_A19, - GFN_A18, - GFN_A17, - GFN_A16, - GFN_A15, - GFN_A14, - GFN_A13, - GFN_A12, - GFN_A11, - GFN_A10, - GFN_A9, - GFN_A8, - GFN_A7, - GFN_A6, - GFN_A5, - GFN_A4, - GFN_A3, - GFN_A2, - GFN_A1, - GFN_A0, - - /* GPSR2 */ - GFN_AVB_AVTP_CAPTURE_A, - GFN_AVB_AVTP_MATCH_A, - GFN_AVB_LINK, - GFN_AVB_PHY_INT, - GFN_AVB_MAGIC, - GFN_AVB_MDC, - GFN_PWM2_A, - GFN_PWM1_A, - GFN_PWM0, - GFN_IRQ5, - GFN_IRQ4, - GFN_IRQ3, - GFN_IRQ2, - GFN_IRQ1, - GFN_IRQ0, - - /* GPSR3 */ - GFN_SD1_WP, - GFN_SD1_CD, - GFN_SD0_WP, - GFN_SD0_CD, - GFN_SD1_DAT3, - GFN_SD1_DAT2, - GFN_SD1_DAT1, - GFN_SD1_DAT0, - GFN_SD1_CMD, - GFN_SD1_CLK, - GFN_SD0_DAT3, - GFN_SD0_DAT2, - GFN_SD0_DAT1, - GFN_SD0_DAT0, - GFN_SD0_CMD, - GFN_SD0_CLK, - - /* GPSR4 */ - GFN_SD3_DS, - GFN_SD3_DAT7, - GFN_SD3_DAT6, - GFN_SD3_DAT5, - GFN_SD3_DAT4, - FN_SD3_DAT3, - FN_SD3_DAT2, - FN_SD3_DAT1, - FN_SD3_DAT0, - FN_SD3_CMD, - FN_SD3_CLK, - GFN_SD2_DS, - GFN_SD2_DAT3, - GFN_SD2_DAT2, - GFN_SD2_DAT1, - GFN_SD2_DAT0, - FN_SD2_CMD, - GFN_SD2_CLK, - - /* GPSR5 */ - GFN_MLB_DAT, - GFN_MLB_SIG, - GFN_MLB_CLK, - FN_MSIOF0_RXD, - GFN_MSIOF0_SS2, - FN_MSIOF0_TXD, - GFN_MSIOF0_SS1, - GFN_MSIOF0_SYNC, - FN_MSIOF0_SCK, - GFN_HRTS0x, - GFN_HCTS0x, - GFN_HTX0, - GFN_HRX0, - GFN_HSCK0, - GFN_RX2_A, - GFN_TX2_A, - GFN_SCK2, - GFN_RTS1x_TANS, - GFN_CTS1x, - GFN_TX1_A, - GFN_RX1_A, - GFN_RTS0x_TANS, - GFN_CTS0x, - GFN_TX0, - GFN_RX0, - GFN_SCK0, - - /* GPSR6 */ - GFN_GP6_30, - GFN_GP6_31, - GFN_USB30_OVC, - GFN_USB30_PWEN, - GFN_USB1_OVC, - GFN_USB1_PWEN, - GFN_USB0_OVC, - GFN_USB0_PWEN, - GFN_AUDIO_CLKB_B, - GFN_AUDIO_CLKA_A, - GFN_SSI_SDATA9_A, - GFN_SSI_SDATA8, - GFN_SSI_SDATA7, - GFN_SSI_WS78, - GFN_SSI_SCK78, - GFN_SSI_SDATA6, - GFN_SSI_WS6, - GFN_SSI_SCK6, - FN_SSI_SDATA5, - FN_SSI_WS5, - FN_SSI_SCK5, - GFN_SSI_SDATA4, - GFN_SSI_WS4, - GFN_SSI_SCK4, - GFN_SSI_SDATA3, - GFN_SSI_WS34, - GFN_SSI_SCK34, - GFN_SSI_SDATA2_A, - GFN_SSI_SDATA1_A, - GFN_SSI_SDATA0, - GFN_SSI_WS01239, - GFN_SSI_SCK01239, - - /* GPSR7 */ - FN_HDMI1_CEC, - FN_HDMI0_CEC, - FN_AVS2, - FN_AVS1, - - /* IPSR0 */ - IFN_AVB_MDC, - FN_MSIOF2_SS2_C, - IFN_AVB_MAGIC, - FN_MSIOF2_SS1_C, - FN_SCK4_A, - IFN_AVB_PHY_INT, - FN_MSIOF2_SYNC_C, - FN_RX4_A, - IFN_AVB_LINK, - FN_MSIOF2_SCK_C, - FN_TX4_A, - IFN_AVB_AVTP_MATCH_A, - FN_MSIOF2_RXD_C, - FN_CTS4x_A, - IFN_AVB_AVTP_CAPTURE_A, - FN_MSIOF2_TXD_C, - FN_RTS4x_TANS_A, - IFN_IRQ0, - FN_QPOLB, - FN_DU_CDE, - FN_VI4_DATA0_B, - FN_CAN0_TX_B, - FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - IFN_IRQ1, - FN_QPOLA, - FN_DU_DISP, - FN_VI4_DATA1_B, - FN_CAN0_RX_B, - FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - - /* IPSR1 */ - IFN_IRQ2, - FN_QCPV_QDE, - FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, - FN_MSIOF3_SYNC_E, - FN_PWM3_B, - IFN_IRQ3, - FN_QSTVB_QVE, - FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, - FN_MSIOF3_SCK_E, - FN_PWM4_B, - IFN_IRQ4, - FN_QSTH_QHS, - FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, - FN_MSIOF3_RXD_E, - FN_PWM5_B, - IFN_IRQ5, - FN_QSTB_QHE, - FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, - FN_MSIOF3_TXD_E, - FN_PWM6_B, - IFN_PWM0, - FN_AVB_AVTP_PPS, - FN_VI4_DATA6_B, - FN_IECLK_B, - IFN_PWM1_A, - FN_HRX3_D, - FN_VI4_DATA7_B, - FN_IERX_B, - IFN_PWM2_A, - FN_PWMFSW0, - FN_HTX3_D, - FN_IETX_B, - IFN_A0, - FN_LCDOUT16, - FN_MSIOF3_SYNC_B, - FN_VI4_DATA8, - FN_DU_DB0, - FN_PWM3_A, - - /* IPSR2 */ - IFN_A1, - FN_LCDOUT17, - FN_MSIOF3_TXD_B, - FN_VI4_DATA9, - FN_DU_DB1, - FN_PWM4_A, - IFN_A2, - FN_LCDOUT18, - FN_MSIOF3_SCK_B, - FN_VI4_DATA10, - FN_DU_DB2, - FN_PWM5_A, - IFN_A3, - FN_LCDOUT19, - FN_MSIOF3_RXD_B, - FN_VI4_DATA11, - FN_DU_DB3, - FN_PWM6_A, - IFN_A4, - FN_LCDOUT20, - FN_MSIOF3_SS1_B, - FN_VI4_DATA12, - FN_VI5_DATA12, - FN_DU_DB4, - IFN_A5, - FN_LCDOUT21, - FN_MSIOF3_SS2_B, - FN_SCK4_B, - FN_VI4_DATA13, - FN_VI5_DATA13, - FN_DU_DB5, - IFN_A6, - FN_LCDOUT22, - FN_MSIOF2_SS1_A, - FN_RX4_B, - FN_VI4_DATA14, - FN_VI5_DATA14, - FN_DU_DB6, - IFN_A7, - FN_LCDOUT23, - FN_MSIOF2_SS2_A, - FN_TX4_B, - FN_VI4_DATA15, - FN_V15_DATA15, - FN_DU_DB7, - IFN_A8, - FN_RX3_B, - FN_MSIOF2_SYNC_A, - FN_HRX4_B, - FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, - FN_PWM1_B, - - /* IPSR3 */ - IFN_A9, - FN_MSIOF2_SCK_A, - FN_CTS4x_B, - FN_VI5_VSYNCx, - IFN_A10, - FN_MSIOF2_RXD_A, - FN_RTS4n_TANS_B, - FN_VI5_HSYNCx, - IFN_A11, - FN_TX3_B, - FN_MSIOF2_TXD_A, - FN_HTX4_B, - FN_HSCK4, - FN_VI5_FIELD, - FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, - FN_PWM2_B, - FN_SPV_EVEN, - IFN_A12, - FN_LCDOUT12, - FN_MSIOF3_SCK_C, - FN_HRX4_A, - FN_VI5_DATA8, - FN_DU_DG4, - IFN_A13, - FN_LCDOUT13, - FN_MSIOF3_SYNC_C, - FN_HTX4_A, - FN_VI5_DATA9, - FN_DU_DG5, - IFN_A14, - FN_LCDOUT14, - FN_MSIOF3_RXD_C, - FN_HCTS4x, - FN_VI5_DATA10, - FN_DU_DG6, - IFN_A15, - FN_LCDOUT15, - FN_MSIOF3_TXD_C, - FN_HRTS4x, - FN_VI5_DATA11, - FN_DU_DG7, - IFN_A16, - FN_LCDOUT8, - FN_VI4_FIELD, - FN_DU_DG0, - - /* IPSR4 */ - IFN_A17, - FN_LCDOUT9, - FN_VI4_VSYNCx, - FN_DU_DG1, - IFN_A18, - FN_LCDOUT10, - FN_VI4_HSYNCx, - FN_DU_DG2, - IFN_A19, - FN_LCDOUT11, - FN_VI4_CLKENB, - FN_DU_DG3, - IFN_CS0x, - FN_VI5_CLKENB, - IFN_CS1x_A26, - FN_VI5_CLK, - FN_EX_WAIT0_B, - IFN_BSx, - FN_QSTVA_QVS, - FN_MSIOF3_SCK_D, - FN_SCK3, - FN_HSCK3, - FN_CAN1_TX, - FN_CANFD1_TX, - FN_IETX_A, - IFN_RDx, - FN_MSIOF3_SYNC_D, - FN_RX3_A, - FN_HRX3_A, - FN_CAN0_TX_A, - FN_CANFD0_TX_A, - IFN_RD_WRx, - FN_MSIOF3_RXD_D, - FN_TX3_A, - FN_HTX3_A, - FN_CAN0_RX_A, - FN_CANFD0_RX_A, - - /* IPSR5 */ - IFN_WE0x, - FN_MSIIOF3_TXD_D, - FN_CTS3x, - FN_HCTS3x, - FN_SCL6_B, - FN_CAN_CLK, - FN_IECLK_A, - IFN_WE1x, - FN_MSIOF3_SS1_D, - FN_RTS3x_TANS, - FN_HRTS3x, - FN_SDA6_B, - FN_CAN1_RX, - FN_CANFD1_RX, - FN_IERX_A, - IFN_EX_WAIT0_A, - FN_QCLK, - FN_VI4_CLK, - FN_DU_DOTCLKOUT0, - IFN_D0, - FN_MSIOF2_SS1_B, - FN_MSIOF3_SCK_A, - FN_VI4_DATA16, - FN_VI5_DATA0, - IFN_D1, - FN_MSIOF2_SS2_B, - FN_MSIOF3_SYNC_A, - FN_VI4_DATA17, - FN_VI5_DATA1, - IFN_D2, - FN_MSIOF3_RXD_A, - FN_VI4_DATA18, - FN_VI5_DATA2, - IFN_D3, - FN_MSIOF3_TXD_A, - FN_VI4_DATA19, - FN_VI5_DATA3, - IFN_D4, - FN_MSIOF2_SCK_B, - FN_VI4_DATA20, - FN_VI5_DATA4, - - /* IPSR6 */ - IFN_D5, - FN_MSIOF2_SYNC_B, - FN_VI4_DATA21, - FN_VI5_DATA5, - IFN_D6, - FN_MSIOF2_RXD_B, - FN_VI4_DATA22, - FN_VI5_DATA6, - IFN_D7, - FN_MSIOF2_TXD_B, - FN_VI4_DATA23, - FN_VI5_DATA7, - IFN_D8, - FN_LCDOUT0, - FN_MSIOF2_SCK_D, - FN_SCK4_C, - FN_VI4_DATA0_A, - FN_DU_DR0, - IFN_D9, - FN_LCDOUT1, - FN_MSIOF2_SYNC_D, - FN_VI4_DATA1_A, - FN_DU_DR1, - IFN_D10, - FN_LCDOUT2, - FN_MSIOF2_RXD_D, - FN_HRX3_B, - FN_VI4_DATA2_A, - FN_CTS4x_C, - FN_DU_DR2, - IFN_D11, - FN_LCDOUT3, - FN_MSIOF2_TXD_D, - FN_HTX3_B, - FN_VI4_DATA3_A, - FN_RTS4x_TANS_C, - FN_DU_DR3, - IFN_D12, - FN_LCDOUT4, - FN_MSIOF2_SS1_D, - FN_RX4_C, - FN_VI4_DATA4_A, - FN_DU_DR4, - - /* IPSR7 */ - IFN_D13, - FN_LCDOUT5, - FN_MSIOF2_SS2_D, - FN_TX4_C, - FN_VI4_DATA5_A, - FN_DU_DR5, - IFN_D14, - FN_LCDOUT6, - FN_MSIOF3_SS1_A, - FN_HRX3_C, - FN_VI4_DATA6_A, - FN_DU_DR6, - FN_SCL6_C, - IFN_D15, - FN_LCDOUT7, - FN_MSIOF3_SS2_A, - FN_HTX3_C, - FN_VI4_DATA7_A, - FN_DU_DR7, - FN_SDA6_C, - FN_FSCLKST, - IFN_SD0_CLK, - FN_MSIOF1_SCK_E, - FN_STP_OPWM_0_B, - IFN_SD0_CMD, - FN_MSIOF1_SYNC_E, - FN_STP_IVCXO27_0_B, - IFN_SD0_DAT0, - FN_MSIOF1_RXD_E, - FN_TS_SCK0_B, - FN_STP_ISCLK_0_B, - IFN_SD0_DAT1, - FN_MSIOF1_TXD_E, - FN_TS_SPSYNC0_B, - FN_STP_ISSYNC_0_B, - - /* IPSR8 */ - IFN_SD0_DAT2, - FN_MSIOF1_SS1_E, - FN_TS_SDAT0_B, - FN_STP_ISD_0_B, - - IFN_SD0_DAT3, - FN_MSIOF1_SS2_E, - FN_TS_SDEN0_B, - FN_STP_ISEN_0_B, - - IFN_SD1_CLK, - FN_MSIOF1_SCK_G, - FN_SIM0_CLK_A, - - IFN_SD1_CMD, - FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - FN_SIM0_D_A, - FN_STP_IVCXO27_1_B, - - IFN_SD1_DAT0, - FN_SD2_DAT4, - FN_MSIOF1_RXD_G, - FN_NFWPx_B, - FN_TS_SCK1_B, - FN_STP_ISCLK_1_B, - - IFN_SD1_DAT1, - FN_SD2_DAT5, - FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - FN_TS_SPSYNC1_B, - FN_STP_ISSYNC_1_B, - - IFN_SD1_DAT2, - FN_SD2_DAT6, - FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - FN_TS_SDAT1_B, - FN_STP_IOD_1_B, - - IFN_SD1_DAT3, - FN_SD2_DAT7, - FN_MSIOF1_SS2_G, - FN_NFRBx_B, - FN_TS_SDEN1_B, - FN_STP_ISEN_1_B, - - /* IPSR9 */ - IFN_SD2_CLK, - FN_NFDATA8, - - IFN_SD2_CMD, - FN_NFDATA9, - - IFN_SD2_DAT0, - FN_NFDATA10, - - IFN_SD2_DAT1, - FN_NFDATA11, - - IFN_SD2_DAT2, - FN_NFDATA12, - - IFN_SD2_DAT3, - FN_NFDATA13, - - IFN_SD2_DS, - FN_NFALE, - - IFN_SD3_CLK, - FN_NFWEx, - - /* IPSR10 */ - IFN_SD3_CMD, - FN_NFREx, - - IFN_SD3_DAT0, - FN_NFDATA0, - - IFN_SD3_DAT1, - FN_NFDATA1, - - IFN_SD3_DAT2, - FN_NFDATA2, - - IFN_SD3_DAT3, - FN_NFDATA3, - - IFN_SD3_DAT4, - FN_SD2_CD_A, - FN_NFDATA4, - - IFN_SD3_DAT5, - FN_SD2_WP_A, - FN_NFDATA5, - - IFN_SD3_DAT6, - FN_SD3_CD, - FN_NFDATA6, - - /* IPSR11 */ - IFN_SD3_DAT7, - FN_SD3_WP, - FN_NFDATA7, - - IFN_SD3_DS, - FN_NFCLE, - - IFN_SD0_CD, - FN_NFDATA14_A, - FN_SCL2_B, - FN_SIM0_RST_A, - - IFN_SD0_WP, - FN_NFDATA15_A, - FN_SDA2_B, - - IFN_SD1_CD, - FN_NFRBx_A, - FN_SIM0_CLK_B, - - IFN_SD1_WP, - FN_NFCEx_A, - FN_SIM0_D_B, - - IFN_SCK0, - FN_HSCK1_B, - FN_MSIOF1_SS2_B, - FN_AUDIO_CLKC_B, - FN_SDA2_A, - FN_SIM0_RST_B, - FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - FN_ADICHS2, - FN_SCK5_B, - - IFN_RX0, - FN_HRX1_B, - FN_TS_SCK0_C, - FN_STP_ISCLK_0_C, - FN_RIF0_D0_B, - - /* IPSR12 */ - IFN_TX0, - FN_HTX1_B, - FN_TS_SPSYNC0_C, - FN_STP_ISSYNC_0_C, - FN_RIF0_D1_B, - - IFN_CTS0x, - FN_HCTS1x_B, - FN_MSIOF1_SYNC_B, - FN_TS_SPSYNC1_C, - FN_STP_ISSYNC_1_C, - FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, - FN_ADICS_SAMP, - - IFN_RTS0x_TANS, - FN_HRTS1x_B, - FN_MSIOF1_SS1_B, - FN_AUDIO_CLKA_B, - FN_SCL2_A, - FN_STP_IVCXO27_1_C, - FN_RIF0_SYNC_B, - FN_ADICHS1, - - IFN_RX1_A, - FN_HRX1_A, - FN_TS_SDAT0_C, - FN_STP_ISD_0_C, - FN_RIF1_CLK_C, - - IFN_TX1_A, - FN_HTX1_A, - FN_TS_SDEN0_C, - FN_STP_ISEN_0_C, - FN_RIF1_D0_C, - - IFN_CTS1x, - FN_HCTS1x_A, - FN_MSIOF1_RXD_B, - FN_TS_SDEN1_C, - FN_STP_ISEN_1_C, - FN_RIF1_D0_B, - FN_ADIDATA, - - IFN_RTS1x_TANS, - FN_HRTS1x_A, - FN_MSIOF1_TXD_B, - FN_TS_SDAT1_C, - FN_STP_ISD_1_C, - FN_RIF1_D1_B, - FN_ADICHS0, - - IFN_SCK2, - FN_SCIF_CLK_B, - FN_MSIOF1_SCK_B, - FN_TS_SCK1_C, - FN_STP_ISCLK_1_C, - FN_RIF1_CLK_B, - FN_ADICLK, - - /* IPSR13 */ - IFN_TX2_A, - FN_SD2_CD_B, - FN_SCL1_A, - FN_FMCLK_A, - FN_RIF1_D1_C, - FN_FSO_CFE_0_B, - - IFN_RX2_A, - FN_SD2_WP_B, - FN_SDA1_A, - FN_FMIN_A, - FN_RIF1_SYNC_C, - FN_FSO_CEF_1_B, - - IFN_HSCK0, - FN_MSIOF1_SCK_D, - FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, - FN_TS_SCK0_D, - FN_STP_ISCLK_0_D, - FN_RIF0_CLK_C, - FN_RX5_B, - - IFN_HRX0, - FN_MSIOF1_RXD_D, - FN_SS1_SDATA2_B, - FN_TS_SDEN0_D, - FN_STP_ISEN_0_D, - FN_RIF0_D0_C, - - IFN_HTX0, - FN_MSIOF1_TXD_D, - FN_SSI_SDATA9_B, - FN_TS_SDAT0_D, - FN_STP_ISD_0_D, - FN_RIF0_D1_C, - - IFN_HCTS0x, - FN_RX2_B, - FN_MSIOF1_SYNC_D, - FN_SSI_SCK9_A, - FN_TS_SPSYNC0_D, - FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, - - IFN_HRTS0x, - FN_TX2_B, - FN_MSIOF1_SS1_D, - FN_SSI_WS9_A, - FN_STP_IVCXO27_0_D, - FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, - - IFN_MSIOF0_SYNC, - FN_AUDIO_CLKOUT_A, - FN_TX5_B, - FN_BPFCLK_D, - - /* IPSR14 */ - IFN_MSIOF0_SS1, - FN_RX5_A, - FN_NFWPx_A, - FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, - FN_STP_IVCXO27_0_C, - FN_AUDIO_CLKOUT3_A, - FN_TCLK1_B, - - IFN_MSIOF0_SS2, - FN_TX5_A, - FN_MSIOF1_SS2_D, - FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, - FN_STP_OPWM_0_D, - FN_AUDIO_CLKOUT_D, - FN_SPEEDIN_B, - - IFN_MLB_CLK, - FN_MSIOF1_SCK_F, - FN_SCL1_B, - - IFN_MLB_SIG, - FN_RX1_B, - FN_MSIOF1_SYNC_F, - FN_SDA1_B, - - IFN_MLB_DAT, - FN_TX1_B, - FN_MSIOF1_RXD_F, - - IFN_SSI_SCK0129, - FN_MSIOF1_TXD_F, - FN_MOUT0, - - IFN_SSI_WS0129, - FN_MSIOF1_SS1_F, - FN_MOUT1, - - IFN_SSI_SDATA0, - FN_MSIOF1_SS2_F, - FN_MOUT2, - - /* IPSR15 */ - IFN_SSI_SDATA1_A, - FN_MOUT5, - - IFN_SSI_SDATA2_A, - FN_SSI_SCK1_B, - FN_MOUT6, - - IFN_SSI_SCK34, - FN_MSIOF1_SS1_A, - FN_STP_OPWM_0_A, - - IFN_SSI_WS34, - FN_HCTS2x_A, - FN_MSIOF1_SS2_A, - FN_STP_IVCXO27_0_A, - - IFN_SSI_SDATA3, - FN_HRTS2x_A, - FN_MSIOF1_TXD_A, - FN_TS_SCK0_A, - FN_STP_ISCLK_0_A, - FN_RIF0_D1_A, - FN_RIF2_D0_A, - - IFN_SSI_SCK4, - FN_HRX2_A, - FN_MSIOF1_SCK_A, - FN_TS_SDAT0_A, - FN_STP_ISD_0_A, - FN_RIF0_CLK_A, - FN_RIF2_CLK_A, - - IFN_SSI_WS4, - FN_HTX2_A, - FN_MSIOF1_SYNC_A, - FN_TS_SDEN0_A, - FN_STP_ISEN_0_A, - FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, - - IFN_SSI_SDATA4, - FN_HSCK2_A, - FN_MSIOF1_RXD_A, - FN_TS_SPSYNC0_A, - FN_STP_ISSYNC_0_A, - FN_RIF0_D0_A, - FN_RIF2_D1_A, - - /* IPSR16 */ - IFN_SSI_SCK6, - FN_SIM0_RST_D, - FN_FSO_TOE_A, - - IFN_SSI_WS6, - FN_SIM0_D_D, - - IFN_SSI_SDATA6, - FN_SIM0_CLK_D, - - IFN_SSI_SCK78, - FN_HRX2_B, - FN_MSIOF1_SCK_C, - FN_TS_SCK1_A, - FN_STP_ISCLK_1_A, - FN_RIF1_CLK_A, - FN_RIF3_CLK_A, - - IFN_SSI_WS78, - FN_HTX2_B, - FN_MSIOF1_SYNC_C, - FN_TS_SDAT1_A, - FN_STP_ISD_1_A, - FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, - - IFN_SSI_SDATA7, - FN_HCTS2x_B, - FN_MSIOF1_RXD_C, - FN_TS_SDEN1_A, - FN_STP_IEN_1_A, - FN_RIF1_D0_A, - FN_RIF3_D0_A, - FN_TCLK2_A, - - IFN_SSI_SDATA8, - FN_HRTS2x_B, - FN_MSIOF1_TXD_C, - FN_TS_SPSYNC1_A, - FN_STP_ISSYNC_1_A, - FN_RIF1_D1_A, - FN_EIF3_D1_A, - - IFN_SSI_SDATA9_A, - FN_HSCK2_B, - FN_MSIOF1_SS1_C, - FN_HSCK1_A, - FN_SSI_WS1_B, - FN_SCK1, - FN_STP_IVCXO27_1_A, - FN_SCK5, - - /* IPSR17 */ - IFN_AUDIO_CLKA_A, - FN_CC5_OSCOUT, - - IFN_AUDIO_CLKB_B, - FN_SCIF_CLK_A, - FN_STP_IVCXO27_1_D, - FN_REMOCON_A, - FN_TCLK1_A, - - IFN_USB0_PWEN, - FN_SIM0_RST_C, - FN_TS_SCK1_D, - FN_STP_ISCLK_1_D, - FN_BPFCLK_B, - FN_RIF3_CLK_B, - FN_FSO_CFE_1_A, - FN_HSCK2_C, - - IFN_USB0_OVC, - FN_SIM0_D_C, - FN_TS_SDAT1_D, - FN_STP_ISD_1_D, - FN_RIF3_SYNC_B, - FN_HRX2_C, - - IFN_USB1_PWEN, - FN_SIM0_CLK_C, - FN_SSI_SCK1_A, - FN_TS_SCK0_E, - FN_STP_ISCLK_0_E, - FN_FMCLK_B, - FN_RIF2_CLK_B, - FN_SPEEDIN_A, - FN_HTX2_C, - - IFN_USB1_OVC, - FN_MSIOF1_SS2_C, - FN_SSI_WS1_A, - FN_TS_SDAT0_E, - FN_STP_ISD_0_E, - FN_FMIN_B, - FN_RIF2_SYNC_B, - FN_REMOCON_B, - FN_HCTS2x_C, - - IFN_USB30_PWEN, - FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, - FN_TS_SDEN1_D, - FN_STP_ISEN_1_D, - FN_STP_OPWM_0_E, - FN_RIF3_D0_B, - FN_TCLK2_B, - FN_TPU0TO0, - FN_BPFCLK_C, - FN_HRTS2x_C, - - IFN_USB30_OVC, - FN_AUDIO_CLKOUT1_B, - FN_SSI_WS2_B, - FN_TS_SPSYNC1_D, - FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, - FN_FSO_TOE_B, - FN_TPU0TO1, - - /* IPSR18 */ - IFN_GP6_30, - FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, - FN_TS_SDEN0_E, - FN_STP_ISEN_0_E, - FN_RIF2_D0_B, - FN_FSO_CFE_0_A, - FN_TPU0TO2, - FN_FMCLK_C, - FN_FMCLK_D, - - IFN_GP6_31, - FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, - FN_TS_SPSYNC0_E, - FN_STP_ISSYNC_0_E, - FN_RIF2_D1_B, - FN_TPU0TO3, - FN_FMIN_C, - FN_FMIN_D, - - /* MOD_SEL0 */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, - FN_SEL_MSIOF3_6, - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - FN_SEL_FSO_0, FN_SEL_FSO_1, - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - - /* MOD_SEL1 */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - FN_SEL_SSI_0, - FN_SEL_SSI_1, - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, - - /* MOD_SEL2 */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - FN_SEL_FM_0, - FN_SEL_FM_1, - FN_SEL_FM_2, - FN_SEL_FM_3, - FN_SEL_SCIF5_0, - FN_SEL_SCIF5_1, - FN_SEL_I2C6_0, - FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - FN_SEL_NDF_0, - FN_SEL_NDF_1, - FN_SEL_SSI2_0, - FN_SEL_SSI2_1, - FN_SEL_SSI9_0, - FN_SEL_SSI9_1, - FN_SEL_TIMER_TMU2_0, - FN_SEL_TIMER_TMU2_1, - FN_SEL_ADG_B_0, - FN_SEL_ADG_B_1, - FN_SEL_ADG_C_0, - FN_SEL_ADG_C_1, - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* GPSR0 */ - D15_GMARK, - D14_GMARK, - D13_GMARK, - D12_GMARK, - D11_GMARK, - D10_GMARK, - D9_GMARK, - D8_GMARK, - D7_GMARK, - D6_GMARK, - D5_GMARK, - D4_GMARK, - D3_GMARK, - D2_GMARK, - D1_GMARK, - D0_GMARK, - - /* GPSR1 */ - CLKOUT_GMARK, - EX_WAIT0_A_GMARK, - WE1x_GMARK, - WE0x_GMARK, - RD_WRx_GMARK, - RDx_GMARK, - BSx_GMARK, - CS1x_A26_GMARK, - CS0x_GMARK, - A19_GMARK, - A18_GMARK, - A17_GMARK, - A16_GMARK, - A15_GMARK, - A14_GMARK, - A13_GMARK, - A12_GMARK, - A11_GMARK, - A10_GMARK, - A9_GMARK, - A8_GMARK, - A7_GMARK, - A6_GMARK, - A5_GMARK, - A4_GMARK, - A3_GMARK, - A2_GMARK, - A1_GMARK, - A0_GMARK, - - /* GPSR2 */ - AVB_AVTP_CAPTURE_A_GMARK, - AVB_AVTP_MATCH_A_GMARK, - AVB_LINK_GMARK, - AVB_PHY_INT_GMARK, - AVB_MAGIC_GMARK, - AVB_MDC_GMARK, - PWM2_A_GMARK, - PWM1_A_GMARK, - PWM0_GMARK, - IRQ5_GMARK, - IRQ4_GMARK, - IRQ3_GMARK, - IRQ2_GMARK, - IRQ1_GMARK, - IRQ0_GMARK, - - /* GPSR3 */ - SD1_WP_GMARK, - SD1_CD_GMARK, - SD0_WP_GMARK, - SD0_CD_GMARK, - SD1_DAT3_GMARK, - SD1_DAT2_GMARK, - SD1_DAT1_GMARK, - SD1_DAT0_GMARK, - SD1_CMD_GMARK, - SD1_CLK_GMARK, - SD0_DAT3_GMARK, - SD0_DAT2_GMARK, - SD0_DAT1_GMARK, - SD0_DAT0_GMARK, - SD0_CMD_GMARK, - SD0_CLK_GMARK, - - /* GPSR4 */ - SD3_DS_GMARK, - SD3_DAT7_GMARK, - SD3_DAT6_GMARK, - SD3_DAT5_GMARK, - SD3_DAT4_GMARK, - SD3_DAT3_MARK, - SD3_DAT2_MARK, - SD3_DAT1_MARK, - SD3_DAT0_MARK, - SD3_CMD_MARK, - SD3_CLK_MARK, - SD2_DS_GMARK, - SD2_DAT3_GMARK, - SD2_DAT2_GMARK, - SD2_DAT1_GMARK, - SD2_DAT0_GMARK, - SD2_CMD_MARK, - SD2_CLK_GMARK, - - /* GPSR5 */ - MLB_DAT_GMARK, - MLB_SIG_GMARK, - MLB_CLK_GMARK, - MSIOF0_RXD_MARK, - MSIOF0_SS2_GMARK, - MSIOF0_TXD_MARK, - MSIOF0_SS1_GMARK, - MSIOF0_SYNC_GMARK, - MSIOF0_SCK_MARK, - HRTS0x_GMARK, - HCTS0x_GMARK, - HTX0_GMARK, - HRX0_GMARK, - HSCK0_GMARK, - RX2_A_GMARK, - TX2_A_GMARK, - SCK2_GMARK, - RTS1x_TANS_GMARK, - CTS1x_GMARK, - TX1_A_GMARK, - RX1_A_GMARK, - RTS0x_TANS_GMARK, - CTS0x_GMARK, - TX0_GMARK, - RX0_GMARK, - SCK0_GMARK, - - /* GPSR6 */ - GP6_30_GMARK, - GP6_31_GMARK, - USB30_OVC_GMARK, - USB30_PWEN_GMARK, - USB1_OVC_GMARK, - USB1_PWEN_GMARK, - USB0_OVC_GMARK, - USB0_PWEN_GMARK, - AUDIO_CLKB_B_GMARK, - AUDIO_CLKA_A_GMARK, - SSI_SDATA9_A_GMARK, - SSI_SDATA8_GMARK, - SSI_SDATA7_GMARK, - SSI_WS78_GMARK, - SSI_SCK78_GMARK, - SSI_SDATA6_GMARK, - SSI_WS6_GMARK, - SSI_SCK6_GMARK, - SSI_SDATA5_MARK, - SSI_WS5_MARK, - SSI_SCK5_MARK, - SSI_SDATA4_GMARK, - SSI_WS4_GMARK, - SSI_SCK4_GMARK, - SSI_SDATA3_GMARK, - SSI_WS34_GMARK, - SSI_SCK34_GMARK, - SSI_SDATA2_A_GMARK, - SSI_SDATA1_A_GMARK, - SSI_SDATA0_GMARK, - SSI_WS01239_GMARK, - SSI_SCK01239_GMARK, - - /* GPSR7 */ - HDMI1_CEC_MARK, - HDMI0_CEC_MARK, - AVS2_MARK, - AVS1_MARK, - - /* IPSR0 */ - AVB_MDC_IMARK, - MSIOF2_SS2_C_MARK, - AVB_MAGIC_IMARK, - MSIOF2_SS1_C_MARK, - SCK4_A_MARK, - AVB_PHY_INT_IMARK, - MSIOF2_SYNC_C_MARK, - RX4_A_MARK, - AVB_LINK_IMARK, - MSIOF2_SCK_C_MARK, - TX4_A_MARK, - AVB_AVTP_MATCH_A_IMARK, - MSIOF2_RXD_C_MARK, - CTS4x_A_MARK, - AVB_AVTP_CAPTURE_A_IMARK, - MSIOF2_TXD_C_MARK, - RTS4x_TANS_A_MARK, - IRQ0_IMARK, - QPOLB_MARK, - DU_CDE_MARK, - VI4_DATA0_B_MARK, - CAN0_TX_B_MARK, - CANFD0_TX_B_MARK, - MSIOF3_SS2_E_MARK, - IRQ1_IMARK, - QPOLA_MARK, - DU_DISP_MARK, - VI4_DATA1_B_MARK, - CAN0_RX_B_MARK, - CANFD0_RX_B_MARK, - MSIOF3_SS1_E_MARK, - - /* IPSR1 */ - IRQ2_IMARK, - QCPV_QDE_MARK, - DU_EXODDF_DU_ODDF_DISP_CDE_MARK, - VI4_DATA2_B_MARK, - MSIOF3_SYNC_E_MARK, - PWM3_B_MARK, - IRQ3_IMARK, - QSTVB_QVE_MARK, - DU_DOTCLKOUT1_MARK, - VI4_DATA3_B_MARK, - MSIOF3_SCK_E_MARK, - PWM4_B_MARK, - IRQ4_IMARK, - QSTH_QHS_MARK, - DU_EXHSYNC_DU_HSYNC_MARK, - VI4_DATA4_B_MARK, - MSIOF3_RXD_E_MARK, - PWM5_B_MARK, - IRQ5_IMARK, - QSTB_QHE_MARK, - DU_EXVSYNC_DU_VSYNC_MARK, - VI4_DATA5_B_MARK, - MSIOF3_TXD_E_MARK, - PWM6_B_MARK, - PWM0_IMARK, - AVB_AVTP_PPS_MARK, - VI4_DATA6_B_MARK, - IECLK_B_MARK, - PWM1_A_IMARK, - HRX3_D_MARK, - VI4_DATA7_B_MARK, - IERX_B_MARK, - PWM2_A_IMARK, - PWMFSW0_MARK, - HTX3_D_MARK, - IETX_B_MARK, - A0_IMARK, - LCDOUT16_MARK, - MSIOF3_SYNC_B_MARK, - VI4_DATA8_MARK, - DU_DB0_MARK, - PWM3_A_MARK, - - /* IPSR2 */ - A1_IMARK, - LCDOUT17_MARK, - MSIOF3_TXD_B_MARK, - VI4_DATA9_MARK, - DU_DB1_MARK, - PWM4_A_MARK, - A2_IMARK, - LCDOUT18_MARK, - MSIOF3_SCK_B_MARK, - VI4_DATA10_MARK, - DU_DB2_MARK, - PWM5_A_MARK, - A3_IMARK, - LCDOUT19_MARK, - MSIOF3_RXD_B_MARK, - VI4_DATA11_MARK, - DU_DB3_MARK, - PWM6_A_MARK, - A4_IMARK, - LCDOUT20_MARK, - MSIOF3_SS1_B_MARK, - VI4_DATA12_MARK, - VI5_DATA12_MARK, - DU_DB4_MARK, - A5_IMARK, - LCDOUT21_MARK, - MSIOF3_SS2_B_MARK, - SCK4_B_MARK, - VI4_DATA13_MARK, - VI5_DATA13_MARK, - DU_DB5_MARK, - A6_IMARK, - LCDOUT22_MARK, - MSIOF2_SS1_A_MARK, - RX4_B_MARK, - VI4_DATA14_MARK, - VI5_DATA14_MARK, - DU_DB6_MARK, - A7_IMARK, - LCDOUT23_MARK, - MSIOF2_SS2_A_MARK, - TX4_B_MARK, - VI4_DATA15_MARK, - V15_DATA15_MARK, - DU_DB7_MARK, - A8_IMARK, - RX3_B_MARK, - MSIOF2_SYNC_A_MARK, - HRX4_B_MARK, - SDA6_A_MARK, - AVB_AVTP_MATCH_B_MARK, - PWM1_B_MARK, - - /* IPSR3 */ - A9_IMARK, - MSIOF2_SCK_A_MARK, - CTS4x_B_MARK, - VI5_VSYNCx_MARK, - A10_IMARK, - MSIOF2_RXD_A_MARK, - RTS4n_TANS_B_MARK, - VI5_HSYNCx_MARK, - A11_IMARK, - TX3_B_MARK, - MSIOF2_TXD_A_MARK, - HTX4_B_MARK, - HSCK4_MARK, - VI5_FIELD_MARK, - SCL6_A_MARK, - AVB_AVTP_CAPTURE_B_MARK, - PWM2_B_MARK, - SPV_EVEN_MARK, - A12_IMARK, - LCDOUT12_MARK, - MSIOF3_SCK_C_MARK, - HRX4_A_MARK, - VI5_DATA8_MARK, - DU_DG4_MARK, - A13_IMARK, - LCDOUT13_MARK, - MSIOF3_SYNC_C_MARK, - HTX4_A_MARK, - VI5_DATA9_MARK, - DU_DG5_MARK, - A14_IMARK, - LCDOUT14_MARK, - MSIOF3_RXD_C_MARK, - HCTS4x_MARK, - VI5_DATA10_MARK, - DU_DG6_MARK, - A15_IMARK, - LCDOUT15_MARK, - MSIOF3_TXD_C_MARK, - HRTS4x_MARK, - VI5_DATA11_MARK, - DU_DG7_MARK, - A16_IMARK, - LCDOUT8_MARK, - VI4_FIELD_MARK, - DU_DG0_MARK, - - /* IPSR4 */ - A17_IMARK, - LCDOUT9_MARK, - VI4_VSYNCx_MARK, - DU_DG1_MARK, - A18_IMARK, - LCDOUT10_MARK, - VI4_HSYNCx_MARK, - DU_DG2_MARK, - A19_IMARK, - LCDOUT11_MARK, - VI4_CLKENB_MARK, - DU_DG3_MARK, - CS0x_IMARK, - VI5_CLKENB_MARK, - CS1x_A26_IMARK, - VI5_CLK_MARK, - EX_WAIT0_B_MARK, - BSx_IMARK, - QSTVA_QVS_MARK, - MSIOF3_SCK_D_MARK, - SCK3_MARK, - HSCK3_MARK, - CAN1_TX_MARK, - CANFD1_TX_MARK, - IETX_A_MARK, - RDx_IMARK, - MSIOF3_SYNC_D_MARK, - RX3_A_MARK, - HRX3_A_MARK, - CAN0_TX_A_MARK, - CANFD0_TX_A_MARK, - RD_WRx_IMARK, - MSIOF3_RXD_D_MARK, - TX3_A_MARK, - HTX3_A_MARK, - CAN0_RX_A_MARK, - CANFD0_RX_A_MARK, - - /* IPSR5 */ - WE0x_IMARK, - MSIIOF3_TXD_D_MARK, - CTS3x_MARK, - HCTS3x_MARK, - SCL6_B_MARK, - CAN_CLK_MARK, - IECLK_A_MARK, - WE1x_IMARK, - MSIOF3_SS1_D_MARK, - RTS3x_TANS_MARK, - HRTS3x_MARK, - SDA6_B_MARK, - CAN1_RX_MARK, - CANFD1_RX_MARK, - IERX_A_MARK, - EX_WAIT0_A_IMARK, - QCLK_MARK, - VI4_CLK_MARK, - DU_DOTCLKOUT0_MARK, - D0_IMARK, - MSIOF2_SS1_B_MARK, - MSIOF3_SCK_A_MARK, - VI4_DATA16_MARK, - VI5_DATA0_MARK, - D1_IMARK, - MSIOF2_SS2_B_MARK, - MSIOF3_SYNC_A_MARK, - VI4_DATA17_MARK, - VI5_DATA1_MARK, - D2_IMARK, - MSIOF3_RXD_A_MARK, - VI4_DATA18_MARK, - VI5_DATA2_MARK, - D3_IMARK, - MSIOF3_TXD_A_MARK, - VI4_DATA19_MARK, - VI5_DATA3_MARK, - D4_IMARK, - MSIOF2_SCK_B_MARK, - VI4_DATA20_MARK, - VI5_DATA4_MARK, - - /* IPSR6 */ - D5_IMARK, - MSIOF2_SYNC_B_MARK, - VI4_DATA21_MARK, - VI5_DATA5_MARK, - D6_IMARK, - MSIOF2_RXD_B_MARK, - VI4_DATA22_MARK, - VI5_DATA6_MARK, - D7_IMARK, - MSIOF2_TXD_B_MARK, - VI4_DATA23_MARK, - VI5_DATA7_MARK, - D8_IMARK, - LCDOUT0_MARK, - MSIOF2_SCK_D_MARK, - SCK4_C_MARK, - VI4_DATA0_A_MARK, - DU_DR0_MARK, - D9_IMARK, - LCDOUT1_MARK, - MSIOF2_SYNC_D_MARK, - VI4_DATA1_A_MARK, - DU_DR1_MARK, - D10_IMARK, - LCDOUT2_MARK, - MSIOF2_RXD_D_MARK, - HRX3_B_MARK, - VI4_DATA2_A_MARK, - CTS4x_C_MARK, - DU_DR2_MARK, - D11_IMARK, - LCDOUT3_MARK, - MSIOF2_TXD_D_MARK, - HTX3_B_MARK, - VI4_DATA3_A_MARK, - RTS4x_TANS_C_MARK, - DU_DR3_MARK, - D12_IMARK, - LCDOUT4_MARK, - MSIOF2_SS1_D_MARK, - RX4_C_MARK, - VI4_DATA4_A_MARK, - DU_DR4_MARK, - - /* IPSR7 */ - D13_IMARK, - LCDOUT5_MARK, - MSIOF2_SS2_D_MARK, - TX4_C_MARK, - VI4_DATA5_A_MARK, - DU_DR5_MARK, - D14_IMARK, - LCDOUT6_MARK, - MSIOF3_SS1_A_MARK, - HRX3_C_MARK, - VI4_DATA6_A_MARK, - DU_DR6_MARK, - SCL6_C_MARK, - D15_IMARK, - LCDOUT7_MARK, - MSIOF3_SS2_A_MARK, - HTX3_C_MARK, - VI4_DATA7_A_MARK, - DU_DR7_MARK, - SDA6_C_MARK, - FSCLKST_MARK, - SD0_CLK_IMARK, - MSIOF1_SCK_E_MARK, - STP_OPWM_0_B_MARK, - SD0_CMD_IMARK, - MSIOF1_SYNC_E_MARK, - STP_IVCXO27_0_B_MARK, - SD0_DAT0_IMARK, - MSIOF1_RXD_E_MARK, - TS_SCK0_B_MARK, - STP_ISCLK_0_B_MARK, - SD0_DAT1_IMARK, - MSIOF1_TXD_E_MARK, - TS_SPSYNC0_B_MARK, - STP_ISSYNC_0_B_MARK, - - /* IPSR8 */ - SD0_DAT2_IMARK, - MSIOF1_SS1_E_MARK, - TS_SDAT0_B_MARK, - STP_ISD_0_B_MARK, - - SD0_DAT3_IMARK, - MSIOF1_SS2_E_MARK, - TS_SDEN0_B_MARK, - STP_ISEN_0_B_MARK, - - SD1_CLK_IMARK, - MSIOF1_SCK_G_MARK, - SIM0_CLK_A_MARK, - - SD1_CMD_IMARK, - MSIOF1_SYNC_G_MARK, - NFCEx_B_MARK, - SIM0_D_A_MARK, - STP_IVCXO27_1_B_MARK, - - SD1_DAT0_IMARK, - SD2_DAT4_MARK, - MSIOF1_RXD_G_MARK, - NFWPx_B_MARK, - TS_SCK1_B_MARK, - STP_ISCLK_1_B_MARK, - - SD1_DAT1_IMARK, - SD2_DAT5_MARK, - MSIOF1_TXD_G_MARK, - NFDATA14_B_MARK, - TS_SPSYNC1_B_MARK, - STP_ISSYNC_1_B_MARK, - - SD1_DAT2_IMARK, - SD2_DAT6_MARK, - MSIOF1_SS1_G_MARK, - NFDATA15_B_MARK, - TS_SDAT1_B_MARK, - STP_IOD_1_B_MARK, - - SD1_DAT3_IMARK, - SD2_DAT7_MARK, - MSIOF1_SS2_G_MARK, - NFRBx_B_MARK, - TS_SDEN1_B_MARK, - STP_ISEN_1_B_MARK, - - /* IPSR9 */ - SD2_CLK_IMARK, - NFDATA8_MARK, - - SD2_CMD_IMARK, - NFDATA9_MARK, - - SD2_DAT0_IMARK, - NFDATA10_MARK, - - SD2_DAT1_IMARK, - NFDATA11_MARK, - - SD2_DAT2_IMARK, - NFDATA12_MARK, - - SD2_DAT3_IMARK, - NFDATA13_MARK, - - SD2_DS_IMARK, - NFALE_MARK, - - SD3_CLK_IMARK, - NFWEx_MARK, - - /* IPSR10 */ - SD3_CMD_IMARK, - NFREx_MARK, - - SD3_DAT0_IMARK, - NFDATA0_MARK, - - SD3_DAT1_IMARK, - NFDATA1_MARK, - - SD3_DAT2_IMARK, - NFDATA2_MARK, - - SD3_DAT3_IMARK, - NFDATA3_MARK, - - SD3_DAT4_IMARK, - SD2_CD_A_MARK, - NFDATA4_MARK, - - SD3_DAT5_IMARK, - SD2_WP_A_MARK, - NFDATA5_MARK, - - SD3_DAT6_IMARK, - SD3_CD_MARK, - NFDATA6_MARK, - - /* IPSR11 */ - SD3_DAT7_IMARK, - SD3_WP_MARK, - NFDATA7_MARK, - - SD3_DS_IMARK, - NFCLE_MARK, - - SD0_CD_IMARK, - NFDATA14_A_MARK, - SCL2_B_MARK, - SIM0_RST_A_MARK, - - SD0_WP_IMARK, - NFDATA15_A_MARK, - SDA2_B_MARK, - - SD1_CD_IMARK, - NFRBx_A_MARK, - SIM0_CLK_B_MARK, - - SD1_WP_IMARK, - NFCEx_A_MARK, - SIM0_D_B_MARK, - - SCK0_IMARK, - HSCK1_B_MARK, - MSIOF1_SS2_B_MARK, - AUDIO_CLKC_B_MARK, - SDA2_A_MARK, - SIM0_RST_B_MARK, - STP_OPWM_0_C_MARK, - RIF0_CLK_B_MARK, - ADICHS2_MARK, - SCK5_B_MARK, - - RX0_IMARK, - HRX1_B_MARK, - TS_SCK0_C_MARK, - STP_ISCLK_0_C_MARK, - RIF0_D0_B_MARK, - - /* IPSR12 */ - TX0_IMARK, - HTX1_B_MARK, - TS_SPSYNC0_C_MARK, - STP_ISSYNC_0_C_MARK, - RIF0_D1_B_MARK, - - CTS0x_IMARK, - HCTS1x_B_MARK, - MSIOF1_SYNC_B_MARK, - TS_SPSYNC1_C_MARK, - STP_ISSYNC_1_C_MARK, - RIF1_SYNC_B_MARK, - AUDIO_CLKOUT_C_MARK, - ADICS_SAMP_MARK, - - RTS0x_TANS_IMARK, - HRTS1x_B_MARK, - MSIOF1_SS1_B_MARK, - AUDIO_CLKA_B_MARK, - SCL2_A_MARK, - STP_IVCXO27_1_C_MARK, - RIF0_SYNC_B_MARK, - ADICHS1_MARK, - - RX1_A_IMARK, - HRX1_A_MARK, - TS_SDAT0_C_MARK, - STP_ISD_0_C_MARK, - RIF1_CLK_C_MARK, - - TX1_A_IMARK, - HTX1_A_MARK, - TS_SDEN0_C_MARK, - STP_ISEN_0_C_MARK, - RIF1_D0_C_MARK, - - CTS1x_IMARK, - HCTS1x_A_MARK, - MSIOF1_RXD_B_MARK, - TS_SDEN1_C_MARK, - STP_ISEN_1_C_MARK, - RIF1_D0_B_MARK, - ADIDATA_MARK, - - RTS1x_TANS_IMARK, - HRTS1x_A_MARK, - MSIOF1_TXD_B_MARK, - TS_SDAT1_C_MARK, - STP_ISD_1_C_MARK, - RIF1_D1_B_MARK, - ADICHS0_MARK, - - SCK2_IMARK, - SCIF_CLK_B_MARK, - MSIOF1_SCK_B_MARK, - TS_SCK1_C_MARK, - STP_ISCLK_1_C_MARK, - RIF1_CLK_B_MARK, - ADICLK_MARK, - - /* IPSR13 */ - TX2_A_IMARK, - SD2_CD_B_MARK, - SCL1_A_MARK, - FMCLK_A_MARK, - RIF1_D1_C_MARK, - FSO_CFE_0_B_MARK, - - RX2_A_IMARK, - SD2_WP_B_MARK, - SDA1_A_MARK, - FMIN_A_MARK, - RIF1_SYNC_C_MARK, - FSO_CEF_1_B_MARK, - - HSCK0_IMARK, - MSIOF1_SCK_D_MARK, - AUDIO_CLKB_A_MARK, - SSI_SDATA1_B_MARK, - TS_SCK0_D_MARK, - STP_ISCLK_0_D_MARK, - RIF0_CLK_C_MARK, - RX5_B_MARK, - - HRX0_IMARK, - MSIOF1_RXD_D_MARK, - SS1_SDATA2_B_MARK, - TS_SDEN0_D_MARK, - STP_ISEN_0_D_MARK, - RIF0_D0_C_MARK, - - HTX0_IMARK, - MSIOF1_TXD_D_MARK, - SSI_SDATA9_B_MARK, - TS_SDAT0_D_MARK, - STP_ISD_0_D_MARK, - RIF0_D1_C_MARK, - - HCTS0x_IMARK, - RX2_B_MARK, - MSIOF1_SYNC_D_MARK, - SSI_SCK9_A_MARK, - TS_SPSYNC0_D_MARK, - STP_ISSYNC_0_D_MARK, - RIF0_SYNC_C_MARK, - AUDIO_CLKOUT1_A_MARK, - - HRTS0x_IMARK, - TX2_B_MARK, - MSIOF1_SS1_D_MARK, - SSI_WS9_A_MARK, - STP_IVCXO27_0_D_MARK, - BPFCLK_A_MARK, - AUDIO_CLKOUT2_A_MARK, - - MSIOF0_SYNC_IMARK, - AUDIO_CLKOUT_A_MARK, - TX5_B_MARK, - BPFCLK_D_MARK, - - /* IPSR14 */ - MSIOF0_SS1_IMARK, - RX5_A_MARK, - NFWPx_A_MARK, - AUDIO_CLKA_C_MARK, - SSI_SCK2_A_MARK, - STP_IVCXO27_0_C_MARK, - AUDIO_CLKOUT3_A_MARK, - TCLK1_B_MARK, - - MSIOF0_SS2_IMARK, - TX5_A_MARK, - MSIOF1_SS2_D_MARK, - AUDIO_CLKC_A_MARK, - SSI_WS2_A_MARK, - STP_OPWM_0_D_MARK, - AUDIO_CLKOUT_D_MARK, - SPEEDIN_B_MARK, - - MLB_CLK_IMARK, - MSIOF1_SCK_F_MARK, - SCL1_B_MARK, - - MLB_SIG_IMARK, - RX1_B_MARK, - MSIOF1_SYNC_F_MARK, - SDA1_B_MARK, - - MLB_DAT_IMARK, - TX1_B_MARK, - MSIOF1_RXD_F_MARK, - - SSI_SCK0129_IMARK, - MSIOF1_TXD_F_MARK, - MOUT0_MARK, - - SSI_WS0129_IMARK, - MSIOF1_SS1_F_MARK, - MOUT1_MARK, - - SSI_SDATA0_IMARK, - MSIOF1_SS2_F_MARK, - MOUT2_MARK, - - /* IPSR15 */ - SSI_SDATA1_A_IMARK, - MOUT5_MARK, - - SSI_SDATA2_A_IMARK, - SSI_SCK1_B_MARK, - MOUT6_MARK, - - SSI_SCK34_IMARK, - MSIOF1_SS1_A_MARK, - STP_OPWM_0_A_MARK, - - SSI_WS34_IMARK, - HCTS2x_A_MARK, - MSIOF1_SS2_A_MARK, - STP_IVCXO27_0_A_MARK, - - SSI_SDATA3_IMARK, - HRTS2x_A_MARK, - MSIOF1_TXD_A_MARK, - TS_SCK0_A_MARK, - STP_ISCLK_0_A_MARK, - RIF0_D1_A_MARK, - RIF2_D0_A_MARK, - - SSI_SCK4_IMARK, - HRX2_A_MARK, - MSIOF1_SCK_A_MARK, - TS_SDAT0_A_MARK, - STP_ISD_0_A_MARK, - RIF0_CLK_A_MARK, - RIF2_CLK_A_MARK, - - SSI_WS4_IMARK, - HTX2_A_MARK, - MSIOF1_SYNC_A_MARK, - TS_SDEN0_A_MARK, - STP_ISEN_0_A_MARK, - RIF0_SYNC_A_MARK, - RIF2_SYNC_A_MARK, - - SSI_SDATA4_IMARK, - HSCK2_A_MARK, - MSIOF1_RXD_A_MARK, - TS_SPSYNC0_A_MARK, - STP_ISSYNC_0_A_MARK, - RIF0_D0_A_MARK, - RIF2_D1_A_MARK, - - /* IPSR16 */ - SSI_SCK6_IMARK, - SIM0_RST_D_MARK, - FSO_TOE_A_MARK, - - SSI_WS6_IMARK, - SIM0_D_D_MARK, - - SSI_SDATA6_IMARK, - SIM0_CLK_D_MARK, - - SSI_SCK78_IMARK, - HRX2_B_MARK, - MSIOF1_SCK_C_MARK, - TS_SCK1_A_MARK, - STP_ISCLK_1_A_MARK, - RIF1_CLK_A_MARK, - RIF3_CLK_A_MARK, - - SSI_WS78_IMARK, - HTX2_B_MARK, - MSIOF1_SYNC_C_MARK, - TS_SDAT1_A_MARK, - STP_ISD_1_A_MARK, - RIF1_SYNC_A_MARK, - RIF3_SYNC_A_MARK, - - SSI_SDATA7_IMARK, - HCTS2x_B_MARK, - MSIOF1_RXD_C_MARK, - TS_SDEN1_A_MARK, - STP_IEN_1_A_MARK, - RIF1_D0_A_MARK, - RIF3_D0_A_MARK, - TCLK2_A_MARK, - - SSI_SDATA8_IMARK, - HRTS2x_B_MARK, - MSIOF1_TXD_C_MARK, - TS_SPSYNC1_A_MARK, - STP_ISSYNC_1_A_MARK, - RIF1_D1_A_MARK, - EIF3_D1_A_MARK, - - SSI_SDATA9_A_IMARK, - HSCK2_B_MARK, - MSIOF1_SS1_C_MARK, - HSCK1_A_MARK, - SSI_WS1_B_MARK, - SCK1_MARK, - STP_IVCXO27_1_A_MARK, - SCK5_MARK, - - /* IPSR17 */ - AUDIO_CLKA_A_IMARK, - CC5_OSCOUT_MARK, - - AUDIO_CLKB_B_IMARK, - SCIF_CLK_A_MARK, - STP_IVCXO27_1_D_MARK, - REMOCON_A_MARK, - TCLK1_A_MARK, - - USB0_PWEN_IMARK, - SIM0_RST_C_MARK, - TS_SCK1_D_MARK, - STP_ISCLK_1_D_MARK, - BPFCLK_B_MARK, - RIF3_CLK_B_MARK, - FSO_CFE_1_A_MARK, - HSCK2_C_MARK, - - USB0_OVC_IMARK, - SIM0_D_C_MARK, - TS_SDAT1_D_MARK, - STP_ISD_1_D_MARK, - RIF3_SYNC_B_MARK, - HRX2_C_MARK, - - USB1_PWEN_IMARK, - SIM0_CLK_C_MARK, - SSI_SCK1_A_MARK, - TS_SCK0_E_MARK, - STP_ISCLK_0_E_MARK, - FMCLK_B_MARK, - RIF2_CLK_B_MARK, - SPEEDIN_A_MARK, - HTX2_C_MARK, - - USB1_OVC_IMARK, - MSIOF1_SS2_C_MARK, - SSI_WS1_A_MARK, - TS_SDAT0_E_MARK, - STP_ISD_0_E_MARK, - FMIN_B_MARK, - RIF2_SYNC_B_MARK, - REMOCON_B_MARK, - HCTS2x_C_MARK, - - USB30_PWEN_IMARK, - AUDIO_CLKOUT_B_MARK, - SSI_SCK2_B_MARK, - TS_SDEN1_D_MARK, - STP_ISEN_1_D_MARK, - STP_OPWM_0_E_MARK, - RIF3_D0_B_MARK, - TCLK2_B_MARK, - TPU0TO0_MARK, - BPFCLK_C_MARK, - HRTS2x_C_MARK, - - USB30_OVC_IMARK, - AUDIO_CLKOUT1_B_MARK, - SSI_WS2_B_MARK, - TS_SPSYNC1_D_MARK, - STP_ISSYNC_1_D_MARK, - STP_IVCXO27_0_E_MARK, - RIF3_D1_B_MARK, - FSO_TOE_B_MARK, - TPU0TO1_MARK, - - /* IPSR18 */ - GP6_30_IMARK, - AUDIO_CLKOUT2_B_MARK, - SSI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - FSO_CFE_0_A_MARK, - TPU0TO2_MARK, - FMCLK_C_MARK, - FMCLK_D_MARK, - - GP6_31_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - FMIN_C_MARK, - FMIN_D_MARK, - - PINMUX_MARK_END, -}; - -static pinmux_enum_t pinmux_data[] = { - PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ - - /* GPSR0 */ - PINMUX_DATA(D15_GMARK, GFN_D15), - PINMUX_DATA(D14_GMARK, GFN_D14), - PINMUX_DATA(D13_GMARK, GFN_D13), - PINMUX_DATA(D12_GMARK, GFN_D12), - PINMUX_DATA(D11_GMARK, GFN_D11), - PINMUX_DATA(D10_GMARK, GFN_D10), - PINMUX_DATA(D9_GMARK, GFN_D9), - PINMUX_DATA(D8_GMARK, GFN_D8), - PINMUX_DATA(D7_GMARK, GFN_D7), - PINMUX_DATA(D6_GMARK, GFN_D6), - PINMUX_DATA(D5_GMARK, GFN_D5), - PINMUX_DATA(D4_GMARK, GFN_D4), - PINMUX_DATA(D3_GMARK, GFN_D3), - PINMUX_DATA(D2_GMARK, GFN_D2), - PINMUX_DATA(D1_GMARK, GFN_D1), - PINMUX_DATA(D0_GMARK, GFN_D0), - - /* GPSR1 */ - PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), - PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), - PINMUX_DATA(WE1x_GMARK, GFN_WE1x), - PINMUX_DATA(WE0x_GMARK, GFN_WE0x), - PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), - PINMUX_DATA(RDx_GMARK, GFN_RDx), - PINMUX_DATA(BSx_GMARK, GFN_BSx), - PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), - PINMUX_DATA(CS0x_GMARK, GFN_CS0x), - PINMUX_DATA(A19_GMARK, GFN_A19), - PINMUX_DATA(A18_GMARK, GFN_A18), - PINMUX_DATA(A17_GMARK, GFN_A17), - PINMUX_DATA(A16_GMARK, GFN_A16), - PINMUX_DATA(A15_GMARK, GFN_A15), - PINMUX_DATA(A14_GMARK, GFN_A14), - PINMUX_DATA(A13_GMARK, GFN_A13), - PINMUX_DATA(A12_GMARK, GFN_A12), - PINMUX_DATA(A11_GMARK, GFN_A11), - PINMUX_DATA(A10_GMARK, GFN_A10), - PINMUX_DATA(A9_GMARK, GFN_A9), - PINMUX_DATA(A8_GMARK, GFN_A8), - PINMUX_DATA(A7_GMARK, GFN_A7), - PINMUX_DATA(A6_GMARK, GFN_A6), - PINMUX_DATA(A5_GMARK, GFN_A5), - PINMUX_DATA(A4_GMARK, GFN_A4), - PINMUX_DATA(A3_GMARK, GFN_A3), - PINMUX_DATA(A2_GMARK, GFN_A2), - PINMUX_DATA(A1_GMARK, GFN_A1), - PINMUX_DATA(A0_GMARK, GFN_A0), - - /* GPSR2 */ - PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), - PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), - PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), - PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), - PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), - PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), - PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), - PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), - PINMUX_DATA(PWM0_GMARK, GFN_PWM0), - PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), - PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), - PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), - PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), - PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), - PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), - - /* GPSR3 */ - PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), - PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), - PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), - PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), - PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), - PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), - PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), - PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), - PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), - PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), - PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), - PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), - PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), - PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), - PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), - PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), - - /* GPSR4 */ - PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), - PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), - PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), - PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), - PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD), - PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK), - PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), - PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), - PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), - PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), - PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD), - PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), - - /* GPSR5 */ - PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), - PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), - PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), - PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), - PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), - PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), - PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), - PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), - PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), - PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), - PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), - PINMUX_DATA(HTX0_GMARK, GFN_HTX0), - PINMUX_DATA(HRX0_GMARK, GFN_HRX0), - PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), - PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), - PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), - PINMUX_DATA(SCK2_GMARK, GFN_SCK2), - PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), - PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), - PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), - PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), - PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), - PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), - PINMUX_DATA(TX0_GMARK, GFN_TX0), - PINMUX_DATA(RX0_GMARK, GFN_RX0), - PINMUX_DATA(SCK0_GMARK, GFN_SCK0), - - /* GPSR6 */ - PINMUX_DATA(GP6_30_GMARK, GFN_GP6_30), - PINMUX_DATA(GP6_31_GMARK, GFN_GP6_31), - PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), - PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), - PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), - PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), - PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), - PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), - PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), - PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), - PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), - PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), - PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), - PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), - PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), - PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), - PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), - PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), - PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), - PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), - PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), - PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), - PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), - PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), - PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), - PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), - PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), - PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), - PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), - PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), - PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), - - /* GPSR7 */ - PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), - PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), - PINMUX_DATA(AVS2_MARK, FN_AVS2), - PINMUX_DATA(AVS1_MARK, FN_AVS1), - - /* ipsr setting .. underconstruction */ -}; - -static struct pinmux_gpio pinmux_gpios[] = { - PINMUX_GPIO_GP_ALL(), - /* GPSR0 */ - GPIO_GFN(D15), - GPIO_GFN(D14), - GPIO_GFN(D13), - GPIO_GFN(D12), - GPIO_GFN(D11), - GPIO_GFN(D10), - GPIO_GFN(D9), - GPIO_GFN(D8), - GPIO_GFN(D7), - GPIO_GFN(D6), - GPIO_GFN(D5), - GPIO_GFN(D4), - GPIO_GFN(D3), - GPIO_GFN(D2), - GPIO_GFN(D1), - GPIO_GFN(D0), - /* GPSR1 */ - GPIO_GFN(CLKOUT), - GPIO_GFN(EX_WAIT0_A), - GPIO_GFN(WE1x), - GPIO_GFN(WE0x), - GPIO_GFN(RD_WRx), - GPIO_GFN(RDx), - GPIO_GFN(BSx), - GPIO_GFN(CS1x_A26), - GPIO_GFN(CS0x), - GPIO_GFN(A19), - GPIO_GFN(A18), - GPIO_GFN(A17), - GPIO_GFN(A16), - GPIO_GFN(A15), - GPIO_GFN(A14), - GPIO_GFN(A13), - GPIO_GFN(A12), - GPIO_GFN(A11), - GPIO_GFN(A10), - GPIO_GFN(A9), - GPIO_GFN(A8), - GPIO_GFN(A7), - GPIO_GFN(A6), - GPIO_GFN(A5), - GPIO_GFN(A4), - GPIO_GFN(A3), - GPIO_GFN(A2), - GPIO_GFN(A1), - GPIO_GFN(A0), - - /* GPSR2 */ - GPIO_GFN(AVB_AVTP_CAPTURE_A), - GPIO_GFN(AVB_AVTP_MATCH_A), - GPIO_GFN(AVB_LINK), - GPIO_GFN(AVB_PHY_INT), - GPIO_GFN(AVB_MAGIC), - GPIO_GFN(AVB_MDC), - GPIO_GFN(PWM2_A), - GPIO_GFN(PWM1_A), - GPIO_GFN(PWM0), - GPIO_GFN(IRQ5), - GPIO_GFN(IRQ4), - GPIO_GFN(IRQ3), - GPIO_GFN(IRQ2), - GPIO_GFN(IRQ1), - GPIO_GFN(IRQ0), - - /* GPSR3 */ - GPIO_GFN(SD1_WP), - GPIO_GFN(SD1_CD), - GPIO_GFN(SD0_WP), - GPIO_GFN(SD0_CD), - GPIO_GFN(SD1_DAT3), - GPIO_GFN(SD1_DAT2), - GPIO_GFN(SD1_DAT1), - GPIO_GFN(SD1_DAT0), - GPIO_GFN(SD1_CMD), - GPIO_GFN(SD1_CLK), - GPIO_GFN(SD0_DAT3), - GPIO_GFN(SD0_DAT2), - GPIO_GFN(SD0_DAT1), - GPIO_GFN(SD0_DAT0), - GPIO_GFN(SD0_CMD), - GPIO_GFN(SD0_CLK), - - /* GPSR4 */ - GPIO_GFN(SD3_DS), - GPIO_GFN(SD3_DAT7), - GPIO_GFN(SD3_DAT6), - GPIO_GFN(SD3_DAT5), - GPIO_GFN(SD3_DAT4), - GPIO_FN(SD3_DAT3), - GPIO_FN(SD3_DAT2), - GPIO_FN(SD3_DAT1), - GPIO_FN(SD3_DAT0), - GPIO_FN(SD3_CMD), - GPIO_FN(SD3_CLK), - GPIO_GFN(SD2_DS), - GPIO_GFN(SD2_DAT3), - GPIO_GFN(SD2_DAT2), - GPIO_GFN(SD2_DAT1), - GPIO_GFN(SD2_DAT0), - GPIO_FN(SD2_CMD), - GPIO_GFN(SD2_CLK), - - /* GPSR5 */ - GPIO_GFN(MLB_DAT), - GPIO_GFN(MLB_SIG), - GPIO_GFN(MLB_CLK), - GPIO_FN(MSIOF0_RXD), - GPIO_GFN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TXD), - GPIO_GFN(MSIOF0_SS1), - GPIO_GFN(MSIOF0_SYNC), - GPIO_FN(MSIOF0_SCK), - GPIO_GFN(HRTS0x), - GPIO_GFN(HCTS0x), - GPIO_GFN(HTX0), - GPIO_GFN(HRX0), - GPIO_GFN(HSCK0), - GPIO_GFN(RX2_A), - GPIO_GFN(TX2_A), - GPIO_GFN(SCK2), - GPIO_GFN(RTS1x_TANS), - GPIO_GFN(CTS1x), - GPIO_GFN(TX1_A), - GPIO_GFN(RX1_A), - GPIO_GFN(RTS0x_TANS), - GPIO_GFN(CTS0x), - GPIO_GFN(TX0), - GPIO_GFN(RX0), - GPIO_GFN(SCK0), - - /* GPSR6 */ - GPIO_GFN(GP6_30), - GPIO_GFN(GP6_31), - GPIO_GFN(USB30_OVC), - GPIO_GFN(USB30_PWEN), - GPIO_GFN(USB1_OVC), - GPIO_GFN(USB1_PWEN), - GPIO_GFN(USB0_OVC), - GPIO_GFN(USB0_PWEN), - GPIO_GFN(AUDIO_CLKB_B), - GPIO_GFN(AUDIO_CLKA_A), - GPIO_GFN(SSI_SDATA9_A), - GPIO_GFN(SSI_SDATA8), - GPIO_GFN(SSI_SDATA7), - GPIO_GFN(SSI_WS78), - GPIO_GFN(SSI_SCK78), - GPIO_GFN(SSI_SDATA6), - GPIO_GFN(SSI_WS6), - GPIO_GFN(SSI_SCK6), - GPIO_FN(SSI_SDATA5), - GPIO_FN(SSI_WS5), - GPIO_FN(SSI_SCK5), - GPIO_GFN(SSI_SDATA4), - GPIO_GFN(SSI_WS4), - GPIO_GFN(SSI_SCK4), - GPIO_GFN(SSI_SDATA3), - GPIO_GFN(SSI_WS34), - GPIO_GFN(SSI_SCK34), - GPIO_GFN(SSI_SDATA2_A), - GPIO_GFN(SSI_SDATA1_A), - GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS01239), - GPIO_GFN(SSI_SCK01239), - - /* GPSR7 */ - GPIO_FN(HDMI1_CEC), - GPIO_FN(HDMI0_CEC), - GPIO_FN(AVS2), - GPIO_FN(AVS1), - - /* IPSR0 */ - GPIO_IFN(AVB_MDC), - GPIO_FN(MSIOF2_SS2_C), - GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_SS1_C), - GPIO_FN(SCK4_A), - GPIO_IFN(AVB_PHY_INT), - GPIO_FN(MSIOF2_SYNC_C), - GPIO_FN(RX4_A), - GPIO_IFN(AVB_LINK), - GPIO_FN(MSIOF2_SCK_C), - GPIO_FN(TX4_A), - GPIO_IFN(AVB_AVTP_MATCH_A), - GPIO_FN(MSIOF2_RXD_C), - GPIO_FN(CTS4x_A), - GPIO_IFN(AVB_AVTP_CAPTURE_A), - GPIO_FN(MSIOF2_TXD_C), - GPIO_FN(RTS4x_TANS_A), - GPIO_IFN(IRQ0), - GPIO_FN(QPOLB), - GPIO_FN(DU_CDE), - GPIO_FN(VI4_DATA0_B), - GPIO_FN(CAN0_TX_B), - GPIO_FN(CANFD0_TX_B), - GPIO_FN(MSIOF3_SS2_E), - GPIO_IFN(IRQ1), - GPIO_FN(QPOLA), - GPIO_FN(DU_DISP), - GPIO_FN(VI4_DATA1_B), - GPIO_FN(CAN0_RX_B), - GPIO_FN(CANFD0_RX_B), - GPIO_FN(MSIOF3_SS1_E), - - /* IPSR1 */ - GPIO_IFN(IRQ2), - GPIO_FN(QCPV_QDE), - GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), - GPIO_FN(VI4_DATA2_B), - GPIO_FN(MSIOF3_SYNC_E), - GPIO_FN(PWM3_B), - GPIO_IFN(IRQ3), - GPIO_FN(QSTVB_QVE), - GPIO_FN(DU_DOTCLKOUT1), - GPIO_FN(VI4_DATA3_B), - GPIO_FN(MSIOF3_SCK_E), - GPIO_FN(PWM4_B), - GPIO_IFN(IRQ4), - GPIO_FN(QSTH_QHS), - GPIO_FN(DU_EXHSYNC_DU_HSYNC), - GPIO_FN(VI4_DATA4_B), - GPIO_FN(MSIOF3_RXD_E), - GPIO_FN(PWM5_B), - GPIO_IFN(IRQ5), - GPIO_FN(QSTB_QHE), - GPIO_FN(DU_EXVSYNC_DU_VSYNC), - GPIO_FN(VI4_DATA5_B), - GPIO_FN(MSIOF3_TXD_E), - GPIO_FN(PWM6_B), - GPIO_IFN(PWM0), - GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(VI4_DATA6_B), - GPIO_FN(IECLK_B), - GPIO_IFN(PWM1_A), - GPIO_FN(HRX3_D), - GPIO_FN(VI4_DATA7_B), - GPIO_FN(IERX_B), - GPIO_IFN(PWM2_A), - GPIO_FN(PWMFSW0), - GPIO_FN(HTX3_D), - GPIO_FN(IETX_B), - GPIO_IFN(A0), - GPIO_FN(LCDOUT16), - GPIO_FN(MSIOF3_SYNC_B), - GPIO_FN(VI4_DATA8), - GPIO_FN(DU_DB0), - GPIO_FN(PWM3_A), - - /* IPSR2 */ - GPIO_IFN(A1), - GPIO_FN(LCDOUT17), - GPIO_FN(MSIOF3_TXD_B), - GPIO_FN(VI4_DATA9), - GPIO_FN(DU_DB1), - GPIO_FN(PWM4_A), - GPIO_IFN(A2), - GPIO_FN(LCDOUT18), - GPIO_FN(MSIOF3_SCK_B), - GPIO_FN(VI4_DATA10), - GPIO_FN(DU_DB2), - GPIO_FN(PWM5_A), - GPIO_IFN(A3), - GPIO_FN(LCDOUT19), - GPIO_FN(MSIOF3_RXD_B), - GPIO_FN(VI4_DATA11), - GPIO_FN(DU_DB3), - GPIO_FN(PWM6_A), - GPIO_IFN(A4), - GPIO_FN(LCDOUT20), - GPIO_FN(MSIOF3_SS1_B), - GPIO_FN(VI4_DATA12), - GPIO_FN(VI5_DATA12), - GPIO_FN(DU_DB4), - GPIO_IFN(A5), - GPIO_FN(LCDOUT21), - GPIO_FN(MSIOF3_SS2_B), - GPIO_FN(SCK4_B), - GPIO_FN(VI4_DATA13), - GPIO_FN(VI5_DATA13), - GPIO_FN(DU_DB5), - GPIO_IFN(A6), - GPIO_FN(LCDOUT22), - GPIO_FN(MSIOF2_SS1_A), - GPIO_FN(RX4_B), - GPIO_FN(VI4_DATA14), - GPIO_FN(VI5_DATA14), - GPIO_FN(DU_DB6), - GPIO_IFN(A7), - GPIO_FN(LCDOUT23), - GPIO_FN(MSIOF2_SS2_A), - GPIO_FN(TX4_B), - GPIO_FN(VI4_DATA15), - GPIO_FN(V15_DATA15), - GPIO_FN(DU_DB7), - GPIO_IFN(A8), - GPIO_FN(RX3_B), - GPIO_FN(MSIOF2_SYNC_A), - GPIO_FN(HRX4_B), - GPIO_FN(SDA6_A), - GPIO_FN(AVB_AVTP_MATCH_B), - GPIO_FN(PWM1_B), - - /* IPSR3 */ - GPIO_IFN(A9), - GPIO_FN(MSIOF2_SCK_A), - GPIO_FN(CTS4x_B), - GPIO_FN(VI5_VSYNCx), - GPIO_IFN(A10), - GPIO_FN(MSIOF2_RXD_A), - GPIO_FN(RTS4n_TANS_B), - GPIO_FN(VI5_HSYNCx), - GPIO_IFN(A11), - GPIO_FN(TX3_B), - GPIO_FN(MSIOF2_TXD_A), - GPIO_FN(HTX4_B), - GPIO_FN(HSCK4), - GPIO_FN(VI5_FIELD), - GPIO_FN(SCL6_A), - GPIO_FN(AVB_AVTP_CAPTURE_B), - GPIO_FN(PWM2_B), - GPIO_FN(SPV_EVEN), - GPIO_IFN(A12), - GPIO_FN(LCDOUT12), - GPIO_FN(MSIOF3_SCK_C), - GPIO_FN(HRX4_A), - GPIO_FN(VI5_DATA8), - GPIO_FN(DU_DG4), - GPIO_IFN(A13), - GPIO_FN(LCDOUT13), - GPIO_FN(MSIOF3_SYNC_C), - GPIO_FN(HTX4_A), - GPIO_FN(VI5_DATA9), - GPIO_FN(DU_DG5), - GPIO_IFN(A14), - GPIO_FN(LCDOUT14), - GPIO_FN(MSIOF3_RXD_C), - GPIO_FN(HCTS4x), - GPIO_FN(VI5_DATA10), - GPIO_FN(DU_DG6), - GPIO_IFN(A15), - GPIO_FN(LCDOUT15), - GPIO_FN(MSIOF3_TXD_C), - GPIO_FN(HRTS4x), - GPIO_FN(VI5_DATA11), - GPIO_FN(DU_DG7), - GPIO_IFN(A16), - GPIO_FN(LCDOUT8), - GPIO_FN(VI4_FIELD), - GPIO_FN(DU_DG0), - - /* IPSR4 */ - GPIO_IFN(A17), - GPIO_FN(LCDOUT9), - GPIO_FN(VI4_VSYNCx), - GPIO_FN(DU_DG1), - GPIO_IFN(A18), - GPIO_FN(LCDOUT10), - GPIO_FN(VI4_HSYNCx), - GPIO_FN(DU_DG2), - GPIO_IFN(A19), - GPIO_FN(LCDOUT11), - GPIO_FN(VI4_CLKENB), - GPIO_FN(DU_DG3), - GPIO_IFN(CS0x), - GPIO_FN(VI5_CLKENB), - GPIO_IFN(CS1x_A26), - GPIO_FN(VI5_CLK), - GPIO_FN(EX_WAIT0_B), - GPIO_IFN(BSx), - GPIO_FN(QSTVA_QVS), - GPIO_FN(MSIOF3_SCK_D), - GPIO_FN(SCK3), - GPIO_FN(HSCK3), - GPIO_FN(CAN1_TX), - GPIO_FN(CANFD1_TX), - GPIO_FN(IETX_A), - GPIO_IFN(RDx), - GPIO_FN(MSIOF3_SYNC_D), - GPIO_FN(RX3_A), - GPIO_FN(HRX3_A), - GPIO_FN(CAN0_TX_A), - GPIO_FN(CANFD0_TX_A), - GPIO_IFN(RD_WRx), - GPIO_FN(MSIOF3_RXD_D), - GPIO_FN(TX3_A), - GPIO_FN(HTX3_A), - GPIO_FN(CAN0_RX_A), - GPIO_FN(CANFD0_RX_A), - - /* IPSR5 */ - GPIO_IFN(WE0x), - GPIO_FN(MSIIOF3_TXD_D), - GPIO_FN(CTS3x), - GPIO_FN(HCTS3x), - GPIO_FN(SCL6_B), - GPIO_FN(CAN_CLK), - GPIO_FN(IECLK_A), - GPIO_IFN(WE1x), - GPIO_FN(MSIOF3_SS1_D), - GPIO_FN(RTS3x_TANS), - GPIO_FN(HRTS3x), - GPIO_FN(SDA6_B), - GPIO_FN(CAN1_RX), - GPIO_FN(CANFD1_RX), - GPIO_FN(IERX_A), - GPIO_IFN(EX_WAIT0_A), - GPIO_FN(QCLK), - GPIO_FN(VI4_CLK), - GPIO_FN(DU_DOTCLKOUT0), - GPIO_IFN(D0), - GPIO_FN(MSIOF2_SS1_B), - GPIO_FN(MSIOF3_SCK_A), - GPIO_FN(VI4_DATA16), - GPIO_FN(VI5_DATA0), - GPIO_IFN(D1), - GPIO_FN(MSIOF2_SS2_B), - GPIO_FN(MSIOF3_SYNC_A), - GPIO_FN(VI4_DATA17), - GPIO_FN(VI5_DATA1), - GPIO_IFN(D2), - GPIO_FN(MSIOF3_RXD_A), - GPIO_FN(VI4_DATA18), - GPIO_FN(VI5_DATA2), - GPIO_IFN(D3), - GPIO_FN(MSIOF3_TXD_A), - GPIO_FN(VI4_DATA19), - GPIO_FN(VI5_DATA3), - GPIO_IFN(D4), - GPIO_FN(MSIOF2_SCK_B), - GPIO_FN(VI4_DATA20), - GPIO_FN(VI5_DATA4), - - /* IPSR6 */ - GPIO_IFN(D5), - GPIO_FN(MSIOF2_SYNC_B), - GPIO_FN(VI4_DATA21), - GPIO_FN(VI5_DATA5), - GPIO_IFN(D6), - GPIO_FN(MSIOF2_RXD_B), - GPIO_FN(VI4_DATA22), - GPIO_FN(VI5_DATA6), - GPIO_IFN(D7), - GPIO_FN(MSIOF2_TXD_B), - GPIO_FN(VI4_DATA23), - GPIO_FN(VI5_DATA7), - GPIO_IFN(D8), - GPIO_FN(LCDOUT0), - GPIO_FN(MSIOF2_SCK_D), - GPIO_FN(SCK4_C), - GPIO_FN(VI4_DATA0_A), - GPIO_FN(DU_DR0), - GPIO_IFN(D9), - GPIO_FN(LCDOUT1), - GPIO_FN(MSIOF2_SYNC_D), - GPIO_FN(VI4_DATA1_A), - GPIO_FN(DU_DR1), - GPIO_IFN(D10), - GPIO_FN(LCDOUT2), - GPIO_FN(MSIOF2_RXD_D), - GPIO_FN(HRX3_B), - GPIO_FN(VI4_DATA2_A), - GPIO_FN(CTS4x_C), - GPIO_FN(DU_DR2), - GPIO_IFN(D11), - GPIO_FN(LCDOUT3), - GPIO_FN(MSIOF2_TXD_D), - GPIO_FN(HTX3_B), - GPIO_FN(VI4_DATA3_A), - GPIO_FN(RTS4x_TANS_C), - GPIO_FN(DU_DR3), - GPIO_IFN(D12), - GPIO_FN(LCDOUT4), - GPIO_FN(MSIOF2_SS1_D), - GPIO_FN(RX4_C), - GPIO_FN(VI4_DATA4_A), - GPIO_FN(DU_DR4), - - /* IPSR7 */ - GPIO_IFN(D13), - GPIO_FN(LCDOUT5), - GPIO_FN(MSIOF2_SS2_D), - GPIO_FN(TX4_C), - GPIO_FN(VI4_DATA5_A), - GPIO_FN(DU_DR5), - GPIO_IFN(D14), - GPIO_FN(LCDOUT6), - GPIO_FN(MSIOF3_SS1_A), - GPIO_FN(HRX3_C), - GPIO_FN(VI4_DATA6_A), - GPIO_FN(DU_DR6), - GPIO_FN(SCL6_C), - GPIO_IFN(D15), - GPIO_FN(LCDOUT7), - GPIO_FN(MSIOF3_SS2_A), - GPIO_FN(HTX3_C), - GPIO_FN(VI4_DATA7_A), - GPIO_FN(DU_DR7), - GPIO_FN(SDA6_C), - GPIO_FN(FSCLKST), - GPIO_IFN(SD0_CLK), - GPIO_FN(MSIOF1_SCK_E), - GPIO_FN(STP_OPWM_0_B), - GPIO_IFN(SD0_CMD), - GPIO_FN(MSIOF1_SYNC_E), - GPIO_FN(STP_IVCXO27_0_B), - GPIO_IFN(SD0_DAT0), - GPIO_FN(MSIOF1_RXD_E), - GPIO_FN(TS_SCK0_B), - GPIO_FN(STP_ISCLK_0_B), - GPIO_IFN(SD0_DAT1), - GPIO_FN(MSIOF1_TXD_E), - GPIO_FN(TS_SPSYNC0_B), - GPIO_FN(STP_ISSYNC_0_B), - - /* IPSR8 */ - GPIO_IFN(SD0_DAT2), - GPIO_FN(MSIOF1_SS1_E), - GPIO_FN(TS_SDAT0_B), - GPIO_FN(STP_ISD_0_B), - - GPIO_IFN(SD0_DAT3), - GPIO_FN(MSIOF1_SS2_E), - GPIO_FN(TS_SDEN0_B), - GPIO_FN(STP_ISEN_0_B), - - GPIO_IFN(SD1_CLK), - GPIO_FN(MSIOF1_SCK_G), - GPIO_FN(SIM0_CLK_A), - - GPIO_IFN(SD1_CMD), - GPIO_FN(MSIOF1_SYNC_G), - GPIO_FN(NFCEx_B), - GPIO_FN(SIM0_D_A), - GPIO_FN(STP_IVCXO27_1_B), - - GPIO_IFN(SD1_DAT0), - GPIO_FN(SD2_DAT4), - GPIO_FN(MSIOF1_RXD_G), - GPIO_FN(NFWPx_B), - GPIO_FN(TS_SCK1_B), - GPIO_FN(STP_ISCLK_1_B), - - GPIO_IFN(SD1_DAT1), - GPIO_FN(SD2_DAT5), - GPIO_FN(MSIOF1_TXD_G), - GPIO_FN(NFDATA14_B), - GPIO_FN(TS_SPSYNC1_B), - GPIO_FN(STP_ISSYNC_1_B), - - GPIO_IFN(SD1_DAT2), - GPIO_FN(SD2_DAT6), - GPIO_FN(MSIOF1_SS1_G), - GPIO_FN(NFDATA15_B), - GPIO_FN(TS_SDAT1_B), - GPIO_FN(STP_IOD_1_B), - - GPIO_IFN(SD1_DAT3), - GPIO_FN(SD2_DAT7), - GPIO_FN(MSIOF1_SS2_G), - GPIO_FN(NFRBx_B), - GPIO_FN(TS_SDEN1_B), - GPIO_FN(STP_ISEN_1_B), - - /* IPSR9 */ - GPIO_IFN(SD2_CLK), - GPIO_FN(NFDATA8), - - GPIO_IFN(SD2_CMD), - GPIO_FN(NFDATA9), - - GPIO_IFN(SD2_DAT0), - GPIO_FN(NFDATA10), - - GPIO_IFN(SD2_DAT1), - GPIO_FN(NFDATA11), - - GPIO_IFN(SD2_DAT2), - GPIO_FN(NFDATA12), - - GPIO_IFN(SD2_DAT3), - GPIO_FN(NFDATA13), - - GPIO_IFN(SD2_DS), - GPIO_FN(NFALE), - - GPIO_IFN(SD3_CLK), - GPIO_FN(NFWEx), - - /* IPSR10 */ - GPIO_IFN(SD3_CMD), - GPIO_FN(NFREx), - - GPIO_IFN(SD3_DAT0), - GPIO_FN(NFDATA0), - - GPIO_IFN(SD3_DAT1), - GPIO_FN(NFDATA1), - - GPIO_IFN(SD3_DAT2), - GPIO_FN(NFDATA2), - - GPIO_IFN(SD3_DAT3), - GPIO_FN(NFDATA3), - - GPIO_IFN(SD3_DAT4), - GPIO_FN(SD2_CD_A), - GPIO_FN(NFDATA4), - - GPIO_IFN(SD3_DAT5), - GPIO_FN(SD2_WP_A), - GPIO_FN(NFDATA5), - - GPIO_IFN(SD3_DAT6), - GPIO_FN(SD3_CD), - GPIO_FN(NFDATA6), - - /* IPSR11 */ - GPIO_IFN(SD3_DAT7), - GPIO_FN(SD3_WP), - GPIO_FN(NFDATA7), - - GPIO_IFN(SD3_DS), - GPIO_FN(NFCLE), - - GPIO_IFN(SD0_CD), - GPIO_FN(NFDATA14_A), - GPIO_FN(SCL2_B), - GPIO_FN(SIM0_RST_A), - - GPIO_IFN(SD0_WP), - GPIO_FN(NFDATA15_A), - GPIO_FN(SDA2_B), - - GPIO_IFN(SD1_CD), - GPIO_FN(NFRBx_A), - GPIO_FN(SIM0_CLK_B), - - GPIO_IFN(SD1_WP), - GPIO_FN(NFCEx_A), - GPIO_FN(SIM0_D_B), - - GPIO_IFN(SCK0), - GPIO_FN(HSCK1_B), - GPIO_FN(MSIOF1_SS2_B), - GPIO_FN(AUDIO_CLKC_B), - GPIO_FN(SDA2_A), - GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM_0_C), - GPIO_FN(RIF0_CLK_B), - GPIO_FN(ADICHS2), - GPIO_FN(SCK5_B), - - GPIO_IFN(RX0), - GPIO_FN(HRX1_B), - GPIO_FN(TS_SCK0_C), - GPIO_FN(STP_ISCLK_0_C), - GPIO_FN(RIF0_D0_B), - - /* IPSR12 */ - GPIO_IFN(TX0), - GPIO_FN(HTX1_B), - GPIO_FN(TS_SPSYNC0_C), - GPIO_FN(STP_ISSYNC_0_C), - GPIO_FN(RIF0_D1_B), - - GPIO_IFN(CTS0x), - GPIO_FN(HCTS1x_B), - GPIO_FN(MSIOF1_SYNC_B), - GPIO_FN(TS_SPSYNC1_C), - GPIO_FN(STP_ISSYNC_1_C), - GPIO_FN(RIF1_SYNC_B), - GPIO_FN(AUDIO_CLKOUT_C), - GPIO_FN(ADICS_SAMP), - - GPIO_IFN(RTS0x_TANS), - GPIO_FN(HRTS1x_B), - GPIO_FN(MSIOF1_SS1_B), - GPIO_FN(AUDIO_CLKA_B), - GPIO_FN(SCL2_A), - GPIO_FN(STP_IVCXO27_1_C), - GPIO_FN(RIF0_SYNC_B), - GPIO_FN(ADICHS1), - - GPIO_IFN(RX1_A), - GPIO_FN(HRX1_A), - GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_ISD_0_C), - GPIO_FN(RIF1_CLK_C), - - GPIO_IFN(TX1_A), - GPIO_FN(HTX1_A), - GPIO_FN(TS_SDEN0_C), - GPIO_FN(STP_ISEN_0_C), - GPIO_FN(RIF1_D0_C), - - GPIO_IFN(CTS1x), - GPIO_FN(HCTS1x_A), - GPIO_FN(MSIOF1_RXD_B), - GPIO_FN(TS_SDEN1_C), - GPIO_FN(STP_ISEN_1_C), - GPIO_FN(RIF1_D0_B), - GPIO_FN(ADIDATA), - - GPIO_IFN(RTS1x_TANS), - GPIO_FN(HRTS1x_A), - GPIO_FN(MSIOF1_TXD_B), - GPIO_FN(TS_SDAT1_C), - GPIO_FN(STP_ISD_1_C), - GPIO_FN(RIF1_D1_B), - GPIO_FN(ADICHS0), - - GPIO_IFN(SCK2), - GPIO_FN(SCIF_CLK_B), - GPIO_FN(MSIOF1_SCK_B), - GPIO_FN(TS_SCK1_C), - GPIO_FN(STP_ISCLK_1_C), - GPIO_FN(RIF1_CLK_B), - GPIO_FN(ADICLK), - - /* IPSR13 */ - GPIO_IFN(TX2_A), - GPIO_FN(SD2_CD_B), - GPIO_FN(SCL1_A), - GPIO_FN(FMCLK_A), - GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0_B), - - GPIO_IFN(RX2_A), - GPIO_FN(SD2_WP_B), - GPIO_FN(SDA1_A), - GPIO_FN(FMIN_A), - GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CEF_1_B), - - GPIO_IFN(HSCK0), - GPIO_FN(MSIOF1_SCK_D), - GPIO_FN(AUDIO_CLKB_A), - GPIO_FN(SSI_SDATA1_B), - GPIO_FN(TS_SCK0_D), - GPIO_FN(STP_ISCLK_0_D), - GPIO_FN(RIF0_CLK_C), - GPIO_FN(RX5_B), - - GPIO_IFN(HRX0), - GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SS1_SDATA2_B), - GPIO_FN(TS_SDEN0_D), - GPIO_FN(STP_ISEN_0_D), - GPIO_FN(RIF0_D0_C), - - GPIO_IFN(HTX0), - GPIO_FN(MSIOF1_TXD_D), - GPIO_FN(SSI_SDATA9_B), - GPIO_FN(TS_SDAT0_D), - GPIO_FN(STP_ISD_0_D), - GPIO_FN(RIF0_D1_C), - - GPIO_IFN(HCTS0x), - GPIO_FN(RX2_B), - GPIO_FN(MSIOF1_SYNC_D), - GPIO_FN(SSI_SCK9_A), - GPIO_FN(TS_SPSYNC0_D), - GPIO_FN(STP_ISSYNC_0_D), - GPIO_FN(RIF0_SYNC_C), - GPIO_FN(AUDIO_CLKOUT1_A), - - GPIO_IFN(HRTS0x), - GPIO_FN(TX2_B), - GPIO_FN(MSIOF1_SS1_D), - GPIO_FN(SSI_WS9_A), - GPIO_FN(STP_IVCXO27_0_D), - GPIO_FN(BPFCLK_A), - GPIO_FN(AUDIO_CLKOUT2_A), - - GPIO_IFN(MSIOF0_SYNC), - GPIO_FN(AUDIO_CLKOUT_A), - GPIO_FN(TX5_B), - GPIO_FN(BPFCLK_D), - - /* IPSR14 */ - GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5_A), - GPIO_FN(NFWPx_A), - GPIO_FN(AUDIO_CLKA_C), - GPIO_FN(SSI_SCK2_A), - GPIO_FN(STP_IVCXO27_0_C), - GPIO_FN(AUDIO_CLKOUT3_A), - GPIO_FN(TCLK1_B), - - GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5_A), - GPIO_FN(MSIOF1_SS2_D), - GPIO_FN(AUDIO_CLKC_A), - GPIO_FN(SSI_WS2_A), - GPIO_FN(STP_OPWM_0_D), - GPIO_FN(AUDIO_CLKOUT_D), - GPIO_FN(SPEEDIN_B), - - GPIO_IFN(MLB_CLK), - GPIO_FN(MSIOF1_SCK_F), - GPIO_FN(SCL1_B), - - GPIO_IFN(MLB_SIG), - GPIO_FN(RX1_B), - GPIO_FN(MSIOF1_SYNC_F), - GPIO_FN(SDA1_B), - - GPIO_IFN(MLB_DAT), - GPIO_FN(TX1_B), - GPIO_FN(MSIOF1_RXD_F), - - GPIO_IFN(SSI_SCK0129), - GPIO_FN(MSIOF1_TXD_F), - GPIO_FN(MOUT0), - - GPIO_IFN(SSI_WS0129), - GPIO_FN(MSIOF1_SS1_F), - GPIO_FN(MOUT1), - - GPIO_IFN(SSI_SDATA0), - GPIO_FN(MSIOF1_SS2_F), - GPIO_FN(MOUT2), - - /* IPSR15 */ - GPIO_IFN(SSI_SDATA1_A), - GPIO_FN(MOUT5), - - GPIO_IFN(SSI_SDATA2_A), - GPIO_FN(SSI_SCK1_B), - GPIO_FN(MOUT6), - - GPIO_IFN(SSI_SCK34), - GPIO_FN(MSIOF1_SS1_A), - GPIO_FN(STP_OPWM_0_A), - - GPIO_IFN(SSI_WS34), - GPIO_FN(HCTS2x_A), - GPIO_FN(MSIOF1_SS2_A), - GPIO_FN(STP_IVCXO27_0_A), - - GPIO_IFN(SSI_SDATA3), - GPIO_FN(HRTS2x_A), - GPIO_FN(MSIOF1_TXD_A), - GPIO_FN(TS_SCK0_A), - GPIO_FN(STP_ISCLK_0_A), - GPIO_FN(RIF0_D1_A), - GPIO_FN(RIF2_D0_A), - - GPIO_IFN(SSI_SCK4), - GPIO_FN(HRX2_A), - GPIO_FN(MSIOF1_SCK_A), - GPIO_FN(TS_SDAT0_A), - GPIO_FN(STP_ISD_0_A), - GPIO_FN(RIF0_CLK_A), - GPIO_FN(RIF2_CLK_A), - - GPIO_IFN(SSI_WS4), - GPIO_FN(HTX2_A), - GPIO_FN(MSIOF1_SYNC_A), - GPIO_FN(TS_SDEN0_A), - GPIO_FN(STP_ISEN_0_A), - GPIO_FN(RIF0_SYNC_A), - GPIO_FN(RIF2_SYNC_A), - - GPIO_IFN(SSI_SDATA4), - GPIO_FN(HSCK2_A), - GPIO_FN(MSIOF1_RXD_A), - GPIO_FN(TS_SPSYNC0_A), - GPIO_FN(STP_ISSYNC_0_A), - GPIO_FN(RIF0_D0_A), - GPIO_FN(RIF2_D1_A), - - /* IPSR16 */ - GPIO_IFN(SSI_SCK6), - GPIO_FN(SIM0_RST_D), - GPIO_FN(FSO_TOE_A), - - GPIO_IFN(SSI_WS6), - GPIO_FN(SIM0_D_D), - - GPIO_IFN(SSI_SDATA6), - GPIO_FN(SIM0_CLK_D), - - GPIO_IFN(SSI_SCK78), - GPIO_FN(HRX2_B), - GPIO_FN(MSIOF1_SCK_C), - GPIO_FN(TS_SCK1_A), - GPIO_FN(STP_ISCLK_1_A), - GPIO_FN(RIF1_CLK_A), - GPIO_FN(RIF3_CLK_A), - - GPIO_IFN(SSI_WS78), - GPIO_FN(HTX2_B), - GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDAT1_A), - GPIO_FN(STP_ISD_1_A), - GPIO_FN(RIF1_SYNC_A), - GPIO_FN(RIF3_SYNC_A), - - GPIO_IFN(SSI_SDATA7), - GPIO_FN(HCTS2x_B), - GPIO_FN(MSIOF1_RXD_C), - GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_IEN_1_A), - GPIO_FN(RIF1_D0_A), - GPIO_FN(RIF3_D0_A), - GPIO_FN(TCLK2_A), - - GPIO_IFN(SSI_SDATA8), - GPIO_FN(HRTS2x_B), - GPIO_FN(MSIOF1_TXD_C), - GPIO_FN(TS_SPSYNC1_A), - GPIO_FN(STP_ISSYNC_1_A), - GPIO_FN(RIF1_D1_A), - GPIO_FN(EIF3_D1_A), - - GPIO_IFN(SSI_SDATA9_A), - GPIO_FN(HSCK2_B), - GPIO_FN(MSIOF1_SS1_C), - GPIO_FN(HSCK1_A), - GPIO_FN(SSI_WS1_B), - GPIO_FN(SCK1), - GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5), - - /* IPSR17 */ - GPIO_IFN(AUDIO_CLKA_A), - GPIO_FN(CC5_OSCOUT), - - GPIO_IFN(AUDIO_CLKB_B), - GPIO_FN(SCIF_CLK_A), - GPIO_FN(STP_IVCXO27_1_D), - GPIO_FN(REMOCON_A), - GPIO_FN(TCLK1_A), - - GPIO_IFN(USB0_PWEN), - GPIO_FN(SIM0_RST_C), - GPIO_FN(TS_SCK1_D), - GPIO_FN(STP_ISCLK_1_D), - GPIO_FN(BPFCLK_B), - GPIO_FN(RIF3_CLK_B), - GPIO_FN(FSO_CFE_1_A), - GPIO_FN(HSCK2_C), - - GPIO_IFN(USB0_OVC), - GPIO_FN(SIM0_D_C), - GPIO_FN(TS_SDAT1_D), - GPIO_FN(STP_ISD_1_D), - GPIO_FN(RIF3_SYNC_B), - GPIO_FN(HRX2_C), - - GPIO_IFN(USB1_PWEN), - GPIO_FN(SIM0_CLK_C), - GPIO_FN(SSI_SCK1_A), - GPIO_FN(TS_SCK0_E), - GPIO_FN(STP_ISCLK_0_E), - GPIO_FN(FMCLK_B), - GPIO_FN(RIF2_CLK_B), - GPIO_FN(SPEEDIN_A), - GPIO_FN(HTX2_C), - - GPIO_IFN(USB1_OVC), - GPIO_FN(MSIOF1_SS2_C), - GPIO_FN(SSI_WS1_A), - GPIO_FN(TS_SDAT0_E), - GPIO_FN(STP_ISD_0_E), - GPIO_FN(FMIN_B), - GPIO_FN(RIF2_SYNC_B), - GPIO_FN(REMOCON_B), - GPIO_FN(HCTS2x_C), - - GPIO_IFN(USB30_PWEN), - GPIO_FN(AUDIO_CLKOUT_B), - GPIO_FN(SSI_SCK2_B), - GPIO_FN(TS_SDEN1_D), - GPIO_FN(STP_ISEN_1_D), - GPIO_FN(STP_OPWM_0_E), - GPIO_FN(RIF3_D0_B), - GPIO_FN(TCLK2_B), - GPIO_FN(TPU0TO0), - GPIO_FN(BPFCLK_C), - GPIO_FN(HRTS2x_C), - - GPIO_IFN(USB30_OVC), - GPIO_FN(AUDIO_CLKOUT1_B), - GPIO_FN(SSI_WS2_B), - GPIO_FN(TS_SPSYNC1_D), - GPIO_FN(STP_ISSYNC_1_D), - GPIO_FN(STP_IVCXO27_0_E), - GPIO_FN(RIF3_D1_B), - GPIO_FN(FSO_TOE_B), - GPIO_FN(TPU0TO1), - - /* IPSR18 */ - GPIO_IFN(GP6_30), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SSI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(FSO_CFE_0_A), - GPIO_FN(TPU0TO2), - GPIO_FN(FMCLK_C), - GPIO_FN(FMCLK_D), - - GPIO_IFN(GP6_31), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), - GPIO_FN(FMIN_C), - GPIO_FN(FMIN_D), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - /* GPSR0(0xE6060100) md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0000FFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_FN, GFN_D15, - GP_0_14_FN, GFN_D14, - GP_0_13_FN, GFN_D13, - GP_0_12_FN, GFN_D12, - GP_0_11_FN, GFN_D11, - GP_0_10_FN, GFN_D10, - GP_0_9_FN, GFN_D9, - GP_0_8_FN, GFN_D8, - GP_0_7_FN, GFN_D7, - GP_0_6_FN, GFN_D6, - GP_0_5_FN, GFN_D5, - GP_0_4_FN, GFN_D4, - GP_0_3_FN, GFN_D3, - GP_0_2_FN, GFN_D2, - GP_0_1_FN, GFN_D1, - GP_0_0_FN, GFN_D0 } - }, - /* GPSR1(0xE6060104) is md[3:1] controls initial value */ - /* md[3:1] .. 0 : 0x0EFFFFFF */ - /* .. other : 0x00000000 */ - { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_FN, GFN_CLKOUT, - GP_1_27_FN, GFN_EX_WAIT0_A, - GP_1_26_FN, GFN_WE1x, - GP_1_25_FN, GFN_WE0x, - GP_1_24_FN, GFN_RD_WRx, - GP_1_23_FN, GFN_RDx, - GP_1_22_FN, GFN_BSx, - GP_1_21_FN, GFN_CS1x_A26, - GP_1_20_FN, GFN_CS0x, - GP_1_19_FN, GFN_A19, - GP_1_18_FN, GFN_A18, - GP_1_17_FN, GFN_A17, - GP_1_16_FN, GFN_A16, - GP_1_15_FN, GFN_A15, - GP_1_14_FN, GFN_A14, - GP_1_13_FN, GFN_A13, - GP_1_12_FN, GFN_A12, - GP_1_11_FN, GFN_A11, - GP_1_10_FN, GFN_A10, - GP_1_9_FN, GFN_A9, - GP_1_8_FN, GFN_A8, - GP_1_7_FN, GFN_A7, - GP_1_6_FN, GFN_A6, - GP_1_5_FN, GFN_A5, - GP_1_4_FN, GFN_A4, - GP_1_3_FN, GFN_A3, - GP_1_2_FN, GFN_A2, - GP_1_1_FN, GFN_A1, - GP_1_0_FN, GFN_A0 } - }, - /* GPSR2(0xE6060108) is md[3:1] controls */ - /* md[3:1] .. 0 : 0x000003C0 */ - /* .. other : 0x00000200 */ - { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, - GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, - GP_2_12_FN, GFN_AVB_LINK, - GP_2_11_FN, GFN_AVB_PHY_INT, - GP_2_10_FN, GFN_AVB_MAGIC, - GP_2_9_FN, GFN_AVB_MDC, - GP_2_8_FN, GFN_PWM2_A, - GP_2_7_FN, GFN_PWM1_A, - GP_2_6_FN, GFN_PWM0, - GP_2_5_FN, GFN_IRQ5, - GP_2_4_FN, GFN_IRQ4, - GP_2_3_FN, GFN_IRQ3, - GP_2_2_FN, GFN_IRQ2, - GP_2_1_FN, GFN_IRQ1, - GP_2_0_FN, GFN_IRQ0 } - }, - - /* GPSR3 */ - { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_FN, GFN_SD1_WP, - GP_3_14_FN, GFN_SD1_CD, - GP_3_13_FN, GFN_SD0_WP, - GP_3_12_FN, GFN_SD0_CD, - GP_3_11_FN, GFN_SD1_DAT3, - GP_3_10_FN, GFN_SD1_DAT2, - GP_3_9_FN, GFN_SD1_DAT1, - GP_3_8_FN, GFN_SD1_DAT0, - GP_3_7_FN, GFN_SD1_CMD, - GP_3_6_FN, GFN_SD1_CLK, - GP_3_5_FN, GFN_SD0_DAT3, - GP_3_4_FN, GFN_SD0_DAT2, - GP_3_3_FN, GFN_SD0_DAT1, - GP_3_2_FN, GFN_SD0_DAT0, - GP_3_1_FN, GFN_SD0_CMD, - GP_3_0_FN, GFN_SD0_CLK } - }, - /* GPSR4 */ - { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_FN, GFN_SD3_DS, - GP_4_16_FN, GFN_SD3_DAT7, - - GP_4_15_FN, GFN_SD3_DAT6, - GP_4_14_FN, GFN_SD3_DAT5, - GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, FN_SD3_DAT3, - GP_4_11_FN, FN_SD3_DAT2, - GP_4_10_FN, FN_SD3_DAT1, - GP_4_9_FN, FN_SD3_DAT0, - GP_4_8_FN, FN_SD3_CMD, - GP_4_7_FN, FN_SD3_CLK, - GP_4_6_FN, GFN_SD2_DS, - GP_4_5_FN, GFN_SD2_DAT3, - GP_4_4_FN, GFN_SD2_DAT2, - GP_4_3_FN, GFN_SD2_DAT1, - GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, FN_SD2_CMD, - GP_4_0_FN, GFN_SD2_CLK } - }, - /* GPSR5 */ - { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_FN, GFN_MLB_DAT, - GP_5_24_FN, GFN_MLB_SIG, - - GP_5_23_FN, GFN_MLB_CLK, - GP_5_22_FN, FN_MSIOF0_RXD, - GP_5_21_FN, GFN_MSIOF0_SS2, - GP_5_20_FN, FN_MSIOF0_TXD, - GP_5_19_FN, GFN_MSIOF0_SS1, - GP_5_18_FN, GFN_MSIOF0_SYNC, - GP_5_17_FN, FN_MSIOF0_SCK, - GP_5_16_FN, GFN_HRTS0x, - GP_5_15_FN, GFN_HCTS0x, - GP_5_14_FN, GFN_HTX0, - GP_5_13_FN, GFN_HRX0, - GP_5_12_FN, GFN_HSCK0, - GP_5_11_FN, GFN_RX2_A, - GP_5_10_FN, GFN_TX2_A, - GP_5_9_FN, GFN_SCK2, - GP_5_8_FN, GFN_RTS1x_TANS, - GP_5_7_FN, GFN_CTS1x, - GP_5_6_FN, GFN_TX1_A, - GP_5_5_FN, GFN_RX1_A, - GP_5_4_FN, GFN_RTS0x_TANS, - GP_5_3_FN, GFN_CTS0x, - GP_5_2_FN, GFN_TX0, - GP_5_1_FN, GFN_RX0, - GP_5_0_FN, GFN_SCK0 } - }, - /* GPSR6 */ - { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_GP6_31, - GP_6_30_FN, GFN_GP6_30, - GP_6_29_FN, GFN_USB30_OVC, - GP_6_28_FN, GFN_USB30_PWEN, - GP_6_27_FN, GFN_USB1_OVC, - GP_6_26_FN, GFN_USB1_PWEN, - GP_6_25_FN, GFN_USB0_OVC, - GP_6_24_FN, GFN_USB0_PWEN, - GP_6_23_FN, GFN_AUDIO_CLKB_B, - GP_6_22_FN, GFN_AUDIO_CLKA_A, - GP_6_21_FN, GFN_SSI_SDATA9_A, - GP_6_20_FN, GFN_SSI_SDATA8, - GP_6_19_FN, GFN_SSI_SDATA7, - GP_6_18_FN, GFN_SSI_WS78, - GP_6_17_FN, GFN_SSI_SCK78, - GP_6_16_FN, GFN_SSI_SDATA6, - GP_6_15_FN, GFN_SSI_WS6, - GP_6_14_FN, GFN_SSI_SCK6, - GP_6_13_FN, FN_SSI_SDATA5, - GP_6_12_FN, FN_SSI_WS5, - GP_6_11_FN, FN_SSI_SCK5, - GP_6_10_FN, GFN_SSI_SDATA4, - GP_6_9_FN, GFN_SSI_WS4, - GP_6_8_FN, GFN_SSI_SCK4, - GP_6_7_FN, GFN_SSI_SDATA3, - GP_6_6_FN, GFN_SSI_WS34, - GP_6_5_FN, GFN_SSI_SCK34, - GP_6_4_FN, GFN_SSI_SDATA2_A, - GP_6_3_FN, GFN_SSI_SDATA1_A, - GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS01239, - GP_6_0_FN, GFN_SSI_SCK01239 } - }, - /* GPSR7 */ - { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_7_3_FN, FN_HDMI1_CEC, - GP_7_2_FN, FN_HDMI0_CEC, - GP_7_1_FN, FN_AVS2, - GP_7_0_FN, FN_AVS1 } - }, - { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR0_31_28 [4] */ - IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, - FN_MSIOF3_SS1_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_27_24 [4] */ - IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, - FN_MSIOF3_SS2_E, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_23_20 [4] */ - IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_19_16 [4] */ - IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_15_12 [4] */ - IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_11_8 [4] */ - IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR0_3_0 [4] */ - IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR1_31_28 [4] */ - IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, - FN_VI4_DATA8, 0, FN_DU_DB0, 0, - 0, FN_PWM3_A, 0, 0, - 0, 0, 0, 0, - /* IPSR1_27_24 [4] */ - IFN_PWM2_A, FN_PWMFSW0, 0, FN_HTX3_D, - 0, 0, 0, 0, - 0, FN_IETX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, 0, FN_HRX3_D, - FN_VI4_DATA7_B, 0, 0, 0, - 0, FN_IERX_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, - FN_VI4_DATA6_B, 0, 0, 0, - 0, FN_IECLK_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, 0, 0, FN_MSIOF3_TXD_E, - 0, FN_PWM6_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, - 0, FN_PWM5_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, - 0, FN_PWM4_B, 0, 0, - 0, 0, 0, 0, - /* IPSR1_3_0 [4] */ - IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, - 0, FN_PWM3_B, 0, 0, - 0, 0, 0, 0 - } - }, - { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR2_31_28 [4] */ - IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, - 0, 0, 0, FN_SDA6_A, - FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR2_27_24 [4] */ - IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, - FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_23_20 [4] */ - IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, - FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_19_16 [4] */ - IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, - FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_15_12 [4] */ - IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, - FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR2_11_8 [4] */ - IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, - FN_VI4_DATA11, 0, FN_DU_DB3, 0, - 0, FN_PWM6_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_7_4 [4] */ - IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, - FN_VI4_DATA10, 0, FN_DU_DB2, 0, - 0, FN_PWM5_A, 0, 0, - 0, 0, 0, 0, - /* IPSR2_3_0 [4] */ - IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, - FN_VI4_DATA9, 0, FN_DU_DB1, 0, - 0, FN_PWM4_A, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR3_31_28 [4] */ - IFN_A16, FN_LCDOUT8, 0, 0, - FN_VI4_FIELD, 0, FN_DU_DG0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_27_24 [4] */ - IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, - FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_23_20 [4] */ - IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, - FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_19_16 [4] */ - IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, - FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_15_12 [4] */ - IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, - FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_11_8 [4] */ - IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, - FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0, - 0, 0, 0, 0, - /* IPSR3_7_4 [4] */ - IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, - 0, FN_VI5_HSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR3_3_0 [4] */ - IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, - 0, FN_VI5_VSYNCx, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR4_31_28 [4] */ - IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, - FN_HTX3_A, 0, 0, 0, - FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_27_24 [4] */ - IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, - FN_HRX3_A, 0, 0, 0, - FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, - 0, 0, 0, 0, - /* IPSR4_23_20 [4] */ - IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, - FN_HSCK3, 0, 0, 0, - FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, - 0, 0, 0, 0, - /* IPSR4_19_16 [4] */ - IFN_CS1x_A26, 0, 0, 0, - 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_15_12 [4] */ - IFN_CS0x, 0, 0, 0, - 0, FN_VI5_CLKENB, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_11_8 [4] */ - IFN_A19, FN_LCDOUT11, 0, 0, - FN_VI4_CLKENB, 0, FN_DU_DG3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_7_4 [4] */ - IFN_A18, FN_LCDOUT10, 0, 0, - FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR4_3_0 [4] */ - IFN_A17, FN_LCDOUT9, 0, 0, - FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR5_31_28 [4] */ - IFN_D4, FN_MSIOF2_SCK_B, 0, 0, - FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_27_24 [4] */ - IFN_D3, 0, FN_MSIOF3_TXD_A, 0, - FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_23_20 [4] */ - IFN_D2, 0, FN_MSIOF3_RXD_A, 0, - FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_19_16 [4] */ - IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, - FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_15_12 [4] */ - IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, - FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_11_8 [4] */ - IFN_EX_WAIT0_A, FN_QCLK, 0, 0, - FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR5_7_4 [4] */ - IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, - FN_HRTS3x, 0, 0, FN_SDA6_B, - FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, - 0, 0, 0, 0, - /* IPSR5_3_0 [4] */ - IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, - FN_HCTS3x, 0, 0, FN_SCL6_B, - FN_CAN_CLK, 0, FN_IECLK_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR6_31_28 [4] */ - IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, - FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_27_24 [4] */ - IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, - FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_23_20 [4] */ - IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, - FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_19_16 [4] */ - IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, - FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_15_12 [4] */ - IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, - FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_11_8 [4] */ - IFN_D7, FN_MSIOF2_TXD_B, 0, 0, - FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_7_4 [4] */ - IFN_D6, FN_MSIOF2_RXD_B, 0, 0, - FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR6_3_0 [4] */ - IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, - FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR7_31_28 [4] */ - IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, - 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_27_24 [4] */ - IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, - 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_23_20 [4] */ - IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, - 0, 0, FN_STP_IVCXO27_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_19_16 [4] */ - IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, - 0, 0, FN_STP_OPWM_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_15_12 [4] */ - FN_FSCLKST, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_11_8 [4] */ - IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, - FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_7_4 [4] */ - IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, - FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR7_3_0 [4] */ - IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, - FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, - FN_NFRBx_B, - 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, - FN_NFDATA15_B, - 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, - FN_NFDATA14_B, - 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, - FN_NFWPx_B, - 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, - FN_NFCEx_B, - 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_11_8 [4] */ - IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, - 0, FN_SIM0_CLK_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_7_4 [4] */ - IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, - 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR8_3_0 [4] */ - IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, - 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR9_31_28 [4] */ - IFN_SD3_CLK, 0, FN_NFWEx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_27_24 [4] */ - IFN_SD2_DS, 0, FN_NFALE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_23_20 [4] */ - IFN_SD2_DAT3, 0, FN_NFDATA13, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_19_16 [4] */ - IFN_SD2_DAT2, 0, FN_NFDATA12, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_15_12 [4] */ - IFN_SD2_DAT1, 0, FN_NFDATA11, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_11_8 [4] */ - IFN_SD2_DAT0, 0, FN_NFDATA10, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_7_4 [4] */ - IFN_SD2_CMD, 0, FN_NFDATA9, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR9_3_0 [4] */ - IFN_SD3_CLK, 0, FN_NFDATA8, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR10_31_28 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_27_24 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_23_20 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_19_16 [4] */ - IFN_SD3_DAT3, 0, FN_NFDATA3, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_15_12 [4] */ - IFN_SD3_DAT2, 0, FN_NFDATA2, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_11_8 [4] */ - IFN_SD3_DAT1, 0, FN_NFDATA1, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_7_4 [4] */ - IFN_SD3_DAT0, 0, FN_NFDATA0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR10_3_0 [4] */ - IFN_SD3_CMD, 0, FN_NFREx, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR11_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, - FN_RIF0_CLK_B, - 0, FN_ADICHS2, 0, FN_RIF0_CLK_B, - 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ - IFN_SD1_WP, 0, FN_NFCEx_A, 0, - 0, FN_SIM0_D_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_19_16 [4] */ - IFN_SD1_CD, 0, FN_NFRBx_A, 0, - 0, FN_SIM0_CLK_B, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ - IFN_SD0_WP, 0, FN_NFDATA15_A, 0, - FN_SDA2_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ - IFN_SD0_CD, 0, FN_NFDATA14_A, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ - IFN_SD3_DS, 0, FN_NFCLE, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ - IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, - 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, - 0, FN_ADICLK, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ - IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, - 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, - 0, FN_ADICHS0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ - IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, - 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, - 0, FN_ADIDATA, 0, 0, - /* IPSR12_19_16 [4] */ - IFN_TX1_A, FN_HTX1_A, 0, 0, - 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ - IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ - IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, - FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, - 0, FN_ADICHS1, 0, 0, - 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ - IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, - 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, - FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, - 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ - IFN_TX0, FN_HTX1_B, 0, 0, - 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ - IFN_MSIOF0_SYNC, 0, 0, 0, - 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, - 0, FN_BPFCLK_D, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, - FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, - FN_AUDIO_CLKOUT2_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ - IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, - FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ - IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ - IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, - FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, 0, FN_RX5_B, 0, - 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CEF_1_B, 0, 0, - 0, 0, 0, 0, - /* IPSR13_3_0 [4] */ - IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0_B, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ - IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, - 0, 0, 0, FN_MOUT2, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ - IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, FN_MOUT1, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ - IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0, - 0, 0, 0, FN_MOUT0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ - IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ - IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, - FN_SDA1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ - IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, - FN_SCL1_B, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, - FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - /* IPSR14_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5_A, 0, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, - FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ - IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, - 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, - FN_RIF2_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ - IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, - 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, - FN_RIF2_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ - IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, - 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, - FN_RIF2_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_19_16 [4] */ - IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, - 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, - FN_RIF2_D0_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ - IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, - 0, 0, FN_STP_IVCXO27_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ - IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, - 0, 0, FN_STP_OPWM_0_A, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_SDATA2_A, 0, 0, 0, - FN_SSI_SCK1_B, 0, 0, FN_MOUT6, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SDATA1_A, 0, 0, 0, - 0, 0, 0, FN_MOUT5, - 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ - IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, - 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_EIF3_D1_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ - IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A, - FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - /* IPSR16_19_16 [4] */ - IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, - FN_RIF3_SYNC_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ - IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, - 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, - FN_RIF3_CLK_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ - IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ - IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ - IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, - 0, 0, 0, 0, - 0, 0, FN_FSO_TOE_A, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, - 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR17_31_28 [4] */ - IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1, - 0, 0, 0, 0, - /* IPSR17_27_24 [4] */ - IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, - FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, - FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, - /* IPSR17_23_20 [4] */ - IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, - FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, - 0, FN_HCTS2x_C, 0, 0, - /* IPSR17_19_16 [4] */ - IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, - FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, - 0, FN_HTX2_C, 0, 0, - /* IPSR17_15_12 [4] */ - IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, - 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, 0, - 0, FN_HRX2_C, 0, 0, - /* IPSR17_11_8 [4] */ - IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, - 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, 0, FN_FSO_CFE_1_A, 0, - 0, FN_HSCK2_C, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, 0, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_AUDIO_CLKA_A, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, FN_CC5_OSCOUT, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 4, 4) { - /* reserved [31..24] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [23..16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* reserved [15..8] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - /* IPSR18_7_4 [4] */ - IFN_GP6_31, 0, 0, FN_AUDIO_CLKOUT3_B, - FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, - FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - FN_FMIN_C, FN_FMIN_D, 0, 0, - /* IPSR18_3_0 [4] */ - IFN_GP6_30, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, - FN_RIF2_D0_B, 0, FN_FSO_CFE_0_A, FN_TPU0TO2, - FN_FMCLK_C, FN_FMCLK_D, 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 3, 2, 3, - 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, - 2, 1, 2, 1, 1, 1) { - /* SEL_MSIOF3 [3] */ - FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, - FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, - FN_SEL_MSIOF3_6, 0, - /* SEL_MSIOF2 [2] */ - FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, - FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* SEL_MSIOF1 [3] */ - FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, - FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, - FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, - FN_SEL_MSIOF1_6, 0, - - /* SEL_LBSC [1] */ - FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* SEL_IEBUS [1] */ - FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* SEL_I2C2 [1] */ - FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* SEL_I2C1 [1] */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* SEL_HSCIF4 [1] */ - FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* SEL_HSCIF3 [2] */ - FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, - FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* SEL_HSCIF1 [1] */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - - /* SEL_FSO [1] */ - FN_SEL_FSO_0, FN_SEL_FSO_1, - /* SEL_HSCIF2 [2] */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - FN_SEL_HSCIF2_2, 0, - /* SEL_ETHERAVB [1] */ - FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* SEL_DRIF3 [1] */ - FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* SEL_DRIF2 [1] */ - FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* SEL_DRIF1 [2] */ - FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, - FN_SEL_DRIF1_2, 0, - - /* SEL_DRIF0 [2] */ - FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, - FN_SEL_DRIF0_2, 0, - /* SEL_CANFD0 [1] */ - FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* SEL_ADG [2] */ - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - /* reserved [3] */ - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, - 2, 3, 1, 2, - 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { - /* SEL_TSIF1 [2] */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - /* SEL_TSIF0 [3] */ - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - 0, - 0, - 0, - /* SEL_TIMER_TMU [1] */ - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - /* SEL_SSP1_1 [2] */ - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - - /* SEL_SSP1_0 [3] */ - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - 0, - 0, - 0, - /* SEL_SSI [1] */ - FN_SEL_SSI_0, - FN_SEL_SSI_1, - /* SEL_SPEED_PULSE_IF [1] */ - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - /* SEL_SIMCARD [2] */ - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - /* SEL_SDHI2 [1] */ - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - - /* SEL_SCIF4 [2] */ - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - 0, - /* SEL_SCIF3 [1] */ - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - /* SEL_SCIF2 [1] */ - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - /* SEL_SCIF1 [1] */ - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - /* SEL_SCIF [1] */ - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - /* SEL_REMOCON [1] */ - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - /* reserved [2] */ - 0, 0, - - 0, 0, - /* SEL_RCAN [1] */ - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - /* SEL_PWM6 [1] */ - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - /* SEL_PWM5 [1] */ - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - /* SEL_PWM4 [1] */ - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - /* SEL_PWM3 [1] */ - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - /* SEL_PWM2 [1] */ - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - /* SEL_PWM1 [1] */ - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, - } - }, - { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 2, 1, - 3, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1) { - /* I2C_SEL_5 [1] */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - /* I2C_SEL_3 [1] */ - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - /* I2C_SEL_0 [1] */ - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - /* SEL_FM [2] */ - FN_SEL_FM_0, - FN_SEL_FM_1, - FN_SEL_FM_2, - FN_SEL_FM_3, - /* SEL_SCIF5 [1] */ - FN_SEL_SCIF5_0, - FN_SEL_SCIF5_1, - - /* SEL_I2C6 [3] */ - FN_SEL_I2C6_0, - FN_SEL_I2C6_1, - FN_SEL_I2C6_2, - 0, - 0, - 0, - 0, - 0, - /* SEL_NDF [1] */ - FN_SEL_NDF_0, - FN_SEL_NDF_1, - /* SEL_SSI2 [1] */ - FN_SEL_SSI2_0, - FN_SEL_SSI2_1, - /* SEL_SSI9 [1] */ - FN_SEL_SSI9_0, - FN_SEL_SSI9_1, - /* SEL_TIMER_TME2 [1] */ - FN_SEL_TIMER_TMU2_0, - FN_SEL_TIMER_TMU2_1, - /* SEL_ADG_B [1] */ - FN_SEL_ADG_B_0, - FN_SEL_ADG_B_1, - - /* SEL_ADG_C [1] */ - FN_SEL_ADG_C_0, - FN_SEL_ADG_C_1, - /* reserved [16] */ - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - /* SEL_VIN4 [1] */ - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, - } - }, - - /* under construction */ - { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_0_15_IN, GP_0_15_OUT, - GP_0_14_IN, GP_0_14_OUT, - GP_0_13_IN, GP_0_13_OUT, - GP_0_12_IN, GP_0_12_OUT, - GP_0_11_IN, GP_0_11_OUT, - GP_0_10_IN, GP_0_10_OUT, - GP_0_9_IN, GP_0_9_OUT, - GP_0_8_IN, GP_0_8_OUT, - GP_0_7_IN, GP_0_7_OUT, - GP_0_6_IN, GP_0_6_OUT, - GP_0_5_IN, GP_0_5_OUT, - GP_0_4_IN, GP_0_4_OUT, - GP_0_3_IN, GP_0_3_OUT, - GP_0_2_IN, GP_0_2_OUT, - GP_0_1_IN, GP_0_1_OUT, - GP_0_0_IN, GP_0_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - GP_1_28_IN, GP_1_28_OUT, - GP_1_27_IN, GP_1_27_OUT, - GP_1_26_IN, GP_1_26_OUT, - GP_1_25_IN, GP_1_25_OUT, - GP_1_24_IN, GP_1_24_OUT, - GP_1_23_IN, GP_1_23_OUT, - GP_1_22_IN, GP_1_22_OUT, - GP_1_21_IN, GP_1_21_OUT, - GP_1_20_IN, GP_1_20_OUT, - GP_1_19_IN, GP_1_19_OUT, - GP_1_18_IN, GP_1_18_OUT, - GP_1_17_IN, GP_1_17_OUT, - GP_1_16_IN, GP_1_16_OUT, - GP_1_15_IN, GP_1_15_OUT, - GP_1_14_IN, GP_1_14_OUT, - GP_1_13_IN, GP_1_13_OUT, - GP_1_12_IN, GP_1_12_OUT, - GP_1_11_IN, GP_1_11_OUT, - GP_1_10_IN, GP_1_10_OUT, - GP_1_9_IN, GP_1_9_OUT, - GP_1_8_IN, GP_1_8_OUT, - GP_1_7_IN, GP_1_7_OUT, - GP_1_6_IN, GP_1_6_OUT, - GP_1_5_IN, GP_1_5_OUT, - GP_1_4_IN, GP_1_4_OUT, - GP_1_3_IN, GP_1_3_OUT, - GP_1_2_IN, GP_1_2_OUT, - GP_1_1_IN, GP_1_1_OUT, - GP_1_0_IN, GP_1_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - GP_2_14_IN, GP_2_14_OUT, - GP_2_13_IN, GP_2_13_OUT, - GP_2_12_IN, GP_2_12_OUT, - GP_2_11_IN, GP_2_11_OUT, - GP_2_10_IN, GP_2_10_OUT, - GP_2_9_IN, GP_2_9_OUT, - GP_2_8_IN, GP_2_8_OUT, - GP_2_7_IN, GP_2_7_OUT, - GP_2_6_IN, GP_2_6_OUT, - GP_2_5_IN, GP_2_5_OUT, - GP_2_4_IN, GP_2_4_OUT, - GP_2_3_IN, GP_2_3_OUT, - GP_2_2_IN, GP_2_2_OUT, - GP_2_1_IN, GP_2_1_OUT, - GP_2_0_IN, GP_2_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - GP_3_15_IN, GP_3_15_OUT, - GP_3_14_IN, GP_3_14_OUT, - GP_3_13_IN, GP_3_13_OUT, - GP_3_12_IN, GP_3_12_OUT, - GP_3_11_IN, GP_3_11_OUT, - GP_3_10_IN, GP_3_10_OUT, - GP_3_9_IN, GP_3_9_OUT, - GP_3_8_IN, GP_3_8_OUT, - GP_3_7_IN, GP_3_7_OUT, - GP_3_6_IN, GP_3_6_OUT, - GP_3_5_IN, GP_3_5_OUT, - GP_3_4_IN, GP_3_4_OUT, - GP_3_3_IN, GP_3_3_OUT, - GP_3_2_IN, GP_3_2_OUT, - GP_3_1_IN, GP_3_1_OUT, - GP_3_0_IN, GP_3_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_4_17_IN, GP_4_17_OUT, - GP_4_16_IN, GP_4_16_OUT, - - GP_4_15_IN, GP_4_15_OUT, - GP_4_14_IN, GP_4_14_OUT, - GP_4_13_IN, GP_4_13_OUT, - GP_4_12_IN, GP_4_12_OUT, - GP_4_11_IN, GP_4_11_OUT, - GP_4_10_IN, GP_4_10_OUT, - GP_4_9_IN, GP_4_9_OUT, - GP_4_8_IN, GP_4_8_OUT, - GP_4_7_IN, GP_4_7_OUT, - GP_4_6_IN, GP_4_6_OUT, - GP_4_5_IN, GP_4_5_OUT, - GP_4_4_IN, GP_4_4_OUT, - GP_4_3_IN, GP_4_3_OUT, - GP_4_2_IN, GP_4_2_OUT, - GP_4_1_IN, GP_4_1_OUT, - GP_4_0_IN, GP_4_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_5_25_IN, GP_5_25_OUT, - GP_5_24_IN, GP_5_24_OUT, - - GP_5_23_IN, GP_5_23_OUT, - GP_5_22_IN, GP_5_22_OUT, - GP_5_21_IN, GP_5_21_OUT, - GP_5_20_IN, GP_5_20_OUT, - GP_5_19_IN, GP_5_19_OUT, - GP_5_18_IN, GP_5_18_OUT, - GP_5_17_IN, GP_5_17_OUT, - GP_5_16_IN, GP_5_16_OUT, - - GP_5_15_IN, GP_5_15_OUT, - GP_5_14_IN, GP_5_14_OUT, - GP_5_13_IN, GP_5_13_OUT, - GP_5_12_IN, GP_5_12_OUT, - GP_5_11_IN, GP_5_11_OUT, - GP_5_10_IN, GP_5_10_OUT, - GP_5_9_IN, GP_5_9_OUT, - GP_5_8_IN, GP_5_8_OUT, - GP_5_7_IN, GP_5_7_OUT, - GP_5_6_IN, GP_5_6_OUT, - GP_5_5_IN, GP_5_5_OUT, - GP_5_4_IN, GP_5_4_OUT, - GP_5_3_IN, GP_5_3_OUT, - GP_5_2_IN, GP_5_2_OUT, - GP_5_1_IN, GP_5_1_OUT, - GP_5_0_IN, GP_5_0_OUT, - } - }, - { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { - GP_INOUTSEL(6) - } - }, - { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - - 0, 0, - 0, 0, - 0, 0, - 0, 0, - GP_6_3_IN, GP_6_3_OUT, - GP_6_2_IN, GP_6_2_OUT, - GP_6_1_IN, GP_6_1_OUT, - GP_6_0_IN, GP_6_0_OUT, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - /* use OUTDT registers? */ - { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, - GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, - GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, - GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } - }, - { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, GP_1_28_DATA, - GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, - GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, - GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, - GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, - GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, - GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, - GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } - }, - { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, - GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, - GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, - GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } - }, - { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, - GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, - GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, - GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } - }, - { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, - GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, - GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, - GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, - GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } - }, - { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { - 0, 0, 0, 0, - 0, 0, GP_5_25_DATA, GP_5_24_DATA, - GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, - GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, - GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, - GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, - GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, - GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } - }, - { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { - GP_INDT(6) } - }, - { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } - }, - { }, -}; - -static struct pinmux_info r8a7796_pinmux_info = { - .name = "r8a7796_pfc", - - .unlock_reg = 0xe6060000, /* PMMR */ - - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_FMIN_D, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), -}; - -void r8a7796_pinmux_init(void) -{ - register_pinmux(&r8a7796_pinmux_info); -} diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a26736a5aca..1e74db36076 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,15 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3128 + bool "Support Rockchip RK3128" + select CPU_V7 + help + The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7 @@ -211,6 +220,7 @@ config SPL_MMC_SUPPORT default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 7e1f864383e..e1b0519b1f4 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -30,6 +30,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += boot_mode.o obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o @@ -43,6 +44,7 @@ obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 460dd6074e6..e5393ec50a8 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -34,10 +34,11 @@ struct rk3036_sdram_priv { struct rk3036_ddr_config ddr_config; }; -/* use integer mode, 396MHz dpll setting +/* + * use integer mode, dpll output 792MHz and ddr get 396MHz * refdiv, fbdiv, postdiv1, postdiv2 */ -const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; +const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; /* 396Mhz ddr timing */ const struct rk3036_ddr_timing ddr_timing = {0x18c, @@ -329,29 +330,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) struct rk3036_pll *pll = &priv->cru->pll[1]; /* pll enter slow-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); /* use integer mode */ - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | dpll_init_cfg.fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | - dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | + dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) rockchip_udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORM << DPLL_MODE_SHIFT); } diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c new file mode 100644 index 00000000000..2e8393d70a9 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/arch/grf_rk3128.h> +#include <asm/arch/boot_mode.h> +#include <asm/arch/timer.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +__weak int rk_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + setup_boot_mode(); + + return rk_board_late_init(); +} + +int board_init(void) +{ + int ret = 0; + + rockchip_timer_init(); + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0xe00000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + gd->ram_size - gd->bd->bi_dram[1].start; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3128_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3128-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3128-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3128_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) +int fb_set_reboot_flag(void) +{ + struct rk3128_grf *grf; + + printf("Setting reboot to fastboot flag ...\n"); + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, &grf->os_reg[0]); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig new file mode 100644 index 00000000000..40655a22b59 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -0,0 +1,24 @@ +if ROCKCHIP_RK3128 + +choice + prompt "RK3128 board select" + +config TARGET_EVB_RK3128 + bool "RK3128 evaluation board" + select BOARD_LATE_INIT + help + RK3128evb is a evaluation board for Rockchip rk3128, + with full function and phisical connectors support like + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3128/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile new file mode 100644 index 00000000000..50e11175423 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3128.o +obj-y += syscon_rk3128.o +obj-y += clk_rk3128.o diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c new file mode 100644 index 00000000000..7ca5fd34841 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3128.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3128_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3128_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c new file mode 100644 index 00000000000..9d6e3b1ee19 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/rk3128.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c new file mode 100644 index 00000000000..0b636390ac2 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3128_syscon_ids[] = { + { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3128) = { + .name = "rk3128_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3128_syscon_ids, +}; diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile index 0f5ac37168a..c2806af69b0 100644 --- a/arch/arm/mach-stm32/Makefile +++ b/arch/arm/mach-stm32/Makefile @@ -4,7 +4,6 @@ # # SPDX-License-Identifier: GPL-2.0+ # - +obj-y += soc.o obj-$(CONFIG_STM32F4) += stm32f4/ obj-$(CONFIG_STM32F7) += stm32f7/ -obj-$(CONFIG_STM32H7) += stm32h7/ diff --git a/arch/arm/mach-stm32/stm32h7/soc.c b/arch/arm/mach-stm32/soc.c index 692dbcc04a8..df20d547c50 100644 --- a/arch/arm/mach-stm32/stm32h7/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -9,11 +9,6 @@ #include <asm/io.h> #include <asm/armv7m_mpu.h> -u32 get_cpu_rev(void) -{ - return 0; -} - int arch_cpu_init(void) { int i; @@ -30,11 +25,11 @@ int arch_cpu_init(void) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_4GB }, - /* Code area, executable & strongly ordered */ - { 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_8MB }, + /* armv7m code area */ + { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, + STRONG_ORDER, REGION_512MB }, - /* Device area in all H7 : Not executable */ + /* Device area : Not executable */ { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, DEVICE_NON_SHARED, REGION_512MB }, @@ -42,8 +37,14 @@ int arch_cpu_init(void) * Armv7m fixed configuration: strongly ordered & not * executable, not cacheable */ - { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, + { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, STRONG_ORDER, REGION_512MB }, + +#if !defined(CONFIG_STM32H7) + /* Device area : Not executable */ + { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, + DEVICE_NON_SHARED, REGION_512MB }, +#endif }; disable_mpu(); @@ -53,7 +54,3 @@ int arch_cpu_init(void) return 0; } - -void s_init(void) -{ -} diff --git a/arch/arm/mach-stm32/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile index 020e78370c8..63db8200300 100644 --- a/arch/arm/mach-stm32/stm32f4/Makefile +++ b/arch/arm/mach-stm32/stm32f4/Makefile @@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += soc.o clock.o timer.o +obj-y += clock.o timer.o diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 15fcadbbe6f..774591d6a59 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h> @@ -81,32 +82,6 @@ #define RCC_ENR_GPIO_J_EN (1 << 9) #define RCC_ENR_GPIO_K_EN (1 << 10) -struct pll_psc { - u8 pll_m; - u16 pll_n; - u8 pll_p; - u8 pll_q; - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; -}; - -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 - #if !defined(CONFIG_STM32_HSE_HZ) #error "CONFIG_STM32_HSE_HZ not defined!" #else diff --git a/arch/arm/mach-stm32/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c deleted file mode 100644 index 9eb655a681f..00000000000 --- a/arch/arm/mach-stm32/stm32f4/soc.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m_mpu.h> -#include <asm/arch/stm32.h> - -u32 get_cpu_rev(void) -{ - return 0; -} - -int arch_cpu_init(void) -{ - struct mpu_region_config stm32_region_config[] = { - { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_4GB }, - }; - int i; - - configure_clocks(); - /* - * Configure the memory protection unit (MPU) to allow full access to - * the whole 4GB address space. - */ - disable_mpu(); - for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) - mpu_config(&stm32_region_config[i]); - enable_mpu(); - - return 0; -} - -void s_init(void) -{ -} diff --git a/arch/arm/mach-stm32/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c index 1dee190766b..163f4616d3f 100644 --- a/arch/arm/mach-stm32/stm32f4/timer.c +++ b/arch/arm/mach-stm32/stm32f4/timer.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile index 6696b267fe4..8132c132340 100644 --- a/arch/arm/mach-stm32/stm32f7/Makefile +++ b/arch/arm/mach-stm32/stm32f7/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += timer.o soc.o +obj-y += timer.o diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c deleted file mode 100644 index a960cc1cbfd..00000000000 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m_mpu.h> -#include <asm/arch/stm32.h> - -u32 get_cpu_rev(void) -{ - return 0; -} - -int arch_cpu_init(void) -{ - int i; - - struct mpu_region_config stm32_region_config[] = { - { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_4GB }, - - { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, - - { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, - - { 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, - - { 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, - }; - - disable_mpu(); - for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) - mpu_config(&stm32_region_config[i]); - enable_mpu(); - - return 0; -} - -void s_init(void) -{ -} diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c index 0521c24810b..69d37a7c708 100644 --- a/arch/arm/mach-stm32/stm32f7/timer.c +++ b/arch/arm/mach-stm32/stm32f7/timer.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/stm32_defs.h> diff --git a/arch/arm/mach-stm32/stm32h7/Makefile b/arch/arm/mach-stm32/stm32h7/Makefile deleted file mode 100644 index cba2e3be1ca..00000000000 --- a/arch/arm/mach-stm32/stm32h7/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2017, STMicroelectronics - All Rights Reserved -# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += soc.o diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts index fbe6d744371..b19ba988dbf 100644 --- a/arch/nds32/dts/ae3xx.dts +++ b/arch/nds32/dts/ae3xx.dts @@ -69,6 +69,14 @@ interrupts = <25 4>; }; + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + }; + nor@0,0 { compatible = "cfi-flash"; reg = <0x88000000 0x1000>; diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts index 99cde2f8b8f..19dc36fa157 100644 --- a/arch/nds32/dts/ag101p.dts +++ b/arch/nds32/dts/ag101p.dts @@ -60,4 +60,12 @@ reg = <0x90900000 0x1000>; interrupts = <25 4>; }; + + mmc0: mmc@98e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <30000000>; + fifo-depth = <0x10>; + reg = <0x98e00000 0x1000>; + interrupts = <5 4>; + }; }; diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 8835dcf36f1..472ada54907 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -34,9 +34,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64) -LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 -LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 - # This is used in the top-level Makefile which does not include # PLATFORM_LDFLAGS LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index e13786efa59..1c42584e76f 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -143,8 +143,8 @@ const char *cpu_vendor_name(int vendor) { const char *name; name = "<invalid cpu vendor>"; - if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && - (x86_vendor_name[vendor] != 0)) + if (vendor < ARRAY_SIZE(x86_vendor_name) && + x86_vendor_name[vendor]) name = x86_vendor_name[vendor]; return name; diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index da378128fec..81444f3d9e1 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -18,7 +18,7 @@ if QEMU config SYS_CAR_ADDR hex - default 0xd0000 + default 0x10000 config SYS_CAR_SIZE hex diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index fe00d7573f5..7d729ea0f7d 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o obj-$(CONFIG_EFI) += efi/ obj-y += e820.o -obj-y += gcc.o obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o @@ -49,12 +48,7 @@ endif obj-$(CONFIG_HAVE_FSP) += fsp/ obj-$(CONFIG_SPL_BUILD) += spl.o -extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a - -NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name) -OBJCOPYFLAGS := --prefix-symbols=__normal_ -$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE - $(call if_changed,objcopy) +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o ifeq ($(CONFIG_$(SPL_)X86_64),) obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index ecd4f4e6c61..e548cdbed59 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -109,7 +109,7 @@ static int boot_prep_linux(bootm_headers_t *images) } is_zimage = 1; #if defined(CONFIG_FIT) - } else if (images->fit_uname_os) { + } else if (images->fit_uname_os && is_zimage) { ret = fit_image_get_data(images->fit_hdr_os, images->fit_noffset_os, (const void **)&data, &len); diff --git a/arch/x86/lib/div64.c b/arch/x86/lib/div64.c new file mode 100644 index 00000000000..4efed74037e --- /dev/null +++ b/arch/x86/lib/div64.c @@ -0,0 +1,113 @@ +/* + * This file is copied from the coreboot repository as part of + * the libpayload project: + * + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common.h> + +union overlay64 { + u64 longw; + struct { + u32 lower; + u32 higher; + } words; +}; + +u64 __ashldi3(u64 num, unsigned int shift) +{ + union overlay64 output; + + output.longw = num; + if (shift >= 32) { + output.words.higher = output.words.lower << (shift - 32); + output.words.lower = 0; + } else { + if (!shift) + return num; + output.words.higher = (output.words.higher << shift) | + (output.words.lower >> (32 - shift)); + output.words.lower = output.words.lower << shift; + } + return output.longw; +} + +u64 __lshrdi3(u64 num, unsigned int shift) +{ + union overlay64 output; + + output.longw = num; + if (shift >= 32) { + output.words.lower = output.words.higher >> (shift - 32); + output.words.higher = 0; + } else { + if (!shift) + return num; + output.words.lower = output.words.lower >> shift | + (output.words.higher << (32 - shift)); + output.words.higher = output.words.higher >> shift; + } + return output.longw; +} + +#define MAX_32BIT_UINT ((((u64)1) << 32) - 1) + +static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p) +{ + u64 result = 0; + + /* + * If divider is zero - let the rest of the system care about the + * exception. + */ + if (!divider) + return 1 / (u32)divider; + + /* As an optimization, let's not use 64 bit division unless we must. */ + if (dividend <= MAX_32BIT_UINT) { + if (divider > MAX_32BIT_UINT) { + result = 0; + if (rem_p) + *rem_p = divider; + } else { + result = (u32)dividend / (u32)divider; + if (rem_p) + *rem_p = (u32)dividend % (u32)divider; + } + return result; + } + + while (divider <= dividend) { + u64 locald = divider; + u64 limit = __lshrdi3(dividend, 1); + int shifts = 0; + + while (locald <= limit) { + shifts++; + locald = locald + locald; + } + result |= __ashldi3(1, shifts); + dividend -= locald; + } + + if (rem_p) + *rem_p = dividend; + + return result; +} + +u64 __udivdi3(u64 num, u64 den) +{ + return _64bit_divide(num, den, NULL); +} + +u64 __umoddi3(u64 num, u64 den) +{ + u64 v = 0; + + _64bit_divide(num, den, &v); + return v; +} diff --git a/arch/x86/lib/gcc.c b/arch/x86/lib/gcc.c deleted file mode 100644 index 3c70d790d49..00000000000 --- a/arch/x86/lib/gcc.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifdef __GNUC__ - -/* - * GCC's libgcc handling is quite broken. While the libgcc functions - * are always regparm(0) the code that calls them uses whatever the - * compiler call specifies. Therefore we need a wrapper around those - * functions. See gcc bug PR41055 for more information. - */ -#define WRAP_LIBGCC_CALL(type, name) \ - type __normal_##name(type a, type b) __attribute__((regparm(0))); \ - type __wrap_##name(type a, type b); \ - type __attribute__((no_instrument_function)) \ - __wrap_##name(type a, type b) \ - { return __normal_##name(a, b); } - -WRAP_LIBGCC_CALL(long long, __divdi3) -WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) -WRAP_LIBGCC_CALL(long long, __moddi3) -WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) - -#endif |