diff options
Diffstat (limited to 'arch')
95 files changed, 1597 insertions, 712 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 4f5b75129f3..2e0528d819c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -134,7 +134,7 @@ config SANDBOX select ARCH_SUPPORTS_LTO select BOARD_LATE_INIT select BZIP2 - select CMD_POWEROFF + select CMD_POWEROFF if CMDLINE select DM select DM_EVENT select DM_FUZZING_ENGINE @@ -152,10 +152,10 @@ config SANDBOX select PCI_ENDPOINT select SPI select SUPPORT_OF_CONTROL - select SYSRESET_CMD_POWEROFF + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF select SYS_CACHE_SHIFT_4 select IRQ - select SUPPORT_EXTENSION_SCAN + select SUPPORT_EXTENSION_SCAN if CMDLINE select SUPPORT_ACPI imply BITREVERSE select BLOBLIST @@ -210,6 +210,9 @@ config SANDBOX imply BINMAN imply CMD_MBR imply CMD_MMC + imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE + imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE + imply CMD_SYSBOOT if BOOTSTD_FULL config SH bool "SuperH architecture" @@ -248,7 +251,7 @@ config X86 imply DM_KEYBOARD imply DM_MMC imply DM_RTC - imply DM_SCSI + imply SCSI imply DM_SERIAL imply DM_SPI imply DM_SPI_FLASH diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c984..1fd7aacc380 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -568,6 +568,7 @@ config ARCH_AT91 select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL + imply SYS_THUMB_BUILD config ARCH_DAVINCI bool "TI DaVinci" @@ -1133,7 +1134,6 @@ config ARCH_SUNXI select DM_SPI_FLASH if SPI select DM_KEYBOARD select DM_MMC if MMC - select DM_SCSI if SCSI select DM_SERIAL select OF_BOARD_SETUP select OF_CONTROL @@ -1838,7 +1838,7 @@ config TARGET_SL28 select PCI select DM_RNG select DM_RTC - select DM_SCSI + select SCSI select DM_SERIAL select DM_SPI select GPIO_EXTRA_HEADER @@ -1945,7 +1945,7 @@ config ARCH_STM32MP select REGMAP select SYSCON select SYSRESET - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if !ARM64 imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF @@ -2053,7 +2053,6 @@ config TARGET_POMELO select PCI select DM_PCI select SCSI - select DM_SCSI select DM_SERIAL imply CMD_PCI help diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc2..20767659376 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1381,6 +1381,9 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcor-drc-compact.dtb \ stm32mp15xx-dhcor-testbench.dtb +dtb-$(CONFIG_STM32MP25X) += \ + stm32mp257f-ev1.dtb + dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ k3-am654-r5-base-board.dtb \ diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi new file mode 100644 index 00000000000..d34a1d5e79c --- /dev/null +++ b/arch/arm/dts/stm32mp25-pinctrl.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi new file mode 100644 index 00000000000..f4f26add2a4 --- /dev/null +++ b/arch/arm/dts/stm32mp25-u-boot.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2023 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + firmware { + optee { + bootph-all; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + bootph-all; + }; + + soc@0 { + bootph-all; + }; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&syscfg { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi new file mode 100644 index 00000000000..cf2f28dc158 --- /dev/null +++ b/arch/arm/dts/stm32mp251.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi new file mode 100644 index 00000000000..af48e82efe8 --- /dev/null +++ b/arch/arm/dts/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi new file mode 100644 index 00000000000..e6fa596211f --- /dev/null +++ b/arch/arm/dts/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi new file mode 100644 index 00000000000..5c5000d3d9d --- /dev/null +++ b/arch/arm/dts/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi new file mode 100644 index 00000000000..a35a9b90388 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + */ + +#include "stm32mp25-u-boot.dtsi" + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts new file mode 100644 index 00000000000..a88494eed34 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 00000000000..abdbc7aebc7 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AI>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 00000000000..2e0d4d349d1 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AK>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 00000000000..2406e972554 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AL>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 3f0182e7665..d2fbf919a5b 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -7,6 +7,7 @@ #ifndef _CPU_H #define _CPU_H +#include <asm/arch/omap.h> #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 0eae857e73a..43f7503571d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -513,14 +513,6 @@ enum dcache_option { }; #endif -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK -#endif - /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE @@ -578,6 +570,14 @@ void psci_system_reset(void); #endif /* CONFIG_ARM64 */ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + #ifndef __ASSEMBLY__ /** * save_boot_params() - Save boot parameters before starting reset sequence diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 6dc27d1d589..9961472f69f 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -22,6 +22,7 @@ #include <cpu_func.h> #include <efi_loader.h> #include <irq_func.h> +#include <semihosting.h> #include <asm/global_data.h> #include <asm/proc-armv/ptrace.h> #include <asm/ptrace.h> @@ -135,6 +136,32 @@ static inline void fixup_pc(struct pt_regs *regs, int offset) regs->ARM_pc = pc | (regs->ARM_pc & PCMASK); } +/* + * Try to "emulate" a semihosting call in the event that we don't have a + * debugger attached. + */ +static bool smh_emulate_trap(struct pt_regs *regs) +{ + if (regs->ARM_cpsr & T_BIT) { + u16 *insn = (u16 *)(regs->ARM_pc - 2); + + if (*insn != SMH_T32_SVC) + return false; + } else { + u32 *insn = (u32 *)(regs->ARM_pc - 4); + + if (*insn != SMH_A32_SVC) + return false; + } + + /* Avoid future semihosting calls */ + disable_semihosting(); + + /* Just pretend the call failed */ + regs->ARM_r0 = -1; + return true; +} + void do_undefined_instruction (struct pt_regs *pt_regs) { efi_restore_gd(); @@ -147,6 +174,10 @@ void do_undefined_instruction (struct pt_regs *pt_regs) void do_software_interrupt (struct pt_regs *pt_regs) { + if (CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) && + smh_emulate_trap(pt_regs)) + return; + efi_restore_gd(); printf ("software interrupt\n"); fixup_pc(pt_regs, -4); diff --git a/arch/arm/lib/semihosting.S b/arch/arm/lib/semihosting.S index 393aade94a5..6e1691a832c 100644 --- a/arch/arm/lib/semihosting.S +++ b/arch/arm/lib/semihosting.S @@ -18,11 +18,17 @@ ENTRY(smh_trap) #elif defined(CONFIG_SYS_THUMB_BUILD) svc #0xab #else +#if CONFIG_SYS_ARM_ARCH < 7 + /* Before the ARMv7 exception model, svc (swi) clobbers lr */ + mov r2, lr +#endif svc #0x123456 #endif #if defined(CONFIG_ARM64) ret +#elif CONFIG_SYS_ARM_ARCH < 7 + bx r2 #else bx lr #endif diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 7cf7d1636f5..843f9b9c281 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -240,6 +240,18 @@ IRQ_STACK_START_IN: movs pc, lr @ jump to next instruction & switch modes. .endm + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, IRQ_STACK_START_IN @ get data regions start + str lr, [r0] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr lr, [r0] @ restore lr + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + .macro get_irq_stack @ setup IRQ stack ldr sp, IRQ_STACK_START .endm @@ -260,9 +272,16 @@ undefined_instruction: .align 5 software_interrupt: - get_bad_stack + get_bad_stack_swi bad_save_user_regs bl do_software_interrupt +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + movs pc, lr @ return & move spsr_svc into cpsr +#endif .align 5 prefetch_abort: diff --git a/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h index eb1488e7442..0cd13d8aaa5 100644 --- a/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h +++ b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h @@ -8,7 +8,6 @@ #ifndef __DM365_LOWLEVEL_H #define __DM365_LOWLEVEL_H -#include <common.h> #include <asm/arch/hardware.h> #include <asm/io.h> diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7529b311f80..50a9c3e4203 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -246,7 +246,7 @@ config TARGET_KOSAGI_NOVENA select DM_GPIO select DM_MMC select PCI - select DM_SCSI + select SCSI select VIDEO select OF_CONTROL select SUPPORT_SPL diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 5eb5a3d3c4a..b9ff9bb83b3 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -53,16 +53,10 @@ static int is_boot_from_stream_device(u32 boot) } static ulong spl_romapi_read_seekable(struct spl_load_info *load, - ulong sector, ulong count, + ulong offset, ulong byte, void *buf) { - u32 pagesize = *(u32 *)load->priv; - ulong byte = count * pagesize; - u32 offset; - - offset = sector * pagesize; - - return spl_romapi_raw_seekable_read(offset, byte, buf) / pagesize; + return spl_romapi_raw_seekable_read(offset, byte, buf); } static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, @@ -107,20 +101,18 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, struct spl_load_info load; memset(&load, 0, sizeof(load)); - load.bl_len = pagesize; + spl_set_bl_len(&load, pagesize); load.read = spl_romapi_read_seekable; - load.priv = &pagesize; - return spl_load_simple_fit(spl_image, &load, offset / pagesize, header); + return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; memset(&load, 0, sizeof(load)); - load.bl_len = pagesize; + spl_set_bl_len(&load, pagesize); load.read = spl_romapi_read_seekable; - load.priv = &pagesize; - ret = spl_load_imx_container(spl_image, &load, offset / pagesize); + ret = spl_load_imx_container(spl_image, &load, offset); } else { /* TODO */ puts("Can't support legacy image\n"); @@ -342,7 +334,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, ss.pagesize = pagesize; memset(&load, 0, sizeof(load)); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_romapi_read_stream; load.priv = &ss; @@ -366,7 +358,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, printf("ROM download failure %d\n", imagesize); memset(&load, 0, sizeof(load)); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_ram_load_read; if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h index 2341a713495..b4823a309fc 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h @@ -8,8 +8,6 @@ #ifndef _PINCTRL_SNAPDRAGON_H #define _PINCTRL_SNAPDRAGON_H -#include <common.h> - struct msm_pinctrl_data { int pin_count; int functions_count; diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c index 01b76f7493c..38db4f2f5c8 100644 --- a/arch/arm/mach-k3/am62ax/am62a_qos_data.c +++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c @@ -5,7 +5,6 @@ * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> #include <asm/arch/hardware.h> #include "common.h" diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index c871e92330b..6085379f1db 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -7,7 +7,6 @@ * Dave Gerlach <d-gerlach@ti.com> */ -#include <common.h> #include <fdt_support.h> #include <spl.h> #include <asm/io.h> diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c index 9353a475a49..4235296774c 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am654_init.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <fdt_support.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index f8087d2421e..14e7c896f91 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -9,7 +9,6 @@ * */ -#include <common.h> #include <asm/system.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index d8974d6c388..4c7b03fe6e0 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <cpu_func.h> #include <image.h> #include <init.h> diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 18814c39ec3..b4398c8e0b9 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <init.h> #include <spl.h> #include <asm/io.h> diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 7170a808c4b..39499be2715 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -6,7 +6,6 @@ * David Huang <d-huang@ti.com> */ -#include <common.h> #include <init.h> #include <spl.h> #include <asm/io.h> diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 605f7931518..2de5d28aebf 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -6,7 +6,6 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ -#include <common.h> #include <asm/io.h> #include <linux/kernel.h> #include "common.h" diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index ebc9704a33b..22697a263a8 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -7,7 +7,6 @@ */ #include <asm/io.h> -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <hang.h> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 73a17276e12..49a82c7edc7 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -6,7 +6,6 @@ * Andreas Dannenberg <dannenberg@ti.com> */ -#include <common.h> #include <dm.h> #include <image.h> #include <log.h> diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arch/arm/mach-keystone/include/mach/mux-k2g.h index 67d47f81721..dfb5ad43506 100644 --- a/arch/arm/mach-keystone/include/mach/mux-k2g.h +++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h @@ -9,7 +9,6 @@ #ifndef __ASM_ARCH_MUX_K2G_H #define __ASM_ARCH_MUX_K2G_H -#include <common.h> #include <asm/io.h> #define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 6deffb81836..8e0de935385 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -589,15 +589,6 @@ int board_ahci_enable(void) return 0; } -#ifdef CONFIG_SCSI_AHCI_PLAT -void scsi_init(void) -{ - printf("MVEBU SATA INIT\n"); - board_ahci_enable(); - ahci_init((void __iomem *)MVEBU_SATA0_BASE); -} -#endif - #ifdef CONFIG_USB_XHCI_MVEBU #define USB3_MAX_WINDOWS 4 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8)) diff --git a/arch/arm/mach-mvebu/include/mach/efuse.h b/arch/arm/mach-mvebu/include/mach/efuse.h index b125c30beb8..fd8ebceb26c 100644 --- a/arch/arm/mach-mvebu/include/mach/efuse.h +++ b/arch/arm/mach-mvebu/include/mach/efuse.h @@ -6,8 +6,6 @@ #ifndef _MVEBU_EFUSE_H #define _MVEBU_EFUSE_H -#include <common.h> - struct efuse_val { union { struct { diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bb01eab80e6..8c10c694dff 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -27,13 +27,6 @@ obj-y += vc.o obj-y += abb.o endif -ifneq ($(CONFIG_OMAP54XX),) -ifeq ($(CONFIG_DM_SCSI),) -obj-y += pipe3-phy.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o -endif -endif - ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index a68b21aeacc..57917da25cf 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -309,13 +309,6 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) } #endif -#ifdef CONFIG_SCSI_AHCI_PLAT -void arch_preboot_os(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); -} -#endif - #ifdef CONFIG_TI_SECURE_DEVICE void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index e6bee48dfcb..b39132222ee 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -485,9 +485,6 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, -#ifdef CONFIG_SCSI_AHCI_PLAT - (*prcm)->cm_l3init_ocp2scp3_clkctrl, -#endif 0 }; @@ -507,9 +504,6 @@ void enable_basic_clocks(void) #ifdef CONFIG_TI_QSPI (*prcm)->cm_l4per_qspi_clkctrl, #endif -#ifdef CONFIG_SCSI_AHCI_PLAT - (*prcm)->cm_l3init_sata_clkctrl, -#endif 0 }; @@ -542,12 +536,6 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); #endif -#ifdef CONFIG_SCSI_AHCI_PLAT - /* Enable optional functional clock for SATA */ - setbits_le32((*prcm)->cm_l3init_sata_clkctrl, - SATA_CLKCTRL_OPTFCLKEN_MASK); -#endif - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); diff --git a/arch/arm/mach-omap2/pipe3-phy.c b/arch/arm/mach-omap2/pipe3-phy.c deleted file mode 100644 index 3dfb184c430..00000000000 --- a/arch/arm/mach-omap2/pipe3-phy.c +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#include <common.h> -#include <sata.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include "pipe3-phy.h" - -/* PLLCTRL Registers */ -#define PLL_STATUS 0x00000004 -#define PLL_GO 0x00000008 -#define PLL_CONFIGURATION1 0x0000000C -#define PLL_CONFIGURATION2 0x00000010 -#define PLL_CONFIGURATION3 0x00000014 -#define PLL_CONFIGURATION4 0x00000020 - -#define PLL_REGM_MASK 0x001FFE00 -#define PLL_REGM_SHIFT 9 -#define PLL_REGM_F_MASK 0x0003FFFF -#define PLL_REGM_F_SHIFT 0 -#define PLL_REGN_MASK 0x000001FE -#define PLL_REGN_SHIFT 1 -#define PLL_SELFREQDCO_MASK 0x0000000E -#define PLL_SELFREQDCO_SHIFT 1 -#define PLL_SD_MASK 0x0003FC00 -#define PLL_SD_SHIFT 10 -#define SET_PLL_GO 0x1 -#define PLL_TICOPWDN BIT(16) -#define PLL_LDOPWDN BIT(15) -#define PLL_LOCK 0x2 -#define PLL_IDLE 0x1 - -/* PHY POWER CONTROL Register */ -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE - -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 - -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 - - -#define PLL_IDLE_TIME 100 /* in milliseconds */ -#define PLL_LOCK_TIME 100 /* in milliseconds */ - -static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) -{ - return __raw_readl(addr + offset); -} - -static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, - u32 data) -{ - __raw_writel(data, addr + offset); -} - -static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 - *pipe3) -{ - u32 rate; - struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - printf("%s: No DPLL configuration for %u Hz SYS CLK\n", - __func__, rate); - return NULL; -} - - -static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_LOCK_TIME; - - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (val & PLL_LOCK) - break; - } while (--timeout); - - if (!(val & PLL_LOCK)) { - printf("%s: DPLL failed to lock\n", __func__); - return -EBUSY; - } - - return 0; -} - -static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) -{ - u32 val; - struct pipe3_dpll_params *dpll_params; - - dpll_params = omap_pipe3_get_dpll_params(phy); - if (!dpll_params) { - printf("%s: Invalid DPLL parameters\n", __func__); - return -EINVAL; - } - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); - - omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - - return omap_pipe3_wait_lock(phy); -} - -static void omap_control_phy_power(struct omap_pipe3 *phy, int on) -{ - u32 val, rate; - - val = readl(phy->power_reg); - - rate = get_sys_clk_freq(); - rate = rate/1000000; - - if (on) { - val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; - } else { - val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - } - - writel(val, phy->power_reg); -} - -int phy_pipe3_power_on(struct omap_pipe3 *phy) -{ - int ret; - u32 val; - - /* Program the DPLL only if not locked */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (!(val & PLL_LOCK)) { - ret = omap_pipe3_dpll_program(phy); - if (ret) - return ret; - } else { - /* else just bring it out of IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - if (val & PLL_IDLE) { - val &= ~PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, - PLL_CONFIGURATION2, val); - ret = omap_pipe3_wait_lock(phy); - if (ret) - return ret; - } - } - - /* Power up the PHY */ - omap_control_phy_power(phy, 1); - - return 0; -} - -int phy_pipe3_power_off(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_IDLE_TIME; - - /* Power down the PHY */ - omap_control_phy_power(phy, 0); - - /* Put DPLL in IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val |= PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - /* wait for LDO and Oscillator to power down */ - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) - break; - } while (--timeout); - - if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { - printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", - __func__, val); - return -EBUSY; - } - - return 0; -} diff --git a/arch/arm/mach-omap2/pipe3-phy.h b/arch/arm/mach-omap2/pipe3-phy.h deleted file mode 100644 index 182bdcd4c81..00000000000 --- a/arch/arm/mach-omap2/pipe3-phy.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#ifndef __OMAP_PIPE3_PHY_H -#define __OMAP_PIPE3_PHY_H - -struct pipe3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct pipe3_dpll_map { - unsigned long rate; - struct pipe3_dpll_params params; -}; - -struct omap_pipe3 { - void __iomem *pll_ctrl_base; - void __iomem *power_reg; - struct pipe3_dpll_map *dpll_map; -}; - - -int phy_pipe3_power_on(struct omap_pipe3 *phy); -int phy_pipe3_power_off(struct omap_pipe3 *pipe3); - -#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c deleted file mode 100644 index 53c39ce1fb6..00000000000 --- a/arch/arm/mach-omap2/sata.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI SATA platform driver - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - */ - -#include <common.h> -#include <ahci.h> -#include <scsi.h> -#include <asm/arch/clock.h> -#include <asm/arch/sata.h> -#include <sata.h> -#include <asm/io.h> -#include <asm/omap_common.h> -#include "pipe3-phy.h" - -static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ - {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -struct omap_pipe3 sata_phy = { - .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, - /* .power_reg is updated at runtime */ - .dpll_map = dpll_map_sata, -}; - -int init_sata(int dev) -{ - int ret; - u32 val; - - sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; - - /* Power up the PHY */ - phy_pipe3_power_on(&sata_phy); - - /* Enable SATA module, No Idle, No Standby */ - val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; - writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); - - ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return ret; -} - -int reset_sata(int dev) -{ - return 0; -} - -/* On OMAP platforms SATA provides the SCSI subsystem */ -void scsi_init(void) -{ - init_sata(0); - scsi_scan(1); -} - -int scsi_bus_reset(struct udevice *dev) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); - ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return 0; -} diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index db47baba6d1..5fc92d07fe6 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -76,6 +76,30 @@ config STM32MP15x STM32MP157, STM32MP153 or STM32MP151 STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 + +config STM32MP25X + bool "Support STMicroelectronics STM32MP25x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core endchoice config NR_DRAM_BANKS @@ -128,6 +152,6 @@ config CMD_STM32KEY source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" - +source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig.25x b/arch/arm/mach-stm32mp/Kconfig.25x new file mode 100644 index 00000000000..2c0f691f8b5 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.25x @@ -0,0 +1,43 @@ +if STM32MP25X + +choice + prompt "STM32MP25x board select" + optional + +config TARGET_ST_STM32MP25X + bool "STMicroelectronics STM32MP25x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP25x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0x87000000 + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index a19b2797c8b..00dc25bb275 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -3,24 +3,17 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # -obj-y += cpu.o obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o -obj-$(CONFIG_STM32MP13x) += stm32mp13x.o -obj-$(CONFIG_STM32MP15x) += stm32mp15x.o +obj-$(CONFIG_STM32MP15x) += stm32mp1/ +obj-$(CONFIG_STM32MP13x) += stm32mp1/ +obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -obj-y += tzc400.o -else +ifndef CONFIG_SPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_TFABOOT) += boot_params.o endif - -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o -obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 599e63a93dd..28a8280b280 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -110,7 +110,7 @@ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_lock(u32 address, u32 otp) +static bool bsec_read_lock(void __iomem *address, u32 otp) { u32 bit; u32 bank; @@ -118,7 +118,7 @@ static bool bsec_read_lock(u32 address, u32 otp) bit = 1 << (otp & OTP_LOCK_MASK); bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); - return !!(readl(address + bank) & bit); + return !!(readl((address + bank)) & bit); } /** @@ -127,7 +127,7 @@ static bool bsec_read_lock(u32 address, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error, -EAGAIN or -ENOTSUPP */ -static u32 bsec_check_error(u32 base, u32 otp) +static u32 bsec_check_error(void __iomem *base, u32 otp) { u32 bit; u32 bank; @@ -149,7 +149,7 @@ static u32 bsec_check_error(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SR_lock(u32 base, u32 otp) +static bool bsec_read_SR_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); } @@ -160,7 +160,7 @@ static bool bsec_read_SR_lock(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SP_lock(u32 base, u32 otp) +static bool bsec_read_SP_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp); } @@ -171,7 +171,7 @@ static bool bsec_read_SP_lock(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SW_lock(u32 base, u32 otp) +static bool bsec_read_SW_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp); } @@ -182,7 +182,7 @@ static bool bsec_read_SW_lock(u32 base, u32 otp) * @power: true to power up , false to power down * Return: 0 if succeed */ -static int bsec_power_safmem(u32 base, bool power) +static int bsec_power_safmem(void __iomem *base, bool power) { u32 val; u32 mask; @@ -208,7 +208,7 @@ static int bsec_power_safmem(u32 base, bool power) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp) +static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp) { u32 val; int ret; @@ -253,7 +253,8 @@ static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp) +static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val, + u32 otp) { *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32)); @@ -268,7 +269,7 @@ static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp) +static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp) { /* check if programming of otp is locked */ if (bsec_read_SW_lock(base, otp)) @@ -288,7 +289,7 @@ static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp) * after the function the otp data is not refreshed in shadow * Return: 0 if no error */ -static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) +static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp) { u32 ret; bool power_up = false; @@ -338,7 +339,7 @@ static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp) +static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp) { int ret; bool power_up = false; @@ -392,7 +393,7 @@ static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp) /* BSEC MISC driver *******************************************************/ struct stm32mp_bsec_plat { - u32 base; + void __iomem *base; }; struct stm32mp_bsec_priv { @@ -724,7 +725,7 @@ static int stm32mp_bsec_of_to_plat(struct udevice *dev) { struct stm32mp_bsec_plat *plat = dev_get_plat(dev); - plat->base = (u32)dev_read_addr_ptr(dev); + plat->base = dev_read_addr_ptr(dev); return 0; } diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 7f37b0d2aa2..fb1208fc5d5 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -24,8 +24,11 @@ int dram_init(void) int ret; ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - log_debug("RAM init failed: %d\n", ret); + /* in case there is no RAM driver, retrieve DDR size from DT */ + if (ret == -ENODEV) { + return fdtdec_setup_mem_size_base(); + } else if (ret) { + log_err("RAM init failed: %d\n", ret); return ret; } ret = ram_get_info(dev, &ram); @@ -33,7 +36,7 @@ int dram_init(void) log_debug("Cannot get RAM size: %d\n", ret); return ret; } - log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size); gd->ram_size = ram.size; @@ -49,9 +52,15 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) if (!total_size) return gd->ram_top; + /* + * make sure U-Boot uses address space below 4GB boundaries even + * if the effective available memory is bigger + */ + gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); - lmb_add(&lmb, gd->ram_base, get_effective_memsize()); + lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); /* add 8M for reserved memory for display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index ac0deced67e..46d469881b3 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -6,14 +6,72 @@ #ifndef _MACH_STM32_H_ #define _MACH_STM32_H_ +#include <linux/sizes.h> #ifndef __ASSEMBLY__ #include <linux/bitops.h> + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, +}; + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) +#define TAMP_BOOT_AUTH_SHIFT 16 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) +#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) +#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) + +enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, +}; + #endif /* * Peripheral memory map * only address used before device tree parsing */ + +#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x) #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 @@ -58,12 +116,6 @@ #define STM32_DDR_SIZE SZ_1G #ifndef __ASSEMBLY__ -/* enumerated used to identify the SYSCON driver instance */ -enum { - STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_SYSCFG, -}; - /* * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT * - boot device = bit 8:4 @@ -74,40 +126,6 @@ enum { #define BOOT_INSTANCE_MASK 0x0F #define BOOT_INSTANCE_SHIFT 0 -enum boot_device { - BOOT_FLASH_SD = 0x10, - BOOT_FLASH_SD_1 = 0x11, - BOOT_FLASH_SD_2 = 0x12, - BOOT_FLASH_SD_3 = 0x13, - - BOOT_FLASH_EMMC = 0x20, - BOOT_FLASH_EMMC_1 = 0x21, - BOOT_FLASH_EMMC_2 = 0x22, - BOOT_FLASH_EMMC_3 = 0x23, - - BOOT_FLASH_NAND = 0x30, - BOOT_FLASH_NAND_FMC = 0x31, - - BOOT_FLASH_NOR = 0x40, - BOOT_FLASH_NOR_QSPI = 0x41, - - BOOT_SERIAL_UART = 0x50, - BOOT_SERIAL_UART_1 = 0x51, - BOOT_SERIAL_UART_2 = 0x52, - BOOT_SERIAL_UART_3 = 0x53, - BOOT_SERIAL_UART_4 = 0x54, - BOOT_SERIAL_UART_5 = 0x55, - BOOT_SERIAL_UART_6 = 0x56, - BOOT_SERIAL_UART_7 = 0x57, - BOOT_SERIAL_UART_8 = 0x58, - - BOOT_SERIAL_USB = 0x60, - BOOT_SERIAL_USB_OTG = 0x62, - - BOOT_FLASH_SPINAND = 0x70, - BOOT_FLASH_SPINAND_1 = 0x71, -}; - /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) @@ -123,7 +141,6 @@ enum boot_device { #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) #define TAMP_FWU_BOOT_IDX_OFFSET 0 - #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -137,25 +154,23 @@ enum boot_device { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif -#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) -#define TAMP_BOOT_MODE_SHIFT 8 -#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) -#define TAMP_BOOT_AUTH_SHIFT 16 -#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) -#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) -#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) -#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) -#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ -enum forced_boot_mode { - BOOT_NORMAL = 0x00, - BOOT_FASTBOOT = 0x01, - BOOT_RECOVERY = 0x02, - BOOT_STM32PROG = 0x03, - BOOT_UMS_MMC0 = 0x10, - BOOT_UMS_MMC1 = 0x11, - BOOT_UMS_MMC2 = 0x12, -}; +#if CONFIG_STM32MP25X +#define STM32_RCC_BASE 0x44200000 +#define STM32_TAMP_BASE 0x46010000 + +#define STM32_DDR_BASE 0x80000000 + +#define STM32_DDR_SIZE SZ_4G + +/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) + +/* TAMP registers zone 3 RIF 1 (RW) at 96*/ +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) +#endif /* STM32MP25X */ /* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -179,6 +194,20 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif +#ifdef CONFIG_STM32MP25X +#define BSEC_OTP_SERIAL 5 +#define BSEC_OTP_RPN 9 +#define BSEC_OTP_PKG 246 +#endif + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_SYSCFG, +}; +#endif /* __ASSEMBLY__*/ -#endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 52aca1e23e1..83388fdb737 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,11 +30,30 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 +/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -59,6 +78,13 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 +/* package used for STM32MP25x */ +#define STM32MP25_PKG_CUSTOM 0 +#define STM32MP25_PKG_AL_TBGA361 3 +#define STM32MP25_PKG_AK_TBGA424 4 +#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_UNKNOWN 7 + /* Get SOC name */ #define SOC_NAME_SIZE 20 void get_soc_name(char name[SOC_NAME_SIZE]); diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile new file mode 100644 index 00000000000..94c7724127e --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o + +obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP15x) += stm32mp15x.o + +obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += tzc400.o +else +obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif + +obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 55574fd4beb..55574fd4beb 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c index de5c5a55ea0..de5c5a55ea0 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..8cdeb0ab3f2 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c index 846637ab162..846637ab162 100644 --- a/arch/arm/mach-stm32mp/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 6c79259b2c8..6c79259b2c8 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 845d973ad1b..845d973ad1b 100644 --- a/arch/arm/mach-stm32mp/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index afc56b02eea..afc56b02eea 100644 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c diff --git a/arch/arm/mach-stm32mp/tzc400.c b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c index cdc4a40edaf..cdc4a40edaf 100644 --- a/arch/arm/mach-stm32mp/tzc400.c +++ b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile new file mode 100644 index 00000000000..b579ce5a800 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o +obj-y += arm64-mmu.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c new file mode 100644 index 00000000000..36c631ef0c2 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <asm/system.h> +#include <asm/armv8/mmu.h> +#include <mach/stm32.h> + +#define MP2_MEM_MAP_MAX 10 + +#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \ + (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE)) +#error "invalid CONFIG_TEXT_BASE value" +#endif + +struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { + { + /* PCIe */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals: alias1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OSPI and FMC: memory-map area */ + .virt = 0x60000000UL, + .phys = 0x60000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * DDR = STM32_DDR_BASE / STM32_DDR_SIZE + * the beginning of DDR (before CONFIG_TEXT_BASE) is not + * mapped, protected by RIF and reserved for other firmware + * (OP-TEE / TF-M / Cube M33) + */ + .virt = CONFIG_TEXT_BASE, + .phys = CONFIG_TEXT_BASE, + .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE), + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = stm32mp2_mem_map; diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c new file mode 100644 index 00000000000..f43d1aaf72c --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <clk.h> +#include <cpu_func.h> +#include <debug_uart.h> +#include <env_internal.h> +#include <init.h> +#include <misc.h> +#include <wdt.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <asm/system.h> +#include <dm/device.h> +#include <dm/lists.h> +#include <dm/uclass.h> + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB alignment + */ +#define EARLY_TLB_SIZE 0xA000 +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + icache_enable(); + early_enable_caches(); + + return 0; +} + +void enable_caches(void) +{ + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + dcache_enable(); +} + +/* used when CONFIG_DISPLAY_CPUINFO is activated */ +int print_cpuinfo(void) +{ + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; +} + +int arch_misc_init(void) +{ + return 0; +} + +/* + * Force data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ +static uintptr_t nt_fw_dtb __section(".data"); + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +/* + * Save the FDT address provided by TF-A in r2 at boot time + * This function is called from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + nt_fw_dtb = r2; + + save_boot_params_ret(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/fdt.c b/arch/arm/mach-stm32mp/stm32mp2/fdt.c new file mode 100644 index 00000000000..31b127b465a --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <asm/u-boot.h> + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c new file mode 100644 index 00000000000..4b2f70af9cc --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 +#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + fallthrough; + case CPU_STM32MP257Dxx: + fallthrough; + case CPU_STM32MP257Cxx: + fallthrough; + case CPU_STM32MP257Axx: + nb_eth = 5; /* dual ETH with TSN support */ + break; + case CPU_STM32MP253Fxx: + fallthrough; + case CPU_STM32MP253Dxx: + fallthrough; + case CPU_STM32MP253Cxx: + fallthrough; + case CPU_STM32MP253Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP251Fxx: + fallthrough; + case CPU_STM32MP251Dxx: + fallthrough; + case CPU_STM32MP251Cxx: + fallthrough; + case CPU_STM32MP251Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP25) { + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + cpu_s = "257F"; + break; + case CPU_STM32MP257Dxx: + cpu_s = "257D"; + break; + case CPU_STM32MP257Cxx: + cpu_s = "257C"; + break; + case CPU_STM32MP257Axx: + cpu_s = "257A"; + break; + case CPU_STM32MP255Fxx: + cpu_s = "255F"; + break; + case CPU_STM32MP255Dxx: + cpu_s = "255D"; + break; + case CPU_STM32MP255Cxx: + cpu_s = "255C"; + break; + case CPU_STM32MP255Axx: + cpu_s = "255A"; + break; + case CPU_STM32MP253Fxx: + cpu_s = "253F"; + break; + case CPU_STM32MP253Dxx: + cpu_s = "253D"; + break; + case CPU_STM32MP253Cxx: + cpu_s = "253C"; + break; + case CPU_STM32MP253Axx: + cpu_s = "253A"; + break; + case CPU_STM32MP251Fxx: + cpu_s = "251F"; + break; + case CPU_STM32MP251Dxx: + cpu_s = "251D"; + break; + case CPU_STM32MP251Cxx: + cpu_s = "251C"; + break; + case CPU_STM32MP251Axx: + cpu_s = "251A"; + break; + default: + cpu_s = "25??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP25_PKG_AL_TBGA361: + package = "AL"; + break; + case STM32MP25_PKG_AK_TBGA424: + package = "AK"; + break; + case STM32MP25_PKG_AI_TBGA436: + package = "AI"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index a0e8e1dfdc5..a2e351d74a7 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -10,8 +10,8 @@ #include <asm/arch/stm32.h> static const struct udevice_id stm32mp_syscon_ids[] = { - { .compatible = "st,stm32mp157-syscfg", - .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG}, { } }; diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index c2410dd7bb1..267cb0b1aba 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -354,10 +354,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT image\n"); - load.dev = NULL; - load.priv = NULL; - load.filename = NULL; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spi_load_read; ret = spl_load_simple_fit(spl_image, &load, load_offset, header); diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index e3fd613f2be..a576e6f6165 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -6,7 +6,6 @@ #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ #define _TEGRA_XUSB_PADCTL_COMMON_H_ -#include <common.h> #include <fdtdec.h> #include <dm/ofnode.h> diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h index 434a7fa20e4..783d7c45c7b 100644 --- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h +++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h @@ -4,7 +4,6 @@ #define _PSU_INIT_GPL_H_ #include <asm/io.h> -#include <common.h> int mask_pollonvalue(unsigned long add, u32 mask, u32 value); diff --git a/arch/m68k/include/asm/fsl_mcdmafec.h b/arch/m68k/include/asm/fsl_mcdmafec.h deleted file mode 100644 index de6c548fafd..00000000000 --- a/arch/m68k/include/asm/fsl_mcdmafec.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef fsl_mcdmafec_h -#define fsl_mcdmafec_h - -/* Re-use of the definitions */ -#include <asm/fec.h> - -typedef struct fecdma { - u32 rsvd0; /* 0x000 */ - u32 eir; /* 0x004 */ - u32 eimr; /* 0x008 */ - u32 rsvd1[6]; /* 0x00C - 0x023 */ - u32 ecr; /* 0x024 */ - u32 rsvd2[6]; /* 0x028 - 0x03F */ - u32 mmfr; /* 0x040 */ - u32 mscr; /* 0x044 */ - u32 rsvd3[7]; /* 0x048 - 0x063 */ - u32 mibc; /* 0x064 */ - u32 rsvd4[7]; /* 0x068 - 0x083 */ - u32 rcr; /* 0x084 */ - u32 rhr; /* 0x088 */ - u32 rsvd5[14]; /* 0x08C - 0x0C3 */ - u32 tcr; /* 0x0C4 */ - u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */ - u32 palr; /* 0x0E4 */ - u32 paur; /* 0x0E8 */ - u32 opd; /* 0x0EC */ - u32 rsvd7[10]; /* 0x0F0 - 0x117 */ - u32 iaur; /* 0x118 */ - u32 ialr; /* 0x11C */ - u32 gaur; /* 0x120 */ - u32 galr; /* 0x124 */ - u32 rsvd8[7]; /* 0x128 - 0x143 */ - u32 tfwr; /* 0x144 */ - u32 rsvd9[14]; /* 0x148 - 0x17F */ - u32 fmc; /* 0x180 */ - u32 rfdr; /* 0x184 */ - u32 rfsr; /* 0x188 */ - u32 rfcr; /* 0x18C */ - u32 rlrfp; /* 0x190 */ - u32 rlwfp; /* 0x194 */ - u32 rfar; /* 0x198 */ - u32 rfrp; /* 0x19C */ - u32 rfwp; /* 0x1A0 */ - u32 tfdr; /* 0x1A4 */ - u32 tfsr; /* 0x1A8 */ - u32 tfcr; /* 0x1AC */ - u32 tlrfp; /* 0x1B0 */ - u32 tlwfp; /* 0x1B4 */ - u32 tfar; /* 0x1B8 */ - u32 tfrp; /* 0x1BC */ - u32 tfwp; /* 0x1C0 */ - u32 frst; /* 0x1C4 */ - u32 ctcwr; /* 0x1C8 */ -} fecdma_t; - -struct fec_info_dma { - int index; - u32 iobase; - u32 pinmux; - u32 miibase; - int phy_addr; - int dup_spd; - char *phy_name; - int phyname_init; - cbd_t *rxbd; /* Rx BD */ - cbd_t *txbd; /* Tx BD */ - uint rx_idx; - uint tx_idx; - char *txbuf; - int initialized; - struct fec_info_dma *next; - u16 rx_task; /* DMA receive Task Number */ - u16 tx_task; /* DMA Transmit Task Number */ - u16 rx_pri; /* DMA Receive Priority */ - u16 tx_pri; /* DMA Transmit Priority */ - u16 rx_init; /* DMA Receive Initiator */ - u16 tx_init; /* DMA Transmit Initiator */ - u16 used_tbd_idx; /* next transmit BD to clean */ - u16 clean_tbd_num; /* the number of available transmit BDs */ - int to_loop; - struct mii_dev *bus; -}; - -/* Bit definitions and macros for IEVENT */ -#define FEC_EIR_TXERR (0x00040000) -#define FEC_EIR_RXERR (0x00020000) -#undef FEC_EIR_CLEAR_ALL -#define FEC_EIR_CLEAR_ALL (0xFFFE0000) - -/* Bit definitions and macros for R_HASH */ -#define FEC_RHASH_FCE_DC (0x80000000) -#define FEC_RHASH_MULTCAST (0x40000000) -#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24) - -/* Bit definitions and macros for FEC_TFWR */ -#undef FEC_TFWR_X_WMRK -#undef FEC_TFWR_X_WMRK_64 -#undef FEC_TFWR_X_WMRK_128 -#undef FEC_TFWR_X_WMRK_192 - -#define FEC_TFWR_X_WMRK(x) ((x)&0x0F) -#define FEC_TFWR_X_WMRK_64 (0x00) -#define FEC_TFWR_X_WMRK_128 (0x01) -#define FEC_TFWR_X_WMRK_192 (0x02) -#define FEC_TFWR_X_WMRK_256 (0x03) -#define FEC_TFWR_X_WMRK_320 (0x04) -#define FEC_TFWR_X_WMRK_384 (0x05) -#define FEC_TFWR_X_WMRK_448 (0x06) -#define FEC_TFWR_X_WMRK_512 (0x07) -#define FEC_TFWR_X_WMRK_576 (0x08) -#define FEC_TFWR_X_WMRK_640 (0x09) -#define FEC_TFWR_X_WMRK_704 (0x0A) -#define FEC_TFWR_X_WMRK_768 (0x0B) -#define FEC_TFWR_X_WMRK_832 (0x0C) -#define FEC_TFWR_X_WMRK_896 (0x0D) -#define FEC_TFWR_X_WMRK_960 (0x0E) -#define FEC_TFWR_X_WMRK_1024 (0x0F) - -/* FIFO definitions */ -/* Bit definitions and macros for FSTAT */ -#define FIFO_STAT_IP (0x80000000) -#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24) -#define FIFO_STAT_FAE (0x00800000) -#define FIFO_STAT_RXW (0x00400000) -#define FIFO_STAT_UF (0x00200000) -#define FIFO_STAT_OF (0x00100000) -#define FIFO_STAT_FR (0x00080000) -#define FIFO_STAT_FULL (0x00040000) -#define FIFO_STAT_ALARM (0x00020000) -#define FIFO_STAT_EMPTY (0x00010000) - -/* Bit definitions and macros for FCTRL */ -#define FIFO_CTRL_WCTL (0x40000000) -#define FIFO_CTRL_WFR (0x20000000) -#define FIFO_CTRL_FRAME (0x08000000) -#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24) -#define FIFO_CTRL_IPMASK (0x00800000) -#define FIFO_CTRL_FAEMASK (0x00400000) -#define FIFO_CTRL_RXWMASK (0x00200000) -#define FIFO_CTRL_UFMASK (0x00100000) -#define FIFO_CTRL_OFMASK (0x00080000) - -#endif /* fsl_mcdmafec_h */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 411b00899c2..b118a917542 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -314,21 +314,6 @@ #include <asm/immap_547x_8x.h> #include <asm/m547x_8x.h> -#ifdef CONFIG_FSLDMAFEC -#define FEC0_RX_TASK 0 -#define FEC0_TX_TASK 1 -#define FEC0_RX_PRIORITY 6 -#define FEC0_TX_PRIORITY 7 -#define FEC0_RX_INIT 16 -#define FEC0_TX_INIT 17 -#define FEC1_RX_TASK 2 -#define FEC1_TX_TASK 3 -#define FEC1_RX_PRIORITY 6 -#define FEC1_TX_PRIORITY 7 -#define FEC1_RX_INIT 30 -#define FEC1_TX_INIT 31 -#endif - #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR diff --git a/arch/m68k/lib/fec.c b/arch/m68k/lib/fec.c index d6f238e4b34..ac36aec0ed7 100644 --- a/arch/m68k/lib/fec.c +++ b/arch/m68k/lib/fec.c @@ -10,7 +10,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC) +#if defined(CONFIG_MCFFEC) static int fec_get_node(int fec_idx) { char fec_alias[5] = {"fec"}; @@ -77,4 +77,4 @@ int fec_get_mii_base(int fec_idx, u32 *mii_base) return fec_get_fdt_prop(fec_idx, "mii-base", mii_base); } -#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC +#endif //CONFIG_MCFFEC diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index f5cb000de6b..340f9a0da56 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -3,7 +3,6 @@ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm-offsets.h> #include <mpc83xx.h> #include <system-constants.h> @@ -19,6 +18,8 @@ #ifdef CONFIG_QE #include <fsl_qe.h> #endif +#include <asm/ppc.h> +#include <asm/fsl_lbc.h> #include "lblaw/lblaw.h" #include "elbc/elbc.h" diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index d72d3147f63..ceb54867894 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,6 +20,7 @@ #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/fsl_lbc.h> #include <asm/u-boot.h> #include "hrcw/hrcw.h" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 96183ac2c84..b770d294e61 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <display_options.h> #include <env.h> #include <init.h> diff --git a/arch/powerpc/cpu/mpc8xx/cache.c b/arch/powerpc/cpu/mpc8xx/cache.c index 41559009cac..525c87f37cd 100644 --- a/arch/powerpc/cpu/mpc8xx/cache.c +++ b/arch/powerpc/cpu/mpc8xx/cache.c @@ -4,7 +4,6 @@ * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr */ -#include <common.h> #include <cpu_func.h> #include <asm/processor.h> #include <asm/ppc.h> diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 56383cecde2..b9afd312ec6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -16,7 +16,6 @@ * Wolfgang Denk <wd@denx.de> */ -#include <common.h> #include <cpu_func.h> #include <display_options.h> #include <net.h> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index feef792ee77..aac4203a6e4 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <watchdog.h> diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index b4a26efe302..b204a3d7517 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -5,7 +5,6 @@ * Code copied & edited from Freescale mpc85xx stuff. */ -#include <common.h> #include <time.h> #include <asm/global_data.h> #include <linux/libfdt.h> diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c index 40793c26e12..8c85fc180b9 100644 --- a/arch/powerpc/cpu/mpc8xx/immap.c +++ b/arch/powerpc/cpu/mpc8xx/immap.c @@ -8,7 +8,6 @@ * MPC8xx Internal Memory Map Functions */ -#include <common.h> #include <command.h> #include <asm/global_data.h> @@ -16,6 +15,7 @@ #include <asm/cpm_8xx.h> #include <asm/iopin_8xx.h> #include <asm/io.h> +#include <asm/ppc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c index eef1951f2fd..babef07ffb1 100644 --- a/arch/powerpc/cpu/mpc8xx/interrupts.c +++ b/arch/powerpc/cpu/mpc8xx/interrupts.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <stdio.h> #include <irq_func.h> #include <mpc8xx.h> #include <mpc8xx_irq.h> diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 1a882a38820..baf81381b39 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <clock_legacy.h> #include <mpc8xx.h> #include <asm/global_data.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/immap_8xx.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c index 56794b08a15..5220c560e5f 100644 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ b/arch/powerpc/cpu/mpc8xx/traps.c @@ -15,7 +15,7 @@ * This file handles the architecture-dependent parts of hardware exceptions */ -#include <common.h> +#include <vsprintf.h> #include <asm/ptrace.h> #include <command.h> #include <asm/processor.h> diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index a03f091c305..95f0f559b4c 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -6,9 +6,6 @@ #ifndef __ASM_PPC_FSL_LBC_H #define __ASM_PPC_FSL_LBC_H -#include <config.h> -#include <common.h> - #ifdef CONFIG_MPC85xx void lbc_sdram_init(void); #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 6ed21c781fe..43d71f5caec 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -9,7 +9,7 @@ #define __ASM_GBL_DATA_H #include <config.h> -#include "asm/types.h" +#include <linux/types.h> /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 95c26d855ab..cbae5109e85 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -287,6 +287,23 @@ int os_persistent_file(char *buf, int maxsize, const char *fname) return 0; } +int os_mktemp(char *fname, off_t size) +{ + int fd; + + fd = mkostemp(fname, O_CLOEXEC); + if (fd < 0) + return -errno; + + if (unlink(fname) < 0) + return -errno; + + if (ftruncate(fd, size)) + return -errno; + + return fd; +} + /* Restore tty state when we exit */ static struct termios orig_term; static bool term_setup; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index c7197795efb..9131eda970b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1914,6 +1914,71 @@ compatible = "sandbox,arm-ffa"; }; }; + + nand-controller { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sandbox,nand"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "soft"; + sandbox,id = [00 e3]; + sandbox,erasesize = <(8 * 1024)>; + sandbox,oobsize = <16>; + sandbox,pagesize = <512>; + sandbox,pages = <0x2000>; + sandbox,err-count = <1>; + sandbox,err-step-size = <512>; + }; + + /* MT29F64G08AKABA */ + nand@1 { + reg = <1>; + nand-ecc-mode = "soft_bch"; + sandbox,id = [2C 48 00 26 89 00 00 00]; + sandbox,onfi = [ + 4f 4e 46 49 0e 00 5a 00 + ff 01 00 00 00 00 03 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 4d 49 43 52 4f 4e 20 20 + 20 20 20 20 4d 54 32 39 + 46 36 34 47 30 38 41 4b + 41 42 41 43 35 20 20 20 + 2c 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 10 00 00 e0 00 00 02 + 00 00 1c 00 80 00 00 00 + 00 10 00 00 02 23 01 50 + 00 01 05 01 00 00 04 00 + 04 01 1e 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 0e 1f 00 1f 00 f4 01 ac + 0d 19 00 c8 00 00 00 00 + 00 00 00 00 00 00 0a 07 + 19 00 00 00 00 00 00 00 + 00 00 00 00 01 00 01 00 + 00 00 04 10 01 81 04 02 + 02 01 1e 90 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 03 20 7d + ]; + sandbox,erasesize = <(512 * 1024)>; + sandbox,oobsize = <224>; + sandbox,pagesize = <4096>; + sandbox,pages = <0x200000>; + sandbox,err-count = <3>; + sandbox,err-step-size = <512>; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/barrier.h b/arch/sandbox/include/asm/barrier.h new file mode 100644 index 00000000000..0928a78cbf8 --- /dev/null +++ b/arch/sandbox/include/asm/barrier.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#define nop() diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h index df7156fe317..2b7dbca8f75 100644 --- a/arch/sandbox/include/asm/clk.h +++ b/arch/sandbox/include/asm/clk.h @@ -6,7 +6,6 @@ #ifndef __SANDBOX_CLK_H #define __SANDBOX_CLK_H -#include <common.h> #include <clk.h> #include <dt-structs.h> #include <linux/clk-provider.h> diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h index 70f36d7afef..499e9a67f6a 100644 --- a/arch/sandbox/include/asm/mbox.h +++ b/arch/sandbox/include/asm/mbox.h @@ -6,8 +6,6 @@ #ifndef __SANDBOX_MBOX_H #define __SANDBOX_MBOX_H -#include <common.h> - #define SANDBOX_MBOX_PING_XOR 0x12345678 struct udevice; diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h index 1845bc8d3ba..4d5e861dbce 100644 --- a/arch/sandbox/include/asm/power-domain.h +++ b/arch/sandbox/include/asm/power-domain.h @@ -6,8 +6,6 @@ #ifndef __SANDBOX_POWER_DOMAIN_H #define __SANDBOX_POWER_DOMAIN_H -#include <common.h> - struct udevice; int sandbox_power_domain_query(struct udevice *dev, unsigned long id); diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h index 40d3e61c110..f0709b41c09 100644 --- a/arch/sandbox/include/asm/reset.h +++ b/arch/sandbox/include/asm/reset.h @@ -6,8 +6,6 @@ #ifndef __SANDBOX_RESET_H #define __SANDBOX_RESET_H -#include <common.h> - struct udevice; int sandbox_reset_query(struct udevice *dev, unsigned long id); diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index f349ea19971..4fab24cd156 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -15,6 +15,7 @@ enum { BOOT_DEVICE_CPGMAC, BOOT_DEVICE_NOR, BOOT_DEVICE_SPI, + BOOT_DEVICE_NAND, }; /** diff --git a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h index 05dd1b2b447..460bfc4f2d4 100644 --- a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h +++ b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h @@ -6,7 +6,6 @@ #ifndef __SLIMBOOTLOADER_ARCH_H__ #define __SLIMBOOTLOADER_ARCH_H__ -#include <common.h> #include <asm/hob.h> /** diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h index 8be1003e6ba..c79ec64afd7 100644 --- a/arch/x86/include/asm/dma-mapping.h +++ b/arch/x86/include/asm/dma-mapping.h @@ -7,7 +7,6 @@ #ifndef __ASM_X86_DMA_MAPPING_H #define __ASM_X86_DMA_MAPPING_H -#include <common.h> #include <asm/cache.h> #include <cpu_func.h> #include <linux/dma-direction.h> |