diff options
Diffstat (limited to 'arch')
22 files changed, 298 insertions, 99 deletions
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 70d050590de..6adc0ed42ba 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -9,6 +9,12 @@ #include <linux/types.h> #include <asm/byteorder.h> +/* + * Compiler barrier. It prevents compiler from reordering instructions before + * and after it. It doesn't prevent HW (CPU) from any reordering though. + */ +#define __comp_b() asm volatile("" : : : "memory") + #ifdef __ARCHS__ /* @@ -45,8 +51,8 @@ #define __iormb() rmb() #define __iowmb() wmb() #else -#define __iormb() asm volatile("" : : : "memory") -#define __iowmb() asm volatile("" : : : "memory") +#define __iormb() __comp_b() +#define __iowmb() __comp_b() #endif static inline void sync(void) @@ -54,31 +60,47 @@ static inline void sync(void) /* Not yet implemented */ } -#define __arch_getb(a) (*(unsigned char *)(a)) -#define __arch_getw(a) (*(unsigned short *)(a)) -#define __arch_getl(a) (*(unsigned int *)(a)) -#define __arch_getq(a) (*(unsigned long long *)(a)) +/* + * We must use 'volatile' in C-version read/write IO accessors implementation + * to avoid merging several reads (writes) into one read (write), or optimizing + * them out by compiler. + * We must use compiler barriers before and after operation (read or write) so + * it won't be reordered by compiler. + */ +#define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8 *)(a); __comp_b(); __v; }) +#define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; }) +#define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; }) +#define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; }) + +#define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v); __comp_b(); }) +#define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); }) +#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); }) +#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); }) -#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) -#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) -#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) -#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) -#define __raw_writeb(v, a) __arch_putb(v, a) -#define __raw_writew(v, a) __arch_putw(v, a) -#define __raw_writel(v, a) __arch_putl(v, a) -#define __raw_writeq(v, a) __arch_putq(v, a) +/* + * We add memory barriers for __raw_readX / __raw_writeX accessors same way as + * it is done for readX and writeX accessors as lots of U-boot driver uses + * __raw_readX / __raw_writeX instead of proper accessor with barrier. + */ +#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) +#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); }) +#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); }) +#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); }) + +#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) +#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) +#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) +#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) -#define __raw_readq(a) __arch_getq(a) static inline void __raw_writesb(unsigned long addr, const void *data, int bytelen) { u8 *buf = (uint8_t *)data; + __iowmb(); + while (bytelen--) __arch_putb(*buf++, addr); } @@ -88,6 +110,8 @@ static inline void __raw_writesw(unsigned long addr, const void *data, { u16 *buf = (uint16_t *)data; + __iowmb(); + while (wordlen--) __arch_putw(*buf++, addr); } @@ -97,6 +121,8 @@ static inline void __raw_writesl(unsigned long addr, const void *data, { u32 *buf = (uint32_t *)data; + __iowmb(); + while (longlen--) __arch_putl(*buf++, addr); } @@ -107,6 +133,8 @@ static inline void __raw_readsb(unsigned long addr, void *data, int bytelen) while (bytelen--) *buf++ = __arch_getb(addr); + + __iormb(); } static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) @@ -115,6 +143,8 @@ static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) while (wordlen--) *buf++ = __arch_getw(addr); + + __iormb(); } static inline void __raw_readsl(unsigned long addr, void *data, int longlen) @@ -123,6 +153,8 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) while (longlen--) *buf++ = __arch_getl(addr); + + __iormb(); } /* @@ -130,21 +162,15 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) * ordering rules but do not guarantee any ordering relative to Normal memory * accesses. */ -#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) -#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ - __raw_readw(c)); __r; }) -#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ - __raw_readl(c)); __r; }) -#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ - __raw_readq(c)); __r; }) - -#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) -#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ - cpu_to_le16(v), (c))) -#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ - cpu_to_le32(v), (c))) -#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ - cpu_to_le64(v), (c))) +#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__arch_putb((v), (c))) +#define writew_relaxed(v, c) ((void)__arch_putw((__force u16)cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__arch_putq((__force u64)cpu_to_le64(v), (c))) /* * MMIO can also get buffered/optimized in micro-arch, so barriers needed diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5d367888d8a..bbb1e2738bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -989,6 +989,8 @@ config ARCH_SUNXI select USB_KEYBOARD if DISTRO_DEFAULTS select USB_STORAGE if DISTRO_DEFAULTS select SPL_USE_TINY_PRINTF + select USE_PREBOOT + select SYS_RELOC_GD_ENV_ADDR imply CMD_DM imply CMD_GPT imply CMD_UBI if MTD_RAW_NAND @@ -1366,6 +1368,7 @@ config TARGET_LS1028ARDB select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT help Support for Freescale LS1028ARDB platform The LS1028A Development System (RDB) is a high-performance diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 275c66d9929..b25639183f8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -74,11 +74,11 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C imply CMD_PCI config ARCH_LS1046A @@ -107,11 +107,11 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C imply SCSI imply SCSI_AHCI diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts index 3fd37beedf4..029a8e386b1 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dts +++ b/arch/arm/dts/fsl-ls1028a-qds.dts @@ -49,6 +49,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index a8f40855b65..85b4815b2ed 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -48,6 +48,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts index 3d41e3bd44f..d39159322a5 100644 --- a/arch/arm/dts/fsl-ls1046a-frwy.dts +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -32,3 +32,6 @@ }; +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c95f44fc361..76dc397328a 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -80,3 +80,7 @@ &sata { status = "okay"; }; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index a05c9e9b9ea..83e34ab02ad 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -43,3 +43,11 @@ &sata { status = "okay"; }; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 34df0f51060..592fd5977e2 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -13,6 +13,9 @@ / { model = "NXP Layerscape LX2160AQDS Board"; compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + aliases { + spi0 = &fspi; + }; }; &esdhc0 { @@ -46,6 +49,20 @@ }; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index e542c6992ab..87617ca51f6 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -39,6 +39,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; mt35xu512aba1: flash@1 { @@ -47,6 +49,8 @@ compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <1>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dts b/arch/arm/dts/r8a7792-blanche-u-boot.dts index 3555663d647..30b27040f5a 100644 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dts +++ b/arch/arm/dts/r8a7792-blanche-u-boot.dts @@ -8,6 +8,10 @@ #include "r8a7792-blanche.dts" #include "r8a7792-u-boot.dtsi" +&iic3 { + status = "okay"; +}; + &scif0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index 8e9eb4b704d..6fd80e35415 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -444,6 +444,23 @@ status = "disabled"; }; + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7792", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts index 32b95940b07..83e8b318384 100644 --- a/arch/arm/dts/rv1108-elgin-r1.dts +++ b/arch/arm/dts/rv1108-elgin-r1.dts @@ -40,9 +40,20 @@ }; &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer_pullup>; status = "okay"; }; &usb20_otg { status = "okay"; }; + +&pinctrl { + uart2m0 { + uart2m0_xfer_pullup: uart2m0-xfer-pullup { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + }; +}; diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi new file mode 100644 index 00000000000..41ac054b81e --- /dev/null +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "rockchip-u-boot.dtsi" diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 1908be4b8b2..debeb8b239a 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -37,3 +37,6 @@ u-boot,dm-pre-reloc; }; +&qspi { + status = "okay"; +}; diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 84e5cb46e5a..333e407b666 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -4,7 +4,8 @@ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_U8500) && \ + !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \ + !defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \ !defined(CONFIG_CORTINA_PLATFORM) #include <asm/arch/gpio.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index 929c413e039..b947cc07291 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -47,4 +47,6 @@ #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 #define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000 + #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 2725e9fcc34..da966fb4583 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -59,4 +59,6 @@ #define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 #define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 +#define SOCFPGA_PHYS_OCRAM_SIZE 0x10000 + #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index d9ef851054d..b10be332680 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -33,6 +33,38 @@ DECLARE_GLOBAL_DATA_PTR; +#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ +#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + SOCFPGA_PHYS_OCRAM_SIZE - \ + BOOTROM_SHARED_MEM_SIZE) +#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) +static u32 rst_mgr_status __section(.data); + +/* + * Bootrom will clear the status register in reset manager and stores the + * reset status value in shared memory. Bootrom stores shared data at last + * 2KB of onchip RAM. + * This function save reset status provided by BootROM to rst_mgr_status. + * More information about reset status register value can be found in reset + * manager register description. + * When running in debugger without Bootrom, r0 to r3 are random values. + * So, skip save the value when r0 is not BootROM shared data address. + * + * r0 - Contains the pointer to the shared memory block. The shared + * memory block is located in the top 2 KB of on-chip RAM. + * r1 - contains the length of the shared memory. + * r2 - unused and set to 0x0. + * r3 - points to the version block. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + if (r0 == BOOTROM_SHARED_MEM_ADDR) + rst_mgr_status = readl(RST_STATUS_SHARED_ADDR); + + save_boot_params_ret(); +} + u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3a3b6734301..be0822bfb7d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 043d9f6eade..a3997b25901 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -36,13 +36,13 @@ /* SUN4I variant of the SPI controller */ /*****************************************************************************/ -#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) -#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) -#define SUN4I_SPI0_RX (0x01C05000 + 0x00) -#define SUN4I_SPI0_TX (0x01C05000 + 0x04) -#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) -#define SUN4I_SPI0_BC (0x01C05000 + 0x20) -#define SUN4I_SPI0_TC (0x01C05000 + 0x24) +#define SUN4I_SPI0_CCTL 0x1C +#define SUN4I_SPI0_CTL 0x08 +#define SUN4I_SPI0_RX 0x00 +#define SUN4I_SPI0_TX 0x04 +#define SUN4I_SPI0_FIFO_STA 0x28 +#define SUN4I_SPI0_BC 0x20 +#define SUN4I_SPI0_TC 0x24 #define SUN4I_CTL_ENABLE BIT(0) #define SUN4I_CTL_MASTER BIT(1) @@ -54,15 +54,15 @@ /* SUN6I variant of the SPI controller */ /*****************************************************************************/ -#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) -#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) -#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) -#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) -#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) -#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) -#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) -#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) -#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) +#define SUN6I_SPI0_CCTL 0x24 +#define SUN6I_SPI0_GCR 0x04 +#define SUN6I_SPI0_TCR 0x08 +#define SUN6I_SPI0_FIFO_STA 0x1C +#define SUN6I_SPI0_MBC 0x30 +#define SUN6I_SPI0_MTC 0x34 +#define SUN6I_SPI0_BCC 0x38 +#define SUN6I_SPI0_TXD 0x200 +#define SUN6I_SPI0_RXD 0x300 #define SUN6I_CTL_ENABLE BIT(0) #define SUN6I_CTL_MASTER BIT(1) @@ -72,7 +72,12 @@ /*****************************************************************************/ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) +#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) +#ifdef CONFIG_MACH_SUN50I_H6 +#define CCM_SPI0_CLK (0x03001000 + 0x940) +#else #define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#endif #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) #define AHB_RESET_SPI0_SHIFT 20 @@ -86,74 +91,111 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + * The H6 uses PC0, PC2, PC3, PC5. */ static void spi0_pinmux_setup(unsigned int pin_function) { - unsigned int pin; + /* All chips use PC0 and PC2. */ + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) - sunxi_gpio_set_cfgpin(pin, pin_function); + /* All chips except H6 use PC1, and only H6 uses PC5. */ + if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) + /* Older generations use PC23 for CS, newer ones use PC3. */ + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40)) sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); else sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); } +static bool is_sun6i_gen_spi(void) +{ + return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6); +} + +static uintptr_t spi0_base_address(void) +{ + if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) + return 0x01C05000; + + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + return 0x05010000; + + if (!is_sun6i_gen_spi()) + return 0x01C05000; + + return 0x01C68000; +} + /* * Setup 6 MHz from OSC24M (because the BROM is doing the same). */ static void spi0_enable_clock(void) { + uintptr_t base = spi0_base_address(); + /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); + else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (is_sun6i_gen_spi()) { /* Enable SPI in the master mode and do a soft reset */ - setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE | - SUN6I_CTL_SRST); + setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | SUN6I_CTL_SRST); /* Wait for completion */ - while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; } else { /* Enable SPI in the master mode and reset FIFO */ - setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | - SUN4I_CTL_ENABLE | - SUN4I_CTL_TF_RST | - SUN4I_CTL_RF_RST); + setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE | + SUN4I_CTL_TF_RST | + SUN4I_CTL_RF_RST); } } static void spi0_disable_clock(void) { + uintptr_t base = spi0_base_address(); + /* Disable the SPI0 controller */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + if (is_sun6i_gen_spi()) + clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | SUN6I_CTL_ENABLE); else - clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | SUN4I_CTL_ENABLE); /* Disable the SPI0 clock */ writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); + else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); } @@ -162,7 +204,8 @@ static void spi0_init(void) { unsigned int pin_function = SUNXI_GPC_SPI0; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUN50I_GPC_SPI0; spi0_pinmux_setup(pin_function); @@ -173,7 +216,8 @@ static void spi0_deinit(void) { /* New SoCs can disable pins, older could only set them as input */ unsigned int pin_function = SUNXI_GPIO_INPUT; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + + if (is_sun6i_gen_spi()) pin_function = SUNXI_GPIO_DISABLE; spi0_disable_clock(); @@ -227,31 +271,32 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) { u8 *buf8 = buf; u32 chunk_len; + uintptr_t base = spi0_base_address(); while (len > 0) { chunk_len = len; if (chunk_len > SPI_READ_MAX_SIZE) chunk_len = SPI_READ_MAX_SIZE; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (is_sun6i_gen_spi()) { sunxi_spi0_read_data(buf8, addr, chunk_len, - SUN6I_SPI0_TCR, + base + SUN6I_SPI0_TCR, SUN6I_TCR_XCH, - SUN6I_SPI0_FIFO_STA, - SUN6I_SPI0_TXD, - SUN6I_SPI0_RXD, - SUN6I_SPI0_MBC, - SUN6I_SPI0_MTC, - SUN6I_SPI0_BCC); + base + SUN6I_SPI0_FIFO_STA, + base + SUN6I_SPI0_TXD, + base + SUN6I_SPI0_RXD, + base + SUN6I_SPI0_MBC, + base + SUN6I_SPI0_MTC, + base + SUN6I_SPI0_BCC); } else { sunxi_spi0_read_data(buf8, addr, chunk_len, - SUN4I_SPI0_CTL, + base + SUN4I_SPI0_CTL, SUN4I_CTL_XCH, - SUN4I_SPI0_FIFO_STA, - SUN4I_SPI0_TX, - SUN4I_SPI0_RX, - SUN4I_SPI0_BC, - SUN4I_SPI0_TC, + base + SUN4I_SPI0_FIFO_STA, + base + SUN4I_SPI0_TX, + base + SUN4I_SPI0_RX, + base + SUN4I_SPI0_BC, + base + SUN4I_SPI0_TC, 0); } diff --git a/arch/powerpc/dts/gdsys/mpc8308.dtsi b/arch/powerpc/dts/gdsys/mpc8308.dtsi index 23e7403d911..1a319e23287 100644 --- a/arch/powerpc/dts/gdsys/mpc8308.dtsi +++ b/arch/powerpc/dts/gdsys/mpc8308.dtsi @@ -17,6 +17,7 @@ /dts-v1/; #include <dt-bindings/memory/mpc83xx-sdram.h> +#include <dt-bindings/clk/mpc83xx-clk.h> / { compatible = "fsl,mpc8308rdb"; @@ -50,6 +51,11 @@ }; }; + socclocks: clocks { + compatible = "fsl,mpc8308-clk"; + #clock-cells = <1>; + }; + board_lbc: localbus@e0005000 { #address-cells = <2>; #size-cells = <1>; @@ -173,6 +179,7 @@ reg = <0x7000 0x1000>; interrupts = <16 0x8>; interrupt-parent = <&ipic>; + clocks = <&socclocks MPC83XX_CLK_CSB>; mode = "cpu"; }; |