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-rw-r--r--board/amcc/acadia/Makefile47
-rw-r--r--board/amcc/acadia/acadia.c152
-rw-r--r--board/amcc/acadia/config.mk41
-rw-r--r--board/amcc/acadia/cpr.c195
-rw-r--r--board/amcc/acadia/flash.c1108
-rw-r--r--board/amcc/acadia/memory.c552
-rw-r--r--board/amcc/acadia/u-boot.lds150
-rw-r--r--board/amcc/ebony/init.S77
-rw-r--r--board/amcc/katmai/init.S10
-rw-r--r--board/amcc/luan/init.S170
-rw-r--r--board/amcc/luan/luan.c99
-rw-r--r--board/amcc/luan/u-boot.lds13
-rw-r--r--board/amcc/ocotea/init.S82
-rw-r--r--board/amcc/sequoia/sdram.c21
-rw-r--r--board/amcc/sequoia/sequoia.c4
-rw-r--r--board/amcc/yucca/init.S83
-rw-r--r--board/amcc/yucca/yucca.c316
17 files changed, 2394 insertions, 726 deletions
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
new file mode 100644
index 00000000000..183f694c7b8
--- /dev/null
+++ b/board/amcc/acadia/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o cpr.o memory.o
+SOBJS =
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
new file mode 100644
index 00000000000..c8aaad2d785
--- /dev/null
+++ b/board/amcc/acadia/acadia.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+/* Some specific Acadia Defines */
+#define CPLD_BASE 0x80000000
+
+void liveoak_gpio_init(void)
+{
+ /*
+ * GPIO0 setup (select GPIO or alternate function)
+ */
+ out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+
+ /*
+ * Ultra (405EZ) was nice enough to add another GPIO controller
+ */
+ out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
+ out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
+ out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
+ out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
+ out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
+ out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
+ out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
+}
+
+#if 0 /* test-only: not called at all??? */
+void ext_bus_cntlr_init(void)
+{
+#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
+ mtebc(pb4ap, EBC_PB4AP);
+ mtebc(pb4cr, EBC_PB4CR);
+#endif
+}
+#endif
+
+int board_early_init_f(void)
+{
+ unsigned int reg;
+
+#if 0 /* test-only */
+ /*
+ * If CRAM memory and SPI/NAND boot, and if the CRAM memory is
+ * already initialized by the pre-loader then we can't reinitialize
+ * CPR registers, GPIO registers and EBC registers as this will
+ * have the effect of un-initializing CRAM.
+ */
+ spr_reg = (volatile unsigned long) mfspr(SPRG7);
+ if (spr_reg != LOAK_CRAM) { /* != CRAM */
+ board_pll_init_f();
+ liveoak_gpio_init();
+ ext_bus_cntlr_init();
+
+ mtebc(pb1ap, CFG_EBC_PB1AP);
+ mtebc(pb1cr, CFG_EBC_PB1CR);
+
+ mtebc(pb2ap, CFG_EBC_PB2AP);
+ mtebc(pb2cr, CFG_EBC_PB2CR);
+ }
+#else
+ board_pll_init_f();
+ liveoak_gpio_init();
+/* ext_bus_cntlr_init(); */
+#endif
+
+#if 0 /* test-only (orig) */
+ /*
+ * If we boot from NAND Flash, we are running in
+ * RAM, so disable the EBC_CS0 so that it goes back
+ * to the NOR Flash. It will be enabled later
+ * for the NAND Flash on EBC_CS1
+ */
+ mfsdr(sdrultra0, reg);
+ mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
+#endif
+#if 0 /* test-only */
+ /* configure for NAND */
+ mfsdr(sdrultra0, reg);
+ reg &= ~SDR_ULTRA0_CSN_MASK;
+ reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
+ mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
+#endif
+
+ /* USB Host core needs this bit set */
+ mfsdr(sdrultra1, reg);
+ mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000010);
+ mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
+ mtdcr(uictr, 0x00000010); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int misc_init_f(void)
+{
+ /* Set EPLD to take PHY out of reset */
+ out8(CPLD_BASE + 0x05, 0x00);
+ udelay(100000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
new file mode 100644
index 00000000000..ce213746589
--- /dev/null
+++ b/board/amcc/acadia/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFC0000
+endif
+
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+
+ifeq ($(CONFIG_SPI_U_BOOT),y)
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds
+PAD_TO = 0x00840000
+endif
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c
new file mode 100644
index 00000000000..23b9e1242bc
--- /dev/null
+++ b/board/amcc/acadia/cpr.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 200.0 | 4 (0x02)|
+ * | PLB | 133.3 | 6 (0x06)|
+ * | OPB | 66.6 | 12 (0x0C)|
+ * | EBC | 66.6 | 12 (0x0C)|
+ * | SPI | 66.6 | 12 (0x0C)|
+ * | UART0 | 10.0 | 40 (0x28)|
+ * | UART1 | 10.0 | 40 (0x28)|
+ * | DAC | 2.0 | 200 (0xC8)|
+ * | ADC | 2.0 | 200 (0xC8)|
+ * | PWM | 100.0 | 4 (0x04)|
+ * | EMAC | 25.0 | 16 (0x10)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x0000033c);
+ mtcpr(cprplld, 0x0c010200);
+ mtcpr(cprprimad, 0x04060c0c);
+ mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 266.64 | 3 |
+ * | PLB | 159.98 | 5 (0x05)|
+ * | OPB | 79.99 | 10 (0x0A)|
+ * | EBC | 79.99 | 10 (0x0A)|
+ * | SPI | 79.99 | 10 (0x0A)|
+ * | UART0 | 28.57 | 7 (0x07)|
+ * | UART1 | 28.57 | 7 (0x07)|
+ * | DAC | 28.57 | 7 (0xA7)|
+ * | ADC | 4 | 50 (0x32)|
+ * | PWM | 28.57 | 7 (0x07)|
+ * | EMAC | 4 | 50 (0x32)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x20000238);
+ mtcpr(cprplld, 0x03010400);
+ mtcpr(cprprimad, 0x03050a0a);
+ mtcpr(cprperc0, 0x00000000);
+ mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0x07323200);
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 333.33 | 2 |
+ * | PLB | 166.66 | 4 (0x04)|
+ * | OPB | 83.33 | 8 (0x08)|
+ * | EBC | 83.33 | 8 (0x08)|
+ * | SPI | 83.33 | 8 (0x08)|
+ * | UART0 | 16.66 | 5 (0x05)|
+ * | UART1 | 16.66 | 5 (0x05)|
+ * | DAC | ???? | 166 (0xA6)|
+ * | ADC | ???? | 166 (0xA6)|
+ * | PWM | 41.66 | 3 (0x03)|
+ * | EMAC | ???? | 3 (0x03)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x0000033C);
+ mtcpr(cprplld, 0x0a010000);
+ mtcpr(cprprimad, 0x02040808);
+ mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0xA6A60300);
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------
+ * | CLK | FREQ (MHz) |
+ * ----------------------
+ * | CPU | 100.00 |
+ * | PLB | 100.00 |
+ * | OPB | 12.00 |
+ * | EBC | 49.00 |
+ * ----------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x000003BC);
+ mtcpr(cprplld, 0x06060600);
+ mtcpr(cprprimad, 0x02020004);
+ mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0xC8C81600);
+ mtcpr(cprclkupd, 0x40000000);
+}
+#endif /* CPU_<speed>_405EZ */
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk (void)
+{
+ unsigned long cpr_plld;
+ unsigned long cpr_primad;
+ unsigned long primad_cpudv;
+ unsigned long pllFbkDiv;
+ unsigned long freqProcessor;
+
+ /*
+ * Read PLL Mode registers
+ */
+ mfcpr(cprplld, cpr_plld);
+
+ /*
+ * Read CPR_PRIMAD register
+ */
+ mfcpr(cprprimad, cpr_primad);
+
+ /*
+ * Determine CPU clock frequency
+ */
+ primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+ if (primad_cpudv == 0)
+ primad_cpudv = 16;
+
+ /*
+ * Determine FBK_DIV.
+ */
+ pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+ if (pllFbkDiv == 0)
+ pllFbkDiv = 256;
+
+ freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
+
+ return (freqProcessor);
+}
+#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/board/amcc/acadia/flash.c b/board/amcc/acadia/flash.c
new file mode 100644
index 00000000000..0626aba9d57
--- /dev/null
+++ b/board/amcc/acadia/flash.c
@@ -0,0 +1,1108 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+ {0xffc00001}, /* 0:boot from big flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ case FLASH_MAN_MX:
+ printf("MIXC ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_MXLV320T:
+ printf ("MXLV320T (32 Mbit, top sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1) {
+ return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ int n;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+#if 0 /* TODO: remove ifdef when Flash responds correctly */
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+#endif /* TODO: remove ifdef when Flash responds correctly */
+
+ /*
+ * TODO: Start
+ * uncomment block above when Flash responds correctly.
+ * also remove the lines below:
+ */
+ info->flash_id = FLASH_MAN_AMD;
+ DEBUGF("FLASH MANUFACT: FLASH_MAN_AMD\n");
+ /* TODO: End */
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+#if 0 /* TODO: remove ifdef when Flash responds correctly */
+ switch (value) {
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+ info->flash_id += FLASH_MXLV320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+#endif /* TODO: remove ifdef when Flash responds correctly */
+
+ /*
+ * TODO: Start
+ * uncomment block above when Flash responds correctly.
+ * also remove the lines below:
+ */
+ DEBUGF("\nFLASH DEVICEID: FLASH_AM320T\n");
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; /* => 4 MB */
+ /* TODO: End */
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n=0; n<2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else if ( ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ) {
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ else {
+ if (info->flash_id & FLASH_BTYPE){
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address,(A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+/*
+ * TODO: FIX: this wait loop sometimes fails: DQ7 indicates the erase command
+ * never was accepted (i.e. didn't start) - why????
+ */
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last, counter = 0;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ DEBUGF("DQ7_2: start = 0x%08lx\n", start);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now);
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ udelay(1000000); /* 1 sec */
+ putc('.');
+ counter++;
+ if (counter > 5) {
+ return -1;
+ }
+ DEBUGF("DQ7_2: now = 0x%08lx, last = 0x%08lx\n", now, last);
+ }
+ return 0;
+}
+
+static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value)
+{
+ int fw_size;
+
+ fw_size = sizeof(value);
+ switch (fw_size)
+ {
+ case 1:
+ out8((ulong)(sector + addr), value);
+ break;
+ case 2:
+ out16((ulong)(sector + (addr << 1)), value);
+ break;
+ default:
+ printf("flash_erase: error incorrect chip programing size.\n");
+ }
+ return;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect, count = 0;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first, count = 0; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ /*
+ * TODO: fix code
+ */
+ wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00800080);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA);
+ wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055);
+ wr_flash_cmd((ulong)addr2, 0, (CFG_FLASH_WORD_SIZE) 0x00300030);
+ udelay(2000000); /* 2 sec */
+ wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0);
+
+#if 0
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+#endif
+ }
+ l_sect = sect;
+ printf("..");
+ printf("..");
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ count++;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+
+ if (count > 0) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ index = 0;
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
new file mode 100644
index 00000000000..a1b015519a7
--- /dev/null
+++ b/board/amcc/acadia/memory.c
@@ -0,0 +1,552 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define CRAM_BANK0_BASE 0x0
+#define CRAM_DIDR 0x00100000
+#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
+#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
+#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
+#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
+#define CRAM_DEVID_NOT_SUPPORTED 0x00000000
+
+#define PSRAM_PASS 0x50415353 /* "PASS" */
+#define PSRAM_FAIL 0x4641494C /* "FAIL" */
+
+static u32 is_cram_inited(void);
+static u32 is_cram(void);
+static long int cram_init(u32);
+static void cram_bcr_write(u32);
+void udelay (unsigned long);
+
+void sdram_init(void)
+{
+ volatile unsigned long spr_reg;
+
+ /*
+ * If CRAM not initialized or CRAM looks initialized because this
+ * is after a warm reboot then set SPRG7 to indicate CRAM needs
+ * initialization. Note that CRAM is initialized by the SPI and
+ * NAND preloader.
+ */
+ spr_reg = (volatile unsigned long) mfspr(SPRG6);
+ if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
+ mtspr(SPRG7, LOAK_NONE); /* "NONE" */
+ }
+#if 1
+ /*
+ * When running the NAND SPL, the normal EBC configuration is not
+ * done, so We need to enable EPLD access on EBC_CS_2 and the memory
+ * on EBC_CS_3
+ */
+
+ /* Enable CPLD - Needed for PSRAM Access */
+
+
+ /* Init SDRAM by setting EBC Bank 3 for PSRAM */
+ mtebc(pb1ap, CFG_EBC_PB1AP);
+ mtebc(pb1cr, CFG_EBC_PB1CR);
+
+ mtebc(pb2ap, CFG_EBC_PB2AP);
+ mtebc(pb2cr, CFG_EBC_PB2CR);
+
+ /* pre-boot loader code: we are in OCM */
+ mtspr(SPRG6, LOAK_SPL); /* "SPL " */
+ mtspr(SPRG7, LOAK_OCM); /* "OCM " */
+#endif
+ return;
+}
+
+static void cram_bcr_write(u32 wr_val)
+{
+ u32 tmp_reg;
+ u32 val;
+ volatile u32 gpio_reg;
+
+ /* # Program CRAM write */
+
+ /*
+ * set CRAM_CRE = 0x1
+ * set wr_val = wr_val << 2
+ */
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg | 0x00000400);
+ wr_val = wr_val << 2;
+ /* wr_val = 0x1c048; */
+
+ /*
+ * # stop PLL clock before programming CRAM
+ * set EPLD0_MUX_CTL.OESPR3 = 1
+ * delay 2
+ */
+
+ /*
+ * # CS1
+ * read 0x00200000
+ * #shift 2 bit left before write
+ * set val = wr_val + 0x00200000
+ * write dmem val 0
+ * read 0x00200000 val
+ * print val/8x
+ */
+ tmp_reg = in32(0x00200000);
+ val = wr_val + 0x00200000;
+ /* val = 0x0021c048; */
+ out32(val, 0x0000);
+ udelay(100000);
+ val = in32(0x00200000);
+
+ debug("CRAM VAL: %x for CS1 ", val);
+
+ /*
+ * # CS2
+ * read 0x02200000
+ * #shift 2 bit left before write
+ * set val = wr_val + 0x02200000
+ * write dmem val 0
+ * read 0x02200000 val
+ * print val/8x
+ */
+ tmp_reg = in32(0x02200000);
+ val = wr_val + 0x02200000;
+ /* val = 0x0221c048; */
+ out32(val, 0x0000);
+ udelay(100000);
+ val = in32(0x02200000);
+
+ debug("CRAM VAL: %x for CS2 ", val);
+
+ /*
+ * # Start PLL clock before programming CRAM
+ * set EPLD0_MUX_CTL.OESPR3 = 0
+ */
+
+ /*
+ * set CRAMCR = 0x1
+ */
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg | 0x00000400);
+
+ /*
+ * # read CRAM config BCR ( bit19:18 = 10b )
+ * #read 0x00200000
+ * # 1001_1001_0001_1111 ( 991f ) =>
+ * #10_0110_0100_0111_1100 => 2647c => 0022647c
+ * #0011_0010_0011_1110 (323e)
+ * #
+ */
+
+ /*
+ * set EPLD0_MUX_CTL.CRAMCR = 0x0
+ */
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
+ return;
+}
+
+static u32 is_cram_inited()
+{
+ volatile unsigned long spr_reg;
+
+ /*
+ * If CRAM is initialized already, then don't reinitialize it again.
+ * In the case of NAND boot and SPI boot, CRAM will already be
+ * initialized by the pre-loader
+ */
+ spr_reg = (volatile unsigned long) mfspr(SPRG7);
+ if (spr_reg == LOAK_CRAM) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/******
+ * return 0 if not CRAM
+ * return 1 if CRAM and it's already inited by preloader
+ * else return cram_id (CRAM Device Identification Register)
+ ******/
+static u32 is_cram(void)
+{
+ u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
+ volatile u32 gpio_reg;
+ volatile u32 cram_id = 0;
+
+ if (is_cram_inited() == 1) {
+ /* this is CRAM and it is already inited (by preloader) */
+ cram_id = 1;
+ } else {
+ /*
+ * # CRAM CLOCK
+ * set GPIO0_TCR.G8 = 1
+ * set GPIO0_OSRL.G8 = 0
+ * set GPIO0_OR.G8 = 0
+ */
+ gpio_reg = in32(GPIO0_TCR);
+ gpio_TCR = gpio_reg;
+ out32(GPIO0_TCR, gpio_reg | 0x00800000);
+ gpio_reg = in32(GPIO0_OSRL);
+ gpio_OSRL = gpio_reg;
+ out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
+ gpio_reg = in32(GPIO0_OR);
+ gpio_OR = gpio_reg;
+ out32(GPIO0_OR, gpio_reg & 0xff7fffff);
+
+ /*
+ * # CRAM Addreaa Valid
+ * set GPIO0_TCR.G10 = 1
+ * set GPIO0_OSRL.G10 = 0
+ * set GPIO0_OR.G10 = 0
+ */
+ gpio_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, gpio_reg | 0x00200000);
+ gpio_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
+ gpio_reg = in32(GPIO0_OR);
+ out32(GPIO0_OR, gpio_reg & 0xffdfffff);
+
+ /*
+ * # config input (EBC_WAIT)
+ * set GPIO0_ISR1L.G9 = 1
+ * set GPIO0_TCR.G9 = 0
+ */
+ gpio_reg = in32(GPIO0_ISR1L);
+ gpio_ISR1L = gpio_reg;
+ out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
+ gpio_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
+
+ /*
+ * Enable CRE to read Registers
+ * set GPIO0_TCR.21 = 1
+ * set GPIO1_OR.21 = 1
+ */
+ gpio_reg = in32(GPIO1_TCR);
+ out32(GPIO1_TCR, gpio_reg | 0x00000400);
+
+ gpio_reg = in32(GPIO1_OR);
+ out32(GPIO1_OR, gpio_reg | 0x00000400);
+
+ /* Read Version ID */
+ cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
+ udelay(100000);
+
+ asm volatile(" sync");
+ asm volatile(" eieio");
+
+ debug("Cram ID: %X ", cram_id);
+
+ switch (cram_id) {
+ case MICRON_MT45W8MW16BGX_CRAM_ID:
+ case MICRON_MT45W8MW16BGX_CRAM_ID2:
+ /* supported CRAM vendor/part */
+ break;
+ case CRAM_DEVID_NOT_SUPPORTED:
+ default:
+ /* check for DIDR Vendor ID of Micron */
+ if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
+ MICRON_DIDR_VENDOR_ID)
+ {
+ /* supported CRAM vendor */
+ break;
+ }
+ /* this is not CRAM or not supported CRAM vendor/part */
+ cram_id = 0;
+ /*
+ * reset the GPIO registers to the values that were
+ * there before this routine
+ */
+ out32(GPIO0_TCR, gpio_TCR);
+ out32(GPIO0_OSRL, gpio_OSRL);
+ out32(GPIO0_OR, gpio_OR);
+ out32(GPIO0_ISR1L, gpio_ISR1L);
+ break;
+ }
+ }
+
+ return cram_id;
+}
+
+static long int cram_init(u32 already_inited)
+{
+ volatile u32 tmp_reg;
+ u32 cram_wr_val;
+
+ if (already_inited == 0) return 0;
+
+ /*
+ * If CRAM is initialized already, then don't reinitialize it again.
+ * In the case of NAND boot and SPI boot, CRAM will already be
+ * initialized by the pre-loader
+ */
+ if (already_inited != 1) {
+ /*
+ * #o CRAM Card
+ * # - CRAMCRE @reg16 = 1; for CRAM to use
+ * # - CRAMCRE @reg16 = 0; for CRAM to program
+ *
+ * # enable CRAM SEL, move from setEPLD.cmd
+ * set EPLD0_MUX_CTL.OECRAM = 0
+ * set EPLD0_MUX_CTL.CRAMCR = 1
+ * set EPLD0_ETHRSTBOOT.SLCRAM = 0
+ * #end
+ */
+
+ /*
+ * #1. EBC need to program READY, CLK, ADV for ASync mode
+ * # config output
+ */
+
+ /*
+ * # CRAM CLOCK
+ * set GPIO0_TCR.G8 = 1
+ * set GPIO0_OSRL.G8 = 0
+ * set GPIO0_OR.G8 = 0
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00800000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
+ tmp_reg = in32(GPIO0_OR);
+ out32(GPIO0_OR, tmp_reg & 0xff7fffff);
+
+ /*
+ * # CRAM Addreaa Valid
+ * set GPIO0_TCR.G10 = 1
+ * set GPIO0_OSRL.G10 = 0
+ * set GPIO0_OR.G10 = 0
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00200000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
+ tmp_reg = in32(GPIO0_OR);
+ out32(GPIO0_OR, tmp_reg & 0xffdfffff);
+
+ /*
+ * # config input (EBC_WAIT)
+ * set GPIO0_ISR1L.G9 = 1
+ * set GPIO0_TCR.G9 = 0
+ */
+ tmp_reg = in32(GPIO0_ISR1L);
+ out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
+
+ /*
+ * # config CS4 from GPIO
+ * set GPIO0_TCR.G0 = 1
+ * set GPIO0_OSRL.G0 = 1
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x80000000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg | 0x40000000);
+
+ /*
+ * #2. EBC in Async mode
+ * # set EBC0_PB1AP = 0x078f0ec0
+ * set EBC0_PB1AP = 0x078f1ec0
+ * set EBC0_PB2AP = 0x078f1ec0
+ */
+ mtebc(pb1ap, 0x078F1EC0);
+ mtebc(pb2ap, 0x078F1EC0);
+
+ /*
+ * #set EBC0_PB1CR = 0x000bc000
+ * #enable CS2 for CRAM
+ * set EBC0_PB2CR = 0x020bc000
+ */
+ mtebc(pb1cr, 0x000BC000);
+ mtebc(pb2cr, 0x020BC000);
+
+ /*
+ * #3. set CRAM in Sync mode
+ * #exec cm_bcr_write.cmd { 0x701f }
+ * #3. set CRAM in Sync mode (full drv strength)
+ * exec cm_bcr_write.cmd { 0x701F }
+ */
+ cram_wr_val = 0x7012; /* CRAM burst setting */
+ cram_bcr_write(cram_wr_val);
+
+ /*
+ * #4. EBC in Sync mode
+ * #set EBC0_PB1AP = 0x9f800fc0
+ * #set EBC0_PB1AP = 0x900001c0
+ * set EBC0_PB2AP = 0x9C0201c0
+ * set EBC0_PB2AP = 0x9C0201c0
+ */
+ mtebc(pb1ap, 0x9C0201C0);
+ mtebc(pb2ap, 0x9C0201C0);
+
+ /*
+ * #5. EBC need to program READY, CLK, ADV for Sync mode
+ * # config output
+ * set GPIO0_TCR.G8 = 1
+ * set GPIO0_OSRL.G8 = 1
+ * set GPIO0_TCR.G10 = 1
+ * set GPIO0_OSRL.G10 = 1
+ */
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00800000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg | 0x00004000);
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg | 0x00200000);
+ tmp_reg = in32(GPIO0_OSRL);
+ out32(GPIO0_OSRL, tmp_reg | 0x00000400);
+
+ /*
+ * # config input
+ * set GPIO0_ISR1L.G9 = 1
+ * set GPIO0_TCR.G9 = 0
+ */
+ tmp_reg = in32(GPIO0_ISR1L);
+ out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
+ tmp_reg = in32(GPIO0_TCR);
+ out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
+
+ /*
+ * # config EBC to use RDY
+ * set SDR0_ULTRA0.EBCREN = 1
+ */
+ mfsdr(sdrultra0, tmp_reg);
+ mtsdr(sdrultra0, tmp_reg | 0x04000000);
+
+ /*
+ * set EPLD0_MUX_CTL.OESPR3 = 0
+ */
+ mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
+ } /* if (already_inited != 1) */
+
+ return (64 * 1024 * 1024);
+}
+
+/******
+ * return 0 if not PSRAM
+ * return 1 if is PSRAM
+ ******/
+static int is_psram(u32 addr)
+{
+ u32 test_pattern = 0xdeadbeef;
+ volatile u32 readback;
+
+ if (addr == CFG_SDRAM_BASE) {
+ /* This is to temp enable OE for PSRAM */
+ out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
+ udelay(10000);
+ }
+
+ out32(addr, test_pattern);
+ asm volatile(" sync");
+ asm volatile(" eieio");
+
+ readback = (volatile u32) in32(addr);
+ asm volatile(" sync");
+ asm volatile(" eieio");
+ if (readback == test_pattern) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static long int psram_init(void)
+{
+ u32 readback;
+ long psramsize = 0;
+ int i;
+
+ /* This is to temp enable OE for PSRAM */
+ out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
+ udelay(10000);
+
+ /*
+ * PSRAM bank 1: read then write to address 0x00000000
+ */
+ for (i = 0; i < 100; i++) {
+ if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
+ readback = PSRAM_PASS;
+ } else {
+ readback = PSRAM_FAIL;
+ break;
+ }
+ }
+ if (readback == PSRAM_PASS) {
+ debug("psram_init(bank0): pass\n");
+ psramsize = (16 * 1024 * 1024);
+ } else {
+ debug("psram_init(bank0): fail\n");
+ return 0;
+ }
+
+#if 0
+ /*
+ * PSRAM bank 1: read then write to address 0x01000000
+ */
+ for (i = 0; i < 100; i++) {
+ if (is_psram((1 << 24) + (i*256)) == 1) {
+ readback = PSRAM_PASS;
+ } else {
+ readback = PSRAM_FAIL;
+ break;
+ }
+ }
+ if (readback == PSRAM_PASS) {
+ debug("psram_init(bank1): pass\n");
+ psramsize = psramsize + (16 * 1024 * 1024);
+ }
+#endif
+
+ mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
+
+ return psramsize;
+}
+
+long int initdram(int board_type)
+{
+ long int sram_size;
+ u32 cram_inited;
+
+ /* Determine Attached Memory Expansion Card*/
+ cram_inited = is_cram();
+ if (cram_inited != 0) { /* CRAM */
+ debug("CRAM Expansion Card attached\n");
+ sram_size = cram_init(cram_inited);
+ } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
+ debug("PSRAM Expansion Card attached\n");
+ sram_size = psram_init();
+ } else { /* no SRAM */
+ debug("No Memory Card Attached!!\n");
+ sram_size = 0;
+ }
+
+ return sram_size;
+}
+
+int testdram(void)
+{
+ return (0);
+}
diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds
new file mode 100644
index 00000000000..be030923b8e
--- /dev/null
+++ b/board/amcc/acadia/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
index cc8f8b444e0..c86076e8069 100644
--- a/board/amcc/ebony/init.S
+++ b/board/amcc/ebony/init.S
@@ -22,53 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -81,16 +35,23 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index f5900bcb7b5..6b024eec40c 100644
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -46,6 +46,11 @@
.globl tlbtabA
tlbtabA:
tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
/*
@@ -81,6 +86,11 @@ tlbtabA:
.globl tlbtabB
tlbtabB:
tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
/*
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index 7830ebdfa6d..d5ee117dfac 100644
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -1,73 +1,31 @@
/*
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -80,53 +38,37 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
-
-#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
- /* large flash */
- tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
- tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
- tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
- tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-
- tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-#else /* else booting from small flash */
- tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-
- tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#endif
-
- tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
-
-#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
- tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
- tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#elif (CFG_SMALL_FLASH == 0xfff00000)
- tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#else
- #error DONT KNOW SRAM LOCATION
-#endif
-
- /* internal ram (l2 cache) */
- tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
-
- /* peripherals at f0000000 */
- tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
-
- /* PCI */
-#if (CONFIG_COMMANDS & CFG_CMD_PCI)
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
-#endif
- tlbtab_end
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
+
+ tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ /* internal ram (l2 cache) */
+ tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+
+ /* peripherals at f0000000 */
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+
+ /* PCI */
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 06a57f6c4aa..778aafc7660 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -106,105 +106,6 @@ int checkboard(void)
/*************************************************************************
- * long int fixed_sdram()
- *
- ************************************************************************/
-static long int fixed_sdram(void)
-{ /* DDR2 init from BDI2000 script */
- mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
- mtdcr( 0x11, 0x84000000 );
- mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
- mtdcr( 0x11, 0x2D122000 );
- mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
- mtdcr( 0x11, 0x00800026 );
- mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
- mtdcr( 0x11, 0x82000800 );
- mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
- mtdcr( 0x11, 0x80000000 );
- mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
- mtdcr( 0x11, 0x00000201 );
- mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
- mtdcr( 0x11, 0x00000201 );
- mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
- mtdcr( 0x11, 0x08200000 );
- mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
- mtdcr( 0x11, 0x80201000 );
- mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
- mtdcr( 0x11, 0x42103242 );
- mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
- mtdcr( 0x11, 0x0C100D14 );
- mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
- mtdcr( 0x11, 0x00000642 );
- mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
- mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
-
- mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
- mtdcr( 0x11, 0x81b80000 );
- mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
- mtdcr( 0x11, 0x82100400 );
- mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
- mtdcr( 0x11, 0x80820000 );
- mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
- mtdcr( 0x11, 0x80830000 );
- mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
- mtdcr( 0x11, 0x80810000 );
- mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
- mtdcr( 0x11, 0x80800542 );
- mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
- mtdcr( 0x11, 0x82100400 );
- mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
- mtdcr( 0x11, 0x80800442 );
- mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
- mtdcr( 0x11, 0x80810380 );
- mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
- mtdcr( 0x11, 0x80810000 );
- udelay( 10*1000 );
-
- mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
- mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
- udelay( 100*1000 );
-
- mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
- mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
-
- mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
- mtdcr( 0x11, 0x00000000 );
- mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
- mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
- mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
- mtdcr( 0x11, 0x00000200 );
-
- return 512 << 20;
-}
-
-
-/*************************************************************************
- * long int initdram
- *
- ************************************************************************/
-long int initdram( int board_type )
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram (0);
-#else
- dram_size = fixed_sdram ();
-#endif
-
- return dram_size;
-}
-
-
-/*************************************************************************
* int testdram()
*
************************************************************************/
diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds
index d122f499f1b..72ce6855d75 100644
--- a/board/amcc/luan/u-boot.lds
+++ b/board/amcc/luan/u-boot.lds
@@ -68,19 +68,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
board/amcc/luan/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
index 7e0b1324929..d211c710b23 100644
--- a/board/amcc/ocotea/init.S
+++ b/board/amcc/ocotea/init.S
@@ -22,55 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-#define _256M 0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -83,19 +35,23 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 77f14384480..f8b837ed286 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -6,7 +6,7 @@
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@@ -379,16 +379,18 @@ void denali_core_search_data_eye(unsigned long memory_size)
long int initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ ulong speed = get_bus_freq(0);
+
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x13030300);
- mtsdram(DDR0_05, 0x0202050E);
- mtsdram(DDR0_06, 0x0104C823);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0102C812);
mtsdram(DDR0_07, 0x000D0100);
- mtsdram(DDR0_08, 0x02360001);
+ mtsdram(DDR0_08, 0x02430001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000300);
mtsdram(DDR0_11, 0x0027C800);
@@ -402,13 +404,16 @@ long int initdram (int board_type)
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
- mtsdram(DDR0_26, 0x5B260181);
+ if (speed > 133333333)
+ mtsdram(DDR0_26, 0x5B26050C);
+ else
+ mtsdram(DDR0_26, 0x5B260408);
mtsdram(DDR0_27, 0x0000682B);
mtsdram(DDR0_28, 0x00000000);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000006);
- mtsdram(DDR0_43, 0x050A0200);
- mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_43, 0x030A0200);
+ mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
wait_for_dlllock();
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index b2b82c75954..daaffe06d35 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -336,6 +336,10 @@ int misc_init_r(void)
}
#endif /* CONFIG_440EPX */
+ mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
+ reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+ mtsdr(SDR0_SRST1, reg);
+
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index c9eca686b25..c92dcf7a514 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
@@ -19,56 +22,10 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a) ((a) & 0x00000fbf)
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ;\
-0: mflr r0 ;\
- mtlr r1 ;\
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -89,12 +46,18 @@
.globl tlbtabA
tlbtabA:
tlbtab_start
- tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
@@ -126,12 +89,18 @@ tlbtabA:
.globl tlbtabB
tlbtabB:
tlbtab_start
- tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index e9b34dd249a..90eaab1c80b 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -44,8 +44,6 @@ int compare_to_true(char *str );
char *remove_l_w_space(char *in_str );
char *remove_t_w_space(char *in_str );
int get_console_port(void);
-unsigned long ppcMfcpr(unsigned long cpr_reg);
-unsigned long ppcMfsdr(unsigned long sdr_reg);
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
@@ -221,7 +219,7 @@ int board_early_init_f (void)
|
+-------------------------------------------------------------------*/
/* Read Pin Strap Register in PPC440SP */
- sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
+ mfsdr(SDR0_PINSTP, sdr0_pinstp);
bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
switch (bootstrap_settings) {
@@ -246,7 +244,7 @@ int board_early_init_f (void)
* Boot Settings in IIC EEprom address 0x50 or 0x54
* Read Serial Device Strap Register1 in PPC440SPe
*/
- sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
+ mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
@@ -564,277 +562,6 @@ int checkboard (void)
return 0;
}
-static long int yucca_probe_for_dimms(void)
-{
- int dimm_installed[MAXDIMMS];
- int dimm_num, result;
- int dimms_found = 0;
- uchar dimm_addr = IIC0_DIMM0_ADDR;
- uchar dimm_spd_data[MAX_SPD_BYTES];
-
- for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
- /* check if there is a chip at the dimm address */
- switch (dimm_num) {
- case 0:
- dimm_addr = IIC0_DIMM0_ADDR;
- break;
- case 1:
- dimm_addr = IIC0_DIMM1_ADDR;
- break;
- }
-
- result = i2c_probe(dimm_addr);
-
- memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
- if (result == 0) {
- /* read first byte of SPD data, if there is any data */
- result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
-
- if (result == 0) {
- result = dimm_spd_data[0];
- result = result > MAX_SPD_BYTES ?
- MAX_SPD_BYTES : result;
- result = i2c_read(dimm_addr, 0, 1,
- dimm_spd_data, result);
- }
- }
-
- if ((result == 0) &&
- (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
- dimm_installed[dimm_num] = TRUE;
- dimms_found++;
- debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
- } else {
- dimm_installed[dimm_num] = FALSE;
- debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
- }
- }
-
- if (dimms_found == 0) {
- printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- hang();
- }
-
- if (dimm_installed[0] != TRUE) {
- printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
- printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
- hang();
- }
-
- return dimms_found;
-}
-
-/*************************************************************************
- * init SDRAM controller with fixed value
- * the initialization values are for 2x MICRON DDR2
- * PN: MT18HTF6472DY-53EB2
- * 512MB, DDR2, 533, CL4, ECC, REG
- ************************************************************************/
-static long int fixed_sdram(void)
-{
- long int yucca_dimms = 0;
-
- yucca_dimms = yucca_probe_for_dimms();
-
- /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */
- mtdcr( 0x10, 0x00000021 );
- mtdcr( 0x11, 0x84000000 );
-
- /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */
- mtdcr( 0x10, 0x00000020 );
- mtdcr( 0x11, 0x2D122000 );
-
- /* SET MCIF0_CODT Die Termination On */
- mtdcr( 0x10, 0x00000026 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x2A800021 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x02800021 );
-
- /* On-Die Termination for Bank 0 */
- mtdcr( 0x10, 0x00000022 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x18000000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x06000000 );
-
- /* On-Die Termination for Bank 1 */
- mtdcr( 0x10, 0x00000023 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x18000000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x01800000 );
-
- /* On-Die Termination for Bank 2 */
- mtdcr( 0x10, 0x00000024 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x01800000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* On-Die Termination for Bank 3 */
- mtdcr( 0x10, 0x00000025 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x01800000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtdcr( 0x10, 0x00000030 );
- mtdcr( 0x11, 0x08200000 );
-
- /* SET MCIF0_MMODE CL 4 */
- mtdcr( 0x10, 0x00000088 );
- mtdcr( 0x11, 0x00000642 );
-
- /* MCIF0_MEMODE */
- mtdcr( 0x10, 0x00000089 );
- mtdcr( 0x11, 0x00000004 );
-
- /*SET MCIF0_MB0CF */
- mtdcr( 0x10, 0x00000040 );
- mtdcr( 0x11, 0x00000201 );
-
- /* SET MCIF0_MB1CF */
- mtdcr( 0x10, 0x00000044 );
- mtdcr( 0x11, 0x00000201 );
-
- /* SET MCIF0_MB2CF */
- mtdcr( 0x10, 0x00000048 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x00000201 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* SET MCIF0_MB3CF */
- mtdcr( 0x10, 0x0000004c );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x00000201 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* SET MCIF0_INITPLR0 # NOP */
- mtdcr( 0x10, 0x00000050 );
- mtdcr( 0x11, 0xB5380000 );
-
- /* SET MCIF0_INITPLR1 # PRE */
- mtdcr( 0x10, 0x00000051 );
- mtdcr( 0x11, 0x82100400 );
-
- /* SET MCIF0_INITPLR2 # EMR2 */
- mtdcr( 0x10, 0x00000052 );
- mtdcr( 0x11, 0x80820000 );
-
- /* SET MCIF0_INITPLR3 # EMR3 */
- mtdcr( 0x10, 0x00000053 );
- mtdcr( 0x11, 0x80830000 );
-
- /* SET MCIF0_INITPLR4 # EMR DLL ENABLE */
- mtdcr( 0x10, 0x00000054 );
- mtdcr( 0x11, 0x80810000 );
-
- /* SET MCIF0_INITPLR5 # MR DLL RESET */
- mtdcr( 0x10, 0x00000055 );
- mtdcr( 0x11, 0x80800542 );
-
- /* SET MCIF0_INITPLR6 # PRE */
- mtdcr( 0x10, 0x00000056 );
- mtdcr( 0x11, 0x82100400 );
-
- /* SET MCIF0_INITPLR7 # Refresh */
- mtdcr( 0x10, 0x00000057 );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR8 # Refresh */
- mtdcr( 0x10, 0x00000058 );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR9 # Refresh */
- mtdcr( 0x10, 0x00000059 );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR10 # Refresh */
- mtdcr( 0x10, 0x0000005A );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR11 # MR */
- mtdcr( 0x10, 0x0000005B );
- mtdcr( 0x11, 0x80800442 );
-
- /* SET MCIF0_INITPLR12 # EMR OCD Default*/
- mtdcr( 0x10, 0x0000005C );
- mtdcr( 0x11, 0x80810380 );
-
- /* SET MCIF0_INITPLR13 # EMR OCD Exit */
- mtdcr( 0x10, 0x0000005D );
- mtdcr( 0x11, 0x80810000 );
-
- /* 0x80: Adv Addr clock by 180 deg */
- mtdcr( 0x10, 0x00000080 );
- mtdcr( 0x11, 0x80000000 );
-
- /* 0x21: Exit self refresh, set DC_EN */
- mtdcr( 0x10, 0x00000021 );
- mtdcr( 0x11, 0x28000000 );
-
- /* 0x81: Write DQS Adv 90 + Fractional DQS Delay */
- mtdcr( 0x10, 0x00000081 );
- mtdcr( 0x11, 0x80000800 );
-
- /* MCIF0_SDTR1 */
- mtdcr( 0x10, 0x00000085 );
- mtdcr( 0x11, 0x80201000 );
-
- /* MCIF0_SDTR2 */
- mtdcr( 0x10, 0x00000086 );
- mtdcr( 0x11, 0x42103242 );
-
- /* MCIF0_SDTR3 */
- mtdcr( 0x10, 0x00000087 );
- mtdcr( 0x11, 0x0C100D14 );
-
- /* SET MQ0_B0BAS base addr 00000000 / 256MB */
- mtdcr( 0x40, 0x0000F800 );
-
- /* SET MQ0_B1BAS base addr 10000000 / 256MB */
- mtdcr( 0x41, 0x0400F800 );
-
- /* SET MQ0_B2BAS base addr 20000000 / 256MB */
- if (yucca_dimms == 2)
- mtdcr( 0x42, 0x0800F800 );
- else if (yucca_dimms == 1)
- mtdcr( 0x42, 0x00000000 );
-
- /* SET MQ0_B3BAS base addr 30000000 / 256MB */
- if (yucca_dimms == 2)
- mtdcr( 0x43, 0x0C00F800 );
- else if (yucca_dimms == 1)
- mtdcr( 0x43, 0x00000000 );
-
- /* SDRAM_RQDC */
- mtdcr( 0x10, 0x00000070 );
- mtdcr( 0x11, 0x8000003F );
-
- /* SDRAM_RDCC */
- mtdcr( 0x10, 0x00000078 );
- mtdcr( 0x11, 0x80000000 );
-
- /* SDRAM_RFDC */
- mtdcr( 0x10, 0x00000074 );
- mtdcr( 0x11, 0x00000220 );
-
- return (yucca_dimms * 512) << 20;
-}
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
-
- dram_size = fixed_sdram();
-
- return dram_size;
-}
-
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
@@ -1267,42 +994,3 @@ int onboard_pci_arbiter_selected(int core_pci)
#endif
return (BOARD_OPTION_NOT_SELECTED);
}
-
-/*---------------------------------------------------------------------------+
- | ppcMfcpr.
- +---------------------------------------------------------------------------*/
-unsigned long ppcMfcpr(unsigned long cpr_reg)
-{
- unsigned long msr;
- unsigned long cpr_cfgaddr_temp;
- unsigned long cpr_value;
-
- msr = (mfmsr () & ~(MSR_EE));
- cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR);
- mtdcr(CPR0_CFGADDR, cpr_reg);
- cpr_value = mfdcr(CPR0_CFGDATA);
- mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
- mtmsr(msr);
-
- return (cpr_value);
-}
-
-/*----------------------------------------------------------------------------+
-| Indirect Access of the System DCR's (SDR)
-| ppcMfsdr
-+----------------------------------------------------------------------------*/
-unsigned long ppcMfsdr(unsigned long sdr_reg)
-{
- unsigned long msr;
- unsigned long sdr_cfgaddr_temp;
- unsigned long sdr_value;
-
- msr = (mfmsr () & ~(MSR_EE));
- sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR);
- mtdcr(SDR0_CFGADDR, sdr_reg);
- sdr_value = mfdcr(SDR0_CFGDATA);
- mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
- mtmsr(msr);
-
- return (sdr_value);
-}
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-18 19:39:14 +0000