diff options
Diffstat (limited to 'board/bf537-stamp')
| -rw-r--r-- | board/bf537-stamp/bf537-stamp.c | 14 | ||||
| -rw-r--r-- | board/bf537-stamp/nand.c | 8 | ||||
| -rw-r--r-- | board/bf537-stamp/post-memory.c | 8 | ||||
| -rw-r--r-- | board/bf537-stamp/spi_flash.c | 2 | ||||
| -rw-r--r-- | board/bf537-stamp/u-boot.lds.S | 4 |
5 files changed, 18 insertions, 18 deletions
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 4567213111b..7303f1b4155 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -109,12 +109,12 @@ phys_size_t initdram(int board_type) printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); - printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); + printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); + printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); #endif - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; - return CFG_MAX_RAM_SIZE; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return CONFIG_SYS_MAX_RAM_SIZE; } #if defined(CONFIG_MISC_INIT_R) @@ -236,11 +236,11 @@ int flash_post_test(int flags) erase_block_flash(n); printf("OK\r"); printf("--------Program block:%2d...", n); - write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf); + write_data(CONFIG_SYS_FLASH_BASE + offset, BLOCK_SIZE, pbuf); printf("OK\r"); printf("--------Verify block:%2d...", n); for (i = 0; i < BLOCK_SIZE; i += 2) { - if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) != + if (*(unsigned short *)(CONFIG_SYS_FLASH_BASE + offset + i) != *temp++) { value = 1; result = 1; diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index 9800083c9e9..c597f2db1e3 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -44,13 +44,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) if (ctrl & NAND_CTRL_CHANGE) { if( ctrl & NAND_CLE ) - IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE; else - IO_ADDR_W = CFG_NAND_BASE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE; if( ctrl & NAND_ALE ) - IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE; else - IO_ADDR_W = CFG_NAND_BASE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE; this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; } this->IO_ADDR_R = this->IO_ADDR_W; diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index fa119919b39..7c36c8155e0 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -6,7 +6,7 @@ #include <post.h> #include <watchdog.h> -#if CONFIG_POST & CFG_POST_MEMORY +#if CONFIG_POST & CONFIG_SYS_POST_MEMORY #define CLKIN 25000000 #define PATTERN1 0x5A5A5A5A #define PATTERN2 0xAAAAAAAA @@ -71,10 +71,10 @@ int memory_post_test(int flags) post_init_uart(sclk); post_out_buff("\n\r\0"); post_out_buff(log[m][n]); - for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) + for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) *(unsigned long *)addr = PATTERN1; post_out_buff("Reading...\0"); - for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) { + for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) { if ((*(unsigned long *)addr) != PATTERN1) { post_out_buff("Error\n\r\0"); ret = 0; @@ -318,5 +318,5 @@ int post_init_sdram(int sclk) return mem_SDRRC; } -#endif /* CONFIG_POST & CFG_POST_MEMORY */ +#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */ #endif /* CONFIG_POST */ diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c index 7c73ddd7208..11a2803e6f2 100644 --- a/board/bf537-stamp/spi_flash.c +++ b/board/bf537-stamp/spi_flash.c @@ -412,7 +412,7 @@ void spi_init_f(void) */ void spi_init_r(void) { -#if defined(CONFIG_POST) && (CONFIG_POST & CFG_POST_SPI) +#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI) /* Our testing strategy here is pretty basic: * - fill src memory with an 8-bit pattern * - write the src memory to the SPI flash diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 4e7fd7c0419..97ebd792601 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -36,7 +36,7 @@ * for different CPU's which may lack non-cache L1 data. */ #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE # define L1_DATA_B_SRAM_SIZE 0 #endif @@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin) /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ MEMORY { - ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } |