diff options
Diffstat (limited to 'board/davinci')
-rw-r--r-- | board/davinci/da8xxevm/da850evm.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index fbf9c2af34e..0a63cc2a199 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -65,6 +65,8 @@ const struct pinmux_config spi1_pins[] = { #ifdef CONFIG_DAVINCI_MMC /* SPI0 pin muxer settings */ const struct pinmux_config mmc0_pins[] = { + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux[0], 8, 4 }, /* GP0[11] */ { pinmux[10], 2, 0 }, /* MMCSD0_CLK */ { pinmux[10], 2, 1 }, /* MMCSD0_CMD */ { pinmux[10], 2, 2 }, /* MMCSD0_DAT_0 */ @@ -140,6 +142,8 @@ const struct pinmux_config aemif_pins[] = { }; #elif defined(CONFIG_SYS_USE_NOR) const struct pinmux_config nor_pins[] = { + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux[0], 8, 4 }, /* GP0[11] */ { pinmux[5], 1, 6 }, { pinmux[6], 1, 6 }, { pinmux[7], 1, 0 }, @@ -190,6 +194,7 @@ const struct pinmux_config nor_pins[] = { int board_init(void) { + unsigned int temp; #ifndef CONFIG_USE_IRQ /* * Mask all IRQs by clearing the global enable and setting @@ -241,6 +246,16 @@ int board_init(void) #ifdef CONFIG_DAVINCI_MMC if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0) return 1; + + /* Set the GPIO direction as output */ + temp = REG(GPIO_BANK0_REG_DIR_ADDR); + temp &= ~(0x01 << 11); + REG(GPIO_BANK0_REG_DIR_ADDR) = temp; + + /* Set the output as high */ + temp = REG(GPIO_BANK0_REG_SET_ADDR); + temp |= (0x01 << 11); + REG(GPIO_BANK0_REG_SET_ADDR) = temp; #endif if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0) @@ -267,6 +282,16 @@ int board_init(void) #elif defined(CONFIG_SYS_USE_NOR) if (davinci_configure_pin_mux(nor_pins, ARRAY_SIZE(nor_pins)) != 0) return 1; + + /* Set the GPIO direction as output */ + temp = REG(GPIO_BANK0_REG_DIR_ADDR); + temp &= ~(0x01 << 11); + REG(GPIO_BANK0_REG_DIR_ADDR) = temp; + + /* Set the output as low */ + temp = REG(GPIO_BANK0_REG_SET_ADDR); + temp |= (0x01 << 11); + REG(GPIO_BANK0_REG_CLR_ADDR) = temp; #endif /* enable the console UART */ |