diff options
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/common/Makefile | 8 | ||||
| -rw-r--r-- | board/freescale/common/pixis.c | 470 | ||||
| -rw-r--r-- | board/freescale/common/pixis.h | 54 | ||||
| -rw-r--r-- | board/freescale/common/pq-mds-pib.c | 60 | ||||
| -rw-r--r-- | board/freescale/common/pq-mds-pib.h | 9 | ||||
| -rw-r--r-- | board/freescale/common/vsc3316_3308.c | 530 | ||||
| -rw-r--r-- | board/freescale/common/zm7300.c | 232 | ||||
| -rw-r--r-- | board/freescale/common/zm7300.h | 21 | ||||
| -rw-r--r-- | board/freescale/imx8mm_evk/spl.c | 3 | ||||
| -rw-r--r-- | board/freescale/imx8mn_evk/spl.c | 3 | ||||
| -rw-r--r-- | board/freescale/imx8mp_evk/imx8mp_evk.c | 4 | ||||
| -rw-r--r-- | board/freescale/imx8mp_evk/spl.c | 3 | ||||
| -rw-r--r-- | board/freescale/imx8qm_mek/README | 2 | ||||
| -rw-r--r-- | board/freescale/imx93_evk/imx93_evk.c | 4 | ||||
| -rw-r--r-- | board/freescale/imx93_evk/spl.c | 3 | ||||
| -rw-r--r-- | board/freescale/ls1021atsn/README.rst | 2 | ||||
| -rw-r--r-- | board/freescale/lx2160a/lx2160a.c | 6 | ||||
| -rw-r--r-- | board/freescale/mx6sllevk/mx6sllevk.c | 18 | ||||
| -rw-r--r-- | board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 16 | ||||
| -rw-r--r-- | board/freescale/mx6ullevk/mx6ullevk.c | 16 | ||||
| -rw-r--r-- | board/freescale/mx7ulp_evk/Makefile | 4 |
21 files changed, 10 insertions, 1458 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index cc1371867d8..b4faf6f9e0a 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,7 +29,6 @@ endif obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o -obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o endif @@ -37,7 +36,6 @@ obj-$(I2C_COMMON) += i2c_common.o obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o obj-$(CONFIG_$(SPL_)VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o -obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif @@ -53,14 +51,9 @@ endif obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o -obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o -obj-$(CONFIG_P2020DS) += ics307_clk.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o -obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o -obj-$(CONFIG_ZM7300) += zm7300.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif @@ -78,7 +71,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ -obj-$(CONFIG_TARGET_P5020DS) += p_corenet/ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c deleted file mode 100644 index 7096b107e54..00000000000 --- a/board/freescale/common/pixis.c +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006,2010 Freescale Semiconductor - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> - -#define pixis_base (u8 *)PIXIS_BASE - -/* - * Simple board reset. - */ -void pixis_reset(void) -{ - out_8(pixis_base + PIXIS_RST, 0); - - while (1); -} - -/* - * Per table 27, page 58 of MPC8641HPCN spec. - */ -static int set_px_sysclk(unsigned long sysclk) -{ - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; - - switch (sysclk) { - case 33: - sysclk_s = 0x04; - sysclk_r = 0x04; - sysclk_v = 0x07; - sysclk_aux = 0x00; - break; - case 40: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x20; - sysclk_aux = 0x01; - break; - case 50: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x2A; - sysclk_aux = 0x02; - break; - case 66: - sysclk_s = 0x01; - sysclk_r = 0x04; - sysclk_v = 0x04; - sysclk_aux = 0x03; - break; - case 83: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x04; - break; - case 100: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x5C; - sysclk_aux = 0x05; - break; - case 134: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x3B; - sysclk_aux = 0x06; - break; - case 166: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x07; - break; - default: - printf("Unsupported SYSCLK frequency.\n"); - return 0; - } - - vclkh = (sysclk_s << 5) | sysclk_r; - vclkl = sysclk_v; - - out_8(pixis_base + PIXIS_VCLKH, vclkh); - out_8(pixis_base + PIXIS_VCLKL, vclkl); - - out_8(pixis_base + PIXIS_AUX, sysclk_aux); - - return 1; -} - -/* Set the CFG_SYSPLL bits - * - * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if - * read_from_px_regs() is called. - */ -static int set_px_mpxpll(unsigned long mpxpll) -{ - switch (mpxpll) { - case 2: - case 4: - case 6: - case 8: - case 10: - case 12: - case 14: - case 16: - clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); - return 1; - } - - printf("Unsupported MPXPLL ratio.\n"); - return 0; -} - -static int set_px_corepll(unsigned long corepll) -{ - u8 val; - - switch (corepll) { - case 20: - val = 0x08; - break; - case 25: - val = 0x0C; - break; - case 30: - val = 0x10; - break; - case 35: - val = 0x1C; - break; - case 40: - val = 0x14; - break; - case 45: - val = 0x0E; - break; - default: - printf("Unsupported COREPLL ratio.\n"); - return 0; - } - - clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); - return 1; -} - -#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE -#define CFG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C -#endif - -/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values - * - * The PIXIS can be programmed to look at either the on-board dip switches - * or various other PIXIS registers to determine the values for COREPLL, - * MPXPLL, and SYSCLK. - * - * CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0 - * register that tells the pixis to use the various PIXIS register. - */ -static void read_from_px_regs(int set) -{ - u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); - - if (set) - tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE; - else - tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE; - - out_8(pixis_base + PIXIS_VCFGEN0, tmp); -} - -/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1 - * register that tells the pixis to use the PX_VBOOT[LBMAP] register. - */ -#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE -#define CFG_SYS_PIXIS_VBOOT_ENABLE 0x04 -#endif - -/* Configure the source of the boot location - * - * The PIXIS can be programmed to look at either the on-board dip switches - * or the PX_VBOOT[LBMAP] register to determine where we should boot. - * - * If we want to boot from the alternate boot bank, we need to tell the PIXIS - * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead. - */ -static void read_from_px_regs_altbank(int set) -{ - u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); - - if (set) - tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE; - else - tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE; - - out_8(pixis_base + PIXIS_VCFGEN1, tmp); -} - -/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that - * tells the PIXIS what the alternate flash bank is. - * - * Note that it's not really a mask. It contains the actual LBMAP bits that - * must be set to select the alternate bank. This code assumes that the - * primary bank has these bits set to 0, and the alternate bank has these - * bits set to 1. - */ -#ifndef CFG_SYS_PIXIS_VBOOT_MASK -#define CFG_SYS_PIXIS_VBOOT_MASK (0x40) -#endif - -/* Tell the PIXIS to boot from the default flash bank - * - * Program the default flash bank into the VBOOT register. This register is - * used only if PX_VCFGEN1[FLASH]=1. - */ -static void clear_altbank(void) -{ - clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK); -} - -/* Tell the PIXIS to boot from the alternate flash bank - * - * Program the alternate flash bank into the VBOOT register. This register is - * used only if PX_VCFGEN1[FLASH]=1. - */ -static void set_altbank(void) -{ - setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK); -} - -/* Reset the board with watchdog disabled. - * - * This respects the altbank setting. - */ -static void set_px_go(void) -{ - /* Disable the VELA sequencer and watchdog */ - clrbits_8(pixis_base + PIXIS_VCTL, 9); - - /* Reboot by starting the VELA sequencer */ - setbits_8(pixis_base + PIXIS_VCTL, 0x1); - - while (1); -} - -/* Reset the board with watchdog enabled. - * - * This respects the altbank setting. - */ -static void set_px_go_with_watchdog(void) -{ - /* Disable the VELA sequencer */ - clrbits_8(pixis_base + PIXIS_VCTL, 1); - - /* Enable the watchdog and reboot by starting the VELA sequencer */ - setbits_8(pixis_base + PIXIS_VCTL, 0x9); - - while (1); -} - -/* Disable the watchdog - * - */ -static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* Disable the VELA sequencer and the watchdog */ - clrbits_8(pixis_base + PIXIS_VCTL, 9); - - return 0; -} - -U_BOOT_CMD( - diswd, 1, 0, pixis_disable_watchdog_cmd, - "Disable watchdog timer", - "" -); - -/* - * This function takes the non-integral cpu:mpx pll ratio - * and converts it to an integer that can be used to assign - * FPGA register values. - * input: strptr i.e. argv[2] - */ -static unsigned long strfractoint(char *strptr) -{ - int i, j; - int mulconst; - int no_dec = 0; - unsigned long intval = 0, decval = 0; - char intarr[3], decarr[3]; - - /* Assign the integer part to intarr[] - * If there is no decimal point i.e. - * if the ratio is an integral value - * simply create the intarr. - */ - i = 0; - while (strptr[i] != '.') { - if (strptr[i] == 0) { - no_dec = 1; - break; - } - intarr[i] = strptr[i]; - i++; - } - - intarr[i] = '\0'; - - if (no_dec) { - /* Currently needed only for single digit corepll ratios */ - mulconst = 10; - decval = 0; - } else { - j = 0; - i++; /* Skipping the decimal point */ - while ((strptr[i] >= '0') && (strptr[i] <= '9')) { - decarr[j] = strptr[i]; - i++; - j++; - } - - decarr[j] = '\0'; - - mulconst = 1; - for (i = 0; i < j; i++) - mulconst *= 10; - decval = dectoul(decarr, NULL); - } - - intval = dectoul(intarr, NULL); - intval = intval * mulconst; - - return intval + decval; -} - -static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned int i; - char *p_cf = NULL; - char *p_cf_sysclk = NULL; - char *p_cf_corepll = NULL; - char *p_cf_mpxpll = NULL; - char *p_altbank = NULL; - char *p_wd = NULL; - int unknown_param = 0; - - /* - * No args is a simple reset request. - */ - if (argc <= 1) { - pixis_reset(); - /* not reached */ - } - - for (i = 1; i < argc; i++) { - if (strcmp(argv[i], "cf") == 0) { - p_cf = argv[i]; - if (i + 3 >= argc) { - break; - } - p_cf_sysclk = argv[i+1]; - p_cf_corepll = argv[i+2]; - p_cf_mpxpll = argv[i+3]; - i += 3; - continue; - } - - if (strcmp(argv[i], "altbank") == 0) { - p_altbank = argv[i]; - continue; - } - - if (strcmp(argv[i], "wd") == 0) { - p_wd = argv[i]; - continue; - } - - unknown_param = 1; - } - - /* - * Check that cf has all required parms - */ - if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll)) - || unknown_param) { -#ifdef CONFIG_SYS_LONGHELP - puts(cmdtp->help); - putc('\n'); -#endif - return 1; - } - - /* - * PIXIS seems to be sensitive to the ordering of - * the registers that are touched. - */ - read_from_px_regs(0); - - if (p_altbank) - read_from_px_regs_altbank(0); - - clear_altbank(); - - /* - * Clock configuration specified. - */ - if (p_cf) { - unsigned long sysclk; - unsigned long corepll; - unsigned long mpxpll; - - sysclk = dectoul(p_cf_sysclk, NULL); - corepll = strfractoint(p_cf_corepll); - mpxpll = dectoul(p_cf_mpxpll, NULL); - - if (!(set_px_sysclk(sysclk) - && set_px_corepll(corepll) - && set_px_mpxpll(mpxpll))) { -#ifdef CONFIG_SYS_LONGHELP - puts(cmdtp->help); - putc('\n'); -#endif - return 1; - } - read_from_px_regs(1); - } - - /* - * Altbank specified - * - * NOTE CHANGE IN BEHAVIOR: previous code would default - * to enabling watchdog if altbank is specified. - * Now the watchdog must be enabled explicitly using 'wd'. - */ - if (p_altbank) { - set_altbank(); - read_from_px_regs_altbank(1); - } - - /* - * Reset with watchdog specified. - */ - if (p_wd) - set_px_go_with_watchdog(); - else - set_px_go(); - - /* - * Shouldn't be reached. - */ - return 0; -} - - -U_BOOT_CMD( - pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, - "Reset the board using the FPGA sequencer", - " pixis_reset\n" - " pixis_reset [altbank]\n" - " pixis_reset altbank wd\n" - " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" - " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>" -); diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h deleted file mode 100644 index f19e85cb1c9..00000000000 --- a/board/freescale/common/pixis.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - */ -#ifndef __PIXIS_H_ -#define __PIXIS_H_ 1 - -/* PIXIS register set. */ -#if defined(CONFIG_TARGET_MPC8536DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 rst2; - u8 aux1; - u8 spd; - u8 aux2; - u8 csr2; - u8 watch; - u8 led; - u8 pwr; - u8 res[3]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[3]; - u8 sclk[3]; - u8 dclk[3]; - u8 i2cdacr; - u8 vcoreacc[4]; - u8 vcorecnt[3]; - u8 vcoremax[2]; - u8 vplatacc[4]; - u8 vplatcnt[3]; - u8 vplatmax[2]; - u8 vtempacc[4]; - u8 vtempcnt[3]; - u8 vtempmax[2]; - u8 res2[4]; -} __attribute__ ((packed)) pixis_t; -#else -#error Need to define pixis_t for this board -#endif - -/* Pointer to the PIXIS register set */ -#define pixis ((pixis_t *)PIXIS_BASE) - -#endif /* __PIXIS_H_ */ diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c deleted file mode 100644 index 162c8a954f0..00000000000 --- a/board/freescale/common/pq-mds-pib.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Tony Li <tony.li@freescale.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation; - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> - -#include "pq-mds-pib.h" - -int pib_init(void) -{ - u8 val8; - u8 orig_i2c_bus; - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; -#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) - /* Assign PIB PMC slot to desired PCI bus */ - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - - eieio(); - - printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); -#endif - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - return 0; -} diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h deleted file mode 100644 index 67066fd118d..00000000000 --- a/board/freescale/common/pq-mds-pib.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation; - */ - -extern int pib_init(void); diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c deleted file mode 100644 index c51f3c5aca2..00000000000 --- a/board/freescale/common/vsc3316_3308.c +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include "vsc3316_3308.h" -#include <log.h> - -#define REVISION_ID_REG 0x7E -#define INTERFACE_MODE_REG 0x79 -#define CURRENT_PAGE_REGISTER 0x7F -#define CONNECTION_CONFIG_PAGE 0x00 -#define INPUT_STATE_REG 0x13 -#define GLOBAL_INPUT_ISE1 0x51 -#define GLOBAL_INPUT_ISE2 0x52 -#define GLOBAL_INPUT_GAIN 0x53 -#define GLOBAL_INPUT_LOS 0x55 -#define GLOBAL_OUTPUT_PE1 0x56 -#define GLOBAL_OUTPUT_PE2 0x57 -#define GLOBAL_OUTPUT_LEVEL 0x58 -#define GLOBAL_OUTPUT_TERMINATION 0x5A -#define GLOBAL_CORE_CNTRL 0x5D -#define OUTPUT_MODE_PAGE 0x23 -#define CORE_CONTROL_PAGE 0x25 -#define CORE_CONFIG_REG 0x75 - -int vsc_if_enable(unsigned int vsc_addr) -{ - u8 data; - - debug("VSC:Configuring VSC at I2C address 0x%2x" - " for 2-wire interface\n", vsc_addr); - - /* enable 2-wire Serial InterFace (I2C) */ - data = 0x02; -#if CONFIG_IS_ENABLED(DM_I2C) - int ret, bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1); -#else - return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); -#endif -} - -int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3316 at I2C address 0x%2x" - " for Tx\n", vsc_addr); - -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Configuring the required input of the switch */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 0x80); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); - -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Configuring the required input of the switch */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 0x80); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - - vsc_wp_config(vsc_addr); - - return 0; -} - -#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR -int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", - vsc_addr); - -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Configure Global Input ISE */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0); - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0); - - /* Configure Tx/Rx Global Output PE1 */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0); - - /* Configure Tx/Rx Global Output PE2 */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0); - - /* Configure Tx/Rx Global Input GAIN */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0); - - /* Setting Global output termination */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0); - - /* Configure Tx/Rx Global Output level */ - if (vsc_addr == VSC3308_TX_ADDRESS) - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4); - else - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning off all the required input of the switch */ - for (i = 0; i < num_con; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - dm_i2c_reg_write(dev, 2, 0); - dm_i2c_reg_write(dev, 3, 0); - } else { - dm_i2c_reg_write(dev, 0, 0); - dm_i2c_reg_write(dev, 1, 0); - } - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn off the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - dm_i2c_reg_write(dev, 0, 0); - dm_i2c_reg_write(dev, 1, 0); - } else { - dm_i2c_reg_write(dev, 3, 0); - dm_i2c_reg_write(dev, 4, 0); - } - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Configure Global Input ISE */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0); - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0); - - /* Configure Tx/Rx Global Output PE1 */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0); - - /* Configure Tx/Rx Global Output PE2 */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0); - - /* Configure Tx/Rx Global Input GAIN */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0); - - /* Setting Global output termination */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0); - - /* Configure Tx/Rx Global Output level */ - if (vsc_addr == VSC3308_TX_ADDRESS) - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4); - else - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning off all the required input of the switch */ - for (i = 0; i < num_con; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - i2c_reg_write(vsc_addr, 2, 0); - i2c_reg_write(vsc_addr, 3, 0); - } else { - i2c_reg_write(vsc_addr, 0, 0); - i2c_reg_write(vsc_addr, 1, 0); - } - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn off the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - i2c_reg_write(vsc_addr, 0, 0); - i2c_reg_write(vsc_addr, 1, 0); - } else { - i2c_reg_write(vsc_addr, 3, 0); - i2c_reg_write(vsc_addr, 4, 0); - } - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - vsc_wp_config(vsc_addr); - - return 0; -} -#endif - -int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3308 at I2C address 0x%x" - " for Tx\n", vsc_addr); -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /*Configure Global Input ISE and gain */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12); - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning ON the required input of the switch */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 0); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /*Configure Global Input ISE and gain */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12); - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning ON the required input of the switch */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 0); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - vsc_wp_config(vsc_addr); - - return 0; -} - -void vsc_wp_config(unsigned int vsc_addr) -{ - debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr); - - /* For new crosspoint configuration to occur, WP bit of - * CORE_CONFIG_REG should be set 1 and then reset to 0 */ -#if CONFIG_IS_ENABLED(DM_I2C) - int ret, bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - - dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01); - dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0); -#else - i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); - i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); -#endif -} diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c deleted file mode 100644 index e8c2fc85c84..00000000000 --- a/board/freescale/common/zm7300.c +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* Power-One ZM7300 DPM */ -#include "zm7300.h" -#include <log.h> - -#define DPM_WP 0x96 -#define WRP_OPCODE 0x01 -#define WRM_OPCODE 0x02 -#define RRP_OPCODE 0x11 - -#define DPM_SUCCESS 0x01 -#define DPM_EXEC_FAIL 0x00 - -static const uint16_t hex_to_1_10mv[] = { - 5000, - 5125, - 5250, - 5375, - 5500, - 5625, - 5750, - 5875, - 6000, - 6125, - 6250, - 6375, - 6500, - 6625, - 6750, - 6875, - 7000, - 7125, - 7250, - 7375, - 7500, - 7625, - 7750, - 7875, - 8000, - 8125, - 8250, - 8375, - 8500, - 8625, - 8750, - 8875, - 9000, - 9125, - 9250, - 9375, - 9500, /* 0.95mV */ - 9625, - 9750, - 9875, - 10000, /* 1.0V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 11125, - 11250, - 11375, - 11500, - 11625, - 11750, - 11875, - 12000, - 12125, - 12250, - 12375, - 0, /* reserved */ -}; - - -/* Read Data d from Register r of POL p */ -u8 dpm_rrp(uchar r) -{ - u8 ret[5]; - - ret[0] = RRP_OPCODE; - /* POL is 0 */ - ret[1] = 0; - ret[2] = r; - i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2); - if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */ - debug("RRP_OPCODE returned success data is %x\n", ret[0]); - return ret[0]; - } else { - return -1; - } -} - -/* Write Data d into DPM register r (RAM) */ -int dpm_wrm(u8 r, u8 d) -{ - u8 ret[5]; - - ret[0] = WRM_OPCODE; - ret[1] = r; - ret[2] = d; - i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1); - if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ - debug("WRM_OPCODE returned success data is %x\n", ret[0]); - return ret[0]; - } else { - return -1; - } -} - -/* Write Data d into Register r of POL(s) a */ -int dpm_wrp(u8 r, u8 d) -{ - u8 ret[7]; - - ret[0] = WRP_OPCODE; - /* only POL0 is present */ - ret[1] = 0x01; - ret[2] = 0x00; - ret[3] = 0x00; - ret[4] = 0x00; - ret[5] = r; - ret[6] = d; - i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1); - if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ - debug("WRP_OPCODE returned success data is %x\n", ret[0]); - return 0; - } else { - return -1; - } -} - -/* Uses the DPM command RRP */ -u8 zm_read(uchar reg) -{ - return dpm_rrp(reg); -} - -/* ZM_write -- - Steps: - a. Write data to the register - b. Read data from register and compare to written value - c. Return return_code & voltage_read -*/ -u8 zm_write(u8 reg, u8 data) -{ - u8 d; - - /* write data to register */ - dpm_wrp(reg, data); - - /* read register and compare to written value */ - d = dpm_rrp(reg); - if (d != data) { - printf("zm_write : Comparison register data failed\n"); - return -1; - } - - return d; -} - -/* zm_write_out_voltage - * voltage in 1/10 mV - */ -int zm_write_voltage(int voltage) -{ - u8 reg = 0x7, vid; - uint16_t voltage_read; - u8 ret; - - vid = (voltage - 5000) / ZM_STEP; - - ret = zm_write(reg, vid); - if (ret != -1) { - voltage_read = hex_to_1_10mv[ret]; - debug("voltage set to %dmV\n", voltage_read/10); - return voltage_read; - } - return -1; -} - -/* zm_read_out_voltage - * voltage in 1/10 mV - */ -int zm_read_voltage(void) -{ - u8 reg = 0x7; - u8 ret; - int voltage; - - ret = zm_read(reg); - if (ret != -1) { - voltage = hex_to_1_10mv[ret]; - debug("Voltage read is %dmV\n", voltage/10); - return voltage; - } else { - return -1; - } -} - -int zm_disable_wp() -{ - u8 new_wp_value; - - /* Disable using Write-Protect register 0x96 */ - new_wp_value = 0x8; - if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) { - printf("Disable Write-Protect register failed\n"); - return -1; - } - return 0; -} - -int zm_enable_wp() -{ - u8 orig_wp_value; - orig_wp_value = 0x0; - - /* Enable using Write-Protect register 0x96 */ - if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) { - printf("Enable Write-Protect register failed\n"); - return -1; - } - return 0; -} diff --git a/board/freescale/common/zm7300.h b/board/freescale/common/zm7300.h deleted file mode 100644 index 9ce24afc178..00000000000 --- a/board/freescale/common/zm7300.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __ZM7300_H_ -#define __ZM7300_H 1_ - -#include <common.h> -#include <i2c.h> -#include <errno.h> -#include <asm/io.h> - -#define ZM_STEP 125 -int zm7300_set_voltage(int voltage_1_10mv); -int zm_write_voltage(int voltage); -int zm_read_voltage(void); -int zm_disable_wp(void); -int zm_enable_wp(void); - -#endif /* __ZM7300_H_ */ diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index b5a2faf3a18..6e9513805cd 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -99,9 +99,6 @@ static int power_init_board(void) /* set VDD_SNVS_0V8 from default 0.85V */ pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - return 0; } diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 380abecd746..ec0378b5b76 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -95,9 +95,6 @@ int power_init_board(void) /* enable LDO4 to 1.2v */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - return 0; } #endif diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 8971a827df3..ce211d486ab 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -55,11 +55,11 @@ int board_init(void) { int ret = 0; - if (CONFIG_IS_ENABLED(FEC_MXC)) { + if (IS_ENABLED(CONFIG_FEC_MXC)) { setup_fec(); } - if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) { + if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) { ret = setup_eqos(); } diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index f1b285417d0..246826a0d48 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -102,9 +102,6 @@ int power_init_board(void) /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); - return 0; } #endif diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index b1a4c6cc822..47fae3d2843 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -12,7 +12,7 @@ Quick Start Get and Build the ARM Trusted firmware ====================================== -$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git clone https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga $ make PLAT=imx8qm bl31 diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index 182ae5fd518..e73a498733b 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -66,10 +66,10 @@ static int setup_eqos(void) int board_init(void) { - if (CONFIG_IS_ENABLED(FEC_MXC)) + if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); - if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) setup_eqos(); return 0; diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 38cfbac6ea6..1aa2977b409 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -74,9 +74,6 @@ int power_init_board(void) /* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); - - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } #endif diff --git a/board/freescale/ls1021atsn/README.rst b/board/freescale/ls1021atsn/README.rst index cdec02f1a35..cd12291d8aa 100644 --- a/board/freescale/ls1021atsn/README.rst +++ b/board/freescale/ls1021atsn/README.rst @@ -50,7 +50,7 @@ To compile and flash an SD card image:: For the QSPI flash, first obtain the Reset Configuration Word binary for bootimg from the QSPI flash from the rcw project -(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw):: +(https://github.com/nxp-qoriq/rcw):: make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/ diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index cf5b1ee46e0..d8a86cdf618 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -676,7 +676,7 @@ void board_quiesce_devices(void) } #endif -#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg) { int err; @@ -798,7 +798,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 mc_memory_size = 0; u16 total_memory_banks; int err; -#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) u8 board_rev; #endif @@ -862,7 +862,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif fdt_fixup_icid(blob); -#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; if (board_rev == 'C') fdt_fixup_i2c_thermal_node(blob); diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index b4fddafe640..10a00095aff 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -35,20 +31,10 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - #ifdef CONFIG_DM_PMIC_PFUZE100 int power_init_board(void) { @@ -58,7 +44,7 @@ int power_init_board(void) u32 switch_num = 6; u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100@08", &dev); + ret = pmic_get("pfuze100@8", &dev); if (ret == -ENODEV) return 0; @@ -94,8 +80,6 @@ int power_init_board(void) int board_early_init_f(void) { - setup_iomux_uart(); - return 0; } diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 9205d5ef6dd..84cc51e9cac 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -33,10 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -59,11 +55,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const fec2_pads[] = { MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -81,11 +72,6 @@ static iomux_v3_cfg_t const fec2_pads[] = { MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), }; -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -216,8 +202,6 @@ int board_ehci_hcd_init(int port) int board_early_init_f(void) { - setup_iomux_uart(); - return 0; } diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index e2473806475..de45f8b1d24 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -35,16 +31,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - int board_mmc_get_env_dev(int devno) { return devno; @@ -57,8 +43,6 @@ int mmc_map_to_kernel_blk(int devno) int board_early_init_f(void) { - setup_iomux_uart(); - return 0; } diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile index 686763d6744..9f33c61f03b 100644 --- a/board/freescale/mx7ulp_evk/Makefile +++ b/board/freescale/mx7ulp_evk/Makefile @@ -2,7 +2,3 @@ # (C) Copyright 2016 Freescale Semiconductor, Inc. obj-y := mx7ulp_evk.o - -extra-$(CONFIG_USE_PLUGIN) := plugin.bin -$(obj)/plugin.bin: $(obj)/plugin.o - $(OBJCOPY) -O binary --gap-fill 0xff $< $@ |