diff options
Diffstat (limited to 'board/freescale')
61 files changed, 1 insertions, 4342 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 114b7ba8f9f..7862a791ac5 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -43,9 +43,7 @@ endif obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o -obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o -obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 596cd0018c5..162c8a954f0 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -36,11 +36,7 @@ int pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_TARGET_MPC832XEMDS) - val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ -#else val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ -#endif i2c_write(0x26, 0x2, 1, &val8, 1); val8 = 0xff; i2c_write(0x26, 0x3, 1, &val8, 1); @@ -55,34 +51,9 @@ int pib_init(void) eieio(); -#if defined(CONFIG_TARGET_MPC832XEMDS) - printf("PCI 32bit bus on PMC2 &PMC3\n"); -#else printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); #endif -#endif - -#if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_TARGET_MPC832XEMDS) - val8 = 0; - i2c_write(0x26, 0x7, 1, &val8, 1); - val8 = 0xf7; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x21, 0x6, 1, &val8, 1); - i2c_write(0x21, 0x7, 1, &val8, 1); - - val8 = 0xdf; - i2c_write(0x21, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x21, 0x3, 1, &val8, 1); - eieio(); - - printf("QOC3 ATM card on PMC1\n"); -#endif -#endif /* Reset to original I2C bus */ i2c_set_bus_num(orig_i2c_bus); return 0; diff --git a/board/freescale/m547xevb/Kconfig b/board/freescale/m547xevb/Kconfig deleted file mode 100644 index 8cfe20ab8dd..00000000000 --- a/board/freescale/m547xevb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5475EVB - -config SYS_CPU - default "mcf547x_8x" - -config SYS_BOARD - default "m547xevb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5475EVB" - -endif diff --git a/board/freescale/m547xevb/MAINTAINERS b/board/freescale/m547xevb/MAINTAINERS deleted file mode 100644 index 0d821eb011f..00000000000 --- a/board/freescale/m547xevb/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -M547XEVB BOARD -M: TsiChung Liew <Tsi-Chung.Liew@nxp.com> -S: Maintained -F: board/freescale/m547xevb/ -F: include/configs/M5475EVB.h -F: configs/M5475AFE_defconfig -F: configs/M5475BFE_defconfig -F: configs/M5475CFE_defconfig -F: configs/M5475DFE_defconfig -F: configs/M5475EFE_defconfig -F: configs/M5475FFE_defconfig -F: configs/M5475GFE_defconfig diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile deleted file mode 100644 index 29fe9dad775..00000000000 --- a/board/freescale/m547xevb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m547xevb.o diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README deleted file mode 100644 index 6b4fbe5c25d..00000000000 --- a/board/freescale/m547xevb/README +++ /dev/null @@ -1,271 +0,0 @@ -Freescale MCF5475EVB ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created Jan 08, 2008 -=========================================== - - -Changed files: -============== - -- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init -- board/freescale/m547xevb/mii.c MII init -- board/freescale/m547xevb/Makefile Makefile -- board/freescale/m547xevb/config.mk config make -- board/freescale/m547xevb/u-boot.lds Linker description - -- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code -- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs -- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support -- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock -- arch/m68k/cpu/mcf547x_8x/Makefile Makefile -- arch/m68k/cpu/mcf547x_8x/config.mk config make -- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code - -- board/freescale/m547xevb/README This readme file - -- drivers/dma/MCD_dmaApi.c DMA API functions -- drivers/dma/MCD_tasks.c DMA Tasks -- drivers/dma/MCD_tasksInit.c DMA Tasks Init -- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver -- drivers/serial/mcfuart.c ColdFire common UART driver - -- include/MCD_dma.h DMA header file -- include/MCD_progCheck.h DMA header file -- include/MCD_tasksInit.h DMA header file -- include/asm-m68k/bitops.h Bit operation function export -- include/asm-m68k/byteorder.h Byte order functions -- include/asm-m68k/errno.h Error Number definition -- include/asm-m68k/fec.h FEC structure and definition -- include/asm-m68k/fsl_i2c.h I2C structure and definition -- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition -- include/asm-m68k/global_data.h Global data structure -- include/asm-m68k/immap.h ColdFire specific header file and driver macros -- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file -- include/asm-m68k/io.h io functions -- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file -- include/asm-m68k/posix_types.h Posix -- include/asm-m68k/processor.h header file -- include/asm-m68k/ptrace.h Exception structure -- include/asm-m68k/rtc.h Realtime clock header file -- include/asm-m68k/string.h String function export -- include/asm-m68k/timer.h Timer structure and definition -- include/asm-m68k/types.h Data types definition -- include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h U-Boot structure - -- include/configs/M5475EVB.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts Coldfire common interrupt functions -- arch/m68k/lib/m68k_linux.c -- arch/m68k/lib/traps.c Exception init code - -1 MCF547x specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in thie coldfire family - -1.2 Configuration settings for M5475EVB Development Board -CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs -CONFIG_M547x -- define for all Freescale MCF547x CPUs -CONFIG_M5475 -- define for M5475EVB board - -CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_FSLDMAFEC -- define to use common dma FEC driver -CONFIG_MII -- enable to use MII driver -CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery -CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer -CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- -CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration -CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration -CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register -CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register -MCFFEC_TOUT_LOOP -- set FEC timeout loop -CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot - -CONFIG_CMD_USB -- enable USB commands -CONFIG_USB_OHCI_NEW -- enable USB OHCI driver -CONFIG_USB_STORAGE -- enable USB Storage device -CONFIG_DOS_PARTITION -- enable DOS read/write - -CONFIG_SLTTMR -- define to use SLT timer - -CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset -CONFIG_SYS_IMMR -- define for MBAR offset - -CONFIG_PCI -- define for PCI support -CONFIG_PCI_PNP -- define for Plug n play support -CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge -CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset -CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset -CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size -CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset -CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset -CONFIG_SYS_PCI_IO_SIZE -- PCI IO size -CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset -CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset -CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size - -CONFIG_SYS_MBAR -- define MBAR offset - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - Flash: 0xFF800000-0xFFFFFFFF (8MB) - DDR: 0x00000000-0x3FFFFFFF (1024MB) - SRAM: 0xF2000000-0xF2000FFF (4KB) - PCI: 0x70000000-0x8FFFFFFF (512MB) - IP: 0xF0000000-0xFFFFFFFF (256MB) - -3. COMPILATION -============== -3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux - version) from codesourcery.com was used. Download it from: - http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -3.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot-1.x.x - make distclean - make M5475AFE_config, or - boot 2MB, RAM 64MB - make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB - make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB - make M5475DFE_config, or - boot 2MB, USB, RAM 64MB - make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB - make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB - make M5475GFE_config, or - boot 2MB, RAM 64MB - make - -5. SCREEN DUMP -============== -5.1 - -U-Boot 1.3.1 (Jan 8 2008 - 12:47:44) - -CPU: Freescale MCF5475 - CPU CLK 266 Mhz BUS CLK 133 Mhz -Board: Freescale FireEngine 5475 EVB -I2C: ready -DRAM: 64 MB -FLASH: 18 MB -In: serial -Out: serial -Err: serial -Net: FEC0, FEC1 --> pri -bootdelay=1 -baudrate=115200 -ethaddr=00:e0:0c:bc:e5:60 -eth1addr=00:e0:0c:bc:e5:61 -ipaddr=192.162.1.2 -serverip=192.162.1.1 -gatewayip=192.162.1.1 -netmask=255.255.255.0 -hostname=M547xEVB -netdev=eth0 -loadaddr=10000 -u-boot=u-boot.bin -load=tftp ${loadaddr) ${u-boot} -upd=run load; run prog -prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save -stdin=serial -stdout=serial -stderr=serial -ethact=FEC0 -mem=65024k - -Environment size: 433/8188 bytes --> bdin -memstart = 0x00000000 -memsize = 0x04000000 -flashstart = 0xFF800000 -flashsize = 0x01200000 -flashoffset = 0x00000000 -sramstart = 0xF2000000 -sramsize = 0x00001000 -mbar = 0xF0000000 -busfreq = 133.333 MHz -pcifreq = 0 MHz -ethaddr = 00:E0:0C:BC:E5:60 -eth1addr = 00:E0:0C:BC:E5:61 -ip_addr = 192.162.1.2 -baudrate = 115200 bps --> ? -? - alias for 'help' -base - print or set address offset -bdinfo - print Board Info structure -boot - boot default, i.e., run 'bootcmd' -bootd - boot default, i.e., run 'bootcmd' -bootelf - Boot from an ELF image in memory -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootvx - Boot vxWorks from an ELF image -cmp - memory compare -coninfo - print console devices and information -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -i2c - I2C sub-system -icache - enable or disable instruction cache -iminfo - print header information for application image -imls - list all images found in flash -itest - return true/false on integer compare -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loady - load binary file over serial line (ymodem mode) -loop - infinite loop on address range -md - memory display -mii - MII utility commands -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nfs - boot image via network using NFS protocol -nm - memory modify (constant address) -pci - list and access PCI Configuration Space -ping - send ICMP ECHO_REQUEST to network host -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -tftpboot- boot image via network using TFTP protocol -usb - USB sub-system -usbboot - boot from USB device -version - print monitor version --> usb start -(Re)start USB... -USB: OHCI pci controller (1131, 1561) found @(0:17:0) -OHCI regs address 0x80000000 -scanning bus for devices... 2 USB Device(s) found - scanning bus for storage devices... 1 Storage Device(s) found --> diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c deleted file mode 100644 index 1568f455e92..00000000000 --- a/board/freescale/m547xevb/m547xevb.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <config.h> -#include <common.h> -#include <init.h> -#include <pci.h> -#include <asm/global_data.h> -#include <asm/immap.h> -#include <asm/io.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale FireEngine 5475 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - siu_t *siu = (siu_t *) (MMAP_SIU); - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - u32 dramsize, i; -#ifdef CONFIG_SYS_DRAMSZ1 - u32 temp; -#endif - - out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); - - dramsize = CONFIG_SYS_DRAMSZ * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); - -#ifdef CONFIG_SYS_DRAMSZ1 - temp = CONFIG_SYS_DRAMSZ1 * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (temp == (1 << i)) - break; - } - i--; - dramsize += temp; - out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); -#endif - - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); - - /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); - - /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - - out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); - - udelay(100); - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI devices, report devices found. - */ -static struct pci_controller hose; -extern void pci_mcf547x_8x_init(struct pci_controller *hose); - -void pci_init_board(void) -{ - pci_mcf547x_8x_init(&hose); -} -#endif /* CONFIG_PCI */ diff --git a/board/freescale/m548xevb/Kconfig b/board/freescale/m548xevb/Kconfig deleted file mode 100644 index da924e3ce98..00000000000 --- a/board/freescale/m548xevb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5485EVB - -config SYS_CPU - default "mcf547x_8x" - -config SYS_BOARD - default "m548xevb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5485EVB" - -endif diff --git a/board/freescale/m548xevb/MAINTAINERS b/board/freescale/m548xevb/MAINTAINERS deleted file mode 100644 index 4e642e69d51..00000000000 --- a/board/freescale/m548xevb/MAINTAINERS +++ /dev/null @@ -1,13 +0,0 @@ -M548XEVB BOARD -M: TsiChung Liew <Tsi-Chung.Liew@nxp.com> -S: Maintained -F: board/freescale/m548xevb/ -F: include/configs/M5485EVB.h -F: configs/M5485AFE_defconfig -F: configs/M5485BFE_defconfig -F: configs/M5485CFE_defconfig -F: configs/M5485DFE_defconfig -F: configs/M5485EFE_defconfig -F: configs/M5485FFE_defconfig -F: configs/M5485GFE_defconfig -F: configs/M5485HFE_defconfig diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile deleted file mode 100644 index 05bfaa33711..00000000000 --- a/board/freescale/m548xevb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m548xevb.o diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c deleted file mode 100644 index b62355a7ae7..00000000000 --- a/board/freescale/m548xevb/m548xevb.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <config.h> -#include <common.h> -#include <init.h> -#include <pci.h> -#include <asm/global_data.h> -#include <asm/immap.h> -#include <asm/io.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale FireEngine 5485 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - siu_t *siu = (siu_t *) (MMAP_SIU); - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - u32 dramsize, i; -#ifdef CONFIG_SYS_DRAMSZ1 - u32 temp; -#endif - - out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); - - dramsize = CONFIG_SYS_DRAMSZ * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); - -#ifdef CONFIG_SYS_DRAMSZ1 - temp = CONFIG_SYS_DRAMSZ1 * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (temp == (1 << i)) - break; - } - i--; - dramsize += temp; - out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); -#endif - - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); - - /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); - - /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - - out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); - - udelay(100); - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI devices, report devices found. - */ -static struct pci_controller hose; -extern void pci_mcf547x_8x_init(struct pci_controller *hose); - -void pci_init_board(void) -{ - pci_mcf547x_8x_init(&hose); -} -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig deleted file mode 100644 index b6332a1368b..00000000000 --- a/board/freescale/mpc8313erdb/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_MPC8313ERDB_NOR - -config SYS_BOARD - default "mpc8313erdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8313ERDB_NOR" - -endif - -if TARGET_MPC8313ERDB_NAND - -config SYS_BOARD - default "mpc8313erdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8313ERDB_NAND" - -endif diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS deleted file mode 100644 index 807fb0b6e9e..00000000000 --- a/board/freescale/mpc8313erdb/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MPC8313ERDB BOARD -#M: - -S: Maintained -F: board/freescale/mpc8313erdb/ -F: include/configs/MPC8313ERDB.h -F: configs/MPC8313ERDB_33_defconfig -F: configs/MPC8313ERDB_66_defconfig -F: configs/MPC8313ERDB_NAND_33_defconfig -F: configs/MPC8313ERDB_NAND_66_defconfig diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile deleted file mode 100644 index af600ccdbb5..00000000000 --- a/board/freescale/mpc8313erdb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := mpc8313erdb.o sdram.o diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README deleted file mode 100644 index 697cee4c42e..00000000000 --- a/board/freescale/mpc8313erdb/README +++ /dev/null @@ -1,111 +0,0 @@ -Freescale MPC8313ERDB Board ------------------------------------------ - -1. Board Switches and Jumpers - - S3 is used to set CONFIG_SYS_RESET_SOURCE. - - To boot the image at 0xFE000000 in NOR flash, use these DIP - switch settings for S3 S4: - - +------+ +------+ - | | | **** | - | **** | | | - +------+ ON +------+ ON - 4321 4321 - (where the '*' indicates the position of the tab of the switch.) - - To boot the image at the beginning of NAND flash, use these - DIP switch settings for S3 S4: - - +------+ +------+ - | * | | *** | - | *** | | * | - +------+ ON +------+ ON - 4321 4321 - (where the '*' indicates the position of the tab of the switch.) - - When booting from NAND, use u-boot-nand.bin, not u-boot.bin. - -2. Memory Map - The memory map looks like this: - - 0x0000_0000 0x07ff_ffff DDR 128M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xe200_0000 0xe20f_ffff PCI IO 16M - 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K - 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K - 0xfa00_0000 0xfa00_7fff Board Status/ 32K - LED Control (CS3) - 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M - - When booting from NAND, NAND flash is CS0 and NOR flash - is CS1. - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC8313ERDB.h - - CONFIG_MPC83xx MPC83xx family - CONFIG_MPC831x MPC831x specific - CONFIG_MPC8313ERDB MPC8313ERDB board specific - -4. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make MPC8313ERDB_XXX_config - (where XXX is: - 33 - 33 MHz oscillator, boot from NOR flash - 66 - 66 MHz oscillator, boot from NOR flash - NAND_33 - 33 MHz oscillator, boot from NAND flash - NAND_66 - 66 MHz oscillator, boot from NAND flash) - make - -5. Downloading and Flashing Images - -5.1 Reflash U-Boot Image using U-Boot - - NOR flash: - - =>run tftpflash - - You may want to try - =>tftpboot $loadaddr $uboot - first, to make sure that the TFTP load will succeed before it - goes ahead and wipes out your current firmware. And of course, - have an alternate means of programming the flash available - if the new U-Boot doesn't boot. - - NAND flash: - - =>tftpboot $loadaddr <filename> - =>nand erase 0 0x80000 - =>nand write $loadaddr 0 0x80000 - - ...where 0x80000 is the filesize rounded up to - the next 0x20000 increment. - -5.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, rootpath (if using NFS root), - fdtfile, and bootfile). - - Then, do one of the following, depending on whether you - want an NFS root or a ramdisk root: - - =>run nfsboot - or - =>run ramboot - -6 Notes - - The console baudrate for MPC8313ERDB is 115200bps. diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c deleted file mode 100644 index 3bf5cff1e10..00000000000 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * - * Author: Scott Wood <scottwood@freescale.com> - */ - -#include <common.h> -#include <clock_legacy.h> -#include <fdt_support.h> -#include <init.h> -#if defined(CONFIG_OF_LIBFDT) -#include <linux/libfdt.h> -#endif -#include <pci.h> -#include <mpc83xx.h> -#include <vsc7385.h> -#include <ns16550.h> -#include <nand.h> -#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD) -#include <asm/gpio.h> -#endif -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - gd->flags |= GD_FLG_SILENT; -#endif -#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD) - mpc83xx_gpio_init_f(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ -#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD) - mpc83xx_gpio_init_r(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: Freescale MPC8313ERDB\n"); - return 0; -} - -#ifndef CONFIG_SPL_BUILD -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI1_MEM_BASE, - .phys_start = CONFIG_SYS_PCI1_MEM_PHYS, - .size = CONFIG_SYS_PCI1_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - .bus_start = CONFIG_SYS_PCI1_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, - .size = CONFIG_SYS_PCI1_MMIO_SIZE, - .flags = PCI_REGION_MEM - }, - { - .bus_start = CONFIG_SYS_PCI1_IO_BASE, - .phys_start = CONFIG_SYS_PCI1_IO_PHYS, - .size = CONFIG_SYS_PCI1_IO_SIZE, - .flags = PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -/* - * Miscellaneous late-boot configurations - * - * If a VSC7385 microcode image is present, then upload it. -*/ -int misc_init_r(void) -{ - int rc = 0; - -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { - puts("Failure uploading VSC7385 microcode.\n"); - rc = 1; - } -#endif - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif -#else /* CONFIG_SPL_BUILD */ -void board_init_f(ulong bootflag) -{ - board_early_init_f(); - ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - puts("NAND boot... "); - timer_init(); - dram_init(); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r'); - - ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c); -} -#endif diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c deleted file mode 100644 index f146ae5d43c..00000000000 --- a/board/freescale/mpc8313erdb/sdram.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * - * Authors: Nick.Spence@freescale.com - * Wilson.Lo@freescale.com - * scottwood@freescale.com - */ - -#include <common.h> -#include <init.h> -#include <mpc83xx.h> -#include <spd_sdram.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <asm/bitops.h> -#include <asm/io.h> - -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC -static void resume_from_sleep(void) -{ - u32 magic = *(u32 *)0; - - typedef void (*func_t)(void); - func_t resume = *(func_t *)4; - - if (magic == 0xf5153ae5) - resume(); - - gd->flags &= ~GD_FLG_SILENT; - puts("\nResume from sleep failed: bad magic word\n"); -} -#endif - -/* Fixed sdram init -- doesn't use serial presence detect. - * - * This is useful for faster booting in configs where the RAM is unlikely - * to be changed, or for things like NAND booting where space is tight. - */ -static long fixed_sdram(void) -{ - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - -#ifndef CONFIG_SYS_RAMBOOT - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - __udelay(50000); - -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & - CSBNDS_EA); - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - - /* Currently we use only one CS, so disable the other bank. */ - im->ddr.cs_config[1] = 0; - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; - else -#endif - im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; - - im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - sync(); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; -#endif - - return msize; -} - -int dram_init(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &im->im_lbc; - u32 msize; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - msize = fixed_sdram(); - - /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF); - /* LB refresh timer prescal, 266MHz/32 */ - lbc->mrtpr = 0x20000000; - sync(); - -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - resume_from_sleep(); -#endif - - /* return total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig deleted file mode 100644 index f76b0d1d6db..00000000000 --- a/board/freescale/mpc8315erdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8315ERDB - -config SYS_BOARD - default "mpc8315erdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8315ERDB" - -endif diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS deleted file mode 100644 index cdac1ac2eed..00000000000 --- a/board/freescale/mpc8315erdb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8315ERDB BOARD -#M: Dave Liu <daveliu@freescale.com> -S: Orphan (since 2018-05) -F: board/freescale/mpc8315erdb/ -F: include/configs/MPC8315ERDB.h -F: configs/MPC8315ERDB_defconfig -F: configs/MPC8315ERDB_NANDSPL_defconfig diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile deleted file mode 100644 index 579181999d4..00000000000 --- a/board/freescale/mpc8315erdb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := mpc8315erdb.o sdram.o diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README deleted file mode 100644 index 8ad6d810c79..00000000000 --- a/board/freescale/mpc8315erdb/README +++ /dev/null @@ -1,105 +0,0 @@ -Freescale MPC8315ERDB Board ------------------------------------------ - -1. Board Switches and Jumpers - - S3 is used to set CONFIG_SYS_RESET_SOURCE. - - To boot the image at 0xFE000000 in NOR flash, use these DIP - switch settings for S3 S4: - - +------+ +------+ - | | | **** | - | **** | | | - +------+ ON +------+ ON - 4321 4321 - (where the '*' indicates the position of the tab of the switch.) - - To boot the image at the beginning of NAND flash, use these - DIP switch settings for S3 S4: - - +------+ +------+ - | * | | *** | - | *** | | * | - +------+ ON +------+ ON - 4321 4321 - (where the '*' indicates the position of the tab of the switch.) - - When booting from NAND, use u-boot-nand.bin, not u-boot.bin. - -2. Memory Map - The memory map looks like this: - - 0x0000_0000 0x07ff_ffff DDR 128M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K - 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M - - When booting from NAND, NAND flash is CS0 and NOR flash - is CS1. - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC8315ERDB.h - - CONFIG_MPC83xx MPC83xx family - CONFIG_MPC831x MPC831x specific - CONFIG_MPC8315 MPC8315 specific - CONFIG_MPC8315ERDB MPC8315ERDB board specific - -4. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin) - make all - -5. Downloading and Flashing Images - -5.1 Reflash U-Boot Image using U-Boot - - NOR flash: - - tftp 40000 u-boot.bin - protect off all - erase fe000000 fe1fffff - - cp.b 40000 fe000000 xxxx - protect on all - - You have to supply the correct byte count with 'xxxx' - from the TFTP result log. - - NAND flash: - - =>tftpboot $loadaddr <filename> - =>nand erase 0 0x80000 - =>nand write $loadaddr 0 0x80000 - - ...where 0x80000 is the filesize rounded up to - the next 0x20000 increment. - -5.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, rootpath (if using NFS root), - fdtfile, and bootfile). - - Then, do one of the following, depending on whether you - want an NFS root or a ramdisk root: - - =>run nfsboot - or - =>run ramboot - -6 Notes - - The console baudrate for MPC8315ERDB is 115200bps. diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c deleted file mode 100644 index e89d5d49559..00000000000 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Author: Scott Wood <scottwood@freescale.com> - * Dave Liu <daveliu@freescale.com> - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <pci.h> -#include <mpc83xx.h> -#include <netdev.h> -#include <asm/io.h> -#include <ns16550.h> -#include <nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - gd->flags |= GD_FLG_SILENT; - - return 0; -} - -#ifndef CONFIG_NAND_SPL - -static u8 read_board_info(void) -{ - u8 val8; - i2c_set_bus_num(0); - - if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) - return val8; - else - return 0; -} - -int checkboard(void) -{ - static const char * const rev_str[] = { - "0.0", - "0.1", - "1.0", - "1.1", - "<unknown>", - }; - u8 info; - int i; - - info = read_board_info(); - i = (!info) ? 4: info & 0x03; - - printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]); - - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI_MEM_BASE, - phys_start: CONFIG_SYS_PCI_MEM_PHYS, - size: CONFIG_SYS_PCI_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI_MMIO_BASE, - phys_start: CONFIG_SYS_PCI_MMIO_PHYS, - size: CONFIG_SYS_PCI_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI_IO_BASE, - phys_start: CONFIG_SYS_PCI_IO_PHYS, - size: CONFIG_SYS_PCI_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); - - /* Configure the clock for PCIE controller */ - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void fdt_tsec1_fixup(void *fdt, struct bd_info *bd) -{ - const char disabled[] = "disabled"; - const char *path; - int ret; - - if (hwconfig_arg_cmp("board_type", "tsec1")) { - return; - } else if (!hwconfig_arg_cmp("board_type", "ulpi")) { - printf("NOTICE: No or unknown board_type hwconfig specified.\n" - " Assuming board with TSEC1.\n"); - return; - } - - ret = fdt_path_offset(fdt, "/aliases"); - if (ret < 0) { - printf("WARNING: can't find /aliases node\n"); - return; - } - - path = fdt_getprop(fdt, ret, "ethernet0", NULL); - if (!path) { - printf("WARNING: can't find ethernet0 alias\n"); - return; - } - - do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_tsec1_fixup(blob, bd); - - return 0; -} -#endif - -int board_eth_init(struct bd_info *bis) -{ - cpu_eth_init(bis); /* Initialize TSECs first */ - return pci_eth_init(bis); -} - -#else /* CONFIG_NAND_SPL */ - -int checkboard(void) -{ - puts("Board: Freescale MPC8315ERDB\n"); - return 0; -} - -void board_init_f(ulong bootflag) -{ - board_early_init_f(); - ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - puts("NAND boot... "); - timer_init(); - dram_init(); - relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, - CONFIG_SYS_NAND_U_BOOT_RELOC); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (gd->flags & GD_FLG_SILENT) - return; - - if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r'); - - ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c); -} - -#endif /* CONFIG_NAND_SPL */ diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c deleted file mode 100644 index ffbb79aaec1..00000000000 --- a/board/freescale/mpc8315erdb/sdram.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Authors: Nick.Spence@freescale.com - * Wilson.Lo@freescale.com - * scottwood@freescale.com - */ - -#include <common.h> -#include <init.h> -#include <mpc83xx.h> -#include <spd_sdram.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <asm/bitops.h> -#include <asm/io.h> - -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void resume_from_sleep(void) -{ - u32 magic = *(u32 *)0; - - typedef void (*func_t)(void); - func_t resume = *(func_t *)4; - - if (magic == 0xf5153ae5) - resume(); - - gd->flags &= ~GD_FLG_SILENT; - puts("\nResume from sleep failed: bad magic word\n"); -} - -/* Fixed sdram init -- doesn't use serial presence detect. - * - * This is useful for faster booting in configs where the RAM is unlikely - * to be changed, or for things like NAND booting where space is tight. - */ -#ifndef CONFIG_SYS_RAMBOOT -static long fixed_sdram(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - __udelay(50000); - - im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - - /* Currently we use only one CS, so disable the other bank. */ - im->ddr.cs_config[1] = 0; - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; - else - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - sync(); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - sync(); - - return msize; -} -#else -static long fixed_sdram(void) -{ - return CONFIG_SYS_DDR_SIZE * 1024 * 1024; -} -#endif /* CONFIG_SYS_RAMBOOT */ - -int dram_init(void) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - u32 msize; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM */ - msize = fixed_sdram(); - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - resume_from_sleep(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig deleted file mode 100644 index acf81221966..00000000000 --- a/board/freescale/mpc8323erdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8323ERDB - -config SYS_BOARD - default "mpc8323erdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8323ERDB" - -endif diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS deleted file mode 100644 index 496ab2af271..00000000000 --- a/board/freescale/mpc8323erdb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8323ERDB BOARD -#M: Michael Barkowski <michael.barkowski@freescale.com> -S: Orphan (since 2018-05) -F: board/freescale/mpc8323erdb/ -F: include/configs/MPC8323ERDB.h -F: configs/MPC8323ERDB_defconfig diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile deleted file mode 100644 index e6f61891d9c..00000000000 --- a/board/freescale/mpc8323erdb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := mpc8323erdb.o diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README deleted file mode 100644 index 9a46da07818..00000000000 --- a/board/freescale/mpc8323erdb/README +++ /dev/null @@ -1,71 +0,0 @@ -Freescale MPC8323ERDB Board ------------------------------------------ - -1. Memory Map - The memory map looks like this: - - 0x0000_0000 0x03ff_ffff DDR 64M - 0x8000_0000 0x8fff_ffff PCI MEM 256M - 0x9000_0000 0x9fff_ffff PCI_MMIO 256M - 0xe000_0000 0xe00f_ffff IMMR 1M - 0xd000_0000 0xd3ff_ffff PCI IO 64M - 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M - -2. Compilation - - Assuming you're using BASH (or similar) as your shell: - - export CROSS_COMPILE=your-cross-compiler-prefix- - make distclean - make MPC8323ERDB_config - make - -3. Downloading and Flashing Images - -3.1 Reflash U-Boot Image using U-Boot - - N.b, have an alternate means of programming - the flash available if the new U-Boot doesn't boot. - - First try a: - - tftpboot $loadaddr $uboot - - to make sure that the TFTP load will succeed before - an erase goes ahead and wipes out your current firmware. - Then do a: - - run tftpflash - - which is a shorter version of the manual sequence: - - tftp $loadaddr u-boot.bin - protect off fe000000 +$filesize - erase fe000000 +$filesize - cp.b $loadaddr fe000000 $filesize - - To keep your old U-Boot's environment variables, do a: - - saveenv - - prior to resetting the board. - -3.2 Downloading and Booting Linux Kernel - - Ensure that all networking-related environment variables are set - properly (including ipaddr, serverip, gatewayip (if needed), - netmask, ethaddr, eth1addr, rootpath (if using NFS root), - fdtfile, and bootfile). - - Then, do one of the following, depending on whether you - want an NFS root or a ramdisk root: - - run nfsboot - - or - - run ramboot - -4 Notes - - The console baudrate for MPC8323ERDB is 115200bps. diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c deleted file mode 100644 index cef3216a6fe..00000000000 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Michael Barkowski <michael.barkowski@freescale.com> - * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <common.h> -#include <eeprom.h> -#include <env.h> -#include <fdt_support.h> -#include <init.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <i2c.h> -#include <miiphy.h> -#include <command.h> -#include <asm/global_data.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <u-boot/crc.h> -#if defined(CONFIG_PCI) -#include <pci.h> -#endif -#include <asm/mmu.h> - -DECLARE_GLOBAL_DATA_PTR; - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* UCC3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ - - /* UCC2 */ - {0, 18, 1, 0, 1}, /* TxD0 */ - {0, 19, 1, 0, 1}, /* TxD1 */ - {0, 20, 1, 0, 1}, /* TxD2 */ - {0, 21, 1, 0, 1}, /* TxD3 */ - {0, 27, 1, 0, 1}, /* TxER */ - {0, 30, 1, 0, 1}, /* TxEN */ - {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ - - {0, 22, 2, 0, 1}, /* RxD0 */ - {0, 23, 2, 0, 1}, /* RxD1 */ - {0, 24, 2, 0, 1}, /* RxD2 */ - {0, 25, 2, 0, 1}, /* RxD3 */ - {0, 26, 1, 0, 1}, /* RxER */ - {0, 28, 2, 0, 1}, /* Rx_DV */ - {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ - {0, 29, 2, 0, 1}, /* COL */ - {0, 31, 2, 0, 1}, /* CRS */ - - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -int fixed_sdram(void); - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; - - msize = fixed_sdram(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__ ("sync"); - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - __asm__ __volatile__ ("sync"); - return msize; -} - -int checkboard(void) -{ - puts("Board: Freescale MPC8323ERDB\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_SYS_I2C_MAC_OFFSET) -int mac_read_from_eeprom(void) -{ - uchar buf[28]; - char str[18]; - int i = 0; - unsigned int crc = 0; - unsigned char enetvar[32]; - - /* Read MAC addresses from EEPROM */ - if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) { - printf("\nEEPROM @ 0x%02x read FAILED!!!\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - } else { - uint32_t crc_buf; - - memcpy(&crc_buf, &buf[24], sizeof(uint32_t)); - - if (crc32(crc, buf, 24) == crc_buf) { - printf("Reading MAC from EEPROM\n"); - for (i = 0; i < 4; i++) { - if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) { - sprintf(str, - "%02X:%02X:%02X:%02X:%02X:%02X", - buf[i * 6], buf[i * 6 + 1], - buf[i * 6 + 2], buf[i * 6 + 3], - buf[i * 6 + 4], buf[i * 6 + 5]); - sprintf((char *)enetvar, - i ? "eth%daddr" : "ethaddr", i); - env_set((char *)enetvar, str); - } - } - } - } - return 0; -} -#endif /* CONFIG_I2C_MAC_OFFSET */ diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig deleted file mode 100644 index e4cfa15a6f2..00000000000 --- a/board/freescale/mpc832xemds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC832XEMDS - -config SYS_BOARD - default "mpc832xemds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC832XEMDS" - -endif diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS deleted file mode 100644 index 232658a203c..00000000000 --- a/board/freescale/mpc832xemds/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -MPC832XEMDS BOARD -#M: Dave Liu <daveliu@freescale.com> -S: Orphan (since 2018-05) -F: board/freescale/mpc832xemds/ -F: include/configs/MPC832XEMDS.h -F: configs/MPC832XEMDS_defconfig -F: configs/MPC832XEMDS_ATM_defconfig -F: configs/MPC832XEMDS_HOST_33_defconfig -F: configs/MPC832XEMDS_HOST_66_defconfig -F: configs/MPC832XEMDS_SLAVE_defconfig diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile deleted file mode 100644 index b1551bf4786..00000000000 --- a/board/freescale/mpc832xemds/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc832xemds.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README deleted file mode 100644 index d141cd33e78..00000000000 --- a/board/freescale/mpc832xemds/README +++ /dev/null @@ -1,128 +0,0 @@ -Freescale MPC832XEMDS Board ------------------------------------------ -1. Board Switches and Jumpers -1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" is logic 1. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW3 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labeled 8 on Switch 4. - SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. - SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. - SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" - and bits labeled 8 is set as "Off". - -1.1 For the MPC832XEMDS PROTO Board - - First, make sure the board default setting is consistent with the document - shipped with your board. Then apply the following setting: - SW3[1-8]= 0000_1000 (core PLL setting, core enable) - SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) - SW5[1-8]= 0010_0110 (Boot from high end) - SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) - SW7[1-8]= 1000_0011 (QE PLL setting) - - ENET3/4 MII mode settings: - J1 1-2 (ETH3_TXER) - J2 2-3 (MII mode) - J3 2-3 (MII mode) - J4 2-3 (ADSL clockOscillator) - J5 1-2 (ETH4_TXER) - J6 2-3 (ClockOscillator) - JP1 removed (don't force PORESET) - JP2 mounted (ETH4/2 MII) - JP3 mounted (ETH3 MII) - JP4 mounted (HRCW from BCSR) - - ENET3/4 RMII mode settings: - J1 1-2 (ETH3_TXER) - J2 1-2 (RMII mode) - J3 1-2 (RMII mode) - J4 2-3 (ADSL clockOscillator) - J5 1-2 (ETH4_TXER) - J6 2-3 (ClockOscillator) - JP1 removed (don't force PORESET) - JP2 removed (ETH4/2 RMII) - JP3 removed (ETH3 RMII) - JP4 removed (HRCW from FLASH) - - on board Oscillator: 66M - - -2. Memory Map - -2.1 The memory map should look pretty much like this: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M - 0xc000_0000 0xdfff_ffff Empty 512M - 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M - 0xe020_0000 0xe02f_ffff Empty 1M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe040_0000 0xefff_ffff Empty 252M - 0xf400_0000 0xf7ff_ffff Empty 64M - 0xf800_0000 0xf800_7fff BCSR on CS1 32K - 0xf800_8000 0xf800_ffff PIB CS2 32K - 0xf801_0000 0xf801_7fff PIB CS3 32K - 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M - - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC832XEPB.h - - CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x - CONFIG_MPC832x MPC832x specific - CONFIG_MPC832XEMDS MPC832XEMDS board specific - -4. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC832XEMDS_config - make - - MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI: - - 1)Make sure the DIP SW support PCI mode as described in Section 1.1. - - 2)To Make U-Boot image support PCI 33MHz, use - Make MPC832XEMDS_HOST_33_config - - 3)To Make U-Boot image support PCI 66MHz, use - Make MPC832XEMDS_HOST_66M_config - -5. Downloading and Flashing Images - -5.0 Download over network: - - tftp 10000 u-boot.bin - -5.1 Reflash U-Boot Image using U-Boot - - tftp 20000 u-boot.bin - protect off fe000000 fe0fffff - erase fe000000 fe0fffff - cp.b 20000 fe000000 xxxx - -You have to supply the correct byte count with 'xxxx' from the TFTP result log. -Maybe 3ffff will work too, that corresponds to the erased sectors. - - -6. Notes - 1) The console baudrate for MPC832XEMDS is 115200bps. diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c deleted file mode 100644 index f34758a9470..00000000000 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * Dave Liu <daveliu@freescale.com> - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <i2c.h> -#include <miiphy.h> -#include <command.h> -#if defined(CONFIG_PCI) -#include <pci.h> -#endif -#include <asm/global_data.h> -#include <asm/mmu.h> -#if defined(CONFIG_OF_LIBFDT) -#include <linux/libfdt.h> -#endif -#if defined(CONFIG_PQ_MDS_PIB) -#include "../common/pq-mds-pib.h" -#endif -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* ETH3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ - - /* ETH4 */ - {1, 18, 1, 0, 1}, /* TxD0 */ - {1, 19, 1, 0, 1}, /* TxD1 */ - {1, 20, 1, 0, 1}, /* TxD2 */ - {1, 21, 1, 0, 1}, /* TxD3 */ - {1, 27, 1, 0, 1}, /* TxER */ - {1, 30, 1, 0, 1}, /* TxEN */ - {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ - - {1, 22, 2, 0, 1}, /* RxD0 */ - {1, 23, 2, 0, 1}, /* RxD1 */ - {1, 24, 2, 0, 1}, /* RxD2 */ - {1, 25, 2, 0, 1}, /* RxD3 */ - {1, 26, 1, 0, 1}, /* RxER */ - {1, 28, 2, 0, 1}, /* Rx_DV */ - {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ - {1, 29, 2, 0, 1}, /* COL */ - {1, 31, 2, 0, 1}, /* CRS */ - - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -int board_early_init_f(void) -{ - volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[9] &= ~0x08; - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - return 0; -} - -int fixed_sdram(void); - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; - - msize = fixed_sdram(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CONFIG_SYS_DDR_SIZE != 128) -#warning Currenly any ddr size other than 128 is not supported -#endif - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__ ("sync"); - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - __asm__ __volatile__ ("sync"); - return msize; -} - -int checkboard(void) -{ - puts("Board: Freescale MPC832XEMDS\n"); - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c deleted file mode 100644 index 944108f6319..00000000000 --- a/board/freescale/mpc832xemds/pci.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -/* - * PCI Configuration space access support for MPC83xx PCI Bridge - */ -#include <init.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <common.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <asm/fsl_i2c.h> -#include <linux/delay.h> -#include "../common/pq-mds-pib.h" - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -void pci_init_board(void) -#ifdef CONFIG_PCISLAVE -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; - struct pci_region *reg[] = { pci1_regions }; - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - - mpc83xx_pci_init(1, reg); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar0 = 0x0; - pci_ctrl[0].pibar0 = 0x0; - pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_4K; - - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 &= ~PIWAR_EN; - - pci_ctrl[0].pitar2 = 0x0; - pci_ctrl[0].pibar2 = 0x0; - pci_ctrl[0].piebar2 = 0x0; - pci_ctrl[0].piwar2 &= ~PIWAR_EN; - - /* Unlock the configuration bit */ - mpc83xx_pcislave_unlock(0); - printf("PCI: Agent mode enabled\n"); -} -#else -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; -#ifndef CONFIG_MPC83XX_PCI2 - struct pci_region *reg[] = { pci1_regions }; -#else - struct pci_region *reg[] = { pci1_regions, pci2_regions }; -#endif - - /* initialize the PCA9555PW IO expander on the PIB board */ - pib_init(); - -#if defined(CONFIG_PCI_66M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#elif defined(CONFIG_PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - udelay(2000); - -#ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg); -#else - mpc83xx_pci_init(2, reg); -#endif -} -#endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig deleted file mode 100644 index 034eab25443..00000000000 --- a/board/freescale/mpc8541cds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8541CDS - -config SYS_BOARD - default "mpc8541cds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8541CDS" - -endif diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS deleted file mode 100644 index cf3b9cf5f72..00000000000 --- a/board/freescale/mpc8541cds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8541CDS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8541cds/ -F: include/configs/MPC8541CDS.h -F: configs/MPC8541CDS_defconfig -F: configs/MPC8541CDS_legacy_defconfig diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile deleted file mode 100644 index b2b721ac92d..00000000000 --- a/board/freescale/mpc8541cds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8541cds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c deleted file mode 100644 index 05c56a85d24..00000000000 --- a/board/freescale/mpc8541cds/ddr.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 6; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c deleted file mode 100644 index 69f151b6151..00000000000 --- a/board/freescale/mpc8541cds/law.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c deleted file mode 100644 index 5b4fbd5e304..00000000000 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ /dev/null @@ -1,429 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - */ - -#include <common.h> -#include <init.h> -#include <pci.h> -#include <vsprintf.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <spd_sdram.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> - -#include "../common/cadmus.h" -#include "../common/eeprom.h" -#include "../common/via.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - char buf[32]; - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - - uint cpu_board_rev = get_cpu_board_revision (); - - printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf("PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - strmhz(buf, pci1_speed), - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf("PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf("PCI2: disabled\n"); - } - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - uint temp_lbcdll; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - - } else { - lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * Determine which address lines to use baed on CPU board rev. - */ - cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= LSDMR_BSMA1617; - } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= LSDMR_BSMA1516; - } else { - /* - * Assume something unable to identify itself is - * really old, and likely has lines 16/17 mapped. - */ - lsdmr_common |= LSDMR_BSMA1617; - } - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CONFIG_PCI) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller hose[] = { - { config_table: pci_mpc85xxcds_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - -#endif /* CONFIG_PCI */ - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(hose); -#endif -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_pci_setup(void *blob, struct bd_info *bd) -{ - int node, tmp[2]; - const char *path; - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose[0].last_busno - hose[0].first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif -#ifdef CONFIG_MPC85XX_PCI2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = hose[1].last_busno - hose[1].first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c deleted file mode 100644 index d4ed51c5438..00000000000 --- a/board/freescale/mpc8541cds/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8555cds/Kconfig b/board/freescale/mpc8555cds/Kconfig deleted file mode 100644 index 04bd572212a..00000000000 --- a/board/freescale/mpc8555cds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8555CDS - -config SYS_BOARD - default "mpc8555cds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8555CDS" - -endif diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS deleted file mode 100644 index 8f32febd914..00000000000 --- a/board/freescale/mpc8555cds/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC8555CDS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8555cds/ -F: include/configs/MPC8555CDS.h -F: configs/MPC8555CDS_defconfig -F: configs/MPC8555CDS_legacy_defconfig diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile deleted file mode 100644 index f121c2fa6b2..00000000000 --- a/board/freescale/mpc8555cds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8555cds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c deleted file mode 100644 index 05c56a85d24..00000000000 --- a/board/freescale/mpc8555cds/ddr.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 6; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c deleted file mode 100644 index 69f151b6151..00000000000 --- a/board/freescale/mpc8555cds/law.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M - * 0xe210_0000 0xe21f_ffff PCI2 IO 1M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c deleted file mode 100644 index 3bb8e769c80..00000000000 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ /dev/null @@ -1,430 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - */ - -#include <common.h> -#include <init.h> -#include <pci.h> -#include <vsprintf.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <spd_sdram.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> - -#include "../common/cadmus.h" -#include "../common/eeprom.h" -#include "../common/via.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - char buf[32]; - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - - uint cpu_board_rev = get_cpu_board_revision (); - - printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf("PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - strmhz(buf, pci1_speed), - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf("PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf("PCI2: disabled\n"); - } - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - uint temp_lbcdll; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - - } else { - lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * Determine which address lines to use baed on CPU board rev. - */ - cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= LSDMR_BSMA1617; - } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= LSDMR_BSMA1516; - } else { - /* - * Assume something unable to identify itself is - * really old, and likely has lines 16/17 mapped. - */ - lsdmr_common |= LSDMR_BSMA1617; - } - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#ifdef CONFIG_PCI -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - - -static struct pci_controller hose[] = { - { - config_table: pci_mpc85xxcds_config_table, - }, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - -#endif - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(hose); -#endif -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_pci_setup(void *blob, struct bd_info *bd) -{ - int node, tmp[2]; - const char *path; - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose[0].last_busno - hose[0].first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif -#ifdef CONFIG_MPC85XX_PCI2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = hose[1].last_busno - hose[1].first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c deleted file mode 100644 index 4a18f05af0d..00000000000 --- a/board/freescale/mpc8555cds/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig deleted file mode 100644 index 4e178c50396..00000000000 --- a/board/freescale/mpc8568mds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8568MDS - -config SYS_BOARD - default "mpc8568mds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8568MDS" - -endif diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS deleted file mode 100644 index f4747866d2b..00000000000 --- a/board/freescale/mpc8568mds/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8568MDS BOARD -M: Priyanka Jain <priyanka.jain@nxp.com> -S: Maintained -F: board/freescale/mpc8568mds/ -F: include/configs/MPC8568MDS.h -F: configs/MPC8568MDS_defconfig diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile deleted file mode 100644 index 1e9095bdddd..00000000000 --- a/board/freescale/mpc8568mds/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2004-2007 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8568mds.o -obj-y += bcsr.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c deleted file mode 100644 index b1e638af5ae..00000000000 --- a/board/freescale/mpc8568mds/bcsr.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007 Freescale Semiconductor. - */ - -#include <common.h> -#include <flash.h> -#include <asm/io.h> - -#include "bcsr.h" - -void enable_8568mds_duart(void) -{ - volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); - volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ - *devices = 0; /* Enable all peripheral devices */ - bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ -} - -void enable_8568mds_flash_write(void) -{ - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - bcsr[9] |= 0x01; -} - -void disable_8568mds_flash_write(void) -{ - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - bcsr[9] &= ~(0x01); -} - -void enable_8568mds_qe_mdio(void) -{ - u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - bcsr[7] |= 0x01; -} - -#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) -void reset_8568mds_uccs(void) -{ - volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); - - /* Turn off UCC1 & UCC2 */ - out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); - out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN); - - /* Mode is RGMII, all bits clear */ - out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK | - BCSR_UCC2_MODE_MSK)); - - /* Turn UCC1 & UCC2 on */ - out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN); - out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN); -} -#endif diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h deleted file mode 100644 index a8e13a2a557..00000000000 --- a/board/freescale/mpc8568mds/bcsr.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007 Freescale Semiconductor. - */ - -#ifndef __BCSR_H_ -#define __BCSR_H_ - -#include <common.h> - -/* BCSR Bit definitions - * BCSR 0 * - 0:3 ccb sys pll - 4:6 cfg core pll - 7 cfg boot seq - - * BCSR 1 * - 0:2 cfg rom lock - 3:5 cfg host agent - 6 PCI IO - 7 cfg RIO size - - * BCSR 2 * - 0:4 QE PLL - 5 QE clock - 6 cfg PCI arbiter - - * BCSR 3 * - 0 TSEC1 reduce - 1 TSEC2 reduce - 2:3 TSEC1 protocol - 4:5 TSEC2 protocol - 6 PHY1 slave - 7 PHY2 slave - - * BCSR 4 * - 4 clock enable - 5 boot EPROM - 6 GETH transactive reset - 7 BRD write potect - - * BCSR 5 * - 1:3 Leds 1-3 - 4 UPC1 enable - 5 UPC2 enable - 6 UPC2 pos - 7 RS232 enable - - * BCSR 6 * - 0 CFG ver 0 - 1 CFG ver 1 - 6 Register config led - 7 Power on reset - - * BCSR 7 * - 2 board host mode indication - 5 enable TSEC1 PHY - 6 enable TSEC2 PHY - - * BCSR 8 * - 0 UCC GETH1 enable - 1 UCC GMII enable - 3 UCC TBI enable - 5 UCC MII enable - 7 Real time clock reset - - * BCSR 9 * - 0 UCC2 GETH enable - 1 UCC2 GMII enable - 3 UCC2 TBI enable - 5 UCC2 MII enable - 6 Ready only - indicate flash ready after burning - 7 Flash write protect -*/ - -#define BCSR_UCC1_GETH_EN (0x1 << 7) -#define BCSR_UCC2_GETH_EN (0x1 << 7) -#define BCSR_UCC1_MODE_MSK (0x3 << 4) -#define BCSR_UCC2_MODE_MSK (0x3 << 0) - -/*BCSR Utils functions*/ - -void enable_8568mds_duart(void); -void enable_8568mds_flash_write(void); -void disable_8568mds_flash_write(void); -void enable_8568mds_qe_mdio(void); - -#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) -void reset_8568mds_uccs(void); -#endif - -#endif /* __BCSR_H_ */ diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c deleted file mode 100644 index 58a979dbc76..00000000000 --- a/board/freescale/mpc8568mds/ddr.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 6; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c deleted file mode 100644 index c04c36b5d82..00000000000 --- a/board/freescale/mpc8568mds/law.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB - *-) 0xe000_0000 0xe00f_ffff CCSR 1M - *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M - *5) 0xc000_0000 0xdfff_ffff SRIO 512MB - *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB - *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB - *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB - *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB - *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB - * - *Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - */ - -struct law_entry law_table[] = { - /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c deleted file mode 100644 index 7b379464cd5..00000000000 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - */ - -#include <common.h> -#include <flash.h> -#include <init.h> -#include <log.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <spd_sdram.h> -#include <i2c.h> -#include <ioports.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> - -#include "bcsr.h" - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* GETH1 */ - {4, 10, 1, 0, 2}, /* TxD0 */ - {4, 9, 1, 0, 2}, /* TxD1 */ - {4, 8, 1, 0, 2}, /* TxD2 */ - {4, 7, 1, 0, 2}, /* TxD3 */ - {4, 23, 1, 0, 2}, /* TxD4 */ - {4, 22, 1, 0, 2}, /* TxD5 */ - {4, 21, 1, 0, 2}, /* TxD6 */ - {4, 20, 1, 0, 2}, /* TxD7 */ - {4, 15, 2, 0, 2}, /* RxD0 */ - {4, 14, 2, 0, 2}, /* RxD1 */ - {4, 13, 2, 0, 2}, /* RxD2 */ - {4, 12, 2, 0, 2}, /* RxD3 */ - {4, 29, 2, 0, 2}, /* RxD4 */ - {4, 28, 2, 0, 2}, /* RxD5 */ - {4, 27, 2, 0, 2}, /* RxD6 */ - {4, 26, 2, 0, 2}, /* RxD7 */ - {4, 11, 1, 0, 2}, /* TX_EN */ - {4, 24, 1, 0, 2}, /* TX_ER */ - {4, 16, 2, 0, 2}, /* RX_DV */ - {4, 30, 2, 0, 2}, /* RX_ER */ - {4, 17, 2, 0, 2}, /* RX_CLK */ - {4, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ - - /* GETH2 */ - {5, 10, 1, 0, 2}, /* TxD0 */ - {5, 9, 1, 0, 2}, /* TxD1 */ - {5, 8, 1, 0, 2}, /* TxD2 */ - {5, 7, 1, 0, 2}, /* TxD3 */ - {5, 23, 1, 0, 2}, /* TxD4 */ - {5, 22, 1, 0, 2}, /* TxD5 */ - {5, 21, 1, 0, 2}, /* TxD6 */ - {5, 20, 1, 0, 2}, /* TxD7 */ - {5, 15, 2, 0, 2}, /* RxD0 */ - {5, 14, 2, 0, 2}, /* RxD1 */ - {5, 13, 2, 0, 2}, /* RxD2 */ - {5, 12, 2, 0, 2}, /* RxD3 */ - {5, 29, 2, 0, 2}, /* RxD4 */ - {5, 28, 2, 0, 2}, /* RxD5 */ - {5, 27, 2, 0, 3}, /* RxD6 */ - {5, 26, 2, 0, 2}, /* RxD7 */ - {5, 11, 1, 0, 2}, /* TX_EN */ - {5, 24, 1, 0, 2}, /* TX_ER */ - {5, 16, 2, 0, 2}, /* RX_DV */ - {5, 30, 2, 0, 2}, /* RX_ER */ - {5, 17, 2, 0, 2}, /* RX_CLK */ - {5, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ - {4, 6, 3, 0, 2}, /* MDIO */ - {4, 5, 1, 0, 2}, /* MDC */ - - /* UART1 */ - {2, 0, 1, 0, 2}, /* UART_SOUT1 */ - {2, 1, 1, 0, 2}, /* UART_RTS1 */ - {2, 2, 2, 0, 2}, /* UART_CTS1 */ - {2, 3, 2, 0, 2}, /* UART_SIN1 */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -void local_bus_init(void); - -int board_early_init_f (void) -{ - /* - * Initialize local bus. - */ - local_bus_init (); - - enable_8568mds_duart(); - enable_8568mds_flash_write(); -#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) - reset_8568mds_uccs(); -#endif -#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) - enable_8568mds_qe_mdio(); -#endif - -#ifdef CONFIG_SYS_I2C2_OFFSET - /* Enable I2C2_SCL and I2C2_SDA */ - volatile struct par_io *port_c; - port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); - port_c->cpdir2 |= 0x0f000000; - port_c->cppar2 &= ~0x0f000000; - port_c->cppar2 |= 0x0a000000; -#endif - - return 0; -} - -int checkboard (void) -{ - printf ("Board: 8568 MDS\n"); - - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - - gur->lbiuiplldcr1 = 0x00078080; - if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; - } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; - } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; - } - - lbc->lcrr |= 0x00030000; - - asm("sync;isync;msync"); -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - asm("msync"); - - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * MPC8568 uses "new" 15-16 style addressing. - */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - lsdmr_common |= LSDMR_BSMA1516; - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CONFIG_PCI) -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8568mds_config_table[] = { - { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} - }, - {} -}; -#endif - -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -/* - * pib_init() -- Initialize the PCA9555 IO expander on the PIB board - */ -void -pib_init(void) -{ - u8 val8, orig_i2c_bus; - /* - * Assign PIB PMC2/3 to PCI bus - */ - - /*switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0x00; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0x00; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - val8 = 0xf9; - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0x00; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - - asm("eieio"); - i2c_set_bus_num(orig_i2c_bus); -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int first_free_busno = 0; -#ifdef CONFIG_PCI1 - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug(" %s: devdisr=%x, io_sel=%x\n", __func__, devdisr, io_sel); - - pci_speed = 66666000; - pci_32 = 1; - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - -#ifndef CONFIG_PCI_PNP - pci1_hose.config_table = pci_mpc8568mds_config_table; -#endif - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif - - fsl_pcie_init_board(first_free_busno); -} -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - - return 0; -} -#endif diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c deleted file mode 100644 index fea1606a1d3..00000000000 --- a/board/freescale/mpc8568mds/tlb.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 Initializations */ - /* - * TLBe 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH (upper half) - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLBe 1: 16M Non-cacheable, guarded - * 0xfe000000 16M FLASH (lower half) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* - * TLBe 2: 1G Non-cacheable, guarded - * 0x80000000 512M PCI1 MEM - * 0xa0000000 512M PCIe MEM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1G, 1), - - /* - * TLBe 3: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCIe IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), - - /* - * TLBe 4: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 4, BOOKE_PAGESZ_64M, 1), - - /* - * TLBe 5: 256K Non-cacheable, guarded - * 0xf8000000 32K BCSR - * 0xf8008000 32K PIB (CS4) - * 0xf8010000 32K PIB (CS5) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS index 471ea07d3ca..df1f0bed939 100644 --- a/board/freescale/t102xrdb/MAINTAINERS +++ b/board/freescale/t102xrdb/MAINTAINERS @@ -7,8 +7,3 @@ F: configs/T1024RDB_defconfig F: configs/T1024RDB_NAND_defconfig F: configs/T1024RDB_SDCARD_defconfig F: configs/T1024RDB_SPIFLASH_defconfig -F: configs/T1024RDB_SECURE_BOOT_defconfig -F: configs/T1023RDB_defconfig -F: configs/T1023RDB_NAND_defconfig -F: configs/T1023RDB_SDCARD_defconfig -F: configs/T1023RDB_SPIFLASH_defconfig diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig index a94a57e7fee..542e574fed1 100644 --- a/board/freescale/t4rdb/Kconfig +++ b/board/freescale/t4rdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_T4160RDB || TARGET_T4240RDB +if TARGET_T4240RDB config SYS_BOARD default "t4rdb" diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS index 7380408aaec..844a15259c0 100644 --- a/board/freescale/t4rdb/MAINTAINERS +++ b/board/freescale/t4rdb/MAINTAINERS @@ -3,6 +3,5 @@ M: Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/t4rdb/ F: include/configs/T4240RDB.h -F: configs/T4160RDB_defconfig F: configs/T4240RDB_defconfig F: configs/T4240RDB_SDCARD_defconfig diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 209983a24bd..f1fd623339c 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -7,7 +7,6 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o obj-y += eth.o |