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-rw-r--r--board/innokom/Makefile2
-rw-r--r--board/innokom/config.mk1
-rw-r--r--board/innokom/flash.c58
-rw-r--r--board/innokom/innokom.c25
-rw-r--r--board/innokom/memsetup.S137
-rw-r--r--board/innokom/u-boot.lds24
6 files changed, 123 insertions, 124 deletions
diff --git a/board/innokom/Makefile b/board/innokom/Makefile
index 7fbe76b727c..59eaee58b1c 100644
--- a/board/innokom/Makefile
+++ b/board/innokom/Makefile
@@ -29,7 +29,7 @@ OBJS := innokom.o flash.o
SOBJS := memsetup.o
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/innokom/config.mk b/board/innokom/config.mk
index 939ffffcf1f..23543920c30 100644
--- a/board/innokom/config.mk
+++ b/board/innokom/config.mk
@@ -13,4 +13,3 @@
# for the addresses _after_ relocation to RAM!! Otherwhise the
# .bss segment is assumed in flash...
TEXT_BASE = 0xa1fe0000
-
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
index b7c2072e707..3caf43d21c3 100644
--- a/board/innokom/flash.c
+++ b/board/innokom/flash.c
@@ -10,7 +10,7 @@
* Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
*
* (C) Copyright 2002
- * Auerswald GmbH & Co KG, Germany
+ * Auerswald GmbH & Co KG, Germany
* Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
*
* See file CREDITS for list of people who contributed to this
@@ -42,7 +42,6 @@
/* Debugging macros ------------------------------------------------------ */
#undef FLASH_DEBUG
-//#define FLASH_DEBUG 1
/* Some debug macros */
#if (FLASH_DEBUG > 2 )
@@ -107,10 +106,10 @@ struct part_info* jffs2_part_info(int part_num) {
/* u-boot partition */
if(part_num==0){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x00000000;
part.size=256*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
@@ -121,24 +120,24 @@ struct part_info* jffs2_part_info(int part_num) {
/* primary OS+firmware partition */
if(part_num==1){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x00040000;
part.size=768*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
}
-
+
/* secondary OS+firmware partition */
if(part_num==2){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x00100000;
part.size=8*1024*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
@@ -149,17 +148,17 @@ struct part_info* jffs2_part_info(int part_num) {
/* data partition */
if(part_num==3){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x00900000;
part.size=7*1024*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
}
-
+
if (current_part == part_num) {
part.usr_priv = &current_part;
part.jffs2_priv = jffs2_priv_saved;
@@ -186,10 +185,10 @@ struct part_info* jffs2_part_info(int part_num) {
/* u-boot partition */
if(part_num==0){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x00000000;
part.size=256*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
@@ -200,24 +199,24 @@ struct part_info* jffs2_part_info(int part_num) {
/* primary OS+firmware partition */
if(part_num==1){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x00040000;
part.size=16*1024*1024-128*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
}
-
+
/* secondary OS+firmware partition */
if(part_num==2){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x01020000;
part.size=16*1024*1024-128*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
@@ -228,17 +227,17 @@ struct part_info* jffs2_part_info(int part_num) {
/* data partition */
if(part_num==3){
memset(&part, 0, sizeof(part));
-
+
part.offset=(char*)0x02000000;
part.size=32*1024*1024;
-
+
/* Mark the struct as ready */
current_part = part_num;
PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
}
-
+
if (current_part == part_num) {
part.usr_priv = &current_part;
part.jffs2_priv = jffs2_priv_saved;
@@ -335,13 +334,13 @@ void flash_print_info (flash_info_t *info)
return;
}
- printf(" Size: %ld MB in %d Sectors\n",
+ printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) printf ("\n ");
-
+
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
@@ -370,7 +369,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
-
+
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) prot++;
@@ -420,13 +419,13 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
goto outahere;
}
}
-
+
PRINTK("clearing status register\n");
- *addr = 0x0050;
+ *addr = 0x0050;
PRINTK("resetting to read mode");
- *addr = 0x00FF;
+ *addr = 0x00FF;
}
-
+
printf("ok.\n");
}
@@ -595,4 +594,3 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
return write_word(info, wp, data);
}
-
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index da238da6c79..ae5402e8431 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -46,10 +46,10 @@ int i2c_init_board(void)
/* disable I2C controller first, otherwhise it thinks we want to */
/* talk to the slave port... */
icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
-
+
/* set gpio pin low _before_ we change direction to output */
GPCR(70) = GPIO_bit(70);
-
+
/* now toggle between output=low and high-impedance */
for (i = 0; i < 20; i++) {
GPDR(70) |= GPIO_bit(70); /* output */
@@ -144,18 +144,18 @@ void innokom_set_led(int led, int state)
break;
case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
- }
- break;
+ GPCR0 |= CSB226_USER_LED1;
+ } else if (state==0) {
+ GPSR0 |= CSB226_USER_LED1;
+ }
+ break;
case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
- }
- break;
+ GPCR0 |= CSB226_USER_LED2;
+ } else if (state==0) {
+ GPSR0 |= CSB226_USER_LED2;
+ }
+ break;
*/
}
@@ -184,4 +184,3 @@ void show_boot_progress (int status)
return;
}
-
diff --git a/board/innokom/memsetup.S b/board/innokom/memsetup.S
index 60f9d50b58e..68577ca0699 100644
--- a/board/innokom/memsetup.S
+++ b/board/innokom/memsetup.S
@@ -159,7 +159,7 @@ memsetup:
mem_init:
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
@@ -167,65 +167,65 @@ mem_init:
/* MSC registers: timing, bus width, mem type */
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
+ /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
adr r3, mem_init /* r0 <- current position of code */
ldr r2, =mem_init
cmp r3, r2 /* skip init if in place */
@@ -233,8 +233,8 @@ mem_init:
/* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
@@ -246,7 +246,7 @@ mem_init:
orr r4, r4, r3
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
/* ---------------------------------------------------------------- */
@@ -262,9 +262,9 @@ mem_init:
/* FIXME: we use async mode for now */
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
/* Step 4a: assert MDREFR:K?RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
@@ -277,16 +277,16 @@ mem_init:
bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4c: assert MDREFR:E1PIN and E0PIO */
orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
@@ -295,8 +295,8 @@ mem_init:
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
@@ -345,8 +345,8 @@ mem_init:
/* Step 4h: Write MDMRS. */
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
/* We are finished with Intel's memory controller initialisation */
@@ -357,17 +357,17 @@ mem_init:
initirqs:
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* Clock initialisation */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
initclks:
@@ -376,34 +376,34 @@ initclks:
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
/* enable the 32Khz oscillator for RTC and PowerManager */
/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
*/
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
/* ---------------------------------------------------------------- */
/* */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
@@ -428,11 +428,10 @@ initclks:
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* End memsetup */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
endmemsetup:
mov pc, lr
-
diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds
index 46beb152c77..1130013d361 100644
--- a/board/innokom/u-boot.lds
+++ b/board/innokom/u-boot.lds
@@ -26,29 +26,33 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = 0x00000000;
- . = ALIGN(4);
+ . = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
- . = ALIGN(4);
- .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
+ . = ALIGN(4);
+ .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
armboot_end_data = .;
- . = ALIGN(4);
+ . = ALIGN(4);
bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) }
bss_end = .;
armboot_end = .;
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-10 00:07:34 +0000