summaryrefslogtreecommitdiff
path: root/board/mpl
diff options
context:
space:
mode:
Diffstat (limited to 'board/mpl')
-rw-r--r--board/mpl/common/pci.c40
-rw-r--r--board/mpl/mip405/mip405.c15
2 files changed, 47 insertions, 8 deletions
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
index a26f542eb3..692930b416 100644
--- a/board/mpl/common/pci.c
+++ b/board/mpl/common/pci.c
@@ -65,21 +65,22 @@ void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char int_line = 0xff;
+ unsigned char pin;
/*
* Write pci interrupt line register
*/
if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
return;
- if(PCI_FUNC(dev)==0)
- {
- /* assuming all function 0 are using their INTA# Pin*/
- int_line=PCI_IRQ_VECTOR(dev);
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
+ if ((pin == 0) || (pin > 4))
+ return;
+
+ int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
#ifdef DEBUG
- printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
- PCI_DEV(dev),dev,int_line,int_line);
+ printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
+ PCI_DEV(dev),dev,int_line,int_line);
#endif
- }
}
extern void pci_405gp_init(struct pci_controller *hose);
@@ -90,11 +91,34 @@ static struct pci_controller hose = {
fixup_irq: pci_pip405_fixup_irq,
};
+
+static void reloc_pci_cfg_table(struct pci_config_table *table)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned long addr;
+
+ for (; table && table->vendor; table++) {
+ addr = (ulong) (table->config_device) + gd->reloc_off;
+#ifdef DEBUG
+ printf ("device \"%d\": 0x%08lx => 0x%08lx\n",
+ table->device, (ulong) (table->config_device), addr);
+#endif
+ table->config_device =
+ (void (*)(struct pci_controller* hose, pci_dev_t dev,
+ struct pci_config_table *))addr;
+ table->priv[0]+=gd->reloc_off;
+ }
+}
+
void pci_init_board(void)
{
/*we want the ptrs to RAM not flash (ie don't use init list)*/
hose.fixup_irq = pci_pip405_fixup_irq;
hose.config_table = pci_pip405_config_table;
+ reloc_pci_cfg_table(hose.config_table);
+#ifdef DEBUG
+ printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
+#endif
pci_405gp_init(&hose);
}
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 8bab47c107..95ad97c589 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -128,6 +128,15 @@ const sdram_t sdram_table[] = {
2, /* Address Mode = 2 */
4, /* size value */
1}, /* ECC enabled */
+ { 0x03, /* Rev A, 128MByte -4 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 3, /* Address Mode = 3 */
+ 5, /* size value */
+ 1}, /* ECC enabled */
{ 0xff, /* terminator */
0xff,
0xff,
@@ -616,9 +625,15 @@ void print_mip405_rev (void)
int last_stage_init (void)
{
+ /* write correct LED configuration */
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
printf ("Error writing to the PHY\n");
}
+ /* since LED/CFG2 is not connected on the -2,
+ * write to correct capability information */
+ if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
+ printf ("Error writing to the PHY\n");
+ }
print_mip405_rev ();
show_stdio_dev ();
check_env ();