diff options
Diffstat (limited to 'board/nx823/nx823.c')
| -rw-r--r-- | board/nx823/nx823.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c index 18840ff48f2..df9aaab7a7a 100644 --- a/board/nx823/nx823.c +++ b/board/nx823/nx823.c @@ -159,7 +159,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1, size8, size9; @@ -170,22 +170,22 @@ phys_size_t initdram (int board_type) * Up to 2 Banks of 64Mbit x 2 devices * Initial builds only have 1 */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; /* * Map controller SDRAM bank 0 */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* * Map controller SDRAM bank 1 */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; /* * Perform SDRAM initializsation sequence @@ -209,7 +209,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -219,7 +219,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -227,7 +227,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -235,7 +235,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -258,7 +258,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -268,9 +268,9 @@ phys_size_t initdram (int board_type) if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* @@ -278,9 +278,9 @@ phys_size_t initdram (int board_type) */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; + CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { @@ -295,16 +295,16 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* @@ -312,9 +312,9 @@ phys_size_t initdram (int board_type) */ memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; + CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { @@ -329,7 +329,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -352,7 +352,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -387,7 +387,7 @@ void load_sernum_ethaddr (void) bd_t *bd = gd->bd; for (i = 0; i < 8; i++) { - bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i); + bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); } bd->bi_enetaddr[0] = 0x10; bd->bi_enetaddr[1] = 0x20; |