diff options
Diffstat (limited to 'board/phytec')
33 files changed, 1348 insertions, 190 deletions
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..f394ace786a 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -4,6 +4,13 @@ config PHYTEC_SOM_DETECTION help Support of I2C EEPROM based SoM detection. +config PHYTEC_SOM_DETECTION_BLOCKS + bool "Extend SoM detection with block support" + depends on PHYTEC_SOM_DETECTION + help + Extend the I2C EEPROM based SoM detection with API v3. This API + introduces blocks with different payloads. + config PHYTEC_IMX8M_SOM_DETECTION bool "Support SoM detection for i.MX8M PHYTEC platforms" depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION @@ -16,6 +23,8 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +34,8 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + select PHYTEC_SOM_DETECTION_BLOCKS + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 3feb00fd1ec..04469d0a924 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -7,6 +7,6 @@ ifdef CONFIG_SPL_BUILD obj- := __dummy__.o endif -obj-y += phytec_som_detection.o -obj-$(CONFIG_ARCH_K3) += am6_som_detection.o +obj-y += phytec_som_detection.o phytec_som_detection_blocks.o +obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c index 2e9884dab44..7930ab42d1c 100644 --- a/board/phytec/common/am6_som_detection.c +++ b/board/phytec/common/am6_som_detection.c @@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data, u8 option) * - The size * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { u8 ddr_id = phytec_check_opt(data, 3); @@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) * - Otherwise a board depended code for the size. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { u8 spi = phytec_check_opt(data, 5); @@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) * - 0x1 if 10/100/1000 MBit Phy is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { u8 eth = phytec_check_opt(data, 6); @@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) * - 1 if it is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { u8 rtc = phytec_check_opt(data, 7); @@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) #else -inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data) +inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data) { return -1; } inline u8 __maybe_unused -phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h index 032f9da3aab..c5c6e179da6 100644 --- a/board/phytec/common/am6_som_detection.h +++ b/board/phytec/common/am6_som_detection.h @@ -9,11 +9,19 @@ #include "phytec_som_detection.h" +#define EEPROM_ADDR 0x50 #define PHYTEC_AM62X_SOM 71 #define PHYTEC_AM64X_SOM 72 #define PHYTEC_EEPROM_VALUE_X 0x21 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC +enum { + EEPROM_RAM_SIZE_512MB = 0, + EEPROM_RAM_SIZE_1GB = 1, + EEPROM_RAM_SIZE_2GB = 2, + EEPROM_RAM_SIZE_4GB = 4 +}; + int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data); diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c index ee34a5b9579..bfd60ffb777 100644 --- a/board/phytec/common/imx8m_som_detection.c +++ b/board/phytec/common/imx8m_som_detection.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet <t.remmet@phytec.de> */ -#include <common.h> #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile new file mode 100644 index 00000000000..40e91a43e99 --- /dev/null +++ b/board/phytec/common/k3/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ +obj-y += board.o +obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c new file mode 100644 index 00000000000..3d7e090ccaa --- /dev/null +++ b/board/phytec/common/k3/board.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#include <env_internal.h> +#include <fdt_support.h> +#include <spl.h> +#include <asm/arch/hardware.h> + +#include "../am6_som_detection.h" + +#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) +int mmc_get_env_dev(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return 0; + case BOOT_DEVICE_MMC2: + return 1; + }; + + return CONFIG_SYS_MMC_ENV_DEV; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 boot_device = get_boot_device(); + + if (prio) + return ENVL_UNKNOWN; + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + case BOOT_DEVICE_SPI: + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + default: + return ENVL_NOWHERE; + }; +} + +#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + env_set_ulong("mmcdev", 0); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_MMC2: + env_set_ulong("mmcdev", 1); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_SPI: + env_set("boot", "spi"); + break; + case BOOT_DEVICE_ETHERNET: + env_set("boot", "net"); + break; + }; + + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return 0; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); + } + } + } + + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + fdt_copy_fixed_partitions(blob); + + return 0; +} +#endif diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c new file mode 100644 index 00000000000..39f7be8dc92 --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#include "k3_ddrss_patch.h" + +#include <fdt_support.h> +#include <linux/errno.h> + +#ifdef CONFIG_K3_AM64_DDRSS +#define LPDDR4_INTR_CTL_REG_COUNT (423U) +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) +#endif + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss) +{ + int i, j; + int ret; + int mem_offset; + + mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000"); + if (mem_offset < 0) + return -ENODEV; + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + for (j = 0; j < ddrss->ctl_regs_num; j++) + if (i == ddrss->ctl_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,ctl-data", i, + ddrss->ctl_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->pi_regs_num; j++) + if (i == ddrss->pi_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,pi-data", i, + ddrss->pi_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->phy_regs_num; j++) + if (i == ddrss->phy_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,phy-data", i, + ddrss->phy_regs[j].val); + if (ret) + return ret; + } + + return 0; +} diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h new file mode 100644 index 00000000000..0a47c85116a --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef K3_DDRSS_PATCH +#define K3_DDRSS_PATCH + +#include <linux/types.h> + +struct ddr_reg { + u32 off; + u32 val; +}; + +struct ddrss { + struct ddr_reg *ctl_regs; + u32 ctl_regs_num; + struct ddr_reg *pi_regs; + u32 pi_regs_num; + struct ddr_reg *phy_regs; + u32 phy_regs_num; +}; + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss); + +#endif /* K3_DDRSS_PATCH */ diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 78c173df20d..166c3eae565 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet <t.remmet@phytec.de> */ -#include <common.h> #include <dm/device.h> #include <dm/uclass.h> #include <i2c.h> @@ -48,16 +47,9 @@ int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, return ret; } -int phytec_eeprom_data_init(struct phytec_eeprom_data *data, - int bus_num, int addr) +int phytec_eeprom_read(u8 *data, int bus_num, int addr, int size, int offset) { - int ret, i; - unsigned int crc; - u8 *ptr; - const unsigned int payload_size = sizeof(struct phytec_eeprom_payload); - - if (!data) - data = &eeprom_data; + int ret; #if CONFIG_IS_ENABLED(DM_I2C) struct udevice *dev; @@ -65,19 +57,182 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); if (ret) { pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); - goto err; + return ret; } - ret = dm_i2c_read(dev, 0, (uint8_t *)data, payload_size); + ret = dm_i2c_read(dev, offset, (uint8_t *)data, size); if (ret) { pr_err("%s: Unable to read EEPROM data: %i\n", __func__, ret); - goto err; + return ret; } #else i2c_set_bus_num(bus_num); - ret = i2c_read(addr, 0, 2, (uint8_t *)data, - sizeof(struct phytec_eeprom_data)); + ret = i2c_read(addr, offset, 2, (uint8_t *)data, size); #endif + return ret; +} + +int phytec_eeprom_data_init_v2(struct phytec_eeprom_data *data) +{ + unsigned int crc; + + if (!data) + return -1; + + crc = crc8(0, (const unsigned char *)&data->payload, PHYTEC_API2_DATA_LEN); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", + __func__); + return -EINVAL; + } + + return 0; +} + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +int phytec_eeprom_data_init_v3_block(struct phytec_eeprom_data *data, + struct phytec_api3_block_header *header, + u8 *payload) +{ + struct phytec_api3_element *element = NULL; + struct phytec_api3_element *list_iterator; + + if (!header) + return -1; + if (!payload) + return -1; + + debug("%s: block type: %i\n", __func__, header->block_type); + switch (header->block_type) { + case PHYTEC_API3_BLOCK_MAC: + element = phytec_blocks_init_mac(header, payload); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + header->block_type); + } + if (!element) + return -1; + + if (!data->payload.block_head) { + data->payload.block_head = element; + return 0; + } + + list_iterator = data->payload.block_head; + while (list_iterator && list_iterator->next) + list_iterator = list_iterator->next; + list_iterator->next = element; + + return 0; +} + +int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + struct phytec_api3_header header; + unsigned int crc; + u8 *payload; + int block_addr; + struct phytec_api3_block_header *block_header; + + if (!data) + return -1; + + ret = phytec_eeprom_read((uint8_t *)&header, bus_num, addr, + PHYTEC_API3_DATA_HEADER_LEN, + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data header.\n", __func__); + goto err; + } + + crc = crc8(0, (const unsigned char *)&header, + PHYTEC_API3_DATA_HEADER_LEN); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 header is unusable.\n", + __func__); + goto err; + } + + debug("%s: data length: %i\n", __func__, header.data_length); + payload = malloc(header.data_length); + if (!payload) { + pr_err("%s: Unable to allocate memory\n", __func__); + goto err_payload; + } + + ret = phytec_eeprom_read(payload, bus_num, addr, header.data_length, + PHYTEC_API3_DATA_HEADER_LEN + + PHYTEC_API2_DATA_LEN); + if (ret) { + pr_err("%s: Failed to read API v3 data payload.\n", __func__); + goto err_payload; + } + + block_addr = 0; + debug("%s: block count: %i\n", __func__, header.block_count); + for (i = 0; i < header.block_count; i++) { + debug("%s: block_addr: %i\n", __func__, block_addr); + block_header = (struct phytec_api3_block_header *) + &payload[block_addr]; + crc = crc8(0, (const unsigned char *)block_header, + PHYTEC_API3_BLOCK_HEADER_LEN); + + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block header is unusable\n", + __func__); + goto err_payload; + } + + ret = phytec_eeprom_data_init_v3_block(data, block_header, + &payload[block_addr + PHYTEC_API3_BLOCK_HEADER_LEN]); + /* Ignore failed block initialization and continue. */ + if (ret) + debug("%s: Unable to create block with index %i.\n", + __func__, i); + + block_addr = block_header->next_block; + } + + free(payload); + return 0; +err_payload: + free(payload); +err: + return -1; +} + +#else + +inline int phytec_eeprom_data_init_v3(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return 0; +} + +#endif + +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + u8 *ptr; + + if (!data) + data = &eeprom_data; + + ret = phytec_eeprom_read((u8 *)data, bus_num, addr, + PHYTEC_API2_DATA_LEN, 0); + if (ret) + goto err; + data->payload.block_head = NULL; if (data->payload.api_rev == 0xff) { pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); @@ -86,31 +241,28 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, } ptr = (u8 *)data; - for (i = 0; i < payload_size; ++i) + for (i = 0; i < PHYTEC_API2_DATA_LEN; ++i) if (ptr[i] != 0x0) break; - if (i == payload_size) { + if (i == PHYTEC_API2_DATA_LEN) { pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); ret = -EINVAL; goto err; } - /* We are done here for early revisions */ - if (data->payload.api_rev <= PHYTEC_API_REV1) { - data->valid = true; - return 0; + if (data->payload.api_rev >= PHYTEC_API_REV2) { + ret = phytec_eeprom_data_init_v2(data); + if (ret) + goto err; } - crc = crc8(0, (const unsigned char *)&data->payload, payload_size); - debug("%s: crc: %x\n", __func__, crc); - - if (crc) { - pr_err("%s: CRC mismatch. EEPROM data is not usable.\n", - __func__); - ret = -EINVAL; - goto err; - } + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + if (data->payload.api_rev >= PHYTEC_API_REV3) { + ret = phytec_eeprom_data_init_v3(data, bus_num, addr); + if (ret) + goto err; + } data->valid = true; return 0; @@ -249,6 +401,17 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, } #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data) +{ + if (!data) + data = &eeprom_data; + if (!data->valid) + return NULL; + + return data->payload.block_head; +} + #else inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, @@ -289,6 +452,12 @@ u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) return PHYTEC_EEPROM_INVAL; } +inline struct phytec_api3_element * __maybe_unused + phytec_get_block_head(struct phytec_eeprom_data *data) +{ + return NULL; +} + #if IS_ENABLED(CONFIG_CMD_EXTENSION) inline struct extension *phytec_add_extension(const char *name, const char *overlay, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 0ad5c14ef4e..5e35a13cb21 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -7,9 +7,13 @@ #ifndef _PHYTEC_SOM_DETECTION_H #define _PHYTEC_SOM_DETECTION_H +#include "phytec_som_detection_blocks.h" + #define PHYTEC_MAX_OPTIONS 17 #define PHYTEC_EEPROM_INVAL 0xff +#define PHYTEC_API2_DATA_LEN 32 + #define PHYTEC_GET_OPTION(option) \ (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') @@ -17,6 +21,7 @@ enum { PHYTEC_API_REV0 = 0, PHYTEC_API_REV1, PHYTEC_API_REV2, + PHYTEC_API_REV3, }; enum phytec_som_type_str { @@ -61,6 +66,7 @@ struct phytec_eeprom_payload { struct phytec_api0_data data_api0; struct phytec_api2_data data_api2; } data; + struct phytec_api3_element *block_head; } __packed; struct phytec_eeprom_data { @@ -86,4 +92,7 @@ struct extension *phytec_add_extension(const char *name, const char *overlay, const char *other); #endif /* IS_ENABLED(CONFIG_CMD_EXTENSION) */ +struct phytec_api3_element * + __maybe_unused phytec_get_block_head(struct phytec_eeprom_data *data); + #endif /* _PHYTEC_SOM_DETECTION_H */ diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c new file mode 100644 index 00000000000..5f3c27ef0c2 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +#include <malloc.h> +#include <u-boot/crc.h> +#include <net.h> +#include <vsprintf.h> + +#include "phytec_som_detection_blocks.h" + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS) + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + struct phytec_api3_element *element; + struct phytec_api3_block_mac *mac; + unsigned int crc; + unsigned int len = sizeof(struct phytec_api3_block_mac); + + if (!header) + return NULL; + if (!payload) + return NULL; + + element = (struct phytec_api3_element *) + calloc(8, PHYTEC_API3_ELEMENT_HEADER_SIZE + len); + if (!element) { + pr_err("%s: Unable to allocate memory\n", __func__); + return NULL; + } + element->block_type = header->block_type; + memcpy(&element->block.mac, payload, len); + mac = &element->block.mac; + + debug("%s: interface: %i\n", __func__, mac->interface); + debug("%s: MAC %pM\n", __func__, mac->address); + + crc = crc8(0, (const unsigned char *)mac, len); + debug("%s: crc: %x\n", __func__, crc); + if (crc) { + pr_err("%s: CRC mismatch. API3 block payload is unusable\n", + __func__); + return NULL; + } + + return element; +} + +int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + char enetenv[9] = "ethaddr"; + char buf[ARP_HLEN_ASCII + 1]; + struct phytec_api3_block_mac *block = &element->block.mac; + int ret; + + if (!is_valid_ethaddr(block->address)) { + pr_err("%s: Invalid MAC address in block.\n", __func__); + return -1; + } + + if (block->interface > 0) { + ret = sprintf(enetenv, "eth%iaddr", block->interface); + if (ret != 8) { + pr_err("%s: Unable to create env string\n", __func__); + return -1; + } + } + + ret = sprintf(buf, "%pM", block->address); + if (ret != ARP_HLEN_ASCII) { + pr_err("%s: Unable to convert MAC address\n", __func__); + return -1; + } + ret = env_set(enetenv, buf); + if (ret) { + pr_err("%s: Failed to set MAC address to env.\n", __func__); + return -1; + } + + debug("%s: Added %s to %s\n", __func__, buf, enetenv); + return 0; +} + +#else + +inline struct phytec_api3_element * + phytec_api3_init_mac_block(struct phytec_api3_block_header *header, + uint8_t *payload) +{ + return NULL; +} + +inline int __maybe_unused + phytec_blocks_add_mac_to_env(struct phytec_api3_element *element) +{ + return -1; +} + +#endif diff --git a/board/phytec/common/phytec_som_detection_blocks.h b/board/phytec/common/phytec_som_detection_blocks.h new file mode 100644 index 00000000000..2a5a83c9039 --- /dev/null +++ b/board/phytec/common/phytec_som_detection_blocks.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +#ifndef _PHYTEC_SOM_DETECTION_BLOCKS_H +#define _PHYTEC_SOM_DETECTION_BLOCKS_H + +#define PHYTEC_API3_DATA_HEADER_LEN 8 +#define PHYTEC_API3_BLOCK_HEADER_LEN 4 +#define PHYTEC_API3_PAYLOAD_START \ + (PHYTEC_API2_DATA_LEN + PHYTEC_API3_DATA_HEADER_LEN) + +#define PHYTEC_API3_ELEMENT_HEADER_SIZE \ + (sizeof(struct phytec_api3_element *) + \ + sizeof(enum phytec_api3_block_types)) + +#define PHYTEC_API3_FOREACH_BLOCK(elem, data) \ + for (elem = phytec_get_block_head(data); elem; elem = elem->next) + +struct phytec_api3_header { + u16 data_length; /* Total length in Bytes of all blocks */ + u8 block_count; /* Number of blocks */ + u8 sub_version; /* Block specification version */ + u8 reserved[3]; /* Reserved */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_block_header { + u8 block_type; /* Block payload identifier */ + u16 next_block; /* Address of the next block */ + u8 crc8; /* checksum */ +} __packed; + +enum phytec_api3_block_types { + PHYTEC_API3_BLOCK_MAC = 0, +}; + +struct phytec_api3_block_mac { + u8 interface; /* Ethernet interface number */ + u8 address[6]; /* MAC-Address */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_api3_element { + struct phytec_api3_element *next; + enum phytec_api3_block_types block_type; + union { + struct phytec_api3_block_mac mac; + } block; +} __packed; + +struct phytec_api3_element * + phytec_blocks_init_mac(struct phytec_api3_block_header *header, + uint8_t *payload); + +int __maybe_unused +phytec_blocks_add_mac_to_env(struct phytec_api3_element *element); + +#endif /* _PHYTEC_SOM_DETECTION_BLOCKS_H */ diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b6d459fdfce..b98c46dbcbd 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -6,7 +6,7 @@ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> */ -#include <common.h> +#include <config.h> #include <init.h> #include <spl.h> #include <asm/arch/clock.h> diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 0f7235979b0..20f2aac332d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -6,7 +6,6 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index b37c6fe218d..ecc5b75d8d4 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -9,7 +9,6 @@ * Both NAND and eMMC cannot be set because they share the * same pins (SD4) */ -#include <common.h> #include <init.h> #include <net.h> #include <asm/arch/crm_regs.h> diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index 5700effbd3f..2022525651d 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -10,7 +10,7 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include <common.h> +#include <config.h> #include <init.h> #include <spl.h> #include <asm/arch/cpu.h> diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c index 7091c985ba1..bb1c48da0fe 100644 --- a/board/phytec/phycore_am335x_r2/mux.c +++ b/board/phytec/phycore_am335x_r2/mux.c @@ -6,7 +6,6 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include <common.h> #include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> #include <asm/arch/mux.h> diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index 1de8850c6c4..7c179ef0078 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -35,3 +35,33 @@ config SPL_LDSCRIPT source "board/phytec/common/Kconfig" endif + +config PHYCORE_AM62X_RAM_SIZE_FIX + bool "Set phyCORE-AM62x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-AM62x RAM size" + depends on PHYCORE_AM62X_RAM_SIZE_FIX + default PHYCORE_AM62X_RAM_SIZE_2GB + +config PHYCORE_AM62X_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM62x. + +config PHYCORE_AM62X_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-AM62x. + +endchoice diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 02ac88e58a4..42463ad054e 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -11,3 +11,4 @@ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst +F: board/phytec/common/k3 diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 618b4c370d1..9f6bc736cbb 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -4,12 +4,17 @@ * Author: Wadim Egorov <w.egorov@phytec.de> */ +#include <asm/arch/hardware.h> #include <asm/io.h> -#include <env.h> -#include <env_internal.h> #include <spl.h> #include <fdt_support.h> -#include <asm/arch/hardware.h> + +#include "phycore-ddr-data.h" +#include "../common/k3/k3_ddrss_patch.h" +#include "../common/am6_som_detection.h" + +#define AM64_DDRSS_SS_BASE 0x0F300000 +#define DDRSS_V2A_CTL_REG 0x0020 DECLARE_GLOBAL_DATA_PTR; @@ -18,15 +23,184 @@ int board_init(void) return 0; } +static u8 phytec_get_am62_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB)) + return EEPROM_RAM_SIZE_4GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am62_ddr_size_default(); + + /* + * HACK: ddrss driver support 2GB RAM by default + * V2A_CTL_REG should be updated to support other RAM size + */ + if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) + if (ram_size == EEPROM_RAM_SIZE_4GB) + writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + case EEPROM_RAM_SIZE_4GB: +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + return gd->ram_top; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + case EEPROM_RAM_SIZE_4GB: + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR upper region */ + gd->bd->bi_dram[1].start = 0x880000000; + gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; +#endif + break; + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; +} + +#if defined(CONFIG_K3_DDRSS) +int update_ddrss_timings(void) +{ + int ret; + u8 ram_size; + struct ddrss *ddr_patch = NULL; + void *fdt = (void *)gd->fdt_blob; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_1GB]; + break; + case EEPROM_RAM_SIZE_2GB: + ddr_patch = NULL; + break; + case EEPROM_RAM_SIZE_4GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_4GB]; + break; + default: + break; + } + + /* Nothing to patch */ + if (!ddr_patch) + return 0; + + debug("Applying DDRSS timings patch for ram_size %d\n", ram_size); + + ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch); + if (ret < 0) { + printf("Failed to apply ddrs timings patch %d\n", ret); + return ret; + } + + return 0; +} + +int do_board_detect(void) +{ + return update_ddrss_timings(); } +#endif + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 @@ -57,67 +231,3 @@ void spl_board_init(void) MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); } #endif - -#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) -int mmc_get_env_dev(void) -{ - u32 boot_device = get_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - return 0; - case BOOT_DEVICE_MMC2: - return 1; - }; - - return CONFIG_SYS_MMC_ENV_DEV; -} -#endif - -enum env_location env_get_location(enum env_operation op, int prio) -{ - u32 boot_device = get_boot_device(); - - if (prio) - return ENVL_UNKNOWN; - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) - return ENVL_FAT; - if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) - return ENVL_MMC; - case BOOT_DEVICE_SPI: - if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) - return ENVL_SPI_FLASH; - default: - return ENVL_NOWHERE; - }; -} - -#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) -int board_late_init(void) -{ - u32 boot_device = get_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - env_set_ulong("mmcdev", 0); - env_set("boot", "mmc"); - break; - case BOOT_DEVICE_MMC2: - env_set_ulong("mmcdev", 1); - env_set("boot", "mmc"); - break; - case BOOT_DEVICE_SPI: - env_set("boot", "spi"); - break; - case BOOT_DEVICE_ETHERNET: - env_set("boot", "net"); - break; - }; - - return 0; -} -#endif diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h new file mode 100644 index 00000000000..fe6eccd959e --- /dev/null +++ b/board/phytec/phycore_am62x/phycore-ddr-data.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef PHYCORE_DDR_DATA +#define PHYCORE_DDR_DATA + +#include "../common/k3/k3_ddrss_patch.h" + +/* 1 GB variant delta */ +struct ddr_reg ddr_1gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x01010000 }, + { 318, 0x3FFF0000 }, + { 327, 0x00000C01 }, + { 328, 0x00000000 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_1gb_pi_regs[] = { + { 77, 0x04000100 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_1gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +/* 4 GB variant delta */ +struct ddr_reg ddr_4gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x00000000 }, + { 318, 0x7FFF0000 }, + { 327, 0x01000C01 }, + { 328, 0x00000001 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_4gb_pi_regs[] = { + { 77, 0x04000000 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_4gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +enum { + PHYCORE_1GB, + PHYCORE_4GB, +}; + +struct ddrss phycore_ddrss_data[] = { + [PHYCORE_1GB] = { + .ctl_regs = &ddr_1gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs), + .pi_regs = &ddr_1gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs), + .phy_regs = &ddr_1gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs), + }, + [PHYCORE_4GB] = { + .ctl_regs = &ddr_4gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs), + .pi_regs = &ddr_4gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs), + .phy_regs = &ddr_4gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs), + }, +}; + +#endif /* PHYCORE_DDR_DATA */ diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index ada3a9233be..42db26a5990 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -1,3 +1,5 @@ +#include <env/ti/k3_dfu.env> + fdtaddr=0x88000000 loadaddr=0x82000000 scriptaddr=0x80000000 diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS index e46e3691bac..58c5e2d0af9 100644 --- a/board/phytec/phycore_imx8mm/MAINTAINERS +++ b/board/phytec/phycore_imx8mm/MAINTAINERS @@ -2,10 +2,7 @@ phyCORE-i.MX8M Mini M: Teresa Remmet <t.remmet@phytec.de> W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/ S: Maintained -F: arch/arm/dts/imx8mm-phyboard-polis-rdk.dts -F: arch/arm/dts/imx8mm-phycore-som.dtsi F: arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi -F: arch/arm/dts/imx8mm-phygate-tauri-l.dts F: arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi F: board/phytec/phycore_imx8mm/ F: configs/imx8mm-phygate-tauri-l_defconfig diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index ef647291690..06cffbca3a6 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet <t.remmet@phytec.de> */ -#include <common.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 690a51f7a72..8d858590a39 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet <t.remmet@phytec.de> */ -#include <common.h> #include <asm/arch/clock.h> #include <asm/arch/ddr.h> #include <asm/arch/imx8mm_pins.h> diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index f846d10bad9..bdf9e97beaa 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,5 +12,72 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +config PHYCORE_IMX8MP_RAM_SIZE_FIX + bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM size" + depends on PHYCORE_IMX8MP_RAM_SIZE_FIX + default PHYCORE_IMX8MP_RAM_SIZE_2GB + +config PHYCORE_IMX8MP_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-i.MX8MP. + RAM frequency is configured independent. + +config PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "8GB RAM" + select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + help + Set RAM size fix to 8GB for phyCORE-i.MX8MP. + Only 2GHz RAMs are supported. + +endchoice + +config PHYCORE_IMX8MP_RAM_FREQ_FIX + bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting" + default false + help + RAM frequency is automatic being detected with the help of + the EEPROM introspection data. Set RAM frequency to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MP RAM frequency" + depends on PHYCORE_IMX8MP_RAM_FREQ_FIX + default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + +config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS + bool "Use 2GHz RAM timings" + help + Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of + 1.5GHz timings. + +config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS + depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB + bool "Use 1.5GHz RAM timings" + help + Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of + 2GHz timings. +endchoice + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/MAINTAINERS b/board/phytec/phycore_imx8mp/MAINTAINERS index d3beb978d3a..645476ae30a 100644 --- a/board/phytec/phycore_imx8mp/MAINTAINERS +++ b/board/phytec/phycore_imx8mp/MAINTAINERS @@ -2,7 +2,6 @@ phyCORE-i.MX8M Plus M: Teresa Remmet <t.remmet@phytec.de> W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/ S: Maintained -F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi F: board/phytec/phycore_imx8mp/ F: configs/phycore-imx8mp_defconfig diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index f2707b85960..9984b6c2601 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -1839,3 +1839,156 @@ struct dram_timing_info dram_timing = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +void set_dram_timings_2ghz_2gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1323; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; +} + +void set_dram_timings_1_5ghz_1gb(void) +{ + dram_timing.ddrc_cfg[3].val = 0x1233; + dram_timing.ddrc_cfg[5].val = 0x5b0087; + dram_timing.ddrc_cfg[6].val = 0x61027f10; + dram_timing.ddrc_cfg[7].val = 0x7b0; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[23].val = 0x8d; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[59].val = 0x1031; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[84].val = 0x1031; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf32d; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf32d; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf32d; +} + +void set_dram_timings_2ghz_1gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[5].val = 0x7a00b4; + dram_timing.ddrc_cfg[23].val = 0xbc; + dram_timing.ddrc_cfg[45].val = 0xf070707; + dram_timing.ddrc_cfg[62].val = 0xc0012; + dram_timing.ddrc_cfg[77].val = 0x13; + dram_timing.ddrc_cfg[87].val = 0x30005; + dram_timing.ddrc_cfg[102].val = 0x5; +} + +void set_dram_timings_1_5ghz_4gb(void) +{ + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_4gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[39].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} + +void set_dram_timings_2ghz_8gb(void) +{ + set_dram_timings_2ghz_2gb(); + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[5].val = 0x7a017c; + dram_timing.ddrc_cfg[23].val = 0x184; + dram_timing.ddrc_cfg[39].val = 0x18; + dram_timing.ddrc_cfg[46].val = 0xf07; + dram_timing.ddrc_cfg[62].val = 0xc0026; + dram_timing.ddrc_cfg[77].val = 0x27; + dram_timing.ddrc_cfg[87].val = 0x3000a; + dram_timing.ddrc_cfg[102].val = 0xa; + + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x3; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; +} diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.h b/board/phytec/phycore_imx8mp/lpddr4_timing.h new file mode 100644 index 00000000000..1c10e085a92 --- /dev/null +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void set_dram_timings_2ghz_2gb(void); +void set_dram_timings_2ghz_1gb(void); +void set_dram_timings_2ghz_4gb(void); +void set_dram_timings_1_5ghz_1gb(void); +void set_dram_timings_1_5ghz_4gb(void); +void set_dram_timings_2ghz_8gb(void); + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index dbdd6bb7937..ef951361844 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -4,12 +4,12 @@ * Author: Teresa Remmet <t.remmet@phytec.de> */ -#include <common.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> +#include <init.h> #include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,3 +56,13 @@ int board_late_init(void) return 0; } + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index df158024654..0610d8bbd0b 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -4,7 +4,6 @@ * Author: Teresa Remmet <t.remmet@phytec.de> */ -#include <common.h> #include <asm/arch/clock.h> #include <asm/arch/ddr.h> #include <asm/arch/imx8mp_pins.h> @@ -21,95 +20,103 @@ #include <power/pca9450.h> #include <spl.h> +#include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" DECLARE_GLOBAL_DATA_PTR; -#define EEPROM_ADDR 0x51 -#define EEPROM_ADDR_FALLBACK 0x59 +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; } +enum phytec_imx8mp_ddr_eeprom_code { + PHYTEC_IMX8MP_DDR_1GB = 2, + PHYTEC_IMX8MP_DDR_2GB = 3, + PHYTEC_IMX8MP_DDR_4GB = 5, + PHYTEC_IMX8MP_DDR_8GB = 7, + PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8, +}; + void spl_dram_init(void) { int ret; + bool use_2ghz_timings = false; + enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL; ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); - if (ret) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) goto out; ret = phytec_imx8m_detect(NULL); if (!ret) phytec_print_som_info(NULL); - u8 rev = phytec_get_rev(NULL); - u8 somtype = phytec_get_som_type(NULL); - - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) { - dram_timing.ddrc_cfg[3].val = 0x1323; - dram_timing.ddrc_cfg[4].val = 0x1e84800; - dram_timing.ddrc_cfg[5].val = 0x7a0118; - dram_timing.ddrc_cfg[8].val = 0xc00307a3; - dram_timing.ddrc_cfg[9].val = 0xc50000; - dram_timing.ddrc_cfg[10].val = 0xf4003f; - dram_timing.ddrc_cfg[11].val = 0xf30000; - dram_timing.ddrc_cfg[14].val = 0x2028222a; - dram_timing.ddrc_cfg[15].val = 0x8083f; - dram_timing.ddrc_cfg[16].val = 0xe0e000; - dram_timing.ddrc_cfg[17].val = 0x12040a12; - dram_timing.ddrc_cfg[18].val = 0x2050f0f; - dram_timing.ddrc_cfg[19].val = 0x1010009; - dram_timing.ddrc_cfg[20].val = 0x502; - dram_timing.ddrc_cfg[21].val = 0x20800; - dram_timing.ddrc_cfg[22].val = 0xe100002; - dram_timing.ddrc_cfg[23].val = 0x120; - dram_timing.ddrc_cfg[24].val = 0xc80064; - dram_timing.ddrc_cfg[25].val = 0x3e8001e; - dram_timing.ddrc_cfg[26].val = 0x3207a12; - dram_timing.ddrc_cfg[28].val = 0x4a3820e; - dram_timing.ddrc_cfg[30].val = 0x230e; - dram_timing.ddrc_cfg[37].val = 0x799; - dram_timing.ddrc_cfg[38].val = 0x9141d1c; - dram_timing.ddrc_cfg[74].val = 0x302; - dram_timing.ddrc_cfg[83].val = 0x599; - dram_timing.ddrc_cfg[99].val = 0x302; - dram_timing.ddrc_cfg[108].val = 0x599; - dram_timing.ddrphy_cfg[66].val = 0x18; - dram_timing.ddrphy_cfg[75].val = 0x1e3; - dram_timing.ddrphy_cfg[77].val = 0x1e3; - dram_timing.ddrphy_cfg[79].val = 0x1e3; - dram_timing.ddrphy_cfg[145].val = 0x3e8; - dram_timing.fsp_msg[0].drate = 4000; - dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; - dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; - dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; - dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; - dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; - dram_timing.fsp_msg[3].drate = 4000; - dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; - dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; - dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; - dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; - dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; - dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; - dram_timing.ddrphy_pie[480].val = 0x465; - dram_timing.ddrphy_pie[481].val = 0xfa; - dram_timing.ddrphy_pie[482].val = 0x9c4; - dram_timing.fsp_table[0] = 4000; + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB)) + size = PHYTEC_IMX8MP_DDR_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB)) + size = PHYTEC_IMX8MP_DDR_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB)) + size = PHYTEC_IMX8MP_DDR_4GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) + size = PHYTEC_IMX8MP_DDR_8GB; + } else { + size = phytec_get_imx8m_ddr_size(NULL); + } + + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB) + size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; + else + use_2ghz_timings = true; + } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ) + size = PHYTEC_IMX8MP_DDR_4GB; + else + use_2ghz_timings = false; + } + } else { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && + (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; } + switch (size) { + case PHYTEC_IMX8MP_DDR_1GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_1gb(); + else + set_dram_timings_1_5ghz_1gb(); + break; + case PHYTEC_IMX8MP_DDR_2GB: + if (use_2ghz_timings) + set_dram_timings_2ghz_2gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB: + set_dram_timings_1_5ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_4GB_2GHZ: + set_dram_timings_2ghz_4gb(); + break; + case PHYTEC_IMX8MP_DDR_8GB: + set_dram_timings_2ghz_8gb(); + break; + default: + goto out; + } + ddr_init(&dram_timing); + return; out: + printf("Could not detect correct RAM size. Fallback to default.\n"); ddr_init(&dram_timing); } diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index 3f49f39e3d5..a970634b4c3 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -4,13 +4,11 @@ * Author: Wadim Egorov <w.egorov@phytec.de> */ -#include <eeprom.h> #include <init.h> #include <log.h> #include <net.h> #include <asm/global_data.h> #include <asm/io.h> -#include <common.h> #include <dm.h> #include <env.h> #include <env_internal.h> |