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path: root/board/sandburst/karef/karef.c
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Diffstat (limited to 'board/sandburst/karef/karef.c')
-rw-r--r--board/sandburst/karef/karef.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index b80c206940..92b15aa50f 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -212,36 +212,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non- critical */
- mtdcr (uic1pr, 0xfffffe03); /* polarity */
- mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffc8ff); /* polarity */
- mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uic3sr, 0xffffffff); /* clear all */
- mtdcr (uic3er, 0x00000000); /* disable all */
- mtdcr (uic3cr, 0x00000000); /* all non-critical */
- mtdcr (uic3pr, 0xffff83ff); /* polarity */
- mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
- mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic3sr, 0xffffffff); /* clear all */
-
- mtdcr (uic0sr, 0xfc000000); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non-critical */
- mtdcr (uic0pr, 0xfc000000);
- mtdcr (uic0tr, 0x00000000);
- mtdcr (uic0vr, 0x00000001);
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000000); /* all non- critical */
+ mtdcr (UIC1PR, 0xfffffe03); /* polarity */
+ mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
+ mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffff83ff); /* polarity */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000);
+ mtdcr (UIC0TR, 0x00000000);
+ mtdcr (UIC0VR, 0x00000001);
fpga_init();