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-rw-r--r--board/tqc/tqm834x/tqm834x.c8
-rw-r--r--board/tqc/tqm85xx/nand.c12
-rw-r--r--board/tqc/tqm85xx/tqm85xx.c35
3 files changed, 27 insertions, 28 deletions
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index e5648799a65..8d046f482f4 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -253,10 +253,10 @@ static int detect_num_flash_banks(void)
debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
/* set OR0 and BR0 */
- im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
- (-(total_size) & OR_GPCM_AM);
- im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
- (BR_MS_GPCM | BR_PS_32 | BR_V);
+ set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+ (-(total_size) & OR_GPCM_AM));
+ set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+ (BR_MS_GPCM | BR_PS_32 | BR_V));
return (0);
}
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index 3da689a9e46..4b16c31de28 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt;
*/
static void upmb_write (u_char addr, ulong val)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val)
/*
* Initialize UPM for NAND flash access.
*/
-static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
+static void nand_upm_setup (volatile fsl_lbc_t *lbc)
{
uint i, j;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
- out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
- out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_br(3, 0); /* disable bank and reset all bits */
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
/*
* Search appropriate UPM table for bus clock.
@@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
/* EAD must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EAD;
- out_be32 (&lbc->or3, or3);
+ set_lbc_or(3, or3);
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
@@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip)
int board_nand_init (struct nand_chip *nand)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
if (!nand_upm_patt)
nand_upm_setup (lbc);
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 8c9d586925a..fc2a6cbdb54 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -269,8 +269,6 @@ int checkboard (void)
int misc_init_r (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
/*
* Adjust flash start and offset to detected values
*/
@@ -281,26 +279,27 @@ int misc_init_r (void)
* Recalculate CS configuration if second FLASH bank is available
*/
if (flash_info[0].size > 0) {
- memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
- (CONFIG_SYS_OR1_PRELIM & 0x00007fff);
- memctl->br1 = gd->bd->bi_flashstart |
- (CONFIG_SYS_BR1_PRELIM & 0x00007fff);
+ set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+ (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+ set_lbc_br(1, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 1
*/
flash_get_size (gd->bd->bi_flashstart, 0);
} else {
- memctl->or1 = 0;
- memctl->br1 = 0;
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
}
/*
* If bank 1 is equipped, bank 0 is mapped after bank 1
*/
- memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
- (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
- memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
- (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
+ set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
/*
* Re-check to get correct base address for bank 0
*/
@@ -341,7 +340,7 @@ int misc_init_r (void)
*/
static void upmc_write (u_char addr, uint val)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val)
uint get_lbc_clock (void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
@@ -386,7 +385,7 @@ uint get_lbc_clock (void)
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
@@ -502,10 +501,10 @@ void local_bus_init (void)
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
- out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
- out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
- out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+ set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-04 02:11:02 +0000