diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/amcc/bamboo/bamboo.c | 722 | ||||
| -rw-r--r-- | board/amcc/bamboo/bamboo.h | 428 | ||||
| -rw-r--r-- | board/ep8248/Makefile | 46 | ||||
| -rw-r--r-- | board/ep8248/config.mk | 30 | ||||
| -rw-r--r-- | board/ep8248/ep8248.c | 263 | ||||
| -rw-r--r-- | board/ep8248/u-boot.lds | 122 |
6 files changed, 1042 insertions, 569 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index a3c70247333..0d5ab710d48 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -32,180 +32,192 @@ void configure_ppc440ep_pins(void); gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; #if 0 -{ /* GPIO Alternate1 Alternate2 Alternate3 */ - { - /* GPIO Core 0 */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ - { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ - }, - { - /* GPIO Core 1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ - } +{ /* GPIO Alternate1 Alternate2 Alternate3 */ + { + /* GPIO Core 0 */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ + { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ + }, + { + /* GPIO Core 1 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ + } }; #endif /*----------------------------------------------------------------------------+ | EBC Devices Characteristics - | Peripheral Bank Access Parameters - EBC0_BnAP - | Peripheral Bank Configuration Register - EBC0_BnCR + | Peripheral Bank Access Parameters - EBC0_BnAP + | Peripheral Bank Configuration Register - EBC0_BnCR +----------------------------------------------------------------------------*/ /* Small Flash */ -#define EBC0_BNAP_SMALL_FLASH EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(6) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(3) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ +#define EBC0_BNAP_SMALL_FLASH \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(6) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(3) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ EBC0_BNAP_PEN_DISABLED -#define EBC0_BNCR_SMALL_FLASH_CS0 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_SMALL_FLASH_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT -#define EBC0_BNCR_SMALL_FLASH_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_SMALL_FLASH_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT /* Large Flash or SRAM */ -#define EBC0_BNAP_LARGE_FLASH_OR_SRAM EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(8) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(1) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_RW | \ +#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(8) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(1) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_RW | \ EBC0_BNAP_PEN_DISABLED -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT /* NVRAM - FPGA */ -#define EBC0_BNAP_NVRAM_FPGA EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(9) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ +#define EBC0_BNAP_NVRAM_FPGA \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(9) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ EBC0_BNAP_PEN_DISABLED -#define EBC0_BNCR_NVRAM_FPGA_CS5 EBC0_BNCR_BAS_ENCODE(0x80000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_NVRAM_FPGA_CS5 \ + EBC0_BNCR_BAS_ENCODE(0x80000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT /* Nand Flash */ -#define EBC0_BNAP_NAND_FLASH EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(3) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(0) | \ - EBC0_BNAP_WBN_ENCODE(0) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_NOT_DELAYED | \ - EBC0_BNAP_BEM_RW | \ +#define EBC0_BNAP_NAND_FLASH \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(3) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(0) | \ + EBC0_BNAP_WBN_ENCODE(0) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_NOT_DELAYED | \ + EBC0_BNAP_BEM_RW | \ EBC0_BNAP_PEN_DISABLED -#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 +#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 /* NAND0 */ -#define EBC0_BNCR_NAND_FLASH_CS1 EBC0_BNCR_BAS_ENCODE(0x90000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_NAND_FLASH_CS1 \ + EBC0_BNCR_BAS_ENCODE(0x90000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT /* NAND1 - Bank2 */ -#define EBC0_BNCR_NAND_FLASH_CS2 EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_NAND_FLASH_CS2 \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT /* NAND1 - Bank3 */ -#define EBC0_BNCR_NAND_FLASH_CS3 EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_NAND_FLASH_CS3 \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT int board_early_init_f(void) @@ -289,18 +301,18 @@ int checkboard(void) * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM) * * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz * ************************************************************************/ void fixed_sdram_init(void) @@ -469,7 +481,7 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -593,7 +605,7 @@ void ext_bus_cntlr_init(void) { unsigned long sdr0_pstrp0, sdr0_sdstp1; unsigned long bootstrap_settings, boot_selection, ebc_boot_size; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; + int computed_boot_device = BOOT_DEVICE_UNKNOWN; unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; @@ -666,8 +678,8 @@ void ext_bus_cntlr_init(void) /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ mfsdr(sdr_sdstp1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; switch(boot_selection) { case SDR0_SDSTP1_BOOT_SEL_EBC: @@ -739,8 +751,8 @@ void ext_bus_cntlr_init(void) /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ mfsdr(sdr_sdstp1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; switch(boot_selection) { case SDR0_SDSTP1_BOOT_SEL_EBC: @@ -774,42 +786,42 @@ void ext_bus_cntlr_init(void) | Resulting EBC init will be among following configurations : | | - Boot from EBC 8bits => boot from SMALL FLASH selected - | EBC-CS0 = Small Flash - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Soft Config - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD + | EBC-CS0 = Small Flash + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Soft Config + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS5 = NVRAM / EPLD | | - Boot from EBC 16bits => boot from Large Flash or SRAM selected - | EBC-CS0 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = Small Flash - | EBC-CS5 = NVRAM / EPLD + | EBC-CS0 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Software Configuration + | EBC-CS4 = Small Flash + | EBC-CS5 = NVRAM / EPLD | | - Boot from NAND Flash - | EBC-CS0 = NAND Flash0 - | EBC-CS1,2,3 = NAND Flash1 - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD + | EBC-CS0 = NAND Flash0 + | EBC-CS1,2,3 = NAND Flash1 + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS5 = NVRAM / EPLD | | - Boot from PCI - | EBC-CS0 = ... - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM or - | Small Flash depending on jumpers - | EBC-CS5 = NVRAM / EPLD + | EBC-CS0 = ... + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Software Configuration + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM or + | Small Flash depending on jumpers + | EBC-CS5 = NVRAM / EPLD | +-------------------------------------------------------------------------*/ switch(computed_boot_device) { /*------------------------------------------------------------------------- */ - case BOOT_FROM_SMALL_FLASH: + case BOOT_FROM_SMALL_FLASH: /*------------------------------------------------------------------------- */ ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; @@ -840,7 +852,7 @@ void ext_bus_cntlr_init(void) break; /*------------------------------------------------------------------------- */ - case BOOT_FROM_LARGE_FLASH_OR_SRAM: + case BOOT_FROM_LARGE_FLASH_OR_SRAM: /*------------------------------------------------------------------------- */ ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; @@ -867,7 +879,7 @@ void ext_bus_cntlr_init(void) break; /*------------------------------------------------------------------------- */ - case BOOT_FROM_NAND_FLASH0: + case BOOT_FROM_NAND_FLASH0: /*------------------------------------------------------------------------- */ ebc0_cs0_bnap_value = 0; ebc0_cs0_bncr_value = 0; @@ -886,7 +898,7 @@ void ext_bus_cntlr_init(void) break; /*------------------------------------------------------------------------- */ - case BOOT_FROM_PCI: + case BOOT_FROM_PCI: /*------------------------------------------------------------------------- */ ebc0_cs0_bnap_value = 0; ebc0_cs0_bncr_value = 0; @@ -922,7 +934,7 @@ void ext_bus_cntlr_init(void) break; /*------------------------------------------------------------------------- */ - case BOOT_DEVICE_UNKNOWN: + case BOOT_DEVICE_UNKNOWN: /*------------------------------------------------------------------------- */ /* Error */ break; @@ -934,16 +946,16 @@ void ext_bus_cntlr_init(void) | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | - EBC0_CFG_PTD_ENABLED | - EBC0_CFG_RTC_2048PERCLK | - EBC0_CFG_EMPL_LOW | - EBC0_CFG_EMPH_LOW | - EBC0_CFG_CSTC_DRIVEN | - EBC0_CFG_BPF_ONEDW | - EBC0_CFG_EMS_8BIT | - EBC0_CFG_PME_DISABLED | - EBC0_CFG_PMT_ENCODE(0) ); + mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | + EBC0_CFG_PTD_ENABLED | + EBC0_CFG_RTC_2048PERCLK | + EBC0_CFG_EMPL_LOW | + EBC0_CFG_EMPH_LOW | + EBC0_CFG_CSTC_DRIVEN | + EBC0_CFG_BPF_ONEDW | + EBC0_CFG_EMS_8BIT | + EBC0_CFG_PME_DISABLED | + EBC0_CFG_PMT_ENCODE(0) ); /*-------------------------------------------------------------------------+ | Initialize EBC Bank 0-4 @@ -988,17 +1000,17 @@ void set_phy_configuration_through_fpga(zmii_config_t config) switch(config) { - case ZMII_CONFIGURATION_IS_MII: + case ZMII_CONFIGURATION_IS_MII: fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; break; - case ZMII_CONFIGURATION_IS_RMII: + case ZMII_CONFIGURATION_IS_RMII: fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; break; - case ZMII_CONFIGURATION_IS_SMII: + case ZMII_CONFIGURATION_IS_SMII: fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; break; - case ZMII_CONFIGURATION_UNKNOWN: - default: + case ZMII_CONFIGURATION_UNKNOWN: + default: break; } out8(FPGA_SELECTION_1_REG,fpga_selection_reg); @@ -1131,7 +1143,7 @@ void ndfc_selection_in_fpga(void) void uart_selection_in_fpga(uart_config_nb_t uart_config) { /* FPGA register */ - unsigned char fpga_selection_3_reg; + unsigned char fpga_selection_3_reg; /* Read FPGA Reagister */ fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); @@ -1140,43 +1152,43 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config) { case L1: /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ + /* L1 configuration: UART0 = 8 pins */ /* ----------------------------------------------------------------------- */ /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); break; case L2: /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ + /* L2 configuration: UART0 = 4 pins */ + /* UART1 = 4 pins */ /* ----------------------------------------------------------------------- */ /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); break; case L3: /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ + /* L3 configuration: UART0 = 4 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ /* ----------------------------------------------------------------------- */ /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); break; case L4: /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); break; @@ -1201,7 +1213,7 @@ void init_default_gpio(void) /* Init GPIO0 */ for(i=0; i<GPIO_MAX; i++) { - gpio_tab[GPIO0][i].add = GPIO0_BASE; + gpio_tab[GPIO0][i].add = GPIO0_BASE; gpio_tab[GPIO0][i].in_out = GPIO_DIS; gpio_tab[GPIO0][i].alt_nb = GPIO_SEL; } @@ -1209,7 +1221,7 @@ void init_default_gpio(void) /* Init GPIO1 */ for(i=0; i<GPIO_MAX; i++) { - gpio_tab[GPIO1][i].add = GPIO1_BASE; + gpio_tab[GPIO1][i].add = GPIO1_BASE; gpio_tab[GPIO1][i].in_out = GPIO_DIS; gpio_tab[GPIO1][i].alt_nb = GPIO_SEL; } @@ -1230,35 +1242,35 @@ void init_default_gpio(void) | Set UART Configuration in PowerPC440EP | | +---------------------------------------------------------------------+ - | | Configuartion | Connector | Nb of pins | Pins | Associated | - | | Number | Port Name | available | naming | CORE | + | | Configuartion | Connector | Nb of pins | Pins | Associated | + | | Number | Port Name | available | naming | CORE | | +-----------------+---------------+------------+--------+-------------+ - | | L1 | Port_A | 8 | UART | UART core 0 | + | | L1 | Port_A | 8 | UART | UART core 0 | | +-----------------+---------------+------------+--------+-------------+ - | | L2 | Port_A | 4 | UART1 | UART core 0 | - | | (L2D) | Port_B | 4 | UART2 | UART core 1 | + | | L2 | Port_A | 4 | UART1 | UART core 0 | + | | (L2D) | Port_B | 4 | UART2 | UART core 1 | | +-----------------+---------------+------------+--------+-------------+ - | | L3 | Port_A | 4 | UART1 | UART core 0 | - | | (L3D) | Port_B | 2 | UART2 | UART core 1 | - | | | Port_C | 2 | UART3 | UART core 2 | + | | L3 | Port_A | 4 | UART1 | UART core 0 | + | | (L3D) | Port_B | 2 | UART2 | UART core 1 | + | | | Port_C | 2 | UART3 | UART core 2 | | +-----------------+---------------+------------+--------+-------------+ - | | | Port_A | 2 | UART1 | UART core 0 | - | | L4 | Port_B | 2 | UART2 | UART core 1 | - | | (L4D) | Port_C | 2 | UART3 | UART core 2 | - | | | Port_D | 2 | UART4 | UART core 3 | + | | | Port_A | 2 | UART1 | UART core 0 | + | | L4 | Port_B | 2 | UART2 | UART core 1 | + | | (L4D) | Port_C | 2 | UART3 | UART core 2 | + | | | Port_D | 2 | UART4 | UART core 3 | | +-----------------+---------------+------------+--------+-------------+ | | Involved GPIOs | | +------------------------------------------------------------------------------+ - | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O | + | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O | | +---------+------------------+-----+-----------------+-----+-------------+-----+ - | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O | - | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I | - | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I | - | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O | - | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA | - | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA | + | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O | + | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I | + | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I | + | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O | + | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA | + | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA | | +------------------------------------------------------------------------------+ | | @@ -1270,7 +1282,7 @@ void update_uart_ios(uart_config_nb_t uart_config) { case L1: /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ + /* L1 configuration: UART0 = 8 pins */ /* ----------------------------------------------------------------------- */ /* Update GPIO Configuration Table */ gpio_tab[GPIO1][2].in_out = GPIO_IN; @@ -1295,8 +1307,8 @@ void update_uart_ios(uart_config_nb_t uart_config) case L2: /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ + /* L2 configuration: UART0 = 4 pins */ + /* UART1 = 4 pins */ /* ----------------------------------------------------------------------- */ /* Update GPIO Configuration Table */ gpio_tab[GPIO1][2].in_out = GPIO_IN; @@ -1321,9 +1333,9 @@ void update_uart_ios(uart_config_nb_t uart_config) case L3: /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ + /* L3 configuration: UART0 = 4 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ /* ----------------------------------------------------------------------- */ /* Update GPIO Configuration Table */ gpio_tab[GPIO1][2].in_out = GPIO_OUT; @@ -1348,10 +1360,10 @@ void update_uart_ios(uart_config_nb_t uart_config) case L4: /* ----------------------------------------------------------------------- */ - /* L4 configuration: UART0 = 2 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* UART3 = 2 pins */ + /* L4 configuration: UART0 = 2 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ + /* UART3 = 2 pins */ /* ----------------------------------------------------------------------- */ /* Update GPIO Configuration Table */ gpio_tab[GPIO1][2].in_out = GPIO_OUT; @@ -1394,15 +1406,15 @@ void update_uart_ios(uart_config_nb_t uart_config) +----------------------------------------------------------------------------*/ void update_ndfc_ios(void) { - /* Update GPIO Configuration Table */ - gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ - gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; + /* Update GPIO Configuration Table */ + gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ + gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; #if 0 - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; #endif } @@ -1412,48 +1424,48 @@ void update_ndfc_ios(void) +----------------------------------------------------------------------------*/ void update_zii_ios(void) { - /* Update GPIO Configuration Table */ - gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ - gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1; + /* Update GPIO Configuration Table */ + gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ + gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */ - gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */ + gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */ - gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */ + gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */ - gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */ + gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */ - gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */ + gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */ - gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */ + gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */ - gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */ + gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */ - gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */ + gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */ - gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */ + gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */ - gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */ + gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */ - gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */ + gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */ - gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */ + gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */ - gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */ + gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */ - gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1; + gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */ + gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1; } @@ -1462,16 +1474,16 @@ void update_zii_ios(void) +----------------------------------------------------------------------------*/ void update_uic_0_3_irq_ios(void) { - gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ + gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */ + gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */ gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */ + gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */ gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */ + gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */ gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1; } @@ -1480,19 +1492,19 @@ void update_uic_0_3_irq_ios(void) +----------------------------------------------------------------------------*/ void update_uic_4_9_irq_ios(void) { - gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ + gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */ + gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */ + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */ + gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */ + gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1; } @@ -1501,19 +1513,19 @@ void update_uic_4_9_irq_ios(void) +----------------------------------------------------------------------------*/ void update_dma_a_b_ios(void) { - gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ + gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; - gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */ + gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2; - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */ + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2; - gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */ + gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2; - gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */ + gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2; } @@ -1522,22 +1534,22 @@ void update_dma_a_b_ios(void) +----------------------------------------------------------------------------*/ void update_dma_c_d_ios(void) { - gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ + gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */ + gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */ gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */ + gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */ gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */ + gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */ gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */ + gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */ gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */ + gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */ gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2; } @@ -1547,16 +1559,16 @@ void update_dma_c_d_ios(void) +----------------------------------------------------------------------------*/ void update_ebc_master_ios(void) { - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */ + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1; - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */ + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1; } @@ -1565,28 +1577,28 @@ void update_ebc_master_ios(void) +----------------------------------------------------------------------------*/ void update_usb2_device_ios(void) { - gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ + gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */ + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */ + gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */ gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */ + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */ + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2; - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */ + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2; - gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */ + gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */ gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1; - gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */ + gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */ gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1; } @@ -1596,7 +1608,7 @@ void update_usb2_device_ios(void) +----------------------------------------------------------------------------*/ void update_pci_patch_ios(void) { - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; } @@ -1701,22 +1713,22 @@ void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t } /* L4 Selection */ - *(core_select_P+UART_CORE0) = CORE_SELECTED; - *(core_select_P+UART_CORE1) = CORE_SELECTED; - *(core_select_P+UART_CORE2) = CORE_SELECTED; - *(core_select_P+UART_CORE3) = CORE_SELECTED; + *(core_select_P+UART_CORE0) = CORE_SELECTED; + *(core_select_P+UART_CORE1) = CORE_SELECTED; + *(core_select_P+UART_CORE2) = CORE_SELECTED; + *(core_select_P+UART_CORE3) = CORE_SELECTED; /* RMII Selection */ - *(core_select_P+RMII_SEL) = CORE_SELECTED; + *(core_select_P+RMII_SEL) = CORE_SELECTED; /* External Interrupt 0-9 selection */ - *(core_select_P+UIC_0_3) = CORE_SELECTED; - *(core_select_P+UIC_4_9) = CORE_SELECTED; + *(core_select_P+UIC_0_3) = CORE_SELECTED; + *(core_select_P+UIC_4_9) = CORE_SELECTED; - *(core_select_P+SCP_CORE) = CORE_SELECTED; - *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; - *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; - *(core_select_P+USB1_DEVICE) = CORE_SELECTED; + *(core_select_P+SCP_CORE) = CORE_SELECTED; + *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; + *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; + *(core_select_P+USB1_DEVICE) = CORE_SELECTED; *config_val_P = CONFIG_IS_VALID; @@ -1733,28 +1745,28 @@ void configure_ppc440ep_pins(void) /* Create Core Selection Table */ core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = { - CORE_NOT_SELECTED, /* IIC_CORE, */ - CORE_NOT_SELECTED, /* SPC_CORE, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ - CORE_NOT_SELECTED, /* UIC_4_9, */ - CORE_NOT_SELECTED, /* USB2_HOST, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ - CORE_NOT_SELECTED, /* USB2_DEVICE, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ - CORE_NOT_SELECTED, /* USB1_DEVICE, */ - CORE_NOT_SELECTED, /* EBC_MASTER, */ - CORE_NOT_SELECTED, /* NAND_FLASH, */ - CORE_NOT_SELECTED, /* UART_CORE0, */ - CORE_NOT_SELECTED, /* UART_CORE1, */ - CORE_NOT_SELECTED, /* UART_CORE2, */ - CORE_NOT_SELECTED, /* UART_CORE3, */ - CORE_NOT_SELECTED, /* MII_SEL, */ - CORE_NOT_SELECTED, /* RMII_SEL, */ - CORE_NOT_SELECTED, /* SMII_SEL, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ - CORE_NOT_SELECTED, /* UIC_0_3 */ - CORE_NOT_SELECTED, /* USB1_HOST */ - CORE_NOT_SELECTED /* PCI_PATCH */ + CORE_NOT_SELECTED, /* IIC_CORE, */ + CORE_NOT_SELECTED, /* SPC_CORE, */ + CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ + CORE_NOT_SELECTED, /* UIC_4_9, */ + CORE_NOT_SELECTED, /* USB2_HOST, */ + CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ + CORE_NOT_SELECTED, /* USB2_DEVICE, */ + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ + CORE_NOT_SELECTED, /* USB1_DEVICE, */ + CORE_NOT_SELECTED, /* EBC_MASTER, */ + CORE_NOT_SELECTED, /* NAND_FLASH, */ + CORE_NOT_SELECTED, /* UART_CORE0, */ + CORE_NOT_SELECTED, /* UART_CORE1, */ + CORE_NOT_SELECTED, /* UART_CORE2, */ + CORE_NOT_SELECTED, /* UART_CORE3, */ + CORE_NOT_SELECTED, /* MII_SEL, */ + CORE_NOT_SELECTED, /* RMII_SEL, */ + CORE_NOT_SELECTED, /* SMII_SEL, */ + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ + CORE_NOT_SELECTED, /* UIC_0_3 */ + CORE_NOT_SELECTED, /* USB1_HOST */ + CORE_NOT_SELECTED /* PCI_PATCH */ }; @@ -1773,9 +1785,9 @@ void configure_ppc440ep_pins(void) /*----------------------------------------------------------------------------+ | SDR + ios table update + fpga initialization +----------------------------------------------------------------------------*/ - unsigned long sdr0_pfc1 = 0; - unsigned long sdr0_usb0 = 0; - unsigned long sdr0_mfr = 0; + unsigned long sdr0_pfc1 = 0; + unsigned long sdr0_usb0 = 0; + unsigned long sdr0_mfr = 0; /* PCI Always selected */ @@ -1886,9 +1898,9 @@ void configure_ppc440ep_pins(void) update_ndfc_ios(); mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 ); /*SDR0_CUST0_CHIPSELGAT_EN2 ); */ /*SDR0_CUST0_CHIPSELGAT_EN3 ); */ @@ -1938,25 +1950,25 @@ void configure_ppc440ep_pins(void) uart_configuration = get_uart_configuration(); switch (uart_configuration) { - case L1: /* L1 Selection */ + case L1: /* L1 Selection */ /* UART0 8 pins Only */ /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; break; - case L2: /* L2 Selection */ + case L2: /* L2 Selection */ /* UART0 and UART1 4 pins */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; break; - case L3: /* L3 Selection */ + case L3: /* L3 Selection */ /* UART0 4 pins, UART1 and UART2 2 pins */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; break; - case L4: /* L4 Selection */ + case L4: /* L4 Selection */ /* UART0, UART1, UART2 and UART3 2 pins */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 612e9af7d88..5f5fcde825e 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -29,107 +29,107 @@ * TLB initialization makes it correspond to logical address 0x80001FF0. * => Done init_chip.s in bootlib */ -#define FPGA_BASE_ADDR 0x80002000 +#define FPGA_BASE_ADDR 0x80002000 /*----------------------------------------------------------------------------+ | Board Jumpers Setting Register | Board Settings provided by jumpers +----------------------------------------------------------------------------*/ -#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) +#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) /* Boot from small flash */ -#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 +#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 /* Operational Flash versus SRAM position in Memory Map */ -#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 -#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 -#define FPGA_SET_REG_SRAM_ABOVE 0x00 +#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 +#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 +#define FPGA_SET_REG_SRAM_ABOVE 0x00 /* Boot From NAND Flash */ -#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 -#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 +#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 +#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 /* On Board PCI Arbiter Select */ -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 /*----------------------------------------------------------------------------+ | Functions Selection Register 1 +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) -#define FPGA_SEL_1_REG_PHY_MASK 0xE0 -#define FPGA_SEL_1_REG_MII 0x80 -#define FPGA_SEL_1_REG_RMII 0x40 -#define FPGA_SEL_1_REG_SMII 0x20 -#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ -#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ -#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ -#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ +#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) +#define FPGA_SEL_1_REG_PHY_MASK 0xE0 +#define FPGA_SEL_1_REG_MII 0x80 +#define FPGA_SEL_1_REG_RMII 0x40 +#define FPGA_SEL_1_REG_SMII 0x20 +#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ +#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ +#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ +#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ /*----------------------------------------------------------------------------+ | Functions Selection Register 2 +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) -#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ -#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ -#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ -#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ -#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ -#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ -#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ - /* 1 = TC - output from 440EP */ -#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ - /* 1 = TC (output from 440EP) */ -#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ +#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) +#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ +#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ +#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ +#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ +#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ +#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ +#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ + /* 1 = TC - output from 440EP */ +#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ + /* 1 = TC (output from 440EP) */ +#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ +#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ +#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ /*----------------------------------------------------------------------------+ | Functions Selection Register 3 +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) -#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 -#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ -#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ -#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ +#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) +#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 +#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ +#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ +#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ /*----------------------------------------------------------------------------+ | Soft Reset Register +----------------------------------------------------------------------------*/ -#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) -#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ -#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ -#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ +#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) +#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ +#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ +#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ /*----------------------------------------------------------------------------+ | SDR Configuration registers +----------------------------------------------------------------------------*/ /* Serial Device Strap Reg 0 */ -#define SDR0_SDSTP0 0x0020 +#define SDR0_SDSTP0 0x0020 /* Serial Device Strap Reg 1 */ -#define SDR0_SDSTP1 0x0021 +#define SDR0_SDSTP1 0x0021 /* Serial Device Strap Reg 2 */ -#define SDR0_SDSTP2 SDR0_STRP2 +#define SDR0_SDSTP2 SDR0_STRP2 /* Serial Device Strap Reg 3 */ -#define SDR0_SDSTP3 SDR0_STRP3 +#define SDR0_SDSTP3 SDR0_STRP3 -#define sdr_pstrp0 0x0040 +#define sdr_pstrp0 0x0040 -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ -#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ +#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ -#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ +#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ +#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ +#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ +#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ /* Serial Device Enabled - Addr = 0xA8 */ #define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 @@ -137,8 +137,8 @@ #define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 /* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ +#define SDR0_PSTRP0 0x0040 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ #define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ @@ -153,182 +153,182 @@ | EBC Configuration Register - EBC0_CFG +----------------------------------------------------------------------------*/ /* External Bus Three-State Control */ -#define EBC0_CFG_EBTC_DRIVEN 0x80000000 +#define EBC0_CFG_EBTC_DRIVEN 0x80000000 /* Device-Paced Time-out Disable */ -#define EBC0_CFG_PTD_ENABLED 0x00000000 +#define EBC0_CFG_PTD_ENABLED 0x00000000 /* Ready Timeout Count */ -#define EBC0_CFG_RTC_MASK 0x38000000 -#define EBC0_CFG_RTC_16PERCLK 0x00000000 -#define EBC0_CFG_RTC_32PERCLK 0x08000000 -#define EBC0_CFG_RTC_64PERCLK 0x10000000 -#define EBC0_CFG_RTC_128PERCLK 0x18000000 -#define EBC0_CFG_RTC_256PERCLK 0x20000000 -#define EBC0_CFG_RTC_512PERCLK 0x28000000 -#define EBC0_CFG_RTC_1024PERCLK 0x30000000 -#define EBC0_CFG_RTC_2048PERCLK 0x38000000 +#define EBC0_CFG_RTC_MASK 0x38000000 +#define EBC0_CFG_RTC_16PERCLK 0x00000000 +#define EBC0_CFG_RTC_32PERCLK 0x08000000 +#define EBC0_CFG_RTC_64PERCLK 0x10000000 +#define EBC0_CFG_RTC_128PERCLK 0x18000000 +#define EBC0_CFG_RTC_256PERCLK 0x20000000 +#define EBC0_CFG_RTC_512PERCLK 0x28000000 +#define EBC0_CFG_RTC_1024PERCLK 0x30000000 +#define EBC0_CFG_RTC_2048PERCLK 0x38000000 /* External Master Priority Low */ -#define EBC0_CFG_EMPL_LOW 0x00000000 +#define EBC0_CFG_EMPL_LOW 0x00000000 #define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 #define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 -#define EBC0_CFG_EMPL_HIGH 0x06000000 +#define EBC0_CFG_EMPL_HIGH 0x06000000 /* External Master Priority High */ -#define EBC0_CFG_EMPH_LOW 0x00000000 +#define EBC0_CFG_EMPH_LOW 0x00000000 #define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 #define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 -#define EBC0_CFG_EMPH_HIGH 0x01800000 +#define EBC0_CFG_EMPH_HIGH 0x01800000 /* Chip Select Three-State Control */ -#define EBC0_CFG_CSTC_DRIVEN 0x00400000 +#define EBC0_CFG_CSTC_DRIVEN 0x00400000 /* Burst Prefetch */ -#define EBC0_CFG_BPF_ONEDW 0x00000000 -#define EBC0_CFG_BPF_TWODW 0x00100000 -#define EBC0_CFG_BPF_FOURDW 0x00200000 +#define EBC0_CFG_BPF_ONEDW 0x00000000 +#define EBC0_CFG_BPF_TWODW 0x00100000 +#define EBC0_CFG_BPF_FOURDW 0x00200000 /* External Master Size */ -#define EBC0_CFG_EMS_8BIT 0x00000000 +#define EBC0_CFG_EMS_8BIT 0x00000000 /* Power Management Enable */ -#define EBC0_CFG_PME_DISABLED 0x00000000 -#define EBC0_CFG_PME_ENABLED 0x00020000 +#define EBC0_CFG_PME_DISABLED 0x00000000 +#define EBC0_CFG_PME_ENABLED 0x00020000 /* Power Management Timer */ -#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) +#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) /*----------------------------------------------------------------------------+ | Peripheral Bank Configuration Register - EBC0_BnCR +----------------------------------------------------------------------------*/ /* BAS - Base Address Select */ -#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) +#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) /* BS - Bank Size */ -#define EBC0_BNCR_BS_MASK 0x000E0000 -#define EBC0_BNCR_BS_1MB 0x00000000 -#define EBC0_BNCR_BS_2MB 0x00020000 -#define EBC0_BNCR_BS_4MB 0x00040000 -#define EBC0_BNCR_BS_8MB 0x00060000 -#define EBC0_BNCR_BS_16MB 0x00080000 -#define EBC0_BNCR_BS_32MB 0x000A0000 -#define EBC0_BNCR_BS_64MB 0x000C0000 -#define EBC0_BNCR_BS_128MB 0x000E0000 +#define EBC0_BNCR_BS_MASK 0x000E0000 +#define EBC0_BNCR_BS_1MB 0x00000000 +#define EBC0_BNCR_BS_2MB 0x00020000 +#define EBC0_BNCR_BS_4MB 0x00040000 +#define EBC0_BNCR_BS_8MB 0x00060000 +#define EBC0_BNCR_BS_16MB 0x00080000 +#define EBC0_BNCR_BS_32MB 0x000A0000 +#define EBC0_BNCR_BS_64MB 0x000C0000 +#define EBC0_BNCR_BS_128MB 0x000E0000 /* BU - Bank Usage */ -#define EBC0_BNCR_BU_MASK 0x00018000 -#define EBC0_BNCR_BU_RO 0x00008000 -#define EBC0_BNCR_BU_WO 0x00010000 -#define EBC0_BNCR_BU_RW 0x00018000 +#define EBC0_BNCR_BU_MASK 0x00018000 +#define EBC0_BNCR_BU_RO 0x00008000 +#define EBC0_BNCR_BU_WO 0x00010000 +#define EBC0_BNCR_BU_RW 0x00018000 /* BW - Bus Width */ -#define EBC0_BNCR_BW_MASK 0x00006000 -#define EBC0_BNCR_BW_8BIT 0x00000000 -#define EBC0_BNCR_BW_16BIT 0x00002000 -#define EBC0_BNCR_BW_32BIT 0x00004000 +#define EBC0_BNCR_BW_MASK 0x00006000 +#define EBC0_BNCR_BW_8BIT 0x00000000 +#define EBC0_BNCR_BW_16BIT 0x00002000 +#define EBC0_BNCR_BW_32BIT 0x00004000 /*----------------------------------------------------------------------------+ | Peripheral Bank Access Parameters - EBC0_BnAP +----------------------------------------------------------------------------*/ /* Burst Mode Enable */ -#define EBC0_BNAP_BME_ENABLED 0x80000000 -#define EBC0_BNAP_BME_DISABLED 0x00000000 +#define EBC0_BNAP_BME_ENABLED 0x80000000 +#define EBC0_BNAP_BME_DISABLED 0x00000000 /* Transfert Wait */ -#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ +#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ /* Chip Select On Timing */ -#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ +#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ /* Output Enable On Timing */ -#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ +#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ /* Write Back Enable On Timing */ -#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ +#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ /* Write Back Enable Off Timing */ -#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ +#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ /* Transfert Hold */ -#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ +#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ /* PerReady Enable */ -#define EBC0_BNAP_RE_ENABLED 0x00000100 -#define EBC0_BNAP_RE_DISABLED 0x00000000 +#define EBC0_BNAP_RE_ENABLED 0x00000100 +#define EBC0_BNAP_RE_DISABLED 0x00000000 /* Sample On Ready */ -#define EBC0_BNAP_SOR_DELAYED 0x00000000 +#define EBC0_BNAP_SOR_DELAYED 0x00000000 #define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080 /* Byte Enable Mode */ -#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 -#define EBC0_BNAP_BEM_RW 0x00000040 +#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 +#define EBC0_BNAP_BEM_RW 0x00000040 /* Parity Enable */ -#define EBC0_BNAP_PEN_DISABLED 0x00000000 -#define EBC0_BNAP_PEN_ENABLED 0x00000020 +#define EBC0_BNAP_PEN_DISABLED 0x00000000 +#define EBC0_BNAP_PEN_ENABLED 0x00000020 /*----------------------------------------------------------------------------+ | Define Boot devices +----------------------------------------------------------------------------*/ /* */ -#define BOOT_FROM_SMALL_FLASH 0x00 -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 -#define BOOT_FROM_NAND_FLASH0 0x02 -#define BOOT_FROM_PCI 0x03 -#define BOOT_DEVICE_UNKNOWN 0x04 +#define BOOT_FROM_SMALL_FLASH 0x00 +#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 +#define BOOT_FROM_NAND_FLASH0 0x02 +#define BOOT_FROM_PCI 0x03 +#define BOOT_DEVICE_UNKNOWN 0x04 -#define PVR_POWERPC_440EP_PASS1 0x42221850 -#define PVR_POWERPC_440EP_PASS2 0x422218D3 +#define PVR_POWERPC_440EP_PASS1 0x42221850 +#define PVR_POWERPC_440EP_PASS2 0x422218D3 #define TRUE 1 #define FALSE 0 -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ +#define GPIO_GROUP_MAX 2 +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ +#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ +#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ +#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ +#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ + /* For the other GPIO number, you must shift */ -#define GPIO0 0 -#define GPIO1 1 +#define GPIO0 0 +#define GPIO1 1 -/*#define MAX_SELECTION_NB CORE_NB */ -#define MAX_CORE_SELECT_NB 22 +/*#define MAX_SELECTION_NB CORE_NB */ +#define MAX_CORE_SELECT_NB 22 /*----------------------------------------------------------------------------+ | PPC440EP GPIOs addresses. +----------------------------------------------------------------------------*/ -#define GPIO0_BASE 0xEF600B00 -#define GPIO0_REAL 0xEF600B00 +#define GPIO0_BASE 0xEF600B00 +#define GPIO0_REAL 0xEF600B00 -#define GPIO1_BASE 0xEF600C00 -#define GPIO1_REAL 0xEF600C00 +#define GPIO1_BASE 0xEF600C00 +#define GPIO1_REAL 0xEF600C00 /* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ /* GPIO0 */ -#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) -#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) -#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) -#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) -#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) -#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) +#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) +#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) +#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) +#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) +#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) +#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) /* GPIO1 */ -#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) -#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) -#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) -#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) -#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) -#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) +#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) +#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) +#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) +#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) +#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) +#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ /*----------------------------------------------------------------------------+ @@ -337,27 +337,27 @@ typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; -typedef struct { unsigned long add; /* gpio core base address */ +typedef struct { unsigned long add; /* gpio core base address */ gpio_driver_t in_out; /* Driver Setting */ gpio_select_t alt_nb; /* Selected Alternate */ } gpio_param_s; /*----------------------------------------------------------------------------+ - | XX XX + | XX XX | | XXXXXX XXX XX XXX XXX - | XX XX X XX XX XX - | XX XX X XX XX XX - | XX XX XX XX XX + | XX XX X XX XX XX + | XX XX X XX XX XX + | XX XX XX XX XX | XXXXXX XXX XXX XXXX XXXX +----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------+ | Defines +----------------------------------------------------------------------------*/ typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, - ZMII_CONFIGURATION_IS_MII, - ZMII_CONFIGURATION_IS_RMII, - ZMII_CONFIGURATION_IS_SMII + ZMII_CONFIGURATION_IS_MII, + ZMII_CONFIGURATION_IS_RMII, + ZMII_CONFIGURATION_IS_SMII } zmii_config_t; /*----------------------------------------------------------------------------+ @@ -366,36 +366,36 @@ typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t; typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t; typedef enum config_list { IIC_CORE, - SCP_CORE, - DMA_CHANNEL_AB, - UIC_4_9, - USB2_HOST, - DMA_CHANNEL_CD, - USB2_DEVICE, - PACKET_REJ_FUNC_AVAIL, - USB1_DEVICE, - EBC_MASTER, - NAND_FLASH, - UART_CORE0, - UART_CORE1, - UART_CORE2, - UART_CORE3, - MII_SEL, - RMII_SEL, - SMII_SEL, - PACKET_REJ_FUNC_EN, - UIC_0_3, - USB1_HOST, - PCI_PATCH, - CORE_NB + SCP_CORE, + DMA_CHANNEL_AB, + UIC_4_9, + USB2_HOST, + DMA_CHANNEL_CD, + USB2_DEVICE, + PACKET_REJ_FUNC_AVAIL, + USB1_DEVICE, + EBC_MASTER, + NAND_FLASH, + UART_CORE0, + UART_CORE1, + UART_CORE2, + UART_CORE3, + MII_SEL, + RMII_SEL, + SMII_SEL, + PACKET_REJ_FUNC_EN, + UIC_0_3, + USB1_HOST, + PCI_PATCH, + CORE_NB } core_list_t; typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5, - B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, - B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, - B3_V16, B3_VALUE_UNKNOWN + B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, + B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, + B3_V16, B3_VALUE_UNKNOWN } block3_value_t; typedef enum config_validity { CONFIG_IS_VALID, - CONFIG_IS_INVALID + CONFIG_IS_INVALID } config_validity_t; diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile new file mode 100644 index 00000000000..8b10993194e --- /dev/null +++ b/board/ep8248/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ep8248/config.mk b/board/ep8248/config.mk new file mode 100644 index 00000000000..eda523be265 --- /dev/null +++ b/board/ep8248/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EP82xx series boards by Embedded Planet +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c new file mode 100644 index 00000000000..69975caa2ee --- /dev/null +++ b/board/ep8248/ep8248.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Support for Embedded Planet EP8248 boards. + * Tested on EP8248E. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8260.h> +#include <ioports.h> + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +int board_early_init_f (void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + bcsr[4] |= 0x30; /* Turn the LEDs off */ + +#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) + bcsr[6] |= 0x10; +#endif +#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) + bcsr[7] |= 0x10; +#endif + +#if CFG_FCC1 + bcsr[8] |= 0xC0; +#endif /* CFG_FCC1 */ +#if CFG_FCC2 + bcsr[8] |= 0x30; +#endif /* CFG_FCC2 */ + + return 0; +} + +long int initdram(int board_type) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + long int msize = 16L << (bcsr[2] & 3); + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + uchar c = 0xFF; + uint psdmr = CFG_PSDMR; + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x02; + immap->im_siu_conf.sc_ppc_alrh = 0x30126745; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_SDRAM_OR; + memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + *ramaddr = c; +#endif /* !CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + puts("Board: "); + switch (bcsr[0]) { + case 0x0C: + printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]); + break; + default: + printf("unknown: ID=%02X\n", bcsr[0]); + } + + return 0; +} diff --git a/board/ep8248/u-boot.lds b/board/ep8248/u-boot.lds new file mode 100644 index 00000000000..d6f35f31e09 --- /dev/null +++ b/board/ep8248/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen <yuli@arabellasw.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) |