diff options
Diffstat (limited to 'board')
36 files changed, 950 insertions, 606 deletions
diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c index 9579d52ffde..7a510c61fb0 100644 --- a/board/Arcturus/ucp1020/cmd_arc.c +++ b/board/Arcturus/ucp1020/cmd_arc.c @@ -2,8 +2,8 @@ /* * Command for accessing Arcturus factory environment. * - * Copyright 2013-2015 Arcturus Networks Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks Inc. + * https://www.arcturusnetworks.com/products/ * by Oleksandr G Zhadan et al. * */ @@ -12,19 +12,13 @@ #include <div64.h> #include <malloc.h> #include <spi_flash.h> - +#include <mmc.h> +#include <version.h> +#include <environment.h> #include <asm/io.h> -#define MAX_SERIAL_SIZE 15 -#define MAX_HWADDR_SIZE 17 - -#define FIRM_ADDR1 (0x200 - sizeof(smac)) -#define FIRM_ADDR2 (0x400 - sizeof(smac)) -#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) -#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) - -static struct spi_flash *flash; -char smac[4][18]; +static ulong fwenv_addr[MAX_FWENV_ADDR]; +const char mystrerr[] = "ERROR: Failed to save factory info"; static int ishwaddr(char *hwaddr) { @@ -38,156 +32,349 @@ static int ishwaddr(char *hwaddr) return -1; } -static int set_arc_product(int argc, char *const argv[]) +#if (FWENV_TYPE == FWENV_MMC) + +static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */ + +int set_mmc_arc_product(int argc, char *const argv[]) { - int err = 0; - char *mystrerr = "ERROR: Failed to save factory info in spi location"; + struct mmc *mmc; + u32 blk, cnt, n; + int i, err = 1; + void *addr; + const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + + mmc = find_mmc_device(mmc_dev_num); + if (!mmc) { + printf("No SD/MMC/eMMC card found\n"); + return 0; + } + if (mmc_init(mmc)) { + printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", + mmc_dev_num); + return 0; + } + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; + } - if (argc != 5) - return -1; + /* Save factory defaults */ + addr = (void *)smac; + cnt = 1; /* One 512 bytes block */ + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + blk = fwenv_addr[i] / 512; + n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); + if (n != cnt) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + } + if (err) + return -2; - /* Check serial number */ - if (strlen(argv[1]) != MAX_SERIAL_SIZE) - return -1; + return err; +} - /* Check HWaddrs */ - if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) - return -1; +static int read_mmc_arc_info(void) +{ + struct mmc *mmc; + u32 blk, cnt, n; + int i; + void *addr; + const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + + mmc = find_mmc_device(mmc_dev_num); + if (!mmc) { + printf("No SD/MMC/eMMC card found\n"); + return 0; + } + if (mmc_init(mmc)) { + printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", + mmc_dev_num); + return 0; + } - strcpy(smac[3], argv[1]); - strcpy(smac[2], argv[2]); - strcpy(smac[1], argv[3]); - strcpy(smac[0], argv[4]); + addr = (void *)smac; + cnt = 1; /* One 512 bytes block */ - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + blk = fwenv_addr[i] / 512; + n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); + flush_cache((ulong) addr, 512); + if (n == cnt) + return (i + 1); + } + return 0; +} +#endif - /* - * Save factory defaults - */ +#if (FWENV_TYPE == FWENV_SPI_FLASH) - if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) { - printf("%s: %s [1]\n", __func__, mystrerr); - err++; - } - if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) { - printf("%s: %s [2]\n", __func__, mystrerr); - err++; - } +static struct spi_flash *flash; +static char smac[4][18]; - if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) { - printf("%s: %s [3]\n", __func__, mystrerr); - err++; - } +int set_spi_arc_product(int argc, char *const argv[]) +{ + int i, err = 1; - if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) { - printf("%s: %s [4]\n", __func__, mystrerr); - err++; + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", + CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); + return -1; } - if (err == 4) { - printf("%s: %s [ALL]\n", __func__, mystrerr); + /* Save factory defaults */ + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + if (spi_flash_write + (flash, fwenv_addr[i], sizeof(smac), smac)) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + if (err) return -2; - } - return 0; + return err; } -int get_arc_info(void) +static int read_spi_arc_info(void) { - int location = 1; - char *myerr = "ERROR: Failed to read all 4 factory info spi locations"; + int i; flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", + CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); + return 0; + } + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + if (!spi_flash_read + (flash, fwenv_addr[i], sizeof(smac), smac)) + return (i + 1); + return 0; +} +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) - if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac), - smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR4, - sizeof(smac), smac)) { - printf("%s: %s\n", __func__, myerr); - return -2; - } - } +static char smac[4][18]; + +int set_nor_arc_product(int argc, char *const argv[]) +{ + int i, err = 1; + + /* Save factory defaults */ + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + ulong fwenv_end = fwenv_addr[i] + 4; + + flash_sect_roundb(&fwenv_end); + flash_sect_protect(0, fwenv_addr[i], fwenv_end); + if (flash_write + ((char *)smac, fwenv_addr[i], sizeof(smac))) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + flash_sect_protect(1, fwenv_addr[i], fwenv_end); } - } - if (smac[3][0] != 0) { - if (location > 1) - printf("Using region %d\n", location); - printf("SERIAL: "); - if (smac[3][0] == 0xFF) { - printf("\t<not found>\n"); - } else { - printf("\t%s\n", smac[3]); - env_set("SERIAL", smac[3]); + if (err) + return -2; + + return err; +} + +static int read_nor_arc_info(void) +{ + int i; + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + memcpy(smac, (void *)fwenv_addr[i], sizeof(smac)); + return (i + 1); } + + return 0; +} +#endif + +int set_arc_product(int argc, char *const argv[]) +{ + if (argc != 5) + return -1; + + /* Check serial number */ + if (strlen(argv[1]) != MAX_SERIAL_SIZE) + return -1; + + /* Check HWaddrs */ + if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) + return -1; + + strcpy(smac[0], argv[1]); + strcpy(smac[1], argv[2]); + strcpy(smac[2], argv[3]); + strcpy(smac[3], argv[4]); + +#if (FWENV_TYPE == FWENV_NOR_FLASH) + return set_nor_arc_product(argc, argv); +#endif +#if (FWENV_TYPE == FWENV_SPI_FLASH) + return set_spi_arc_product(argc, argv); +#endif +#if (FWENV_TYPE == FWENV_MMC) + return set_mmc_arc_product(argc, argv); +#endif + return -2; +} + +static int read_arc_info(void) +{ +#if (FWENV_TYPE == FWENV_NOR_FLASH) + return read_nor_arc_info(); +#endif +#if (FWENV_TYPE == FWENV_SPI_FLASH) + return read_spi_arc_info(); +#endif +#if (FWENV_TYPE == FWENV_MMC) + return read_mmc_arc_info(); +#endif + return 0; +} + +static int do_get_arc_info(void) +{ + int l = read_arc_info(); + char *oldserial = env_get("SERIAL"); + char *oldversion = env_get("VERSION"); + + if (oldversion != NULL) + if (strcmp(oldversion, U_BOOT_VERSION) != 0) + oldversion = NULL; + + if (l == 0) { + printf("%s: failed to read factory info\n", __func__); + return -2; } - if (strcmp(smac[2], "00:00:00:00:00:00") == 0) - return 0; + printf("\rSERIAL: "); + if (smac[0][0] == EMPY_CHAR) { + printf("<not found>\n"); + } else { + printf("%s\n", smac[0]); + env_set("SERIAL", smac[0]); + } - printf("HWADDR0:"); - if (smac[2][0] == 0xFF) { - printf("\t<not found>\n"); + if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { + env_set("ethaddr", NULL); + env_set("eth1addr", NULL); + env_set("eth2addr", NULL); + goto done; + } + + printf("HWADDR0: "); + if (smac[1][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("ethaddr"); - if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { - env_set("ethaddr", smac[2]); - printf("\t%s (factory)\n", smac[2]); + if (ret == NULL) { + env_set("ethaddr", smac[1]); + printf("%s\n", smac[1]); + } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { + env_set("ethaddr", smac[1]); + printf("%s (factory)\n", smac[1]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } - if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { - env_set("eth1addr", smac[2]); - env_set("eth2addr", smac[2]); - return 0; + if (strcmp(smac[2], "00:00:00:00:00:00") == 0) { + env_set("eth1addr", NULL); + env_set("eth2addr", NULL); + goto done; } - printf("HWADDR1:"); - if (smac[1][0] == 0xFF) { - printf("\t<not found>\n"); + printf("HWADDR1: "); + if (smac[2][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("eth1addr"); - if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { - env_set("eth1addr", smac[1]); - printf("\t%s (factory)\n", smac[1]); + if (ret == NULL) { + env_set("ethaddr", smac[2]); + printf("%s\n", smac[2]); + } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { + env_set("eth1addr", smac[2]); + printf("%s (factory)\n", smac[2]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } - if (strcmp(smac[0], "00:00:00:00:00:00") == 0) { - env_set("eth2addr", smac[1]); - return 0; + if (strcmp(smac[3], "00:00:00:00:00:00") == 0) { + env_set("eth2addr", NULL); + goto done; } - printf("HWADDR2:"); - if (smac[0][0] == 0xFF) { - printf("\t<not found>\n"); + printf("HWADDR2: "); + if (smac[3][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("eth2addr"); - if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { - env_set("eth2addr", smac[0]); - printf("\t%s (factory)\n", smac[0]); + if (ret == NULL) { + env_set("ethaddr", smac[3]); + printf("%s\n", smac[3]); + } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { + env_set("eth2addr", smac[3]); + printf("%s (factory)\n", smac[3]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } +done: + if (oldserial == NULL || oldversion == NULL) { + if (oldversion == NULL) + env_set("VERSION", U_BOOT_VERSION); + env_save(); + } return 0; } -static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +static int init_fwenv(void) +{ + int i, ret = -1; + + fwenv_addr[0] = FWENV_ADDR1; + fwenv_addr[1] = FWENV_ADDR2; + fwenv_addr[2] = FWENV_ADDR3; + fwenv_addr[3] = FWENV_ADDR4; + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + ret = 0; + if (ret) + printf("%s: No firmfare info storage address is defined\n", + __func__); + return ret; +} + +void get_arc_info(void) +{ + if (!init_fwenv()) + do_get_arc_info(); +} + +static int do_arc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]) { const char *cmd; int ret = -1; @@ -196,15 +383,14 @@ static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) --argc; ++argv; - if (strcmp(cmd, "product") == 0) { + if (init_fwenv()) + return ret; + + if (strcmp(cmd, "product") == 0) ret = set_arc_product(argc, argv); - goto done; - } - if (strcmp(cmd, "info") == 0) { - ret = get_arc_info(); - goto done; - } -done: + else if (strcmp(cmd, "info") == 0) + ret = do_get_arc_info(); + if (ret == -1) return CMD_RET_USAGE; diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c index 1a1fcb9be9c..54fd1782cb1 100644 --- a/board/Arcturus/ucp1020/ucp1020.c +++ b/board/Arcturus/ucp1020/ucp1020.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * by Oleksandr G Zhadan et al. * based on board/freescale/p1_p2_rdb_pc/spl.c * original copyright follows: @@ -108,7 +108,9 @@ int checkboard(void) { printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); board_gpio_init(); +#ifdef CONFIG_MMC printf("SD/MMC: 4-bit Mode\n"); +#endif return 0; } @@ -193,7 +195,9 @@ int last_stage_init(void) static char newkernelargs[256]; static u8 id1[16]; static u8 id2; +#ifdef CONFIG_MMC struct mmc *mmc; +#endif char *sval, *kval; if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { @@ -215,6 +219,7 @@ int last_stage_init(void) kval = env_get("kernelargs"); +#ifdef CONFIG_MMC mmc = find_mmc_device(0); if (mmc) if (!mmc_init(mmc)) { @@ -234,6 +239,7 @@ int last_stage_init(void) env_set("kernelargs", mmckargs); } } +#endif get_arc_info(); if (kval) { diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h index cf1ddd718bb..1b527cdb1cf 100644 --- a/board/Arcturus/ucp1020/ucp1020.h +++ b/board/Arcturus/ucp1020/ucp1020.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * by Oleksandr G Zhadan et al. */ @@ -35,8 +35,10 @@ #define GPIO_WD GPIO15 +#ifdef CONFIG_MMC static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro"; static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw"; +#endif int get_arc_info(void); diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 0608a5a88b9..21156a4ca94 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) ARM Ltd 2015 * * Author: Liviu Dudau <Liviu.Dudau@arm.com> - * - * SPDX-Licence-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/bosch/guardian/MAINTAINERS b/board/bosch/guardian/MAINTAINERS index 8d16ec0202c..2f674d7f839 100644 --- a/board/bosch/guardian/MAINTAINERS +++ b/board/bosch/guardian/MAINTAINERS @@ -1,5 +1,7 @@ Guardian BOARD M: Sjoerd Simons <sjoerd.simons@collabora.co.uk> +M: Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com> +M: Moses Christopher Bollavarapu <BollavarapuMoses.Christopher@in.bosch.com> S: Maintained F: board/bosch/guardian/ F: include/configs/am335x_guardian.h diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 97376c41652..dddfd26a13f 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -79,7 +79,7 @@ int fsl_setenv_chain_of_trust(void) * bootdelay = 0 (To disable Boot Prompt) * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) */ - env_set("bootdelay", "0"); + env_set("bootdelay", "-2"); #ifdef CONFIG_ARM env_set("secureboot", "y"); diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS index 6f1a95ea3b1..2c288256985 100644 --- a/board/freescale/ls1028a/MAINTAINERS +++ b/board/freescale/ls1028a/MAINTAINERS @@ -19,3 +19,13 @@ F: board/freescale/ls1028a/ F: include/configs/ls1028a_common.h F: include/configs/ls1028ardb.h F: configs/ls1028ardb_tfa_defconfig + +LS1028AQDS_SECURE_BOOT BOARD +M: Tang Yuantian <andy.tang@nxp.com> +S: Maintained +F: configs/ls1028aqds_tfa_SECURE_BOOT_defconfig + +LS1028ARDB_SECURE_BOOT BOARD +M: Tang Yuantian <andy.tang@nxp.com> +S: Maintained +F: configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 8763913e318..e1919d29885 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -161,16 +162,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { if (port == FM1_DTSEC9) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s1_p1"); + "sgmii-riser-s1-p1"); } else if (port == FM1_DTSEC2) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s2_p1"); + "sgmii-riser-s2-p1"); } else if (port == FM1_DTSEC5) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s3_p1"); + "sgmii-riser-s3-p1"); } else if (port == FM1_DTSEC6) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s4_p1"); + "sgmii-riser-s4-p1"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { @@ -191,19 +192,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p1"); + "qsgmii-s1-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p2"); + "qsgmii-s1-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p3"); + "qsgmii-s1-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p4"); + "qsgmii-s1-p4"); break; default: break; @@ -213,19 +214,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p1"); + "qsgmii-s2-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p2"); + "qsgmii-s2-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p3"); + "qsgmii-s2-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p4"); + "qsgmii-s2-p4"); break; default: break; @@ -268,16 +269,16 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); + fdt_status_okay_by_alias(fdt, "emi1-slot3"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig new file mode 100644 index 00000000000..6a4c3e92f7b --- /dev/null +++ b/board/freescale/ls1046afrwy/Kconfig @@ -0,0 +1,17 @@ + +if TARGET_LS1046AFRWY + +config SYS_BOARD + default "ls1046afrwy" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046afrwy" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS new file mode 100644 index 00000000000..357d23e70d3 --- /dev/null +++ b/board/freescale/ls1046afrwy/MAINTAINERS @@ -0,0 +1,7 @@ +LS1046AFRWY BOARD +M: Pramod Kumar <pramod.kumar_1@nxp.com> +S: Maintained +F: board/freescale/ls1046afrwy/ +F: board/freescale/ls1046afrwy/ls1046afrwy.c +F: include/configs/ls1046afrwy.h +F: configs/ls1046afrwy_tfa_defconfig diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile new file mode 100644 index 00000000000..c70f5cda797 --- /dev/null +++ b/board/freescale/ls1046afrwy/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 NXP + +obj-y += ddr.o +obj-y += ls1046afrwy.o +obj-$(CONFIG_NET) += eth.o diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README new file mode 100644 index 00000000000..d7b5a7794f6 --- /dev/null +++ b/board/freescale/ls1046afrwy/README @@ -0,0 +1,76 @@ +Overview +-------- +The LS1046A Freeway Board (iFRWY) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The FRWY-LS1046A provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + FRWY-LS1046A board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: Unused + - Lane2: QSGMII + - Lane3: Unused + - SERDES2 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: PCIe3 with PCIe x1 slot + - Lane2: Unused + - Lane3: PCIe3 with PCIe x1 slot + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One 512 MB NAND flash with ECC support + - USB 3.0 + - Two Type A port + - SDHC: connects directly to a full microSD slot + - QSPI: 64 MB high-speed flash Memory for boot code and storage + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +QSPI flash map: +Start Address End Address Description Size +0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB +0x00_4010_0000 - 0x00_404F_FFFF FIP Image + (Bl31 + BL32(optee. + bin) + Bl33(uboot) + + headers for secure + boot) 4MB +0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB +0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB +0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB +0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB +0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB +0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB + +Booting Options +--------------- +a) QSPI boot +b) microSD boot diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c new file mode 100644 index 00000000000..daf17e01693 --- /dev/null +++ b/board/freescale/ls1046afrwy/ddr.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c new file mode 100644 index 00000000000..9f8bd928509 --- /dev/null +++ b/board/freescale/ls1046afrwy/eth.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_dtsec.h> +#include <fsl_mdio.h> +#include <malloc.h> + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info dtsec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x3040: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(FM1_DTSEC6, dev); + fm_info_set_mdio(FM1_DTSEC5, dev); + fm_info_set_mdio(FM1_DTSEC10, dev); + fm_info_set_mdio(FM1_DTSEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + u32 srds_s1; + int i, prop; + int offset, nodeoff; + const char *path; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Cycle through all aliases */ + for (prop = 0; ; prop++) { + const char *name; + + /* FDT might have been edited, recompute the offset */ + offset = fdt_first_property_offset(blob, + fdt_path_offset(blob, + "/aliases") + ); + /* Select property number 'prop' */ + for (i = 0; i < prop; i++) + offset = fdt_next_property_offset(blob, offset); + + if (offset < 0) + break; + + path = fdt_getprop_by_offset(blob, offset, &name, NULL); + nodeoff = fdt_path_offset(blob, path); + + switch (srds_s1) { + case 0x3040: + if (!strcmp(name, "ethernet1")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet2")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet3")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet6")) + fdt_status_disabled(blob, nodeoff); + break; + default: + printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n", + __func__, srds_s1); + break; + } + } + + return 0; +} +#endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c new file mode 100644 index 00000000000..41412a76b69 --- /dev/null +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_sec.h> +#include <fsl_dspi.h> + +#define LS1046A_PORSR1_REG 0x1EE0000 +#define BOOT_SRC_SD 0x20000000 +#define BOOT_SRC_MASK 0xFF800000 +#define BOARD_REV_GPIO 13 +#define USB2_SEL_MASK 0x00000100 + +#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ +(((word) & 0x00ff0000) >> 8) | \ +(((word) & 0x0000ff00) << 8) | \ +(((word) & 0x000000ff) << 24)) +#define SPI_MCR_REG 0x2100000 + +DECLARE_GLOBAL_DATA_PTR; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static inline void demux_select_usb2(void) +{ + u32 val; + struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); + + val = in_be32(&pgpio->gpdir); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdir, val); + + val = in_be32(&pgpio->gpdat); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdat, val); +} + +static inline void set_spi_cs_signal_inactive(void) +{ + /* default: all CS signals inactive state is high */ + uint mcr_val; + uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + mcr_val = in_be32(SPI_MCR_REG); + mcr_val |= DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); + out_be32(SPI_MCR_REG, mcr_cfg_val); + mcr_val = in_be32(SPI_MCR_REG); + mcr_val &= ~DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +static inline uint8_t get_board_version(void) +{ + u8 val; + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03; + + return val; +} + +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; + u32 boot_src; + u8 rev; + + rev = get_board_version(); + switch (rev) { + case 0x00: + puts("Board: LS1046AFRWY, Rev: A, boot from "); + break; + case 0x01: + puts("Board: LS1046AFRWY, Rev: B, boot from "); + break; + default: + puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); + break; + } + boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); + + if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) + puts("SD\n"); + else + puts("QSPI\n"); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; +val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + /* + * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT + * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); +#ifdef CONFIG_HAS_FSL_IIC3 + /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x0000); +#endif + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#ifndef CONFIG_HAS_FSL_IIC3 + /* + * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input + * to select I2C3_USB2_SEL_IO + * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to + * I2C3 header (default) + * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to + * USB2 port + * programmed to select USB2 by setting GPIO3_23 output to one + */ + demux_select_usb2(); +#endif +#endif + set_spi_cs_signal_inactive(); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index abe8ee95d4e..1eb40677b50 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include <common.h> @@ -161,19 +161,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); break; case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); break; default: break; @@ -193,16 +193,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); break; default: break; @@ -246,13 +246,13 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 6109b280c68..3b4cb86692d 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -509,7 +509,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) { + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); fdt_fixup_board_phy(fdt); } else { diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c index c761aea0ac0..ef26f14c461 100644 --- a/board/freescale/t208xqds/pci.c +++ b/board/freescale/t208xqds/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c index 480933b3cc9..da33a0bd8a2 100644 --- a/board/renesas/sh7752evb/sh7752evb.c +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -174,6 +174,7 @@ int board_mmc_init(bd_t *bis) static int get_sh_eth_mac_raw(unsigned char *buf, int size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; @@ -190,6 +191,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size) return 1; } spi_flash_free(spi); +#endif return 0; } @@ -239,6 +241,7 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_DEPRECATED int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret; @@ -302,3 +305,4 @@ U_BOOT_CMD( "write MAC address for GETHERC", "[GETHERC ch0] [GETHERC ch1]\n" ); +#endif diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index dfdc6b79b7a..5ddddb65711 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -190,6 +190,7 @@ int board_mmc_init(bd_t *bis) static int get_sh_eth_mac_raw(unsigned char *buf, int size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; @@ -206,6 +207,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size) return 1; } spi_flash_free(spi); +#endif return 0; } @@ -255,6 +257,7 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_DEPRECATED int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret; @@ -318,3 +321,4 @@ U_BOOT_CMD( "write MAC address for GETHERC", "[GETHERC ch0] [GETHERC ch1]\n" ); +#endif diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c index 90c5508e439..3222701ad2d 100644 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -30,6 +30,7 @@ static void init_gctrl(void) static int init_pcie_bridge_from_spi(void *buf, size_t size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; unsigned long pcie_addr; @@ -54,6 +55,10 @@ static int init_pcie_bridge_from_spi(void *buf, size_t size) spi_flash_free(spi); return 0; +#else + printf("No SPI support so no PCIe support\n"); + return 1; +#endif } static void init_pcie_bridge(void) @@ -231,6 +236,7 @@ int board_mmc_init(bd_t *bis) static int get_sh_eth_mac_raw(unsigned char *buf, int size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; @@ -247,6 +253,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size) return 1; } spi_flash_free(spi); +#endif return 0; } @@ -352,6 +359,7 @@ U_BOOT_CMD( "enable SH-G200 bus (disable PCIe-G200)" ); +#ifdef CONFIG_DEPRECATED int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret; @@ -418,3 +426,4 @@ U_BOOT_CMD( "write MAC address for ETHERC/GETHERC", "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" ); +#endif diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 2ee6e462a61..c661d2e06ae 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig + +ROCK64-RK3328 +M: Matwey V. Kornilov <matwey.kornilov@gmail.com> +S: Maintained +F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index bf2ad98c473..eb1b832274a 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -6,46 +6,14 @@ #include <common.h> #include <dm.h> #include <dm/pinctrl.h> -#include <dm/uclass-internal.h> #include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { - struct udevice *pinctrl, *regulator; + struct udevice *regulator; int ret; - /* - * The PWM do not have decicated interrupt number in dts and can - * not get periph_id by pinctrl framework, so let's init them here. - * The PWM2 and PWM3 are for pwm regulater. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto out; - } - - /* Enable pwm0 for panel backlight */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0); - if (ret) { - debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); - if (ret) { - debug("%s PWM2 pinctrl init fail!\n", __func__); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); - if (ret) { - debug("%s PWM3 pinctrl init fail!\n", __func__); - goto out; - } - ret = regulators_enable_boot_on(false); if (ret) debug("%s: Cannot enable boot on regulator\n", __func__); @@ -65,30 +33,3 @@ int board_init(void) out: return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index f67dfb451ff..9b31b0b3790 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -60,7 +60,7 @@ Creating a SPL image for SD-Card/eMMC Creating a SPL image for SPI-NOR > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree - > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb + > make CROSS_COMPILE=aarch64-linux-gnu- Flash the image =============== diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its deleted file mode 100644 index 530f059f3da..00000000000 --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ -/* - * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH - * - * Minimal dts for a SPL FIT image payload. - */ - -/dts-v1/; - -/ { - description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot (64-bit)"; - data = /incbin/("../../../u-boot-nodtb.bin"); - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <0x00200000>; - }; - atf { - description = "ARM Trusted Firmware"; - data = /incbin/("../../../bl31-rk3399.bin"); - type = "firmware"; - arch = "arm64"; - os = "arm-trusted-firmware"; - compression = "none"; - load = <0x1000>; - entry = <0x1000>; - }; - pmu { - description = "Cortex-M0 firmware"; - data = /incbin/("../../../rk3399m0.bin"); - type = "pmu-firmware"; - compression = "none"; - load = <0x180000>; - }; - fdt { - description = "RK3399-Q7 (Puma) flat device-tree"; - data = /incbin/("../../../u-boot.dtb"); - type = "flat_dt"; - compression = "none"; - }; - }; - - configurations { - default = "conf"; - conf { - description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "atf"; - loadables = "uboot", "pmu"; - fdt = "fdt"; - }; - }; -}; diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh new file mode 100755 index 00000000000..420e7daf4ce --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh @@ -0,0 +1,94 @@ +#!/bin/sh +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> +# +# Based on the board/sunxi/mksunxi_fit_atf.sh +# +# Script to generate FIT image source for 64-bit puma boards with +# U-Boot proper, ATF, PMU firmware and devicetree. +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" + +if [ ! -f $BL31 ]; then + echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + BL31=/dev/null +fi + +[ -z "$PMUM0" ] && PMUM0="rk3399m0.bin" + +if [ ! -f $PMUM0 ]; then + echo "WARNING: PMUM0 file $PMUM0 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + PMUM0=/dev/null +fi + +cat << __HEADER_EOF +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * Minimal dts for a SPL FIT image payload. + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0x1000>; + entry = <0x1000>; + }; + pmu { + description = "Cortex-M0 firmware"; + data = /incbin/("$PMUM0"); + type = "pmu-firmware"; + compression = "none"; + load = <0x180000>; + }; + fdt { + description = "RK3399-Q7 (Puma) flat device-tree"; + data = /incbin/("u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; +__HEADER_EOF + +cat << __CONF_HEADER_EOF + }; + + configurations { + default = "conf"; + conf { + description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; + firmware = "atf"; + loadables = "uboot", "pmu"; + fdt = "fdt"; + }; +__CONF_HEADER_EOF + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c6b509c109c..251cd2d5667 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -13,10 +13,8 @@ #include <dm/pinctrl.h> #include <dm/uclass-internal.h> #include <asm/io.h> -#include <asm/gpio.h> #include <asm/setup.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/periph.h> @@ -38,62 +36,6 @@ int board_init(void) return 0; } -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} - -void spl_board_init(void) -{ - int ret; - struct rk3399_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); - - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - preloader_console_init(); -} - static void setup_macaddr(void) { #if CONFIG_IS_ENABLED(CMD_NET) diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README index d14399090e2..c5c675c4ead 100644 --- a/board/vamrs/rock960_rk3399/README +++ b/board/vamrs/rock960_rk3399/README @@ -61,7 +61,6 @@ Compile the U-Boot > export CROSS_COMPILE=aarch64-linux-gnu- > make rock960-rk3399_defconfig > make - > make u-boot.itb Compile the rkdeveloptool ========================= diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 0f5ef3a09a4..2eb7120e84b 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -5,11 +5,7 @@ #include <common.h> #include <dm.h> -#include <dm/pinctrl.h> -#include <dm/uclass-internal.h> -#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { @@ -21,30 +17,3 @@ int board_init(void) return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile index e3803bb0431..b837e7b0dd8 100644 --- a/board/work-microwave/work_92105/Makefile +++ b/board/work-microwave/work_92105/Makefile @@ -6,5 +6,6 @@ ifdef CONFIG_SPL_BUILD obj-y += work_92105_spl.o else -obj-y += work_92105.o work_92105_display.o +obj-y += work_92105.o +obj-$(CONFIG_DEPRECATED) += work_92105_display.o endif diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index eb2e7d7eb88..3f23af9ed40 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -52,8 +52,10 @@ int board_early_init_r(void) gpio_request(GPO_19, "NAND_nWP"); gpio_direction_output(GPO_19, 1); +#ifdef CONFIG_DEPRECATED /* initialize display */ work_92105_display_init(); +#endif return 0; } diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index e6fed25152a..efc1d356d6d 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -2,6 +2,7 @@ XILINX_ZYNQMP BOARDS M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: arch/arm/dts/zynqmp-* +F: arch/arm/dts/avnet-ultra96* F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig deleted file mode 100644 index c6635040a37..00000000000 --- a/board/zipitz2/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_ZIPITZ2 - -config SYS_BOARD - default "zipitz2" - -config SYS_CONFIG_NAME - default "zipitz2" - -endif diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS deleted file mode 100644 index e027cd361aa..00000000000 --- a/board/zipitz2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZIPITZ2 BOARD -M: Vasily Khoruzhick <anarsoul@gmail.com> -S: Maintained -F: board/zipitz2/ -F: include/configs/zipitz2.h -F: configs/zipitz2_defconfig diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile deleted file mode 100644 index 2bbe4364e8f..00000000000 --- a/board/zipitz2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2009 -# Marek Vasut <marek.vasut@gmail.com> -# -# Heavily based on pxa255_idp platform - -obj-y := zipitz2.o diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c deleted file mode 100644 index 9208c882c27..00000000000 --- a/board/zipitz2/zipitz2.c +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009 - * Marek Vasut <marek.vasut@gmail.com> - * - * Heavily based on pxa255_idp platform - */ - -#include <common.h> -#include <command.h> -#include <serial.h> -#include <asm/arch/hardware.h> -#include <asm/arch/pxa.h> -#include <asm/arch/regs-mmc.h> -#include <spi.h> -#include <asm/io.h> -#include <usb.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_SPI -void lcd_start(void); -#else -inline void lcd_start(void) {}; -#endif - -/* - * Miscelaneous platform dependent initialisations - */ -int board_init(void) -{ - /* arch number of Z2 */ - gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Enable LCD */ - lcd_start(); - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ -} -#endif - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -#ifdef CONFIG_CMD_SPI - -struct { - unsigned char reg; - unsigned short data; - unsigned char mdelay; -} lcd_data[] = { - { 0x07, 0x0000, 0 }, - { 0x13, 0x0000, 10 }, - { 0x11, 0x3004, 0 }, - { 0x14, 0x200F, 0 }, - { 0x10, 0x1a20, 0 }, - { 0x13, 0x0040, 50 }, - { 0x13, 0x0060, 0 }, - { 0x13, 0x0070, 200 }, - { 0x01, 0x0127, 0 }, - { 0x02, 0x0700, 0 }, - { 0x03, 0x1030, 0 }, - { 0x08, 0x0208, 0 }, - { 0x0B, 0x0620, 0 }, - { 0x0C, 0x0110, 0 }, - { 0x30, 0x0120, 0 }, - { 0x31, 0x0127, 0 }, - { 0x32, 0x0000, 0 }, - { 0x33, 0x0503, 0 }, - { 0x34, 0x0727, 0 }, - { 0x35, 0x0124, 0 }, - { 0x36, 0x0706, 0 }, - { 0x37, 0x0701, 0 }, - { 0x38, 0x0F00, 0 }, - { 0x39, 0x0F00, 0 }, - { 0x40, 0x0000, 0 }, - { 0x41, 0x0000, 0 }, - { 0x42, 0x013f, 0 }, - { 0x43, 0x0000, 0 }, - { 0x44, 0x013f, 0 }, - { 0x45, 0x0000, 0 }, - { 0x46, 0xef00, 0 }, - { 0x47, 0x013f, 0 }, - { 0x48, 0x0000, 0 }, - { 0x07, 0x0015, 30 }, - { 0x07, 0x0017, 0 }, - { 0x20, 0x0000, 0 }, - { 0x21, 0x0000, 0 }, - { 0x22, 0x0000, 0 }, -}; - -void zipitz2_spi_sda(int set) -{ - /* GPIO 13 */ - if (set) - writel((1 << 13), GPSR0); - else - writel((1 << 13), GPCR0); -} - -void zipitz2_spi_scl(int set) -{ - /* GPIO 22 */ - if (set) - writel((1 << 22), GPCR0); - else - writel((1 << 22), GPSR0); -} - -unsigned char zipitz2_spi_read(void) -{ - /* GPIO 40 */ - return !!(readl(GPLR1) & (1 << 8)); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Always valid */ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* GPIO 88 low */ - writel((1 << 24), GPCR2); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* GPIO 88 high */ - writel((1 << 24), GPSR2); -} - -void lcd_start(void) -{ - int i; - unsigned char reg[3] = { 0x74, 0x00, 0 }; - unsigned char data[3] = { 0x76, 0, 0 }; - unsigned char dummy[3] = { 0, 0, 0 }; - - /* PWM2 AF */ - writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); - /* Enable clock to all PWM */ - writel(readl(CKEN) | 0x3, CKEN); - /* Configure PWM2 */ - writel(0x4f, PWM_CTRL2); - writel(0x2ff, PWM_PWDUTY2); - writel(792, PWM_PERVAL2); - - /* Toggle the reset pin to reset the LCD */ - writel((1 << 19), GPSR0); - udelay(100000); - writel((1 << 19), GPCR0); - udelay(20000); - writel((1 << 19), GPSR0); - udelay(20000); - - /* Program the LCD init sequence */ - for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { - reg[0] = 0x74; - reg[1] = 0x0; - reg[2] = lcd_data[i].reg; - spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); - - data[0] = 0x76; - data[1] = lcd_data[i].data >> 8; - data[2] = lcd_data[i].data & 0xff; - spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); - - if (lcd_data[i].mdelay) - udelay(lcd_data[i].mdelay * 1000); - } - - writel((1 << 11), GPSR0); -} -#endif |