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diff --git a/board/AndesTech/adp-ag101/README b/board/AndesTech/adp-ag101/README new file mode 100644 index 00000000000..46fc6377422 --- /dev/null +++ b/board/AndesTech/adp-ag101/README @@ -0,0 +1,74 @@ +Andes Technology SoC AG101 +========================== + +AG101 is the first SoC produced by Andes Technology using N1213 CPU core. +AG101 has integrated both AHB and APB bus and many periphals for application +and product development. + +ADP-AG101 +========= + +ADP-AG101 is the SoC with AG101 hardcore CPU. + +Please check http://www.andestech.com/p2-4.htm for detail of this SoC. + +Configurations +============== + +CONFIG_MEM_REMAP: + Doing memory remap is essential for preparing some non-OS or RTOS + applications. + + This is also a must on ADP-AG101 board. + (While other boards may not have this problem). + + The reason is because the ROM/FLASH circuit on PCB board. + AG101-A0 board has 2 jumpers MA17 and SW5 to configure which + ROM/FLASH is used to boot. + + When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0, + and the FLASH is connected to BANK1. + When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0), + and the FLASH is connected to BANK0. + It will occur problem when doing flash probing if the flash is at + BANK0 (0x00000000) while memory remapping was skipped. + + Other board like ADP-AG101P may not enable this since there is only + a FLASH connected to bank0. + +CONFIG_SKIP_LOWLEVEL_INIT: + If you want to boot this system from FLASH and bypass e-bios (the + other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT + in "include/configs/adp-ag101.h". + +Build and boot steps +==================== + +build: +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make adp-ag101` in u-boot root to build the image. + +burn u-boot to flash: +1. Make sure the MA17 (J16) is Lo. +2. Make sure the dip switch SW5 is set to "0101". +3. Power On. Press button "S1", then press button "SW1", then you will found the + debug LED show 67 means the system successfully booted into e-bios. + Now you can control the e-bios boot loader from your console. +4. Under "Command>>" prompt, enter "97" (CopyImageFromCard) +5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c". +6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you + just build. It is usually "u-boot.bin". +7. Under "Enter Dest. Address =>" prompt, enter the memory address where you + want to put the binary from SD card to RAM. + Address "0x500000" is our suggestion. +8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command + environment. +9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the + binary from RAM to FLASH. +10. Under "CLI>" prompt, enter "exit" to finish the burn process. + +boot u-boot from flash: +1. Make sure the MA17 (J16) is Hi). +2. Make sure the dip switch SW5 is set to "1010". +3. Power On. Press button "S1", then you will see the debug LED count to 20. +4. Now you can use u-boot on ADP-AG101 board. diff --git a/board/Marvell/db64360/README b/board/Marvell/db64360/README new file mode 100644 index 00000000000..ebac4cec197 --- /dev/null +++ b/board/Marvell/db64360/README @@ -0,0 +1,105 @@ +This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360. + +Author: Ronen Shitrit <rshitrit@il.marvell.com> + +This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT. + +Supported CPU Types : ++++++++++++++++++++++ + IBM750FX (ver 2.3) + MPC7455 (ver 2.1) + +Supported CPU Cache Library: +++++++++++++++++++++++++++++ + L1 and L2 only. + +CPU Control: +++++++++++++ + Marvell optimized CPU control settings: + Big Endian + Enable CPU pipeline + Data and address parity checking + AACK# assert after 2 cycles + +U-Boot I/O Interface Support: ++++++++++++++++++++++++++++++ +- Serial Interface (UART) + This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. +- Network Interface + This LSP supports the following network devices: + o MV64360 Gigabit Ethernet Controller device + o Intel 82559 PCI NIC device +- PCI Interface + This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: + o Local PCI configuration header control. + o External PCI configuration header control (for other agents on the bus). + o PCI configuration application. Scans and configures the PCI agents on the bus. + o PCI Internal Arbiter activation and configuration. + +Memory Interface Support: ++++++++++++++++++++++++++ +- DDR + o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). + o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. + +- Devices + o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. + o JFFS2 + JFFS2 is a crash/power down safe file system for disk-less embedded devices. + This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. + +Unsupported Features: ++++++++++++++++++++++ + Messaging unit - No support for MV64360 Messaging unit. + Watchdog Timer - No support for MV64360 Watchdog unit. + L3 cache - No support for L3 cache on MPC7455 + Dual PCU - No support for Dual CPU + PCI-X was never tested + IDMA driver - No support for MV64360 IDMA unit. + +BSP Special Considerations: ++++++++++++++++++++++++++++ +- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. +- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. + +Test Cases: +########### +UART: ++++++ +Check that the UART baud rate is configured to 57600 and 115200, and check: + Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. + Load S-Record file over the UART using Windows HyperTerminal. + +Network: +++++++++ +Use TFTP application to load a debugged executable and execute it. +Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. + +Memory: ++++++++ +Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: +o 128MB DIMM consist of 16 x 64Mbit devices +o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. +o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. +o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. +o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered + +For each chip select device perform data access to verify its accessibility. + +Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. +Load the U-Boot and: +use the ls command to check correct scan of the JFFS2 on the large flash. +Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. + +PCI: +++++ +1)Insert different PCI cards: +Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 +on different slots (0-3) of the PCI and check: +o Correct detection of the PCI devices. +o Correct address mapping of the PCI devices. +2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. + +Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/board/Marvell/db64460/README b/board/Marvell/db64460/README new file mode 100644 index 00000000000..c6e01fe1efb --- /dev/null +++ b/board/Marvell/db64460/README @@ -0,0 +1,105 @@ +This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460. + +Author: Ronen Shitrit <rshitrit@il.marvell.com> + + +Supported CPU Types : ++++++++++++++++++++++ +IBM750Gx Rev 1.0 +MPC7457 Rev 1.1 + +Supported CPU Cache Library: +++++++++++++++++++++++++++++ + L1 and L2 only. + +CPU Control: +++++++++++++ + Marvell optimized CPU control settings: + Big Endian + Enable CPU pipeline + Data and address parity checking + AACK# assert after 2 cycles + +U-Boot I/O Interface Support: ++++++++++++++++++++++++++++++ +- Serial Interface (UART) + This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. +- Network Interface + This LSP supports the following network devices: + o MV64360 Gigabit Ethernet Controller device + o Intel 82559 PCI NIC device +- PCI Interface + This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: + o Local PCI configuration header control. + o External PCI configuration header control (for other agents on the bus). + o PCI configuration application. Scans and configures the PCI agents on the bus. + o PCI Internal Arbiter activation and configuration. + +Memory Interface Support: ++++++++++++++++++++++++++ +- DDR + o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). + o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. + +- Devices + o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. + o JFFS2 + JFFS2 is a crash/power down safe file system for disk-less embedded devices. + This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. + +Unsupported Features: ++++++++++++++++++++++ + Messaging unit - No support for MV64360 Messaging unit. + Watchdog Timer - No support for MV64360 Watchdog unit. + L3 cache - No support for L3 cache on MPC7455 + Dual PCU - No support for Dual CPU + PCI-X was never tested + IDMA driver - No support for MV64360 IDMA unit. + XOR Engine - No support for MV64460 XOR Engine + +BSP Special Considerations: ++++++++++++++++++++++++++++ +- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. +- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. + +Test Cases: +########### +UART: ++++++ +Check that the UART baud rate is configured to 57600 and 115200, and check: + Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. + Load S-Record file over the UART using Windows HyperTerminal. + +Network: +++++++++ +Use TFTP application to load a debugged executable and execute it. +Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. + +Memory: ++++++++ +Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: +o 128MB DIMM consist of 16 x 64Mbit devices +o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. +o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. +o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. +o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. +o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered + +For each chip select device perform data access to verify its accessibility. + +Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. +Load the U-Boot and: +use the ls command to check correct scan of the JFFS2 on the large flash. +Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. + +PCI: +++++ +1)Insert different PCI cards: +Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 +on different slots (0-3) of the PCI and check: +o Correct detection of the PCI devices. +o Correct address mapping of the PCI devices. +2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. + +Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/board/RPXClassic/README b/board/RPXClassic/README new file mode 100644 index 00000000000..e03f670d1c1 --- /dev/null +++ b/board/RPXClassic/README @@ -0,0 +1,19 @@ +# Porting U-Boot onto RPXClassic LF_BW31 board +# Written by Pierre AUBERT +# E-Mail p.aubert@staubli.com +# Stäubli Faverges - <www.staubli.com> +# +# Sept. 20 2001 +# +# Cross compile: Montavista Hardhat ported on HP-UX 10.20 +# + +Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 +DRAM : 16 Mb from 0 +NVRAM : 512 kb from 0xfa000000 + + +- environment is stored in NVRAM +- Mac address is read from EEPROM +- ethernet on SCC1 or fast ethernet on FEC are running (depending on the + configuration flag CONFIG_FEC_ENET) diff --git a/board/RPXlite/README b/board/RPXlite/README new file mode 100644 index 00000000000..3ca671126d4 --- /dev/null +++ b/board/RPXlite/README @@ -0,0 +1,877 @@ +# Porting U-Boot onto RPXlite board +# Written by Yoo. Jonghoon +# E-Mail : yooth@ipone.co.kr +# IP ONE Inc. + +# Since 2001. 1. 29 + +# Shell : bash +# Cross-compile tools : Montavista Hardhat +# Debugging tools : Windriver VisionProbe (PowerPC BDM) +# ppcboot ver. : ppcboot-0.8.1 + +############################################################### +# 1. Hardware setting +############################################################### + +1.1. Board, BDM settings + Install board, BDM, connect each other + +1.2. Save Register value + Boot with board-on monitor program and save the + register values with BDM. + +1.3. Configure flash programmer + Check flash memory area in the memory map. + 0xFFC00000 - 0xFFFFFFFF + + Boot monitor program is at + 0xFFF00000 + + You can program on-board flash memory with VisionClick + flash programmer. Set the target flash device as: + + 29DL800B + + (?) The flash memory device in the board *is* 29LV800B, + but I cannot program it with '29LV800B' option. + (in VisionClick flash programming tools) + I don't know why... + +1.4. Save boot monitor program *IMPORTANT* + Upload boot monitor program from board to file. + boot monitor program starts at 0xFFF00000 + +1.5. Test flash memory programming + Try to erase boot program in the flash memory, + and re-write them. + *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE + BEFORE ERASING FLASH + +############################################################### +# 2. U-Boot setting +############################################################### + +2.1. Download U-Boot tarball at + ftp://ftp.denx.de + (The latest version is ppcboot-0.8.1.tar.bz2) + + To extract the archive use the following syntax : + > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - + +2.2. Add the following lines in '.profile' + export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin + +2.3. Make board specific config, for example: + > cd ppcboot-0.8.1 + > make TQM860L_config + + Now we can build ppcboot bin files. + After make all, you must see these files in your + ppcboot root directory. + + ppcboot + ppcboot.bin + ppcboot.srec + ppcboot.map + +2.4. Make your own board directory into the + ppcboot-0.8.1/board + and make your board-specific files here. + + For exmanple, tqm8xx files are composed of + .depend : Nothing + Makefile : To make config file + config.mk : Sets base address + flash.c : Flash memory control files + ppcboot.lds : linker(ld) script? (I don't know this yet) + tqm8xx.c : DRAM control and board check routines + + And, add your board config lines in the + ppcboot-0.8.1/Makefile + + Finally, add config_(your board).h file in the + ppcboot-0.8.1/include/ + + I've made board/rpxlite directory, and just copied + tqm8xx settings for now. + + Rebuild ppcboot for rpxlite board: + > make rpxlite_config + > make + +############################################################### +# 3. U-Boot porting +############################################################### + +3.1. My RPXlite files are based on tqm8xx board files. + > cd board + > cp -r tqm8xx RPXLITE + > cd RPXLITE + > mv tqm8xx.c RPXLITE.c + > cd ../../include + > cp config_tqm8xx.h config_RPXLITE.h + +3.2. Modified files are: + board/RPXLITE/RPXLITE.c /* DRAM-related routines */ + board/RPXLITE/flash.c /* flash-related routines */ + board/RPXLITE/config.mk /* set text base address */ + arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ + include/config_RPXLITE.h /* board specific registers */ + + See 'reg_config.txt' for register values in detail. + +############################################################### +# 4. Running Linux +############################################################### + + +############################################################### +# Misc Information +############################################################### + +mem_config.txt: +=============== + +Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device +manufacturer id : 01 (AMD) +device id : 5B (AM29LV800B) +size : 4Mbyte +sector # : 19 + +Sector information : + +number start addr. size +00 FFC0_0000 64 +01 FFC1_0000 32 +02 FFC1_8000 32 +03 FFC2_0000 128 +04 FFC4_0000 256 +05 FFC8_0000 256 +06 FFCC_0000 256 +07 FFD0_0000 256 +08 FFD4_0000 256 +09 FFD8_0000 256 +10 FFDC_0000 256 +11 FFE0_0000 256 +12 FFE4_0000 256 +13 FFE8_0000 256 +14 FFEC_0000 256 +15 FFF0_0000 256 +16 FFF4_0000 256 +17 FFF8_0000 256 +18 FFFC_0000 256 + + +reg_config.txt: +=============== + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* SIU (System Interface Unit) */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ + + +/*### IMMR */ +/*### Internal Memory Map Register */ +/*### Chap. 11.4.1 */ + + ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ + PARTNUM = 0x21 + MASKNUM = 0x00 + + => 0xFA20 2100 + +--------------------------------------------------------------------- + +/*### SIUMCR */ +/*### SIU Module Configuration Register */ +/*### Chap. 11.4.2 */ +/*### Offset : 0x0000 0000 */ + + EARB = 0 + EARP = 0 + DSHW = 0 + DBGC = 0 + DBPC = 0 + FRC = 0 + DLK = 0 + OPAR = 0 + PNCS = 0 + DPC = 0 + MPRE = 0 + MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ + AEME = 0 + SEME = 0 + BSC = 0 + GB5E = 0 + B2DD = 0 + B3DD = 0 + + => 0x0000 0800 + +--------------------------------------------------------------------- + +/*### SYPCR */ +/*### System Protection Control Register */ +/*### Chap. 11.4.3 */ +/*### Offset : 0x0000 0004 */ + + SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ + BMT = 0x06 /* BUS monitoring timing */ + BME = 1 /* BUS monitor enable */ + SWF = 1 + SWE = 0 /* SW watchdog disable */ + SWRI = 0 + SWP = 1 + + => 0xFFFF 0689 + +--------------------------------------------------------------------- + +/*### TESR */ +/*### Transfer Error Status Register */ +/*### Chap. 11.4.4 */ +/*### Offset : 0x0000 0020 */ + + IEXT = 0 + ITMT = 0 + IPB = 0000 + DEXT = 0 + DTMT = 0 + DPB = 0000 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIPEND */ +/*### SIU Interrupt Pending Register */ +/*### Chap. 11.5.4.1 */ +/*### Offset : 0x0000 0010 */ + + IRQ0~IRQ7 = 0 + LVL0~LVL7 = 0 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIMASK */ +/*### SIU Interrupt Mask Register */ +/*### Chap. 11.5.4.2 */ +/*### Offset : 0x0000 0014 */ + + IRM0~IRM7 = 0 /* Mask all interrupts */ + LVL0~LVL7 = 0 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIEL */ +/*### SIU Interrupt Edge/Level Register */ +/*### Chap. 11.5.4.3 */ +/*### Offset : 0x0000 0018 */ + + ED0~ED7 = 0 /* Low level triggered */ + WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIVEC */ +/*### SIU Interrupt Vector Register */ +/*### Chap. 11.5.4.4 */ +/*### Offset : 0x0000 001C */ + + INTC = 3C /* The lowest interrupt is pending..(?) */ + + => 0x3C00 0000 + +--------------------------------------------------------------------- + +/*### SWSR */ +/*### Software Service Register */ +/*### Chap. 11.7.1 */ +/*### Offset : 0x0000 001E */ + + SEQ = 0 + + => 0x0000 + +--------------------------------------------------------------------- + +/*### SDCR */ +/*### SDMA Configuration Register */ +/*### Chap. 20.2.1 */ +/*### Offset : 0x0000 0032 */ + + FRZ = 0 + RAID = 01 /* Priority level 5 (BR5) (normal operation) */ + + => 0x0000 0001 + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* UPMA (User Programmable Machine A) */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ + +/*### Chap. 16.6.4.1 */ +/*### Offset = 0x0000 017c */ + + T0 = CFFF CC24 /* Single Read */ + T1 = 0FFF CC04 + T2 = 0CAF CC04 + T3 = 03AF CC08 + T4 = 3FBF CC27 /* last */ + T5 = FFFF CC25 + T6 = FFFF CC25 + T7 = FFFF CC25 + T8 = CFFF CC24 /* Burst Read */ + T9 = 0FFF CC04 + T10 = 0CAF CC84 + T11 = 03AF CC88 + T12 = 3FBF CC27 /* last */ + T13 = FFFF CC25 + T14 = FFFF CC25 + T15 = FFFF CC25 + T16 = FFFF CC25 + T17 = FFFF CC25 + T18 = FFFF CC25 + T19 = FFFF CC25 + T20 = FFFF CC25 + T21 = FFFF CC25 + T22 = FFFF CC25 + T23 = FFFF CC25 + T24 = CFFF CC24 /* Single Write */ + T25 = 0FFF CC04 + T26 = 0CFF CC04 + T27 = 03FF CC00 + T28 = 3FFF CC27 /* last */ + T29 = FFFF CC25 + T30 = FFFF CC25 + T31 = FFFF CC25 + T32 = CFFF CC24 /* Burst Write */ + T33 = 0FFF CC04 + T34 = 0CFF CC80 + T35 = 03FF CC8C + T36 = 0CFF CC00 + T37 = 33FF CC27 /* last */ + T38 = FFFF CC25 + T39 = FFFF CC25 + T40 = FFFF CC25 + T41 = FFFF CC25 + T42 = FFFF CC25 + T43 = FFFF CC25 + T44 = FFFF CC25 + T45 = FFFF CC25 + T46 = FFFF CC25 + T47 = FFFF CC25 + T48 = C0FF CC24 /* Refresh */ + T49 = 03FF CC24 + T50 = 0FFF CC24 + T51 = 0FFF CC24 + T52 = 3FFF CC27 /* last */ + T53 = FFFF CC25 + T54 = FFFF CC25 + T55 = FFFF CC25 + T56 = FFFF CC25 + T57 = FFFF CC25 + T58 = FFFF CC25 + T59 = FFFF CC25 + T60 = FFFF CC25 /* Exception */ + T61 = FFFF CC25 + T62 = FFFF CC25 + T63 = FFFF CC25 + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* UPMB */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### Chap. 16.6.4.1 */ + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* MEMC */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### BR0 & OR0 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ +/*### Flash memory */ + + BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFE00 0001 + + AM = 1111 1110 0000 0000 0 /* 32MBytes */ + ATM = 000 + CSNT/SAM = 0 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0100 /* cycle length = 4 */ + SETA = 0 + TRLX = 0 + EHTR = 0 + + => 0xFE00 0140 + +/*### BR1 & OR1 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ +/*### SDRAM */ + + BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 1 /* UPMA */ + V = 1 /* Valid */ + + => 0x0000 0081 + + AM = 1111 1110 0000 0000 /* 32MBytes */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 11 + BIH = 0 + SCY = 0000 /* cycle length = 0 */ + SETA = 0 + TRLX = 0 + EHTR = 0 + + => 0xFE00 0E00 + +/*### BR2 & OR2 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ + + BR2 & OR2 = 0x0000 0000 /* Not used */ + +/*### BR3 & OR3 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ +/*### BCSR */ + + BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFA40 0001 + + AM = 1111 1111 0111 1111 1 /* (?) */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0001 /* cycle length = 1 */ + SETA = 0 + TRLX = 0 + + => 0xFF7F 8910 + +/*### BR4 & OR4 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ +/*### NVRAM & SRAM */ + + BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ + AT = 000 + PS = 01 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFA00 0401 + + AM = 1111 1111 1111 1000 0 /* 8MByte */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0111 /* cycle length = 7 */ + SETA = 0 + TRLX = 0 + + => 0xFFF8 0970 + +/*### BR5 & OR5 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ + + BR5 & OR5 = 0x0000 0000 /* Not used */ + +/*### BR6 & OR6 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ + + BR6 & OR6 = 0x0000 0000 /* Not used */ + +/*### BR7 & OR7 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ + + BR7 & OR7 = 0x0000 0000 /* Not used */ + +/*### MAR */ +/*### Memory Address Register */ +/*### Chap. 16.4.7 */ +/*### Offset : 0x0000 0164 */ + + MA = External memory address + +/*### MCR */ +/*### Memory Command Register */ +/*### Chap. 16.4.5 */ +/*### Offset : 0x0000 0168 */ + + OP = xx /* Command op code */ + UM = 1 /* Select UPMA */ + MB = 001 /* Select CS1 */ + MCLF = xxxx /* Loop times */ + MAD = xx xxxx /* Memory array index */ + +/*### MAMR */ +/*### Machine A Mode Register */ +/*### Chap. 16.4.4 */ +/*### Offset : 0x0000 0170 */ + + PTA = 0101 1000 + PTAE = 1 /* Periodic timer A enabled */ + AMA = 010 + DSA = 00 + G0CLA = 000 + GPLA4DIS = 1 + RLFA = 0100 + WLFA = 0011 + TLFA = 0000 + + => 0x58A0 1430 + +/*### MBMR */ +/*### Machine B Mode Register */ +/*### Chap. 16.4.4 */ +/*### Offset : 0x0000 0174 */ + + PTA = 0100 1110 + PTAE = 0 /* Periodic timer B disabled */ + AMA = 000 + DSA = 00 + G0CLA = 000 + GPLA4DIS = 1 + RLFA = 0000 + WLFA = 0000 + TLFA = 0000 + + => 0x4E00 1000 + +/*### MSTAT */ +/*### Memory Status Register */ +/*### Chap. 16.4.3 */ +/*### Offset : 0x0000 0178 */ + + PER0~PER7 = Parity error + WPER = Write protection error + + => 0x0000 + +/*### MPTPR */ +/*### Memory Periodic Timer Prescaler Register */ +/*### Chap. 16.4.8 */ +/*### Offset : 0x0000 017A */ + + PTP = 0000 1000 /* Divide by 8 */ + + => 0x0800 + +/*### MDR */ +/*### Memory Data Register */ +/*### Chap. 16.4.6 */ +/*### Offset : 0x0000 017C */ + + MD = Memory data contains the RAM array word + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* TIMERS */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### TBREFx */ +/*### Timebase Reference Registers */ +/*### Chap. 11.9.2 */ +/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ +/*### (Locked) */ + + TBREFF0 = 0xFFFF FFFF + TBREFF1 = 0xFFFF FFFF + +--------------------------------------------------------------------- + +/*### TBSCR */ +/*### Timebase Status and Control Registers */ +/*### Chap. 11.9.3 */ +/*### Offset : 0x0000 0200 */ +/*### (Locked) */ + + TBIRQ = 00000000 + REF0 = 0 + REF1 = 0 + REFE0 = 0 /* Reference interrupt disable */ + REFE1 = 0 + TBF = 1 + TBE = 1 /* Timebase enable */ + + => 0x0003 + +--------------------------------------------------------------------- + +/*### RTCSC */ +/*### Real-Time Clock Status and Control Registers */ +/*### Chap. 11.10.1 */ +/*### Offset : 0x0000 0220 */ +/*### (Locked) */ + + RTCIRQ = 00000000 + SEC = 1 + ALR = 0 + 38K = 0 /* PITRTCLK is driven by 32.768KHz */ + SIE = 0 + ALE = 0 + RTF = 0 + RTE = 1 /* Real-Time clock enabled */ + + => 0x0081 + +--------------------------------------------------------------------- + +/*### RTC */ +/*### Real-Time Clock Registers */ +/*### Chap. 11.10.2 */ +/*### Offset : 0x0000 0224 */ +/*### (Locked) */ + + RTC = Real time clock measured in second + +--------------------------------------------------------------------- + +/*### RTCAL */ +/*### Real-Time Clock Alarm Registers */ +/*### Chap. 11.10.3 */ +/*### Offset : 0x0000 022C */ +/*### (Locked) */ + + ALARM = 0xFFFF FFFF + +--------------------------------------------------------------------- + +/*### RTSEC */ +/*### Real-Time Clock Alarm Second Registers */ +/*### Chap. 11.10.4 */ +/*### Offset : 0x0000 0228 */ +/*### (Locked) */ + + COUNTER = Counter bits(fraction of a second) + +--------------------------------------------------------------------- + +/*### PISCR */ +/*### Periodic Interrupt Status and Control Register */ +/*### Chap. 11.11.1 */ +/*### Offset : 0x0000 0240 */ +/*### (Locked) */ + + PIRQ = 0 + PS = 0 /* Write 1 to clear */ + PIE = 0 + PITF = 1 + PTE = 0 /* PIT disabled */ + +--------------------------------------------------------------------- + +/*### PITC */ +/*### PIT Count Register */ +/*### Chap. 11.11.2 */ +/*### Offset : 0x0000 0244 */ +/*### (Locked) */ + + PITC = PIT count + +--------------------------------------------------------------------- + +/*### PITR */ +/*### PIT Register */ +/*### Chap. 11.11.3 */ +/*### Offset : 0x0000 0248 */ +/*### (Locked) */ + + PIT = PIT count /* Read only */ + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* CLOCKS */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + + +--------------------------------------------------------------------- + +/*### SCCR */ +/*### System Clock and Reset Control Register */ +/*### Chap. 15.6.1 */ +/*### Offset : 0x0000 0280 */ +/*### (Locked) */ + + COM = 11 /* Clock output disabled */ + TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ + RTDIV = 0 /* The clock is divided by 4 */ + RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ + CRQEN = 0 + PRQEN = 0 + EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ + DFSYNC = 00 /* Divided by 1 (normal operation) */ + DFBRG = 00 /* Divided by 1 (normal operation) */ + DFNL = 000 + DFNH = 000 + + => 0x6200 0000 + +--------------------------------------------------------------------- + +/*### PLPRCR */ +/*### PLL, Low-Power, and Reset Control Register */ +/*### Chap. 15.6.2 */ +/*### Offset : 0x0000 0284 */ +/*### (Locked) */ + + MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ + SPLSS = 0 + TEXPS = 0 + TMIST = 0 + CSRC = 0 /* The general system clock is generated by the DFNH field */ + LPM = 00 /* Normal high/normal low mode */ + CSR = 0 + LOLRE = 0 + FIOPD = 0 + + => 0x0050 0000 + +--------------------------------------------------------------------- + +/*### RSR */ +/*### Reset Status Register */ +/*### Chap. 12.2 */ +/*### Offset : 0x0000 0288 */ +/*### (Locked) */ + + EHRS = External hard reset + ESRS = External soft reset + LLRS = Loss-of-lock reset + SWRS = Software watchdog reset + CSRS = Check stop reset + DBHRS = Debug port hard reset + DBSRS = Debug port soft reset + JTRS = JTAG reset + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* DMA */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### SDSR */ +/*### SDMA Status Register */ +/*### Chap. 20.2.2 */ +/*### Offset : 0x0000 0908 */ + + SBER = 0 /* SDMA channel bus error */ + DSP2 = 0 /* DSP chain2 (Tx) interrupt */ + DSP1 = 0 /* DSP chain1 (Rx) interrupt */ + + => 0x00 + +/*### SDMR */ +/*### SDMA Mask Register */ +/*### Chap. 20.2.3 */ +/*### Offset : 0x0000 090C */ + + SBER = 0 + DSP2 = 0 + DSP1 = 0 /* All interrupts are masked */ + + => 0x00 + +/*### SDAR */ +/*### SDMA Address Register */ +/*### Chap. 20.2.4 */ +/*### Offset : 0x0000 0904 */ + + AR = 0xxxxx xxxx /* current system address */ + + => 0xFA20 23AC + +/*### IDSRx */ +/*### IDMA Status Register */ +/*### Chap. 20.3.3.2 */ +/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ + + AD = 0 + DONE = 0 + OB = 0 + + => 0x00 + +/*### IDMRx */ +/*### IDMA Mask Register */ +/*### Chap. 20.3.3.3 */ +/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ + + AD = 0 + DONE = 0 + OB = 0 diff --git a/board/RPXlite/README.PlanetCore b/board/RPXlite/README.PlanetCore new file mode 100644 index 00000000000..b73c5f5a87d --- /dev/null +++ b/board/RPXlite/README.PlanetCore @@ -0,0 +1,163 @@ +After several heart-struck failure, I got one workable way to program +each other in FLASH between PlanetCore and U-Boot. + +Hardware Platform : RPXlite DW(EP 823 H1 DW) + +1. From U-Boot to PlanetCore + +Utilities : PlanetCore Boot Loader - PCL200.mot + +[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot +PCL200.mot pcl200.bin + +[Target Operation] +u-boot>t 100000 pcl200.bin +u-boot>go 0x100000 +## Starting application at 0x00100000 ... + +MPC8xx PlanetCore Flash Burner v2.00 +Copyright 2001 Embedded Planet. All rights reserved. + +Construct Flash Device.....done. + + +Program MPC8xx PlanetCore Boot Loader v2.00 +Built Sep 19, 2001 at 14:34:42 +Image located from FC000000 to FC01B5D1. +(Skipping an image, only loading low boot image) + +Low boot board detected, skipping high boot image. +Erasing, programming and verifying will start in 20 +seconds +Press P to start immediately or ESC to cancel +Press Space or Enter for more options. +.............. + +Erasing +Programming +FLASH programmed successfully! +Press R to induce a hard reset + +MPC8xx PlanetCore Boot Loader v2.00 +Copyright 2001 Embedded Planet. All rights reserved. +DRAM available size = 64 MB +wvCV +DRAM OK +> + +2. From PlanetCore to U-Boot + +Utilities : PlanetCore FLASH Burner - PCB200.mot + +Use Flash Burner to finish the work: + +First, TFTP the U-Boot image file to RAM; For example, +RPXlite_DW.bin to 0x400000 +Second, TFTP FLASH Burner to RAM; For example, +0x100000 +Third, run the FLASH Burner and Program the U-Boot +image into the correct location in FLASH. + +[Target Operation] +MPC8xx PlanetCore Boot Loader v2.00 +Copyright 2001 Embedded Planet. All rights reserved. +DRAM available size = 64 MB +wvCV +DRAM OK +>t +Load using tftp via Ethernet +Enter server IP address <172.16.115.6> : +Enter server filename <PCL200.mot> : RPXlite_DW.bin +Enter (B)inary or (S)record input mode <S> : B +Enter address offset : <00400000 hex> : + +Total bytes = 120096 in 232184 uSecs +Loaded addresses 00400000 through 0041D51F. +Start address = 00400000 +>t +Load using tftp via Ethernet +Enter server IP address <172.16.115.6> : +Enter server filename <RPXlite_DW.bin> : PCB200.mot +Enter (B)inary or (S)record input mode <B> : S +Enter address offset : <00000000 hex> : +.512.1024..2048....4096..... +Total bytes = 326280 in 2570249 uSecs +Loaded addresses 00100000 through 0011BB51. +Start address = 00100000 +>go +[Go 00100000] + +MPC8xx PlanetCore Flash Burner v2.00 +Copyright 2001 Embedded Planet. All rights reserved. + +Construct Flash Device.....done. + +Bad start address +Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = +0xFFFFFFFF +Forcing Menu Interface + +h[elp] Show commands. +c[ode] Show information on code to be loaded. +di[splay] Display all flash sections. +du[mp] Dump memory. d ? for more info. +e[rase] Erase flash sections. +f[ill] Fill flash sections. +im[age] Toggle load high, low, or both flash +images. +in[fo] Show flash information. +ma[p] Show memory map. +mo[dify] Modify memory. m ? for more info. +p[rogram] Erase, program, and verify now. +reset Restart the loader. +s[how] Show flash sections to erase and program. +t[est] Test flash sections. +q[uit] Quit without programming. +#program 400000 ff000000 1D51F +doProgram( 400000 ff000000 1D51F ) + +Start = 0x00400000, target = 0xFF000000, length = +0x0001D51F +Erasing sector 0xFF000000, length 0x008000. +Erasing sector 0xFF008000, length 0x008000. +Erasing sector 0xFF010000, length 0x008000. +Erasing sector 0xFF018000, length 0x008000. +Programming FF000000 through FF01D51E +FLASH programmed successfully! +Press R to induce a hard reset + +Forcing Hard Reset by MachineCheck and +ResetOnCheckstop... + +U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) + +CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB +D-Cache +Board: RPXlite_DW +DRAM: 64 MB +FLASH: 16 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET +u-boot> + +------------------------------------------------- + +Well, sometimes network function of PlanetCore couldn't work when +switching from U-Boot to PlanetCore. For example, you couldn't +download a file from HOST PC via TFTP. Don't worry, just restart your +HOST PC and everything would work as smooth as clockwork. I don't +know the reason WHY:-) + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Merry Christmas and Happy New Year! + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +===== +Best regards, + +Sam diff --git a/board/alaska/README b/board/alaska/README new file mode 100644 index 00000000000..334507397d5 --- /dev/null +++ b/board/alaska/README @@ -0,0 +1,482 @@ +Freescale Alaska MPC8220 board +============================== + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 9/21/04 +=========================================== + + +Changed files: +============== + +- Makefile added MPC8220 and Alaska8220_config +- MAKEALL added MPC8220 and Alaska8220 +- README added CONFIG_MPC8220, Alaska8220_config + +- common/cmd_bdinfo.c added board information members for MPC8220 +- common/cmd_bootm.c added clocks for MPC8220 in do_bootm_linux() + +- include/common.h added CONFIG_MPC8220 + +- include/asm-ppc/u-boot.h added board information members for MPC8220 +- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk, + vco_clk, pev_clk, flb_clk, and bExtUart + +- arch/powerpc/lib/board.c added CONFIG_MPC8220 support + +- net/eth.c added FEC support for MPC8220 + +Added files: +============ +- board/alaska directory for Alaska MPC8220 +- board/alaska/alaska.c Alaska dram and BATs setup +- board/alaska/extserial.c external serial (debug card serial) support +- board/alaska/flash.c Socket (AMD) and Onboard (INTEL) flash support +- board/alaska/serial.c to determine which int/ext serial to use +- board/alaska/Makefile Makefile +- board/alaska/config.mk config make +- board/alaska/u-boot.lds Linker description + +- arch/powerpc/cpu/mpc8220/dma.h multi-channel dma header file +- arch/powerpc/cpu/mpc8220/dramSetup.h dram setup header file +- arch/powerpc/cpu/mpc8220/fec.h MPC8220 FEC header file +- arch/powerpc/cpu/mpc8220/cpu.c cpu specific code +- arch/powerpc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup +- arch/powerpc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup +- arch/powerpc/cpu/mpc8220/fec.c MPC8220 FEC driver +- arch/powerpc/cpu/mpc8220/i2c.c MPC8220 I2C driver +- arch/powerpc/cpu/mpc8220/interrupts.c interrupt support (not enable) +- arch/powerpc/cpu/mpc8220/loadtask.c load dma +- arch/powerpc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock +- arch/powerpc/cpu/mpc8220/traps.c exception +- arch/powerpc/cpu/mpc8220/uart.c MPC8220 UART driver +- arch/powerpc/cpu/mpc8220/Makefile Makefile +- arch/powerpc/cpu/mpc8220/config.mk config make +- arch/powerpc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program +- arch/powerpc/cpu/mpc8220/io.S io functions +- arch/powerpc/cpu/mpc8220/start.S start up + +- include/mpc8220.h + +- include/asm-ppc/immap_8220.h + +- include/configs/Alaska8220.h + + +1. SWITCH SETTINGS +================== +1.1 SW1: 0 - Boot from Socket Flash (AMD) or 1 - Onboard Flash (INTEL) + SW2: 0 - Select MPC8220 UART or 1 - Debug Card UART + SW3: unsed + SW4: 0 - 1284 or 1 - FEC1 + SW5: 0 - PEV or 1 - FEC2 + + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + DDR: 0x00000000-0x1fffffff (max 512MB) + MBAR: 0xf0000000-0xf0027fff (128KB) + CPLD: 0xf1000000-0xf103ffff (256KB) + FPGA: 0xf2000000-0xf203ffff (256KB) + Flash: 0xfe000000-0xffffffff (max 32MB) + +3. DEFINITIONS AND COMPILATION +============================== +3.1 Explanation on NEW definitions in include/configs/alaska8220.h + CONFIG_MPC8220 MPC8220 specific + CONFIG_ALASKA8220 Alaska board specific + CONFIG_SYS_MPC8220_CLKIN Define Alaska Input Clock + CONFIG_PSC_CONSOLE Enable MPC8220 UART + CONFIG_EXTUART_CONSOLE Enable External 16552 UART + CONFIG_SYS_AMD_BOOT To determine the u-boot is booted from AMD or Intel + CONFIG_SYS_MBAR MBAR base address + CONFIG_SYS_DEFAULT_MBAR Reset MBAR base address + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1-1-x + make distclean + make Alaska8220_config + make + + +4. SCREEN DUMP +============== +4.1 Alaska MPC8220 board + Boot from AMD (NOTE: May not show exactly the same) + +U-Boot 1.1.1 (Sep 22 2004 - 22:14:41) + +CPU: MPC8220 (JTAG ID 1640301d) at 300 MHz + Bus 120 MHz, CPU 300 MHz, PCI 30 MHz, VCO 480 MHz +Board: Alaska MPC8220 Evaluation Board +I2C: 93 kHz, ready +DRAM: 256 MB +Reserving 167k for U-Boot at: 0ffd6000 +FLASH: 16.5 MB +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: FEC ETHERNET +=> flinfo + +Bank # 1: INTEL 28F128J3A + Size: 8 MB in 64 Sectors + Sector Start Addresses: + FE000000 FE020000 FE040000 FE060000 FE080000 + FE0A0000 FE0C0000 FE0E0000 FE100000 FE120000 + FE140000 FE160000 FE180000 FE1A0000 FE1C0000 + FE1E0000 FE200000 FE220000 FE240000 FE260000 + FE280000 FE2A0000 FE2C0000 FE2E0000 FE300000 + FE320000 FE340000 FE360000 FE380000 FE3A0000 + FE3C0000 FE3E0000 FE400000 FE420000 FE440000 + FE460000 FE480000 FE4A0000 FE4C0000 FE4E0000 + FE500000 FE520000 FE540000 FE560000 FE580000 + FE5A0000 FE5C0000 FE5E0000 FE600000 FE620000 + FE640000 FE660000 FE680000 FE6A0000 FE6C0000 + FE6E0000 FE700000 FE720000 FE740000 FE760000 + FE780000 FE7A0000 FE7C0000 FE7E0000 + +Bank # 2: INTEL 28F128J3A + Size: 8 MB in 64 Sectors + Sector Start Addresses: + FE800000 FE820000 FE840000 FE860000 FE880000 + FE8A0000 FE8C0000 FE8E0000 FE900000 FE920000 + FE940000 FE960000 FE980000 FE9A0000 FE9C0000 + FE9E0000 FEA00000 FEA20000 FEA40000 FEA60000 + FEA80000 FEAA0000 FEAC0000 FEAE0000 FEB00000 + FEB20000 FEB40000 FEB60000 FEB80000 FEBA0000 + FEBC0000 FEBE0000 FEC00000 FEC20000 FEC40000 + FEC60000 FEC80000 FECA0000 FECC0000 FECE0000 + FED00000 FED20000 FED40000 FED60000 FED80000 + FEDA0000 FEDC0000 FEDE0000 FEE00000 FEE20000 + FEE40000 FEE60000 FEE80000 FEEA0000 FEEC0000 + FEEE0000 FEF00000 (RO) FEF20000 (RO) FEF40000 FEF60000 + FEF80000 FEFA0000 FEFC0000 FEFE0000 (RO) + +Bank # 3: AMD AMD29F040B + Size: 0 MB in 7 Sectors + Sector Start Addresses: + FFF00000 (RO) FFF10000 (RO) FFF20000 (RO) FFF30000 FFF40000 + FFF50000 FFF60000 + +Bank # 4: AMD AMD29F040B + Size: 0 MB in 1 Sectors + Sector Start Addresses: + FFF70000 (RO) +=> bdinfo + +memstart = 0xF0009800 +memsize = 0x10000000 +flashstart = 0xFFF00000 +flashsize = 0x01080000 +flashoffset = 0x00025000 +sramstart = 0xF0020000 +sramsize = 0x00008000 +bootflags = 0x00000001 +intfreq = 300 MHz +busfreq = 120 MHz +inpfreq = 30 MHz +flbfreq = 30 MHz +pcifreq = 30 MHz +vcofreq = 480 MHz +pevfreq = 81 MHz +ethaddr = 00:E0:0C:BC:E0:60 +eth1addr = 00:E0:0C:BC:E0:61 +IP addr = 192.162.1.2 +baudrate = 115200 bps +=> printenv +bootargs=root=/dev/ram rw +bootdelay=5 +baudrate=115200 +ethaddr=00:e0:0c:bc:e0:60 +eth1addr=00:e0:0c:bc:e0:61 +ipaddr=192.162.1.2 +serverip=192.162.1.1 +gatewayip=192.162.1.1 +netmask=255.255.255.0 +hostname=Alaska +stdin=serial +stdout=serial +stderr=serial +ethact=FEC ETHERNET + +Environment size: 268/65532 bytes +=> setenv ipaddr 192.160.1.2 +=> setenv serverip 192.160.1.1 +=> setenv gatewayip 192.160.1.1 +=> saveenv +Saving Environment to Flash... + +. +Un-Protected 1 sectors +Erasing Flash... +Erasing sector 0 ... done +Erased 1 sectors +Writing to Flash... done + +. +Protected 1 sectors +=> tftp 0x10000 linux.elf +Using FEC ETHERNET device +TFTP from server 192.160.1.1; our IP address is 192.160.1.2; sending through gateway 192.160.1.1 +Filename 'linux.elf'. +Load address: 0x10000 +Loading: invalid RARP header +################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################## +done +Bytes transferred = 2917494 (2c8476 hex) +=> bootelf +Loading .text @ 0x00a00000 (23820 bytes) +Loading .data @ 0x00a06000 (2752512 bytes) +Clearing .bss @ 0x00ca6000 (12764 bytes) +## Starting application at 0x00a00000 ... + +Collect some entropy from RAM........done +loaded at: 00A00000 00CA91DC +zimage at: 00A06A93 00AD7756 +initrd at: 00AD8000 00CA5565 +avail ram: 00CAA000 014AA000 + +Linux/PPC load: ip=off console=ttyS0,115200 +Uncompressing Linux...done. +Now booting the kernel +Total memory in system: 256 MB +Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb +Linux version 2.4.21-rc1 (r61688@bluesocks.sps.mot.com) (gcc version 3.3.1) #17 Wed Sep 8 11:49:16 CDT 2004 +Motorola Alaska port (C) 2003 Motorola, Inc. +CPLD rev 3 +CPLD switches 0x1b +Set Pin Mux for FEC1 +Set Pin Mux for FEC2 +Alaska Pin Multiplexing: +Port Configuration Register 0 = 0 +Port Configuration Register 1 = 0 +Port Configuration Register 2 = 0 +Port Configuration Register 3 = 50000000 +Port Configuration Register 3 - PCI = 51400180 +Setup Alaska FPGA PIC: +Interrupt Enable Register *(u32) = 0 +Interrupt Status Register = 2f0000 +Interrupt Enable Register in_be32 = 0 +Interrupt Status Register = 2f0000 +Interrupt Enable Register in_le32 = 0 +Interrupt Status Register = 2f00 +Interrupt Enable Register readl = 0 +Interrupt Status Register = 2f00 +Interrupt Enable Register = 0 +Interrupt Status Register = 2f0000 +Setup Alaska PCI Controller: +On node 0 totalpages: 65536 +zone(0): 65536 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: ip=off console=ttyS0,115200 +Using XLB clock (120.00 MHz) to set up decrementer +Calibrating delay loop... 199.88 BogoMIPS +Memory: 254792k available (1476k kernel code, 708k data, 228k init, 0k highmem) +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes) +Inode cache hash table entries: 16384 (order: 5, 131072 bytes) +Mount cache hash table entries: 512 (order: 0, 4096 bytes) +Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes) +Page-cache hash table entries: 65536 (order: 6, 262144 bytes) +POSIX conformance testing by UNIFIX +PCI: Probing PCI hardware +PCI: (pcibios_init) Global-Hose = 0xc029d000 +Scanning bus 00 +Fixups for bus 00 +Bus scan for 00 returning with max=00 +PCI: (pcibios_init) finished pci_scan_bus(hose->first_busno = 0, hose->ops = c01a1a74, hose = c029d000) +PCI: (pcibios_init) PCI Bus Count = 0 =?= Next Bus# = 1 +PCI: (pcibios_init@pci_fixup_irqs) finished machine dependent PCI interrupt routing! +PCI: bridge rsrc 81000000..81ffffff (100), parent c01a7f88 +PCI: bridge rsrc 84000000..87ffffff (200), parent c01a7fa4 +PCI: (pcibios_init) finished allocating and assigning resources! +initDma! +Using 90 DMA buffer descriptors +descUsed f0023600, descriptors f002360c freeSram f0024140 +unmask SDMA tasks: 0xf0008018 = 0x6f000000 +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Initializing RT netlink socket +Starting kswapd +Journalled Block Device driver loaded +JFFS version 1.0, (C) 1999, 2000 Axis Communications AB +JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications AB. +pty: 256 Unix98 ptys configured +tracek: Copyright (C) Motorola, 2003. +Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled +ttyS00 at 0xf1001008 (irq = 73) is a ST16650 +ttyS01 at 0xf1001010 (irq = 74) is a ST16650 +elp-fpanel: Copyright (C) Motorola, 2003. +fpanel: fpanelWait timeout +elp-engine: Copyright (C) Motorola, 2003. +Video disabled due to configuration switch 4 +Alpine 1284 driver: Copyright (C) Motorola, 2003. +1284 disabled due to configuration switch 5 +Alpine USB driver: Copyright (C) Motorola, 2003. +OK +USB: Descriptor download completed OK +enable_irq(41) unbalanced +enable_irq(75) unbalanced +elp-dmaram: Copyright (C) Motorola, 2003. +Total memory in system: 256 MB +elp_dmaram: offset is 0x10000000, size is 0 +Xicor NVRAM driver: Copyright (C) Motorola, 2003. +elp-video: Copyright (C) Motorola, 2003. +Video disabled due to configuration switch 4 +elp-pfm: Copyright (C) Motorola, 2003. +paddle: Copyright (C) Motorola, 2001, present. +RAMDISK driver initialized: 16 RAM disks of 12288K size 1024 blocksize +loop: loaded (max 8 devices) +PPP generic driver version 2.4.2 +PPP Deflate Compression module registered +Uniform Multi-Platform E-IDE driver Revision: 7.00beta-2.4 +ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx +init_alaska_mtd: chip probing count 0 +cfi_cmdset_0001: Erase suspend on write enabled +Using buffer write method +init_alaska_mtd: bank1, name:ALASKA0, size:16777216bytes +ALASKA flash0: Using Static image partition definition +Creating 3 MTD partitions on "ALASKA0": +0x00000000-0x00280000 : "kernel" +0x00280000-0x00fe0000 : "user" +0x00fe0000-0x01000000 : "signature" +mgt_fec_module_init +mgt_fec_init() +mgt_fec_init +mgt_init_fec_dev(0xc05f6000,0) +dev c05f6000 fec_priv c05f6160 fec f0009000 +mgt_init_fec_dev(0xc05f6800,1) +dev c05f6800 fec_priv c05f6960 fec f0009800 +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP, IGMP +IP: routing cache hash table of 2048 buckets, 16Kbytes +TCP: Hash tables configured (established 16384 bind 32768) +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +RAMDISK: Compressed image found at block 0 +Freeing initrd memory: 1845k freed +JFFS: Trying to mount a non-mtd device. +VFS: Mounted root (romfs filesystem) readonly. +Freeing unused kernel memory: 228k init +INIT: version 2.78 booting +INIT: Entering runlevel: 1 +"Space, a great big place of unknown stuff." -Dexter, for our MotD. +[01/Jan/1970:00:00:01 +0000] boa: server version Boa/0.94.8.3 +[01/Jan/1970:00:00:01 +0000] boa: server built Sep 7 2004 at 17:40:55. +[01/Jan/1970:00:00:01 +0000] boa: starting server pid=28, port 80 +Mounting flash filesystem, will take a minute... +/etc/rc: line 30: /dev/lp0: No such devish-2.05b# +sh-2.05b# ifup eth0 +client (v0.9.9-pre) started +adapter index 2 +adapter hardware address 00:e0:0c:bc:e0:60 +execle'ing /usr/share/udhcpc/default.script +/sbin/ifconfig eth0 +eth0 Link encap:Ethernet HWaddr 00:E0:0C:BC:E0:60 + BROADCAST MULTICAST MTU:1500 Metric:1 + mgt_fec_open + Rfec request irq +X fec_open: rcv_ring_size 8, xmt_ring_size 8 +packmgt_fec_open(): call netif_start_queue() +ets:0 errors:0 dropped:0 overruns:0 frame:0 + TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 + collisions:0 txqueuelen:100 + RX bytes:0 (0.0 b) TX bytes:0 (0.0 b) + Base address:0x9000 + +/sbin/ifconfig eth0 up +entering raw listen mode +Opening raw socket on ifindex 2 +adding option 0x35 +adding option 0x3d +adding option 0x3c +Sending discover... +Waiting on select... +unrelated/bogus packet +Waiting on select... +oooooh!!! got some! +adding option 0x35 +adding option 0x3d +adding option 0x3c +adding option 0x32 +adding option 0x36 +Sending select for 163.12.48.146... +Waiting on select... +oooooh!!! got some! +Waiting on select... +oooooh!!! got some! +Lease of 163.12.48.146 obtained, lease time 345600 +execle'ing /usr/share/udhcpc/default.script +/sbin/ifconfig eth0 163.12.48.146 netmask 255.255.254.0 +/sbin/ifconfig eth0 up +deleting routers +/sbin/route del default +/sbin/route add default gw 163.12.49.254 dev eth0 +adding dns 163.12.252.230 +adding dns 192.55.22.4 +adding dns 192.5.249.4 +entering none listen mode +sh-2.05b# + +5. REPROGRAM U-BOOT +=================== +5.1 Reprogram u-boot (boot from AMD) + 1. Unprotect the boot sector + => protect off bank 3 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfff00000 0xfff6ffff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfff00000 + 5. Reset for the new u-boot to take place + => reset + +5.2 Reprogram u-boot (boot from AMD program at INTEL) + 1. Unprotect the boot sector + => protect off bank 2 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfef00000 0xfefdffff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfef00000 + 5. Reset for the new u-boot to take place + => reset + +5.3 Reprogram u-boot (boot from INTEL) + 1. Unprotect the boot sector + => protect off bank 4 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfff00000 0xfffdffff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfff00000 + 5. Reset for the new u-boot to take place + => reset + +5.4 Reprogram u-boot (boot from INTEL program at AMD) + 1. Unprotect the boot sector + => protect off bank 1 + 2. Download new u-boot binary file + => tftp 0x10000 u-boot.bin + 3. Erase bootsector (max 7 sectors) + => erase 0xfe080000 0xfe0effff + 4. Program the u-boot to flash + => cp.b 0x10000 0xfe080000 + 5. Reset for the new u-boot to take place + => reset diff --git a/board/amcc/bamboo/README b/board/amcc/bamboo/README new file mode 100644 index 00000000000..e139c6d1295 --- /dev/null +++ b/board/amcc/bamboo/README @@ -0,0 +1,77 @@ +The 2 important dipswitches are configured as shown below: + +SW1 (for 33MHz SysClk) +---------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF OFF OFF OFF OFF ON + +SW7 (for Op-Code Flash and Boot Option H) +----------------------------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF ON OFF OFF OFF OFF + +The EEPROM at location 0x52 is loaded with these 16 bytes: +C47042A6 05D7A190 40082350 0d050000 + +SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors +SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB +SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output +SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz +SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor +SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A +SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B +SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B +SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor +SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor +SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 +SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 +SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 +SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer +SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit +SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC +SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled +SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled +SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 +SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled +SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 +SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled +SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC +SDR0_SDSTP0[NE]: 0 : NDFC: disabled +SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit +SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection +SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) +SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled +SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready +SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter +SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC +SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC +SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC +SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC +SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count + +PPC440EP Clocking Configuration + +SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz +OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz + +The above information is reported by Eugene O'Brien +<Eugene.O'Brien@advantechamt.com>. Thanks a lot. + +2007-08-06, Stefan Roese <sr@denx.de> +--------------------------------------------------------------------- + +The configuration for the AMCC 440EP eval board "Bamboo" was changed +to only use 384 kbytes of FLASH for the U-Boot image. This way the +redundant environment can be saved in the remaining 2 sectors of the +same flash chip. + +Caution: With an upgrade from an earlier U-Boot version the current +environment will be erased since the environment is now saved in +different sectors. By using the following command the environment can +be saved after upgrading the U-Boot image and *before* resetting the +board: + +setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ + 'cp.b FFF60000 FFF80000 20000' + +2006-07-27, Stefan Roese <sr@denx.de> diff --git a/board/amcc/ebony/README b/board/amcc/ebony/README new file mode 100644 index 00000000000..4df00b35612 --- /dev/null +++ b/board/amcc/ebony/README @@ -0,0 +1,136 @@ + AMCC Ebony Board + + Last Update: September 12, 2002 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ebony evaluation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off on +SW 2 on on +SW 3 on on +SW 4 off on +SW 5 on off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C probe +===================== + +The i2c utilities have been tested on both Rev B. and Rev C. and +look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent +probing the CDCV850 clock controller at address 0x69 (since reading +it causes the i2c implementation to misbehave. The output of +'i2c probe' should look like this (assuming you are only using a single +SO-DIMM: + +=> i2c probe +Valid chip addresses: 50 53 54 +Excluded chip addresses: 69 + + +GETTING OUT OF I2C TROUBLE +=========================== + +If you're like me ... you may have screwed up your bootstrap serial +eeprom ... or worse, your SPD eeprom when experimenting with the +i2c commands. If so, here are some ideas on how to get out of +trouble: + +Serial bootstrap eeprom corruption: +----------------------------------- +Power down the board and set the following straps: + +J41 - open +J42 - strapped + +This will select the default sys0 and sys1 settings (the serial +eeproms are not used). Then power up the board and fix the serial +eeprom using the 'i2c mm' command. Here are the values I currently +use: + +=> i2c md 50 0 10 +0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ + +=> i2c md 54 0 10 +0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... + +Once you have the eeproms set correctly change the +J41/J42 straps as you desire. + +SPD eeprom corruption: +------------------------ +I've corrupted the SPD eeprom several times ... perhaps too much coffee +and not enough presence of mind ;-). By default, the ebony code uses +the SPD to initialize the DDR SDRAM control registers. So if the SPD +eeprom is corrupted, U-Boot will never get into ram. Here's how I got +out of this situation: + +0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then +use 'i2c md' to capture the various device contents to a file. Some day +you may be glad you did this ... trust me :-). Otherwise try the +following: + +1. In the include/configs/EBONY.h file find the line that defines +the CONFIG_SPD_EEPROM macro and undefine it. E.g: + +#undef CONFIG_SPD_EEPROM + +This will make the code use default SDRAM control register +settings without using the SPD eeprom. + +2. Rebuild U-Boot + +3. Load the new U-Boot image and reboot ebony. + +4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom +contents that work with the default SO-DIMM that comes with the +ebony board (micron 8VDDT164AG-265A1). Note: these are probably +_not_ the factory settings ... but they work. + +=> i2c md 53 0 10 80 +0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... +0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P- +0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u.. +0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................ +0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16 +0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c +0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%.............. +0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + + +PCI DOUBLE-ENUMERATION WOES +=========================== + +If you're not using PCI-X cards and are simply using 32-bit and/or +33 MHz cards via extenders and the like, you may notice that the +initial pci scan reports various devices twice ... and configuration +does not succeed (one or more devices are enumerated twice). To correct +this we replaced the 2K ohm resistor on the IDSEL line(s) with a +22 ohm resistor and the problem went away. This change hasn't broken +anything yet -- use at your own risk. + +We never tested anything other than 33 MHz/32-bit cards. If you have +the chance to do this, please let me know how things turn out :-) + + +Regards, +--Scott +<smcnutt@artesyncp.com> diff --git a/board/amcc/ocotea/README.ocotea b/board/amcc/ocotea/README.ocotea new file mode 100644 index 00000000000..be79b03c8a0 --- /dev/null +++ b/board/amcc/ocotea/README.ocotea @@ -0,0 +1,73 @@ + AMCC Ocotea Board + + Last Update: March 2, 2004 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ocotea 440gx evaluation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off off +SW 2 on off +SW 3 off off +SW 4 off off +SW 5 off off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C Information +===================== + +See README.ebony for information. + +PCI +=========================== + +Untested at the time of writing. + +PPC440GX Ethernet EMACs +=========================== + +All EMAC ports have been tested and are known to work +with EPS Group 4. + +Special note about the Cicada CIS8201: + The CIS8201 Gigabit PHY comes up in GMII mode by default. + One must hit an extended register to allow use of RGMII mode. + This has been done in the 440gx_enet.c file with a #ifdef/endif + pair. + +AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. +The addresses contained in the config header file are from my particular +board and you _*should*_ change them to reflect your board either in the +config file and/or in your environment variables. I found the addresses on +labels on the bottom side of the board. + + +BDI2k or JTAG Debugging +=========================== + +For ease of debugging you can swap the small boot flash and external SRAM +by changing U46:3 to on. You can then use the sram as your boot flash by +loading the sram via the jtag debugger. + + +Regards, +--Travis +<tsawyer@sandburst.com> diff --git a/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot new file mode 100644 index 00000000000..25dd2a23781 --- /dev/null +++ b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot @@ -0,0 +1,99 @@ +------------------------------------------ +Installation of U-Boot using PIBS firmware +------------------------------------------ + +This document describes how to install U-Boot on the Ocotea PPC440GX +Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the +soldered FLASH. After this you should be able to switch between PIBS and +U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before +continuing. + +Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu +program. See the hints for configuring cu above. Make sure you can +communicate with the PIBS firmware: reset the board and hit ENTER a couple of +times until you see the PIBS prompt (PIBS $). Then proceed as follows: + + +Read MAC Addresses from PIBS +---------------------------- + +To read the configured MAC addresses available on your Ocotea board please use +the following commands: + +PIBS $ echo $hwdaddr0 +000173017FE3 +PIBS $ echo $hwdaddr1 +000173017FE4 +PIBS $ echo $hwdaddr2 +000173017FE1 +PIBS $ echo $hwdaddr3 +000173017FE2 + +In U-Boot this is stored in the following environment variables: + +* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) +* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) +* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) +* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) + + +Configure the network interface (ent0 == emac0) +----------------------------------------------- + +To download the U-Boot image we need to configure the ethernet interface with +the following commands: + +PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up +PIBS $ set ipdstaddr0=192.168.1.1 +status: writing PIBS variable value to FLASH +PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin +status: writing PIBS variable value to FLASH + +Please insert correct parameters for your configuration (ip-addresses and +file-location). + + +Program U-Boot into soldered User-FLASH +--------------------------------------- + +Please make sure to use a newer version of U-Boot (at least 1.1.3), since +older versions don't support running from user-FLASH. + +To program U-Boot into the soldered user-FLASH use the following command: + +PIBS $ storefile bin eth 0xffbc0000 + +This commands loads the file vis ethernet into ram and copies it into the +user-FLASH. + + +Switch to U-Boot +---------------- + +Now you can turn your board off and switch SW1 (U46) to on (= closed). After +powering the board you should see the following message: + +U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) + +AMCC PowerPC 440 GX Rev. C +Board: AMCC 440GX Evaluation Board + VCO: 1066 MHz + CPU: 533 MHz + PLB: 152 MHz + OPB: 76 MHz + EPB: 76 MHz +I2C: ready +DRAM: 256 MB +FLASH: 5 MB +PCI: Bus Dev VenId DevId Class Int +In: serial +Out: serial +Err: serial +KGDB: kgdb ready +ready +Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 +BEDBUG:ready +=> + + +April 06 2005, Stefan Roese <sr@denx.de> diff --git a/board/armltd/integrator/README b/board/armltd/integrator/README new file mode 100644 index 00000000000..5a0e9349248 --- /dev/null +++ b/board/armltd/integrator/README @@ -0,0 +1,110 @@ + + U-Boot for ARM Integrator Development Platforms + + Peter Pearse, ARM Ltd. + peter.pearse@arm.com + www.arm.com + +Manuals available from :- +http://www.arm.com/products/DevTools/Hardware_Platforms.html + +Overview : +-------- +There are two Integrator variants - Integrator/AP and Integrator/CP. +Each may be fitted with a variety of core modules (CMs). +Each CM consists of a ARM processor core and associated hardware e.g + FPGA implementing various controllers and/or register + SSRAM + SDRAM + RAM controllers + clock generators etc. +CMs may be fitted with varying amounts of SDRAM using a DIMM socket. + +Boot Methods : +------------ +Integrator platforms can be configured to use U-Boot in at least three ways :- +a) Run ARM boot monitor, manually run U-Boot image from flash +b) Run ARM boot monitor, automatically run U-Boot image from flash +c) Run U-Boot image direct from flash. + +In cases a) and b) the ARM boot monitor will have configured the CM and mapped +writeable memory to 0x00000000 in the Integrator address space. +U-Boot has to carry out minimal configration before standard code is run. + +In case c) it may be necessary for U-Boot to perform CM dependent initialization. + +Configuring U-Boot : +------------------ + The makefile contains targets for Integrator platforms of both types +fitted with all current variants of CM. If these targets are to be used with +boot process c) above then CONFIG_INIT_CRITICAL may need to be defined to ensure +that the CM is correctly configured. + + There are also targets independent of CM. These may not be suitable for +boot process c) above. They have been preserved for backward compatibility with +existing build processes. + +Code Hierarchy Applied : +---------------------- +Code specific to initialization of a particular ARM processor has been placed in +cpu/arm<>/start.S so that it may be used by other boards. + +However, to avoid duplicating code through all processor files, a generic core +for ARM Integrator CMs has been added + + arch/arm/cpu/arm_intcm + +Otherwise. for example, the standard CM reset via the CM control register would +need placing in each CM processor file...... + +Code specific to the initialization of the CM, rather than the cpu, and initialization +of the Integrator board itself, has been placed in + + board/integrator<>/platform.S + board/integrator<>/integrator<>.c + +Targets +======= +The U-Boot make targets map to the available core modules as below. + +Integrator/AP is no longer available from ARM. +Core modules marked ** are also no longer available. + +ap720t_config ** CM720T +ap920t_config ** CM920T +ap926ejs_config Integrator Core Module for ARM926EJ-STM +ap946es_config Integrator Core Module for ARM946E-STM +cp920t_config ** CM920T +cp926ejs_config Integrator Core Module for ARM926EJ-STM +cp946es_config Integrator Core Module for ARM946E-STM +cp1136_config Integrator Core Module ARM1136JF-S TM + +The final groups of targets are for core modules where no explicit cpu +code has yet been added to U-Boot i.e. they all use the same U-Boot binary +using the generic "arm_intcm" core: + +ap966_config Integrator Core Module for ARM966E-S TM +ap922_config Integrator Core Module for ARM922T TM with ETM +ap922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur +ap7_config ** CM7TDMI +integratorap_config +ap_config + + +cp966_config Integrator Core Module for ARM966E-S TM +cp922_config Integrator Core Module for ARM922T TM with ETM +cp922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur +cp1026_config Integrator Core Module ARM1026EJ-S TM +integratorcp_config +cp_config + +The Makefile targets call board/integrator<>/split_by_variant.sh +to configure various defines in include/configs/integrator<>.h +to indicate the core module & core configuration and ensure that +board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image. + +********************************* +Because of this mechanism +> make clean +must be run before each change in configuration +********************************* diff --git a/board/cmi/README b/board/cmi/README new file mode 100644 index 00000000000..0edd50ad22c --- /dev/null +++ b/board/cmi/README @@ -0,0 +1,84 @@ + +Summary: +======== + +This file contains information about the cmi board configuration. +Please see cmi_mpc5xx_config for further details. The cmi board is +a customer specific board but should work with small modifications +on every board which has a MPC5xx and either a 28F128J3A, +28F320J3A or 28F640J3A Intel flash mounted. + +Board Discription: +================== + +* Motorola MPC555 +* RS232 connection +* Intel flash 28F640J3A +* Micron SRAM 1M +* Altera PLD + +Bootstrap: +========== + +In contrast to the usual boot sequence used in U-Boot, on the +cmi board we don't boot from the external flash directly. +Because of we use a 16-bit flash and don't sample a RCW +from the data bus to set the startup buswidth to 16-bit. +Unfortunatly the default width, sampled from the default RCW +is 32-bit. For this reason we burn the proper RCW into the +internal flash shadow location and boot after power-on or +reset from the internal flash and then branch to 0x02000100 +where the U-Boot reset vector handler is located. + +Memory Map: +=========== + +Memory Map after relocation: + + 0x0000 0000 CONFIG_SYS_SDRAM_BASE + : + 0x000F 9FFF + : + : + 0x0100 0000 CONFIG_SYS_IMMR (Internal memory map base adress) + : + 0x0130 7FFF + : + : + 0x0200 0000 CONFIG_SYS_FLASH_BASE + : + 0x027C FFFF + : + : + 0x0300 0000 PLD_BASE + +Flash Partition: + + 0x0200 0000 Block 0 and 1 contain U-Boot except + : environment + : + 0x0201 FFFF + 0x0202 0000 Block 2 contains environment (.ppcenv) + : + 0x0202 FFFF + +See README file for futher information about U-Boot relocation +and partitioning. + +Tested Features: +================ + +* U-Boot commands: go, loads, loadb, all memory features, printenv, + setenv, saveenv, protect, erase, fli, bdi, mtest, reset, version, + coninfo, help (see configuration file for available commands) + +* Blinking led to indicate boot process + +Added or Changed Files: +======================= + +u-boot-0.2.0/board/cmi/* +u-boot-0.2.0/include/configs/cmi_mpc5xx.h + +Regards, +Martin diff --git a/board/cobra5272/README b/board/cobra5272/README new file mode 100644 index 00000000000..ae0f148258d --- /dev/null +++ b/board/cobra5272/README @@ -0,0 +1,156 @@ +File: README.COBRA5272 +Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de) +Contents: This is the README of u-boot (Universal bootloader) for our + COBRA5272 board. +Version: v01.00 +Date: Tue Mar 30 00:28:33 CEST 2004 +License: This document is published under the GNU GPL +______________________________________________________________________ + +CHANGES +040330 v01.00 Creation + +______________________________________________________________________ + + +CONFIGURING +----------- + +1. Modify include/configs/cobra5272.h acc. to your prefs + +2. If necessary, modify board/cobra5272/config.mk (see below) + +3. + +> make cobra5272_config + +> make + + +Please refer to u-boot README (general info, u-boot-x-x-x/README), +to u-boot-x-x-x/doc/README.COBRA5272 and +to the comments in u-boot-x-x-x/include/configs/cobra5272.h + +Configuring u-boot is done by commenting/uncommenting preprocessor defines. + +Default configuration is + + FLASH version (for further info see subsection below) + link address 0xffe00000 + + 16 MB RAM + + network enabled + no default IP address for target, host set, no MACaddress set + + bootdelay for autoboot 5 sec. + autoboot disabled + + +#----------------------------------- +# u-boot FLASH version & RAM version +#----------------------------------- + +The u-boot bootloader for Coldfire processors can be configured + + 1. as a standalone bootloader residing in flash & relocating itself to RAM on + startup automatically => "FLASH version" + + 2. as a RAM version which will not load from flash automatically as it needs a + prestage bootloader ("chainloading") & is running only from the RAM address it + is linked to => "RAM version" + + This version may be very helpful when installing u-boot for the first time + since it can be used to make available s. th. like a "bootstrap + mechanism". + + +How to build the different images: + +------------------------------ +Flash version +------------------------------ + +Compile u-boot + +in dir ./u-boot-x-x-x/ + +please first check: + + in ./include/configs/cobra5272.h + + CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows: + + #if 0 + #define CONFIG_MONITOR_IS_IN_RAM + /* define if monitor is started from a pre-loader */ + #endif + + => u-boot as single bootloader starting from flash + + + in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be + + CONFIG_SYS_TEXT_BASE = 0xffe00000 + + => linking address for u-boot as single bootloader stored in flash + +then: + + host> make cobra5272_config + rm -f include/config.h include/config.mk + Configuring for cobra5272 board... + host> make + [...] + + host> cp u-boot.bin /tftpboot/u-boot_flash.bin + + +------------------------------ +RAM version +------------------------------ + +in dir ./u-boot-x-x-x/ + + host> make distclean + +please modify the settings: + + in ./include/configs/cobra5272.h + + CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows: + + #if 1 + #define CONFIG_MONITOR_IS_IN_RAM + /*define if monitor is started from a pre-loader */ + #endif + + => u-boot as RAM version, chainloaded by another bootloader or using bdm cable + + + in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be + + CONFIG_SYS_TEXT_BASE = 0x00020000 + + => target linking address for RAM + + +then: + + host> make cobra5272_config + rm -f include/config.h include/config.mk + Configuring for cobra5272 board... + host> make + [...] + + host> cp u-boot.bin /tftpboot/u-boot_ram.bin + + +---- +HINT +---- + +If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM +version by typing (in dir ./u-boot-x-x-x/) +"board/cobra5272/bdm/load-cobra_uboot" , +in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available. diff --git a/board/davinci/da8xxevm/README.hawkboard b/board/davinci/da8xxevm/README.hawkboard new file mode 100644 index 00000000000..d6ae02ec028 --- /dev/null +++ b/board/davinci/da8xxevm/README.hawkboard @@ -0,0 +1,92 @@ +Summary +======= +The README is for the boot procedure used for TI's OMAP-L138 based +hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB +DDR SDRAM along with a host of other controllers. + +The hawkboard is booted in three stages. The initial bootloader which +executes upon reset is the Rom Boot Loader(RBL) which sits in the +internal ROM of the omap. The RBL initialises the memory and the nand +controller, and copies the image stored at a predefined location(block +1) of the nand flash. The image loaded by the RBL to the memory is the +AIS signed spl image. This, in turns copies the u-boot binary from the +nand flash to the memory and jumps to the u-boot entry point. + +AIS is an image format defined by TI for the images that are to be +loaded to memory by the RBL. The image is divided into a series of +sections and the image's entry point is specified. Each section comes +with meta data like the target address the section is to be copied to +and the size of the section, which is used by the RBL to load the +image. At the end of the image the RBL jumps to the image entry +point. + +The secondary stage bootloader(spl) which is loaded by the RBL then +loads the u-boot from a predefined location in the nand to the memory +and jumps to the u-boot entry point. + +The reason a secondary stage bootloader is used is because the ECC +layout expected by the RBL is not the same as that used by +u-boot/linux. This also implies that for flashing the spl image,we +need to use the u-boot which uses the ECC layout expected by the +RBL[1]. Booting u-boot over UART(UART boot) is explained here[2]. + + +Compilation +=========== +Three images might be needed + +* spl - This is the secondary bootloader which boots the u-boot + binary. + +* u-boot binary - This is the image flashed to the nand and copied to + the memory by the spl. + + Both the images get compiled with hawkboard_config, with the TOPDIR + containing the u-boot images, and the spl image under the spl + directory. + + The spl image needs to be processed with the AISGen tool for + generating the AIS signed image to be flashed. Steps for generating + the AIS image are explained here[3]. + +* u-boot for uart boot - This is same as the u-boot binary generated + above, with the sole difference of the CONFIG_SYS_TEXT_BASE being + 0xc1080000, as expected by the RBL. + + hawkboard_uart_config + + +Flashing the images to Nand +=========================== +The spl AIS image needs to be flashed to the block 1 of the Nand +flash, as that is the location the RBL expects the image[4]. For +flashing the spl, boot over the u-boot specified in [1], and flash the +image + +=> tftpboot 0xc0700000 <nand_spl_ais.bin> +=> nand erase 0x20000 0x20000 +=> nand write.e 0xc0700000 0x20000 <nand_spl_size> + +The u-boot binary is flashed at location 0xe0000(block 6) of the nand +flash. The spl loader expects the u-boot at this location. For +flashing the u-boot binary + +=> tftpboot 0xc0700000 u-boot.bin +=> nand erase 0xe0000 0x40000 +=> nand write.e 0xc0700000 0xe0000 <u-boot-size> + + +Links +===== + +[1] + http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin + +[2] + http://elinux.org/Hawkboard#Booting_u-boot_over_UART + +[3] + http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot + +[4] + http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks diff --git a/board/dnp5370/README b/board/dnp5370/README new file mode 100644 index 00000000000..0172698e96d --- /dev/null +++ b/board/dnp5370/README @@ -0,0 +1,67 @@ +This document describes the board support for +Dil/NetPC DNP/5370 (http://www.dilnetpc.com/dnp0086.htm) module. +The distributor is SSV (http://www.ssv-embedded.de), + +The module used to develop the support files contains: + +* Processor: Blackfin BF537 Rev 0.3 (600 MHz core / 120MHz RAM) + +* RAM: 32 MB SDRAM + Hynix HY57V561620FTP-H 810EA + Connected to Blackfin via "Expansion Bus" + Address range 0x0000.0000 - 0x1fff.ffff + +* NOR flash: 32 MBit (4 MByte) + Exel Semiconductor ES29LVS320EB + Connected to Blackfin via "Expansion Bus", + Chip Selects 0, 1 and 2, each is connected + to a 1 MB memory bank at Blackfin, therefore + only 3 MB accessible. + Address range 0x2000.0000 - 0x202f.ffff + CFI compatible + + Exel Semiconductor was bought by Rohm Semiconductor (www.rohm.com). + +* NAND flash: 64 MBit (8 MByte) + Atmel 45DB642D-CNU + Connected to Blackfin via SPI + CFI compatible + +* Davicom DM9161EP Ethernet PHY + +* A SD card reader, connected via SPI + +* Hardware watchdog MAX823 or TPS3823 + +(other devices not listed here) + +To run it, the module must be inserted in a 64 pin DIL socket +on another board, e.g. DNP/EVA13 (together: SSV SK28). + +The Blackfin is booted from NOR flash. The NOR flash data begins +with the U-Boot code and is then followed by the Linux code. +Finally, the MAC is stored in the last sector. +You may need to adjust these settings to your needs. +The memory map used to develop the board support is: + +Memory map: +0x00000000 .. 0x01ffffff SDRAM +0x20000000 .. 0x202fffff NOR flash + +RAM use: +0x01f9bffc .. 0x01fbbffb U-Boot stack +0x01f9c000 .. 0x01f9ffff U-Boot global data +0x01fa0000 .. 0x01fbffff U-Boot malloc() RAM +0x01fc0000 .. 0x01ffffff U-Boot execution RAM + +NOR flash use: +0x20000000 .. 0x0002ffff U-Boot +0x20004000 .. 0x20005fff U-Boot environment +0x20030000 .. 0x202effff Linux kernel image +0x202f0000 .. 0x202fffff MAC address sector + +NOR flash is 0x00300000 (3145728) bytes large (3 MB). +Max space for compressed kernel in flash is 0x002c0000 (2883584) bytes (2.75 MB) +Max space for u-boot in flash is 0x00030000 (196608) bytes (192 KB) + +The module is hardwired to BYPASS boot mode. diff --git a/board/evb64260/README b/board/evb64260/README new file mode 100644 index 00000000000..74211dea439 --- /dev/null +++ b/board/evb64260/README @@ -0,0 +1,54 @@ +This file contains status information for the port of U-Boot to the +Galileo Evaluation Board. + +Author: Josh Huber <huber@mclx.com> + Mission Critical Linux, Inc. + +The support for the Galileo Evaluation board is fairly minimal now. +It's sufficient to boot Linux, but doesn't provide too much more than +what's required to do this. + +Both DUART channels are supported (to use the second one, you have to +modify the board -- see the schematics for where to solder on the +devices module). The ethernet ports are supported, and the MPSC is +supported as a console driver. (keep in mind that the kernel has no +support for this yet) + +There are still occaisonal lockups with the MPSC console driver due to +(we think!) overrun problems. If you're looking for something stable +to use for Linux development, consider sticking with the DUART console +for now. + +Automatic memory sizing mostly works. We've had problems with some +combinations of memory. Please send us email if you're having trouble +with respect to the memory detection. + +Right now, only the 512k boot flash is supported. Support for the +16MB flash on the devices module is forthcoming. Right now the flash +is stored at the 256k boundry in flash, wasting a whole sector (64k!) +for environment data. This isn't really a big deal since we're not +using the 512k for anything else. (Just U-Boot and the environment) + +Finally, here is a sample output session: + +U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11) + +Initializing... + CPU: MPC7400 (altivec enabled) v2.9 + Board: EVB64260 + DRAM: 256 MB + FLASH: 512 kB + In: serial + Out: serial + Err: serial + +=> + +The default configuration should be correct for the evaluation board, +as it's shipped from Galileo. Keep in mind that the default baudrate +is set to 38400, 8N1. + +Good luck, and make sure to send any bugreports to us (or the +u-boot-users list). + +Josh diff --git a/board/evb64260/README.EVB-64260-750CX b/board/evb64260/README.EVB-64260-750CX new file mode 100644 index 00000000000..5ea38eaea3a --- /dev/null +++ b/board/evb64260/README.EVB-64260-750CX @@ -0,0 +1,7 @@ +The EVB-64260-750CX is quite similar to the EVB-64260-BP already +supported except the following differences: +* It has an IBM-750CXe soldiered on board instead of the slot-1 in the + BP. +* It has a single PCI male connector instead of the 4 PCI female + connectors on the BP. It also gets power trough the PCI connector. +* It has only a single DIMM slot instead of the 2 slots in the BP. diff --git a/board/fads/README b/board/fads/README new file mode 100644 index 00000000000..bae9652f012 --- /dev/null +++ b/board/fads/README @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2000 + * Dave Ellis, SIXNET, dge@sixnetio.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +Using the Motorola MPC8XXFADS development board +=============================================== + +CONFIGURATIONS +-------------- + +There are ready-to-use default configurations available for the +FADS823, FADS850SAR and FADS860T. The FADS860T configuration also +works for the 855T processor. + +LOADING U-Boot INTO FADS FLASH MEMORY +-------------------------------------- + +MPC8BUG can load U-Boot into the FLASH memory using LOADF. + + loadf u-boot.srec 100000 + + +STARTING U-Boot FROM MPC8BUG +----------------------------- + +To start U-Boot from MPC8BUG: + +1. Reset the board: + reset :h + +2. Change BR0 and OR0 back to their values at reset: + rms memc br0 00000001 + rms memc or0 00000d34 + +3. Modify DER so MPC8BUG gets control only when it should: + rms der 2002000f + +4. Start as if from reset: + go 100 + +This is NOT exactly the same as starting U-Boot without +MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset. +After it does the reset it writes SYPCR (to disable the watchdog) +and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots +of other initialization). That is why it is necessary to set BR0 +and OR0 to map the FLASH everywhere. U-Boot can't turn on the +watchdog after that, since MPC8BUG has used the only chance to write +to SYPCR. + +Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets +U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T +processor (your mileage may vary). It is probably better (and a lot +easier) just to accept having the watchdog disabled when the debug +cable is connected. + +in MPC8BUG: + reset :h + rms memc br0 00000001 + rms memc or0 00000d34 + rms der 2000f + go 100 + +Now U-Boot is running with the MPC8BUG value for SYPCR. Use the +U-Boot 'reset' command to reset the board. + =>reset +Next, in MPC8BUG: + rms der 2000f + go + +Now U-Boot is running with the U-Boot value for SYPCR. diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README new file mode 100644 index 00000000000..b6e955bcadb --- /dev/null +++ b/board/freescale/m52277evb/README @@ -0,0 +1,231 @@ +Freescale MCF52277EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created Jan 8, 2008 +=========================================== + + +Changed files: +============== + +- board/freescale/m52277evb/m52277evb.c Dram setup +- board/freescale/m52277evb/Makefile Makefile +- board/freescale/m52277evb/config.mk config make +- board/freescale/m52277evb/u-boot.lds Linker description + +- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code +- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock +- arch/m68k/cpu/mcf5227x/Makefile Makefile +- arch/m68k/cpu/mcf5227x/config.mk config make +- arch/m68k/cpu/mcf5227x/start.S start up assembly code + +- doc/README.m52277evb This readme file + +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/crossbar.h CrossBar structure and definition +- include/asm-m68k/dspi.h DSPI structure and definition +- include/asm-m68k/edma.h eDMA structure and definition +- include/asm-m68k/flexbus.h FlexBus structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5227x.h mcf5227x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/lcd.h LCD structure and definition +- include/asm-m68k/m5227x.h mcf5227x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/ssi.h SSI structure and definition +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M52277EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +1 MCF52277 specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in this coldfire family + +1.2 Configuration settings for M52277EVB Development Board +CONFIG_MCF5227x -- define for all MCF5227x CPUs +CONFIG_M52277 -- define for all Freescale MCF52277 CPUs +CONFIG_M52277EVB -- define for M52277EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base + +CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot, +update will be provided at later time + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + + DDR: 0x40000000-0x4FFFFFFF (64MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M52277EVB_config + make + +4. SCREEN DUMP +============== +4.1 M52277EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 1.3.1 (Jan 8 2008 - 12:44:08) + +CPU: Freescale MCF52277 (Mask:6c Version:0) + CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ + INP CLK 16 Mhz VCO CLK 480 Mhz +Board: Freescale 52277 EVB +I2C: ready +DRAM: 64 MB +FLASH: 16 MB +In: serial +Out: serial +Err: serial +-> print +baudrate=115200 +hostname=M52277EVB +inpclk=16000000 +loadaddr=(0x40000000 + 0x10000) +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save +u-boot=u-boot.bin +stdin=serial +stdout=serial +stderr=serial +mem=65024k + +Environment size: 280/32764 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x04000000 +flashstart = 0x00000000 +flashsize = 0x01000000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 80 MHz +flbfreq = 80 Mhz +inpfreq = 16 Mhz +vcofreq = 480 Mhz + +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +i2c - I2C sub-system +icache - enable or disable instruction cache +iminfo - print header information for application image +imls - list all images found in flash +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +source - run script from memory +version - print monitor version +-> diff --git a/board/freescale/m5253evbe/README b/board/freescale/m5253evbe/README new file mode 100644 index 00000000000..f51609f3e04 --- /dev/null +++ b/board/freescale/m5253evbe/README @@ -0,0 +1,103 @@ +Freescale Amadeus Plus M5253EVBE board +====================================== + +Hayden Fraser(Hayden.Fraser@freescale.com) +Created 06/05/2007 +=========================================== + + +1. SWITCH SETTINGS +================== +1.1 N/A + + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + SDR: 0x00000000-0x00ffffff + SRAM0: 0x20010000-0x20017fff + SRAM1: 0x20000000-0x2000ffff + MBAR1: 0x10000000-0x4fffffff + MBAR2: 0x80000000-0xCfffffff + Flash: 0xffe00000-0xffffffff + +3. DEFINITIONS AND COMPILATION +============================== +3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h + CONFIG_MCF52x2 Processor family + CONFIG_MCF5253 MCF5253 specific + CONFIG_M5253EVBE Amadeus Plus board specific + CONFIG_SYS_CLK Define Amadeus Plus CPU Clock + CONFIG_SYS_MBAR MBAR base address + CONFIG_SYS_MBAR2 MBAR2 base address + +3.2 Compilation + export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- + cd u-boot-1-2-x + make distclean + make M5253EVBE_config + make + + +4. SCREEN DUMP +============== +4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00) + +CPU: Freescale Coldfire MCF5253 at 62 MHz +Board: Freescale MCF5253 EVBE +DRAM: 16 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +=> flinfo + +Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors + AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49 + Erase timeout: 16384 ms, write timeout: 1 ms + + Sector Start Addresses: + FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO + FFE20000 FFE30000 FFE40000 FFE50000 FFE60000 + FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000 + FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000 + FFF10000 FFF20000 FFF30000 FFF40000 FFF50000 + FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000 + FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000 + +=> bdinfo +boot_params = 0x00F62F90 +memstart = 0x00000000 +memsize = 0x01000000 +flashstart = 0xFFE00000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +baudrate = 19200 bps + +=> printenv +bootdelay=5 +baudrate=19200 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 134/8188 bytes +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... +. done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +5. COMPILER +----------- +To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture +compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used. +You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M +codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README new file mode 100644 index 00000000000..64a3d42f0ce --- /dev/null +++ b/board/freescale/m53017evb/README @@ -0,0 +1,180 @@ +Freescale MCF53017EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 10/22/08 +=========================================== + + +Changed files: +============== + +- board/freescale/m53017evb/m53017evb.c Dram setup +- board/freescale/m53017evb/mii.c Mii access +- board/freescale/m53017evb/Makefile Makefile +- board/freescale/m53017evb/config.mk config make +- board/freescale/m53017evb/u-boot.lds Linker description + +- arch/m68k/cpu/mcf532x/cpu.c cpu specific code +- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock +- arch/m68k/cpu/mcf532x/Makefile Makefile +- arch/m68k/cpu/mcf532x/config.mk config make +- arch/m68k/cpu/mcf532x/start.S start up assembly code + +- doc/README.m53017evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/net/mcfmii.c ColdFire common Mii driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5301x.h mcf5301x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf5301x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M53017EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +1 MCF5301x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M53017EVB Development Board +CONFIG_MCF5301x -- define for all MCF5301x CPUs +CONFIG_M53015 -- define for MCF53015 CPUs +CONFIG_M53017EVB -- define for M53017EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xFC000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot + make distclean + make M53017EVB_config + make + +4. SCREEN DUMP +============== +4.1 M53017EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 2008.10 (Oct 22 2007 - 11:07:57) + +CPU: Freescale MCF53015 (Mask:76 Version:0) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale M53017EVB +I2C: ready +DRAM: 64 MB +FLASH: 16 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0, FEC1 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M53017EVB +netdev=eth0 +loadaddr=40010000 +u-boot=u-boot.bin +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=65024k + +Environment size: 437/4092 bytes +-> diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README new file mode 100644 index 00000000000..419d4d6d1ec --- /dev/null +++ b/board/freescale/m5373evb/README @@ -0,0 +1,326 @@ +Freescale MCF5373EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 11/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m5373evb/m5373evb.c Dram setup +- board/freescale/m5373evb/mii.c Mii access +- board/freescale/m5373evb/Makefile Makefile +- board/freescale/m5373evb/config.mk config make +- board/freescale/m5373evb/u-boot.lds Linker description + +- arch/m68k/cpu/mcf532x/cpu.c cpu specific code +- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf532x/Makefile Makefile +- arch/m68k/cpu/mcf532x/config.mk config make +- arch/m68k/cpu/mcf532x/start.S start up assembly code + +- doc/README.m5373evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_532x.h mcf532x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf532x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M5373EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +1 MCF5373 specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M5373EVB Development Board +CONFIG_MCF532x -- define for all MCF532x CPUs +CONFIG_M5373 -- define for all Freescale MCF5373 CPUs +CONFIG_M5373EVB -- define for M5373EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M5373EVB_config + make + +4. SCREEN DUMP +============== +4.1 M5373EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 1.3.0 (Nov 8 2007 - 12:44:08) + +CPU: Freescale MCF5373 (Mask:65 Version:1) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale FireEngine 5373 EVB +I2C: ready +DRAM: 32 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M5373EVB +netdev=eth0 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +u-boot=u-boot.bin +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 401/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x02000000 +flashstart = 0x00000000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 80 MHz +ethaddr = 00:E0:0C:BC:E5:60 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +i2c - I2C sub-system +icache - enable or disable instruction cache +iminfo - print header information for application image +imls - list all images found in flash +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nand - NAND sub-system +nboot - boot from NAND device +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +source - run script from memory +tftpboot- boot image via network using TFTP protocol +version - print monitor version +-> tftp 0x40800000 uImage +Using FEC0 device +TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'. +Load address: 0x40800000 +Loading: ################################################################# + ################################################################# + ########## +done +Bytes transferred = 2053270 (1f5496 hex) +-> bootm 0x40800000 +## Booting image at 40800000 ... + Image Name: Linux Kernel Image + Created: 2007-11-07 20:33:08 UTC + Image Type: M68K Linux Kernel Image (gzip compressed) + Data Size: 2053206 Bytes = 2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7 + + +uClinux/COLDFIRE(m537x) +COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512 +NET: Registered protocol family 16 +USB-MCF537x: (HOST module) EHCI device is registered +USB-MCF537x: (OTG module) EHCI device is registered +USB-MCF537x: (OTG module) UDC device is registered +usbcore: registered new interface driver usbfs +usbcore: registered new interface driver hub +usbcore: registered new device driver usb +NET: Registered protocol family 2 +IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) +TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered +JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +loop: module loaded +nbd: registered device at major 43 +usbcore: registered new interface driver ub FEC ENET Version 0.2 +fec: PHY @ 0x1, ID 0x20005c90 -- DP83848 +eth0: ethernet 00:e0:0c:bc:e5:60 +uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM": +0x00000000-0x0022b000 : "ROMfs" +uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit": +0x00000000-0x01000000 : "M53xx flash partition 1" +QSPI: spi->max_speed_hz 300000 +QSPI: Baud set to 255 +SPI: Coldfire master initialized +M537x - Disable UART1 when using Audio +udc: Freescale MCF53xx UDC driver version 27 October 2006 init +udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver +usbcore: registered new interface driver usbhid +drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +VFS: Mounted root (romfs filesystem) readonly. +Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems +mount: Mounting devpts on /dev/pts failed: No such device +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device: +Setting up networking on eth0: +info, udhcpc (v0.9.9-pre) started +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +debug, Sending discover... +debug, Sending discover... +debug, Sending select for 172.27.0.130... +info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers +route: SIOC[ADD|DEL]RT: No such process +adding dns 172.27.0.1 +Starting the boa webserver: +Setting time from ntp server: ntp.cs.strath.ac.uk +ntp.cs.strath.ac.uk: Unknown host + + +BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands. + +# diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README new file mode 100644 index 00000000000..2bc6ce4bf37 --- /dev/null +++ b/board/freescale/m54455evb/README @@ -0,0 +1,409 @@ +Freescale MCF54455EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 4/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init +- board/freescale/m54455evb/flash.c Atmel and INTEL flash support +- board/freescale/m54455evb/Makefile Makefile +- board/freescale/m54455evb/config.mk config make +- board/freescale/m54455evb/u-boot.lds Linker description + +- common/cmd_bdinfo.c Clock frequencies output +- common/cmd_mii.c mii support + +- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code +- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf5445x/Makefile Makefile +- arch/m68k/cpu/mcf5445x/config.mk config make +- arch/m68k/cpu/mcf5445x/start.S start up assembly code + +- doc/README.m54455evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5445x.h mcf5445x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m5445x.h mcf5445x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M54455EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +- rtc/mcfrtc.c Realtime clock Driver + +1 MCF5445x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M54455EVB Development Board +CONFIG_MCF5445x -- define for all MCF5445x CPUs +CONFIG_M54455 -- define for all Freescale MCF54455 CPUs +CONFIG_M54455EVB -- define for M54455EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop +CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot + +CONFIG_ISO_PARTITION -- enable ISO read/write +CONFIG_DOS_PARTITION -- enable DOS read/write +CONFIG_IDE_RESET -- define ide_reset() +CONFIG_IDE_PREINIT -- define ide_preinit() +CONFIG_ATAPI -- define ATAPI support +CONFIG_LBA48 -- define LBA48 (larger than 120GB) support +CONFIG_SYS_IDE_MAXBUS -- define max channel +CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel +CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address +CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset +CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO +CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses +CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers +CONFIG_SYS_ATA_STRIDE -- define for Interval between registers +_IO_BASE -- define for IO base address + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_PCI -- define for PCI support +CONFIG_PCI_PNP -- define for Plug n play support +CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset +CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset +CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size +CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset +CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset +CONFIG_SYS_PCI_IO_SIZE -- PCI IO size +CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset +CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset +CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size + +CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_SYS_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base +CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1 + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + ATA: 0x90000000-0x9FFFFFFF (256MB) + PCI: 0xA0000000-0xBFFFFFFF (512MB) + FlexBus: 0xC0000000-0xDFFFFFFF (512MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Atmel boot: + Flash0: 0x00000000-0x0007FFFF (512KB) + Flash1: 0x04000000-0x05FFFFFF (32MB) + Intel boot: + Flash0: 0x00000000-0x01FFFFFF (32MB) + Flash1: 0x04000000-0x0407FFFF (512KB) + + CPLD: 0x08000000-0x08FFFFFF (16MB) + FPGA: 0x09000000-0x09FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. SWITCH SETTINGS +================== +3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state + SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down + 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active + SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down + SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL + +4. COMPILATION +============== +4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version) +from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +4.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M54455EVB_config, or - default to atmel 33Mhz input clock + make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock + make M54455EVB_a33_config, or - default to atmel 33Mhz input clock + make M54455EVB_a66_config, or - default to atmel 66Mhz input clock + make M54455EVB_intel_config, or - default to intel 33Mhz input clock + make M54455EVB_i33_config, or - default to intel 33Mhz input clock + make M54455EVB_i66_config, or - default to intel 66Mhz input clock + make + +5. SCREEN DUMP +============== +5.1 M54455EVB Development board + Boot from Atmel (NOTE: May not show exactly the same) + +U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08) + +CPU: Freescale MCF54455 (Mask:48 Version:1) + CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz + PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz +Board: Freescale M54455 EVB +I2C: ready +DRAM: 256 MB +FLASH: 16.5 MB +In: serial +Out: serial +Err: serial +Net: FEC0, FEC1 +IDE: Bus 0: not available +-> print +bootargs=root=/dev/ram rw +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +eth1addr=00:e0:0c:bc:e5:61 +hostname=M54455EVB +netdev=eth0 +inpclk=33333333 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +mtdids=nor0=M54455EVB-1 +mtdparts=M54455EVB-1:16m(user) +u-boot=u-boot54455.bin +filesize=292b4 +fileaddr=40010000 +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 563/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x10000000 +flashstart = 0x00000000 +flashsize = 0x01080000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 133.333 MHz +pcifreq = 33.333 MHz +flbfreq = 66.666 MHz +inpfreq = 33.333 MHz +vcofreq = 533.333 MHz +ethaddr = 00:E0:0C:BC:E5:60 +eth1addr = 00:E0:0C:BC:E5:61 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +diskboot- boot from IDE device +echo - echo args to console +erase - erase FLASH memory +ext2load- load binary file from a Ext2 filesystem +ext2ls - list files in a directory (default /) +fatinfo - print information about filesystem +fatload - load binary file from a dos filesystem +fatls - list files in a directory (default /) +flinfo - print FLASH memory information +fsinfo - print information about filesystems +fsload - load binary file from a filesystem image +go - start application at address 'addr' +help - print online help +i2c - I2C sub-system +icache - enable or disable instruction cache +ide - IDE sub-system +iminfo - print header information for application image +imls - list all images found in flash +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +pci - list and access PCI Configuration Space +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +source - run script from memory +tftpboot- boot image via network using TFTP protocol +version - print monitor version +->bootm 4000000 + +## Booting image at 04000000 ... + Image Name: Linux Kernel Image + Created: 2007-08-14 15:13:00 UTC + Image Type: M68K Linux Kernel Image (uncompressed) + Data Size: 2301952 Bytes = 2.2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK +OK +Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr +erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007 +starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB +Built 1 zonelists. Total pages: 32624 +Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph +ysmap-flash.0:5M(kernel)ro,-(jffs2) +PID hash table entries: 1024 (order: 10, 4096 bytes) +Console: colour dummy device 80x25 +Dentry cache hash table entries: 32768 (order: 4, 131072 bytes) +Inode-cache hash table entries: 16384 (order: 3, 65536 bytes) +Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init) +Mount-cache hash table entries: 1024 +NET: Registered protocol family 16 +SCSI subsystem initialized +NET: Registered protocol family 2 +IP route cache hash table entries: 2048 (order: 0, 8192 bytes) +TCP established hash table entries: 8192 (order: 2, 32768 bytes) +TCP bind hash table entries: 4096 (order: 1, 16384 bytes) +TCP: Hash tables configured (established 8192 bind 4096) +TCP reno registered +JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler anticipatory registered +io scheduler deadline registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 +ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART +RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize +loop: loaded (max 8 devices) +FEC ENET Version 0.2 +fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849 +eth0: ethernet 00:08:ee:00:e4:19 +physmap platform flash device: 01000000 at 04000000 +physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank + Intel/Sharp Extended Query Table at 0x0031 +Using buffer write method +cfi_cmdset_0001: Erase suspend on write enabled +2 cmdlinepart partitions found on MTD device physmap-flash.0 +Creating 2 MTD partitions on "physmap-flash.0": +0x00000000-0x00500000 : "kernel" +mtd: Giving out device 0 to kernel +0x00500000-0x01000000 : "jffs2" +mtd: Giving out device 1 to jffs2 +mice: PS/2 mouse device common for all mice +i2c /dev entries driver +TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +NET: Registered protocol family 15 +VFS: Mounted root (jffs2 filesystem). +Setting the hostname to freescale +Mounting filesystems +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory +Starting syslogd and klogd +Setting up networking on loopback device: +Setting up networking on eth0: +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +Adding static route for default gateway to 172.27.255.254: +Setting nameserver to 172.27.0.1 in /etc/resolv.conf: +Starting inetd: +/ # diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README new file mode 100644 index 00000000000..d3aec20e4f1 --- /dev/null +++ b/board/freescale/m547xevb/README @@ -0,0 +1,272 @@ +Freescale MCF5475EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created Jan 08, 2008 +=========================================== + + +Changed files: +============== + +- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init +- board/freescale/m547xevb/mii.c MII init +- board/freescale/m547xevb/Makefile Makefile +- board/freescale/m547xevb/config.mk config make +- board/freescale/m547xevb/u-boot.lds Linker description + +- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code +- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support +- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf547x_8x/Makefile Makefile +- arch/m68k/cpu/mcf547x_8x/config.mk config make +- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code + +- doc/README.m5475evb This readme file + +- drivers/dma/MCD_dmaApi.c DMA API functions +- drivers/dma/MCD_tasks.c DMA Tasks +- drivers/dma/MCD_tasksInit.c DMA Tasks Init +- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- include/MCD_dma.h DMA header file +- include/MCD_progCheck.h DMA header file +- include/MCD_tasksInit.h DMA header file +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/errno.h Error Number definition +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M5475EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/traps.c Exception init code + +1 MCF547x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M5475EVB Development Board +CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs +CONFIG_M547x -- define for all Freescale MCF547x CPUs +CONFIG_M5475 -- define for M5475EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_FSLDMAFEC -- define to use common dma FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop +CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot + +CONFIG_CMD_USB -- enable USB commands +CONFIG_USB_OHCI_NEW -- enable USB OHCI driver +CONFIG_USB_STORAGE -- enable USB Storage device +CONFIG_DOS_PARTITION -- enable DOS read/write + +CONFIG_SLTTMR -- define to use SLT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_PCI -- define for PCI support +CONFIG_PCI_PNP -- define for Plug n play support +CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge +CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset +CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset +CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size +CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset +CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset +CONFIG_SYS_PCI_IO_SIZE -- PCI IO size +CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset +CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset +CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0xFF800000-0xFFFFFFFF (8MB) + DDR: 0x00000000-0x3FFFFFFF (1024MB) + SRAM: 0xF2000000-0xF2000FFF (4KB) + PCI: 0x70000000-0x8FFFFFFF (512MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux + version) from codesourcery.com was used. Download it from: + http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M5475AFE_config, or - boot 2MB, RAM 64MB + make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB + make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB + make M5475DFE_config, or - boot 2MB, USB, RAM 64MB + make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB + make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB + make M5475GFE_config, or - boot 2MB, RAM 64MB + make + +5. SCREEN DUMP +============== +5.1 + +U-Boot 1.3.1 (Jan 8 2008 - 12:47:44) + +CPU: Freescale MCF5475 + CPU CLK 266 Mhz BUS CLK 133 Mhz +Board: Freescale FireEngine 5475 EVB +I2C: ready +DRAM: 64 MB +FLASH: 18 MB +In: serial +Out: serial +Err: serial +Net: FEC0, FEC1 +-> pri +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +eth1addr=00:e0:0c:bc:e5:61 +ipaddr=192.162.1.2 +serverip=192.162.1.1 +gatewayip=192.162.1.1 +netmask=255.255.255.0 +hostname=M547xEVB +netdev=eth0 +loadaddr=10000 +u-boot=u-boot.bin +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save +stdin=serial +stdout=serial +stderr=serial +ethact=FEC0 +mem=65024k + +Environment size: 433/8188 bytes +-> bdin +memstart = 0x00000000 +memsize = 0x04000000 +flashstart = 0xFF800000 +flashsize = 0x01200000 +flashoffset = 0x00000000 +sramstart = 0xF2000000 +sramsize = 0x00001000 +mbar = 0xF0000000 +busfreq = 133.333 MHz +pcifreq = 0 MHz +ethaddr = 00:E0:0C:BC:E5:60 +eth1addr = 00:E0:0C:BC:E5:61 +ip_addr = 192.162.1.2 +baudrate = 115200 bps +-> ? +? - alias for 'help' +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +i2c - I2C sub-system +icache - enable or disable instruction cache +iminfo - print header information for application image +imls - list all images found in flash +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +pci - list and access PCI Configuration Space +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +source - run script from memory +tftpboot- boot image via network using TFTP protocol +usb - USB sub-system +usbboot - boot from USB device +version - print monitor version +-> usb start +(Re)start USB... +USB: OHCI pci controller (1131, 1561) found @(0:17:0) +OHCI regs address 0x80000000 +scanning bus for devices... 2 USB Device(s) found + scanning bus for storage devices... 1 Storage Device(s) found +-> diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README new file mode 100644 index 00000000000..cbb043e1d00 --- /dev/null +++ b/board/freescale/mpc7448hpc2/README @@ -0,0 +1,184 @@ +Freescale MPC7448hpc2 (Taiga) board +=================================== + +Created 08/11/2006 Roy Zang +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX +chassis. + +Building U-Boot +------------------ +The mpc7448hpc2 code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make mpc7448hpc2_config + Configuring for mpc7448hpc2 board... + + $ make + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + +Board Switches +---------------------- + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README new file mode 100644 index 00000000000..be7ef32b45f --- /dev/null +++ b/board/freescale/mpc8313erdb/README @@ -0,0 +1,111 @@ +Freescale MPC8313ERDB Board +----------------------------------------- + +1. Board Switches and Jumpers + + S3 is used to set CONFIG_SYS_RESET_SOURCE. + + To boot the image at 0xFE000000 in NOR flash, use these DIP + switch settings for S3 S4: + + +------+ +------+ + | | | **** | + | **** | | | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + + To boot the image at the beginning of NAND flash, use these + DIP switch settings for S3 S4: + + +------+ +------+ + | * | | *** | + | *** | | * | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + + When booting from NAND, use u-boot-nand.bin, not u-boot.bin. + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x07ff_ffff DDR 128M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K + 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K + 0xfa00_0000 0xfa00_7fff Board Status/ 32K + LED Control (CS3) + 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M + + When booting from NAND, NAND flash is CS0 and NOR flash + is CS1. + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8313ERDB.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC831x MPC831x specific + CONFIG_MPC8313ERDB MPC8313ERDB board specific + +4. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make MPC8313ERDB_XXX_config + (where XXX is: + 33 - 33 MHz oscillator, boot from NOR flash + 66 - 66 MHz oscillator, boot from NOR flash + NAND_33 - 33 MHz oscillator, boot from NAND flash + NAND_66 - 66 MHz oscillator, boot from NAND flash) + make + +5. Downloading and Flashing Images + +5.1 Reflash U-boot Image using U-boot + + NOR flash: + + =>run tftpflash + + You may want to try + =>tftpboot $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + have an alternate means of programming the flash available + if the new u-boot doesn't boot. + + NAND flash: + + =>tftpboot $loadaddr <filename> + =>nand erase 0 0x80000 + =>nand write $loadaddr 0 0x80000 + + ...where 0x80000 is the filesize rounded up to + the next 0x20000 increment. + +5.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, rootpath (if using NFS root), + fdtfile, and bootfile). + + Then, do one of the following, depending on whether you + want an NFS root or a ramdisk root: + + =>run nfsboot + or + =>run ramboot + +6 Notes + + The console baudrate for MPC8313ERDB is 115200bps. diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README new file mode 100644 index 00000000000..b32132d0533 --- /dev/null +++ b/board/freescale/mpc8315erdb/README @@ -0,0 +1,105 @@ +Freescale MPC8315ERDB Board +----------------------------------------- + +1. Board Switches and Jumpers + + S3 is used to set CONFIG_SYS_RESET_SOURCE. + + To boot the image at 0xFE000000 in NOR flash, use these DIP + switch settings for S3 S4: + + +------+ +------+ + | | | **** | + | **** | | | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + + To boot the image at the beginning of NAND flash, use these + DIP switch settings for S3 S4: + + +------+ +------+ + | * | | *** | + | *** | | * | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + + When booting from NAND, use u-boot-nand.bin, not u-boot.bin. + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x07ff_ffff DDR 128M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K + 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M + + When booting from NAND, NAND flash is CS0 and NOR flash + is CS1. + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8315ERDB.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC831x MPC831x specific + CONFIG_MPC8315 MPC8315 specific + CONFIG_MPC8315ERDB MPC8315ERDB board specific + +4. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin) + make all + +5. Downloading and Flashing Images + +5.1 Reflash U-boot Image using U-boot + + NOR flash: + + tftp 40000 u-boot.bin + protect off all + erase fe000000 fe1fffff + + cp.b 40000 fe000000 xxxx + protect on all + + You have to supply the correct byte count with 'xxxx' + from the TFTP result log. + + NAND flash: + + =>tftpboot $loadaddr <filename> + =>nand erase 0 0x80000 + =>nand write $loadaddr 0 0x80000 + + ...where 0x80000 is the filesize rounded up to + the next 0x20000 increment. + +5.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, rootpath (if using NFS root), + fdtfile, and bootfile). + + Then, do one of the following, depending on whether you + want an NFS root or a ramdisk root: + + =>run nfsboot + or + =>run ramboot + +6 Notes + + The console baudrate for MPC8315ERDB is 115200bps. diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README new file mode 100644 index 00000000000..6f898293735 --- /dev/null +++ b/board/freescale/mpc8323erdb/README @@ -0,0 +1,71 @@ +Freescale MPC8323ERDB Board +----------------------------------------- + +1. Memory Map + The memory map looks like this: + + 0x0000_0000 0x03ff_ffff DDR 64M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xd000_0000 0xd3ff_ffff PCI IO 64M + 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M + +2. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make MPC8323ERDB_config + make + +3. Downloading and Flashing Images + +3.1 Reflash U-boot Image using U-boot + + N.b, have an alternate means of programming + the flash available if the new u-boot doesn't boot. + + First try a: + + tftpboot $loadaddr $uboot + + to make sure that the TFTP load will succeed before + an erase goes ahead and wipes out your current firmware. + Then do a: + + run tftpflash + + which is a shorter version of the manual sequence: + + tftp $loadaddr u-boot.bin + protect off fe000000 +$filesize + erase fe000000 +$filesize + cp.b $loadaddr fe000000 $filesize + + To keep your old u-boot's environment variables, do a: + + saveenv + + prior to resetting the board. + +3.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, rootpath (if using NFS root), + fdtfile, and bootfile). + + Then, do one of the following, depending on whether you + want an NFS root or a ramdisk root: + + run nfsboot + + or + + run ramboot + +4 Notes + + The console baudrate for MPC8323ERDB is 115200bps. diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README new file mode 100644 index 00000000000..4142aa9c8d5 --- /dev/null +++ b/board/freescale/mpc832xemds/README @@ -0,0 +1,128 @@ +Freescale MPC832XEMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW3 is switch 18 as silk-screened onto the board. + SW4[8] is the bit labeled 8 on Switch 4. + SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. + SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. + SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC832XEMDS PROTO Board + + First, make sure the board default setting is consistent with the document + shipped with your board. Then apply the following setting: + SW3[1-8]= 0000_1000 (core PLL setting, core enable) + SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) + SW5[1-8]= 0010_0110 (Boot from high end) + SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) + SW7[1-8]= 1000_0011 (QE PLL setting) + + ENET3/4 MII mode settings: + J1 1-2 (ETH3_TXER) + J2 2-3 (MII mode) + J3 2-3 (MII mode) + J4 2-3 (ADSL clockOscillator) + J5 1-2 (ETH4_TXER) + J6 2-3 (ClockOscillator) + JP1 removed (don't force PORESET) + JP2 mounted (ETH4/2 MII) + JP3 mounted (ETH3 MII) + JP4 mounted (HRCW from BCSR) + + ENET3/4 RMII mode settings: + J1 1-2 (ETH3_TXER) + J2 1-2 (RMII mode) + J3 1-2 (RMII mode) + J4 2-3 (ADSL clockOscillator) + J5 1-2 (ETH4_TXER) + J6 2-3 (ClockOscillator) + JP1 removed (don't force PORESET) + JP2 removed (ETH4/2 RMII) + JP3 removed (ETH3 RMII) + JP4 removed (HRCW from FLASH) + + on board Oscillator: 66M + + +2. Memory Map + +2.1 The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M + 0xe020_0000 0xe02f_ffff Empty 1M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xefff_ffff Empty 252M + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xf800_8000 0xf800_ffff PIB CS2 32K + 0xf801_0000 0xf801_7fff PIB CS3 32K + 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC832XEPB.h + + CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x + CONFIG_MPC832x MPC832x specific + CONFIG_MPC832XEMDS MPC832XEMDS board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC832XEMDS_config + make + + MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: + + 1)Make sure the DIP SW support PCI mode as described in Section 1.1. + + 2)To Make U-Boot image support PCI 33MHz, use + Make MPC832XEMDS_HOST_33_config + + 3)To Make U-Boot image support PCI 66MHz, use + Make MPC832XEMDS_HOST_66M_config + +5. Downloading and Flashing Images + +5.0 Download over network: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 20000 u-boot.bin + protect off fe000000 fe0fffff + erase fe000000 fe0fffff + cp.b 20000 fe000000 xxxx + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. +Maybe 3ffff will work too, that corresponds to the erased sectors. + + +6. Notes + 1) The console baudrate for MPC832XEMDS is 115200bps. diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README new file mode 100644 index 00000000000..48bbd50356e --- /dev/null +++ b/board/freescale/mpc8349itx/README @@ -0,0 +1,187 @@ +Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards +--------------------------------------------------- + +1. Board Description + + The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring + the Freescale MPC8349E processor in a Mini-ITX form factor. + + The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: + + A) One 8MB on-board flash EEPROM chip, instead of two. + B) No SATA controller + C) No Compact Flash slot + D) No Mini-PCI slot + E) No Vitesse 7385 5-port Ethernet switch + F) No 4-port USB Type-A interface + +2. Board Switches and Jumpers + +2.0 Descriptions for all of the board jumpers can be found in the User + Guide. Of particular interest to U-Boot developers is jumper J22: + + Pos. Name Default Description + ----------------------------------------------------------------------- + A LGPL0 ON (0) HRCW source, bit 0 + B LGPL1 ON (0) HRCW source, bit 1 + C LGPL3 ON (0) HRCW source, bit 2 + D LGPL5 OFF (1) PCI_SYNC_OUT frequency + E BOOT1 ON (0) Flash EEPROM boot device + F PCI_M66EN ON (0) PCI 66MHz enable + G I2C-WP ON (0) I2C EEPROM write protection + H F_WP OFF (1) Flash EEPROM write protection + + Jumper J22.E is only for the ITX, and it decides the configuration + of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip + U4 is located at address FE000000 and flash chip U7 is at FE800000. + If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. + + For U-Boot development, J22.E can be used to switch back-and-forth + between two U-Boot images. + +3. Memory Map + +3.1. The memory map should look pretty much like this: + + 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) + 0xF001_0000 - 0xF001_FFFF Local bus expansion slot + 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) + 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) + +3.2 Flash EEPROM layout. + + On the ITX, jumper J22.E is used to determine which flash chips are + at which address. When J22.E is switched, addresses from FE000000 + to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. + + On the ITX, at the normal boot address (aka HIGHBOOT): + + FE00_0000 HRCW + FE70_0000 Alternative U-Boot image + FE80_0000 Alternative HRCW + FEF0_0000 U-Boot image + FEFF_FFFF End of flash + + On the ITX, at the low boot address (LOWBOOT) + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + FE80_0000 Alternative HRCW and U-Boot image + FEFF_FFFF End of flash + + On the ITX-GP, the only option is LOWBOOT and there is only one chip + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + F7FF_FFFF End of flash + +4. Definitions + +4.1 Explanation of NEW definitions in: + + include/configs/MPC8349ITX.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ITX MPC8349E-mITX + CONFIG_MPC8349ITXGP MPC8349E-mITX-GP + +5. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + + make MPC8349ITX_config + or: + make MPC8349ITXGP_config + or: + make MPC8349ITX_LOWBOOT_config + + make + +6. Downloading and Flashing Images + +6.1 Download via tftp: + + tftp $loadaddr <uboot> + + where "<uboot>" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.1 Reflash U-Boot Image using U-Boot + + setenv uboot <uboot> + run tftpflash + + where "<uboot>" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.2 Using the HRCW to switch between two different U-Boot images on the ITX + + Because the ITX has 16MB of flash, it is possible to keep two U-Boot + images in flash, and use the HRCW to specify which one is to be used + when the board boots. This trick is especially effective with a + hardware debugger that can override the HRCW, such as the BDI-2000. + + When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image + at address FE000000. When the BMS bit is 1, the ITX will boot the + image at address FEF00000. + + Therefore, just put a U-Boot image at both FE000000 and FEF00000 and + change the BMS bit whenever you want to boot the other image. + + Step-by-step instructions: + + 1) Build an ITX image to be loaded at FEF00000 + + make distclean + make MPC8349ITX_config + make + + 2) Take the u-boot.bin image and flash it at FEF00000. + + tftp $loadaddr u-boot.bin + protect off all + erase FEF00000 +$filesize + cp.b $loadaddr FEF00000 $filesize + + 3) Build an ITX image to be loaded at FE000000 + + make distclean + make MPC8349ITX_LOWBOOT_config + make + + 4) Take the u-boot.bin image and flash it at FE000000. + + tftp $loadaddr u-boot.bin + protect off FE000000 +$filesize + erase FE000000 +$filesize + cp.b $loadaddr FE000000 $filesize + + The HRCW in flash is currently set to boot the image at FE000000. + + If you have a hardware debugger, configure it to set the HRCW to + B460A000 04040000 if you want to boot the image at FEF00000, or set + it to B060A000 04040000 if you want to boot the image at FE000000. + + To change the HRCW in flash to boot the image at FEF00000, use these + U-Boot commands: + + cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 + mw.b 1020 b4 8 ; modify BMS bit + protect off FE000000 +10000 + erase FE000000 +10000 + cp.b 1000 FE000000 10000 + +7. Notes + 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README new file mode 100644 index 00000000000..6afa7539690 --- /dev/null +++ b/board/freescale/mpc8360emds/README @@ -0,0 +1,155 @@ +Freescale MPC8360EMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW18 is switch 18 as silk-screened onto the board. + SW4[8] is the bit labeled 8 on Switch 4. + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. + SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. + SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 There are three type boards for MPC8360E silicon up to now, They are + + * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) + * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) + * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) + +1.2 For all the MPC8360EMDS Board + + First, make sure the board default setting is consistent with the + document shipped with your board. Then apply the following setting: + SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) + SW4[1-8]= 0011_0000 (Flash boot on local bus) + SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH) + SW10[1-8]= 0000_1000 (core PLL setting) + SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) + JP6 1-2 + on board Oscillator: 66M + +1.3 Since different board/chip rev. combinations have AC timing issues, + u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default + by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). + + When the rev2.x silicon mount on these boards, and if you are using + u-boot version after this patch, to make the ethernet interfaces usable, + and to enable RGMII-ID on your board, you have to setup the jumpers + correctly. + + * MPC8360E-MDS-PB PROTO + nothing to do + * MPC8360E-MDS-PB PILOT + JP9 and JP8 should be ON + * MPC8360EA-MDS-PB PROTO + JP2 and JP3 should be ON + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M + 0xe020_0000 0xe02f_ffff Empty 1M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xefff_ffff Empty 252M + 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xf800_8000 0xf800_ffff PIB CS4 32K + 0xf801_0000 0xf801_7fff PIB CS5 32K + 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC8360EMDS.h + + CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 + CONFIG_MPC8360 MPC8360 specific + CONFIG_MPC8360EMDS MPC8360EMDS board specific + +4. Compilation + + MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip). + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC8360EMDS_XX_config + make + + MPC8360EMDS support ATM, PCI in host and slave mode. + + To make u-boot support ATM : + 1) Make MPC8360EMDS_XX_ATM_config + + To make u-boot support PCI host 66M : + 1) DIP SW support PCI mode as described in Section 1.1. + 2) Make MPC8360EMDS_XX_HOST_66_config + + To make u-boot support PCI host 33M : + 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 + 2) Make MPC8360EMDS_XX_HOST_33_config + + To make u-boot support PCI slave 66M : + 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 + 2) Make MPC8360EMDS_XX_SLAVE_config + + (where XX is: + 33 - 33.33MHz oscillator + 66 - 66MHz oscillator) + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 20000 u-boot.bin + protect off fef00000 fef3ffff + erase fef00000 fef3ffff + + cp.b 20000 fef00000 xxxx + + or + + cp.b 20000 fef00000 3ffff + + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. +Maybe 3ffff will work too, that corresponds to the erased sectors. + + +6. Notes + 1) The console baudrate for MPC8360EMDS is 115200bps. diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README new file mode 100644 index 00000000000..faf21c9ffb6 --- /dev/null +++ b/board/freescale/mpc837xemds/README @@ -0,0 +1,104 @@ +Freescale MPC837xEMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW4[8] is the bit labeled 8 on Switch 4. + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. + SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC837xEMDS Processor Board + + First, make sure the board default setting is consistent with the + document shipped with your board. Then apply the following setting: + SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) + SW4[1-8]= 0000_0110 (core PLL setting) + SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) + SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) + SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) + J3 2-3, TSEC1 LVDD1 with 2.5V + J6 2-3, TSEC2 LVDD2 with 2.5V + J9 2-3, CLKIN from osc on board + J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND + J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) + mounted, HRCW load from BCSR. + + on board Oscillator: 66M + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M + 0xe010_0000 0xe02f_ffff Empty 2M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xe05f_ffff Empty 2M + 0xe060_0000 0xe060_7fff NAND Flash 32K + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC837XEMDS.h + + CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360 + CONFIG_MPC837x MPC837x specific + CONFIG_MPC837XEMDS MPC837XEMDS board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC837XEMDS_config + make + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 40000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 40000 u-boot.bin + protect off fe000000 fe1fffff + erase fe000000 fe1fffff + + cp.b 40000 fe000000 xxxx + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. + +6. Notes + 1) The console baudrate for MPC837XEMDS is 115200bps. diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README new file mode 100644 index 00000000000..cfb6efa27e4 --- /dev/null +++ b/board/freescale/mpc837xerdb/README @@ -0,0 +1,97 @@ +Freescale MPC837xE-RDB Board +----------------------------------------- + +1. Board Description + + The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E, + MPC8378E, and the MPC8379E processors in a Mini-ITX form factor. + + The MPC837xE-RDB's have the following common features: + + A) 256-MBytes on-board DDR2 unbuffered SDRAM + B) 8-Mbytes NOR Flash + C) 32-MBytes NAND Flash + D) 1 Secure Digital High Speed Card (SDHC) Interface + E) 1 Gigabit Ethernet + F) 5-port Ethernet switch (Vitesse 7385) + G) 1 32-bit, 3.3 V, PCI slot + H) 1 32-bit, 3.3 V, Mini-PCI slot + I) 4-port USB 2.0 Hub + J) 1-port OTG USB + K) 2 serial ports (top main console) + L) on board Oscillator: 66M + + The MPC837xE-RDB's have the following differences: + + MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB + SATA controllers 2 0 4 + PCI-Express (mini) 2 2 0 + SGMII Ports 0 2 0 + + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + Address Range Device Size Port Size + (Bytes) (Bits) + =========================== ================= ======= ========= + 0x0000_0000 0x0fff_ffff DDR 256M 64 + 0x1000_0000 0x7fff_ffff Empty 1.75G - + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32 + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32 + 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32 + 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - + 0xe060_0000 0xe060_7fff NAND Flash 32K 8 + 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16 + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC837XERDB.h + + CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 + CONFIG_MPC837x MPC837x specific + CONFIG_MPC837XERDB MPC837xE-RDB board specific + + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC837XERDB_config + make + + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb $loadaddr + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp $loadaddr u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp $loadaddr u-boot.bin + protect off fe000000 fe0fffff + erase fe000000 fe0fffff + cp.b $loadaddr fe000000 $filesize + + +6. Additional Notes: + 1) The console is connected to the top RS-232 connector and the + baudrate for MPC837XE-RDB is 115200bps. diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README new file mode 100644 index 00000000000..2a38bd6dda5 --- /dev/null +++ b/board/freescale/mpc8536ds/README @@ -0,0 +1,127 @@ +Overview: +========= + +The MPC8536E integrates a PowerPC processor core with system logic +required for imaging, networking, and communications applications. + +Boot from NAND: +=============== + +The MPC8536E is capable of booting from NAND flash which uses the image +u-boot-nand.bin. This image contains two parts: a first stage image(also +call 4K NAND loader and a second stage image. The former is appended to +the latter to produce u-boot-nand.bin. + +The bootup process can be divided into two stages: the first stage will +configure the L2SRAM, then copy the second stage image to L2SRAM and jump +to it. The second stage image is to configure all the hardware and boot up +to U-Boot command line. + +The 4K NAND loader's code comes from the corresponding nand_spl directory, +along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL +is mainly used to shrink the code size to the 4K size limitation. + +The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the +second stage image. It's set in the board config file when boot from NAND +is selected. + +Build and boot steps +-------------------- + +1. Building image + make MPC8536DS_NAND_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 1011 + SW9[1-3] = 101 + Note: 1 stands for 'on', 0 stands for 'off' + +3. Flash image + tftp 1000000 u-boot-nand.bin + nand erase 0 a0000 + nand write 1000000 0 a0000 + +Boot from On-chip ROM: +====================== + +The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC +and boot from eSPI. When power on, the porcessor excutes the ROM code to +initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from +the memory device that interfaced to the controller, such as the SDCard or +SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. + +The memory device should contain a specific data structure with control word +and config word at the fixed address. The config word direct the process how +to config the memory device, and the control word direct the processor where +to find the image on the memory device, or where copy the main image to. The +user can use any method to store the data structure to the memory device, only +if store it on the assigned address. + +Build and boot steps +-------------------- + +For boot from eSDHC: +1. Build image + make MPC8536DS_SDCARD_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0111 + SW3[1] = 0 + SW8[7] = 0 - The on-board SD/MMC slot is active + SW8[7] = 1 - The externel SD/MMC slot is active + +3. Put image to SDCard + Put the follwing info at the assigned address on the SDCard: + + Offset | Data | Description + -------------------------------------------------------- + | 0x40-0x43 | 0x424F4F54 | BOOT signature | + -------------------------------------------------------- + | 0x48-0x4B | 0x00080000 | u-boot.bin's size | + -------------------------------------------------------- + | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard | + -------------------------------------------------------- + | 0x58-0x5B | 0xF8F80000 | Target Address | + ------------------------------------------------------- + | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | + -------------------------------------------------------- + | 0x68-0x6B | 0x6 | Number of Config Addr/Data | + -------------------------------------------------------- + | 0x80-0x83 | 0xFF720100 | Config Addr 1 | + | 0x84-0x87 | 0xF8F80000 | Config Data 1 | + -------------------------------------------------------- + | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | + | 0x8c-0x8f | 0x0000000C | Config Data 2 | + -------------------------------------------------------- + | 0x90-0x93 | 0xFF720000 | Config Addr 3 | + | 0x94-0x97 | 0x80010000 | Config Data 3 | + -------------------------------------------------------- + | 0x98-0x9b | 0xFF72e40c | Config Addr 4 | + | 0x9c-0x9f | 0x00000040 | Config Data 4 | + -------------------------------------------------------- + | 0xa0-0xa3 | 0x40000001 | Config Addr 5 | + | 0xa4-0xa7 | 0x00000100 | Config Data 5 | + -------------------------------------------------------- + | 0xa8-0xab | 0x80000001 | Config Addr 6 | + | 0xac-0xaf | 0x80000001 | Config Data 6 | + -------------------------------------------------------- + | ...... | + -------------------------------------------------------- + | 0x???????? | u-boot.bin | + -------------------------------------------------------- + + then insert the SDCard to the active slot to boot up. + +For boot from eSPI: +1. Build image + make MPC8536DS_SPIFLASH_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0110 + +3. Put image to SPI flash + Put the info in the above table onto the SPI flash, then + boot up. diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README new file mode 100644 index 00000000000..b49c3c07c40 --- /dev/null +++ b/board/freescale/mpc8544ds/README @@ -0,0 +1,122 @@ +Overview +-------- +The MPC8544DS system is similar to the 85xx CDS systems such +as the MPC8548CDS due to the similar E500 core. However, it +is placed on the same board as the 8641 HPCN system. + + +Flash Banks +----------- +Like the 85xx CDS systems, the 8544 DS board has two flash banks. +They are both present on boot, but there locations can be swapped +using the dip-switch SW10, bit 2. + +However, unlike the CDS systems, but similar to the 8641 HPCN +board, a runtime reset through the FPGA can also affect a swap +on the flash bank mappings for the next reset cycle. + +Irrespective of the switch SW10[2], booting is always from the +boot bank at 0xfff8_0000. + + +Memory Map +---------- + +0xff80_0000 - 0xffbf_ffff Alternate bank 4MB +0xffc0_0000 - 0xffff_ffff Boot bank 4MB + +0xffb8_0000 Alternate image start 512KB +0xfff8_0000 Boot image start 512KB + + +Flashing Images +--------------- + +For example, to place a new image in the alternate flash bank +and then reset with that new image temporarily, use this: + + tftp 1000000 u-boot.bin.8544ds + erase ffb80000 ffbfffff + cp.b 1000000 ffb80000 80000 + pixis_reset altbank + + +To overwrite the image in the boot flash bank: + + tftp 1000000 u-boot.bin.8544ds + protect off all + erase fff80000 ffffffff + cp.b 1000000 fff80000 80000 + +Other example U-Boot image and flash manipulations examples +can be found in the README.mpc85xxcds file as well. + + +The pixis_reset command +----------------------- +A new command, "pixis_reset", is introduced to reset mpc8641hpcn board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + +Valid clock choices are in the 8641 Reference Manuals. + + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts + +After placing the DTB file in your TFTP disk area, +you can download that dtb file using a command like: + + tftp 900000 mpc8544ds.dtb + +Burn it to flash if you want. + + +Booting Linux +------------- + +Place a linux uImage in the TFTP disk area too. + + tftp 1000000 uImage.8544 + tftp 900000 mpc8544ds.dtb + bootm 1000000 - 900000 + +Watch your ethact, netdev and bootargs U-Boot environment variables. +You may want to do something like this too: + + setenv ethact eTSEC3 + setenv netdev eth1 diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README new file mode 100644 index 00000000000..3d12a964cd7 --- /dev/null +++ b/board/freescale/mpc8569mds/README @@ -0,0 +1,77 @@ +Overview +-------- +MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform +I/O Board). The mpc8569 PowerTM processor is mounted on PB board. + +Building U-boot +----------- + make MPC8569MDS_config + make + +Memory Map +---------- +0x0000_0000 0x7fff_ffff DDR 2G +0xa000_0000 0xbfff_ffff PCIe MEM 512MB +0xe000_0000 0xe00f_ffff CCSRBAR 1M +0xe280_0000 0xe2ff_ffff PCIe I/O 8M +0xc000_0000 0xdfff_ffff SRIO 512MB +0xf000_0000 0xf3ff_ffff SDRAM 64MB +0xf800_0000 0xf800_7fff BCSR 32KB +0xf800_8000 0xf800_ffff PIB (CS4) 32KB +0xf801_0000 0xf801_7fff PIB (CS5) 32KB +0xfe00_0000 0xffff_ffff Flash 32MB + + +Flashing u-boot Images +--------------- + +Use the following commands to program u-boot image into flash: + + => tftp 1000000 u-boot.bin + => protect off all + => erase fff80000 ffffffff + => cp.b 1000000 fff80000 80000 + + +Setting the correct MAC addresses +----------------------- +The command - "mac", is introduced to set on-board system EEPROM in the format +defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC +addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when +we first get the board. The commands are as follows: + => mac i NXID /* Set NXID to this EEPROM */ + => mac e 01 /* Set Errata, this value is not defined by hardware + designer, we can set whatever we want */ + => mac n a0 /* Set Serial Number. This is not defined by hardware + designer, we can set whatever we want */ + => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */ + + => mac p 8 /* Set the number of mac ports, it should be 8 */ + => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac + address, you can refer to the value on + the sticker of the rear side of the board + */ + ..... + => mac 7 xx:xx:xx:xx:xx:xx + => mac read + => mac save + +After resetting the board, the ethxaddrs will be filled with the mac addresses +if such environment variables are blank(never been set before). If the ethxaddr +has been set but we want to update it, we can use the following commands: + => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */ + => save + => reset + + +Programming the ucode to flash +--------------------------------- +MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's +IRAM so that the QE can work. The ucode binary can be downloaded from +http://opensource.freescale.com/firmware/, and it must be programmed to +the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot +hangs at "Net:" + + +Please note the above two steps(setting mac addresses and programming ucode) are +very important to get the board booting up and working properly. diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README new file mode 100644 index 00000000000..57fd2ad6160 --- /dev/null +++ b/board/freescale/mpc8572ds/README @@ -0,0 +1,166 @@ +Overview +-------- +MPC8572DS is a high-performance computing, evaluation and development platform +supporting the mpc8572 PowerTM processor. + +Building U-boot +----------- + make MPC8572DS_config + make + +Flash Banks +----------- +MPC8572DS board has two flash banks. They are both present on boot, but their +locations can be swapped using the dip-switch SW9[1:2]. + +Booting is always from the boot bank at 0xec00_0000. + + +Memory Map +---------- + +0xe800_0000 - 0xebff_ffff Alternate bank 64MB +0xec00_0000 - 0xefff_ffff Boot bank 64MB + +0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB +0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB + + +Flashing Images +--------------- + +To place a new u-boot image in the alternate flash bank and then reset with that + new image temporarily, use this: + + tftp 1000000 u-boot.bin + erase ebf80000 ebffffff + cp.b 1000000 ebf80000 80000 + pixis_reset altbank + + +To program the image in the boot flash bank: + + tftp 1000000 u-boot.bin + protect off all + erase eff80000 ffffffff + cp.b 1000000 eff80000 80000 + + +The pixis_reset command +----------------------- +The command - "pixis_reset", is introduced to reset mpc8572ds board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + +Examples: + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts + + +Booting Linux +------------- + +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage.8572 + tftp c00000 mpc8572ds.dtb + bootm 1000000 - c00000 + + +Implementing AMP(Asymmetric MultiProcessing) +------------- +1. Build kernel image for core0: + + a. $ make 85xx/mpc8572_ds_defconfig + + b. $ make menuconfig + - un-select "Processor support"->"Symetric multi-processing support" + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 + +2. Build kernel image for core1: + + a. $ make 85xx/mpc8572_ds_defconfig + + b. $ make menuconfig + - Un-select "Processor support"->"Symetric multi-processing support" + - Select "Advanced setup" -> " Prompt for advanced kernel + configuration options" + - Select "Set physical address where the kernel is loaded" and + set it to 0x20000000, assuming core1 will start from 512MB. + - Select "Set custom page offset address" + - Select "Set custom kernel base address" + - Select "Set maximum low memory" + - "Exit" and save the selection. + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 + +3. Create dtb for core0: + + $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb + +4. Create dtb for core1: + + $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb + +5. Bring up two cores separately: + + a. Power on the board, under u-boot prompt: + => setenv <serverip> + => setenv <ipaddr> + => setenv bootargs root=/dev/ram rw console=ttyS0,115200 + b. Bring up core1's kernel first: + => setenv bootm_low 0x20000000 + => setenv bootm_size 0x10000000 + => tftp 21000000 8572/uImage.core1 + => tftp 22000000 8572/ramdiskfile + => tftp 20c00000 8572/mpc8572ds_core1.dtb + => interrupts off + => bootm start 21000000 22000000 20c00000 + => bootm loados + => bootm ramdisk + => bootm fdt + => fdt boardsetup + => fdt chosen $initrd_start $initrd_end + => bootm prep + => cpu 1 release $bootm_low - $fdtaddr - + c. Bring up core0's kernel(on the same u-boot console): + => setenv bootm_low 0 + => setenv bootm_size 0x20000000 + => tftp 1000000 8572/uImage.core0 + => tftp 2000000 8572/ramdiskfile + => tftp c00000 8572/mpc8572ds_core0.dtb + => bootm 1000000 2000000 c00000 + +Please note only core0 will run u-boot, core1 starts kernel directly after +"cpu release" command is issued. diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README new file mode 100644 index 00000000000..31a9af3fee1 --- /dev/null +++ b/board/freescale/mpc8610hpcd/README @@ -0,0 +1,73 @@ +Freescale MPC8610HPCD board +=========================== + + +Building U-Boot +--------------- + + $ make MPC8610HPCD_config + Configuring for MPC8610HPCD board... + + $ make + + +Flashing U-Boot +--------------- +The flash is 128M starting at 0xF800_0000. + +The alternate image is at 0xFBF0_0000 +The boot image is at 0xFFF0_0000. + + +To Flash U-Boot into the booting bank: + + tftp 1000000 u-boot.bin + protect off all + erase fff00000 +$filesize + cp.b 1000000 fff00000 $filesize + + +To Flash U-boot into the alternate bank + + tftp 1000000 u-boot.bin + erase fbf00000 +$filesize + cp.b 1000000 fbf00000 $filesize + + +pixis_reset command +------------------- +A new command, "pixis_reset", is introduced to reset mpc8610hpcd board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + + +DIP Switch Settings +------------------- +To manually switch the flash banks using the DIP switch +settings, toggle both SW6:1 and SW6:2. diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README new file mode 100644 index 00000000000..d8fe0a4a136 --- /dev/null +++ b/board/freescale/mpc8641hpcn/README @@ -0,0 +1,186 @@ +Freescale MPC8641HPCN board +=========================== + +Created 05/24/2006 Haiying Wang +------------------------------- + +1. Building U-Boot +------------------ +The 86xx HPCN code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make MPC8641HPCN_config + Configuring for MPC8641HPCN board... + + $ make + + +2. Switch and Jumper Setting +---------------------------- +Jumpers: + J14 Pins 1-2 (near plcc32 socket) + +Switches: + SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1 + 01100 :: CORE = 2.5:1 + 10000 :: CORE = 3:1 + 11100 :: CORE = 3.5:1 + 10100 :: CORE = 4:1 + 01110 :: CORE = 4.5:1 + SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz + 001 :: SYSCLK = 40MHz + + SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X + 0100 :: 4X + 0110 :: 6X + 1000 :: 8X + 1010 :: 10X + 1100 :: 12X + 1110 :: 14X + 0000 :: 16X + SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus + + SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V + 0100000 :: VCORE = 1.11V + SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V + 1 :: VCC_PLAT = 1.0V + + SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root + SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq + SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX + + SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash + 0 :: boot from PromJet + SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower + halves (virtual banks) + 0 :: normal + SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected + SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4 + 1:1 for PD6 + SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined + SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined + + SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff + SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation + SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ + SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 :: + SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 :: + SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 :: + + SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 + SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled + SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode + SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz + SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode + SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled + SW8(7) = 1 ACPWR = 1 :: non-battery + SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable + + +3. Flash U-Boot +--------------- +The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves. +It is possible to use either half to boot using u-boot. Switch 5 bit 2 +is used for this purpose. + +0xEF800000 to 0xEFBFFFFF - 4MB +0xEFC00000 to 0xEFFFFFFF - 4MB +When this bit is 0, U-Boot is at 0xEFF00000. +When this bit is 1, U-Boot is at 0xEFB00000. + +Use the above mentioned flash commands to program the other half, and +use switch 5, bit 2 to alternate between the halves. Note: The booting +version of U-Boot will always be at 0xEFF00000. + +To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF): + + tftp 1000000 u-boot.bin + protect off all + erase eff00000 +$filesize + cp.b 1000000 eff00000 $filesize + +or use tftpflash command: + run tftpflash + +To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF): + + tftp 1000000 u-boot.bin + erase efb00000 +$filesize + cp.b 1000000 efb00000 $filesize + + +4. Memory Map +------------- +NOTE: RIO and PCI are mutually exclusive, so they share an address + +For 32-bit u-boot, devices are mapped so that the virtual address == +the physical address, and the map looks liks this: + + Memory Range Device Size + ------------ ------ ---- + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff RIO MEM 512M + 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M + 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M + 0xffe0_0000 0xffef_ffff CCSR 1M + 0xffdf_0000 0xffdf_7fff PIXIS 8K + 0xffdf_8000 0xffdf_ffff CF 8K + 0xf840_0000 0xf840_3fff Stack space 32K + 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K + 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K + 0xef80_0000 0xefff_ffff Flash 8M + +For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit. +However, the physical map is altered to reside in 36-bit space, as follows. +Addresses are no longer mapped with VA == PA. All accesses from +software use the VA; the PA is only used for setting up windows +and mappings. Note that with the exception of PCI MEM and RIO, the low + 32 bits are the same as the VA above; only the top 4 bits vary: + + Memory Range Device Size + ------------ ------ ---- + 0x0_0000_0000 0x0_7fff_ffff DDR 2G + 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M + 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M + 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M + 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M + 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K + 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K + 0x0_f840_0000 0xf_f840_3fff Stack space 32K + 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K + 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K + 0xf_ef80_0000 0xf_efff_ffff Flash 8M + +5. pixis_reset command +-------------------- +A new command, "pixis_reset", is introduced to reset mpc8641hpcn board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + +Valid clock choices are in the 8641 Reference Manuals. diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README new file mode 100644 index 00000000000..3d69ed5839c --- /dev/null +++ b/board/freescale/mx35pdk/README @@ -0,0 +1,188 @@ +Overview +-------------- + +mx35pdk (known als as mx35_3stack) is a development board by Freescale. +It consists of three pluggable board: + - CPU module, with CPU, RAM, flash + - Personality board, with most interfaces (USB, Network,..) + - Debug board with JTAG header. + +The board is usually delivered with redboot. This howto explains how to boot +a linux kernel and how to replace the original bootloader with U-Boot. + +The board is delivered with Redboot on the NAND flash. It is possible to +switch the boot device with the switches SW1-SW2 on the Personality board, +and with SW5-SW10 on the Debug board. + +Delivered Redboot script to start the kernel +--------------------------------------------------- + +In redboot the following script is stored: + +fis load kernel +exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" + +Kernel is taken from flash. The image is in zImage format. + +Booting from NET, rootfs on NFS: +----------------------------------- + +To change the script in redboot: + +load -r -b 0x100000 <path_to_zImage> +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" + +If the ip address is not set, you can set it with : + +ip_address -l <board_ip/netmask> -h <server_ip> + +Linux partitions: +--------------------------- + +As default, the board is shipped with these partition tables for NAND +and for NOR: + +Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": +0x00000000-0x00100000 : "nand.bootloader" +0x00100000-0x00600000 : "nand.kernel" +0x00600000-0x06600000 : "nand.rootfs" +0x06600000-0x06e00000 : "nand.configure" +0x06e00000-0x80000000 : "nand.userfs" + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. +For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. + +However, the setup in redboot is not correct and does not use the whole flash. + +Better solution is to use the kernel parameter mtdparts. +Here the resulting script to be defined in RedBoot with fconfig: + +load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 +exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" + +Flashing U-Boot +-------------------------------- + +There are two options: the original bootloader in NAND can be replaced with +u-boot, or u-boot can be stored on the NOR flash without erasing +the delivered bootloader. +The boot storage can be select using the switches on the personality board +(SW1-SW2) and on the DEBUG board (SW4-SW10). + +The second option is to be preferred if you have not a JTAG debugger. +If something goes wrong flashing the bootloader, it is always possible to +recover the board booting from the other device. + +Replacing the bootloader on the NAND +-------------------------------------- +To replace RedBoot with U-Boot, the easy way is to do this in linux. +Start the kernel with the suggested options. Make sure to have set the +mtdparts exactly as described, because this matches the layout on the +mx35pdk. + +You should see in your boot log the following entries for the NAND +flash: + +5 cmdlinepart partitions found on MTD device mxc_nand +Creating 5 MTD partitions on "mxc_nand": +0x000000000000-0x000000100000 : "boot" +0x000000100000-0x000000600000 : "linux" +0x000000600000-0x000006600000 : "root" +0x000006600000-0x000006e00000 : "cfg" +0x000006e00000-0x000080000000 : "user" + +You can use the utilities flash_eraseall and nandwrite to put +u-boot on the NAND. The bootloader is marked as "boot", and 1MB is +reserved. If everything is correct, this partition is accessed as +/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and +get the device node from the partition name: + +$ cat /proc/mtd | grep boot + +I suggest you try the utilities on a different partition to be sure +if everything works correctly. If not, and you remove RedBoot, you have to +reinstall it using the ATK tool as suggested by Freescale, or using a +JTAG debugger. + +I report the versions of the utilities I used (they are provided with ELDK): + +-bash-3.2# nandwrite --version +nandwrite $Revision: 1.32 $ + +flash_eraseall --version +flash_eraseall $Revision: 1.22 $ + +nandwrite reports a warning if the file to be saved is not sector aligned. +This should have no consequences, but I preferred to pad u-boot.bin +to get no problem at all. +$ dd if=/dev/zero of=zeros bs=1 count=74800 +$ cat u-boot.bin zeros > u-boot-padded.bin + +To erase the partition: +$ flash_eraseall /dev/mtd4 + +Writing u-boot: + +$ nandwrite /dev/mtd4 u-boot-padded.bin + +Now U-Boot is stored on the booting partition. + +To boot from NAND, you have to select the switches as follows: + +Personality board + SW2 1, 4, 5 on + 2, 3, 6, 7, 8 off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 + + +Saving U-Boot in the NOR flash +--------------------------------- + +The procedure to save in the NOR flash is quite the same as to write into the NAND. + +Check the partition for boot in the NOR flash. Setting the mtdparts as reported, +the boot partition should be /dev/mtd0. + +Creating 6 MTD partitions on "mxc_nor_flash.0": +0x00000000-0x00080000 : "Bootloader" +0x00080000-0x00480000 : "nor.Kernel" +0x00480000-0x02280000 : "nor.userfs" +0x02280000-0x03e80000 : "nor.rootfs" +0x01fe0000-0x01fe3000 : "FIS directory" +0x01fff000-0x04000000 : "Redboot config" + +To erase the whole partition: +$ flash_eraseall /dev/mtd0 + +Writing u-boot: +dd if=u-boot.bin of=/dev/mtd0 + +To boot from NOR, you have to select the switches as follows: + +Personality board + SW2 all off + SW1 all off + +Debug Board: + SW5 0 + SW6 0 + SW7 0 + SW8 1 + SW9 1 + SW10 0 diff --git a/board/freescale/mx6qsabrelite/README b/board/freescale/mx6qsabrelite/README new file mode 100644 index 00000000000..6f2f5343de2 --- /dev/null +++ b/board/freescale/mx6qsabrelite/README @@ -0,0 +1,72 @@ +U-Boot for the Freescale i.MX6q SabreLite board + +This file contains information for the port of U-Boot to the Freescale +i.MX6q SabreLite board. + +1. Boot source, boot from SD card +--------------------------------- + +The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports +boot from SD card only. However, by default, the SabreLite +boards boot from the SPI NOR flash. These boards need to be reflashed with +a small SD card loader to support boot from SD card. This small SD card loader +will be flashed into the SPI NOR. The board will still boot from SPI NOR, but +the loader will in turn request the BootROM to load the U-Boot from SD card. + +The SD card loader is available from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +under a open-source 3-clause BSD license. + +To update the SPI-NOR on the SabreLite board without the Freescale +manufacturing tool use the following procedure: + +1. Write this SD card loader onto a large SD card using: + + sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx + +Note: Replace sXx with the device representing the SD card in your system. + +Note: This writes SD card loader at address 0 + +2. Put this SD card into the slot for the large SD card (SD3 on the bottom of +the board). Make sure SW1 switch is at position "00", so that it can boot +from the fuses. + +3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot +(the default one the board is shipped with, starting from the SPI NOR) and +enter the following commands: + + MX6Q SABRELITE U-Boot > mmc dev 0 + MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 + MX6Q SABRELITE U-Boot > sf probe 1 + MX6Q SABRELITE U-Boot > sf erase 0 0x40000 + MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 + +4. done. + +In case you somehow do not succeed with this procedure you will have to use +the Freescale manufacturing tool in order to reflash the SPI-NOR. + +Note: The board now boots from full size SD3 on the bottom of the board. NOT + the micro SD4/BOOT slot on the top of the board. I.e. you have to use + full size SD cards. + +This information is taken from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +2. Build +-------- + +To build U-Boot for the SabreLite board: + + make mx6qsabrelite_config + make u-boot.imx + +To copy the resulting u-boot.imx to the SD card: + + sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync + +Note: Replace sXx with the device representing the SD card in your system. diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README new file mode 100644 index 00000000000..04d91970748 --- /dev/null +++ b/board/freescale/p1022ds/README @@ -0,0 +1,23 @@ +Overview +-------- +P1022ds is a Low End Dual core platform supporting the P1022 processor +of QorIQ series. P1022 is an e500 based dual core SOC. + + +Pin Multiplex(hwconfig setting) +------------------------------- +Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex +via hwconfig, i.e: +'setenv hwconfig usb2' to enable USB2 and disable eTsec2 +'setenv hwconfig tdm' to enable TDM and disable Audio +'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz) + and disable TDM +'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio +'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources + is 11MHz), disable eTsec2 and TDM + +Warning: TDM and AUDIO can not enable simultaneous ! +and AUDIO codec clock sources only setting as 11MHz or 12MHz ! +'setenv hwconfig 'audclk:12;tdm' --- error ! +'setenv hwconfig 'audclk:11;tdm' --- error ! +'setenv hwconfig 'audclk:10' --- error ! diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README new file mode 100644 index 00000000000..685f5daa995 --- /dev/null +++ b/board/freescale/p1023rds/README @@ -0,0 +1,101 @@ +Overview +-------- +The P1023 process includes a performance optimized implementation of the +QorIQ data Path Acceleration Architecture (DPAA). This architecture +provides the infrastructure to support simplified sharing of networking +interfaces and accelerators by multiple CPU cores. P1023 is an e500 based +dual core SOC. + +P1023RDS board is a Low End Dual core platform supporting the P1023 +processor of QorIQ series. + +Building U-boot +--------------- +To build the u-boot for P1023RDS: +Configure to NOR boot: + make P1023RDS_config +Configure to NAND boot: + make P1023RDS_NAND_config +Build: + make + +Board Switches +-------------- +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks. + +J4: all open + +Default NOR flash boot switch setting: + Sw3[1:8]: off on on off on on off off + Sw4[1:8]: off off off on off off off off + Sw6[1:8]: off on off on off on on off + Sw7[1:8]: off on off off on off off off + Sw8[1:8]: on off off off off off off off + +For NAND flash boot,set +Sw4[1:4]: off on on on + +The default native ethernet setting is for RGMII mode. +To use SGMII mode, set +SW8[1:2]: OFF OFF +SW7[6:7]: ON ON + +Memory Map +---------- +0x0000_0000 0x7fff_ffff DDR 2G Cacheable +0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable +0xc000_0000 0xdfff_ffff PCI 512M non-cacheable +0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + +0xe000_0000 0xe003_ffff BCSR 256K BCSR +0xee00_0000 0xefff_ffff NOR flash 32M NOR flash +0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M +0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable +0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + +Flashing u-boot Images +--------------- +To program the image in the boot flash bank: +NOR flash boot: + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +NAND flash boot: + => tftp 1000000 u-boot-nand.bin + => nand erase 0 80000 + => nand write 1000000 0 80000 + +Firmware ucode location +--------------------------------- +Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. +u-boot loads ucode FLASH. The location for ucode: +NOR Flash: 0xfe000000 +NAND Flash: 0x1f00000 + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/p1023rds.dts +or + make p1023rds.dtb ARCH=powerpc +in linux-2.6 directory. + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 p1023rds.dtb + bootm 1000000 2000000 c00000 diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README new file mode 100644 index 00000000000..cb664a5bd7d --- /dev/null +++ b/board/freescale/p1_p2_rdb/README @@ -0,0 +1,145 @@ +Overview +-------- +P2020RDB is a Low End Dual core platform supporting the P2020 processor +of QorIQ series. P2020 is an e500 based dual core SOC. + +Building U-boot +----------- +To build the u-boot for P2020RDB: + make P2020RDB_config + make + +NOR Flash Banks +----------- +RDB board for P2020 has two flash banks. They are both present on boot. + +Booting by default is always from the boot bank at 0xef00_0000. + +Memory Map +---------- +0xef00_0000 - 0xef7f_ffff Alternate bank 8MB +0xe800_0000 - 0xefff_ffff Boot bank 8MB + +0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB +0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB + +Switch settings to boot from the NOR flash banks +------------------------------------------------ +SW4[8]=0 default NOR Flash bank +SW4[8]=1 Alternate NOR Flash bank + +Flashing Images +--------------- +To place a new u-boot image in the alternate flash bank and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot.bin + erase ef780000 ef7fffff + cp.b 1000000 ef780000 80000 + +Now to boot from the alternate bank change the SW4[8] from 0 to 1. + +To program the image in the boot flash bank: + tftp 1000000 u-boot.bin + protect off all + erase eff80000 ffffffff + cp.b 1000000 eff80000 80000 + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage.p2020rdb + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 p2020rdb.dtb + bootm 1000000 2000000 c00000 + +Implementing AMP(Asymmetric MultiProcessing) +--------------------------------------------- +1. Build kernel image for core0: + + a. $ make 85xx/p1_p2_rdb_defconfig + + b. $ make menuconfig + - un-select "Processor support"-> + "Symetric multi-processing support" + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 + +2. Build kernel image for core1: + + a. $ make 85xx/p1_p2_rdb_defconfig + + b. $ make menuconfig + - Un-select "Processor support"-> + "Symetric multi-processing support" + - Select "Advanced setup" -> + "Prompt for advanced kernel configuration options" + - Select + "Set physical address where the kernel is loaded" + and set it to 0x20000000, assuming core1 will + start from 512MB. + - Select "Set custom page offset address" + - Select "Set custom kernel base address" + - Select "Set maximum low memory" + - "Exit" and save the selection. + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 + +3. Create dtb for core0: + + $ dtc -I dts -O dtb -f -b 0 + arch/powerpc/boot/dts/p2020rdb_camp_core0.dts > + /tftpboot/p2020rdb_camp_core0.dtb + +4. Create dtb for core1: + + $ dtc -I dts -O dtb -f -b 1 + arch/powerpc/boot/dts/p2020rdb_camp_core1.dts > + /tftpboot/p2020rdb_camp_core1.dtb + +5. Bring up two cores separately: + + a. Power on the board, under u-boot prompt: + => setenv <serverip> + => setenv <ipaddr> + => setenv bootargs root=/dev/ram rw console=ttyS0,115200 + b. Bring up core1's kernel first: + => setenv bootm_low 0x20000000 + => setenv bootm_size 0x10000000 + => tftp 21000000 uImage.core1 + => tftp 22000000 ramdiskfile + => tftp 20c00000 p2020rdb_camp_core1.dtb + => interrupts off + => bootm start 21000000 22000000 20c00000 + => bootm loados + => bootm ramdisk + => bootm fdt + => fdt boardsetup + => fdt chosen $initrd_start $initrd_end + => bootm prep + => cpu 1 release $bootm_low - $fdtaddr - + c. Bring up core0's kernel(on the same u-boot console): + => setenv bootm_low 0 + => setenv bootm_size 0x20000000 + => tftp 1000000 uImage.core0 + => tftp 2000000 ramdiskfile + => tftp c00000 p2020rdb_camp_core0.dtb + => bootm 1000000 2000000 c00000 + +Please note only core0 will run u-boot, core1 starts kernel directly +after "cpu release" command is issued. diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README new file mode 100644 index 00000000000..44377317dd0 --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/README @@ -0,0 +1,46 @@ +Overview +-------- +P1_P2_RDB_PC represents a set of boards including + P1020MSBG-PC + P1020RDB-PC + P1020UTM-PC + P1021RDB-PC + P1024RDB + P1025RDB + P2020RDB-PC + +They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC +has 64-bit DDR. All others have 32-bit DDR. + +Key features on these boards include: + * DDR3 + * NOR flash + * NAND flash (on RDB's only) + * SPI flash (on RDB's only) + * SDHC/MMC card slot + * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) + * PCIE slot and mini-PCIE slots + +As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM +is used to store SPD data. In case of absent or corrupted SPD, falling back +to timing data embedded in the source code will be used. Raw timing data is +extracted from DDR chip datasheet. Different speeds of DDR are supported with +this approach. ODT option is forced to fit this set of boards, again because +they don't have regular DIMMs. + +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification +for writing timing. + +VSC firmware Address is defined by default in config file for eTSEC1. + +SD width is based off DIP switch. DIP switch is detected on the +board by reading i2c bus and setting the appropriate mux values. + +Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have +pins multiplexing. QE function needs to be disabled to access Nor Flash and +CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" +in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to +enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below + +'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. +'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README new file mode 100644 index 00000000000..292d0d39cf6 --- /dev/null +++ b/board/freescale/p2041rdb/README @@ -0,0 +1,123 @@ +Overview +========= +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2041RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2041RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 441 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 46a 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2041RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command: + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2041rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/board/freescale/p3060qds/README b/board/freescale/p3060qds/README new file mode 100644 index 00000000000..ec627980c11 --- /dev/null +++ b/board/freescale/p3060qds/README @@ -0,0 +1,110 @@ +Overview +========= +The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC. + +The P3060 Processor combines six e500mc Power Architecture processor +cores(1.2GHz) with high-performance datapath acceleration +architecture(DPAA), CoreNet fabric infrastructure, as well as network +and peripheral bus interfaces required for networking, telecom/datacom, +wireless infrastructure, and military/aerospace applications. + + +P3060QDS Board Specifications: +============================== +Memory subsystem: + * 2G Bytes UDIMM DDR3(64bit bus) with ECC on + * 128M Bytes NOR flash single-chip memory + * 16M Bytes SPI flash + * 8K Bytes AT24C64 I2C EEPROM for RCW + +Ethernet(Default SERDES 0x19): + * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45) + * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45) + * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1) + * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1) + * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2) + * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2) + * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1) + * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1) + +PCIe: + * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4 + * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3 + +RapidIO: + * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3) + * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4) + +USB: + * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface + * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface + +I2C: + * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD, + AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68) + * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon + ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D) + * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40) + * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56) + * I2C1_CH4: PCIe SLOT1 + * I2C1_CH5: PCIe SLOT2 + * I2C1_CH6: PCIe SLOT3 + * I2C1_CH7: PCIe SLOT4 + * I2C2: NULL + * I2C3: NULL + +UART: + * Supports two UARTs up to 115200 bps for console + + +Boot from NOR flash +=================== +1. Build image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu- + make P3060QDS_config + make + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash) + Note: 1 stands for 'on', 0 stands for 'off' + + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb + +Or use the following command: + {linux-2.6}/make p3060qds.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p3060qds.dtb + + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p3060rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/board/icecube/README b/board/icecube/README new file mode 100644 index 00000000000..5252bc97678 --- /dev/null +++ b/board/icecube/README @@ -0,0 +1,13 @@ +--------------------------------------------------------------------------- +Build target Flash address | BDI "go" command | Reset Vector +--------------------------------------------------------------------------- +Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 +Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 +Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 +icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100 +icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100 +icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 +icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100 +icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100 +icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100 +--------------------------------------------------------------------------- diff --git a/board/icecube/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power new file mode 100644 index 00000000000..5b04fbba72a --- /dev/null +++ b/board/icecube/README.Lite5200B_low_power @@ -0,0 +1,22 @@ +Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM) +---------------------------------------------------------- + +Low-power mode as described in Lite5200B User's Manual, means that +with support of MC68HLC908QT1 microcontroller (refered to as QT), +everything but the SDRAM can be powered down. This brings +maximum power saving, while one can still restore previous state +quickly. + +Quick overview where U-Boot comes into the picture: +- OS saves device states +- OS saves wakeup handler address to physical 0x0, puts SDRAM into + self-refresh and signals to QT, it should power down the board +- / board is sleeping here / +- someone presses SW4 (connected to QT) +- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up, + so get SDRAM out of self-refresh and transfer control to OS + wakeup handler +- OS restores device states + +This was tested on Linux with USB and Ethernet in use. Adding +support for other devices is an OS issue. diff --git a/board/incaip/README b/board/incaip/README new file mode 100644 index 00000000000..132915292ea --- /dev/null +++ b/board/incaip/README @@ -0,0 +1,57 @@ + +Flash programming on the INCA-IP board is complicated because of the +EBU swapping unit. A BDI2000 can be used for flash programming only +if the EBU swapping unit is enabled; otherwise it will not detect the +flash memory. But the EBU swapping unit is disadbled after reset, so +if you program some code to flash with the swapping unit on, it will +not be runnable with the swapping unit off. + +The consequence is that you have to write a pre-swapped image to +flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is +provided in the "tools/" directory. Use it as follows: + + bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp + +Note that the current BDI config file _disables_ the EBU swapping +unit for the flash bank 0. To enable it, (this is required for the +BDI flash commands to work) uncomment the following line in the +config file: + + ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled + +and comment out + + WM32 0xb8000260 0x004161ff ; Swapping unit disabled + +Alternatively, you can use "mm 0xb8000260 <value>" commands to +enable/disable the swapping unit manually. + +Just for reference, here is the complete sequence of actions we took +to install a U-Boot image into flash. + + 1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp + + 2. From BDI: + + mm 0xb8000260 0x404161ff + erase 0xb0000000 + erase 0xb0010000 + prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin + mm 0xb8000260 0x004161ff + go 0xb0000000 + + +Ethernet autonegotiation needs some time to complete. Instead of +delaying the boot process in all cases, we just start the +autonegotiation process when U-Boot comes up and that is all. Most +likely, it will complete by the time the network transfer is +attempted for the first time. In the worst case, if a transfer is +attempted before the autonegotiation is complete, just a single +packet would be lost resulting in a single timeout error, and then +the transfer would proceed normally. So the time that we would have +lost unconditionally waiting for the autonegotiation to complete, we +have to wait only if the file transfer is started immediately after +reset. We've verified that this works for all the clock +configurations. + +(C) 2003 Wolfgang Denk diff --git a/board/iphase4539/README b/board/iphase4539/README new file mode 100644 index 00000000000..c5146d9b186 --- /dev/null +++ b/board/iphase4539/README @@ -0,0 +1,358 @@ + +This file contains basic information on the port of U-Boot to IPHASE4539 +(Interphase 4539 T1/E1/J1 PMC Communications Controller). +All the changes fit in the common U-Boot infrastructure, providing a new +IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539, +type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h" +file if necessary, then type "make". + + +Common file modifications: +-------------------------- + +The following common files have been modified by this project: +(starting from the ppcboot-1.1.5/ directory) + +MAKEALL - IPHASE4539 entry added +Makefile - IPHASE4539_config entry added + + +New files: +---------- + +The following new files have been added by this project: +(starting from the ppcboot-1.1.5/ directory) + +board/iphase4539/ - board-specific directory +board/iphase4539/Makefile - board-specific makefile +board/iphase4539/config.mk - config file +board/iphase4539/flash.c - flash driver (for AM29LV033C) +board/iphase4539/ppcboot.lds - linker script +board/iphase4539/iphase4539.c - ioport and memory initialization +include/config_IPHASE4539.h - main configuration file + + +New configuration options: +-------------------------- + +CONFIG_IPHASE4539 + + Main board-specific option (should be defined for IPHASE4539). + + +Acceptance criteria tests: +-------------------------- + +The following tests have been conducted to validate the port of U-Boot +to IPHASE4539: + +1. Operation on serial console: + +With SMC1 defined as console in the main configuration file, the U-Boot +output appeared on the serial terminal connected to the 2.5mm stereo jack +connector as follows: + +------------------------------------------------------------------------------ +=> help +base - print or set address offset +bdinfo - print Board Info structure +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +cmp - memory compare +coninfo - print console devices and informations +cp - memory copy +crc32 - checksum calculation +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +iminfo - print header information for application image +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loop - infinite loop on address range +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +source - run script from memory +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +version - print monitor version +? - alias for 'help' +=> +------------------------------------------------------------------------------ + + +2. Flash driver operation + +The following sequence was performed to test the "flinfo" command: + +------------------------------------------------------------------------------ +=> flinfo + +Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors) + Size: 4 MB in 64 Sectors + Sector Start Addresses: + FF800000 (RO) FF810000 (RO) FF820000 FF830000 FF840000 + FF850000 FF860000 FF870000 FF880000 FF890000 + FF8A0000 FF8B0000 FF8C0000 FF8D0000 FF8E0000 + FF8F0000 FF900000 FF910000 FF920000 FF930000 + FF940000 FF950000 FF960000 FF970000 FF980000 + FF990000 FF9A0000 FF9B0000 FF9C0000 FF9D0000 + FF9E0000 FF9F0000 FFA00000 FFA10000 FFA20000 + FFA30000 FFA40000 FFA50000 FFA60000 FFA70000 + FFA80000 FFA90000 FFAA0000 FFAB0000 FFAC0000 + FFAD0000 FFAE0000 FFAF0000 FFB00000 (RO) FFB10000 (RO) + FFB20000 (RO) FFB30000 (RO) FFB40000 FFB50000 FFB60000 + FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000 + FFBC0000 FFBD0000 FFBE0000 FFBF0000 +------------------------------------------------------------------------------ + +Note: the Hardware Configuration Word (HWC) of the 8260 is on the +first sector of the flash and should not be touched. The U-Boot +environment variables are stored on second sector and U-Boot +starts at the address 0xFFB00000. + + +The following sequence was performed to test the erase command: + +------------------------------------------------------------------------------ +=> cp 0 ff880000 10 +Copy to Flash... done +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> erase ff880000 ff88ffff +Erase Flash from 0xff880000 to 0xff88ffff +.. done +Erased 1 sectors +=> md ff880000 +ff880000: ffffffff ffffffff ffffffff ffffffff ................ +ff880010: ffffffff ffffffff ffffffff ffffffff ................ +ff880020: ffffffff ffffffff ffffffff ffffffff ................ +ff880030: ffffffff ffffffff ffffffff ffffffff ................ +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 ff880000 10 +Copy to Flash... done +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> erase 1:8 +Erase Flash Sectors 8-8 in Bank # 1 +.. done +=> md ff880000 20 +ff880000: ffffffff ffffffff ffffffff ffffffff ................ +ff880010: ffffffff ffffffff ffffffff ffffffff ................ +ff880020: ffffffff ffffffff ffffffff ffffffff ................ +ff880030: ffffffff ffffffff ffffffff ffffffff ................ +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 ff880000 10 +Copy to Flash... done +=> cp 0 ff890000 10 +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> md ff890000 +ff890000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff890020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff890030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff890040: ffffffff ffffffff ffffffff ffffffff ................ +ff890050: ffffffff ffffffff ffffffff ffffffff ................ +ff890060: ffffffff ffffffff ffffffff ffffffff ................ +ff890070: ffffffff ffffffff ffffffff ffffffff ................ +=> erase 1:8-9 +Erase Flash Sectors 8-9 in Bank # 1 +.... done +=> md ff880000 20 +ff880000: ffffffff ffffffff ffffffff ffffffff ................ +ff880010: ffffffff ffffffff ffffffff ffffffff ................ +ff880020: ffffffff ffffffff ffffffff ffffffff ................ +ff880030: ffffffff ffffffff ffffffff ffffffff ................ +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> md ff890000 +ff890000: ffffffff ffffffff ffffffff ffffffff ................ +ff890010: ffffffff ffffffff ffffffff ffffffff ................ +ff890020: ffffffff ffffffff ffffffff ffffffff ................ +ff890030: ffffffff ffffffff ffffffff ffffffff ................ +ff890040: ffffffff ffffffff ffffffff ffffffff ................ +ff890050: ffffffff ffffffff ffffffff ffffffff ................ +ff890060: ffffffff ffffffff ffffffff ffffffff ................ +ff890070: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the Flash programming commands: + +------------------------------------------------------------------------------ +=> erase ff880000 ff88ffff +Erase Flash from 0xff880000 to 0xff88ffff +.. done +Erased 1 sectors +=> cp 0 ff880000 10 +Copy to Flash... done +=> md 0 20 +00000000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +00000020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +00000030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +00000040: 3c83c000 2c040000 40823378 7c0000a6 <...,...@.3x|... +00000050: 60000030 7c1b03a6 3c00c000 600035ec `..0|...<...`.5. +00000060: 7c1a03a6 4c000064 00000000 00000000 |...L..d........ +00000070: 00000000 00000000 00000000 00000000 ................ +=> md ff880000 20 +ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x +ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x +ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. +ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x +ff880040: ffffffff ffffffff ffffffff ffffffff ................ +ff880050: ffffffff ffffffff ffffffff ffffffff ................ +ff880060: ffffffff ffffffff ffffffff ffffffff ................ +ff880070: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test storage of the environment +variables in Flash: + +------------------------------------------------------------------------------ +=> setenv foo bar +=> saveenv +Un-Protected 1 sectors +Erasing Flash... +.. done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=> reset +... +=> printenv +... +foo=bar +... +Environment size: 339/65532 bytes +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test image download and run over +Ethernet interface (both interfaces were tested): + +------------------------------------------------------------------------------ +=> tftpboot 40000 hello_world.bin +ARP broadcast 1 +TFTP from server 10.0.0.1; our IP address is 10.0.0.8 +Filename 'hello_world.bin'. +Load address: 0x40000 +Loading: ############# +done +Bytes transferred = 65932 (1018c hex) +=> go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "<NULL>" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> +------------------------------------------------------------------------------ + + +3. Known Problems + +None for the moment. + + +---------------------------------------------------------------------------- +U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller +---------------------------------------------------------------------------- + +U-Boot: + + Configure and make U-Boot: + + $ cd <path>/u-boot + $ make IPHASE4539_config + $ make dep + $ make + $ cp -p u-boot.bin /tftpboot + + Load u-boot.bin into the Flash memory at 0xffb00000. + + +Linux: + + Configure and make Linux: + + $ cd <patch>/linux-2.4 + $ make IPHASE4539_config + $ make oldconfig + $ make dep + $ make uImage + $ cp -p arch/powerpc/mbxboot/uImage /tftpboot + + Load uImage via tftp and boot it. + + +Flash organisation: + + The following preliminary layout of the Flash memory + is defined: + + 0xff800000 ( 0 - 64 kB): Hardware Configuration Word. + 0xff810000 ( 64 kB - 128 kB): U-Boot Environment. + 0xff820000 ( 128 kB - 3 MB): RAMdisk. + 0xffb00000 ( 3 MB - 3328 kB): U-Boot. + 0xffb40000 (3328 KB - 4 MB): Linux Kernel. + + +For further information concerning U-Boot and Linux please consult +the "DENX U-Boot and Linux Guide". + + +(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg@denx.de +=================================================================== diff --git a/board/keymile/km83xx/README.kmeter1 b/board/keymile/km83xx/README.kmeter1 new file mode 100644 index 00000000000..7f4fc999f8f --- /dev/null +++ b/board/keymile/km83xx/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-boot Image using U-boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/board/korat/README b/board/korat/README new file mode 100644 index 00000000000..e059f788c46 --- /dev/null +++ b/board/korat/README @@ -0,0 +1,64 @@ +The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to +chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to +addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains +from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash +Bank #1 (with the starting address depending on the flash size detected at +runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0 +cannot be modified in the field. This also prevents FLASH0 from executing +commands to return chip information, so its configuration is hard-coded in +U-Boot. + +There are two versions of U-Boot for Korat: "permanent" and "upgradable". The +permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses +0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is +located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000 +for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are +used for the U-Boot environmental parameters, and addresses 0xF7FC0000 - +0xF7FDFFFF are used for the redundant copy of the parameters. These locations +are used by both versions of U-Boot. + +On booting, the permanent U-Boot in FLASH0 begins executing. After performing +minimal setup, it monitors the state of the board's Reset switch (GPIO47). If +the switch is sensed as open before a timeout period, then U-Boot branches to +address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the +beginning. If the switch remains closed thoughout the timeout period, the +permanent U-Boot activates the on-board buzzer until the switch is sensed as +opened. It then continues to execute without branching to FLASH1. The effect +of this is that normally the Korat board boots its upgradable U-Boot, but, if +this has been corrupted, the user can boot the permanent U-Boot, which can then +be used to erase and reload FLASH1 as needed. + +Note that it is not necessary for the permanent U-Boot to have all the latest +features, but only that it have sufficient functionality (working "tftp", +"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no +assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is +sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC. + +The build sequence: + + make korat_perm_config + make all + +builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining +preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build: + + make korat_config + make all + +creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and +leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined. + +2008-02-22, Larry Johnson <lrj@acm.org> + + +The CompactFlash(R) controller on the Korat board provides a hi-speed USB +interface. This may be connected to either a dedicated port on the on-board +USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot +environment variable "korat_usbcf" can be used to specify which of these two +USB host ports is used for CompactFlash. The valid setting for the variable are +the strings "pci" and "ppc". If the variable defined and set to "ppc", then the +PowerPC USB port is used. In all other cases the on-board USB controller is +used, but if "korat_usbcf" is defined but is set to a string other than the two +valid options, a warning is also issued. + +2009-01-28, Larry Johnson <lrj@acm.org> diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README new file mode 100644 index 00000000000..1994b65be11 --- /dev/null +++ b/board/matrix_vision/mergerbox/README @@ -0,0 +1,59 @@ +Matrix Vision MergerBox +----------------------- + +1. Board Description + + The MergerBox is a 120x160mm single board computing platform + for 3D Full-HD digital video processing. + + Power Supply is 10-32VDC. + +2 System Components + +2.1 CPU + Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. + 256 MByte DDR-II memory @ 333MHz data rate. + 64 MByte Nor Flash on local bus. + 1 GByte Nand Flash on FCM. + 1 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F with 4-Port hub. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. + 2 PCIe x1 busses on local mPCIe and cutom expansion connector. + 2 SATA host ports. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 Graphics + SM107 emebedded video controller driving a 5" 800x480 TFT panel. + Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. + +2.3 FPGA + Altera Cyclone-IV EP4C115 with several PCI DMA engines. + Connects to 7x Gennum 3G-SDI transceivers as video interconnect + as well as a HDMI v1.4 compliant output for 3D monitoring. + Utilizes two more DDR-II controllers providing 256MB memory. + +2.4 I2C + Bus1: + AD7418 @ 0x50 for voltage/temp. monitoring. + SX8650 @ 0x90 touch controller for HMI. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + Bus2: + mPCIe SMBus + SiI9022A @ 0x72/0xC0 HDMI transmitter. + TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. + LMH1983 @ 0xCA video PLL. + DS1338C @ 0xD0 real-time clock with embedded crystal. + 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. + +3 Flash layout. + + reset vector is 0x00000100, i.e. low boot. + + 00000000 u-boot binary. + 00100000 FPGA raw bit file. + 00300000 FIT image holding kernel, dtb and rescue squashfs. + 03d00000 u-boot environment. + 03e00000 splash image + + mtd partitions are propagated to linux kernel via device tree blob. diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p new file mode 100644 index 00000000000..a691137550e --- /dev/null +++ b/board/matrix_vision/mvbc_p/README.mvbc_p @@ -0,0 +1,73 @@ +Matrix Vision mvBlueCOUGAR-P (mvBC-P) +------------------------------------- + +1. Board Description + + The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera + with main focus on GigEVision protocol in combination with local image + preprocessing. + + Power Supply is either VDC 48V or Pover over Ethernet (PoE). + +2 System Components + +2.1 CPU + Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. + 64MB SDRAM @ 133MHz. + 8 MByte Nor Flash on local bus. + 1 serial ports. Console running on ttyS0 @ 115200 8N1. + +2.2 PCI + PCI clock fixed at 66MHz. Arbitration inside FPGA. + Intel GD82541ER network MAC/PHY and FPGA connected. + +2.3 FPGA + Altera Cyclone-II EP2C8 with PCI DMA engine. + Connects to Matrix Vision specific CCD/CMOS sensor interface. + Utilizes 64MB Nand Flash. + +2.3.1 I/O @ FPGA + 2 Outputs : photo coupler + 2 Inputs : photo coupler + +2.4 I2C + LM75 @ 0x90 for temperature monitoring. + EEPROM @ 0xA0 for vendor specifics. + image sensor interface (slave addresses depend on sensor) + +3 Flash layout. + + reset vector is 0x00000100, i.e. "LOWBOOT". + + FF800000 u-boot + FF840000 u-boot script image + FF850000 redundant u-boot script image + FF860000 FPGA raw bit file + FF8A0000 tbd. + FF900000 root FS + FFC00000 kernel + FFFC0000 device tree blob + FFFD0000 redundant device tree blob + FFFE0000 environment + FFFF0000 redundant environment + + mtd partitions are propagated to linux kernel via device tree blob. + +4 Booting + + On startup the bootscript @ FF840000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + 3. device tree blob - name is stored in "dtb_name" + Fallback files are the flash versions. diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 new file mode 100644 index 00000000000..a0686f7fa57 --- /dev/null +++ b/board/matrix_vision/mvblm7/README.mvblm7 @@ -0,0 +1,84 @@ +Matrix Vision mvBlueLYNX-M7 (mvBL-M7) +------------------------------------- + +1. Board Description + + The mvBL-M7 is a 120x120mm single board computing platform + with strong focus on stereo image processing applications. + + Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) + on any port (requires add-on board). + +2 System Components + +2.1 CPU + Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. + 512MByte DDR-II memory @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 SD-Card slot connected to SPI. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 PCI + A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. + +2.3 FPGA + Altera Cyclone-II EP2C20/35 with PCI DMA engines. + Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. + Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. + +2.3.1 I/O @ FPGA + 2x8 Outputs : Infineon High-Side Switches to Main Supply. + 2x8 Inputs : Programmable input threshold + trigger capabilities + 2 dedicated flash interfaces for illuminator boards. + Cross trigger for chaining several boards. + +2.4 I2C + Bus1: + MAX5381 DAC @ 0x60 for 1st digital input threshold. + LM75 @ 0x90 for temperature monitoring. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + 1st image sensor interface (slave addresses depend on sensor) + Bus2: + MAX5381 DAC @ 0x60 for 2nd digital input threshold. + 2nd image sensor interface (slave addresses depend on sensor) + +3 Flash layout. + + reset vector is 0xFFF00100, i.e. "HIGHBOOT". + + FF800000 environment + FF802000 redundant environment + FF804000 u-boot script image + FF806000 redundant u-boot script image + FF808000 device tree blob + FF80A000 redundant device tree blob + FF80C000 tbd. + FF80E000 tbd. + FF810000 kernel + FFC00000 root FS + FFF00000 u-boot + FFF80000 FPGA raw bit file + + mtd partitions are propagated to linux kernel via device tree blob. + +4 Booting + + On startup the bootscript @ FF804000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + 3. device tree blob - name is stored in "dtb_name" + Fallback files are the flash versions. diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr new file mode 100644 index 00000000000..8e34cb78385 --- /dev/null +++ b/board/matrix_vision/mvsmr/README.mvsmr @@ -0,0 +1,55 @@ +Matrix Vision mvSMR +------------------- + +1. Board Description + + The mvSMR is a 75x130mm single image processing board used + in automation. Power Supply is 24VDC. + +2 System Components + +2.1 CPU + Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. + 64MB DDR-I @ 133MHz. + 8 MByte Nor Flash on local bus. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + +2.2 PCI + PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. + +2.3 FPGA + Xilinx Spartan-3 XC3S200 with PCI DMA engine. + Connects to Matrix Vision specific CCD/CMOS sensor interface. + +2.4 I2C + EEPROM @ 0xA0 for vendor specifics. + image sensor interface (slave addresses depend on sensor) + +3 Flash layout. + + reset vector is 0x00000100, i.e. "LOWBOOT". + + FF800000 u-boot + FF806000 u-boot script image + FF808000 u-boot environment + FF840000 FPGA raw bit file + FF880000 root FS + FFF00000 kernel + +4 Booting + + On startup the bootscript @ FF806000 is executed. This script can be + exchanged easily. Default boot mode is "boot from flash", i.e. system + works stand-alone. + + This behaviour depends on some environment variables : + + "netboot" : yes ->try dhcp/bootp and boot from network. + A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for + DHCP server configuration, e.g. to provide different images to + different devices. + + During netboot the system tries to get 3 image files: + 1. Kernel - name + data is given during BOOTP. + 2. Initrd - name is stored in "initrd_name" + Fallback files are the flash versions. diff --git a/board/mbx8xx/README b/board/mbx8xx/README new file mode 100644 index 00000000000..c889fe97911 --- /dev/null +++ b/board/mbx8xx/README @@ -0,0 +1,68 @@ +IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board + config file!!! + + +WARNING: Wrong settings of this parameter have the potential to +damage hardware by running the MBX's CPU at frequencies that exceed +it's rating and/or overdriving the it's SPLL! + + +Ramblings: +1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s. +2) Of these 12 variants, only 2 were entry level boards. +3) I believe that the 2 entry level boards were the only ones that + used OSCM clocking. I can't be completely certain of this at this + point. +4) Motorola never offered an MBX that ran faster than 50Mhz. +5) The 10, non-entry level boards, ran at 40Mhz. +6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860. +7) Motorola no longer sells MBXs. + +Based on this information, I can surmise that the default power-on +reset clocking was one of the following three options. + +Multiplier SPLL Options +------------------------------------ +513 OSCM is SPLL input +5 OSCM is SPLL input +1 EXTCLK is SPLL input + +The forth option: + +5 EXTCLK is SPLL input + +is not possible on MBXs. This is because the minimum EXTCLK input +frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran +above 50 Mhz. + +The board I have borrowed definitely uses a multiplier of 1 for +EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it. + +One of the two default OSCM modes are most likely what was used on +the entry level boards to cheapen them by eliminating the external +crystal oscillator. + +To add insult to injury, the stupid 860 PLPRCR register retains it's +multiplication factor through hard resets. You can't clear it out +because it is battery backed and once it is set wrong, it stays +wrong. The only way to reset it, so that it takes on it's default +multiplier is to disconnect all power including external, batteries, +as well discharging caps on the board. This precludes the fact that +your 860 may be quite DEAD by this time! + +If you don't setup the multiplication factor for boards that use the +OSCM input, they won't run correctly, but at least they won't be +dead. + +Addtionally, there is no good way to determine the clock input source +from CPU register data. The only way to deal with this is either hard +code it, determine the correct value with some rather NASTY timing +loops, or try to grok it from external data sources. Motorola +firmware opts for the NASTY timing loops, but needs to configure the +serial ports to do so. + + +You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your +MBX8xx board is using the OSCM clocking mode. + +You better know what you are doing here. diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README new file mode 100644 index 00000000000..012db1c5f74 --- /dev/null +++ b/board/mpl/pip405/README @@ -0,0 +1,375 @@ +U-Boot Changes due to PIP405 Port: +=================================== + +Changed files: +============== +- MAKEALL added PIP405 +- makefile added PIP405 +- common/Makefile added Floppy disk and SCSI support +- common/board.c added PIP405, SCSI support, get_PCI_freq() +- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE +- common/cmd_i2c.c added "defined(CONFIG_PIP405)" +- common/cmd_ide.c changed div. functions to work with block device + description + added ATAPI support +- common/command.c added SCSI and Floppy support +- common/console.c replaced // with /* comments + added console settings from environment +- common/devices.c added ISA keyboard init +- common/main.c corrected the read of bootdelay +- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405 +- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support + added page write +- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq +- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING +- disk/Makefile added part_iso for CD support +- disk/part.c changed to work with block device description + added ISO CD support + added dev_print (was ide_print in cmd_ide.c) +- disk/part_dos.c changed to work with block device description +- disk/part_mac.c changed to work with block device description +- include/ata.h added ATAPI commands +- include/cmd_bsp.h added PIP405 commands definitions +- include/cmd_condefs.h added Floppy and SCSI support +- include/cmd_disk.h changed to work with block device description +- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 +- include/i2c.h added "defined(CONFIG_PIP405)" +- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE +- include/u-boot.h moved partitions functions definitions to part.h + added "defined(CONFIG_PIP405)" + added get_PCI_freq() definition +- rtc/Makefile added MC146818 RTC support +- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE + +Added files: +============ +- board/pip405 directory for PIP405 +- board/pip405/cmd_pip405.c board specific commands +- board/pip405/config.mk config make +- board/pip405/flash.c flash support +- board/pip405/init.s start-up +- board/pip405/kbd.c keyboard support +- board/pip405/kbd.h keyboard support +- board/pip405/Makefile Makefile +- board/pip405/pci_piix4.h southbridge definitions +- board/pip405/pci_pip405.c PCI support for PIP405 +- board/pip405/pci_pip405.h PCI support for PIP405 +- board/pip405/pip405.c PIP405 board init +- board/pip405/pip405.h PIP405 board init +- board/pip405/pip405_isa.c ISA support +- board/pip405/pip405_isa.h ISA support +- board/pip405/u-boot.lds Linker description +- board/pip405/u-boot.lds.debugLinker description debug +- board/pip405/sym53c8xx.c SYM53C810A support +- board/pip405/sym53c8xx_defs.h SYM53C810A definitions +- board/pip405/vga_table.h definitions of tables for VGA +- board/pip405/video.c CT69000 support +- board/pip405/video.h CT69000 support +- common/cmd_fdc.c Floppy disk support +- common/cmd_scsi.c SCSI support +- disk/part_iso.c ISO CD ROM support +- disk/part_iso.h ISO CD ROM support +- include/cmd_fdc.h command forFloppy disk support +- include/cmd_scsi.h command for SCSI support +- include/part.h partitions functions definitions + (was part of u-boot.h) +- include/scsi.h SCSI support +- rtc/mc146818.c MC146818 RTC support + + +New Config Switches: +==================== +For detailed description, refer to the corresponding paragraph in the +section "Changes". + +New Commands: +------------- +CONFIG_CMD_SCSI SCSI Support +CONFIG_CMF_FDC Floppy disk support + +IDE additions: +-------------- +CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin, + the routine ide_set_reset(int idereset) is used. +ATAPI support (experimental) +---------------------------- +CONFIG_ATAPI enables ATAPI Support + +SCSI support (experimental) only SYM53C8xx supported +---------------------------------------------------- +CONFIG_SCSI_SYM53C8XX type of SCSI controller +CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs +CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6) +CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN + maximum of Target devices (multiple LUN support + for boot) + +ISO (CD-Boot) partition support (Experimental) +---------------------------------------------- +CONFIG_ISO_PARTITION CD-boot support + +RTC +---- +CONFIG_RTC_MC146818 MC146818 RTC support + +Keyboard: +--------- +CONFIG_ISA_KEYBOARD Standard (PC-Style) Keyboard support + +Video: +------ +CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip + CONFIG_VIDEO must be defined also + +External peripheral base address: +--------------------------------- +CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts + _must_ be defined for ISA-bus parts + +Identify: +--------- +CONFIG_IDENT_STRING added to the U_BOOT_VERSION String + +Environment / Console: +---------------------- + +CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from + the values stored in the evironment. + +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the + values stored in the environment or the standard + serial in/out put should be assigned to the console. + +CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching + are stored in the environment. + +PIP405 specific: +---------------- +CONFIG_PORT_ADDR address used to read boot configuration +MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked +SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect +SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module. + + +Changes: +======== + +Added Devices: +============== + +Floppy support: +--------------- +Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS ++ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk +with a image header (see: mkimage). No interrupts and no DMA are used for this. +Added files: +- common/cmd_fdc.c +- include/cmd_fdc.h + +SCSI support: +------------- +Support for Symbios SYM53C810A chip. Implemented as follows: +- without disconnect +- only asynchrounous +- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to + save RAM) +- multiple SCSI ID support +- no write support +- analyses the MAC, DOS and ISO pratition similar to the IDE support +- allows booting from SCSI devices similar to the IDE support. +The device numbers are not assigned like they are within the IDE support. The first +device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all +LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the +device descriptors are not yet dynamically allocated. 56 boot devices are overkill +anyway. Please refer to the section "Todo" chapter "block device support enhancement". +The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus. +Added files: +- common/cmd_scsi.c +- common/board.c +- include/cmd_scsi.h +- include/scsi.h +- board/pip405/sym53c8xx.c +- board/pip405/sym53c8xx_defs.h + +ATAPI support (IDE changes): +---------------------------- +Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c. +To support a hardreset, when the IDE reset pin is not connected to the +CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When +this switch is enabled the routine void ide_set_reset(int idereset) must be +within the board specific files. +Only read from ATAPI devices are supported. +Found out that the function trim_trail cuts off the last character if the whole +string is filled. Added function cpy_ident instead, which trims also leading +spaces and copies the string in the buffer. +Changed files: +- common/cmd_ide.c +- include/ata.h + +ISO partition support: +---------------------- +Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain +the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0. +The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI +("diskboot") and SCSI ("scsiboot") devices. +Added files: +- disk/iso_part.c +- disk/iso_part.h + +Block device changes: +--------------------- +To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter +block_dev_desc will be used when accessing the functions in these files. The block +device descriptor (block_dev_desc) contains a pointer to the read routine of the +device, which will be used to read blocks from the device. +Renamed function ide_print to dev_print and moved it to the file disk/part.c to use +it for IDE ATAPI and SCSI devices. +Please refer to the section "Todo" chapter "block device support enhancement". +Added files: +- include/part.h +changed files: +- disk/dos_part.c +- disk/dos_part.h +- disk/mac_part.c +- disk/mac_part.h +- disk/part.c +- common/cmd_ide.c +- include/u-boot.h + + +MC146818 RTC support: +--------------------- +Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO +base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS. +Added files: +- rtc/mc146818.c + +Standard ISA bus Keyboard support: +---------------------------------- +Added support for the standard PC kyeboard controller. For the PIP405 the superIO +controller must be set up previously. The keyboard uses the standard ISA IRQ, so +the ISA PIC must also be set up. +Added files: +- board/pip405/kbd.c +- board/pip405/kbd.h +- board/pip405/pip405_isa.c +- board/pip405/pip405_isa.h + +Chips and Technologie 69000 VGA controller support: +--------------------------------------------------- +Added support for the CT69000 VGA controller. +Added files: +- board/pip405/video.c +- board/pip405/video.h +- board/pip405/vga_table.h + + +Changed Items: +============== + +Identify: +--------- +Added the config variable CONFIG_IDENT_STRING which will be added to the +"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate +and custom versions. +Changed files: +- arch/powerpc/cpu/ppc4xx/start.s + +Firmware Image: +--------------- +Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the +U-Boot update with prior CRC check. +Changed files: +- include/image.h +- tools/mkimage.c +- common/cmd_bootm.c + +Correct PCI Frequency for PPC405: +--------------------------------- +Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU. +The PCI Frequency will now be set correct in the board description in common/board.c. +(was set to the busfreq before). +Changed files: +- arch/powerpc/cpu/ppc4xx/speed.c +- common/board.c + +I2C Stuff: +---------- +Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c. +Added 16bit read/write support for I2C (PPC405), and page write to +I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE. +Changed files: +- arch/powerpc/cpu/ppc4xx/i2c.c +- common/cmd_i2c.c + +Environment / Console: +---------------------- +Although in README.console described, the U-Boot has not assinged the values +found in the environment to the console. Corrected this behavior, but only if +CONFIG_SYS_CONSOLE_IS_IN_ENV is defined. +If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the +values stored in the environment or the standard serial in/output should be +assigned to the console. This is useful if the environment values are not correct. +If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at +start-up time will be written to the environment. This means that if the +environment values are overwritten by the overwrite_console() routine, they will be +stored in the environment. +Changed files: +- common/console.c + +Correct bootdelay intepretation: +-------------------------------- +Changed bootdelay read from the environment from simple_strtoul (unsigned) to +simple_strtol (signed), to be able to get a bootdelay of -1. +Changed files: +- common/main.c + +Todo: +===== + +Block device support enhancement: +--------------------------------- +Consider to unify the block device handling. Instead of using diskboot for IDE, +scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only +one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1", +"fd0" ???) to boot from. The other ide commands can be handled in the same way +("dev hda read.." instead of "ide read.." or "dev sda read.." instead of +"scsi read..."). Todo this, a common way of assign a block device to its name +(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0, +hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for +floppy ???) must be defined. +Maybe there are better ideas to do this. + +Console assingment: +------------------- +Consider to initialize and assign the console stdin, stdout and stderr as soon as +possible to see the boot messages also on an other console than serial. + + +Todo for PIP405: +================ + +LCD support for VGA: +-------------------- +Add LCD support for the CT69000 + +Default environment: +-------------------- +Consider to write a default environment to the OTP part of the EEPROM and use it +if the normal environment is not valid. Useful for serial# and ethaddr values. + +Watchdog: +--------- +Implement Watchdog. + +Files clean-up: +--------------- +Following files needs to be cleaned up: +- cmd_pip405.c +- flash.c +- pci_pip405.c +- pip405.c +- pip405_isa.c +Consider to split up the files in their functions. diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README new file mode 100644 index 00000000000..05faab68c83 --- /dev/null +++ b/board/phytec/pcm030/README @@ -0,0 +1,42 @@ +To build RAMBOOT, replace this section the main Makefile + +pcm030_config \ +pcm030_RAMBOOT_config \ +pcm030_LOWBOOT_config: unconfig + @ >include/config.h + @[ -z "$(findstring LOWBOOT_,$@)" ] || \ + { echo "CONFIG_SYS_TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ + echo "... with LOWBOOT configuration" ; \ + } + @[ -z "$(findstring RAMBOOT_,$@)" ] || \ + { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\ + config.tmp ; \ + echo "... with RAMBOOT configuration" ; \ + echo "... remember to make sure that MBAR is already \ + switched to 0xF0000000 !!!" ; \ + } + @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec + @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1" + +Alternative SDRAM settings: + +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x715f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 + +/* Settings for XLB = 99 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714b0f00 +#define SDRAM_CONFIG1 0x63611730 +#define SDRAM_CONFIG2 0x47670000 + +The board ships default with the environment in EEPROM +Moving the environment to flash can be more reliable + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 diff --git a/board/qemu-mips/README b/board/qemu-mips/README index 565241b5878..9fd97e1249a 100644 --- a/board/qemu-mips/README +++ b/board/qemu-mips/README @@ -13,3 +13,170 @@ Derived from au1x00 with a lot of things cut out. Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with recent qemu versions. When using emulated flash, launch with -pflash <filename> and erase mips_bios.bin. + + + +Notes for the Qemu MIPS port +---------------------------- + +I) Example usage: + +# ln -s u-boot.bin mips_bios.bin +start it: +qemu-system-mips -L . /dev/null -nographic + +or + +if you use a qemu version after commit 4224 + +create image: +# dd of=flash bs=1k count=4k if=/dev/zero +# dd of=flash bs=1k conv=notrunc if=u-boot.bin +start it: +# qemu-system-mips -M mips -pflash flash -monitor null -nographic + +2) Download kernel + initrd + +On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/ +you can downland + +#config to build the kernel +qemu_mips_defconfig +#patch to fix mips interrupt init on 2.6.24.y kernel +qemu_mips_kernel.patch +initrd.gz +vmlinux +vmlinux.bin +System.map + +4) Generate uImage + +# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage + +5) Copy uImage to Flash +# dd if=uImage bs=1k conv=notrunc seek=224 of=flash + +6) Generate Ide Disk + +# dd of=ide bs=1k cout=100k if=/dev/zero + +# sfdisk -C 261 -d ide +# partition table of ide +unit: sectors + + ide1 : start= 63, size= 32067, Id=83 + ide2 : start= 32130, size= 32130, Id=83 + ide3 : start= 64260, size= 4128705, Id=83 + ide4 : start= 0, size= 0, Id= 0 + +7) Copy to ide + +# dd if=uImage bs=512 conv=notrunc seek=63 of=ide + +8) Generate ext2 on part 2 on Copy uImage and initrd.gz + +# Attached as loop device ide offset = 32130 * 512 +# losetup -o 16450560 -f ide +# Format as ext2 ( arg2 : nb blocks) +# mke2fs /dev/loop0 16065 +# losetup -d /dev/loop0 +# Mount and copy uImage and initrd.gz to it +# mount -o loop,offset=16450560 -t ext2 ide /mnt +# mkdir /mnt/boot +# cp {initrd.gz,uImage} /mnt/boot/ +# Umount it +# umount /mnt + +9) Set Environment + +setenv rd_start 0x80800000 +setenv rd_size 2663940 +setenv kernel BFC38000 +setenv oad_addr 80500000 +setenv load_addr2 80F00000 +setenv kernel_flash BFC38000 +setenv load_addr_hello 80200000 +setenv bootargs 'root=/dev/ram0 init=/bin/sh' +setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz' +setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz' +setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2' +setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage' +setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage' +setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}' +setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}' +setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin' +setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}' +setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' +setenv bootcmd 'run boot_tftp_flash' + +10) Now you can boot from flash, ide, ide+ext2 and tfp + +# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + +II) How to debug U-Boot + +In order to debug U-Boot you need to start qemu with gdb server support (-s) +and waiting the connection to start the CPU (-S) + +# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + +in an other console you start gdb + +1) Debugging of U-Boot Before Relocation + +Before relocation, the addresses in the ELF file can be used without any problems +by connecting to the gdb server localhost:1234 + +# mipsel-unknown-linux-gnu-gdb u-boot +GNU gdb 6.6 +Copyright (C) 2006 Free Software Foundation, Inc. +GDB is free software, covered by the GNU General Public License, and you are +welcome to change it and/or distribute copies of it under certain conditions. +Type "show copying" to see the conditions. +There is absolutely no warranty for GDB. Type "show warranty" for details. +This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"... +(gdb) target remote localhost:1234 +Remote debugging using localhost:1234 +_start () at start.S:64 +64 RVECENT(reset,0) /* U-boot entry point */ +Current language: auto; currently asm +(gdb) b board.c:289 +Breakpoint 1 at 0xbfc00cc8: file board.c, line 289. +(gdb) c +Continuing. + +Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290 +290 relocate_code (addr_sp, id, addr); +Current language: auto; currently c +(gdb) p/x addr +$1 = 0x87fa0000 + +2) Debugging of U-Boot After Relocation + +For debugging U-Boot after relocation we need to know the address to which +U-Boot relocates itself to 0x87fa0000 by default. +And replace the symbol table to this offset. + +(gdb) symbol-file +Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y +Error in re-setting breakpoint 1: +No symbol table is loaded. Use the "file" command. +No symbol file now. +(gdb) add-symbol-file u-boot 0x87fa0000 +add symbol table from file "u-boot" at + .text_addr = 0x87fa0000 +(y or n) y +Reading symbols from /private/u-boot-arm/u-boot...done. +Breakpoint 1 at 0x87fa0cc8: file board.c, line 289. +(gdb) c +Continuing. + +Program received signal SIGINT, Interrupt. +0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78 +78 while ((tmo - read_c0_count()) < 0x7fffffff) diff --git a/board/renesas/sh7757lcr/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr new file mode 100644 index 00000000000..3e9c1c1a1e9 --- /dev/null +++ b/board/renesas/sh7757lcr/README.sh7757lcr @@ -0,0 +1,77 @@ +======================================== +Renesas R0P7757LC0030RL board +======================================== + +This board specification: +========================= + +The R0P7757LC0030RL(board config name:sh7757lcr) has the following device: + + - SH7757 (SH-4A) + - DDR3-SDRAM 256MB (with ECC) + - SPI ROM 8MB + - 2D Graphic controller + - Ethernet controller + - eMMC 2GB + + +configuration for This board: +============================= + +You can select the configuration as follows: + + - make sh7785lcr_config + + +This board specific command: +============================ + +This board has the following its specific command: + + - sh_g200 + - write_mac + + +1. sh_g200 + +If we run this command, SH4 can control the G200. +The default setting is that SH4 cannot control the G200. + + +2. write_mac + +You can write MAC address to SPI ROM. + + Usage 1) Write MAC address + + write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1] + + For example) + => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83 + *) We have to input the command as a single line + (without carriage return) + *) We have to reset after input the command. + + Usage 2) Show current data + + write_mac + + For example) + => write_mac + ETHERC ch0 = 00:00:87:6c:21:80 + ETHERC ch1 = 00:00:87:6c:21:81 + GETHERC ch0 = 00:00:87:6c:21:82 + GETHERC ch1 = 00:00:87:6c:21:83 + + +Update SPI ROM: +============================ + +1. Copy u-boot image to RAM area. +2. Probe SPI device. + => sf probe 0 + 8192 KiB M25P64 at 0:0 is now current device +3. Erase SPI ROM. + => sf erase 0 80000 +4. Write u-boot image to SPI ROM. + => sf write 0x89000000 0 80000 diff --git a/board/renesas/sh7785lcr/README.sh7785lcr b/board/renesas/sh7785lcr/README.sh7785lcr new file mode 100644 index 00000000000..56455fc1625 --- /dev/null +++ b/board/renesas/sh7785lcr/README.sh7785lcr @@ -0,0 +1,123 @@ +======================================== +Renesas Technology R0P7785LC0011RL board +======================================== + +This board specification: +========================= + +The R0P7785LC0011RL(board config name:sh7785lcr) has the following device: + + - SH7785 (SH-4A) + - DDR2-SDRAM 512MB + - NOR Flash 64MB + - 2D Graphic controller + - SATA controller + - Ethernet controller + - USB host/peripheral controller + - SD controller + - I2C controller + - RTC + +This board has 2 physical memory maps. It can be changed with DIP switch(S2-5). + + phys address | S2-5 = OFF | S2-5 = ON + -------------------------------+---------------+--------------- + 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash + 0x04000000 - 0x05ffffff(CS1) | PLD | PLD + 0x06000000 - 0x07ffffff(CS1) | reserved | I2C + 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM + 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM + 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 + 0x14000000 - 0x17ffffff(CS5) | I2C | USB + 0x18000000 - 0x1bffffff(CS6) | reserved | SD + 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) + + +configuration for This board: +============================= + +You can choose configuration as follows: + + - make sh7785lcr_config + - make sh7785lcr_32bit_config + +When you use "make sh7785lcr_config", there is build U-Boot for 29-bit +address mode. This mode can use 128MB DDR-SDRAM. + +When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit +extended address mode. This mode can use 384MB DDR-SDRAM. And if you run +"pmb" command, this mode can use 512MB DDR-SDRAM. + + * 32-bit extended address mode PMB mapping * + a) on start-up + virt | phys | size | device + -------------+---------------+---------------+--------------- + 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable) + 0xa0000000 | 0x00000000 | 64MB | NOR Flash + 0xa4000000 | 0x04000000 | 16MB | PLD + 0xa6000000 | 0x08000000 | 16MB | USB + 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable) + + b) after "pmb" command + virt | phys | size | device + -------------+---------------+---------------+--------------- + 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable) + 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable) + + +This board specific command: +============================ + +This board has the following its specific command: + + - hwtest + - printmac + - setmac + - pmb (sh7785lcr_32bit_config only) + + +1. hwtest + +This is self-check command. This command has the following options: + + - all : test all hardware + - pld : output PLD version + - led : turn on LEDs + - dipsw : test DIP switch + - sm107 : output SM107 version + - net : check RTL8110 ID + - sata : check SiI3512 ID + - net : output PCI slot device ID + +i.e) +=> hwtest led +turn on LEDs 3, 5, 7, 9 +turn on LEDs 4, 6, 8, 10 + +=> hwtest net +Ethernet OK + + +2. printmac + +This command outputs MAC address of this board. + +i.e) +=> printmac +MAC = 00:00:87:**:**:** + + +3. setmac + +This command writes MAC address of this board. + +i.e) +=> setmac 00:00:87:**:**:** + + +4. pmb + +This command change PMB for DDR-SDRAM all mapping. However you cannot use +NOR Flash and USB Host on U-Boot when you run this command. +i.e) +=> pmb diff --git a/board/sandbox/sandbox/README.sandbox b/board/sandbox/sandbox/README.sandbox new file mode 100644 index 00000000000..04692b34fa7 --- /dev/null +++ b/board/sandbox/sandbox/README.sandbox @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +Native Execution of U-Boot +========================== + +The 'sandbox' architecture is designed to allow U-Boot to run under Linux on +almost any hardware. To achieve this it builds U-Boot (so far as possible) +as a normal C application with a main() and normal C libraries. + +All of U-Boot's architecture-specific code therefore cannot be built as part +of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test +all the generic code, not specific to any one architecture. The idea is to +create unit tests which we can run to test this upper level code. + +CONFIG_SANDBOX is defined when building a native board. + +The chosen vendor and board names are also 'sandbox', so there is a single +board in board/sandbox/sandbox. + +CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian +machines. + +Note that standalone/API support is not available at present. + +The serial driver is a very simple implementation which reads and writes to +the console. It does not set the terminal into raw mode, so cursor keys and +history will not work yet. + + +Tests +----- + +So far we have no tests, but when we do these will be documented here. diff --git a/board/sandpoint/README b/board/sandpoint/README index 9e48168a24c..a2e0831f33b 100644 --- a/board/sandpoint/README +++ b/board/sandpoint/README @@ -13,3 +13,401 @@ seem to maintain it any more. I can be reached by mail as tkoeller@gmx.net. Thomas Koeller + + + + +The port was tested on a Sandpoint 8240 X3 board, with U-Boot +installed in the flash memory of the CPU card. Please use the +following DIP switch settings: + +Motherboard: + +SW1.1: on SW1.2: on SW1.3: on SW1.4: on +SW1.5: on SW1.6: on SW1.7: on SW1.8: on + +SW2.1: on SW2.2: on SW2.3: on SW2.4: on +SW2.5: on SW2.6: on SW2.7: on SW2.8: on + + +CPU Card: + +SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on +SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF + +SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF +SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on + + +The followind detailed description of installation and initial steps +with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>: + + +Directions for installing U-Boot on Sandpoint+Unity8240 +using the Abatron BDI2000 BDM/JTAG debugger ... + +Background and Reference info: +http://u-boot.sourceforge.net/ +http://www.abatron.ch/ +http://www.abatron.ch/BDI/bdihw.html +http://www.abatron.ch/DataSheets/BDI2000.pdf +http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf +http://e-www.motorola.com/collateral/SPX3UM.pdf +http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf + + +Connection Diagram: + =========== + === ===== |----- | +| | <---------------> | | | | | +|PC | rs232 | BDI |=============[] | | +| | |2000 | BDM probe | | | +| | <---------------> | | |----- | + === ethernet ===== | | + | | + =========== + Sandpoint X3 with + Unity 8240 proc + + +PART 1) + DIP Switch Settings: + +Sandpoint X3 8240 processor board DIP switch settings, with +U-Boot to be installed in the flash memory of the CPU card: + +Motorola Sandpoint X3 Motherboard: +SW1.1: on SW1.2: on SW1.3: on SW1.4: on +SW1.5: on SW1.6: on SW1.7: on SW1.8: on +SW2.1: on SW2.2: on SW2.3: on SW2.4: on +SW2.5: on SW2.6: on SW2.7: on SW2.8: on + +Motorola Unity 8240 CPU Card: +SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on +SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF +SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF +SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on + + +PART 2) + Connect the BDI2000 Cable to the Sandpoint/Unity 8240: + +BDM Pin 1 on the Unity 8240 processor board is towards the +PCI PMC connectors, or away from the socketed SDRAM, i.e.: + + ==================== + | ---------------- | + | | SDRAM | | + | | | | + | ---------------- | + | |~| | + | |B| ++++++ | + | |D| + uP + | + | |M| +8240+ | + | ~ 1 ++++++ | + | | + | | + | | + | PMC conn ====== | + | ===== ====== | + | | + ==================== + + +PART 3) + Setting up the BDI2000, and preparing for TCP/IP network comms: + +Connect the BDI2000 to the PC using the supplied serial cable. +Download the BDI2000 software and install it using setup.exe. + +[Note: of course you can also use the Linux command line tool +"bdisetup" to configure your BDI2000 - the sources are included on +the floppy disk that comes with your BDI2000. Just in case you don't +have any Windows PC's - like me :-) -- wd ] + +Power up the BDI2000; then follow directions to assign the IP +address and related network information. Note that U-Boot +will be loaded to the Sandpoint via tftp. You need to either +use the Abatron-provided tftp application or provide a tftp +server (e.g. Linux/Solaris/*BSD) somewhere on your network. +Once the IP address etc are assigned via the RS232 port, +further communication with the BDI2000 will happen via the +ethernet connection. + +PART 4) + Making a TCP/IP network connection to the Abatron BDI2000: + +Telnet to the Abatron BDI2000. Assuming that all of the +networking info was loaded via RS232 correctly, you will see +the following (scrolling): + +- TARGET: waiting for target Vcc +- TARGET: waiting for target Vcc + + +PART 5) + Power up the target Sandpoint: +If the BDM connections are correct, the following will now appear: + +- TARGET: waiting for target Vcc +- TARGET: waiting for target Vcc +- TARGET: processing power-up delay +- TARGET: processing user reset request +- BDI asserts HRESET +- Reset JTAG controller passed +- Bypass check: 0x55 => 0xAA +- Bypass check: 0x55 => 0xAA +- JTAG exists check passed +- Target PVR is 0x00810101 +- COP status is 0x01 +- Check running state passed +- BDI scans COP freeze command +- BDI removes HRESET +- COP status is 0x05 +- Check stopped state passed +- Check LSRL length passed +- BDI sets breakpoint at 0xFFF00100 +- BDI resumes program execution +- Waiting for target stop passed +- TARGET: Target PVR is 0x00810101 +- TARGET: reseting target passed +- TARGET: processing target startup .... +- TARGET: processing target startup passed +BDI> + + +PART 6) + Erase the current contents of the flash memory: + +BDI>era 0xFFF00000 + Erasing flash at 0xfff00000 + Erasing flash passed +BDI>era 0xFFF04000 + Erasing flash at 0xfff04000 + Erasing flash passed +BDI>era 0xFFF06000 + Erasing flash at 0xfff06000 + Erasing flash passed +BDI>era 0xFFF08000 + Erasing flash at 0xfff08000 + Erasing flash passed +BDI>era 0xFFF10000 + Erasing flash at 0xfff10000 + Erasing flash passed +BDI>era 0xFFF20000 + Erasing flash at 0xfff20000 + Erasing flash passed + + +PART 7) + Program the flash memory with the U-Boot image: + +BDI>prog 0xFFF00000 u-boot.bin bin + Programming u-boot.bin , please wait .... + Programming flash passed + + +PART 8) + Connect PC to Sandpoint: +Using a crossover serial cable, attach the PC serial port to the +Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. + + +PART 9) + Reset the Unity and begin U-Boot execution: + +BDI>reset +- TARGET: processing user reset request +- TARGET: Target PVR is 0x00810101 +- TARGET: reseting target passed +- TARGET: processing target init list .... +- TARGET: processing target init list passed + +BDI>go + +Now see output from U-Boot running, sent via serial port: + +U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) + +CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache +Board: Sandpoint 8240 Unity +DRAM: 64 MB +FLASH: 2 MB +PCI: scanning bus0 ... + bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE + 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 + 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 + 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 +In: serial +Out: serial +Err: serial +=> + + +PART 10) + Set and save any required environmental variables, examples of some: + +=> setenv ethaddr 00:03:47:97:D0:79 +=> setenv bootfile your_qnx_image_here +=> setenv hostname sandpointX +=> setenv netmask 255.255.255.0 +=> setenv ipaddr 192.168.0.11 +=> setenv serverip 192.168.0.10 +=> setenv gatewayip=192.168.0.1 +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +**** Example environment: **** + +=> printenv +baudrate=9600 +bootfile=telemetry +hostname=sp1 +ethaddr=00:03:47:97:E4:6B +load=tftp 100000 u-boot.bin +update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv +filesize=1f304 +gatewayip=145.17.228.1 +netmask=255.255.255.0 +ipaddr=145.17.228.42 +serverip=145.17.242.46 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 332/8188 bytes +=> + +here's some text useful stuff for cut-n-paste: +setenv hostname sandpoint1 +setenv netmask 255.255.255.0 +setenv ipaddr 145.17.228.81 +setenv serverip 145.17.242.46 +setenv gatewayip 145.17.228.1 +saveenv + +PART 11) + Test U-Boot by tftp'ing new U-Boot, overwriting current: + +=> protect off all +Un-Protect Flash Bank # 1 +=> tftp 100000 u-boot.bin +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 127628 (1f28c hex) +=> era all +Erase Flash Bank # 1 + done +Erase Flash Bank # 2 - missing +=> cp.b 0x100000 FFF00000 1f28c +Copy to Flash... done +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> reset + +You can put these commands into some environment variables; + +=> setenv load tftp 100000 u-boot.bin +=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv +=> saveenv + +Then you just have to type "run load" then "run update" + +=> run load +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 127748 (1f304 hex) +=> run update +Un-Protect Flash Bank # 1 +Un-Protect Flash Bank # 2 +Erase Flash from 0xfff00000 to 0xfff3ffff + done +Erased 7 sectors +Copy to Flash... done +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + + +PART 12) + Load OS image (ELF format) via U-Boot using tftp + + +=> tftp 800000 sandpoint-simple.elf +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'sandpoint-simple.elf'. +Load address: 0x800000 +Loading: ################################################################# + ################################################################# + ################################################################# + ######################## +done +Bytes transferred = 1120284 (11181c hex) +==> + +PART 13) + Begin OS image execution: (note that unless you have the +serial parameters of your OS image set to 9600 (i.e. same as +the U-Boot binary) you will get garbage here until you change +the serial communications speed. + +=> bootelf 800000 +Loading @ 0x001f0100 (1120028 bytes) +## Starting application at 0x001f1d28 ... +Replace init_hwinfo() with a board specific version + +Loading QNX6.... + +Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 +<...loader and kernel messages snipped...> + +Welcome to Neutrino on the Sandpoint +# + + +other information: + +CVS Retrieval Notes: + +U-Boot's SourceForge CVS repository can be checked out +through anonymous (pserver) CVS with the following +instruction set. The module you wish to check out must +be specified as the modulename. When prompted for a +password for anonymous, simply press the Enter key. + +cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login + +cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot diff --git a/board/sbc8349/README b/board/sbc8349/README new file mode 100644 index 00000000000..2c35919f28c --- /dev/null +++ b/board/sbc8349/README @@ -0,0 +1,127 @@ + + + U-Boot for Wind River SBC834x Boards + ==================================== + + +The Wind River SBC834x board is a 6U form factor (not CPCI) reference +design that uses the MPC8347E or MPC8349E processor. U-Boot support +for this board is heavily based on the existing U-Boot support for +Freescale MPC8349 reference boards. + +Support has been primarily tested on the SBC8349 version of the board, +although earlier versions were also tested on the SBC8347. The primary +difference in the two is the level of PCI functionality. + + http://www.windriver.com/products/OCD/SBC8347E_49E/ + + +Flash Details: +============== + +The flash type is intel 28F640Jx (4096x16) [one device]. Base address +is 0xFF80_0000 which is also where the Hardware Reset Configuration +Word (HRCW) is stored. Caution should be used to not reset the +board without having a valid HRCW in place (i.e. erased flash) as +then a Wind River ICE will be required to restore the HRCW and flash +image. + + +Restoring a corrupted or missing flash image: +============================================= + +Note that U-boot versions up to and including 2009.06 had essentially +two copies of u-boot in flash; one at the very beginning, which set +the HRCW, and one at the very end, which was the image that was run. +As of this point in time, the two have been combined into just one +at the beginning of flash, which provides both the HRCW, and the image +that is executed. This frees up the remainder of flash for other uses. +Use of the u-boot command "fli" will indicate what parts are in use. +Details for storing U-boot to flash using a Wind River ICE can be found +on page 19 of the board manual (request ERG-00328-001). The following +is a summary of that information: + + - Connect ICE and establish connection to it from WorkBench/OCD. + - Ensure you have background mode (BKM) in the OCD terminal window. + - Select the appropriate flash type (listed above) + - Prepare a u-boot image by using the Wind River Convert utility; + by using "Convert and Add file" on the ELF file from your build. + Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are + trying to preserve your old environment settings and user flash). + - Set the start address of the erase/flash process to FF80_0000 + - Set the target RAM required to 64kB. + - Select sectors for erasing (see note on enviroment below) + - Select Erase and Reprogram. + +Note that some versions of the register files used with Workbench +would zero some TSEC registers, which inhibits ethernet operation +by u-boot when this register file is played to the target. Using +"INN" in the OCD terminal window instead of "IN" before the "GO" +will not play the register file, and allow u-boot to use the TSEC +interface while executed from the ICE "GO" command. + +Alternatively, you can locate the register file which will be named +WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines +beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to +use all the remaining register file content. + +If you wish to preserve your prior U-Boot environment settings, +then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF. +The size for converting (and erasing) must be at least as large +as u-boot.bin. + + +Updating U-Boot with U-Boot: +============================ + +This procedure is very similar to other boards that have u-boot installed. +Assuming that the network has been configured, and that the new u-boot.bin +has been copied to the TFTP server, the commands are: + + tftp 200000 u-boot.bin + protect off all + erase ff800000 ff83ffff + cp.b 200000 ff800000 40000 + protect on all + +You may wish to do a "md ff800000 20" operation as a prefix and postfix +to the above steps to inspect/compare the HRCW before/after as an extra +safety check before resetting the board upon completion of the reflash. + +PCI: +==== + +There are three configuration choices: + sbc8349_config + sbc8349_PCI_33_config + sbc8349_PCI_66_config + +The 1st does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. The only +reason for choosing to not enable PCI would be if you had a very +early (rev 1.0) CPU with possible PCI issues. + +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with sbc8349_PCI_33_config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. This has been tested with an intel PCI-X e1000 card. +This is also the appropriate choice for people with a recent (non 1.0) +CPU who currently have the PCI slot physically empty, but intend to +possibly add a PCI-X card at a later date. + + => pci + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 00.00.00 0x1957 0x0080 Processor 0x20 + 00.11.00 0x8086 0x1026 Network controller 0x00 + => diff --git a/board/sbc8548/README b/board/sbc8548/README new file mode 100644 index 00000000000..feac5e3e63e --- /dev/null +++ b/board/sbc8548/README @@ -0,0 +1,269 @@ +Intro: +====== + +The SBC8548 is a stand alone single board computer with a 1GHz +MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz +memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, +and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC +ethernet connections. + +U-boot Configuration: +===================== + +The following possible u-boot configuration targets are available: + + 1) sbc8548_config + 2) sbc8548_PCI_33_config + 3) sbc8548_PCI_66_config + 4) sbc8548_PCI_33_PCIE_config + 5) sbc8548_PCI_66_PCIE_config + +Generally speaking, most people should choose to use #5. Details +of each choice are listed below. + +Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. + +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with a _PCI_33_ config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. [The above discussion assumes that the SW2[1-4] has not been changed +to reflect a different CCB:SYSCLK ratio] + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. Options four and five are just repeats of option two +and three, but with PCI-e support enabled as well. + +PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx +is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with +a 33MHz PCI configuration is currently untested.) + + => pci 0 + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 00.00.00 0x1057 0x0012 Processor 0x20 + 00.01.00 0x8086 0x1026 Network controller 0x00 + => pci 1 + Scanning PCI devices on bus 1 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 01.00.00 0x1957 0x0012 Processor 0x20 + => pci 2 + Scanning PCI devices on bus 2 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 02.00.00 0x1148 0x9e00 Network controller 0x00 + => + +Memory Size and using SPD: +========================== + +The default configuration uses hard coded memory configuration settings +for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD +EEPROM data to read what memory is installed. + +There is a hardware errata, which causes the older local bus SDRAM +SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so +that the SPD data can not be read reliably. You can test if your +board has the errata fix by running "i2c probe". If you see 0x53 +as a valid device, it has been fixed. If you only see 0x50, 0x51 +then your board does not have the fix. + +You can also visually inspect the board to see if this hardware +fix has been applied: + + 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on + the back of the PCB behind the DDR SDRAM SODIMM connector. + 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad + to R313 pin 2. Pin 2 for each resistor is the end of the + resistor closest to the CPU. + +Boards without the mod will have R314 and R313 in parallel, like "||". +After the mod, they will be touching and form an "L" shape. + +If you want to upgrade to larger RAM size, you can simply enable + #define CONFIG_SPD_EEPROM + #define CONFIG_DDR_SPD +in include/configs/sbc8548.h file. (The lines are already there +but listed as #undef). + +If you did the i2c test, and your board does not have the errata +fix, then you will have to physically remove the LBC 128MB DIMM +from the board's socket to resolve the above i2c address overlap +issue and allow SPD autodetection of RAM to work. + + +Updating U-boot with U-boot: +============================ + +Note that versions of u-boot up to and including 2009.08 had u-boot stored +at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from +0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to +update u-boot with u-boot and it uses the old address, you will render +your board inoperable, and you will require JTAG recovery. + +The following steps list how to update with the current address: + + tftp u-boot.bin + md 200000 10 + protect off all + erase fffa0000 ffffffff + cp.b 200000 fffa0000 60000 + md fffa0000 10 + protect on all + +The "md" steps in the above are just a precautionary step that allow +you to confirm the u-boot version that was downloaded, and then confirm +that it was copied to flash. + +The above assumes that you are using the default board settings which +have u-boot in the 8MB flash, tied to /CS0. + +If you are running the default 8MB /CS0 settings but want to store an +image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, +(as a backup, etc) then the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era eff00000 efffffff + cp.b 200000 eff00000 100000 + md eff00000 10 + protect on all + +Finally, if you are running the alternate 64MB /CS0 settings and want +to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT +enabled) the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era fff00000 ffffffff + cp.b 200000 fff00000 100000 + md fff00000 10 + protect on all + + +Hardware Reference: +=================== + +The following contains some summary information on hardware settings +that are relevant to u-boot, based on the board manual. For the +most up to date and complete details of the board, please request the +reference manual ERG-00327-001.pdf from www.windriver.com + +Boot flash: + intel V28F640Jx, 8192x8 (one device) at 0xff80_0000 + +Sodimm flash: + intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + Note that this address reflects the default setting for + the JTAG debugging tools, but since the alignment is + rather inconvenient, u-boot puts it at 0xec00_0000. + + + Jumpers: + +Jumper Name ON OFF +---------------------------------------------------------------- +JP12 CS0/CS6 swap see note[*] see note[*] + +JP13 SODIMM flash write OK writes disabled + write prot. + +JP14 HRESET/TRST joined isolated + +JP15 PWR ON when AC pwr use S1 for on/off + +JP16 Demo LEDs lit not lit + +JP19 PCI mode PCI PCI-X + + +[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash +onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 +is jumpered parallel to the LBC-SDRAM, then /CS0 is for the +SODIMM flash and /CS6 is for the boot flash. Note that in this +alternate setting, you also need to switch SW2.8 to ON. +See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting +and boot u-boot from the 64MB SODIMM + + + Switches: + +The defaults are marked with a * + +Name Desc. ON OFF +------------------------------------------------------------------ +S1 Pwr toggle n/a n/a + +SW2.1 CFG_SYS_PLL0 1 0* +SW2.2 CFG_SYS_PLL1 1* 0 +SW2.3 CFG_SYS_PLL2 1* 0 +SW2.4 CFG_SYS_PLL3 1 0* +SW2.5 CFG_CORE_PLL0 1* 0 +SW2.6 CFG_CORE_PLL1 1 0* +SW2.7 CFG_CORE_PLL2 1* 0 +SW2.8 CFG_ROM_LOC1 1 0* + +SW3.1 CFG_HOST_AGT0 1* 0 +SW3.2 CFG_HOST_AGT1 1* 0 +SW3.3 CFG_HOST_AGT2 1* 0 +SW3.4 CFG_IO_PORTS0 1* 0 +SW3.5 CFG_IO_PORTS0 1 0* +SW3.6 CFG_IO_PORTS0 1 0* + +SerDes CLK(MHz) SW5.1 SW5.2 +---------------------------------------------- +25 0 0 +100* 1 0 +125 0 1 +200 1 1 + +SerDes CLK spread SW5.3 SW5.4 +---------------------------------------------- ++/- 0.25% 0 0 +-0.50% 1 0 +-0.75% 0 1 +No Spread* 1 1 + +SW4 settings are readable from the EPLD and are currently not used for +any hardware settings (i.e. user configuration switches). + + LEDs: + +Name Desc. ON OFF +------------------------------------------------------------------ +D13 PCI/PCI-X PCI-X PCI +D14 3.3V PWR 3.3V no power +D15 SYSCLK 66MHz 33MHz + + + Default Memory Map: + +start end CS<n> width Desc. +---------------------------------------------------------------------- +0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) +f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) +f800_0000 f8b0_1fff CS5 - EPLD +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] +ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) + +[*] fb80 represents the default programmed by WR JTAG register files, + but u-boot places the flash at either ec00 or fc00 based on JP12. + +The EPLD on CS5 demuxes the following devices at the following offsets: + +offset size width device +-------------------------------------------------------- +0 1fff 8 7 segment display LED +10_0000 1fff 4 user switches +30_0000 1fff 4 HW Rev. register +b0_0000 1fff 8 8kB EEPROM diff --git a/board/sbc8560/README b/board/sbc8560/README new file mode 100644 index 00000000000..c4b642236e9 --- /dev/null +++ b/board/sbc8560/README @@ -0,0 +1,57 @@ +The port was tested on Wind River System Sbc8560 board +<www.windriver.com>. U-Boot was installed on the flash memory of the +CPU card (no the SODIMM). + +NOTE: Please configure uboot compile to the proper PCI frequency and +setup the appropriate DIP switch settings. + +SBC8560 board: + +Make sure boards switches are set to their appropriate conditions. +Refer to the Engineering Reference Guide ERG-00300-002. Of particular +importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which +select the on-board FLASH device (Intel 28F128Jx); 2) The settings +for the Clock SW9 (33 MHz or 66 MHz). + + Note: SW9 Settings: 66 MHz + 4:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on + Note: SW9 Settings: 33 MHz + 8:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on + + +Flashing the FLASH device with the "Wind River ICE": + +1) Properly connect and configure the Wind River ICE to the target + JTAG port. This includes running the SBC8560 register script. Make + sure target memory can be read and written. + +2) Build the u-boot image: + make distclean + make SBC8560_66_config or SBC8560_33_config + make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all + + Note: reference is made to the ELDK3.0 compiler. Further, it seems + the ppc_8xx compiler is required for the 85xx (no 85xx + designated compiler in ELDK3.0) + +3) Convert the uboot (.elf) file to a uboot.bin file (using + visionClick converter). The bin file should be converted from + fffc0000 to ffffffff + +4) Setup the Flash Utility (tools menu) for: + + Do a "dc clr" [visionClick] to load the default register settings + Determine the clock speed of the PCI bus and set SW9 accordingly + Note: the speed of the PCI bus defaults to the slowest PCI card + PlayBack the "default" register file for the SBC8560 + Select the uboot.bin file with zero bias + Select the initialize Target prior to programming + Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm + Select the erase base address from FFFC0000 to FFFFFFFF + Select the start address from 0 with size of 4000 + +5) Erase and Program diff --git a/board/sbc8641d/README b/board/sbc8641d/README new file mode 100644 index 00000000000..a051466a11b --- /dev/null +++ b/board/sbc8641d/README @@ -0,0 +1,28 @@ +Wind River SBC8641D reference board +=========================== + +Created 06/14/2007 Joe Hamman +Copyright 2007, Embedded Specialties, Inc. +Copyright 2007 Wind River Systemes, Inc. +----------------------------- + +1. Building U-Boot +------------------ +The SBC8641D code is known to build using ELDK 4.1. + + $ make sbc8641d_config + Configuring for sbc8641d board... + + $ make + + +2. Switch and Jumper Settings +----------------------------- +All Jumpers & Switches are in their default positions. Please refer to +the board documentation for details. Some settings control CPU voltages +and settings may change with board revisions. + +3. Known limitations +-------------------- +PCI: + The PCI command may hang if no boards are present in either slot. diff --git a/board/sheldon/simpc8313/README.simpc8313 b/board/sheldon/simpc8313/README.simpc8313 new file mode 100644 index 00000000000..b362c6aeea0 --- /dev/null +++ b/board/sheldon/simpc8313/README.simpc8313 @@ -0,0 +1,80 @@ +Sheldon Instruments SIMPC8313 Board +----------------------------------------- + +1. Board Switches and Jumpers + + S2 is used to set CFG_RESET_SOURCE. + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | * * **** | + | * * | + +----------+ + 12345678 + + To boot the image in Small page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | *** **** | + | * | + +----------+ + 12345678 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x1fff_ffff DDR 512M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K + or + 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K + 0xff00_0000 0xff00_7fff FPGA (CS1) 1M + +3. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make SIMPC8313_LP_config + (or make SIMPC8313_SP_config, depending on the page size + of your NAND flash) + make + +4. Downloading and Flashing Images + +4.1 Reflash U-boot Image using U-boot + + =>run update_uboot + + You may want to try + =>tftp $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + if the new u-boot doesn't boot, you can plug the board into + your PCI slot and with the supplied driver and sample app + you can reburn a working u-boot. + +4.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, fdtfile, and bootfile). + + =>tftp $loadaddr uImage + =>nand write $loadaddr kernel $filesize + =>tftp $loadaddr $fdtfile + =>nand write $loadaddr 7e0000 1800 + + =>boot + +5 Notes + + The console baudrate for SIMPC8313 is 115200bps. diff --git a/board/st/nhk8815/README.nhk8815 b/board/st/nhk8815/README.nhk8815 new file mode 100644 index 00000000000..9008e393637 --- /dev/null +++ b/board/st/nhk8815/README.nhk8815 @@ -0,0 +1,32 @@ + +The Nomadik 8815 CPU has a "secure" boot mode where no external access +(not even JTAG) is allowed. The "remap" bits in the evaluation board +are configured in order to boot from the internal ROM memory (in +secure mode). + +The boot process as defined by the manufacturer executes external code +(loaded from NAND or OneNAND) that that disables such "security" in +order to run u-boot and later the kernel without constraints. Such +code is a proprietary initial boot loader, called "X-Loader" (in case +anyone wonders, it has no relations with other loaders with the same +name and there is no GPL code inside the ST X-Loader). + +SDRAM configuration, PLL setup and initial loading from NAND is +implemented in the X-Loader, so U-Boot is already running in SDRAM +when control is handed over to it. + +The Makefile offers two different configurations to be used if you +boot from Nand or OneNand. + + make nhk8815_config + make nhk8815_onenand_config + +Both support OneNand and Nand. Since U-Boot, running in RAM, can't know +where it was loaded from, the configurations differ in where the filesystem +is looked for by default. + + +On www.st.com/nomadik and on www.stnwireless.com there are documents, +summary data and white papers on Nomadik. The full datasheet for +STn8815 is not currently available on line but under specific request +to the local ST sales offices. diff --git a/board/stx/stxxtc/README.stxxtc b/board/stx/stxxtc/README.stxxtc new file mode 100644 index 00000000000..7d9d4d3a2e0 --- /dev/null +++ b/board/stx/stxxtc/README.stxxtc @@ -0,0 +1,59 @@ + + +First, some build notes on the Silicon Turnkey eXpress XTc. + +This board has both 87x/88x procesor options at various +frequencies. The configuration file has some macros for setting +the clock speed, not all have been tested. They all have +a 10MHz input clock. Please do not check in a configuration +file that selects a high speed not available on all processors. +We chose the 66MHz core and bus speed, which should be OK on +all boards. If you have a processor, lucky you! :-) +Just build a new configuration with that speed, check +the macro configuration to ensure it's correct. If the +macro is updated, please check that in, but keep default +processor speed. + +The board is likely to have more than 1Mbyte of NOR boot flash. +It was also configured with a high boot vector (Dan's fault) +so the standard 8xx mapping doesn't work well. We had to move +the addresses around a little bit so one copy would work. The +flash got fragmented, and we are working on a better solution. +There is an "xtc.cfg" floating around for the BDI2000, use +that for programming a new version of U-Boot. You can probably +find it on the Silicon Turnkey eXpress (www.silicontkx.com), +Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de) +servers. + +The board will also have various SDRAM sizes, but the code +should automatically determine the amount of memory. + +There are a couple of different board versions, visually +they use different BGA or surface mount memory parts. However, +they are logically the same board. + +Now, some operational notes. + +The board has the option of sporting two FEC Ethernet ports. +The second port isn't configured to be automatically available +because it would cause U-Boot to generate a board data structure +(the bd_t) with multiple MAC addresses and be incompatible with +standard 8xx kernel builds. You can use/test the second FEC +in U-Boot by assigning an 'eth1addr' and selecting the second +FEC as the port to use. + +Since this is just a development board and not a product, STx +does not assign unique MAC addresses. We just pilfer the +"default" ones used by Wolfgang on some other boards. Please +ensure you assign unique MAC addresses when using these boards. + +The serial port baud rate is 38400, because that's the way +I like it :-) + +Thanks to Pantelis for lots of the work on this board port. + +Have Fun! + + -- Dan + +15 August 2005 diff --git a/board/ti/omap730p2/README.omap730p2 b/board/ti/omap730p2/README.omap730p2 new file mode 100644 index 00000000000..7c70916120b --- /dev/null +++ b/board/ti/omap730p2/README.omap730p2 @@ -0,0 +1,91 @@ + + u-boot for the TI OMAP730 Perseus2 + + Dave Peverley, MPC-Data Limited + http://www.mpc-data.co.uk + + +Overview : + + As the OMAP730 is similar to the OMAP1610 in many ways, this port was based +on the u-boot port to the OMAP1610 Innovator. Supported features are : + + - Serial terminal support + - Onboard NOR Flash + - Ethernet via the seperate debug board + - Tested on Rev4 and Rev5 boards + + It has also been tested to work correctly when built with a 'standard' GCC +3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain. + + +Hardware Configuration : + + The main dips on the P2 board should be set to 2,3,7 and 9 on with all +others off. On the debug board, dips 1 and 7 should be on with the rest off. +The serial console has been set up to run from the DB9 connector on the +P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit. + + It should be noted that the P2 board has NOR flash that is addressable via +either CS0 or CS3. This mode can be changed via DIP9 on the P2 board. + + +Installing u-boot for the P2 : + + You can simply build u-boot for the Perseus by following the instructions +in the main readme file. The target configuration is "omap730p2_config". +Once u-boot has been built, you should strip the executable so it can be +loaded via CCS (which cant cope with the symbols in the ELF binary) : + $ cp u-boot u-boot.out + $ arm-linux-strip u-boot.out + + The method we've used for installing u-boot the first time on a P2 is +as follows : + +1) Configure TI Code Composer Studio to connect to the P2 board via JTAG + as described in the Users Guide. + +2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU + and run the "init_mmu" GEL script. + +3) Use the "Load Program" option to send the u-boot.out file to the P2 and + run. + + At this point, u-boot should run and you will see the boot menu on your +serial terminal. You can then load the u-boot image to memory : + + # loadb 0x10000000 + + Send the "u-boot.bin" binary via the serial using Kermit. Once loaded +you can self-flash u-boot : + + # protect off 1:0 + # erase 1:0 + # cp.b 0x10000000 0x0 0x20000 + + You should now be able to reset the board and run u-boot from flash. + + +Alternative flash option : + + Sometimes, if you've been silly, you can get the board into a state where +whats in flash has upset the board so much that you can no longer connect +to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode +of the P2 so that you boot from RAM instead of NOR flash. This moves NOR +flash up to 0x0C000000. You can build a special version of u-boot to +utilise this by the following config : + + $ make omap730p2_cs0boot_config + + If you load this up via CCS it will detect flash at its alternate location +and allow you to programme your u-boot image (which, remember must be built +for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work +fine again. + + +Errata : + +1) It's been observed that sometimes the tftp transfer of kernels to the + board can have checksum errors or stall. This appears to be an issue + with the lan91c96.c driver, and can normally be worked around by + resetting the board and trying again. diff --git a/board/timll/devkit8000/README b/board/timll/devkit8000/README new file mode 100644 index 00000000000..609bf51aee2 --- /dev/null +++ b/board/timll/devkit8000/README @@ -0,0 +1,15 @@ +DevKit8000 +========== + +The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board +with Ethernet and Touch Screen controller on board. + +For more information go to: +http://www.embedinfo.com/English/Product/devkit8000.asp + +There's no real MAC address available. +If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used. + +Build: +make devkit8000_config +make diff --git a/board/tqc/tqm8260/README b/board/tqc/tqm8260/README new file mode 100644 index 00000000000..93b55068f57 --- /dev/null +++ b/board/tqc/tqm8260/README @@ -0,0 +1,415 @@ + +This file contains basic information on the port of U-Boot to TQM8260. +All the changes fit in the common U-Boot infrastructure, providing a +new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, +type "make TQM8260_config", edit the "include/config_TQM8260.h" file +if necessary, then type "make". + + +Common file modifications: +-------------------------- + +The following common files have been modified by this project: +(starting from the ppcboot-0.9.3/ directory) + +MAKEALL - TQM8260 entry added +Makefile - TQM8260_config entry added +arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added +arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious + bug fixed (fcr -> scr) +arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added +include/flash.h - added definitions for the AM29LV640D Flash chip + + +New files: +---------- + +The following new files have been added by this project: +(starting from the ppcboot-0.9.3/ directory) + +board/tqm8260/ - board-specific directory +board/tqm8260/Makefile - board-specific makefile +board/tqm8260/config.mk - config file +board/tqm8260/flash.c - flash driver (for AM29LV640D) +board/tqm8260/ppcboot.lds - linker script +board/tqm8260/tqm8260.c - ioport and memory initialization +arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver +include/config_TQM8260.h - main configuration file + + +New configuration options: +-------------------------- + +CONFIG_TQM8260 + + Main board-specific option (should be defined for TQM8260). + +CONFIG_82xx_CONS_SMC1 + + If defined, SMC1 will be used as the console + +CONFIG_82xx_CONS_SMC2 + + If defined, SMC2 will be used as the console + +CONFIG_SYS_INIT_LOCAL_SDRAM + + If defined, the SDRAM on the local bus will be initialized and + mapped at BR2. + + +Acceptance criteria tests: +-------------------------- + +The following tests have been conducted to validate the port of U-Boot +to TQM8260: + +1. Operation on serial console: + +With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, +the U-Boot output appeared on the serial terminal connected to COM1 as +follows: + +------------------------------------------------------------------------------ +=> help +go - start application at address 'addr' +run - run commands in an environment variable +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +rarpboot- boot image via network using RARP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +loads - load S-Record file over serial line +loadb - load binary file over serial line (kermit mode) +md - memory display +mm - memory modify (auto-incrementing) +nm - memory modify (constant address) +mw - memory write (fill) +cp - memory copy +cmp - memory compare +crc32 - checksum calculation +base - print or set address offset +printenv- print environment variables +setenv - set environment variables +saveenv - save environment variables to persistent storage +protect - enable or disable FLASH write protection +erase - erase FLASH memory +flinfo - print FLASH memory information +bdinfo - print Board Info structure +iminfo - print header information for application image +coninfo - print console devices and informations +eeprom - EEPROM sub-system +loop - infinite loop on address range +mtest - simple RAM test +icache - enable or disable instruction cache +dcache - enable or disable data cache +reset - Perform RESET of the CPU +echo - echo args to console +version - print monitor version +help - print online help +? - alias for 'help' +=> +------------------------------------------------------------------------------ + + +2. Flash driver operation + +The following sequence was performed to test the "flinfo" command: + +------------------------------------------------------------------------------ +=> flinfo + +Bank # 1: AMD 29LV640D (64 M, uniform sector) + Size: 32 MB in 128 Sectors + Sector Start Addresses: + 40000000 40040000 (RO) 40080000 400C0000 40100000 + 40140000 40180000 401C0000 40200000 40240000 + 40280000 402C0000 40300000 40340000 40380000 + 403C0000 40400000 40440000 40480000 404C0000 + 40500000 40540000 40580000 405C0000 40600000 + 40640000 40680000 406C0000 40700000 40740000 + 40780000 407C0000 40800000 40840000 40880000 + 408C0000 40900000 40940000 40980000 409C0000 + 40A00000 40A40000 40A80000 40AC0000 40B00000 + 40B40000 40B80000 40BC0000 40C00000 40C40000 + 40C80000 40CC0000 40D00000 40D40000 40D80000 + 40DC0000 40E00000 40E40000 40E80000 40EC0000 + 40F00000 40F40000 40F80000 40FC0000 41000000 + 41040000 41080000 410C0000 41100000 41140000 + 41180000 411C0000 41200000 41240000 41280000 + 412C0000 41300000 41340000 41380000 413C0000 + 41400000 41440000 41480000 414C0000 41500000 + 41540000 41580000 415C0000 41600000 41640000 + 41680000 416C0000 41700000 41740000 41780000 + 417C0000 41800000 41840000 41880000 418C0000 + 41900000 41940000 41980000 419C0000 41A00000 + 41A40000 41A80000 41AC0000 41B00000 41B40000 + 41B80000 41BC0000 41C00000 41C40000 41C80000 + 41CC0000 41D00000 41D40000 41D80000 41DC0000 + 41E00000 41E40000 41E80000 41EC0000 41F00000 + 41F40000 41F80000 41FC0000 +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the erase command: + +------------------------------------------------------------------------------ +=> cp 0 40080000 10 +Copy to Flash... done +=> erase 40080000 400bffff +Erase Flash from 0x40080000 to 0x400bffff +.. done +Erased 1 sectors +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 40080000 10 +Copy to Flash... done +=> erase 1:2 +Erase Flash Sectors 2-2 in Bank # 1 +.. done +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 40080000 10 +Copy to Flash... done +=> cp 0 400c0000 10 +Copy to Flash... done +=> erase 1:2-3 +Erase Flash Sectors 2-3 in Bank # 1 +... done +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> md 400c0000 +400c0000: ffffffff ffffffff ffffffff ffffffff ................ +400c0010: ffffffff ffffffff ffffffff ffffffff ................ +400c0020: ffffffff ffffffff ffffffff ffffffff ................ +400c0030: ffffffff ffffffff ffffffff ffffffff ................ +400c0040: ffffffff ffffffff ffffffff ffffffff ................ +400c0050: ffffffff ffffffff ffffffff ffffffff ................ +400c0060: ffffffff ffffffff ffffffff ffffffff ................ +400c0070: ffffffff ffffffff ffffffff ffffffff ................ +400c0080: ffffffff ffffffff ffffffff ffffffff ................ +400c0090: ffffffff ffffffff ffffffff ffffffff ................ +400c00a0: ffffffff ffffffff ffffffff ffffffff ................ +400c00b0: ffffffff ffffffff ffffffff ffffffff ................ +400c00c0: ffffffff ffffffff ffffffff ffffffff ................ +400c00d0: ffffffff ffffffff ffffffff ffffffff ................ +400c00e0: ffffffff ffffffff ffffffff ffffffff ................ +400c00f0: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the Flash programming commands: + +------------------------------------------------------------------------------ +=> erase 40080000 400bffff +Erase Flash from 0x40080000 to 0x400bffff +.. done +Erased 1 sectors +=> cp 0 40080000 10 +Copy to Flash... done +=> md 0 +00000000: 00000000 00000104 61100200 01000000 ........a....... +00000010: 00000000 00000000 81140000 82000100 ................ +00000020: 01080000 00004000 22800000 00000600 ......@."....... +00000030: 00200800 00000000 10000100 00008000 . .............. +00000040: 00812000 00000200 00020000 80000000 .. ............. +00000050: 00028001 00001000 00040400 00000200 ................ +00000060: 20480000 00000000 20090000 00142000 H...... ..... . +00000070: 00000000 00004000 24210000 10000000 ......@.$!...... +00000080: 02440002 10000000 00200008 00000000 .D....... ...... +00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. +000000a0: 04420800 00000000 00000040 00020000 .B.........@.... +000000b0: 05020000 00100000 00060000 00000000 ................ +000000c0: 00400000 00000000 00080000 00040000 .@.............. +000000d0: 10400000 00800004 00000000 00000200 .@.............. +000000e0: 80890000 00010004 00080000 00000020 ............... +000000f0: 08000000 10000000 00010000 00000000 ................ +=> md 40080000 +40080000: 00000000 00000104 61100200 01000000 ........a....... +40080010: 00000000 00000000 81140000 82000100 ................ +40080020: 01080000 00004000 22800000 00000600 ......@."....... +40080030: 00200800 00000000 10000100 00008000 . .............. +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test storage of the environment +variables in Flash: + +------------------------------------------------------------------------------ +=> setenv foo bar +=> saveenv +Un-Protected 1 sectors +Erasing Flash... +.. done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=> reset +... +=> printenv +bootdelay=CONFIG_BOOTDELAY +baudrate=9600 +ipaddr=192.168.4.7 +serverip=192.168.4.1 +ethaddr=66:55:44:33:22:11 +foo=bar +stdin=serial +stdout=serial +stderr=serial + +Environment size: 170/262140 bytes +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test image download and run over +Ethernet interface (both interfaces were tested): + +------------------------------------------------------------------------------ +=> tftpboot 40000 hello_world.bin +ARP broadcast 1 +TFTP from server 192.168.2.2; our IP address is 192.168.2.7 +Filename 'hello_world.bin'. +Load address: 0x40000 +Loading: ############# +done +Bytes transferred = 65912 (10178 hex) +=> go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "<NULL>" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test eeprom read/write commands: + +------------------------------------------------------------------------------ +=> md 40000 +00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x +00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x +00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! +00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L +00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... +00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. +00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... +000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... +000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... +000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L +000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L +000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! +000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. +=> eeprom write 40000 0 40 + +EEPROM write: addr 00040000 off 0000 count 64 ... done +=> mw 50000 0 1000 +=> eeprom read 50000 0 40 + +EEPROM read: addr 00050000 off 0000 count 64 ... done +=> md 50000 +00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x +00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00050040: 00000000 00000000 00000000 00000000 ................ +00050050: 00000000 00000000 00000000 00000000 ................ +00050060: 00000000 00000000 00000000 00000000 ................ +00050070: 00000000 00000000 00000000 00000000 ................ +00050080: 00000000 00000000 00000000 00000000 ................ +00050090: 00000000 00000000 00000000 00000000 ................ +000500a0: 00000000 00000000 00000000 00000000 ................ +000500b0: 00000000 00000000 00000000 00000000 ................ +000500c0: 00000000 00000000 00000000 00000000 ................ +000500d0: 00000000 00000000 00000000 00000000 ................ +000500e0: 00000000 00000000 00000000 00000000 ................ +000500f0: 00000000 00000000 00000000 00000000 ................ +=> +------------------------------------------------------------------------------ + + +Patch per Mon, 06 Aug 2001 17:57:27: + +- upgraded Flash support (added support for the following chips: + AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) +- BCR tweakage for the 8260 bus mode +- SIUMCR tweakage enabling the MI interrupt (IRQ7) + +To simplify switching between the bus modes, a new configuration +option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" +file. If it is defined, BCR will be configured for the 60x mode, +otherwise - for the 8260 mode. + +Concerning the SIUMCR modification: it's hard to predict whether it +will induce any problems on the other (60x mode) board. However, the +problems (if they appear) should be easy to notice - if the board +does not boot, it's most likely caused by the DPPC configuration in +SIUMCR. diff --git a/board/xes/xpedite1000/README b/board/xes/xpedite1000/README new file mode 100644 index 00000000000..1da8b800bec --- /dev/null +++ b/board/xes/xpedite1000/README @@ -0,0 +1,82 @@ + XES XPedite1000 Board + + Last Update: December 29, 2003 +======================================================================= + +This file contains some handy info regarding U-Boot and the XES +XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Jumpers selected for AMD29LV040B flash part as the boot flash. + + +I2C Strap EEPROM & Environment Settings +======================================= + +The XPedite1000 uses a single I2C eeprom for the 440 strappings and for +the environment variables. The first page (256 bytes) contains the +strappings and the 2 EMAC HW Ethernet addresses. Be careful not to +change the 1st page of the EEPROM! Unpopulated jumper J560 can get you +out of trouble as it disables the strapping read from EEPROM. + +I2C probe +===================== + +The i2c utilities work and have been tested on Rev B. of the 440GX. See +README.ebony for more information about i2c probing with the 440. + + +GETTING OUT OF I2C TROUBLE +=========================== + +(Direct quote from README.ebony) +If you're like me ... you may have screwed up your bootstrap serial +eeprom ... or worse, your SPD eeprom when experimenting with the +i2c commands. If so, here are some ideas on how to get out of +trouble: + +Serial bootstrap eeprom corruption: +----------------------------------- +Power down the board and set the following straps: + +J560 - closed + +This will select the default sys0 and sys1 settings (the serial +eeproms are not used). Then power up the board and fix the serial +eeprom using the 'i2c mm' command. Here are the values I currently +use: + +=> i2c md 50 0 10 + +0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B............. + +Once you have the eeproms set correctly change the +J560 straps as you desire. + + +PPC440GX Ethernet EMACs +======================= + +The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected +only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and +placed in the bd info structure for enet2addr and enet3addr. The ethernet driver +senses that enetaddr and enet1addr are 0's and does not use them. + +As of this writing gigabit ethernet and the TCPIP acceleration hardware is not +supported. + + +Flash Support +============= + +As of this writing, there is support for the 1/2mb boot flash only. User flash +is not yet supported. + + +Regards, +--Travis +<travis.sawyer@sandburst.com> diff --git a/board/zeus/README b/board/zeus/README new file mode 100644 index 00000000000..1848d8cd384 --- /dev/null +++ b/board/zeus/README @@ -0,0 +1,73 @@ + +Storage of the board specific values (ethaddr...) +------------------------------------------------- + +The board specific environment variables that should be unique +for each individual board, can be stored in the I2C EEPROM. This +will be done from offset 0x80 with the length of 0x80 bytes. The +following command can be used to store the values here: + +=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001 + + ethaddr eth1addr serial# + +Now those 3 values are stored into the I2C EEPROM. A CRC is added +to make sure that the values get not corrupted. + + +SW-Reset Pushbutton handling: +----------------------------- + +The SW-reset push button is connected to a GPIO input too. This +way U-Boot can "see" how long the SW-reset was pressed, and a +specific action can be taken. Two different actions are supported: + +a) Release after more than 5 seconds and less then 10 seconds: + -> Run POST + + Please note, that the POST test will take a while (approx. 1 min + on the 128MByte board). This is mainly due to the system memory + test. + +b) Release after more than 10 seconds: + -> Restore factory default settings + + The factory default values are restored. The default environment + variables are restored (ipaddr, serverip...) and the board + specific values (ethaddr, eth1addr and serial#) are restored + to the environment from the I2C EEPROM. Also a bootline parameter + is added to the Linux bootline to signal the Linux kernel upon + the next startup, that the factory defaults should be restored. + +The command to check this sw-reset status and act accordingly is + +=> chkreset + +This command is added to the default "bootcmd", so that it is called +automatically upon startup. + +Also, the 2 LED's are used to indicate the current status of this +command (time passed since pushing the button). When the POST test +will be run, the green LED will be switched off, and when the +factory restore will be initiated, the reg LED will be switched off. + + +Loggin of POST results: +----------------------- + +The results of the POST tests are logged in a logbuffer located at the end +of the onboard memory. It can be accessed with the U-Boot command "log": + +=> log show +<4>POST memory PASSED +<4>POST cache PASSED +<4>POST cpu PASSED +<4>POST uart PASSED +<4>POST ethernet PASSED + +The DENX Linux kernel tree has support for this log buffer included. Exactly +this buffer is used for logging of all kernel messages too. By enabling the +compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you +can access the U-Boot log messages from Linux too. + +2007-08-10, Stefan Roese <sr@denx.de> |