diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/bticino/mamoj/Kconfig | 12 | ||||
| -rw-r--r-- | board/bticino/mamoj/MAINTAINERS | 10 | ||||
| -rw-r--r-- | board/bticino/mamoj/Makefile | 8 | ||||
| -rw-r--r-- | board/bticino/mamoj/README | 124 | ||||
| -rw-r--r-- | board/bticino/mamoj/mamoj.c | 26 | ||||
| -rw-r--r-- | board/bticino/mamoj/spl.c | 171 | ||||
| -rw-r--r-- | board/engicam/imx6q/MAINTAINERS | 11 | ||||
| -rw-r--r-- | board/engicam/imx6ul/MAINTAINERS | 5 | ||||
| -rw-r--r-- | board/ge/bx50v3/Kconfig | 2 | ||||
| -rw-r--r-- | board/ge/bx50v3/bx50v3.c | 71 | ||||
| -rw-r--r-- | board/k+p/kp_imx53/Kconfig | 15 | ||||
| -rw-r--r-- | board/k+p/kp_imx53/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/k+p/kp_imx53/Makefile | 8 | ||||
| -rw-r--r-- | board/k+p/kp_imx53/kp_id_rev.c | 120 | ||||
| -rw-r--r-- | board/k+p/kp_imx53/kp_id_rev.h | 27 | ||||
| -rw-r--r-- | board/k+p/kp_imx53/kp_imx53.c | 211 |
16 files changed, 800 insertions, 27 deletions
diff --git a/board/bticino/mamoj/Kconfig b/board/bticino/mamoj/Kconfig new file mode 100644 index 0000000000..e5aec589c8 --- /dev/null +++ b/board/bticino/mamoj/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6DL_MAMOJ + +config SYS_BOARD + default "mamoj" + +config SYS_VENDOR + default "bticino" + +config SYS_CONFIG_NAME + default "imx6dl-mamoj" + +endif diff --git a/board/bticino/mamoj/MAINTAINERS b/board/bticino/mamoj/MAINTAINERS new file mode 100644 index 0000000000..c35b387a82 --- /dev/null +++ b/board/bticino/mamoj/MAINTAINERS @@ -0,0 +1,10 @@ +MX6DL_MAMOJ BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +M: Raffaele RECALCATI <raffaele.recalcati@bticino.it> +M: Simone CIANNI <simone.cianni@bticino.it> +S: Maintained +F: board/bticino/mamoj +F: include/configs/imx6dl-mamoj.h +F: configs/imx6dl_mamoj_defconfig +F: arch/arm/dts/imx6dl-mamoj.dts +F: arch/arm/dts/imx6dl-mamoj-u-boot.dtsi diff --git a/board/bticino/mamoj/Makefile b/board/bticino/mamoj/Makefile new file mode 100644 index 0000000000..f1ddda4891 --- /dev/null +++ b/board/bticino/mamoj/Makefile @@ -0,0 +1,8 @@ +# Copyright (C) 2018 BTicino +# Copyright (C) 2017 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mamoj.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/bticino/mamoj/README b/board/bticino/mamoj/README new file mode 100644 index 0000000000..5333c72537 --- /dev/null +++ b/board/bticino/mamoj/README @@ -0,0 +1,124 @@ +BTicino Mamoj board: +=================== + +Build: + + $ make mrproper + $ make imx6dl_mamoj_defconfig + $ make + + This will generate the SPL image called SPL and the u-boot-dtb.img. + +The following methods can be used for booting Mamoj boards: + +1. USB SDP boot + +2. eMMC boot (via DFU) + +3. Falcon mode + +1. USB SDP boot: +--------------- + + - Build imx_usb_loader + + $ git clone git://github.com/boundarydevices/imx_usb_loader.git + $ cd imx_usb_loader + $ make + + - Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory + + - Put the board in "Serial Download Mode" + + - Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host + + - Turn-on board + + - Identify VID/PID using lsusb + + Bus 001 Device 010: ID 15a2:0061 Freescale Semiconductor, Inc. i.MX 6Solo/6DualLite SystemOnChip in RecoveryMode + + - Update the conf files + + imx_usb.conf + 0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf + + mx6_usb_rom.conf + mx6_usb + hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000 + SPL:jump header2 + + mx6_usb_sdp_spl.conf + mx6_spl_sdp + hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000 + u-boot-dtb.img:jump header2 + + - Launch the loader + + $ ./imx_usb + + We can see U-Boot boot from USB SDP on minicom + +2. eMMC boot via DFU: +-------------------- + + Once booted from USB SDP, program the eMMC as below(make sure to connect USB OTG) + + - Change eMMC partition config + + => mmc partconf 2 1 0 0 + + - Partition eMMC on host + + => ums 0 mmc 2 + + Host will able to detect the eMMC disk as UMS, partition the same. + + - Program SPL + + => setenv dfu_alt_info $dfu_alt_info_spl + => dfu 0 mmc 2 + + At Host + + # dfu-util -D SPL -a spl + + - Program u-boot-dtb.img + + => setenv dfu_alt_info $dfu_alt_info_uboot + => dfu 0 mmc 2 + + At Host + + # dfu-util -D u-boot-dtb.img -a u-boot + + Poweroff and Poweron the board and see U-Boot booting from eMMC. + +3. Falcon mode: +-------------- + + - Skip 10M space and create dual partitions for eMMC, start sector is 20480 + + Partition Map for MMC device 2 -- Partition Type: DOS + + Part Start Sector Num Sectors UUID Type + 1 20480 131072 c52e78be-01 83 + 2 151552 7581696 c52e78be-02 83 + + - Write uImage + + => fatload mmc 2:1 $kernel_addr_r uImage + => mmc write $kernel_addr_r 0x1000 0x4000 + + - Write dtb and args + + => setenv bootargs console=ttymxc2,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw quiet + => fatload mmc 2:1 $fdt_addr_r imx6dl-mamoj.dtb + => spl export fdt $kernel_addr_r - $fdt_addr_r + => mmc write 0x13000000 0x800 0x800 + + Poweroff and Poweron the board and see Linux booting directly after SPL. + +-- +Jagan Teki <jagan@amarulasolutions.com> +03/12/18 diff --git a/board/bticino/mamoj/mamoj.c b/board/bticino/mamoj/mamoj.c new file mode 100644 index 0000000000..6ad7e31092 --- /dev/null +++ b/board/bticino/mamoj/mamoj.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it> + * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it> + * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} diff --git a/board/bticino/mamoj/spl.c b/board/bticino/mamoj/spl.c new file mode 100644 index 0000000000..c53bdce0ce --- /dev/null +++ b/board/bticino/mamoj/spl.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it> + * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it> + * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <common.h> +#include <spl.h> + +#include <asm/io.h> +#include <linux/sizes.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMX6SDL_DRIVE_STRENGTH 0x28 +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart3_pads[] = { + IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif + +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, + .dram_cas = IMX6SDL_DRIVE_STRENGTH, + .dram_ras = IMX6SDL_DRIVE_STRENGTH, + .dram_reset = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, +}; + +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6SDL_DRIVE_STRENGTH, + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, +}; + +static struct mx6_ddr3_cfg mt41k128m16jt_125 = { + .mem_speed = 1600, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + +static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { + .p0_mpwldectrl0 = 0x0042004b, + .p0_mpwldectrl1 = 0x0038003c, + .p0_mpdgctrl0 = 0x42340230, + .p0_mpdgctrl1 = 0x0228022c, + .p0_mprddlctl = 0x42444646, + .p0_mpwrdlctl = 0x38382e2e, +}; + +static struct mx6_ddr_sysinfo mem_dl = { + .dsize = 1, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .refsel = 1, + .refr = 7, +}; + +static void spl_dram_init(void) +{ + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125); + + udelay(100); +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00003f3f, &ccm->CCGR0); + writel(0x0030fc00, &ccm->CCGR1); + writel(0x000fc000, &ccm->CCGR2); + writel(0x3f300000, &ccm->CCGR3); + writel(0xff00f300, &ccm->CCGR4); + writel(0x0f0000c3, &ccm->CCGR5); + writel(0x000003cc, &ccm->CCGR6); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + SETUP_IOMUX_PADS(uart3_pads); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/board/engicam/imx6q/MAINTAINERS b/board/engicam/imx6q/MAINTAINERS index 71f794586f..6b46378c54 100644 --- a/board/engicam/imx6q/MAINTAINERS +++ b/board/engicam/imx6q/MAINTAINERS @@ -9,12 +9,21 @@ F: configs/imx6dl_icore_nand_defconfig F: configs/imx6qdl_icore_rqs_defconfig F: configs/imx6qdl_icore_mipi_defconfig F: configs/imx6qdl_icore_nand_defconfig +F: arch/arm/dts/imx6qdl.dtsi +F: arch/arm/dts/imx6qdl-u-boot.dtsi F: arch/arm/dts/imx6qdl-icore.dtsi +F: arch/arm/dts/imx6qdl-icore-u-boot.dtsi F: arch/arm/dts/imx6q-icore.dts +F: arch/arm/dts/imx6q-icore-u-boot.dtsi F: arch/arm/dts/imx6dl-icore.dts +F: arch/arm/dts/imx6dl-icore-u-boot.dtsi F: arch/arm/dts/imx6qdl-icore-rqs.dtsi +F: arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi F: arch/arm/dts/imx6q-icore-rqs.dts +F: arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi F: arch/arm/dts/imx6dl-icore-rqs.dts +F: arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi F: arch/arm/dts/imx6dl-icore-mipi.dts +F: arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi F: arch/arm/dts/imx6q-icore-mipi.dts -F: arch/arm/dts/imx6qdl-icore.dtsi +F: arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi diff --git a/board/engicam/imx6ul/MAINTAINERS b/board/engicam/imx6ul/MAINTAINERS index 73dbec88e2..88db309aec 100644 --- a/board/engicam/imx6ul/MAINTAINERS +++ b/board/engicam/imx6ul/MAINTAINERS @@ -8,7 +8,12 @@ F: configs/imx6ul_geam_nand_defconfig F: configs/imx6ul_isiot_emmc_defconfig F: configs/imx6ul_isiot_mmc_defconfig F: configs/imx6ul_isiot_nand_defconfig +F: arch/arm/dts/imx6ul.dtsi +F: arch/arm/dts/imx6ul-u-boot.dtsi F: arch/arm/dts/imx6ul-geam-kit.dts +F: arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi F: arch/arm/dts/imx6ul-isiot.dtsi +F: arch/arm/dts/imx6ul-isiot-u-boot.dtsi F: arch/arm/dts/imx6ul-isiot-emmc.dts +F: arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi F: arch/arm/dts/imx6ul-isiot-nand.dts diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig index d50dece18e..993b055930 100644 --- a/board/ge/bx50v3/Kconfig +++ b/board/ge/bx50v3/Kconfig @@ -1,4 +1,4 @@ -if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3 +if TARGET_GE_BX50V3 config IMX_CONFIG default "board/ge/bx50v3/bx50v3.cfg" diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 05142eba51..b2d065c1b8 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -33,6 +33,11 @@ #include "../../../drivers/net/e1000.h" DECLARE_GLOBAL_DATA_PTR; +struct vpd_cache; + +static int confidx = 3; /* Default to b850v3. */ +static struct vpd_cache vpd; + #ifndef CONFIG_SYS_I2C_EEPROM_ADDR # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 @@ -361,20 +366,21 @@ int board_cfb_skip(void) return 0; } -static int detect_baseboard(struct display_info_t const *dev) +static int is_b850v3(void) { - if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) || - IS_ENABLED(CONFIG_TARGET_GE_B650V3)) - return 1; + return confidx == 3; +} - return 0; +static int detect_lcd(struct display_info_t const *dev) +{ + return !is_b850v3(); } struct display_info_t const displays[] = {{ .bus = -1, .addr = -1, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_baseboard, + .detect = detect_lcd, .enable = NULL, .mode = { .name = "G121X1-L03", @@ -492,6 +498,8 @@ static void setup_display_bx50v3(void) struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + enable_videopll(); + /* When a reset/reboot is performed the display power needs to be turned * off for atleast 500ms. The boot time is ~300ms, we need to wait for * an additional 200ms here. Unfortunately we use external PMIC for @@ -593,23 +601,16 @@ static void process_vpd(struct vpd_cache *vpd) switch (vpd->product_id) { case VPD_PRODUCT_B450: env_set("confidx", "1"); + i210_index = 0; + fec_index = 1; break; case VPD_PRODUCT_B650: env_set("confidx", "2"); - break; - case VPD_PRODUCT_B850: - env_set("confidx", "3"); - break; - } - - switch (vpd->product_id) { - case VPD_PRODUCT_B450: - /* fall thru */ - case VPD_PRODUCT_B650: i210_index = 0; fec_index = 1; break; case VPD_PRODUCT_B850: + env_set("confidx", "3"); i210_index = 1; fec_index = 2; break; @@ -624,7 +625,6 @@ static void process_vpd(struct vpd_cache *vpd) static int read_vpd(uint eeprom_bus) { - struct vpd_cache vpd; int res; int size = 1024; uint8_t *data; @@ -644,7 +644,6 @@ static int read_vpd(uint eeprom_bus) if (res == 0) { memset(&vpd, 0, sizeof(vpd)); vpd_reader(size, data, &vpd, vpd_callback); - process_vpd(&vpd); } free(data); @@ -684,7 +683,7 @@ int board_early_init_f(void) setup_iomux_uart(); #if defined(CONFIG_VIDEO_IPUV3) - if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) + if (is_b850v3()) /* Set LDB clock to Video PLL */ select_ldb_di_clock_source(MXC_PLL5_CLK); else @@ -694,12 +693,35 @@ int board_early_init_f(void) return 0; } +static void set_confidx(const struct vpd_cache* vpd) +{ + switch (vpd->product_id) { + case VPD_PRODUCT_B450: + confidx = 1; + break; + case VPD_PRODUCT_B650: + confidx = 2; + break; + case VPD_PRODUCT_B850: + confidx = 3; + break; + } +} + int board_init(void) { + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); + + read_vpd(CONFIG_SYS_I2C_EEPROM_BUS); + + set_confidx(&vpd); + gpio_direction_output(SUS_S3_OUT, 1); gpio_direction_output(WIFI_EN, 1); #if defined(CONFIG_VIDEO_IPUV3) - if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) + if (is_b850v3()) setup_display_b850v3(); else setup_display_bx50v3(); @@ -710,10 +732,6 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); - return 0; } @@ -779,12 +797,15 @@ void pmic_init(void) int board_late_init(void) { - read_vpd(CONFIG_SYS_I2C_EEPROM_BUS); + process_vpd(&vpd); #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + if (is_b850v3()) + env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60"); + /* board specific pmic init */ pmic_init(); diff --git a/board/k+p/kp_imx53/Kconfig b/board/k+p/kp_imx53/Kconfig new file mode 100644 index 0000000000..017c1e30d8 --- /dev/null +++ b/board/k+p/kp_imx53/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KP_IMX53 + +config SYS_BOARD + default "kp_imx53" + +config SYS_VENDOR + default "k+p" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "kp_imx53" + +endif diff --git a/board/k+p/kp_imx53/MAINTAINERS b/board/k+p/kp_imx53/MAINTAINERS new file mode 100644 index 0000000000..c105a93e70 --- /dev/null +++ b/board/k+p/kp_imx53/MAINTAINERS @@ -0,0 +1,6 @@ +KP_IMX53_HSC BOARD +M: Lukasz Majewski <lukma@denx.de> +S: Maintained +F: board/k+p/kp_imx53/ +F: include/configs/kp_imx53.h +F: configs/kp_imx53_defconfig diff --git a/board/k+p/kp_imx53/Makefile b/board/k+p/kp_imx53/Makefile new file mode 100644 index 0000000000..66629c98ab --- /dev/null +++ b/board/k+p/kp_imx53/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2018, DENX Software Engineering +# Lukasz Majewski <lukma@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += kp_imx53.o kp_id_rev.o diff --git a/board/k+p/kp_imx53/kp_id_rev.c b/board/k+p/kp_imx53/kp_id_rev.c new file mode 100644 index 0000000000..e8f51769f6 --- /dev/null +++ b/board/k+p/kp_imx53/kp_id_rev.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Based on code developed by: + * + * Copyright (C) 2012 TQ-Systems GmbH + * Daniel Gericke <daniel.gericke@tqs.de> + */ + +#include <common.h> +#include <environment.h> +#include <i2c.h> +#include "kp_id_rev.h" + +static int eeprom_has_been_read; +static struct id_eeprom eeprom; + +void show_eeprom(void) +{ + char safe_string[33]; + int i; + u8 *p; + + puts("Module EEPROM:\n"); + /* ID */ + for (i = 0; i <= sizeof(eeprom.id) && 0xff != eeprom.id[i]; ++i) + safe_string[i] = eeprom.id[i]; + safe_string[i] = '\0'; + + if (!strncmp(safe_string, "TQM", 3)) { + printf(" ID: %s\n", safe_string); + env_set("boardtype", safe_string); + } else { + puts(" unknown hardware variant\n"); + } + + /* Serial number */ + for (i = 0; (sizeof(eeprom.serial) >= i) && + (eeprom.serial[i] >= 0x30) && + (eeprom.serial[i] <= 0x39); ++i) + safe_string[i] = eeprom.serial[i]; + safe_string[i] = '\0'; + + if (strlen(safe_string) == 8) { + printf(" SN: %s\n", safe_string); + env_set("serial#", safe_string); + } else { + puts(" unknown serial number\n"); + } + + /* MAC address */ + p = eeprom.mac; + if (!is_valid_ethaddr(p)) { + printf(" Not valid ETH EEPROM addr!\n"); + return; + } + + printf(" MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + p[0], p[1], p[2], p[3], p[4], p[5]); + + eth_env_set_enetaddr("ethaddr", p); +} + +int read_eeprom(void) +{ + struct udevice *dev; + int ret; + + if (eeprom_has_been_read) + return 0; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("Cannot find EEPROM !\n"); + return ret; + } + + ret = dm_i2c_read(dev, 0x0, (uchar *)&eeprom, sizeof(eeprom)); + + eeprom_has_been_read = (ret == 0) ? 1 : 0; + return ret; +} + +int read_board_id(void) +{ + unsigned char rev_id = 0x42; + char rev_str[32], buf[8]; + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(2, 0x22, 1, &dev); + if (ret) { + printf("Cannot find pcf8574 IO expander !\n"); + return ret; + } + + dm_i2c_read(dev, 0x0, &rev_id, sizeof(rev_id)); + + sprintf(rev_str, "%02X", rev_id); + if (rev_id & 0x80) { + printf("BBoard:4x00 Rev:%s\n", rev_str); + env_set("boardtype", "ddc"); + env_set("fit_config", "imx53_kb_conf"); + } else { + printf("BBoard:40x0 Rev:%s\n", rev_str); + env_set("boardtype", "hsc"); + env_set("fit_config", "imx53_kb_40x0_conf"); + } + + sprintf(buf, "kp-%s", env_get("boardtype")); + env_set("boardname", buf); + env_set("boardsoc", "imx53"); + env_set("kb53_rev", rev_str); + + return 0; +} diff --git a/board/k+p/kp_imx53/kp_id_rev.h b/board/k+p/kp_imx53/kp_id_rev.h new file mode 100644 index 0000000000..aa64173926 --- /dev/null +++ b/board/k+p/kp_imx53/kp_id_rev.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * Based on code developed by: + * + * Copyright (C) 2012 TQ-Systems GmbH + * Daniel Gericke <daniel.gericke@tqs.de> + */ + +#ifndef __KP_ID_REV_H_ +#define __KP_ID_REV_H_ + +struct id_eeprom { + u8 hrcw_primary[0x20]; + u8 mac[6]; /* 0x20 ... 0x25 */ + u8 rsv1[10]; + u8 serial[8]; /* 0x30 ... 0x37 */ + u8 rsv2[8]; + u8 id[0x40]; /* 0x40 ... 0x7f */ +} __packed; + +void show_eeprom(void); +int read_eeprom(void); +int read_board_id(void); +#endif /* __KP_ID_REV_H_ */ diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c new file mode 100644 index 0000000000..c80eed36c6 --- /dev/null +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/arch/clock.h> +#include <asm/gpio.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <power/pmic.h> +#include <fsl_pmic.h> +#include "kp_id_rev.h" + +#define VBUS_PWR_EN IMX_GPIO_NR(7, 8) +#define PHY_nRST IMX_GPIO_NR(7, 6) +#define BOOSTER_OFF IMX_GPIO_NR(2, 23) + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + u32 size; + + size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + gd->ram_size = size; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN"); + gpio_direction_output(VBUS_PWR_EN, 1); + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[] = { + {MMC_SDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* eMMC is always present */ +} + +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_DSE_HIGH) + +int board_mmc_init(bd_t *bis) +{ + int ret; + + static const iomux_v3_cfg_t sd3_pads[] = { + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), + }; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + if (ret) + return ret; + + return 0; +} +#endif + +static int power_init(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("mc34708", &dev); + if (ret) { + printf("%s: mc34708 not found !\n", __func__); + return ret; + } + + /* Set VDDGP to 1.110V for 800 MHz on SW1 */ + pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708, + SWx_1_110V_MC34708); + + /* Set VCC as 1.30V on SW2 */ + pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708, + SWx_1_300V_MC34708); + + /* Set global reset timer to 4s */ + pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708, + TIMER_4S_MC34708); + + return ret; +} + +static void setup_clocks(void) +{ + int ret; + u32 ref_clk = MXC_HCLK; + /* + * CPU clock set to 800MHz and DDR to 400MHz + */ + ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 800MHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + +static void setup_ups(void) +{ + gpio_request(BOOSTER_OFF, "BOOSTER_OFF"); + gpio_direction_output(BOOSTER_OFF, 0); +} + +int board_early_init_f(void) +{ + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +void eth_phy_reset(void) +{ + gpio_request(PHY_nRST, "PHY_nRST"); + gpio_direction_output(PHY_nRST, 1); + udelay(50); + gpio_set_value(PHY_nRST, 0); + udelay(400); + gpio_set_value(PHY_nRST, 1); + udelay(50); +} + +int board_late_init(void) +{ + int ret = 0; + + setup_ups(); + + if (!power_init()) + setup_clocks(); + + ret = read_eeprom(); + if (ret) + printf("Error %d reading EEPROM content!\n", ret); + + eth_phy_reset(); + + show_eeprom(); + read_board_id(); + + return ret; +} |