diff options
Diffstat (limited to 'board')
-rw-r--r-- | board/amcc/sequoia/cmd_sequoia.c | 205 | ||||
-rw-r--r-- | board/esd/common/auto_update.c | 4 | ||||
-rw-r--r-- | board/freescale/common/pq-mds-pib.c | 102 | ||||
-rw-r--r-- | board/freescale/common/pq-mds-pib.h | 9 | ||||
-rw-r--r-- | board/freescale/mpc8313erdb/Makefile (renamed from board/mpc8313erdb/Makefile) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8313erdb/config.mk (renamed from board/mpc8313erdb/config.mk) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8313erdb/mpc8313erdb.c (renamed from board/mpc8313erdb/mpc8313erdb.c) | 19 | ||||
-rw-r--r-- | board/freescale/mpc8313erdb/sdram.c (renamed from board/mpc8313erdb/sdram.c) | 3 | ||||
-rw-r--r-- | board/freescale/mpc8323erdb/mpc8323erdb.c | 37 | ||||
-rw-r--r-- | board/freescale/mpc832xemds/Makefile (renamed from board/mpc8349emds/Makefile) | 2 | ||||
-rw-r--r-- | board/freescale/mpc832xemds/config.mk (renamed from board/mpc832xemds/config.mk) | 0 | ||||
-rw-r--r-- | board/freescale/mpc832xemds/mpc832xemds.c (renamed from board/mpc832xemds/mpc832xemds.c) | 31 | ||||
-rw-r--r-- | board/freescale/mpc832xemds/pci.c (renamed from board/mpc832xemds/pci.c) | 64 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/Makefile (renamed from board/mpc832xemds/Makefile) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/config.mk (renamed from board/mpc8349emds/config.mk) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/mpc8349emds.c (renamed from board/mpc8349emds/mpc8349emds.c) | 26 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/pci.c (renamed from board/mpc8349emds/pci.c) | 41 | ||||
-rw-r--r-- | board/freescale/mpc8349itx/Makefile (renamed from board/mpc8349itx/Makefile) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8349itx/config.mk (renamed from board/mpc8349itx/config.mk) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8349itx/mpc8349itx.c (renamed from board/mpc8349itx/mpc8349itx.c) | 21 | ||||
-rw-r--r-- | board/freescale/mpc8349itx/pci.c (renamed from board/mpc8349itx/pci.c) | 39 | ||||
-rw-r--r-- | board/freescale/mpc8360emds/Makefile (renamed from board/mpc8360emds/Makefile) | 2 | ||||
-rw-r--r-- | board/freescale/mpc8360emds/config.mk (renamed from board/mpc8360emds/config.mk) | 0 | ||||
-rw-r--r-- | board/freescale/mpc8360emds/mpc8360emds.c (renamed from board/mpc8360emds/mpc8360emds.c) | 50 | ||||
-rw-r--r-- | board/freescale/mpc8360emds/pci.c (renamed from board/mpc8360emds/pci.c) | 48 | ||||
-rw-r--r-- | board/lwmon5/sdram.c | 2 | ||||
-rw-r--r-- | board/netstal/common/hcu_flash.c (renamed from board/netstal/common/flash.c) | 0 | ||||
-rw-r--r-- | board/netstal/hcu4/Makefile | 14 | ||||
-rw-r--r-- | board/netstal/hcu4/hcu4.c | 20 | ||||
-rw-r--r-- | board/netstal/hcu5/Makefile | 14 | ||||
-rw-r--r-- | board/netstal/hcu5/hcu5.c | 69 | ||||
-rw-r--r-- | board/netstal/hcu5/sdram.c | 17 | ||||
-rw-r--r-- | board/sbc8349/sbc8349.c | 5 | ||||
-rw-r--r-- | board/tqm834x/tqm834x.c | 4 |
34 files changed, 552 insertions, 296 deletions
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index 6fc60eaaa2f..f3803c09f89 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -26,76 +26,185 @@ #include <command.h> #include <i2c.h> -static u8 boot_533_nor[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 -}; +/* + * There are 2 versions of production Sequoia & Rainier platforms. + * The primary difference is the reference clock. Those with + * 33333333 reference clocks will also have 667MHz rated + * processors. Not enough differences to have unique clock + * settings. + * + * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The + * values are independent of the rest of the clock settings. + * + * All Sequoias & Rainiers select from two possible EEPROMs in Boot + * Config F. One for 33MHz PCI, one for 66MHz PCI. The following + * values are for the 33MHz PCI configuration. Byte 5 (0 base) is + * the only value affected for a 66MHz PCI and simply needs a +0x10. + */ + +#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02 + +/* check with Stefan on CFG_I2C_EEPROM_ADDR */ +#define I2C_EEPROM_ADDR 0x52 -static u8 boot_533_nand[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +static char *config_labels[] = { + "CPU: 333 PLB: 133 OPB: 66 EBC: 66", + "CPU: 333 PLB: 166 OPB: 83 EBC: 55", + "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + "CPU: 400 PLB: 160 OPB: 80 EBC: 53", + "CPU: 416 PLB: 166 OPB: 83 EBC: 55", + "CPU: 500 PLB: 166 OPB: 83 EBC: 55", + "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 166 OPB: 83 EBC: 55", + NULL }; -static u8 boot_667_nor[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 +static u8 boot_configs[][17] = { + { + (NOR_COMPATIBLE), + 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } }; -static u8 boot_667_nand[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +/* + * Bytes 6,8,9,11 change for NAND boot + */ +static u8 nand_boot[] = { + 0xd0, 0xa0, 0x68, 0x58 }; static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u8 chip; - u8 *buf; - int cpu_freq; + u8 *buf, bNAND; + int x, y, nbytes, selcfg; + extern char console_buffer[]; - if (argc < 3) { + if (argc < 2) { printf("Usage:\n%s\n", cmdtp->usage); return 1; } - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (!((cpu_freq == 533) || (cpu_freq == 667))) { - printf("Unsupported cpu-frequency - only 533 and 667 supported\n"); + if ((strcmp(argv[1], "nor") != 0) && + (strcmp(argv[1], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); return 1; } - /* use 0x52 as I2C EEPROM address for now */ - chip = 0x52; + /* set the nand flag based on provided input */ + if ((strcmp(argv[1], "nand") == 0)) + bNAND = 1; + else + bNAND = 0; - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { - printf("Unsupported boot-device - only nor|nand support\n"); - return 1; - } + printf("Available configurations: \n\n"); - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nand; - break; - case 667: - buf = boot_667_nand; - break; + if (bNAND) { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nand compatible */ + if (boot_configs[x][0] & NAND_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } else { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nor; - break; - case 667: - buf = boot_667_nor; - break; + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nor compatible */ + if (boot_configs[x][0] & NOR_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); + do { + nbytes = readline(" Selection [1-x / quit]: "); + + if (nbytes) { + if (strcmp(console_buffer, "quit") == 0) + return 0; + selcfg = simple_strtol(console_buffer, NULL, 10); + if ((selcfg < 1) || (selcfg > y)) + nbytes = 0; + } + } while (nbytes == 0); + + + y = (selcfg - 1); + + for (x = 0; boot_configs[x][0] != 0; x++) { + if (bNAND) { + if (boot_configs[x][0] & NAND_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } else { + if (boot_configs[x][0] & NOR_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } + } + + buf = &boot_configs[x][1]; + + if (bNAND) { + buf[6] = nand_boot[0]; + buf[8] = nand_boot[1]; + buf[9] = nand_boot[2]; + buf[11] = nand_boot[3]; + } + + /* check CPLD register +5 for PCI 66MHz flag */ + if (in8(CFG_BCSR_BASE + 5) & 0x01) + buf[5] += 0x10; + + if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); printf("Done\n"); @@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, + bootstrap, 2, 0, do_bootstrap, "bootstrap - program the I2C bootstrap EEPROM\n", - "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n" + "<nand|nor> - strap to boot from NAND or NOR flash\n" ); diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index da147ee5508..a76b00fe494 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -24,10 +24,6 @@ #include <common.h> -#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) -#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! -#endif - #include <command.h> #include <image.h> #include <asm/byteorder.h> diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c new file mode 100644 index 00000000000..8c013c72fb7 --- /dev/null +++ b/board/freescale/common/pq-mds-pib.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Tony Li <tony.li@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> + +#include "pq-mds-pib.h" + +int pib_init(void) +{ + u8 val8; + u8 orig_i2c_bus; + + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0; +#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) + /* Assign PIB PMC slot to desired PCI bus */ + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(CONFIG_MPC832XEMDS) + val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ +#else + val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + eieio(); + +#if defined(CONFIG_MPC832XEMDS) + printf("PCI 32bit bus on PMC2 &PMC3\n"); +#else + printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); +#endif +#endif + +#if defined(CONFIG_PQ_MDS_PIB_ATM) +#if defined(CONFIG_MPC8360EMDS) + val8 = 0; + i2c_write(0x20, 0x6, 1, &val8, 1); + i2c_write(0x20, 0x7, 1, &val8, 1); + + val8 = 0xdf; + i2c_write(0x20, 0x2, 1, &val8, 1); + val8 = 0xf7; + i2c_write(0x20, 0x3, 1, &val8, 1); + + eieio(); + + printf("QOC3 ATM card on PMC0\n"); +#elif defined(CONFIG_MPC832XEMDS) + val = 0; + i2c_write(0x26, 0x7, 1, &val, 1); + val = 0xf7; + i2c_write(0x26, 0x3, 1, &val, 1); + + val = 0; + i2c_write(0x21, 0x6, 1, &val, 1); + i2c_write(0x21, 0x7, 1, &val, 1); + + val = 0xdf; + i2c_write(0x21, 0x2, 1, &val, 1); + val = 0xef; + i2c_write(0x21, 0x3, 1, &val, 1); + + eieio(); + + printf("QOC3 ATM card on PMC1\n"); +#endif +#endif + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); + return 0; +} diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h new file mode 100644 index 00000000000..67066fd118d --- /dev/null +++ b/board/freescale/common/pq-mds-pib.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +extern int pib_init(void); diff --git a/board/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile index a987e510dd2..a987e510dd2 100644 --- a/board/mpc8313erdb/Makefile +++ b/board/freescale/mpc8313erdb/Makefile diff --git a/board/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk index f76826495ef..f76826495ef 100644 --- a/board/mpc8313erdb/config.mk +++ b/board/freescale/mpc8313erdb/config.mk diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 999fe9e39bb..861c143df57 100644 --- a/board/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -23,7 +23,11 @@ */ #include <common.h> +#if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif #include <pci.h> #include <mpc83xx.h> @@ -96,21 +100,22 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p) { + if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 4b6778837f2..e6e84107eb2 100644 --- a/board/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -112,8 +112,6 @@ long int initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ msize = fixed_sdram(); @@ -127,7 +125,6 @@ long int initdram(int board_type) resume_from_sleep(); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize; } diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 1886f196b27..e7386130098 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -17,7 +17,6 @@ #include <miiphy.h> #include <command.h> #include <libfdt.h> -#include <libfdt_env.h> #if defined(CONFIG_PCI) #include <pci.h> #endif @@ -92,8 +91,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -185,33 +182,21 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); } - +#endif ft_cpu_setup(blob, bd); - #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } -#endif /* CONFIG_OF_BOARD_SETUP */ +#endif diff --git a/board/mpc8349emds/Makefile b/board/freescale/mpc832xemds/Makefile index 5ec7a871d4d..ea52484c063 100644 --- a/board/mpc8349emds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc832xemds/config.mk b/board/freescale/mpc832xemds/config.mk index 6c3eca75341..6c3eca75341 100644 --- a/board/mpc832xemds/config.mk +++ b/board/freescale/mpc832xemds/config.mk diff --git a/board/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 772da678f00..6ba25d4644c 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -29,6 +29,11 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -86,6 +91,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + int fixed_sdram(void); long int initdram(int board_type) @@ -101,8 +114,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -155,22 +166,22 @@ int checkboard(void) return 0; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index d0a407ae8aa..6bc35c70f2d 100644 --- a/board/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -20,6 +20,8 @@ #include <i2c.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif #include <asm/fsl_i2c.h> @@ -129,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -198,43 +199,6 @@ void pci_init_board(void) PIWAR_IWS_2G; /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - - /* * Release PCI RST Output signal */ udelay(2000); @@ -290,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC2 & PMC3\n"); - /* * Hose scan. */ @@ -299,7 +261,27 @@ void pci_init_board(void) } #endif /* CONFIG_PCISLAVE */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc832xemds/Makefile b/board/freescale/mpc8349emds/Makefile index 5ec7a871d4d..5ec7a871d4d 100644 --- a/board/mpc832xemds/Makefile +++ b/board/freescale/mpc8349emds/Makefile diff --git a/board/mpc8349emds/config.mk b/board/freescale/mpc8349emds/config.mk index edf64d1508a..edf64d1508a 100644 --- a/board/mpc8349emds/config.mk +++ b/board/freescale/mpc8349emds/config.mk diff --git a/board/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 521d1bbd4ed..39c09162760 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -34,6 +34,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif int fixed_sdram(void); @@ -68,8 +70,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -88,7 +88,7 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -189,9 +189,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc= &immap->lbus; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -253,26 +250,25 @@ void sdram_init(void) #else void sdram_init(void) { - puts(" SDRAM on Local Bus is NOT available!\n"); } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index d6a12b82a49..ae94a2f384f 100644 --- a/board/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -25,6 +25,12 @@ #include <pci.h> #include <asm/mpc8349_pci.h> #include <i2c.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -382,7 +388,40 @@ pci_init_board(void) } -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index 31bcdb8642a..31bcdb8642a 100644 --- a/board/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile diff --git a/board/mpc8349itx/config.mk b/board/freescale/mpc8349itx/config.mk index 79f1765fa1b..79f1765fa1b 100644 --- a/board/mpc8349itx/config.mk +++ b/board/freescale/mpc8349itx/config.mk diff --git a/board/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 178b1d36fbf..c82f7847a22 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -39,6 +39,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif #ifndef CONFIG_SPD_EEPROM @@ -74,7 +76,7 @@ int fixed_sdram(void) im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; im->ddr.sdram_mode = (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); im->ddr.sdram_interval = @@ -160,7 +162,6 @@ long int initdram(int board_type) ddr_enable_ecc(msize * 1048576); #endif - puts(" DDR RAM: "); /* return total bus RAM size(bytes) */ return msize * 1024 * 1024; } @@ -385,22 +386,22 @@ int misc_init_r(void) return rc; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index e81ad273568..5ca094d4cbc 100644 --- a/board/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -31,6 +31,8 @@ #include <i2c.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#elif defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -332,8 +334,40 @@ void pci_init_board(void) #endif } -#endif /* CONFIG_PCI */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { @@ -355,3 +389,4 @@ ft_pci_setup(void *blob, bd_t *bd) #endif } #endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index 5ec7a871d4d..ea52484c063 100644 --- a/board/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8360emds/config.mk b/board/freescale/mpc8360emds/config.mk index 9ace8860cfd..9ace8860cfd 100644 --- a/board/mpc8360emds/config.mk +++ b/board/freescale/mpc8360emds/config.mk diff --git a/board/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 3fa093d1d55..e050cd4395a 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -29,7 +29,9 @@ #include <ft_build.h> #elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <libfdt_env.h> +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -107,6 +109,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -139,7 +149,7 @@ long int initdram(int board_type) * Initialize SDRAM if it is on local bus. */ sdram_init(); - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -224,8 +234,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc = &immap->lbus; uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -281,36 +289,13 @@ void sdram_init(void) #else void sdram_init(void) { - puts("SDRAM on Local Bus is NOT available!\n"); } #endif -#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ - && defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_LIBFDT) - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } -#else +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; @@ -320,10 +305,9 @@ ft_board_setup(void *blob, bd_t *bd) *p = cpu_to_be32(bd->bi_memsize); } #endif - + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif - ft_cpu_setup(blob, bd); } -#endif /* CONFIG_OF_x */ +#endif diff --git a/board/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 8f904710ca8..cf7ef90443f 100644 --- a/board/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -22,7 +22,6 @@ #include <ft_build.h> #elif defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#include <libfdt_env.h> #endif #include <asm/fsl_i2c.h> @@ -132,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -201,43 +199,6 @@ void pci_init_board(void) PIWAR_IWS_2G; /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - - /* * Release PCI RST Output signal */ udelay(2000); @@ -293,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); - /* * Hose scan. */ @@ -314,7 +273,12 @@ ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } } #elif defined(CONFIG_OF_FLAT_TREE) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index f906b859a31..d4547e24cf1 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -57,7 +57,6 @@ void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); -#ifdef CONFIG_ADD_RAM_INFO static u32 is_ecc_enabled(void) { u32 val; @@ -87,7 +86,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif static int wait_for_dlllock(void) { diff --git a/board/netstal/common/flash.c b/board/netstal/common/hcu_flash.c index be2cb377347..be2cb377347 100644 --- a/board/netstal/common/flash.c +++ b/board/netstal/common/hcu_flash.c diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index d9825a5f255..af90821faae 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 2b9560484d7..48a3f13bad7 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -43,7 +43,7 @@ enum { HW_GENERATION_MCU25 = 0x09, }; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); long int spd_sdram(int(read_spd)(uint addr)); #ifdef CONFIG_SPD_EEPROM @@ -121,22 +121,24 @@ int checkboard (void) printf ("HCU3: index %d\n\n", index); else if (generation == HW_GENERATION_HCU4) printf ("HCU4: index %d\n\n", index); - /* GPIO here noch nicht richtig initialisert !!! */ - sysLedSet(0); + hcu_led_set(0); for (j = 0; j < 7; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(50 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { u32 tmp = ~value; u32 *ledReg; @@ -243,9 +245,9 @@ long int fixed_hcu4_sdram (int board_type) } /*---------------------------------------------------------------------------+ - * getSerialNr + * hcu_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 hcu_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; @@ -265,7 +267,7 @@ int misc_init_r(void) char *s = getenv("ethaddr"); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = hcu_serial_number(); for (i = 0; i < 6; ++i) { gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index eee310b1a14..27398b905b6 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o sdram.o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o sdram.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 23df0814ff5..b9b10fdc29a 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,10 +22,11 @@ #include <asm/processor.h> #include <ppc440.h> #include <asm/mmu.h> +#include <net.h> DECLARE_GLOBAL_DATA_PTR; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; @@ -41,7 +42,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083 -#define SYS_IO_ADDRESS 0xcce00000 +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) +#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) #define DEFAULT_ETH_ADDR "ethaddr" /* ethaddr for first or etha1ddr for second ethernet */ @@ -182,11 +184,14 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_BOARD_PRE_INIT int board_pre_init(void) { return board_early_init_f(); } +#endif + int checkboard(void) { unsigned int j; @@ -211,38 +216,51 @@ int checkboard(void) printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); for (j = 0;j < 6; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(200 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return in16(SYS_IO_ADDRESS) & 0x3f; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { out16(SYS_IO_ADDRESS, value); } /*---------------------------------------------------------------------------+ - * getSerialNr + * get_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 get_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; if (*serial == 0xffffffff) - return get_ticks(); + return 0; return *serial; } /*---------------------------------------------------------------------------+ + * hcu_get_slot + *---------------------------------------------------------------------------*/ +u32 hcu_get_slot(void) +{ + u16 *slot = (u16 *)SYS_SLOT_ADDRESS; + return (*slot) & 0x7f; +} + + +/*---------------------------------------------------------------------------+ * misc_init_r. *---------------------------------------------------------------------------*/ int misc_init_r(void) @@ -250,7 +268,7 @@ int misc_init_r(void) char *s = getenv(DEFAULT_ETH_ADDR); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = get_serial_number(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; @@ -272,8 +290,7 @@ int misc_init_r(void) gd->bd->bi_enetaddr[2] = 0x13; gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; - /* byte[5].bit 0 must be zero */ - gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + gd->bd->bi_enetaddr[5] = hcu_get_slot(); sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], @@ -283,6 +300,25 @@ int misc_init_r(void) setenv(DEFAULT_ETH_ADDR, ethaddr); } + /* IP-Adress update */ + { + IPaddr_t ipaddr; + char *ipstring; + + ipstring = getenv("ipaddr"); + if (ipstring == 0) + ipaddr = string_to_ip("172.25.1.99"); + else + ipaddr = string_to_ip(ipstring); + if ((ipaddr & 0xff) != (32 + hcu_get_slot())) { + char tmp[22]; + + ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot(); + ip_to_string (ipaddr, tmp); + printf("%s: enforce %s\n", __FUNCTION__, tmp); + setenv("ipaddr", tmp); + } + } #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -346,6 +382,7 @@ int misc_init_r(void) return 0; } +#if defined(CONFIG_PCI) /************************************************************************* * pci_pre_init * @@ -358,7 +395,6 @@ int misc_init_r(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -411,7 +447,6 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -421,7 +456,6 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*-------------------------------------------------------------+ @@ -478,13 +512,11 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -499,8 +531,6 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif -/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -517,9 +547,8 @@ void pci_master_init(struct pci_controller *hose) * * ************************************************************************/ -#if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */ diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 40391958d21..9ee9ab599b6 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,7 +36,7 @@ #include <asm/mmu.h> #include <ppc440.h> -void sysLedSet(u32 value); +void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); @@ -70,7 +70,6 @@ void dflush(void); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -#ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { PPC440_SYS_INFO board_cfg; @@ -99,7 +98,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif /*-------------------------------------------------------------------- * wait_for_dlllock. @@ -138,7 +136,7 @@ static int wait_for_dlllock(void) void sdram_panic(const char *reason) { printf("\n%s: reason %s", __FUNCTION__, reason); - sysLedSet(0xff); + hcu_led_set(0xff); while (1) { } /* Never return */ @@ -197,6 +195,13 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes, mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* + * Clear possible errors + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + mtspr(mcsr, mfspr(mcsr)); + /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | @@ -244,7 +249,6 @@ long int initdram (int board_type) sdram_panic(INVALID_HW_CONFIG); break; } - dram_size -= 16 * 1024 * 1024; mtsdram(DDR0_07, 0x00090100); /* * TCPD=200 cycles of clock input is required to lock the DLL. @@ -283,6 +287,7 @@ long int initdram (int board_type) /* * Program tlb entries for this size (dynamic) */ + remove_tlb(CFG_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); /* @@ -291,6 +296,8 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + /* Diminish RAM to initialize */ + dram_size = dram_size - 32 ; #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 4cd447e097f..86166ea4439 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -64,8 +64,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -84,7 +82,6 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -130,7 +127,7 @@ int fixed_sdram(void) #if defined(CONFIG_DDR_2T_TIMING) | SDRAM_CFG_2T_EN #endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + | SDRAM_CFG_SDRAM_TYPE_DDR1; #if defined (CONFIG_DDR_32BIT) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 9c35e22c8e1..7d0b0554840 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -114,7 +114,7 @@ long int initdram (int board_type) /* enable DDR controller */ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR); + SDRAM_CFG_SDRAM_TYPE_DDR1); SYNC; /* size detection */ @@ -388,7 +388,7 @@ static void set_ddr_config(void) { /* don't enable DDR controller yet */ im->ddr.sdram_cfg = SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR; + SDRAM_CFG_SDRAM_TYPE_DDR1; SYNC; /* Set SDRAM mode */ |