diff options
Diffstat (limited to 'board')
137 files changed, 2657 insertions, 5121 deletions
diff --git a/board/8dtech/eco5pk/Kconfig b/board/8dtech/eco5pk/Kconfig deleted file mode 100644 index 55535669fae..00000000000 --- a/board/8dtech/eco5pk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ECO5PK - -config SYS_BOARD - default "eco5pk" - -config SYS_VENDOR - default "8dtech" - -config SYS_CONFIG_NAME - default "eco5pk" - -endif diff --git a/board/8dtech/eco5pk/MAINTAINERS b/board/8dtech/eco5pk/MAINTAINERS deleted file mode 100644 index 20c1c8c87e2..00000000000 --- a/board/8dtech/eco5pk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ECO5PK BOARD -M: Raphael Assenat <raph@8d.com> -S: Maintained -F: board/8dtech/eco5pk/ -F: include/configs/eco5pk.h -F: configs/eco5pk_defconfig diff --git a/board/8dtech/eco5pk/Makefile b/board/8dtech/eco5pk/Makefile deleted file mode 100644 index 114fe1b2156..00000000000 --- a/board/8dtech/eco5pk/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Adapted from ti/evm/Makefile - -obj-y := eco5pk.o diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c deleted file mode 100644 index dcbd4835b39..00000000000 --- a/board/8dtech/eco5pk/eco5pk.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board - * - * Based on am3517evm.c - * - * Copyright (C) 2011-2012 8D Technologies inc. - * Copyright (C) 2009 Texas Instruments Incorporated - */ -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/emac_defs.h> -#include <asm/gpio.h> -#include <i2c.h> -#include <u-boot/crc.h> -#include <asm/mach-types.h> -#include "eco5pk.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - gpio_request(30, "RESOUT"); - gpio_direction_output(30, 1); - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_ECO5_PK(); -} diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h deleted file mode 100644 index 7c8fcb0be37..00000000000 --- a/board/8dtech/eco5pk/eco5pk.h +++ /dev/null @@ -1,391 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * eco5.h - Header file for the 8D Technologies ECO5 board. - * - * Based on am3517evm.h - * Based on ti/evm/evm.h - * - * Copyright (C) 2011 8D Technologies inc. - * Copyright (C) 2009 Texas Instruments Incorporated - */ - -#ifndef _ECO5PK_H__ -#define _ECO5PK_H__ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "ECO5 Board", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_ECO5_PK() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (M0)) \ - MUX_VAL(CP(SDRC_CKE1), (M0)) \ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ - /* - ETH_nRESET*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - /* - CAM_RESET*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ - /* MMC */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \ - \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ - /* - LCD_INI*/\ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ - /* - LCD_ENVDD */\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ - /* - LCD_QVGA/nVGA */\ - MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ - /* - LCD_RESB */\ - /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ - \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ - /* - LAN_INTR*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ - \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ - /* LCD_EN_BACKLIGHT */\ - MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ - /* Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ - /* SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ - /* - GPIO30 */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ - /* - PEN_IRQ */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\ - /* - VIO_1V8*/\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ - \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ - /* JTAG */\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ - /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ - /* Die to Die */\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) - -#endif diff --git a/board/Barix/ipam390/Kconfig b/board/Barix/ipam390/Kconfig deleted file mode 100644 index b85d4da44b0..00000000000 --- a/board/Barix/ipam390/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IPAM390 - -config SYS_BOARD - default "ipam390" - -config SYS_VENDOR - default "Barix" - -config SYS_CONFIG_NAME - default "ipam390" - -endif diff --git a/board/Barix/ipam390/MAINTAINERS b/board/Barix/ipam390/MAINTAINERS deleted file mode 100644 index 640e34fc8da..00000000000 --- a/board/Barix/ipam390/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IPAM390 BOARD -M: Heiko Schocher <hs@denx.de> -S: Maintained -F: board/Barix/ipam390/ -F: include/configs/ipam390.h -F: configs/ipam390_defconfig diff --git a/board/Barix/ipam390/Makefile b/board/Barix/ipam390/Makefile deleted file mode 100644 index 735250a1e21..00000000000 --- a/board/Barix/ipam390/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - -obj-y += ipam390.o diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390 deleted file mode 100644 index be09280dd81..00000000000 --- a/board/Barix/ipam390/README.ipam390 +++ /dev/null @@ -1,229 +0,0 @@ -Summary -======= -The README is for the boot procedure on the ipam390 board - -In the context of U-Boot, the board is booted in three stages. The initial -bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits -in the internal ROM. The RBL initializes the internal memory and then -depending on the exact board and pin configurations will initialize another -controller (such as NAND) to continue the boot process by loading -the secondary program loader (SPL). The SPL will initialize the system -further (some clocks, SDRAM). As on this board is used the falcon boot -mode, now 2 ways are possible depending on the GPIO 7_14 input pin, -connected with the "soft reset switch" - -If this pin is logical 1 (high level): -spl code starts the kernel image without delay - -If this pin is logical 0 (low level): -spl code starts the u-boot image - -AIS is an image format defined by TI for the images that are to be loaded -to memory by the RBL. The image is divided into a series of sections and -the image's entry point is specified. Each section comes with meta data -like the target address the section is to be copied to and the size of the -section, which is used by the RBL to load the image. At the end of the -image the RBL jumps to the image entry point. The AIS format allows for -other things such as programming the clocks and SDRAM if the header is -programmed for it. We do not take advantage of this and instead use SPL as -it allows for additional flexibility (run-time detect of board revision, -loading the next image from a different media, etc). - -Compilation -=========== -run "tools/buildman/buildman -k ipam390" in the u-boot source tree. -Once this build completes you will have a ../current/ipam390/u-boot.ais file -that needs to be written to the nand flash. - -Flashing the images to NAND -========================== -The AIS image can be written to NAND flash using the following commands. -Assuming that the network is configured and enabled and the u-boot.ais file -is tftp'able. - -U-Boot > print upd_uboot -upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize} -U-Boot > -U-Boot > run upd_uboot -Using DaVinci-EMAC device -TFTP from server 192.168.1.1; our IP address is 192.168.20.71 -Filename '/tftpboot/ipam390/u-boot.ais'. -Load address: 0xc0000000 -Loading: ################################## - 1.5 MiB/s -done -Bytes transferred = 493716 (78894 hex) - -NAND erase.part: device 0 offset 0x20000, size 0x160000 -Erasing at 0x160000 -- 100% complete. -OK - -NAND write: device 0 offset 0x20000, size 0x78894 - 493716 bytes written: OK -U-Boot > - -Recovery -======== - -In the case of a "bricked" board, you need to use the TI tools found -here[1] to create an uboot-uart-ais.bin file - -- cd to the u-boot source tree - -- compile the u-boot for the ipam390 board: -$ tools/buildman/buildman -k ipam390 - - -> Now we shall have u-boot.bin - -- Create u-boot-uart-ais.bin -$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini ipam390-ais-uart.cfg \ - -o ../current/ipam390/uboot-uart-ais.bin ./u-boot.bin@0xC1080000; - -Note: The ipam390-ais-uart.cfg is found in the board directory -for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg - -- We can now run bootloader on IPAM390 via UART using the command below: - -$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin -NOTE: Do not cancel the command execution! The command takes 20+ seconds -to upload u-boot over serial and run it! -Outcome: -Waiting for the OMAP-L138... -(AIS Parse): Read magic word 0x41504954. -(AIS Parse): Waiting for BOOTME... (power on or reset target now) -(AIS Parse): BOOTME received! -(AIS Parse): Performing Start-Word Sync... -(AIS Parse): Performing Ping Opcode Sync... -(AIS Parse): Processing command 0: 0x5853590D. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Executing function... -(AIS Parse): Processing command 1: 0x5853590D. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Executing function... -(AIS Parse): Processing command 2: 0x5853590D. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Executing function... -(AIS Parse): Processing command 3: 0x5853590D. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Executing function... -(AIS Parse): Processing command 4: 0x5853590D. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Executing function... -(AIS Parse): Processing command 5: 0x58535901. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Loading section... -(AIS Parse): Loaded 326516-Byte section to address 0xC1080000. -(AIS Parse): Processing command 6: 0x58535906. -(AIS Parse): Performing Opcode Sync... -(AIS Parse): Performing jump and close... -(AIS Parse): AIS complete. Jump to address 0xC1080000. -(AIS Parse): Waiting for DONE... -(AIS Parse): Boot completed successfully. - -Operation completed successfully. - -Falcon Bootmode (boot linux without booting U-Boot) -=================================================== - -The Falcon Mode extends this way allowing to start the Linux kernel directly -from SPL. A new command is added to U-Boot to prepare the parameters that SPL -must pass to the kernel, using ATAGS or Device Tree. - -In normal mode, these parameters are generated each time before -loading the kernel, passing to Linux the address in memory where -the parameters can be read. -With Falcon Mode, this snapshot can be saved into persistent storage and SPL is -informed to load it before running the kernel. - -To boot the kernel, these steps under a Falcon-aware U-Boot are required: - -1. Boot the board into U-Boot. -Use the "spl export" command to generate the kernel parameters area or the DT. -U-Boot runs as when it boots the kernel, but stops before passing the control -to the kernel. - -Here the command sequence for the ipam390 board: -- load the linux kernel image into ram: - -U-Boot > nand read c0100000 2 200000 400000 - -NAND read: device 0 offset 0x200000, size 0x400000 - 4194304 bytes read: OK - -- generate the bootparms image: - -U-Boot > spl export atags c0100000 -## Booting kernel from Legacy Image at c0100000 ... - Image Name: Linux-3.5.1 - Image Type: ARM Linux Kernel Image (uncompressed) - Data Size: 2504280 Bytes = 2.4 MiB - Load Address: c0008000 - Entry Point: c0008000 - Verifying Checksum ... OK - Loading Kernel Image ... OK -subcommand not supported -subcommand not supported -Argument image is now in RAM at: 0xc0000100 - -- copy the bootparms image into nand: - -U-Boot > mtdparts - -device nand0 <davinci_nand.0>, # parts = 6 - #: name size offset mask_flags - 0: u-boot-env 0x00020000 0x00000000 0 - 1: u-boot 0x00160000 0x00020000 0 - 2: bootparms 0x00020000 0x00180000 0 - 3: factory-info 0x00060000 0x001a0000 0 - 4: kernel 0x00400000 0x00200000 0 - 5: rootfs 0x07a00000 0x00600000 0 - -active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000 - -defaults: -mtdids : nand0=davinci_nand.0 -mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs) -U-Boot > nand erase.part bootparms - -NAND erase.part: device 0 offset 0x180000, size 0x20000 -Erasing at 0x180000 -- 100% complete. -OK -U-Boot > nand write c0000100 180000 20000 - -NAND write: device 0 offset 0x180000, size 0x20000 - 131072 bytes written: OK -U-Boot > - -You can use also the predefined U-Boot Environment variable "setbootparms", -which will do all the above steps in one command: - -U-Boot > print setbootparms -setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000 -U-Boot > run setbootparms - -NAND read: device 0 offset 0x200000, size 0x400000 - 4194304 bytes read: OK -## Booting kernel from Legacy Image at c0100000 ... - Image Name: Linux-3.5.1 - Image Type: ARM Linux Kernel Image (uncompressed) - Data Size: 2504280 Bytes = 2.4 MiB - Load Address: c0008000 - Entry Point: c0008000 - Verifying Checksum ... OK - Loading Kernel Image ... OK -subcommand not supported -subcommand not supported -Argument image is now in RAM at: 0xc0000100 - -NAND erase.part: device 0 offset 0x180000, size 0x20000 -Erasing at 0x180000 -- 100% complete. -OK - -NAND write: device 0 offset 0x180000, size 0x20000 - 131072 bytes written: OK -U-Boot > - -Links -===== -[1] - http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/ diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg deleted file mode 100644 index 709cf231d01..00000000000 --- a/board/Barix/ipam390/ipam390-ais-uart.cfg +++ /dev/null @@ -1,202 +0,0 @@ -; General settings that can be overwritten in the host code -; that calls the AISGen library. -[General] - -; Can be 8 or 16 - used in emifa -busWidth=8 - -; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW -BootMode=UART - -; 8,16,24 - used for SPI,I2C -;AddrWidth=8 - -; NO_CRC,SECTION_CRC,SINGLE_CRC -crcCheckType=NO_CRC - -; This section allows setting the PLL0 system clock with a -; specified multiplier and divider as shown. The clock source -; can also be chosen for internal or external. -; |------24|------16|-------8|-------0| -; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| -; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| -;[PLL0CONFIG] -;PLL0CFG0 = 0x00180001 -;PLL0CFG1 = 0x00000205 - -[PLLANDCLOCKCONFIG] -PLL0CFG0 = 0x00180001 -PLL0CFG1 = 0x00000205 -PERIPHCLKCFG = 0x00000051 - -; This section allows setting up the PLL1. Usually this will -; take place as part of the EMIF3a DDR setup. The format of -; the input args is as follows: -; |------24|------16|-------8|-------0| -; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| -; PLL1CFG1: | RSVD | PLLDIV3| -[PLL1CONFIG] -PLL1CFG0 = 0x18010001 -PLL1CFG1 = 0x00000002 - -; This section lets us configure the peripheral interface -; of the current booting peripheral (I2C, SPI, or UART). -; Use with caution. The format of the PERIPHCLKCFG field -; is as follows: -; SPI: |------24|------16|-------8|-------0| -; | RSVD |PRESCALE| -; -; I2C: |------24|------16|-------8|-------0| -; | RSVD |PRESCALE| CLKL | CLKH | -; -; UART: |------24|------16|-------8|-------0| -; | RSVD | OSR | DLH | DLL | -[PERIPHCLKCFG] -PERIPHCLKCFG = 0x00000051 - -; This section can be used to configure the PLL1 and the EMIF3a registers -; for starting the DDR2 interface. -; See PLL1CONFIG section for the format of the PLL1CFG fields. -; |------24|------16|-------8|-------0| -; PLL1CFG0: | PLL1CFG | -; PLL1CFG1: | PLL1CFG | -; DDRPHYC1R: | DDRPHYC1R | -; SDCR: | SDCR | -; SDTIMR: | SDTIMR | -; SDTIMR2: | SDTIMR2 | -; SDRCR: | SDRCR | -; CLK2XSRC: | CLK2XSRC | -[EMIF3DDR] -PLL1CFG0 = 0x18010001 -PLL1CFG1 = 0x00000002 -DDRPHYC1R = 0x000000C2 -SDCR = 0x0017C432 -SDTIMR = 0x26922A09 -SDTIMR2 = 0x4414C722 -SDRCR = 0x00000498 -CLK2XSRC = 0x00000000 - -; This section can be used to configure the EMIFA to use -; CS0 as an SDRAM interface. The fields required to do this -; are given below. -; |------24|------16|-------8|-------0| -; SDBCR: | SDBCR | -; SDTIMR: | SDTIMR | -; SDRSRPDEXIT: | SDRSRPDEXIT | -; SDRCR: | SDRCR | -; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | -;[EMIF25SDRAM] -;SDBCR = 0x00004421 -;SDTIMR = 0x42215810 -;SDRSRPDEXIT = 0x00000009 -;SDRCR = 0x00000410 -;DIV4p5_CLK_ENABLE = 0x00000001 - -; This section can be used to configure the async chip selects -; of the EMIFA (CS2-CS5). The fields required to do this -; are given below. -; |------24|------16|-------8|-------0| -; A1CR: | A1CR | -; A2CR: | A2CR | -; A3CR: | A3CR | -; A4CR: | A4CR | -; NANDFCR: | NANDFCR | -;[EMIF25ASYNC] -;A1CR = 0x00000000 -;A2CR = 0x00000000 -;A3CR = 0x00000000 -;A4CR = 0x00000000 -;NANDFCR = 0x00000000 -[EMIF25ASYNC] -A1CR = 0x00000000 -A2CR = 0x04202110 -A3CR = 0x00000000 -A4CR = 0x00000000 -NANDFCR = 0x00000012 - -; This section should be used in place of PLL0CONFIG when -; the I2C, SPI, or UART modes are being used. This ensures that -; the system PLL and the peripheral's clocks are changed together. -; See PLL0CONFIG section for the format of the PLL0CFG fields. -; See PERIPHCLKCFG section for the format of the CLKCFG field. -; |------24|------16|-------8|-------0| -; PLL0CFG0: | PLL0CFG | -; PLL0CFG1: | PLL0CFG | -; PERIPHCLKCFG: | CLKCFG | -;[PLLANDCLOCKCONFIG] -;PLL0CFG0 = 0x00180001 -;PLL0CFG1 = 0x00000205 -;PERIPHCLKCFG = 0x00010032 - -; This section should be used to setup the power state of modules -; of the two PSCs. This section can be included multiple times to -; allow the configuration of any or all of the device modules. -; |------24|------16|-------8|-------0| -; LPSCCFG: | PSCNUM | MODULE | PD | STATE | -;[PSCCONFIG] -;LPSCCFG= - -; This section allows setting of a single PINMUX register. -; This section can be included multiple times to allow setting -; as many PINMUX registers as needed. -; |------24|------16|-------8|-------0| -; REGNUM: | regNum | -; MASK: | mask | -; VALUE: | value | -;[PINMUX] -;REGNUM = 5 -;MASK = 0x00FF0000 -;VALUE = 0x00880000 - -; No Params required - simply include this section for the fast boot -; function to be called -;[FASTBOOT] - -; This section allows setting up the PLL1. Usually this will -; take place as part of the EMIF3a DDR setup. The format of -; the input args is as follows: -; |------24|------16|-------8|-------0| -; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| -; PLL1CFG1: | RSVD | PLLDIV3| -;[PLL1CONFIG] -;PLL1CFG0 = 0x15010001 -;PLL1CFG1 = 0x00000002 - -; This section can be used to configure the PLL1 and the EMIF3a registers -; for starting the DDR2 interface on ARM-boot D800K002 devices. -; |------24|------16|-------8|-------0| -; DDRPHYC1R: | DDRPHYC1R | -; SDCR: | SDCR | -; SDTIMR: | SDTIMR | -; SDTIMR2: | SDTIMR2 | -; SDRCR: | SDRCR | -; CLK2XSRC: | CLK2XSRC | -;[ARM_EMIF3DDR_PATCHFXN] -;DDRPHYC1R = 0x000000C2 -;SDCR = 0x0017C432 -;SDTIMR = 0x26922A09 -;SDTIMR2 = 0x4414C722 -;SDRCR = 0x00000498 -;CLK2XSRC = 0x00000000 - -; This section can be used to configure the PLL1 and the EMIF3a registers -; for starting the DDR2 interface on DSP-boot D800K002 devices. -; |------24|------16|-------8|-------0| -; DDRPHYC1R: | DDRPHYC1R | -; SDCR: | SDCR | -; SDTIMR: | SDTIMR | -; SDTIMR2: | SDTIMR2 | -; SDRCR: | SDRCR | -; CLK2XSRC: | CLK2XSRC | -;[DSP_EMIF3DDR_PATCHFXN] -;DDRPHYC1R = 0x000000C4 -;SDCR = 0x08134632 -;SDTIMR = 0x26922A09 -;SDTIMR2 = 0x0014C722 -;SDRCR = 0x00000492 -;CLK2XSRC = 0x00000000 - -;[INPUTFILE] -;FILENAME=u-boot.bin -;LOADADDRESS=0xC1080000 -;ENTRYPOINTADDRESS=0xC1080000 diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c deleted file mode 100644 index da75ead9bfa..00000000000 --- a/board/Barix/ipam390/ipam390.c +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * Based on: - * U-Boot:board/davinci/da8xxevm/da850evm.c - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on da830evm.c. Original Copyrights follow: - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <netdev.h> -#include <spi.h> -#include <spi_flash.h> -#include <asm/arch/hardware.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/emac_defs.h> -#include <asm/arch/pinmux_defs.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <hwconfig.h> -#include <bootstage.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_DRIVER_TI_EMAC -#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII -#define HAS_RMII 1 -#else -#define HAS_RMII 0 -#endif -#endif /* CONFIG_DRIVER_TI_EMAC */ - -void dsp_lpsc_on(unsigned domain, unsigned int id) -{ - dv_reg_p mdstat, mdctl, ptstat, ptcmd; - struct davinci_psc_regs *psc_regs; - - psc_regs = davinci_psc0_regs; - mdstat = &psc_regs->psc0.mdstat[id]; - mdctl = &psc_regs->psc0.mdctl[id]; - ptstat = &psc_regs->ptstat; - ptcmd = &psc_regs->ptcmd; - - while (*ptstat & (0x1 << domain)) - ; - - if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ - - *mdctl |= 0x03; - - *ptcmd = 0x1 << domain; - - while (*ptstat & (0x1 << domain)) - ; - while ((*mdstat & 0x1f) != 0x03) - ; /* Probably an overkill... */ -} - -static void dspwake(void) -{ - unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; - u32 val; - - /* if the device is ARM only, return */ - if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) - return; - - if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) - return; - - *resetvect++ = 0x1E000; /* DSP Idle */ - /* clear out the next 10 words as NOP */ - memset(resetvect, 0, sizeof(unsigned) * 10); - - /* setup the DSP reset vector */ - writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); - - dsp_lpsc_on(1, DAVINCI_LPSC_GEM); - val = readl(PSC0_MDCTL + (15 * 4)); - val |= 0x100; - writel(val, (PSC0_MDCTL + (15 * 4))); -} - -int misc_init_r(void) -{ - dspwake(); - return 0; -} - -static const struct pinmux_config gpio_pins[] = { - /* GP7[14] selects bootmode*/ - { pinmux(16), 8, 3 }, /* GP7[14] */ -}; - -const struct pinmux_resource pinmuxes[] = { -#ifdef CONFIG_DRIVER_TI_EMAC - PINMUX_ITEM(emac_pins_mdio), -#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII - PINMUX_ITEM(emac_pins_rmii), -#else - PINMUX_ITEM(emac_pins_mii), -#endif -#endif - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(uart2_pins_rtscts), - PINMUX_ITEM(uart0_pins_txrx), - PINMUX_ITEM(uart0_pins_rtscts), -#ifdef CONFIG_NAND_DAVINCI - PINMUX_ITEM(emifa_pins_cs3), - PINMUX_ITEM(emifa_pins_nand), -#endif - PINMUX_ITEM(gpio_pins), -}; - -const int pinmuxes_size = ARRAY_SIZE(pinmuxes); - -const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_UART0 }, /* console */ - { DAVINCI_LPSC_GPIO }, -}; - -const int lpsc_size = ARRAY_SIZE(lpsc); - -#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK -#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 -#endif - -#define REV_AM18X_EVM 0x100 - -/* - * get_board_rev() - setup to pass kernel board revision information - * Returns: - * bit[0-3] Maximum cpu clock rate supported by onboard SoC - * 0000b - 300 MHz - * 0001b - 372 MHz - * 0010b - 408 MHz - * 0011b - 456 MHz - */ -u32 get_board_rev(void) -{ - char *s; - u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; - u32 rev = 0; - - s = env_get("maxcpuclk"); - if (s) - maxcpuclk = simple_strtoul(s, NULL, 10); - - if (maxcpuclk >= 456000000) - rev = 3; - else if (maxcpuclk >= 408000000) - rev = 2; - else if (maxcpuclk >= 372000000) - rev = 1; -#ifdef CONFIG_DA850_AM18X_EVM - rev |= REV_AM18X_EVM; -#endif - return rev; -} - -int board_early_init_f(void) -{ - /* - * Power on required peripherals - * ARM does not have access by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) - return 1; - - return 0; -} - -int board_init(void) -{ - irq_init(); - - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* setup the SUSPSRC for ARM to control emulation suspend */ - writel(readl(&davinci_syscfg_regs->suspsrc) & - ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART0), - &davinci_syscfg_regs->suspsrc); - - /* configure pinmux settings */ - if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) - return 1; - -#ifdef CONFIG_DRIVER_TI_EMAC - davinci_emac_mii_mode_sel(HAS_RMII); -#endif /* CONFIG_DRIVER_TI_EMAC */ - - /* enable the console UART */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), -#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) - &davinci_uart0_ctrl_regs->pwremu_mgmt); -#else - &davinci_uart2_ctrl_regs->pwremu_mgmt); -#endif - return 0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ - -static int init_led(int gpio, char *name, int val) -{ - int ret; - - ret = gpio_request(gpio, name); - if (ret) - return -1; - ret = gpio_direction_output(gpio, val); - if (ret) - return -1; - - return gpio; -} - -#define LED_ON 0 -#define LED_OFF 1 - -#if !defined(CONFIG_SPL_BUILD) -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress(int status) -{ - static int red; - static int green; - - if (red == 0) - red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); - if (red != CONFIG_IPAM390_GPIO_LED_RED) - return; - if (green == 0) - green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", - LED_OFF); - if (green != CONFIG_IPAM390_GPIO_LED_GREEN) - return; - - switch (status) { - case BOOTSTAGE_ID_RUN_OS: - /* - * set normal state - * LED Red : on - * LED green: off - */ - gpio_set_value(red, LED_ON); - gpio_set_value(green, LED_OFF); - break; - case BOOTSTAGE_ID_MAIN_LOOP: - /* - * U-Boot operation - * LED Red : on - * LED green: on - */ - gpio_set_value(red, LED_ON); - gpio_set_value(green, LED_ON); - break; - } -} -#endif -#endif - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - int ret; - int bootmode = 0; - - /* - * GP7[14] selects bootmode: - * 1: boot linux - * 0: boot u-boot - * if error accessing gpio boot U-Boot - * - * SPL bootmode - * 0: boot linux - * 1: boot u-boot - */ - ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode"); - if (ret) - bootmode = 1; - if (!bootmode) { - ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE); - if (ret) - bootmode = 1; - } - if (!bootmode) - ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE); - if (!bootmode) - if (ret == 0) - bootmode = 1; - /* - * LED red : on - * LED green: off - */ - init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); - init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); - return bootmode; -} -#endif diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds deleted file mode 100644 index 06ed3fa89f8..00000000000 --- a/board/Barix/ipam390/u-boot-spl-ipam390.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - */ - -MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_FOOTPRINT } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/arm926ejs/start.o (.text*) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } >.sram - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sram - - __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram -} diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index 190f141091f..c8cc73ab141 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -64,6 +64,7 @@ static int resetc_init(void) return -1; } + resetc.is_psoc = 1; rc = dm_i2c_probe(i2cbus, RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev); if (rc) { diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index 6db1b26e081..de97d6ad586 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -26,12 +26,6 @@ int misc_init_r(void) meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - /* Reset PHY on GPIOZ_14 */ - clrbits_le32(GX_GPIO_EN(3), BIT(14)); - clrbits_le32(GX_GPIO_OUT(3), BIT(14)); - mdelay(10); - setbits_le32(GX_GPIO_OUT(3), BIT(14)); - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 807cfcdb196..1593e2bd4ea 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -73,6 +73,36 @@ int misc_init_r(void) /* SPL */ #ifdef CONFIG_SPL_BUILD +/* must set PB25 low to enable the CAN transceivers */ +static void board_can_stdby_dis(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0); +} + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */ +} + +/* deassert reset lines for external periph in case of warm reboot */ +static void board_reset_additional_periph(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */ +} + +static void board_start_additional_periph(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */ + atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */ +} + #ifdef CONFIG_SD_BOOT void spl_mmc_init(void) { @@ -93,12 +123,20 @@ void spl_board_init(void) #ifdef CONFIG_SD_BOOT spl_mmc_init(); #endif + board_reset_additional_periph(); + board_can_stdby_dis(); + board_leds_init(); } void spl_display_print(void) { } +void spl_board_prepare_for_boot(void) +{ + board_start_additional_periph(); +} + static void ddrc_conf(struct atmel_mpddrc_config *ddrc) { ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); diff --git a/board/beckhoff/mx53cx9020/Makefile b/board/beckhoff/mx53cx9020/Makefile index 423a5532ca6..7f15fc5746d 100644 --- a/board/beckhoff/mx53cx9020/Makefile +++ b/board/beckhoff/mx53cx9020/Makefile @@ -4,4 +4,4 @@ # Patrick Bruenn <p.bruenn@beckhoff.com> obj-y += mx53cx9020.o -obj-$(CONFIG_VIDEO) += mx53cx9020_video.o +obj-$(CONFIG_DM_VIDEO) += mx53cx9020_video.o diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index 79d8a62cf1b..9450d925f6f 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -8,26 +8,12 @@ */ #include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/arch/iomux-mx53.h> -#include <asm/arch/clock.h> #include <asm/mach-imx/mx5_video.h> #include <ACEX1K.h> -#include <netdev.h> -#include <i2c.h> -#include <mmc.h> -#include <fsl_esdhc.h> #include <asm/gpio.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <input.h> -#include <fs.h> -#include <dm/platform_data/serial_mxc.h> enum LED_GPIOS { GPIO_SD1_CD = IMX_GPIO_NR(1, 1), @@ -91,6 +77,9 @@ void weim_cs0_settings(u32 mode) static void setup_gpio_eim(void) { + gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS"); + gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE"); + gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG"); gpio_direction_input(GPIO_C3_STATUS); gpio_direction_input(GPIO_C3_DONE); gpio_direction_output(GPIO_C3_CONFIG, 1); @@ -100,6 +89,7 @@ static void setup_gpio_eim(void) static void setup_gpio_sups(void) { + gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT"); gpio_direction_input(GPIO_SUPS_INT); static const int BLINK_INTERVALL = 50000; @@ -116,6 +106,16 @@ static void setup_gpio_sups(void) static void setup_gpio_leds(void) { + gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R"); + gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B"); + gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G"); + gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R"); + gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B"); + gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G"); + gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R"); + gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B"); + gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G"); + gpio_direction_output(GPIO_LED_SD2_R, 0); gpio_direction_output(GPIO_LED_SD2_B, 0); gpio_direction_output(GPIO_LED_SD2_G, 0); @@ -136,55 +136,6 @@ int board_ehci_hcd_init(int port) } #endif -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR}, - {MMC_SDHC2_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - gpio_direction_input(GPIO_SD1_CD); - gpio_direction_input(GPIO_SD2_CD); - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(GPIO_SD1_CD); - else - ret = !gpio_get_value(GPIO_SD2_CD); - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - u32 index; - int ret; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { - switch (index) { - case 0: - break; - case 1: - break; - default: - printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n", - CONFIG_SYS_FSL_ESDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif static int power_init(void) { @@ -212,29 +163,21 @@ static void clock_1GHz(void) int board_early_init_f(void) { - setup_gpio_leds(); - setup_gpio_sups(); - setup_gpio_eim(); - setup_iomux_lcd(); return 0; } -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; mxc_set_sata_internal_clock(); + setup_gpio_leds(); + setup_gpio_sups(); + setup_gpio_eim(); + setup_iomux_lcd(); + return 0; } diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c index 4055bccc2b7..bf472902562 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020_video.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c @@ -8,41 +8,39 @@ */ #include <common.h> -#include <linux/list.h> -#include <asm/gpio.h> #include <asm/arch/iomux-mx53.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> +#include <asm/gpio.h> +#include <asm/mach-imx/video.h> #define CX9020_DVI_PWD IMX_GPIO_NR(6, 1) -static struct fb_videomode const vga_640x480 = { - .name = "VESA_VGA_640x480", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, /* picosecond (25.175 MHz) */ - .left_margin = 40, - .right_margin = 60, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 20, - .vsync_len = 10, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -}; +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = NULL, + .mode = { + .name = "DVI", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39721, /* picosecond (25.175 MHz) */ + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); void setup_iomux_lcd(void) { /* Turn on DVI_PWD */ imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1); + gpio_request(CX9020_DVI_PWD, "CX9020_DVI_PWD"); gpio_direction_output(CX9020_DVI_PWD, 1); } - -int board_video_skip(void) -{ - const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24); - if (ret) - printf("VESA VG 640x480 cannot be configured: %d\n", ret); - return ret; -} diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index 56328463aec..7f8e0f951d4 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2018 Cisco Systems, Inc. + * (C) Copyright 2019 Synamedia * * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org> */ @@ -9,7 +10,6 @@ #include <common.h> #include <asm/io.h> #include <asm/bootm.h> -#include <mach/sdhci.h> #include <mach/timer.h> #include <mmc.h> #include <fdtdec.h> @@ -80,69 +80,6 @@ void enable_caches(void) */ } -static const phys_addr_t bcmstb_sdhci_address(u32 alias_index) -{ - int node = 0; - int ret = 0; - char sdhci[16] = { 0 }; - const void *fdt = gd->fdt_blob; - const char *path = NULL; - struct fdt_resource resource = { 0 }; - - if (!fdt) { - printf("%s: Invalid gd->fdt_blob\n", __func__); - return 0; - } - - node = fdt_path_offset(fdt, "/aliases"); - if (node < 0) { - printf("%s: Failed to find /aliases node\n", __func__); - return 0; - } - - sprintf(sdhci, "sdhci%d", alias_index); - path = fdt_getprop(fdt, node, sdhci, NULL); - if (!path) { - printf("%s: Failed to find alias for %s\n", __func__, sdhci); - return 0; - } - - node = fdt_path_offset(fdt, path); - if (node < 0) { - printf("%s: Failed to resolve BCMSTB SDHCI alias\n", __func__); - return 0; - } - - ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", - "host", &resource); - if (ret) { - printf("%s: Failed to read BCMSTB SDHCI host resource\n", - __func__); - return 0; - } - - return resource.start; -} - -int board_mmc_init(bd_t *bis) -{ - phys_addr_t sdhci_base_address = 0; - - sdhci_base_address = bcmstb_sdhci_address(CONFIG_BCMSTB_SDHCI_INDEX); - - if (!sdhci_base_address) { - sdhci_base_address = BCMSTB_SDHCI_BASE; - printf("%s: Assuming BCMSTB SDHCI address: 0x%p\n", - __func__, (void *)sdhci_base_address); - } - - debug("BCMSTB SDHCI base address: 0x%p\n", (void *)sdhci_base_address); - - bcmstb_sdhci_init(sdhci_base_address); - - return 0; -} - int timer_init(void) { gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY); diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig deleted file mode 100644 index 2f5473d76a1..00000000000 --- a/board/compulab/cm_t3517/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CM_T3517 - -config SYS_BOARD - default "cm_t3517" - -config SYS_VENDOR - default "compulab" - -config SYS_CONFIG_NAME - default "cm_t3517" - -endif diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS deleted file mode 100644 index fbb6882138b..00000000000 --- a/board/compulab/cm_t3517/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM_T3517 BOARD -M: Igor Grinberg <grinberg@compulab.co.il> -S: Maintained -F: board/compulab/cm_t3517/ -F: include/configs/cm_t3517.h -F: configs/cm_t3517_defconfig diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile deleted file mode 100644 index bfcb75f98f0..00000000000 --- a/board/compulab/cm_t3517/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> -# -# Authors: Igor Grinberg <grinberg@compulab.co.il> - -obj-y += cm_t3517.o mux.o diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c deleted file mode 100644 index 668bb7631ae..00000000000 --- a/board/compulab/cm_t3517/cm_t3517.c +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> - * - * Authors: Igor Grinberg <grinberg@compulab.co.il> - */ - -#include <common.h> -#include <environment.h> -#include <status_led.h> -#include <net.h> -#include <netdev.h> -#include <usb.h> -#include <mmc.h> -#include <linux/compiler.h> -#include <linux/usb/musb.h> - -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/am35x_def.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/musb.h> -#include <asm/omap_musb.h> -#include <asm/ehci-omap.h> - -#include "../common/common.h" -#include "../common/eeprom.h" - -DECLARE_GLOBAL_DATA_PTR; - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "CM-T3517 board", - "NAND 128/512M", -}; - -#ifdef CONFIG_USB_MUSB_AM35X -static struct musb_hdrc_config cm_t3517_musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - -static struct omap_musb_board_data cm_t3517_musb_board_data = { - .set_phy_power = am35x_musb_phy_power, - .clear_irq = am35x_musb_clear_irq, - .reset = am35x_musb_reset, -}; - -static struct musb_hdrc_platform_data cm_t3517_musb_pdata = { -#if defined(CONFIG_USB_MUSB_HOST) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_MUSB_GADGET) - .mode = MUSB_PERIPHERAL, -#else -#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" -#endif - .config = &cm_t3517_musb_config, - .power = 250, - .platform_ops = &am35x_ops, - .board_data = &cm_t3517_musb_board_data, -}; - -static void cm_t3517_musb_init(void) -{ - /* - * Set up USB clock/mode in the DEVCONF2 register. - * USB2.0 PHY reference clock is 13 MHz - */ - clrsetbits_le32(&am35x_scm_general_regs->devconf2, - CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, - CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | - CONF2_VBDTCTEN | CONF2_DATPOL); - - if (!musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data, - (void *)AM35XX_IPSS_USBOTGSS_BASE)) - printf("Failed initializing AM35x MUSB!\n"); -} -#else -static inline void am3517_evm_musb_init(void) {} -#endif - -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); -#endif - - cm_t3517_musb_init(); - - return 0; -} - -/* - * Routine: get_board_rev - * Description: read system revision - */ -u32 get_board_rev(void) -{ - return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); -}; - -int misc_init_r(void) -{ - cl_print_pcb_info(); - omap_die_id_display(); - - return 0; -} - -#if defined(CONFIG_MMC) -#define SB_T35_CD_GPIO 144 -#define SB_T35_WP_GPIO 59 - -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO); -} -#endif - -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONTROL_EFUSE_EMAC_LSB 0x48002380 -#define CONTROL_EFUSE_EMAC_MSB 0x48002384 - -static int am3517_get_efuse_enetaddr(u8 *enetaddr) -{ - u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB); - u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB); - - enetaddr[0] = (u8)((msb >> 16) & 0xff); - enetaddr[1] = (u8)((msb >> 8) & 0xff); - enetaddr[2] = (u8)(msb & 0xff); - enetaddr[3] = (u8)((lsb >> 16) & 0xff); - enetaddr[4] = (u8)((lsb >> 8) & 0xff); - enetaddr[5] = (u8)(lsb & 0xff); - - return is_valid_ethaddr(enetaddr); -} - -static inline int cm_t3517_init_emac(bd_t *bis) -{ - int ret = cpu_eth_init(bis); - - if (ret > 0) - return ret; - - printf("Failed initializing EMAC! "); - return 0; -} -#else /* !CONFIG_DRIVER_TI_EMAC */ -static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; } -static inline int cm_t3517_init_emac(bd_t *bis) { return 0; } -#endif /* CONFIG_DRIVER_TI_EMAC */ - -/* - * Routine: handle_mac_address - * Description: prepare MAC address for on-board Ethernet. - */ -static int cm_t3517_handle_mac_address(void) -{ - unsigned char enetaddr[6]; - int ret; - - ret = eth_env_get_enetaddr("ethaddr", enetaddr); - if (ret) - return 0; - - ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); - if (ret) { - ret = am3517_get_efuse_enetaddr(enetaddr); - if (ret) - return ret; - } - - if (!is_valid_ethaddr(enetaddr)) - return -1; - - return eth_env_set_enetaddr("ethaddr", enetaddr); -} - -#define SB_T35_ETH_RST_GPIO 164 - -/* - * Routine: board_eth_init - * Description: initialize module and base-board Ethernet chips - */ -int board_eth_init(bd_t *bis) -{ - int rc = 0, rc1 = 0; - - rc1 = cm_t3517_handle_mac_address(); - if (rc1) - printf("No MAC address found! "); - - rc1 = cm_t3517_init_emac(bis); - if (rc1 > 0) - rc++; - - rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE, - NULL, SB_T35_ETH_RST_GPIO); - if (rc1 > 0) - rc++; - - return rc; -} - -#ifdef CONFIG_USB_EHCI_OMAP -static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -#define CM_T3517_USB_HUB_RESET_GPIO 152 -#define SB_T35_USB_HUB_RESET_GPIO 98 - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst"); - cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); - - return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(void) -{ - cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO); - cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); - - return omap_ehci_hcd_stop(); -} -#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c deleted file mode 100644 index 89f2477a2e6..00000000000 --- a/board/compulab/cm_t3517/mux.c +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> - * - * Authors: Igor Grinberg <grinberg@compulab.co.il> - */ - -#include <common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux.h> -#include <asm/io.h> - -void set_muxconf_regs(void) -{ - /* SDRC */ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); - - /* GPMC */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); - - /* SB-T35 Ethernet */ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); - /* DVI enable */ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ - /* DataImage backlight */ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ - - /* SB-T35 SD/MMC WP GPIO59 */ - MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); - /* SB-T35 Audio Enable GPIO61 */ - MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); - /* SB-T35 Ethernet IRQ GPIO65 */ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ - - /* UART3 Console */ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); - /* RTC V3020 nCS GPIO163 */ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ - /* SB-T35 Ethernet nRESET GPIO164 */ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ - - /* SB-T35 SD/MMC CD GPIO144 */ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ - /* WIFI nRESET GPIO145 */ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ - /* USB1 PHY Reset GPIO 146 */ - MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ - /* USB2 PHY Reset GPIO 147 */ - MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ - - /* MMC1 */ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)); - - /* DSS */ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); - - /* I2C */ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); - - /* SB-T35 USB HUB Reset GPIO98 */ - MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ - /* CM-T3517 USB HUB Reset GPIO152 */ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ - - /* RMII */ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); - MUX_VAL(CP(RMII_MDIO_CLK), (M0)); - MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); - MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); - MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); - - /* Green LED GPIO186 */ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ - - /* SPI */ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ - /* LCD reset GPIO157 */ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ - - /* RTC V3020 CS Enable GPIO160 */ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ - /* SB-T35 LVDS Transmitter SHDN GPIO162 */ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ - - /* USB0 - mUSB */ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); - /* USB1 EHCI */ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ - /* USB2 EHCI */ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ - - /* SYS_BOOT */ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ -} diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index a2e386f67de..81f69d38502 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -410,7 +410,7 @@ struct eeprom_field layout_legacy[5] = { #define layout_legacy layout_unknown #endif -#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517) +#if defined(CONFIG_CM_T3X) struct eeprom_field layout_v1[12] = { { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 1bc26828bfa..a90b7a35383 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -62,7 +62,7 @@ static int get_mac_addr(u8 *addr) return -1; } - ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr); + ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr); if (ret) { printf("Error - unable to read MAC address from SPI flash.\n"); return -1; diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 2c2f885d43e..fe1bf441014 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -353,7 +353,7 @@ int misc_init_r(void) return 0; } -#ifndef CONFIG_DM_MMC +#if !CONFIG_IS_ENABLED(DM_MMC) #ifdef CONFIG_MMC_DAVINCI static struct davinci_mmc mmc_sd0 = { .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig deleted file mode 100644 index ae5b16e1421..00000000000 --- a/board/davinci/ea20/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_EA20 - -config SYS_BOARD - default "ea20" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "ea20" - -endif diff --git a/board/davinci/ea20/MAINTAINERS b/board/davinci/ea20/MAINTAINERS deleted file mode 100644 index 5c300a3cbfe..00000000000 --- a/board/davinci/ea20/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -EA20 BOARD -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/davinci/ea20/ -F: include/configs/ea20.h -F: configs/ea20_defconfig diff --git a/board/davinci/ea20/Makefile b/board/davinci/ea20/Makefile deleted file mode 100644 index 2ea42d99670..00000000000 --- a/board/davinci/ea20/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - -obj-y += ea20.o diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c deleted file mode 100644 index 573e0ae97a6..00000000000 --- a/board/davinci/ea20/ea20.c +++ /dev/null @@ -1,337 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de - * - * Based on da850evm.c, original Copyrights follow: - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on da830evm.c. Original Copyrights follow: - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <netdev.h> -#include <asm/mach-types.h> -#include <asm/arch/hardware.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/emac_defs.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> -#include <asm/gpio.h> -#include "../../../drivers/video/da8xx-fb.h" - -DECLARE_GLOBAL_DATA_PTR; - -static const struct da8xx_panel lcd_panel = { - /* Casio COM57H531x */ - .name = "Casio_COM57H531x", - .width = 640, - .height = 480, - .hfp = 12, - .hbp = 144, - .hsw = 30, - .vfp = 10, - .vbp = 35, - .vsw = 3, - .pxl_clk = 25000000, - .invert_pxl_clk = 0, -}; - -static const struct display_panel disp_panel = { - QVGA, - 16, - 16, - COLOR_ACTIVE, -}; - -static const struct lcd_ctrl_config lcd_cfg = { - &disp_panel, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .bpp = 16, - .fdd = 255, - .tft_alt_mode = 0, - .stn_565_mode = 0, - .mono_8bit_mode = 0, - .invert_line_clock = 1, - .invert_frm_clock = 1, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, -}; - -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi1_pins[] = { - { pinmux(5), 1, 1 }, - { pinmux(5), 1, 2 }, - { pinmux(5), 1, 4 }, - { pinmux(5), 1, 5 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 2 }, - { pinmux(4), 2, 3 } -}; - -/* UART0 pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(3), 2, 7 }, - { pinmux(3), 2, 6 }, - { pinmux(3), 2, 4 }, - { pinmux(3), 2, 5 } -}; - -#ifdef CONFIG_DRIVER_TI_EMAC -#define HAS_RMII 1 -static const struct pinmux_config emac_pins[] = { - { pinmux(14), 8, 2 }, - { pinmux(14), 8, 3 }, - { pinmux(14), 8, 4 }, - { pinmux(14), 8, 5 }, - { pinmux(14), 8, 6 }, - { pinmux(14), 8, 7 }, - { pinmux(15), 8, 1 }, - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; -#endif - -#ifdef CONFIG_NAND_DAVINCI -const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 0}, /* CS2 */ - { pinmux(7), 0, 1}, /* CS3 in three state*/ - { pinmux(7), 1, 4 }, /* EMA_WE */ - { pinmux(7), 1, 5 }, /* EMA_OE */ - { pinmux(9), 1, 0 }, /* EMA_D[7] */ - { pinmux(9), 1, 1 }, /* EMA_D[6] */ - { pinmux(9), 1, 2 }, /* EMA_D[5] */ - { pinmux(9), 1, 3 }, /* EMA_D[4] */ - { pinmux(9), 1, 4 }, /* EMA_D[3] */ - { pinmux(9), 1, 5 }, /* EMA_D[2] */ - { pinmux(9), 1, 6 }, /* EMA_D[1] */ - { pinmux(9), 1, 7 }, /* EMA_D[0] */ - { pinmux(12), 1, 5 }, /* EMA_A[2] */ - { pinmux(12), 1, 6 }, /* EMA_A[1] */ - { pinmux(6), 1, 0 } /* EMA_CLK */ -}; -#endif - -const struct pinmux_config gpio_pins[] = { - { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/ - { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/ - { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/ - { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */ - { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/ -}; - -const struct pinmux_config lcd_pins[] = { - { pinmux(17), 2, 1 }, /* LCD_D_0 */ - { pinmux(17), 2, 0 }, /* LCD_D_1 */ - { pinmux(16), 2, 7 }, /* LCD_D_2 */ - { pinmux(16), 2, 6 }, /* LCD_D_3 */ - { pinmux(16), 2, 5 }, /* LCD_D_4 */ - { pinmux(16), 2, 4 }, /* LCD_D_5 */ - { pinmux(16), 2, 3 }, /* LCD_D_6 */ - { pinmux(16), 2, 2 }, /* LCD_D_7 */ - { pinmux(18), 2, 1 }, /* LCD_D_8 */ - { pinmux(18), 2, 0 }, /* LCD_D_9 */ - { pinmux(17), 2, 7 }, /* LCD_D_10 */ - { pinmux(17), 2, 6 }, /* LCD_D_11 */ - { pinmux(17), 2, 5 }, /* LCD_D_12 */ - { pinmux(17), 2, 4 }, /* LCD_D_13 */ - { pinmux(17), 2, 3 }, /* LCD_D_14 */ - { pinmux(17), 2, 2 }, /* LCD_D_15 */ - { pinmux(18), 2, 6 }, /* LCD_PCLK */ - { pinmux(19), 2, 0 }, /* LCD_HSYNC */ - { pinmux(19), 2, 1 }, /* LCD_VSYNC */ - { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */ -}; - -const struct pinmux_config halten_pin[] = { - { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */ -}; - -static const struct pinmux_resource pinmuxes[] = { -#ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi1_pins), -#endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), -#ifdef CONFIG_NAND_DAVINCI - PINMUX_ITEM(nand_pins), -#endif -#ifdef CONFIG_VIDEO - PINMUX_ITEM(lcd_pins), -#endif -}; - -static const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART0 }, /* console */ - { DAVINCI_LPSC_GPIO }, - { DAVINCI_LPSC_LCDC }, /* LCD */ -}; - -int board_early_init_f(void) -{ - /* PinMux for GPIO */ - if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) - return 1; - - /* Set DISP_ON high to enable LCD output*/ - gpio_direction_output(97, 1); - - /* Set the RESETOUTn low */ - gpio_direction_output(111, 0); - - /* Set U0_SW0 low for UART0 as console*/ - gpio_direction_output(106, 0); - - /* Set U0_SW1 low for UART0 as console*/ - gpio_direction_output(108, 0); - - /* Set LCD_B_PWR low to power down LCD Backlight*/ - gpio_direction_output(102, 0); - - irq_init(); - - /* - * NAND CS setup - cycle counts based on da850evm NAND timings in the - * Linux kernel @ 25MHz EMIFA - */ -#ifdef CONFIG_NAND_DAVINCI - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | - DAVINCI_ABCR_RHOLD(0) | - DAVINCI_ABCR_TA(0) | - DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->ab1cr); /* CS2 */ -#endif - - /* - * Power on required peripherals - * ARM does not have access by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) - return 1; - - /* setup the SUSPSRC for ARM to control emulation suspend */ - writel(readl(&davinci_syscfg_regs->suspsrc) & - ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART0), - &davinci_syscfg_regs->suspsrc); - - /* configure pinmux settings */ - if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) - return 1; - -#ifdef CONFIG_DRIVER_TI_EMAC - if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) - return 1; - - davinci_emac_mii_mode_sel(HAS_RMII); -#endif /* CONFIG_DRIVER_TI_EMAC */ - - /* enable the console UART */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart0_ctrl_regs->pwremu_mgmt); - - /* - * Reconfigure the LCDC priority to the highest to ensure that - * the throughput/latency requirements for the LCDC are met. - */ - writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff, - &davinci_syscfg_regs->mstpri[2]); - - - return 0; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_init(void) -{ - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_EA20; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - da8xx_video_init(&lcd_panel, &lcd_cfg, 16); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT - -int board_late_init(void) -{ - unsigned char buf[2]; - int ret; - - /* PinMux for HALTEN */ - if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) - return 1; - - /* Set HALTEN to high */ - gpio_direction_output(134, 1); - - /* Set fixed contrast settings for LCD via I2C potentiometer */ - buf[0] = 0x00; - buf[1] = 0xd7; - ret = i2c_write(0x2e, 6, 1, buf, 2); - if (ret) - puts("\nContrast Settings FAILED\n"); - - /* Set LCD_B_PWR high to power up LCD Backlight*/ - gpio_set_value(102, 1); - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ - -#ifdef CONFIG_DRIVER_TI_EMAC - -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - /* - * This board has a RMII PHY. However, the MDC line on the SOM - * must not be disabled (there is no MII PHY on the - * baseboard) via the GPIO2[6], because this pin - * disables at the same time the SPI flash. - */ - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 20ea6dc59b7..7f9a74dd48e 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -36,5 +36,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply OF_BOARD_SETUP imply SIFIVE_SERIAL imply SMP + imply PCI + imply DM_PCI + imply PCIE_ECAM_GENERIC + imply CMD_PCI + imply E1000 + imply NVME endif diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig index b8d9432dcc9..ef2af40f7e8 100644 --- a/board/esd/vme8349/Kconfig +++ b/board/esd/vme8349/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "vme8349" endif + +if TARGET_CADDY2 + +config SYS_BOARD + default "vme8349" + +config SYS_VENDOR + default "esd" + +config SYS_CONFIG_NAME + default "caddy2" + +endif diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 45ad3a83ee8..4c220fa8e13 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,7 +38,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main memory */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; msize = spd_sdram(); @@ -60,7 +60,7 @@ int dram_init(void) int checkboard(void) { -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 puts("Board: esd VME-CADDY/2\n"); #else puts("Board: esd VME-CPU/8349\n"); @@ -69,7 +69,7 @@ int checkboard(void) return 0; } -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 int board_eth_init(bd_t *bis) { return pci_eth_init(bis); @@ -102,7 +102,7 @@ int misc_init_r() * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 * and VME-CADDY/2) have different SDRAM configurations. */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 #define SMALL_RAM 0xff #define LARGE_RAM 0x00 #else @@ -165,7 +165,7 @@ static spd_eeprom_t default_spd_eeprom = { SPD_VAL(0x7e, 0x1d), /* 63 */ { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, SPD_VAL(0x00, 0x00), /* 72 */ -#ifdef VME_CADDY2 +#ifdef CONFIG_TARGET_CADDY2 { "vme-caddy/2 ram " } #else { "vme-cpu/2 ram " } diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index d152a7821f4..ae660398575 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -36,7 +36,7 @@ int pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ #else val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ @@ -55,7 +55,7 @@ int pib_init(void) eieio(); -#if defined(CONFIG_MPC832XEMDS) +#if defined(CONFIG_TARGET_MPC832XEMDS) printf("PCI 32bit bus on PMC2 &PMC3\n"); #else printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); @@ -76,7 +76,7 @@ int pib_init(void) eieio(); printf("QOC3 ATM card on PMC0\n"); -#elif defined(CONFIG_MPC832XEMDS) +#elif defined(CONFIG_TARGET_MPC832XEMDS) val8 = 0; i2c_write(0x26, 0x7, 1, &val8, 1); val8 = 0xf7; diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig new file mode 100644 index 00000000000..ca22c922035 --- /dev/null +++ b/board/freescale/ls1028a/Kconfig @@ -0,0 +1,65 @@ +if TARGET_LS1028AQDS + +config SYS_BOARD + default "ls1028a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1028aqds" + +config EMMC_BOOT + bool "Support for booting from EMMC" + default n + +config SYS_TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT + default 0x82000000 if TFABOOT + default 0x20100000 + +if FSL_LS_PPA +config SYS_LS_PPA_FW_ADDR + hex "PPA Firmware Addr" + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A + default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA header Addr" + default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A +endif +endif + +source "board/freescale/common/Kconfig" + +endif + +if TARGET_LS1028ARDB + +config SYS_BOARD + default "ls1028a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1028ardb" + +config EMMC_BOOT + bool "Support for booting from EMMC" + default n + +config SYS_TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT + default 0x82000000 if TFABOOT + default 0x20100000 + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS new file mode 100644 index 00000000000..6f1a95ea3b1 --- /dev/null +++ b/board/freescale/ls1028a/MAINTAINERS @@ -0,0 +1,21 @@ +LS1028AQDS BOARD +M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> +M: Rai Harninder <harninder.rai@nxp.com> +M: Rajesh Bhagat <rajesh.bhagat@nxp.com> +M: Tang Yuantian <andy.tang@nxp.com> +S: Maintained +F: board/freescale/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028aqds.h +F: configs/ls1028aqds_tfa_defconfig + +LS1028ARDB BOARD +M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> +M: Rai Harninder <harninder.rai@nxp.com> +M: Rajesh Bhagat <rajesh.bhagat@nxp.com> +M: Tang Yuantian <andy.tang@nxp.com> +S: Maintained +F: board/freescale/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028ardb.h +F: configs/ls1028ardb_tfa_defconfig diff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile new file mode 100644 index 00000000000..9bc144cbfea --- /dev/null +++ b/board/freescale/ls1028a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1028a.o +obj-y += ddr.o diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README new file mode 100644 index 00000000000..323881faa50 --- /dev/null +++ b/board/freescale/ls1028a/README @@ -0,0 +1,164 @@ +Overview +-------- +The LS1028A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports ARM SoC LS1028A and its +derivatives. + +LS1028A SoC Overview +-------------------------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +RDB Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For XSPI NOR boot (default) +SW2: 1111_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +For SD Boot +SW2: 1000_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +For eMMC Boot +SW2: 1001_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +LS1028ARDB board Overview +------------------------- +Processor + Two Arm Cortex- A72 processor cores: + - Based on 64-bit ARMv8 architecture + - Up to 1.3 GHz operation + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 + data cache + - Arranged as a single cluster of two cores sharing a single 1 MB L2 + cache +DDR memory + - Five onboard 1G x8 discrete memory modules (Four data byte lanes + ECC) + - 32-bit data and 4-bit ECC + - One chip select + - Data transfer rates of up to 1.6 GT/s + - Single-bit error correction and double-bit error detection ECC (4-bit + check word across 32-bit data) +High-speed serial ports(SerDes) + - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the + Qualcomm AR8033 PHY + - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected + through the NXP F104S8A PHY + - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3 + (8 Gbit/s) cards + - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B + slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or + SATA Gen 3 cards (6 Gbit/s) at a time +eSDHC + - eSDHC1, eSDHC2 +SPI + - Connects to two mikroBUS sockets to support mikro-click modules, + such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near + field communications (NFC) controller +Octal SPI (XSPI) + - One 256 MB onboard XSPI serial NOR flash memory + - One 512 MB onboard XSPI serial NAND flash memory + - Supports a QSPI emulator for offboard QSPI emulation +I2C + - All system devices are accessed via I2C1, which is multiplexed on + I2C multiplexer PCA9848 to isolate address conflicts and reduce + capacitive load + - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor, + thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules + 1 and 2 +CAN + - The two CAN DB9 ports can support CAN FD fast phase at data rates of + up to 5 Mbit/s +Serial audio interface(SAI) + - Audio codec SGTL5000 provides headphone and audio LINEOUT for + stereo speakers + - IEEE1588 interface to support audio on SAI4 + +QDS Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For SD Boot +SW1 : 1000_0000 +SW2 : 1110_0110 +SW3 : 0000_0010 +SW4 : 0000_0000 +SW5 : 0000_0000 +SW6 : 0000_0000 +SW7 : 1111_0011 +SW8 : 1110_0000 +SW9 : 1000_0001 +SW10: 1110_0000 + +For XSPI Boot +SW1 : 1111_0000 +SW2 : 0000_0110 +SW3 : 0000_0010 +SW4 : 0000_0000 +SW5 : 0110_0000 +SW6 : 0101_0000 +SW7 : 1111_0011 +SW8 : 1110_0000 +SW9 : 1000_0000 +SW10: 1110_0000 + +LS1028AQDS board Overview +------------------------- +Processor + Two Arm Cortex- A72 processor cores: + - Based on 64-bit ARMv8 architecture + - Up to 1.3 GHz operation + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 + data cache + - Arranged as a single cluster of two cores sharing a single 1 MB L2 + cache +DDR memory + - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L + - Supports a single- or dual-ranked SODIMM or UDIMM connector + - 32-bit data and 4-bit ECC + - Supports x8/x16 devices + - Supports ECC error detection and correction + - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to + all devices in case of DDR3L or DDR4, respectively. Power can + switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or + DDR4 devices, respectively +SerDes (Serializer/Deserializer) + - Four-lane (0-3) SerDes: + - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10 + Gbit SXGMII, 1 Gbit SGMII + - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII + - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII + - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII, SATA 2.0/3.0 + - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII + add-in cards + - Lane 1 connects to a 2x10 connector with SFP+ through a retimer; + lane 2 (TX lines) connects to an SMA connector + Lane 3 connects to 1x7 header to support SATA devices +eSDHC + - eSDHC1, eSDHC2 +SPI + - SPI1 and SPI2 support three onboard SPI flash memory devices: + 512 Mbit high-speed flash (with speed of up to 108/54 MHz) + memory for storage + 4 Mbit low-speed flash memory (with speed of up to 40 MHz) + 64 Mbit high-speed flash memory (with speed of up to 104/80 + MHz) + - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of + up to 104/80 MHz) + - All memories operate at 1.8 V + - A header is provided on SPI1 to test SPI slave mode +I2C + - LS1028A supports eight I2C controllers +Serial audio interface(SAI) + Two SAI ports with audio codec SGTL5000: + - Include stereo LINEIN with support for external analog input + - Provide headphone and line output +Display + - DisplayPort connector to connect the DP data to a 4K display device + (computer monitor) + - eDP connector to connect the DP data to a 4K display panel diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c new file mode 100644 index 00000000000..74d3af5c359 --- /dev/null +++ b/board/freescale/ls1028a/ddr.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c new file mode 100644 index 00000000000..e5de4eb70c4 --- /dev/null +++ b/board/freescale/ls1028a/ls1028a.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <fsl_ddr.h> +#include <asm/io.h> +#include <hwconfig.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <asm/arch-fsl-layerscape/soc.h> +#include <i2c.h> +#include <asm/arch/soc.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif +#include <fsl_immap.h> +#include <netdev.h> + +#include <fdtdec.h> +#include <miiphy.h> +#include "../common/qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int config_board_mux(void) +{ +#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS) + u8 reg; + + reg = QIXIS_READ(brdcfg[13]); + /* Field| Function + * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3): + * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}. + * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4): + * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}. + */ + reg &= ~(0xf0); + reg |= 0xb0; + QIXIS_WRITE(brdcfg[13], reg); + + reg = QIXIS_READ(brdcfg[15]); + /* Field| Function + * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY): + * CAN1 | 0= CAN #1 transceiver enabled + * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY): + * CAN2 | 0= CAN #2 transceiver enabled + */ + reg &= ~(0xc0); + QIXIS_WRITE(brdcfg[15], reg); +#endif + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + +#ifndef CONFIG_SYS_EARLY_PCI_INIT + pci_init(); +#endif + +#if defined(CONFIG_TARGET_LS1028ARDB) + u8 val = I2C_MUX_CH_DEFAULT; + + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); +#endif + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + config_board_mux(); + + return 0; +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif + + fsl_lsch3_early_init_f(); + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + fdt_fixup_memory_banks(blob, base, size, 2); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_QIXIS +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + u8 sw; + + int clock; + char *board; + char buf[64] = {0}; + static const char *freq[6] = {"100.00", "125.00", "156.25", + "161.13", "322.26", "100.00 SS"}; + + cpu_name(buf); + /* find the board details */ + sw = QIXIS_READ(id); + + switch (sw) { + case 0x46: + board = "QDS"; + break; + case 0x47: + board = "RDB"; + break; + case 0x49: + board = "HSSI"; + break; + default: + board = "unknown"; + break; + } + + sw = QIXIS_READ(arch); + printf("Board: %s-%s, Version: %c, boot from ", + buf, board, (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else if (src == BOOT_SOURCE_SD_MMC2) { + puts("eMMC\n"); + } else { +#endif +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif defined(CONFIG_EMMC_BOOT) + puts("eMMC\n"); +#else + switch (sw) { + case 0: + case 4: + printf("NOR\n"); + break; + case 1: + printf("NAND\n"); + break; + default: + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + break; + } +#endif +#ifdef CONFIG_TFABOOT + } +#endif + + printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board); + puts("SERDES1 Reference : "); + + sw = QIXIS_READ(brdcfg[2]); +#ifdef CONFIG_TARGET_LS1028ARDB + clock = (sw >> 6) & 3; +#else + clock = (sw >> 4) & 0xf; +#endif + + printf("Clock1 = %sMHz ", freq[clock]); +#ifdef CONFIG_TARGET_LS1028ARDB + clock = (sw >> 4) & 3; +#else + clock = sw & 0xf; +#endif + printf("Clock2 = %sMHz\n", freq[clock]); + + return 0; +} +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 3875d045438..6109b280c68 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -449,12 +449,20 @@ unsigned long get_board_ddr_clk(void) int board_init(void) { +#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) + /* invert AQR107 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index e64b3107b5f..317e63ea6a1 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -33,7 +33,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -61,7 +61,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig index 145608feab2..b6332a1368b 100644 --- a/board/freescale/mpc8313erdb/Kconfig +++ b/board/freescale/mpc8313erdb/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MPC8313ERDB +if TARGET_MPC8313ERDB_NOR config SYS_BOARD default "mpc8313erdb" @@ -7,6 +7,19 @@ config SYS_VENDOR default "freescale" config SYS_CONFIG_NAME - default "MPC8313ERDB" + default "MPC8313ERDB_NOR" + +endif + +if TARGET_MPC8313ERDB_NAND + +config SYS_BOARD + default "mpc8313erdb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8313ERDB_NAND" endif diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 5e074e3d87b..c8e30a09478 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -47,7 +47,7 @@ static long fixed_sdram(void) volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; @@ -57,12 +57,12 @@ static long fixed_sdram(void) */ __udelay(50000); -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; @@ -109,8 +109,9 @@ int dram_init(void) msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF); + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; sync(); #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS index 5a67b409934..cdac1ac2eed 100644 --- a/board/freescale/mpc8315erdb/MAINTAINERS +++ b/board/freescale/mpc8315erdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8315erdb/ F: include/configs/MPC8315ERDB.h F: configs/MPC8315ERDB_defconfig +F: configs/MPC8315ERDB_NANDSPL_defconfig diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index b9f94c83324..2f0f29a0e57 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -44,7 +44,7 @@ static long fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 772688186b5..2dc6d7f5f5f 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -79,7 +79,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; msize = fixed_sdram(); diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 869538feb92..61b95c601e6 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -98,7 +98,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; msize = fixed_sdram(); diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig index 51f0b34f398..d1541180799 100644 --- a/board/freescale/mpc8349emds/Kconfig +++ b/board/freescale/mpc8349emds/Kconfig @@ -10,3 +10,16 @@ config SYS_CONFIG_NAME default "MPC8349EMDS" endif + +if TARGET_MPC8349EMDS_SDRAM + +config SYS_BOARD + default "mpc8349emds" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "MPC8349EMDS_SDRAM" + +endif diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index e6648d66a05..a8f26a9a316 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -4,3 +4,6 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig +F: configs/MPC8349EMDS_SDRAM_defconfig +F: configs/MPC8349EMDS_PCI64_defconfig +F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index d40ed3742e0..913b5843e95 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -56,7 +56,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) #ifndef CONFIG_SYS_FSL_DDR2 msize = spd_sdram() * 1024 * 1024; @@ -91,7 +91,7 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(ddr_size); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) @@ -112,12 +112,12 @@ int fixed_sdram(void) im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; @@ -183,28 +183,36 @@ void sdram_init(void) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3; /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; + + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -232,12 +240,13 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index a2feda855f6..005190ed87d 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -77,11 +77,11 @@ void pib_init(void) i2c_write(0x26, 0x6, 1, &val8, 1); val8 = 0x34; i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(PCI_ALL_PCI1) +#elif defined(CONFIG_PCI_ALL_PCI1) val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(PCI_ONE_PCI1) +#elif defined(CONFIG_PCI_ONE_PCI1) val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ #else val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ @@ -98,11 +98,11 @@ void pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); -#if defined(PCI_64BIT) +#if defined(CONFIG_PCI_64BIT) printf("PCI1: 64-bit on PMC2\n"); -#elif defined(PCI_ALL_PCI1) +#elif defined(CONFIG_PCI_ALL_PCI1) printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(PCI_ONE_PCI1) +#elif defined(CONFIG_PCI_ONE_PCI1) printf("PCI1: 32-bit on PMC1\n"); printf("PCI2: 32-bit on PMC2, PMC3\n"); #else diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 3bdec1c4005..81b3f00b56e 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -19,6 +19,9 @@ #include <linux/libfdt.h> #endif +#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" +#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h" + DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SPD_EEPROM @@ -34,14 +37,14 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[0].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; @@ -129,7 +132,7 @@ int dram_init(void) return -ENXIO; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #ifdef CONFIG_SPD_EEPROM msize = spd_sdram(); #else @@ -152,7 +155,7 @@ int dram_init(void) int checkboard(void) { -#ifdef CONFIG_MPC8349ITX +#ifdef CONFIG_TARGET_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); #else puts("Board: Freescale MPC8349E-mITX-GP\n"); diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS index 8386aa72977..ce9c446f2df 100644 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ b/board/freescale/mpc837xemds/MAINTAINERS @@ -4,4 +4,5 @@ S: Orphan (since 2018-05) F: board/freescale/mpc837xemds/ F: include/configs/MPC837XEMDS.h F: configs/MPC837XEMDS_defconfig +F: configs/MPC837XEMDS_SLAVE_defconfig F: configs/MPC837XEMDS_HOST_defconfig diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 09a046dff8d..16922087c01 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -252,7 +252,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); #if (CONFIG_SYS_DDR_SIZE != 512) diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS index 81b4eed5ede..9f44a37a0d9 100644 --- a/board/freescale/mpc837xerdb/MAINTAINERS +++ b/board/freescale/mpc837xerdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mpc837xerdb/ F: include/configs/MPC837XERDB.h F: configs/MPC837XERDB_defconfig +F: configs/MPC837XERDB_SLAVE_defconfig diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index d9a47b90b2f..18f396aac8b 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -95,7 +95,7 @@ int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index af9058a5d77..7dfe104561a 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -5,16 +5,13 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o -obj-$(CONFIG_IO) += miiphybb.o -obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o -obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o -obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o -obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o -obj-$(CONFIG_STRIDER) += fanctrl.o +obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o +obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o +obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o +obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c index c416bf1dc42..06cdc05825b 100644 --- a/board/gdsys/common/adv7611.c +++ b/board/gdsys/common/adv7611.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h> @@ -174,3 +176,5 @@ out: return res; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c index 1234149f42c..5e42467651d 100644 --- a/board/gdsys/common/ch7301.c +++ b/board/gdsys/common/ch7301.c @@ -6,6 +6,8 @@ /* Chrontel CH7301C DVI Transmitter */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -61,3 +63,5 @@ int ch7301_probe(unsigned screen, bool power) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index 8e2f4071ef7..05a14ff1038 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -10,34 +10,53 @@ #include <gdsys_fpga.h> +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +#include <dm.h> +#include <misc.h> +#include <regmap.h> +#include <board.h> + +#include "../../../drivers/misc/gdsys_soc.h" +#include "../../../drivers/misc/gdsys_ioep.h" +#include "../../../drivers/misc/ihs_fpga.h" + +const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2; +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ + +enum status_print_type { + STATUS_LOUD = 0, + STATUS_SILENT = 1, +}; + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS enum { - STATE_TX_PACKET_BUILDING = 1<<0, - STATE_TX_TRANSMITTING = 1<<1, - STATE_TX_BUFFER_FULL = 1<<2, - STATE_TX_ERR = 1<<3, - STATE_RECEIVE_TIMEOUT = 1<<4, - STATE_PROC_RX_STORE_TIMEOUT = 1<<5, - STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6, - STATE_RX_DIST_ERR = 1<<7, - STATE_RX_LENGTH_ERR = 1<<8, - STATE_RX_FRAME_CTR_ERR = 1<<9, - STATE_RX_FCS_ERR = 1<<10, - STATE_RX_PACKET_DROPPED = 1<<11, - STATE_RX_DATA_LAST = 1<<12, - STATE_RX_DATA_FIRST = 1<<13, - STATE_RX_DATA_AVAILABLE = 1<<15, + STATE_TX_PACKET_BUILDING = BIT(0), + STATE_TX_TRANSMITTING = BIT(1), + STATE_TX_BUFFER_FULL = BIT(2), + STATE_TX_ERR = BIT(3), + STATE_RECEIVE_TIMEOUT = BIT(4), + STATE_PROC_RX_STORE_TIMEOUT = BIT(5), + STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6), + STATE_RX_DIST_ERR = BIT(7), + STATE_RX_LENGTH_ERR = BIT(8), + STATE_RX_FRAME_CTR_ERR = BIT(9), + STATE_RX_FCS_ERR = BIT(10), + STATE_RX_PACKET_DROPPED = BIT(11), + STATE_RX_DATA_LAST = BIT(12), + STATE_RX_DATA_FIRST = BIT(13), + STATE_RX_DATA_AVAILABLE = BIT(15), }; enum { - CTRL_PROC_RECEIVE_ENABLE = 1<<12, - CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15, + IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), + IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), + IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7), + IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), }; enum { - IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5, - IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6, - IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7, - IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8, + CTRL_PROC_RECEIVE_ENABLE = BIT(12), + CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), }; struct io_generic_packet { @@ -47,12 +66,17 @@ struct io_generic_packet { u8 bc; u16 packet_length; } __attribute__((__packed__)); +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr; +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +struct udevice *dev; +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ -static void io_check_status(unsigned int fpga, u16 status, bool silent) +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +static void io_check_status(uint fpga, u16 status, enum status_print_type type) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | @@ -66,7 +90,37 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent) err_ctr++; FPGA_SET_REG(fpga, ep.rx_tx_status, status); - if (silent) + if (type == STATUS_SILENT) + return; + + if (status & STATE_RX_PACKET_DROPPED) + printf("RX_PACKET_DROPPED, status %04x\n", status); + + if (status & STATE_RX_DIST_ERR) + printf("RX_DIST_ERR\n"); + if (status & STATE_RX_LENGTH_ERR) + printf("RX_LENGTH_ERR\n"); + if (status & STATE_RX_FRAME_CTR_ERR) + printf("RX_FRAME_CTR_ERR\n"); + if (status & STATE_RX_FCS_ERR) + printf("RX_FCS_ERR\n"); + + if (status & STATE_TX_ERR) + printf("TX_ERR\n"); +} +#else +static void io_check_status(struct udevice *dev, enum status_print_type type) +{ + u16 status = 0; + int ret; + + ret = misc_call(dev, 0, NULL, 0, &status, 0); + if (!ret) + return; + + err_ctr++; + + if (type != STATUS_LOUD) return; if (status & STATE_RX_PACKET_DROPPED) @@ -84,10 +138,12 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent) if (status & STATE_TX_ERR) printf("TX_ERR\n"); } +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ -static void io_send(unsigned int fpga, unsigned int size) +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +static void io_send(uint fpga, uint size) { - unsigned int k; + uint k; struct io_generic_packet packet = { .source_address = 1, .packet_type = 1, @@ -106,10 +162,31 @@ static void io_send(unsigned int fpga, unsigned int size) tx_ctr++; } +#else +static void io_send(struct udevice *dev, uint size) +{ + uint k; + u16 buffer[HEADER_WORDS + 128]; + struct io_generic_packet header = { + .source_address = 1, + .packet_type = 1, + .packet_length = size, + }; + const uint words = (size + 1) / 2; + + memcpy(buffer, &header, 2 * HEADER_WORDS); + for (k = 0; k < words; ++k) + buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8); + + misc_write(dev, 0, buffer, HEADER_WORDS + words); + + tx_ctr++; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ -static void io_receive(unsigned int fpga) +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +static void io_receive(uint fpga) { - unsigned int k = 0; u16 rx_tx_status; FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); @@ -123,17 +200,25 @@ static void io_receive(unsigned int fpga) FPGA_GET_REG(fpga, ep.receive_data, &rx); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - - ++k; } } +#else +static void io_receive(struct udevice *dev) +{ + u16 buffer[HEADER_WORDS + 128]; -static void io_reflect(unsigned int fpga) + if (!misc_read(dev, 0, buffer, 0)) + rx_ctr++; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +static void io_reflect(uint fpga) { u16 buffer[128]; - unsigned int k = 0; - unsigned int n; + uint k = 0; + uint n; u16 rx_tx_status; FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); @@ -157,7 +242,22 @@ static void io_reflect(unsigned int fpga) tx_ctr++; } +#else +static void io_reflect(struct udevice *dev) +{ + u16 buffer[HEADER_WORDS + 128]; + struct io_generic_packet *header; + if (misc_read(dev, 0, buffer, 0)) + return; + + header = (struct io_generic_packet *)&buffer; + + misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length); +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* * FPGA io-endpoint reflector * @@ -166,8 +266,8 @@ static void io_reflect(unsigned int fpga) */ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int fpga; - unsigned int rate = 0; + uint fpga; + uint rate = 0; unsigned long long last_seen = 0; if (argc < 2) @@ -181,10 +281,10 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 2) rate = simple_strtoul(argv[2], NULL, 10); - /* enable receive path */ + /* Enable receive path */ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); - /* set device address to dummy 1*/ + /* Set device address to dummy 1*/ FPGA_SET_REG(fpga, ep.device_address, 1); rx_ctr = 0; tx_ctr = 0; err_ctr = 0; @@ -196,7 +296,7 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FPGA_GET_REG(fpga, top_interrupt, &top_int); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - io_check_status(fpga, rx_tx_status, true); + io_check_status(fpga, rx_tx_status, STATUS_SILENT); if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) io_reflect(fpga); @@ -214,19 +314,71 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#else +/* + * FPGA io-endpoint reflector + * + * Syntax: + * ioreflect {reportrate} + */ +int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *fpga; + struct regmap *map; + uint rate = 0; + unsigned long long last_seen = 0; + if (!dev) { + printf("No device selected\n"); + return 1; + } + + gdsys_soc_get_fpga(dev, &fpga); + regmap_init_mem(dev_ofnode(dev), &map); + + /* Enable receive path */ + misc_set_enabled(dev, true); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + uint top_int; + + ihs_fpga_get(map, top_interrupt, &top_int); + io_check_status(dev, STATUS_SILENT); + if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && + (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) + io_reflect(dev); + + if (rate) { + if (!(tx_ctr % rate) && (tx_ctr != last_seen)) + printf("refl %llu, err %llu\n", tx_ctr, + err_ctr); + last_seen = tx_ctr; + } + + if (ctrlc()) + break; + } + + return 0; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#define DISP_LINE_LEN 16 + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* * FPGA io-endpoint looptest * * Syntax: * ioloop {fpga} {size} {rate} */ -#define DISP_LINE_LEN 16 int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int fpga; - unsigned int size; - unsigned int rate = 0; + uint fpga; + uint size; + uint rate = 0; if (argc < 3) return CMD_RET_USAGE; @@ -262,7 +414,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FPGA_GET_REG(fpga, top_interrupt, &top_int); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - io_check_status(fpga, rx_tx_status, false); + io_check_status(fpga, rx_tx_status, STATUS_LOUD); if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) io_send(fpga, size); if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) @@ -273,15 +425,130 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; udelay(1000000 / rate); if (!(tx_ctr % rate)) - printf("d %lld, tx %llu, rx %llu, err %llu\n", + printf("d %llu, tx %llu, rx %llu, err %llu\n", + tx_ctr - rx_ctr, tx_ctr, rx_ctr, + err_ctr); + } + } + + return 0; +} +#else +/* + * FPGA io-endpoint looptest + * + * Syntax: + * ioloop {size} {rate} + */ +int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint size; + uint rate = 0; + struct udevice *fpga; + struct regmap *map; + + if (!dev) { + printf("No device selected\n"); + return 1; + } + + gdsys_soc_get_fpga(dev, &fpga); + regmap_init_mem(dev_ofnode(dev), &map); + + if (argc < 2) + return CMD_RET_USAGE; + + /* + * packet size is specified since argc > 1 + */ + size = simple_strtoul(argv[2], NULL, 10); + + /* + * If another parameter, it is the test rate in packets per second. + */ + if (argc > 2) + rate = simple_strtoul(argv[3], NULL, 10); + + /* Enable receive path */ + misc_set_enabled(dev, true); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + uint top_int; + + if (ctrlc()) + break; + + ihs_fpga_get(map, top_interrupt, &top_int); + + io_check_status(dev, STATUS_LOUD); + if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) + io_send(dev, size); + if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) + io_receive(dev); + + if (rate) { + udelay(1000000 / rate); + if (!(tx_ctr % rate)) + printf("d %llu, tx %llu, rx %llu, err %llu\n", tx_ctr - rx_ctr, tx_ctr, rx_ctr, err_ctr); } } + return 0; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *ioep = NULL; + struct udevice *board; + char name[8]; + int ret; + + if (board_get(&board)) + return CMD_RET_FAILURE; + + if (argc > 1) { + int i = simple_strtoul(argv[1], NULL, 10); + + snprintf(name, sizeof(name), "ioep%d", i); + + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep); + + if (ret || !ioep) { + printf("Invalid IOEP %d\n", i); + return CMD_RET_FAILURE; + } + + dev = ioep; + } else { + int i = 0; + + while (1) { + snprintf(name, sizeof(name), "ioep%d", i); + + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep); + + if (ret || !ioep) + break; + + printf("IOEP %d:\t%s\n", i++, ioep->name); + } + + if (dev) + printf("\nSelected IOEP: %s\n", dev->name); + else + puts("\nNo IOEP selected.\n"); + } return 0; } +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS U_BOOT_CMD( ioloop, 4, 0, do_ioloop, "fpga io-endpoint looptest", @@ -293,3 +560,22 @@ U_BOOT_CMD( "fpga io-endpoint reflector", "fpga reportrate" ); +#else +U_BOOT_CMD( + ioloop, 3, 0, do_ioloop, + "fpga io-endpoint looptest", + "packetsize [packets/sec]" +); + +U_BOOT_CMD( + ioreflect, 2, 0, do_ioreflect, + "fpga io-endpoint reflector", + "reportrate" +); + +U_BOOT_CMD( + iodev, 2, 0, do_iodev, + "fpga io-endpoint listing/selection", + "[ioep device to select]" +); +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 69d4b8c3334..9ca69ebcbbe 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -6,6 +6,8 @@ /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -155,3 +157,5 @@ int dp501_probe(unsigned screen, bool power) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c index 5e776831dbb..27c875cbec0 100644 --- a/board/gdsys/common/fanctrl.c +++ b/board/gdsys/common/fanctrl.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h> @@ -29,3 +31,5 @@ void init_fan_controller(u8 addr) val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; i2c_reg_write(addr, FAN_CONFIG, val); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c index f189e5fbd11..5ba6613ed56 100644 --- a/board/gdsys/common/fpga.c +++ b/board/gdsys/common/fpga.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <gdsys_fpga.h> @@ -22,3 +24,5 @@ int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index b17e8db91bf..f160a57cc2d 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -11,6 +11,7 @@ #include <gdsys_fpga.h> #else #include <fdtdec.h> +#include <dm.h> #include <regmap.h> #endif @@ -28,7 +29,7 @@ static inline u16 read_reg(struct udevice *fpga, uint base, uint addr) struct regmap *map; u8 *ptr; - regmap_init_mem(fpga, &map); + regmap_init_mem(dev_ofnode(fpga), &map); ptr = regmap_get_range(map, 0); return in_le16((u16 *)(ptr + base + addr)); @@ -40,7 +41,7 @@ static inline void write_reg(struct udevice *fpga, uint base, uint addr, struct regmap *map; u8 *ptr; - regmap_init_mem(fpga, &map); + regmap_init_mem(dev_ofnode(fpga), &map); ptr = regmap_get_range(map, 0); out_le16((u16 *)(ptr + base + addr), val); diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 8e105012479..066222c563d 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -4,233 +4,586 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <gdsys_fpga.h> -enum { - UNITTYPE_MAIN_SERVER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_VIDEO_USER = 3, +enum pcb_video_type { + PCB_DVI_SL, + PCB_DP_165MPIX, + PCB_DP_300MPIX, + PCB_HDMI, + PCB_DP_1_2, + PCB_HDMI_2_0, }; -enum { - UNITTYPEPCB_DVI = 0, - UNITTYPEPCB_DP_165 = 1, - UNITTYPEPCB_DP_300 = 2, - UNITTYPEPCB_HDMI = 3, +enum pcb_transmission_type { + PCB_CAT_1G, + PCB_FIBER_3G, + PCB_CAT_10G, + PCB_FIBER_10G, }; -enum { - COMPRESSION_NONE = 0, - COMPRESSION_TYPE_1 = 1, - COMPRESSION_TYPE_1_2 = 3, - COMPRESSION_TYPE_1_2_3 = 7, +enum carrier_speed { + CARRIER_SPEED_1G, + CARRIER_SPEED_3G, + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, + CARRIER_SPEED_10G, }; -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, +enum ram_config { + RAM_DDR2_32BIT_295MBPS, + RAM_DDR3_32BIT_590MBPS, + RAM_DDR3_48BIT_590MBPS, + RAM_DDR3_64BIT_1800MBPS, + RAM_DDR3_48BIT_1800MBPS, }; -enum { - SYSCLK_147456 = 0, +enum sysclock { + SYSCLK_147456, }; -enum { - RAM_DDR2_32 = 0, - RAM_DDR3_32 = 1, - RAM_DDR3_48 = 2, +struct fpga_versions { + bool video_channel; + bool con_side; + enum pcb_video_type pcb_video_type; + enum pcb_transmission_type pcb_transmission_type; + unsigned int hw_version; }; -enum { - CARRIER_SPEED_1G = 0, - CARRIER_SPEED_2_5G = 1, +struct fpga_features { + u8 video_channels; + u8 carriers; + enum carrier_speed carrier_speed; + enum ram_config ram_config; + enum sysclock sysclock; + + bool pcm_tx; + bool pcm_rx; + bool spdif_tx; + bool spdif_rx; + bool usb2; + bool rs232; + bool compression_type1; + bool compression_type2; + bool compression_type3; + bool interlace; + bool osd; + bool compression_pipes; }; -bool ioep_fpga_has_osd(unsigned int fpga) +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) { - u16 fpga_features; - unsigned feature_osd; + enum { + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), + VERSIONS_FPGA_CON_SIDE = BIT(13), + VERSIONS_FPGA_SC = BIT(14), + VERSIONS_PCB_CON = BIT(9), + VERSIONS_PCB_SC = BIT(8), + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, + VERSIONS_HW_VER_MASK = 0xf << 0, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; + + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { + case VERSIONS_PCB_VIDEO_DP_1_2: + versions->pcb_video_type = PCB_DP_1_2; + break; + + case VERSIONS_PCB_VIDEO_HDMI_2_0: + versions->pcb_video_type = PCB_HDMI_2_0; + break; + } + + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { + case VERSIONS_PCB_TRANSMISSION_FIBER_10G: + versions->pcb_transmission_type = PCB_FIBER_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_10G: + versions->pcb_transmission_type = PCB_CAT_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_FIBER_3G: + versions->pcb_transmission_type = PCB_FIBER_3G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_1G: + versions->pcb_transmission_type = PCB_CAT_1G; + break; - FPGA_GET_REG(0, fpga_features, &fpga_features); - feature_osd = fpga_features & (1<<11); + } - return feature_osd; + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + return 0; } -void ioep_fpga_print_info(unsigned int fpga) +static int get_features(unsigned int fpga, struct fpga_features *features) { - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned unit_type_pcb_video; - unsigned feature_compression; - unsigned feature_osd; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - - FPGA_GET_REG(fpga, versions, &versions); - FPGA_GET_REG(fpga, fpga_version, &fpga_version); - FPGA_GET_REG(fpga, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - unit_type_pcb_video = (versions & 0x01c0) >> 6; - feature_compression = (fpga_features & 0xe000) >> 13; - feature_osd = fpga_features & (1<<11); - feature_audio = (fpga_features & 0x0600) >> 9; - feature_sysclock = (fpga_features & 0x0180) >> 7; - feature_ramconfig = (fpga_features & 0x0060) >> 5; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features & 0x000c) >> 2; - feature_video_channels = fpga_features & 0x0003; - - switch (unit_type) { - case UNITTYPE_MAIN_SERVER: - case UNITTYPE_MAIN_USER: - printf("Mainchannel"); + enum { + FEATURE_SPDIF_RX = BIT(15), + FEATURE_SPDIF_TX = BIT(14), + FEATURE_PCM_RX = BIT(13), + FEATURE_PCM_TX = BIT(12), + FEATURE_RAM_MASK = GENMASK(11, 8), + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), + FEATURE_CARRIER_SPEED_1G = 0x0 << 6, + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, + FEATURE_CARRIER_SPEED_10G = 0x2 << 6, + FEATURE_CARRIERS_MASK = GENMASK(5, 4), + FEATURE_CARRIERS_0 = 0x0 << 4, + FEATURE_CARRIERS_1 = 0x1 << 4, + FEATURE_CARRIERS_2 = 0x2 << 4, + FEATURE_CARRIERS_4 = 0x3 << 4, + FEATURE_USB2 = BIT(3), + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, + }; + + enum { + EXT_FEATURE_OSD = BIT(15), + EXT_FEATURE_ETHERNET = BIT(9), + EXT_FEATURE_INTERLACE = BIT(8), + EXT_FEATURE_RS232 = BIT(7), + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); + + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { + case FEATURE_VIDEOCHANNELS_0: + features->video_channels = 0; break; - case UNITTYPE_VIDEO_SERVER: - case UNITTYPE_VIDEO_USER: - printf("Videochannel"); + case FEATURE_VIDEOCHANNELS_1: + features->video_channels = 1; break; - default: - printf("UnitType %d(not supported)", unit_type); + case FEATURE_VIDEOCHANNELS_1_1: + case FEATURE_VIDEOCHANNELS_2: + features->video_channels = 2; break; - } + }; - switch (unit_type) { - case UNITTYPE_MAIN_SERVER: - case UNITTYPE_VIDEO_SERVER: - printf(" Server"); - if (versions & (1<<4)) - printf(" UC"); + switch (raw_features & FEATURE_CARRIERS_MASK) { + case FEATURE_CARRIERS_0: + features->carriers = 0; break; - case UNITTYPE_MAIN_USER: - case UNITTYPE_VIDEO_USER: - printf(" User"); + case FEATURE_CARRIERS_1: + features->carriers = 1; break; - default: + case FEATURE_CARRIERS_2: + features->carriers = 2; + break; + + case FEATURE_CARRIERS_4: + features->carriers = 4; break; } - if (versions & (1<<5)) - printf(" Fiber"); - else - printf(" CAT"); + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { + case FEATURE_CARRIER_SPEED_1G: + features->carrier_speed = CARRIER_SPEED_1G; + break; + case FEATURE_CARRIER_SPEED_2_5G: + features->carrier_speed = CARRIER_SPEED_2_5G; + break; + case FEATURE_CARRIER_SPEED_10G: + features->carrier_speed = CARRIER_SPEED_10G; + break; + } - switch (unit_type_pcb_video) { - case UNITTYPEPCB_DVI: - printf(" DVI,"); + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT_295MBPS: + features->ram_config = RAM_DDR2_32BIT_295MBPS; break; - case UNITTYPEPCB_DP_165: - printf(" DP 165MPix/s,"); + case FEATURE_RAM_DDR3_32BIT_590MBPS: + features->ram_config = RAM_DDR3_32BIT_590MBPS; break; - case UNITTYPEPCB_DP_300: - printf(" DP 300MPix/s,"); + case FEATURE_RAM_DDR3_48BIT_590MBPS: + features->ram_config = RAM_DDR3_48BIT_590MBPS; break; - case UNITTYPEPCB_HDMI: - printf(" HDMI,"); + case FEATURE_RAM_DDR3_64BIT_1800MBPS: + features->ram_config = RAM_DDR3_64BIT_1800MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_1800MBPS: + features->ram_config = RAM_DDR3_48BIT_1800MBPS; break; } - printf(" FPGA V %d.%02d\n features:", - fpga_version / 100, fpga_version % 100); + features->pcm_tx = raw_features & FEATURE_PCM_TX; + features->pcm_rx = raw_features & FEATURE_PCM_RX; + features->spdif_tx = raw_features & FEATURE_SPDIF_TX; + features->spdif_rx = raw_features & FEATURE_SPDIF_RX; + features->usb2 = raw_features & FEATURE_USB2; + features->rs232 = raw_extended_features & EXT_FEATURE_RS232; + features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1; + features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2; + features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3; + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; + features->osd = raw_extended_features & EXT_FEATURE_OSD; + features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK; + + return 0; +} + +#else + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + /* HW version encoding is a mess, leave it for the moment */ + VERSIONS_HW_VER_MASK = 0xf << 0, + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), + VERSIONS_SFP = BIT(5), + VERSIONS_VIDEO_MASK = 0x7 << 6, + VERSIONS_VIDEO_DVI = 0x0 << 6, + VERSIONS_VIDEO_DP_165 = 0x1 << 6, + VERSIONS_VIDEO_DP_300 = 0x2 << 6, + VERSIONS_VIDEO_HDMI = 0x3 << 6, + VERSIONS_UT_MASK = 0xf << 12, + VERSIONS_UT_MAIN_SERVER = 0x0 << 12, + VERSIONS_UT_MAIN_USER = 0x1 << 12, + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, + VERSIONS_UT_VIDEO_USER = 0x3 << 12, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + switch (raw_versions & VERSIONS_UT_MASK) { + case VERSIONS_UT_MAIN_SERVER: + versions->video_channel = false; + versions->con_side = false; + break; + + case VERSIONS_UT_MAIN_USER: + versions->video_channel = false; + versions->con_side = true; + break; + case VERSIONS_UT_VIDEO_SERVER: + versions->video_channel = true; + versions->con_side = false; + break; - switch (feature_compression) { - case COMPRESSION_NONE: - printf(" no compression"); + case VERSIONS_UT_VIDEO_USER: + versions->video_channel = true; + versions->con_side = true; break; - case COMPRESSION_TYPE_1: - printf(" compression type1(delta)"); + } + + switch (raw_versions & VERSIONS_VIDEO_MASK) { + case VERSIONS_VIDEO_DVI: + versions->pcb_video_type = PCB_DVI_SL; break; - case COMPRESSION_TYPE_1_2: - printf(" compression type1(delta), type2(inline)"); + case VERSIONS_VIDEO_DP_165: + versions->pcb_video_type = PCB_DP_165MPIX; break; - case COMPRESSION_TYPE_1_2_3: - printf(" compression type1(delta), type2(inline), type3(intempo)"); + case VERSIONS_VIDEO_DP_300: + versions->pcb_video_type = PCB_DP_300MPIX; break; - default: - printf(" compression %d(not supported)", feature_compression); + case VERSIONS_VIDEO_HDMI: + versions->pcb_video_type = PCB_HDMI; break; } - printf(", %sosd", feature_osd ? "" : "no "); + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); + if (raw_versions & VERSIONS_SFP) + versions->pcb_transmission_type = PCB_FIBER_3G; + else + versions->pcb_transmission_type = PCB_CAT_1G; + + return 0; +} + +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_CARRIER_SPEED_2_5 = BIT(4), + FEATURE_RAM_MASK = 0x7 << 5, + FEATURE_RAM_DDR2_32BIT = 0x0 << 5, + FEATURE_RAM_DDR3_32BIT = 0x1 << 5, + FEATURE_RAM_DDR3_48BIT = 0x2 << 5, + FEATURE_PCM_AUDIO_TX = BIT(9), + FEATURE_PCM_AUDIO_RX = BIT(10), + FEATURE_OSD = BIT(11), + FEATURE_USB20 = BIT(12), + FEATURE_COMPRESSION_MASK = 7 << 13, + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, + }; + + enum { + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), + EXTENDED_FEATURE_RS232 = BIT(2), + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), + EXTENDED_FEATURE_INTERLACE = BIT(4), + }; + + u16 raw_features; +#ifdef GDSYS_LEGACY_DRIVERS + u16 raw_extended_features; +#endif + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); +#ifdef GDSYS_LEGACY_DRIVERS + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); +#endif + + features->video_channels = raw_features & 0x3; + features->carriers = (raw_features >> 2) & 0x3; + + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT: + features->ram_config = RAM_DDR2_32BIT_295MBPS; break; - case AUDIO_TX: - printf(", audio tx"); + case FEATURE_RAM_DDR3_32BIT: + features->ram_config = RAM_DDR3_32BIT_590MBPS; break; - case AUDIO_RX: - printf(", audio rx"); + case FEATURE_RAM_DDR3_48BIT: + features->ram_config = RAM_DDR3_48BIT_590MBPS; break; + } - case AUDIO_RXTX: - printf(", audio rx+tx"); + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; +#ifdef GDSYS_LEGACY_DRIVERS + features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX; + features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX; +#endif + + features->usb2 = raw_features & FEATURE_USB20; +#ifdef GDSYS_LEGACY_DRIVERS + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; +#endif + + features->compression_type1 = false; + features->compression_type2 = false; + features->compression_type3 = false; + switch (raw_features & FEATURE_COMPRESSION_MASK) { + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: + features->compression_type3 = true; + case FEATURE_COMPRESSION_TYPE1_TYPE2: + features->compression_type2 = true; + case FEATURE_COMPRESSION_TYPE1: + features->compression_type1 = true; break; + } + +#ifdef GDSYS_LEGACY_DRIVERS + features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE; +#endif + features->osd = raw_features & FEATURE_OSD; +#ifdef GDSYS_LEGACY_DRIVERS + features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES; +#endif - default: - printf(", audio %d(not supported)", feature_audio); + return 0; +} + +#endif + +bool ioep_fpga_has_osd(unsigned int fpga) +{ + struct fpga_features features; + + get_features(fpga, &features); + + return features.osd; +} + +void ioep_fpga_print_info(unsigned int fpga) +{ + u16 fpga_version; + struct fpga_versions versions; + struct fpga_features features; + + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + get_versions(fpga, &versions); + get_features(fpga, &features); + + if (versions.video_channel) + printf("Videochannel"); + else + printf("Mainchannel"); + + if (versions.con_side) + printf(" User"); + else + printf(" Server"); + +// FIXME +#if 0 + if (versions & (1<<4)) + printf(" UC"); +#endif + + switch(versions.pcb_transmission_type) { + case PCB_CAT_1G: + case PCB_CAT_10G: + printf(" CAT"); + break; + case PCB_FIBER_3G: + case PCB_FIBER_10G: + printf(" Fiber"); + break; + }; + + switch (versions.pcb_video_type) { + case PCB_DVI_SL: + printf(" DVI,"); + break; + case PCB_DP_165MPIX: + printf(" DP 165MPix/s,"); + break; + case PCB_DP_300MPIX: + printf(" DP 300MPix/s,"); + break; + case PCB_HDMI: + printf(" HDMI,"); + break; + case PCB_DP_1_2: + printf(" DP 1.2,"); + break; + case PCB_HDMI_2_0: + printf(" HDMI 2.0,"); break; } + printf(" FPGA V %d.%02d\n features: ", + fpga_version / 100, fpga_version % 100); + + if (!features.compression_type1 && + !features.compression_type2 && + !features.compression_type3) + printf("no compression, "); + + if (features.compression_type1) + printf("type1, "); + + if (features.compression_type2) + printf("type2, "); + + if (features.compression_type3) + printf("type3, "); + + printf("%sosd", features.osd ? "" : "no "); + + if (features.pcm_rx && features.pcm_tx) + printf(", pcm rx+tx"); + else if(features.pcm_rx) + printf(", pcm rx"); + else if(features.pcm_tx) + printf(", pcm tx"); + + if (features.spdif_rx && features.spdif_tx) + printf(", spdif rx+tx"); + else if(features.spdif_rx) + printf(", spdif rx"); + else if(features.spdif_tx) + printf(", spdif tx"); + puts(",\n "); - switch (feature_sysclock) { + switch (features.sysclock) { case SYSCLK_147456: printf("clock 147.456 MHz"); break; - - default: - printf("clock %d(not supported)", feature_sysclock); - break; } - switch (feature_ramconfig) { - case RAM_DDR2_32: + switch (features.ram_config) { + case RAM_DDR2_32BIT_295MBPS: printf(", RAM 32 bit DDR2"); break; - - case RAM_DDR3_32: + case RAM_DDR3_32BIT_590MBPS: printf(", RAM 32 bit DDR3"); break; - - case RAM_DDR3_48: + case RAM_DDR3_48BIT_590MBPS: + case RAM_DDR3_48BIT_1800MBPS: printf(", RAM 48 bit DDR3"); break; - - default: - printf(", RAM %d(not supported)", feature_ramconfig); + case RAM_DDR3_64BIT_1800MBPS: + printf(", RAM 64 bit DDR3"); break; } - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); + printf(", %d carrier(s)", features.carriers); - printf(", %d video channel(s)\n", feature_video_channels); + switch(features.carrier_speed) { + case CARRIER_SPEED_1G: + printf(", 1Gbit/s"); + break; + case CARRIER_SPEED_3G: + printf(", 3Gbit/s"); + break; + case CARRIER_SPEED_10G: + printf(", 10Gbit/s"); + break; + } + + printf(", %d video channel(s)\n", features.video_channels); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c index bf89d4e2920..c43d24b26d4 100644 --- a/board/gdsys/common/mclink.c +++ b/board/gdsys/common/mclink.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -134,3 +136,5 @@ int mclink_receive(u8 slave, u16 addr, u16 *data) return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c deleted file mode 100644 index 042835d6af6..00000000000 --- a/board/gdsys/common/miiphybb.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include <common.h> -#include <miiphy.h> - -#include <asm/io.h> - -struct io_bb_pinset { - int mdio; - int mdc; -}; - -static int io_bb_mii_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int io_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | pins->mdio); - - return 0; -} - -static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~pins->mdio); - - return 0; -} - -static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdio); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdio); - - return 0; -} - -static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct io_bb_pinset *pins = bus->priv; - - *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); - - return 0; -} - -static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdc); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdc); - - return 0; -} - -static int io_bb_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct io_bb_pinset io_bb_pinsets[] = { - { - .mdio = CONFIG_SYS_MDIO_PIN, - .mdc = CONFIG_SYS_MDC_PIN, - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .mdio = CONFIG_SYS_MDIO1_PIN, - .mdc = CONFIG_SYS_MDC1_PIN, - }, -#endif -}; - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = CONFIG_SYS_GBIT_MII_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[0], - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .name = CONFIG_SYS_GBIT_MII1_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[1], - }, -#endif -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 392d0059da8..10c43291469 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h> #include <malloc.h> @@ -497,3 +499,5 @@ U_BOOT_CMD( "size_x(max. " __stringify(MAX_X_CHARS) ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n" ); + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
\ No newline at end of file diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c index c4b2256da3a..d40c08d9e94 100644 --- a/board/gdsys/common/phy.c +++ b/board/gdsys/common/phy.c @@ -45,8 +45,6 @@ struct mii_setupcmd fixup_88e1518[] = { { MIICMD_SET, 16, 0x214d }, { MIICMD_SET, 17, 0xcc0c }, { MIICMD_SET, 16, 0x2159 }, - { MIICMD_SET, 22, 0x00fb }, - { MIICMD_SET, 7, 0xc00d }, { MIICMD_SET, 22, 0x0000 }, }; diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 9d99f686923..30811889fbf 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -4,6 +4,35 @@ config GDSYS_LEGACY_OSD_CMDS Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by gdsys devices. +config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + +config SYS_FPGA0_BASE + hex + default E0600000 + help + The base address of the first FPGA's register map. + +config SYS_FPGA0_SIZE + hex + default 1 + help + The base address of the first FPGA's register map. + +config SYS_FPGA1_BASE + hex + help + The base address of the second FPGA's register map. + +config SYS_FPGA1_SIZE + hex + help + The base address of the second FPGA's register map. + if TARGET_HRCON config SYS_BOARD @@ -18,6 +47,9 @@ config SYS_CONFIG_NAME config GDSYS_LEGACY_OSD_CMDS default y +config GDSYS_LEGACY_DRIVERS + default y + endif if TARGET_STRIDER @@ -33,9 +65,60 @@ config SYS_CONFIG_NAME config GDSYS_LEGACY_OSD_CMDS default y + +config GDSYS_LEGACY_DRIVERS + default y + +endif + +if TARGET_GAZERBEAM + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "gazerbeam" + +config SYS_FPGA1_BASE + default E0700000 + +config SYS_FPGA1_SIZE + default 1 + +config GDSYS_LEGACY_OSD_CMDS + default y endif +if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM + +choice + prompt "FPGA flavor selection" + +config SYS_FPGA_FLAVOR_LEGACY + bool "Legacy flavor" + help + This enables support for the gdsys pre-Gazerbeam FPGA memory layout. + +config SYS_FPGA_FLAVOR_GAZERBEAM + bool "Gazerbeam flavor" + help + This enables support for the gdsys FPGA memory layout of the + Gazerbeam board. + +endchoice + +config EXTENDED_FEATURES + bool "FPGA extended features" + depends on GDSYS_LEGACY_DRIVERS + help + Enable support for the extended features field of the IHS FPGA. + config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help These commands provide FPGA tests. + +endif diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index 755b9a23858..ed1b6fa1062 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -6,7 +6,9 @@ F: include/configs/hrcon.h F: configs/hrcon_defconfig F: configs/hrcon_dh_defconfig F: include/configs/strider.h +F: configs/strider_defconfig F: configs/strider_cpu_defconfig F: configs/strider_cpu_dp_defconfig F: configs/strider_con_defconfig F: configs/strider_con_dp_defconfig +F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index 60d22325738..9af5fe04d18 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -4,5 +4,6 @@ # Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc obj-y := mpc8308.o sdram.o -obj-$(CONFIG_HRCON) += hrcon.o -obj-$(CONFIG_STRIDER) += strider.o +obj-$(CONFIG_TARGET_HRCON) += hrcon.o +obj-$(CONFIG_TARGET_STRIDER) += strider.o +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c new file mode 100644 index 00000000000..cd621744d28 --- /dev/null +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <board.h> +#include <dm.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <misc.h> +#include <tpm-v1.h> +#include <video_osd.h> + +#include "../common/ihs_mdio.h" +#include "../../../drivers/board/gazerbeam.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct ihs_mdio_info ihs_mdio_info[] = { + { .fpga = NULL, .name = "ihs0", .base = 0x58 }, + { .fpga = NULL, .name = "ihs1", .base = 0x58 }, +}; + +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + +int board_early_init_r(void) +{ + struct udevice *board; + struct udevice *serdes; + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + /* Initialize serdes */ + uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes); + + if (board_detect(board)) + puts("Device information detection failed.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + if (mc == 2 || mc == 1) + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22"); + + if (mc == 4) { + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20"); + dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0"); + dev_enable_by_path("/fpga1bus"); + } + + if (mc == 2 || con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video1"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video1"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video1"); + } + + if (con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video0"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video0"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video0"); + } + + return 0; +} + +int checkboard(void) +{ + struct udevice *board; + char *s = env_get("serial#"); + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + puts("Board: Gazerbeam "); + printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC"); + printf("%s", con == VAR_CON ? "CON" : "CPU"); + + if (s) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void display_osd_info(struct udevice *osd, + struct video_osd_info *osd_info) +{ + printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n", + osd->name, osd_info->major_version, osd_info->minor_version, + osd_info->width, osd_info->height); +} + +int last_stage_init(void) +{ + int fpga_hw_rev = 0; + int i; + struct udevice *board; + struct udevice *osd; + struct video_osd_info osd_info; + struct udevice *tpm; + int ret; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + if (board) { + int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev); + + if (res) + printf("Could not determind FPGA HW revision (res = %d)\n", res); + } + + env_set_ulong("fpga_hw_rev", fpga_hw_rev); + + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) || + tpm_continue_self_test(tpm)) { + printf("TPM init failed\n"); + } + + if (fpga_hw_rev >= 4) { + for (i = 0; i < 4; i++) { + struct udevice *rxaui; + char name[8]; + + snprintf(name, sizeof(name), "rxaui%d", i); + /* Disable RXAUI polarity inversion */ + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui); + if (!ret) + misc_set_enabled(rxaui, false); + } + } + + for (uclass_first_device(UCLASS_VIDEO_OSD, &osd); + osd; + uclass_next_device(&osd)) { + video_osd_get_info(osd, &osd_info); + display_osd_info(osd, &osd_info); + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fsl_fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 2d709dee945..d14a28ec94d 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -35,11 +35,11 @@ #define MAX_MUX_CHANNELS 2 enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, + MCFPGA_DONE = BIT(0), + MCFPGA_INIT_N = BIT(1), + MCFPGA_PROGRAM_N = BIT(2), + MCFPGA_UPDATE_ENABLE_N = BIT(3), + MCFPGA_RESET_N = BIT(4), }; enum { @@ -47,7 +47,7 @@ enum { GPIO_MDIO = 1 << 15, }; -unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; struct { @@ -107,7 +107,7 @@ int checkboard(void) printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); - if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -120,12 +120,11 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; u16 fpga_features; bool hw_type_cat = pca9698_get_value(0x20, 20); - bool ch0_rgmii2_present = false; + bool ch0_rgmii2_present; FPGA_GET_REG(0, fpga_features, &fpga_features); @@ -137,16 +136,16 @@ int last_stage_init(void) /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - unsigned int ctr = 0; + uint ctr = 0; if (i2c_probe(mclink_controllers[k])) continue; while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); + printf("no done for mclink_controller %u\n", k); break; } } @@ -159,8 +158,10 @@ int last_stage_init(void) } if (hw_type_cat) { + uint mux_ch; int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -179,7 +180,7 @@ int last_stage_init(void) } /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -207,6 +208,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -233,17 +235,17 @@ int last_stage_init(void) * provide access to fpga gpios and controls (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); } -void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); } -int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val; @@ -252,7 +254,7 @@ int fpga_gpio_get(unsigned int bus, int pin) return val & pin; } -void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val; @@ -260,7 +262,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); } -void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val; @@ -273,7 +275,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 4, 1); } -void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 4, state ? 0 : 1); } @@ -285,11 +287,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); } -int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 19); } @@ -367,7 +369,7 @@ int ft_board_setup(void *blob, bd_t *bd) */ struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -494,5 +496,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, }; -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 0112244fc79..ae77fc2fd12 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,14 +24,34 @@ DECLARE_GLOBAL_DATA_PTR; -int get_fpga_state(unsigned dev) +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS +/* as gpio output status cannot be read back, we have to buffer it locally */ +u32 gpio0_out; + +void setbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out |= mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + +void clrbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out &= ~mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + +int get_fpga_state(uint dev) { return gd->arch.fpga_state[dev]; } int board_early_init_f(void) { - unsigned k; + uint k; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; @@ -41,8 +61,8 @@ int board_early_init_f(void) int board_early_init_r(void) { - unsigned k; - unsigned ctr; + uint k; + uint ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; @@ -59,7 +79,7 @@ int board_early_init_r(void) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; while (!mpc8308_get_fpga_done(k)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_DONE_FAILED; @@ -86,7 +106,7 @@ int board_early_init_r(void) if (val == REFLECTION_TESTPATTERN_INV) break; - udelay(100000); + mdelay(100); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_REFLECTION_FAILED; @@ -97,3 +117,4 @@ int board_early_init_r(void) return 0; } +#endif diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h index dc07d564eb5..1e4f24fb2ae 100644 --- a/board/gdsys/mpc8308/mpc8308.h +++ b/board/gdsys/mpc8308/mpc8308.h @@ -1,6 +1,9 @@ #ifndef __MPC8308_H_ #define __MPC8308_H_ +void setbits_gpio0_out(u32 mask); +void clrbits_gpio0_out(u32 mask); + /* functions to be provided by board implementation */ void mpc8308_init(void); void mpc8308_set_fpga_reset(unsigned state); diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 5ced8eb0819..2a77fed2702 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -11,6 +11,8 @@ * board\freescale\mpc8315erdb\sdram.c */ +#ifndef CONFIG_MPC83XX_SDRAM + #include <common.h> #include <mpc83xx.h> #include <spd_sdram.h> @@ -34,7 +36,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -62,7 +64,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) @@ -81,3 +83,5 @@ int dram_init(void) return 0; } + +#endif /* !CONFIG_MPC83XX_SDRAM */ diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index fa26585296a..1fdea675bda 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -50,7 +50,7 @@ enum { GPIO_MDIO = 1 << 15, }; -unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; struct { @@ -110,7 +110,7 @@ int checkboard(void) printf("Strider %s", hw_type_cat ? "CAT" : "Fiber"); - if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -123,17 +123,17 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uint mux_ch; + uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; #ifdef CONFIG_STRIDER_CPU - unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; + uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; #endif bool hw_type_cat = pca9698_get_value(0x20, 18); #ifdef CONFIG_STRIDER_CON_DP bool is_dh = pca9698_get_value(0x20, 25); #endif - bool ch0_sgmii2_present = false; + bool ch0_sgmii2_present; /* Turn on Analog Devices ADV7611 */ pca9698_direction_output(0x20, 8, 0); @@ -146,8 +146,8 @@ int last_stage_init(void) /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { - unsigned int ctr = 0; - unsigned char *mclink_controllers = mclink_controllers_dvi; + uint ctr = 0; + uchar *mclink_controllers = mclink_controllers_dvi; #ifdef CONFIG_STRIDER_CPU if (i2c_probe(mclink_controllers[k])) { @@ -161,7 +161,7 @@ int last_stage_init(void) #endif while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { printf("no done for mclink_controller %d\n", k); break; @@ -178,6 +178,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -196,7 +197,7 @@ int last_stage_init(void) } /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -235,7 +236,7 @@ int last_stage_init(void) for (k = 1; k <= slaves; ++k) FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ - udelay(500000); + mdelay(500); #endif for (k = 1; k <= slaves; ++k) { @@ -260,6 +261,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -286,17 +288,17 @@ int last_stage_init(void) * provide access to fpga gpios (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus, gpio.set, pin); } -void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus, gpio.clear, pin); } -int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val; @@ -306,7 +308,7 @@ int fpga_gpio_get(unsigned int bus, int pin) } #ifdef CONFIG_STRIDER_CON_DP -void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val; @@ -314,7 +316,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus, control, val | pin); } -void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val; @@ -328,7 +330,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 26, 1); } -void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 26, state ? 0 : 1); } @@ -340,11 +342,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); } -int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 20); } @@ -422,7 +424,7 @@ int ft_board_setup(void *blob, bd_t *bd) */ struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -549,5 +551,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, }; -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig index 8514d086b97..f5154271d15 100644 --- a/board/gdsys/p1022/Kconfig +++ b/board/gdsys/p1022/Kconfig @@ -1,3 +1,10 @@ +config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + if TARGET_CONTROLCENTERD config SYS_BOARD @@ -9,4 +16,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "controlcenterd" +config GDSYS_LEGACY_DRIVERS + default y + endif diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig deleted file mode 100644 index 25ba548dab6..00000000000 --- a/board/htkw/mcx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MCX - -config SYS_BOARD - default "mcx" - -config SYS_VENDOR - default "htkw" - -config SYS_CONFIG_NAME - default "mcx" - -endif diff --git a/board/htkw/mcx/MAINTAINERS b/board/htkw/mcx/MAINTAINERS deleted file mode 100644 index 513d19daa7c..00000000000 --- a/board/htkw/mcx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MCX BOARD -M: Anatolij Gustschin <agust@denx.de> -S: Maintained -F: board/htkw/mcx/ -F: include/configs/mcx.h -F: configs/mcx_defconfig diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile deleted file mode 100644 index 54bfc13781b..00000000000 --- a/board/htkw/mcx/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Ilya Yanok, Emcraft Systems -# -# Based on ti/evm/Makefile - -obj-y := mcx.o diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c deleted file mode 100644 index ee29fe7cf90..00000000000 --- a/board/htkw/mcx/mcx.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Ilya Yanok, Emcraft Systems - * - * Based on ti/evm/evm.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include <asm/gpio.h> -#include <asm/omap_gpio.h> -#include <asm/arch/dss.h> -#include <asm/arch/clock.h> -#include <errno.h> -#include <i2c.h> -#ifdef CONFIG_USB_EHCI_HCD -#include <usb.h> -#include <asm/ehci-omap.h> -#endif -#include "mcx.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define HOT_WATER_BUTTON 42 -#define LCD_OUTPUT 55 - -/* Address of the framebuffer in RAM. */ -#define FB_START_ADDRESS 0x88000000 - -#ifdef CONFIG_USB_EHCI_HCD -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} -#endif - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - gpio_direction_output(LCD_OUTPUT, 0); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) { - puts("Failed to get hot-water-button pin\n"); - return -ENODEV; - } - gpio_direction_input(HOT_WATER_BUTTON); - - /* - * if hot-water-button is pressed - * change bootcmd - */ - if (gpio_get_value(HOT_WATER_BUTTON)) - return 0; - - env_set("bootcmd", "run swupdate"); - - return 0; -} -#endif - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_MCX(); -} - -#if defined(CONFIG_MMC_OMAP_HS) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) - -static struct panel_config lcd_cfg = { - .timing_h = PANEL_TIMING_H(40, 40, 48), - .timing_v = PANEL_TIMING_V(29, 13, 3), - .pol_freq = 0x00003000, /* Pol Freq */ - .divisor = 0x0001000E, - .panel_type = 0x01, /* TFT */ - .data_lines = 0x03, /* 24 Bit RGB */ - .load_mode = 0x02, /* Frame Mode */ - .panel_color = 0, - .lcd_size = PANEL_LCD_SIZE(800, 480), - .gfx_format = GFXFORMAT_RGB24_UNPACKED, -}; - -int board_video_init(void) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - void *fb; - - fb = (void *)FB_START_ADDRESS; - - lcd_cfg.frame_buffer = fb; - - setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); - setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); - - omap3_dss_panel_config(&lcd_cfg); - omap3_dss_enable(); - - return 0; -} -#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h deleted file mode 100644 index f9ff50f8a70..00000000000 --- a/board/htkw/mcx/mcx.h +++ /dev/null @@ -1,400 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Ilya Yanok, Emcraft Systems - * - * Based on ti/evm/evm.h - */ - -#ifndef _AM3517EVM_H_ -#define _AM3517EVM_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "HTKW mcx Board", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_MCX() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (M0)) \ - MUX_VAL(CP(SDRC_CKE1), (M0)) \ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ - /*sdrc_strben_dly0*/\ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ - /*sdrc_strben_dly1*/\ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \ - /* GPIO_43 LCD buffer enable */ \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ - /* GPIO_57 TS_PenIRQn */\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ - /* GPIO_58 ETHERNET RESET */\ - MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ - /* GPIO_61 SD-CARD CD */ \ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ - /* GPIO_62 Nand write protect, keep enabled */ \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ - /* GPIO_65 SD-CARD WP */\ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ - /* MMC */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ - /* GPIO_131 LCD Enable */ \ - MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ - /* GPIO_132 USB host Enable */\ - MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ - /* GPIO_133 HDMI PD */\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ - \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ - /* GPIO_152 USB phy2 reset */\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ - /* GPIO_153 */\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ - /* GPIO_154 USB phy1 reset */\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ - /* GPIO_155 TS_BUSY */\ - /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \ - /* GPIO_170 Touchscreen ISR */\ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat7 */\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat4 */\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat5 */\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat6 */\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ - /* HSUSB2_dat3 */\ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ - /* CCDC_FIELD: gpio_95, uP-TXD4 */ \ - MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \ - /* CCDC_HD: gpio_96, uP-RTS4# */ \ - MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \ - /* CCDC_VD: gpio_97, uP-CTS4# */ \ - MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \ - /* CCDC_WEN: gpio_98, uP-RXD4 */ \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ - /* Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ - \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ - /* JTAG */\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ - /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_stp */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_clk */\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ - /* Die to Die */\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ - -#endif diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index d547af4b05a..caa36064f05 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); sync(); @@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); /* now check the real size */ disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); #endif return msize; @@ -129,8 +129,8 @@ int dram_init(void) msize = setup_sdram(); - out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF)); + out_be32(&lbc->mrtpr, 0x20000000); sync(); gd->ram_size = msize; diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index d6c594c96ac..fbbbb17034f 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -1,4 +1,4 @@ -if TARGET_KM8360 +if TARGET_KMETER1 config SYS_BOARD default "km83xx" @@ -7,7 +7,46 @@ config SYS_VENDOR default "keymile" config SYS_CONFIG_NAME - default "km8360" + default "kmeter1" + +endif + +if TARGET_KMCOGE5NE + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmcoge5ne" + +endif + +if TARGET_KMVECT1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmvect1" + +endif + +if TARGET_KMTEGR1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtegr1" endif @@ -36,3 +75,55 @@ config SYS_CONFIG_NAME default "tuxx1" endif + +if TARGET_KMSUPX5 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmsupx5" + +endif + +if TARGET_TUGE1 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "tuge1" + +endif + +if TARGET_KMOPTI2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmopti2" + +endif + +if TARGET_KMTEPR2 + +config SYS_BOARD + default "km83xx" + +config SYS_VENDOR + default "keymile" + +config SYS_CONFIG_NAME + default "kmtepr2" + +endif diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 63b06517ac3..94e0d572e22 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,5 +1,5 @@ KM83XX BOARD -M: Holger Brunck <holger.brunck@keymile.com> +M: Holger Brunck <holger.brunck@ch.abb.com> S: Maintained F: board/keymile/km83xx/ F: include/configs/km8360.h diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 4818a4994a0..880ce67fa6c 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -33,7 +33,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) /* MDIO */ {0, 1, 3, 0, 2}, /* MDIO */ {0, 2, 1, 0, 1}, /* MDC */ @@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ -#elif !defined(CONFIG_MPC8309) +#elif !defined(CONFIG_ARCH_MPC8309) /* Local Bus */ {0, 16, 1, 0, 3}, /* LA00 */ {0, 17, 1, 0, 3}, /* LA01 */ @@ -148,7 +148,7 @@ int board_early_init_r(void) u32 *mxmr = &lbc->mamr; #endif -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_ARCH_MPC8360) unsigned short svid; /* * Because of errata in the UCCs, we have to write to the reserved @@ -271,7 +271,7 @@ int last_stage_init(void) } #endif -#if defined(CONFIG_KMCOGE5NE) +#if defined(CONFIG_TARGET_KMCOGE5NE) struct bfticu_iomap *base = (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; @@ -311,7 +311,7 @@ static int fixed_sdram(void) msize = CONFIG_SYS_DDR_SIZE << 20; disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); msize /= (1024 * 1024); if (CONFIG_SYS_DDR_SIZE != msize) { @@ -338,7 +338,7 @@ int dram_init(void) return -ENXIO; out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_BASE & LAWBAR_BAR); + CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 079c8036772..d156e8574bd 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -1,5 +1,5 @@ KM_ARM BOARD -M: Valentin Longchamp <valentin.longchamp@keymile.com> +M: Valentin Longchamp <valentin.longchamp@ch.abb.com> S: Maintained F: board/keymile/km_arm/ F: include/configs/km_kirkwood.h diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS index 93b6bad0a8b..c5170c97e71 100644 --- a/board/keymile/kmp204x/MAINTAINERS +++ b/board/keymile/kmp204x/MAINTAINERS @@ -1,5 +1,5 @@ KMP204X BOARD -M: Valentin Longchamp <valentin.longchamp@keymile.com> +M: Valentin Longchamp <valentin.longchamp@ch.abb.com> S: Maintained F: board/keymile/kmp204x/ F: include/configs/kmp204x.h diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig new file mode 100644 index 00000000000..bf8e1a13ece --- /dev/null +++ b/board/microchip/mpfs_icicle/Kconfig @@ -0,0 +1,26 @@ +if TARGET_MICROCHIP_ICICLE + +config SYS_BOARD + default "mpfs_icicle" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_icicle" + +config SYS_TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + imply SMP + imply SYS_NS16550 + +endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS new file mode 100644 index 00000000000..22f3b97d8b1 --- /dev/null +++ b/board/microchip/mpfs_icicle/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS icicle +M: Padmarao Begari <padmarao.begari@microchip.com> +M: Cyril Jean <cyril.jean@microchip.com> +S: Maintained +F: board/microchip/mpfs_icicle/ +F: include/configs/microchip_mpfs_icicle.h +F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile new file mode 100644 index 00000000000..72b0410dda8 --- /dev/null +++ b/board/microchip/mpfs_icicle/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari <padmarao.begari@microchip.com> +# + +obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c new file mode 100644 index 00000000000..0ef243186d4 --- /dev/null +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(1u << 5u)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c index 4118c019ccf..baf70d8807b 100644 --- a/board/mpc8308_p1m/sdram.c +++ b/board/mpc8308_p1m/sdram.c @@ -29,7 +29,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + CONFIG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -57,7 +57,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/nvidia/nyan-big/README b/board/nvidia/nyan-big/README new file mode 100644 index 00000000000..0e53d8d92fe --- /dev/null +++ b/board/nvidia/nyan-big/README @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2018 Google LLC +# Written by Simon Glass <sjg@chromium.org> + +U-Boot on Nyan +============== + +Nyan-big is supported by mainline U-Boot. This device is based on Tegra124. +To build it, use the nyan-big config. + +To boot it, connect a USB A-A cable from your computer to the back USB port. +Connect a servo board. Then with t20_rec and warn_rst held down: + + sudo tegrarcm --bct cbootimage-configs/tegra124/nvidia/norrin/PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct + --bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000 + +The norrin config is close enough that it works well with Nyan. diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ff5c67de985..3c7bfead249 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -121,7 +121,7 @@ static void enable_required_clocks(void) int nvidia_board_init(void) { clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); - clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); + clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000); /* For external MAX98090 audio codec */ clock_external_output(1); diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 212037da5ac..4985302d6bc 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -5,9 +5,13 @@ */ #include <common.h> +#include <environment.h> +#include <fdtdec.h> #include <i2c.h> +#include <linux/libfdt.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> +#include <asm/arch-tegra/cboot.h> #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-2180.h" @@ -94,3 +98,96 @@ int tegra_pcie_board_init(void) return 0; } #endif /* PCI */ + +static void ft_mac_address_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) { + printf("ethernet alias points to absent node %s\n", path); + return; + } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } +} + +static int ft_copy_carveout(void *dst, const void *src, const char *node) +{ + struct fdt_memory fb; + int err; + + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", node, + err); + + return err; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", + &fb); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, err); + return err; + } + + return 0; +} + +static void ft_carveout_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + static const char * const nodes[] = { + "/host1x@50000000/dc@54200000", + "/host1x@50000000/dc@54240000", + }; + unsigned int i; + int err; + + for (i = 0; i < ARRAY_SIZE(nodes); i++) { + err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to copy carveout for %s: %d\n", + nodes[i], err); + continue; + } + } +} + +int ft_board_setup(void *fdt, bd_t *bd) +{ + ft_mac_address_setup(fdt); + ft_carveout_setup(fdt); + + return 0; +} diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 496e8a02111..d294c7ae013 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -4,10 +4,14 @@ */ #include <common.h> +#include <environment.h> +#include <fdtdec.h> #include <i2c.h> +#include <linux/libfdt.h> +#include <asm/arch-tegra/cboot.h> #include "../p2571/max77620_init.h" -int tegra_board_init(void) +void pin_mux_mmc(void) { struct udevice *dev; uchar val; @@ -18,19 +22,18 @@ int tegra_board_init(void) ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); if (ret) { printf("%s: Cannot find MAX77620 I2C chip\n", __func__); - return ret; + return; } /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ val = 0xF2; ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1); if (ret) { printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); - return ret; + return; } - - return 0; } +#ifdef CONFIG_PCI_TEGRA int tegra_pcie_board_init(void) { struct udevice *dev; @@ -52,3 +55,101 @@ int tegra_pcie_board_init(void) return 0; } +#endif + +static void ft_mac_address_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) { + printf("ethernet alias points to absent node %s\n", path); + return; + } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } +} + +static int ft_copy_carveout(void *dst, const void *src, const char *node) +{ + struct fdt_memory fb; + int err; + + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", node, + err); + + return err; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", + &fb); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, err); + return err; + } + + return 0; +} + +static void ft_carveout_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + static const char * const nodes[] = { + "/host1x@13e00000/display-hub@15200000/display@15200000", + "/host1x@13e00000/display-hub@15200000/display@15210000", + "/host1x@13e00000/display-hub@15200000/display@15220000", + }; + unsigned int i; + int err; + + for (i = 0; i < ARRAY_SIZE(nodes); i++) { + printf("copying carveout for %s...\n", nodes[i]); + + err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to copy carveout for %s: %d\n", + nodes[i], err); + + continue; + } + } +} + +int ft_board_setup(void *fdt, bd_t *bd) +{ + ft_mac_address_setup(fdt); + ft_carveout_setup(fdt); + + return 0; +} diff --git a/board/omicron/calimain/Kconfig b/board/omicron/calimain/Kconfig deleted file mode 100644 index 1ec48e6b551..00000000000 --- a/board/omicron/calimain/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CALIMAIN - -config SYS_BOARD - default "calimain" - -config SYS_VENDOR - default "omicron" - -config SYS_CONFIG_NAME - default "calimain" - -endif diff --git a/board/omicron/calimain/MAINTAINERS b/board/omicron/calimain/MAINTAINERS deleted file mode 100644 index ad788a6dba1..00000000000 --- a/board/omicron/calimain/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -CALIMAIN BOARD -M: Manfred Rudigier <manfred.rudigier@omicronenergy.com> -M: Christoph Rüdisser <christoph.ruedisser@omicronenergy.com> -S: Maintained -F: board/omicron/calimain/ -F: include/configs/calimain.h -F: configs/calimain_defconfig diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile deleted file mode 100644 index d873f0d7368..00000000000 --- a/board/omicron/calimain/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - -obj-y := calimain.o diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c deleted file mode 100644 index 6f7b2b8cb14..00000000000 --- a/board/omicron/calimain/calimain.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 OMICRON electronics GmbH - * - * Based on da850evm.c. Original Copyrights follow: - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <netdev.h> -#include <watchdog.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/emac_defs.h> -#include <asm/arch/pinmux_defs.h> -#include <asm/arch/davinci_misc.h> -#include <asm/arch/timer_defs.h> -#include "../../../drivers/gpio/da8xx_gpio.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define CALIMAIN_HWVERSION_MASK 0x7f000000 -#define CALIMAIN_HWVERSION_SHIFT 24 - -/* Hardware version pinmux settings */ -const struct pinmux_config hwversion_pins[] = { - { pinmux(16), 8, 2 }, /* GP7[15] */ - { pinmux(16), 8, 3 }, /* GP7[14] */ - { pinmux(16), 8, 4 }, /* GP7[13] */ - { pinmux(16), 8, 5 }, /* GP7[12] */ - { pinmux(16), 8, 6 }, /* GP7[11] */ - { pinmux(16), 8, 7 }, /* GP7[10] */ - { pinmux(17), 8, 0 }, /* GP7[9] */ - { pinmux(17), 8, 1 } /* GP7[8] */ -}; - -const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(emac_pins_mii), - PINMUX_ITEM(emac_pins_mdio), - PINMUX_ITEM(emifa_pins_nor), - PINMUX_ITEM(emifa_pins_cs2), - PINMUX_ITEM(emifa_pins_cs3), -}; - -const int pinmuxes_size = ARRAY_SIZE(pinmuxes); - -const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_GPIO }, -}; - -const int lpsc_size = ARRAY_SIZE(lpsc); - -/* read board revision from GPIO7[8..14] */ -u32 get_board_rev(void) -{ - lpsc_on(DAVINCI_LPSC_GPIO); - if (davinci_configure_pin_mux(hwversion_pins, - ARRAY_SIZE(hwversion_pins)) != 0) - return 0xffffffff; - - return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK) - >> CALIMAIN_HWVERSION_SHIFT; -} - -/* - * determine the oscillator frequency depending on the board revision - * - * rev 0x00 ... 25 MHz oscillator - * rev 0x01 ... 24 MHz oscillator - */ -int calimain_get_osc_freq(void) -{ - u32 rev; - int freq; - - rev = get_board_rev(); - switch (rev) { - case 0x00: - freq = 25000000; - break; - default: - freq = 24000000; - break; - } - return freq; -} - -int board_init(void) -{ - int val; - - irq_init(); - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - -#ifdef CONFIG_DRIVER_TI_EMAC - /* select emac MII mode */ - val = readl(&davinci_syscfg_regs->cfgchip3); - val &= ~(1 << 8); - writel(val, &davinci_syscfg_regs->cfgchip3); -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#ifdef CONFIG_HW_WATCHDOG - davinci_hw_watchdog_enable(); -#endif - - printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq()); - printf("Board revision: %d\n", get_board_rev()); - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - davinci_hw_watchdog_reset(); -} -#endif diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile index 604522ebb16..1fc90d1dab4 100644 --- a/board/renesas/draak/Makefile +++ b/board/renesas/draak/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := draak.o +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := draak.o ../rcar-common/common.o +endif diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 8f3d3915f77..46d9f74785c 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -70,21 +70,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - if (fdtdec_setup_mem_size_base() != 0) - return -EINVAL; - - return 0; -} - -int dram_init_banksize(void) -{ - fdtdec_setup_memory_banksize(); - - return 0; -} - #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile index dffa2954045..062c46ba24f 100644 --- a/board/renesas/eagle/Makefile +++ b/board/renesas/eagle/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := eagle.o +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := eagle.o ../rcar-common/common.o +endif diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index 0e5efea19d0..d6240b19efb 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -67,21 +67,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - if (fdtdec_setup_mem_size_base() != 0) - return -EINVAL; - - return 0; -} - -int dram_init_banksize(void) -{ - fdtdec_setup_memory_banksize(); - - return 0; -} - #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile index 2741035c576..1fd9a03ecc9 100644 --- a/board/renesas/ebisu/Makefile +++ b/board/renesas/ebisu/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := ebisu.o +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := ebisu.o ../rcar-common/common.o +endif diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c index 60429e45290..cb7d432a15a 100644 --- a/board/renesas/ebisu/ebisu.c +++ b/board/renesas/ebisu/ebisu.c @@ -43,41 +43,6 @@ int board_init(void) return 0; } -/* - * If the firmware passed a device tree use it for U-Boot DRAM setup. - */ -extern u64 rcar_atf_boot_args[]; - -int dram_init(void) -{ - const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); - const void *blob; - - /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - blob = atf_fdt_blob; - else - blob = gd->fdt_blob; - - return fdtdec_setup_mem_size_base_fdt(blob); -} - -int dram_init_banksize(void) -{ - const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); - const void *blob; - - /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - blob = atf_fdt_blob; - else - blob = gd->fdt_blob; - - fdtdec_setup_memory_banksize_fdt(blob); - - return 0; -} - #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 1ce6e2eac1b..292867e496c 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -9,3 +9,41 @@ #include <common.h> #include <asm/arch/rmobile.h> + +#ifdef CONFIG_RCAR_GEN3 + +DECLARE_GLOBAL_DATA_PTR; + +/* If the firmware passed a device tree use it for U-Boot DRAM setup. */ +extern u64 rcar_atf_boot_args[]; + +int dram_init(void) +{ + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; + + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + return fdtdec_setup_mem_size_base_fdt(blob); +} + +int dram_init_banksize(void) +{ + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; + + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + fdtdec_setup_memory_banksize_fdt(blob); + + return 0; +} +#endif diff --git a/board/renesas/rcar-common/gen3-spl.c b/board/renesas/rcar-common/gen3-spl.c new file mode 100644 index 00000000000..27140c5c35c --- /dev/null +++ b/board/renesas/rcar-common/gen3-spl.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen3 recovery SPL + * + * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <spl.h> + +#define RCAR_CNTC_BASE 0xE6080000 +#define CNTCR_EN BIT(0) + +void board_init_f(ulong dummy) +{ + writel(CNTCR_EN, RCAR_CNTC_BASE); + timer_init(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_UART; +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + debug("image entry point: 0x%lx\n", spl_image->entry_point); + if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { + typedef void (*image_entry_arg_t)(int, int, int, int) + __attribute__ ((noreturn)); + image_entry_arg_t image_entry = + (image_entry_arg_t)(uintptr_t) spl_image->entry_point; + image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0); + } else { + typedef void __noreturn (*image_entry_noargs_t)(void); + image_entry_noargs_t image_entry = + (image_entry_noargs_t)spl_image->entry_point; + image_entry(); + } +} + +void s_init(void) +{ +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index 5b4dea91c14..95258079e40 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := salvator-x.o +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := salvator-x.o ../rcar-common/common.o +endif diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 1db08fce6a2..22fe9619cfb 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -69,41 +69,6 @@ int board_init(void) return 0; } -/* - * If the firmware passed a device tree use it for U-Boot DRAM setup. - */ -extern u64 rcar_atf_boot_args[]; - -int dram_init(void) -{ - const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); - const void *blob; - - /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - blob = atf_fdt_blob; - else - blob = gd->fdt_blob; - - return fdtdec_setup_mem_size_base_fdt(blob); -} - -int dram_init_banksize(void) -{ - const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); - const void *blob; - - /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - blob = atf_fdt_blob; - else - blob = gd->fdt_blob; - - fdtdec_setup_memory_banksize_fdt(blob); - - return 0; -} - #define RST_BASE 0xE6160000 #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CA53RESCNT (RST_BASE + 0x44) diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index 406fdc8fa40..f4d24c68a67 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := ulcb.o cpld.o +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := ulcb.o cpld.o ../rcar-common/common.o +endif diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index faf19c35803..bcae6ff67ca 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -68,41 +68,6 @@ int board_init(void) return 0; } -/* - * If the firmware passed a device tree use it for U-Boot DRAM setup. - */ -extern u64 rcar_atf_boot_args[]; - -int dram_init(void) -{ - const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); - const void *blob; - - /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - blob = atf_fdt_blob; - else - blob = gd->fdt_blob; - - return fdtdec_setup_mem_size_base_fdt(blob); -} - -int dram_init_banksize(void) -{ - const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); - const void *blob; - - /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - blob = atf_fdt_blob; - else - blob = gd->fdt_blob; - - fdtdec_setup_memory_banksize_fdt(blob); - - return 0; -} - #ifdef CONFIG_MULTI_DTB_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f55c92f80c3..3308b3595fd 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -18,9 +18,29 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +NANOPI-NEO4 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi-neo4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi + +ROCK-PI-4 +M: Akash Gajjar <akash@openedev.com> +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/rock-pi-4-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi + +ROCKPRO64 +M: Akash Gajjar <akash@openedev.com> +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/rockpro64-rk3399_defconfig +F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index b8ba29ac6da..a647de6b112 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -45,7 +45,7 @@ int dram_init(void) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -79,19 +79,19 @@ int fixed_sdram(void) u32 ddr_size = msize << 20; /* DDR size in bytes */ u32 ddr_size_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA); im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; @@ -147,6 +147,9 @@ void sdram_init(void) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | + LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | + LSDMR_WRC3 | LSDMR_CL3; puts("\n SDRAM on Local Bus: "); print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); @@ -156,22 +159,27 @@ void sdram_init(void) */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->lbcr = 0x00000000; + /* LB refresh timer prescal, 266MHz/32 */ + lbc->mrtpr = 0x20000000; + /* LB sdram refresh timer, about 6us */ + lbc->lsrt = 0x32000000; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + /* 0x68636733; precharge all the banks */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + /* 0x48636733; auto refresh */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -199,12 +207,13 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ + /* 0x40636733; normal operation */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index f46437901d1..8eb5e304ab2 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_PING imply CLK_SIFIVE imply CLK_SIFIVE_FU540_PRCI + imply CLK_SIFIVE_GEMGXL_MGMT imply DOS_PARTITION imply EFI_PARTITION imply IP_DYN diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c index 5c1acca20d7..c3d832f5848 100644 --- a/board/st/stm32mp1/board.c +++ b/board/st/stm32mp1/board.c @@ -38,9 +38,10 @@ void board_debug_uart_init(void) #endif #ifdef CONFIG_PMIC_STPMIC1 -int board_ddr_power_init(void) +int board_ddr_power_init(enum ddr_type ddr_type) { struct udevice *dev; + bool buck3_at_1800000v = false; int ret; ret = uclass_get_device_by_driver(UCLASS_PMIC, @@ -49,53 +50,127 @@ int board_ddr_power_init(void) /* No PMIC on board */ return 0; - /* VTT = Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); - if (ret < 0) - return ret; - - ret &= ~STPMIC1_LDO3_MODE; - ret &= ~STPMIC1_LDO12356_VOUT_MASK; - ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - - ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - ret); - if (ret < 0) - return ret; - - /* VDD_DDR = Set BUCK2 to 1.35V */ - ret = pmic_clrsetbits(dev, - STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), - STPMIC1_BUCK_VOUT_MASK, - STPMIC1_BUCK2_1350000V); - if (ret < 0) - return ret; - - /* Enable VDD_DDR = BUCK2 */ - ret = pmic_clrsetbits(dev, - STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), - STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA); - if (ret < 0) - return ret; - - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - - /* Enable VREF */ - ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR, - STPMIC1_VREF_ENA, STPMIC1_VREF_ENA); - if (ret < 0) - return ret; - - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - - /* Enable LDO3 */ - ret = pmic_clrsetbits(dev, - STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); - if (ret < 0) - return ret; - - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + switch (ddr_type) { + case STM32MP_DDR3: + /* VTT = Set LDO3 to sync mode */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); + if (ret < 0) + return ret; + + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); + + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + ret); + if (ret < 0) + return ret; + + /* VDD_DDR = Set BUCK2 to 1.35V */ + ret = pmic_clrsetbits(dev, + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_VOUT_MASK, + STPMIC1_BUCK2_1350000V); + if (ret < 0) + return ret; + + /* Enable VDD_DDR = BUCK2 */ + ret = pmic_clrsetbits(dev, + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA); + if (ret < 0) + return ret; + + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + + /* Enable VREF */ + ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR, + STPMIC1_VREF_ENA, STPMIC1_VREF_ENA); + if (ret < 0) + return ret; + + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + + /* Enable VTT = LDO3 */ + ret = pmic_clrsetbits(dev, + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); + if (ret < 0) + return ret; + + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + + break; + + case STM32MP_LPDDR2: + case STM32MP_LPDDR3: + /* + * configure VDD_DDR1 = LDO3 + * Set LDO3 to 1.8V + * + bypass mode if BUCK3 = 1.8V + * + normal mode if BUCK3 != 1.8V + */ + ret = pmic_reg_read(dev, + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3)); + if (ret < 0) + return ret; + + if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V) + buck3_at_1800000v = true; + + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); + if (ret < 0) + return ret; + + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO3_1800000; + if (buck3_at_1800000v) + ret |= STPMIC1_LDO3_MODE; + + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + ret); + if (ret < 0) + return ret; + + /* VDD_DDR2 : Set BUCK2 to 1.2V */ + ret = pmic_clrsetbits(dev, + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_VOUT_MASK, + STPMIC1_BUCK2_1200000V); + if (ret < 0) + return ret; + + /* Enable VDD_DDR1 = LDO3 */ + ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); + if (ret < 0) + return ret; + + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + + /* Enable VDD_DDR2 =BUCK2 */ + ret = pmic_clrsetbits(dev, + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA); + if (ret < 0) + return ret; + + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + + /* Enable VREF */ + ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR, + STPMIC1_VREF_ENA, STPMIC1_VREF_ENA); + if (ret < 0) + return ret; + + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + + break; + + default: + break; + }; return 0; } diff --git a/board/technexion/twister/Kconfig b/board/technexion/twister/Kconfig deleted file mode 100644 index 4c0ace8edda..00000000000 --- a/board/technexion/twister/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TWISTER - -config SYS_BOARD - default "twister" - -config SYS_VENDOR - default "technexion" - -config SYS_CONFIG_NAME - default "twister" - -endif diff --git a/board/technexion/twister/MAINTAINERS b/board/technexion/twister/MAINTAINERS deleted file mode 100644 index 1ce2b37026a..00000000000 --- a/board/technexion/twister/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TWISTER BOARD -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/technexion/twister/ -F: include/configs/twister.h -F: configs/twister_defconfig diff --git a/board/technexion/twister/Makefile b/board/technexion/twister/Makefile deleted file mode 100644 index 3408dc04b25..00000000000 --- a/board/technexion/twister/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Ilya Yanok, Emcraft Systems -# -# Based on ti/evm/Makefile - -obj-y := twister.o diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c deleted file mode 100644 index 0590e5f8afe..00000000000 --- a/board/technexion/twister/twister.c +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Copyright (C) 2009 TechNexion Ltd. - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/omap_gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <i2c.h> -#include <spl.h> -#include <mmc.h> -#include <asm/gpio.h> -#include <usb.h> -#include <asm/ehci-omap.h> -#include "twister.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Timing definitions for Ethernet Controller */ -static const u32 gpmc_smc911[] = { - NET_GPMC_CONFIG1, - NET_GPMC_CONFIG2, - NET_GPMC_CONFIG3, - NET_GPMC_CONFIG4, - NET_GPMC_CONFIG5, - NET_GPMC_CONFIG6, -}; - -static const u32 gpmc_XR16L2751[] = { - XR16L2751_GPMC_CONFIG1, - XR16L2751_GPMC_CONFIG2, - XR16L2751_GPMC_CONFIG3, - XR16L2751_GPMC_CONFIG4, - XR16L2751_GPMC_CONFIG5, - XR16L2751_GPMC_CONFIG6, -}; - -#ifdef CONFIG_USB_EHCI_OMAP -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} -#endif - -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - /* Chip select 1 and 3 are used for XR16L2751 UART controller */ - enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1], - XR16L2751_UART1_BASE, GPMC_SIZE_16M); - - enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3], - XR16L2751_UART2_BASE, GPMC_SIZE_16M); - - gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET"); - gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1); - - return 0; -} - -#ifndef CONFIG_SPL_BUILD -int misc_init_r(void) -{ - char *eth_addr; - struct tam3517_module_info info; - int ret; - - omap_die_id_display(); - - eth_addr = env_get("ethaddr"); - if (eth_addr) - return 0; - - TAM3517_READ_EEPROM(&info, ret); - if (!ret) - TAM3517_READ_MAC_FROM_EEPROM(&info); - - return 0; -} -#endif - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_TWISTER(); -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_DRIVER_TI_EMAC - davinci_emac_initialize(); -#endif - /* init cs for extern lan */ - enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} - -#if defined(CONFIG_MMC_OMAP_HS) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#ifdef CONFIG_SPL_OS_BOOT -/* - * Do board specific preparation before SPL - * Linux boot - */ -void spl_board_prepare_for_linux(void) -{ - /* init cs for extern lan */ - enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5], - CONFIG_SMC911X_BASE, GPMC_SIZE_16M); -} -int spl_start_uboot(void) -{ - int val = 0; - if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) { - gpio_direction_input(SPL_OS_BOOT_KEY); - val = gpio_get_value(SPL_OS_BOOT_KEY); - gpio_free(SPL_OS_BOOT_KEY); - } - return val; -} -#endif diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h deleted file mode 100644 index a56187db8a5..00000000000 --- a/board/technexion/twister/twister.h +++ /dev/null @@ -1,400 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Copyright (C) 2010 TechNexion Ltd. - */ - -#ifndef _TAM3517_H_ -#define _TAM3517_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "TAM3517 TWISTER Board", - "NAND", -}; - -#define XR16L2751_GPMC_CONFIG1 0x00000000 -#define XR16L2751_GPMC_CONFIG2 0x001e1e01 -#define XR16L2751_GPMC_CONFIG3 0x00080300 -#define XR16L2751_GPMC_CONFIG4 0x1c091c09 -#define XR16L2751_GPMC_CONFIG5 0x04181f1f -#define XR16L2751_GPMC_CONFIG6 0x00000FCF - -#define XR16L2751_UART1_BASE 0x21000000 -#define XR16L2751_UART2_BASE 0x23000000 - -/* GPIO used to select between U-Boot and kernel */ -#define SPL_OS_BOOT_KEY 55 - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_TWISTER() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (M0)) \ - MUX_VAL(CP(SDRC_CKE1), (M0)) \ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ - /*sdrc_strben_dly0*/\ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ - /*sdrc_strben_dly1*/\ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ - /* MMC */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - /* CardDetect */\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ - \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\ - /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \ - \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ - /* Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ - /* - GPIO30 */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ - /* - VIO_1V8*/\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ - \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ - /* JTAG */\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \ - MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \ - /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_stp */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_clk */\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ - /* hsusb1_dir */\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - /* hsusb1_nxt */\ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ - /* Die to Die */\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ - -#endif diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig deleted file mode 100644 index fd7196a6f91..00000000000 --- a/board/teejet/mt_ventoux/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MT_VENTOUX - -config SYS_BOARD - default "mt_ventoux" - -config SYS_VENDOR - default "teejet" - -config SYS_CONFIG_NAME - default "mt_ventoux" - -endif diff --git a/board/teejet/mt_ventoux/MAINTAINERS b/board/teejet/mt_ventoux/MAINTAINERS deleted file mode 100644 index d23464c20f8..00000000000 --- a/board/teejet/mt_ventoux/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MT_VENTOUX BOARD -M: Stefano Babic <sbabic@denx.de> -S: Maintained -F: board/teejet/mt_ventoux/ -F: include/configs/mt_ventoux.h -F: configs/mt_ventoux_defconfig diff --git a/board/teejet/mt_ventoux/Makefile b/board/teejet/mt_ventoux/Makefile deleted file mode 100644 index f0071562866..00000000000 --- a/board/teejet/mt_ventoux/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Ilya Yanok, Emcraft Systems -# -# Based on ti/evm/Makefile - -obj-y := mt_ventoux.o diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c deleted file mode 100644 index 33de7a21318..00000000000 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ /dev/null @@ -1,342 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Copyright (C) 2009 TechNexion Ltd. - */ - -#include <common.h> -#include <netdev.h> -#include <malloc.h> -#include <fpga.h> -#include <video_fb.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/omap_gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/dss.h> -#include <asm/arch/clock.h> -#include <i2c.h> -#include <spartan3.h> -#include <asm/gpio.h> -#ifdef CONFIG_USB_EHCI_HCD -#include <usb.h> -#include <asm/ehci-omap.h> -#endif -#include "mt_ventoux.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define BUZZER 140 -#define SPEAKER 141 -#define USB1_PWR 127 -#define USB2_PWR 149 - -#ifndef CONFIG_FPGA -#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" -#endif - -#define FPGA_RESET 62 -#define FPGA_PROG 116 -#define FPGA_CCLK 117 -#define FPGA_DIN 118 -#define FPGA_INIT 119 -#define FPGA_DONE 154 - -#define LCD_PWR 138 -#define LCD_PON_PIN 139 - -#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) -static struct { - u32 xres; - u32 yres; -} panel_resolution[] = { - { 480, 272 }, - { 800, 480 } -}; - -static struct panel_config lcd_cfg[] = { - { - .timing_h = PANEL_TIMING_H(40, 5, 2), - .timing_v = PANEL_TIMING_V(8, 8, 2), - .pol_freq = 0x00003000, /* Pol Freq */ - .divisor = 0x00010033, /* 9 Mhz Pixel Clock */ - .panel_type = 0x01, /* TFT */ - .data_lines = 0x03, /* 24 Bit RGB */ - .load_mode = 0x02, /* Frame Mode */ - .panel_color = 0, - .gfx_format = GFXFORMAT_RGB24_UNPACKED, - }, - { - .timing_h = PANEL_TIMING_H(20, 192, 4), - .timing_v = PANEL_TIMING_V(2, 20, 10), - .pol_freq = 0x00004000, /* Pol Freq */ - .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ - .panel_type = 0x01, /* TFT */ - .data_lines = 0x03, /* 24 Bit RGB */ - .load_mode = 0x02, /* Frame Mode */ - .panel_color = 0, - .gfx_format = GFXFORMAT_RGB24_UNPACKED, - } -}; -#endif - -/* Timing definitions for FPGA */ -static const u32 gpmc_fpga[] = { - FPGA_GPMC_CONFIG1, - FPGA_GPMC_CONFIG2, - FPGA_GPMC_CONFIG3, - FPGA_GPMC_CONFIG4, - FPGA_GPMC_CONFIG5, - FPGA_GPMC_CONFIG6, -}; - -#ifdef CONFIG_USB_EHCI_HCD -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} -#endif - - -static inline void fpga_reset(int nassert) -{ - gpio_set_value(FPGA_RESET, !nassert); -} - -int fpga_pgm_fn(int nassert, int nflush, int cookie) -{ - debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); - - gpio_set_value(FPGA_PROG, !nassert); - - return nassert; -} - -int fpga_init_fn(int cookie) -{ - return !gpio_get_value(FPGA_INIT); -} - -int fpga_done_fn(int cookie) -{ - return gpio_get_value(FPGA_DONE); -} - -int fpga_pre_config_fn(int cookie) -{ - debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); - - /* Setting GPIOs for programming Mode */ - gpio_request(FPGA_RESET, "FPGA_RESET"); - gpio_direction_output(FPGA_RESET, 1); - gpio_request(FPGA_PROG, "FPGA_PROG"); - gpio_direction_output(FPGA_PROG, 1); - gpio_request(FPGA_CCLK, "FPGA_CCLK"); - gpio_direction_output(FPGA_CCLK, 1); - gpio_request(FPGA_DIN, "FPGA_DIN"); - gpio_direction_output(FPGA_DIN, 0); - gpio_request(FPGA_INIT, "FPGA_INIT"); - gpio_direction_input(FPGA_INIT); - gpio_request(FPGA_DONE, "FPGA_DONE"); - gpio_direction_input(FPGA_DONE); - - /* Be sure that signal are deasserted */ - gpio_set_value(FPGA_RESET, 1); - gpio_set_value(FPGA_PROG, 1); - - return 0; -} - -int fpga_post_config_fn(int cookie) -{ - debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); - - fpga_reset(true); - udelay(100); - fpga_reset(false); - - return 0; -} - -/* Write program to the FPGA */ -int fpga_wr_fn(int nassert_write, int flush, int cookie) -{ - gpio_set_value(FPGA_DIN, nassert_write); - - return nassert_write; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - gpio_set_value(FPGA_CCLK, assert_clk); - - return assert_clk; -} - -xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_post_config_fn, -}; - -xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, - (void *)&mt_ventoux_fpga_fns, 0); - -/* Initialize the FPGA */ -static void mt_ventoux_init_fpga(void) -{ - fpga_pre_config_fn(0); - - /* Setting CS1 for FPGA access */ - enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], - FPGA_BASE_ADDR, GPMC_SIZE_128M); - - fpga_init(); - fpga_add(fpga_xilinx, &fpga); -} - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - mt_ventoux_init_fpga(); - - /* GPIO_140: speaker #mute */ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) - /* GPIO_141: Buzz Hi */ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) - - /* Turning off the buzzer */ - gpio_request(BUZZER, "BUZZER_MUTE"); - gpio_request(SPEAKER, "SPEAKER"); - gpio_direction_output(BUZZER, 0); - gpio_direction_output(SPEAKER, 0); - - /* Activate USB power */ - gpio_request(USB1_PWR, "USB1_PWR"); - gpio_request(USB2_PWR, "USB2_PWR"); - gpio_direction_output(USB1_PWR, 1); - gpio_direction_output(USB2_PWR, 1); - - return 0; -} - -#ifndef CONFIG_SPL_BUILD -int misc_init_r(void) -{ - char *eth_addr; - struct tam3517_module_info info; - int ret; - - TAM3517_READ_EEPROM(&info, ret); - omap_die_id_display(); - - if (ret) - return 0; - eth_addr = env_get("ethaddr"); - if (!eth_addr) - TAM3517_READ_MAC_FROM_EEPROM(&info); - - TAM3517_PRINT_SOM_INFO(&info); - return 0; -} -#endif - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_MT_VENTOUX(); -} - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int board_eth_init(bd_t *bis) -{ - davinci_emac_initialize(); - return 0; -} - -#if defined(CONFIG_MMC_OMAP_HS) && \ - !defined(CONFIG_SPL_BUILD) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) -int board_video_init(void) -{ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - struct panel_config *panel = &lcd_cfg[0]; - char *s; - u32 index = 0; - - void *fb; - - fb = (void *)0x88000000; - - s = env_get("panel"); - if (s) { - index = simple_strtoul(s, NULL, 10); - if (index < ARRAY_SIZE(lcd_cfg)) - panel = &lcd_cfg[index]; - else - return 0; - } - - panel->frame_buffer = fb; - printf("Panel: %dx%d\n", panel_resolution[index].xres, - panel_resolution[index].yres); - panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | - (panel_resolution[index].xres - 1); - - gpio_request(LCD_PWR, "LCD Power"); - gpio_request(LCD_PON_PIN, "LCD Pon"); - gpio_direction_output(LCD_PWR, 0); - gpio_direction_output(LCD_PON_PIN, 1); - - - setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); - setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); - - omap3_dss_panel_config(panel); - omap3_dss_enable(); - - return 0; -} -#endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h deleted file mode 100644 index 5e017742340..00000000000 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ /dev/null @@ -1,403 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Stefano Babic <sbabic@denx.de> - * - * Author: Hardy Weng <hardy.weng@technexion.com> - * - * Copyright (C) 2010 TechNexion Ltd. - */ - -#ifndef _MT_VENTOUX_H_ -#define _MT_VENTOUX_H_ - -const omap3_sysinfo sysinfo = { - DDR_DISCRETE, - "Teejet MT_VENTOUX Board", - "NAND", -}; - -/* FPGA CS1 configuration */ -#define FPGA_GPMC_CONFIG1 0x00001200 -#define FPGA_GPMC_CONFIG2 0x00161f00 -#define FPGA_GPMC_CONFIG3 0x00040400 -#define FPGA_GPMC_CONFIG4 0x120c1f08 -#define FPGA_GPMC_CONFIG5 0x001e161f -#define FPGA_GPMC_CONFIG6 0x96080fcf - -#define FPGA_BASE_ADDR 0x20000000 - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_MT_VENTOUX() \ - /* SDRC */\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SDRC_CKE0), (M0)) \ - MUX_VAL(CP(SDRC_CKE1), (M0)) \ - MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ - /* GPMC */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\ - MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \ - /* GPIO 55 : NFS */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \ - /*GPIO_62: FPGA_RESET */ \ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ - /* GPIO_64*/ \ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ - /* MMC */\ - MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - /* GPIO_126: CardDetect */\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - /*GPIO_128 */ \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ - /* GPIO_138: LCD_ENVD */\ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \ - /* GPIO_139: LCD_PON */\ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \ - /* GPIO_116: FPGA_PROG */ \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \ - /* GPIO_117: FPGA_CCLK */ \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \ - /* GPIO_118: FPGA_DIN */ \ - MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ - /* GPIO_119: FPGA_INIT */ \ - \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \ - /*GPIO_152: Ignition Sense */ \ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \ - /*GPIO_153: Power Button Sense */ \ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \ - /* GPIO_154: FPGA_DONE */ \ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \ - /* GPIO_155: CA8_irq */ \ - /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \ - /* GPIO_149: USB status 2 */\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \ - /* GPIO_150: USB status 1 */\ - \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \ - /* gpt9_pwm */\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \ - /* gpt10_pwm */\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \ - /* gpt8_pwm */\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \ - /* gpt11_pwm */\ - \ - MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \ - /*GPIO_163 : TS_PENIRQ*/ \ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \ - /*GPIO_164 : MMC */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \ - \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \ - /* GPIO94 */\ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \ - /* GPIO95: #Enable Output */\ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \ - /* GPIO 99: #SOM_PWR_OFF */\ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \ - /* GPIO_100: #power out */\ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \ - /* GPIO_102 */\ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ - /* GPIO_170: auto update */\ - /* Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ - /* - GPIO30 */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ - MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ - \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \ - /* gpio_10 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ - /* JTAG */\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \ - MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \ - /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_stp */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ - /* hsusb1_clk */\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \ - /* gpio_24 */\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ - /* gpio_26 */\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ - /* gpio_29 */\ - /* Die to Die */\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ - -#endif diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig index 8a94cbd9edb..9e232527549 100644 --- a/board/theobroma-systems/puma_rk3399/Kconfig +++ b/board/theobroma-systems/puma_rk3399/Kconfig @@ -16,6 +16,6 @@ config ENV_SIZE default 0x2000 config ENV_OFFSET - default 0x3c000 if ENV_IS_IN_SPI_FLASH + default 0x3fc000 if ENV_IS_IN_SPI_FLASH endif diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 37a599768b1..6e1ede39339 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -93,6 +93,10 @@ static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { }; static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index 34c68ac4637..c9b05e44c24 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -71,7 +71,7 @@ pci_init_board(void) reg32 = 0xff000000; #endif if (clk->spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR + /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR * fields accordingly */ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 7c92f4f54c1..04941b26be4 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -72,13 +72,13 @@ int dram_init(void) int cs; /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); /* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS); set_cs_config(cs, INITIAL_CS_CONFIG); @@ -102,7 +102,7 @@ int dram_init(void) debug("\nDetecting Bank%d\n", cs); bank_size = get_ddr_bank_size(cs, - (long *)(CONFIG_SYS_DDR_BASE + size)); + (long *)(CONFIG_SYS_SDRAM_BASE + size)); size += bank_size; debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); @@ -235,8 +235,8 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); /* set OR0 and BR0 */ - set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM)); + set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | + OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM)); set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | (BR_MS_GPCM | BR_PS_32 | BR_V)); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index f0fc1fe3b31..1559ff210da 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -38,7 +38,7 @@ static long fixed_sdram(void) u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + (CONFIG_SYS_SDRAM_BASE & 0xfffff000)); out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -48,12 +48,12 @@ static long fixed_sdram(void) */ __udelay(50000); -#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) #warning Chip select bounds is only configurable in 16MB increments #endif out_be32(&im->ddr.csbnds[0].csbnds, - ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & CSBNDS_EA)); out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); @@ -80,7 +80,7 @@ static long fixed_sdram(void) /* now check the real size */ disable_addr_trans (); - msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans (); #endif @@ -100,8 +100,8 @@ int dram_init(void) msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + out_be32(&lbc->lbcr, 0x00040000); + out_be32(&lbc->mrtpr, 0x20000000); sync(); /* return total bus SDRAM size(bytes) -- DDR */ diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 69fbc8b6907..9d7a94ff9d9 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -46,6 +46,15 @@ DECLARE_GLOBAL_DATA_PTR; #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) #define REV_DETECTION IMX_GPIO_NR(2, 28) +/* Speed defined in Kconfig is only applicable when not using DM_I2C. */ +#ifdef CONFIG_DM_I2C +#define I2C1_SPEED_NON_DM 0 +#define I2C2_SPEED_NON_DM 0 +#else +#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED +#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED +#endif + static bool with_pmic; int dram_init(void) @@ -463,13 +472,13 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #if defined(CONFIG_VIDEO_IPUV3) - setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); if (is_mx6dq() || is_mx6dqp()) { - setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info); - setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info); + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info); + setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info); } else { - setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info); - setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info); + setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info); + setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info); } setup_display(); |