diff options
Diffstat (limited to 'board')
46 files changed, 966 insertions, 181 deletions
diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile index 341378b4e54..d1ef5cb8600 100644 --- a/board/CZ.NIC/turris_omnia/Makefile +++ b/board/CZ.NIC/turris_omnia/Makefile @@ -3,3 +3,5 @@ # Copyright (C) 2017 Marek Behún <kabel@kernel.org> obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o +obj-$(CONFIG_CMD_EEPROM_LAYOUT) += eeprom.o +obj-$(CONFIG_SPL_BUILD) += old_ddr3_training.o diff --git a/board/CZ.NIC/turris_omnia/eeprom.c b/board/CZ.NIC/turris_omnia/eeprom.c new file mode 100644 index 00000000000..6e2640ad2a7 --- /dev/null +++ b/board/CZ.NIC/turris_omnia/eeprom.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ + +#include <asm/unaligned.h> +#include <ctype.h> +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <eeprom_field.h> +#include <eeprom_layout.h> +#include <u-boot/crc.h> + +#define _DEF_FIELD(_n, _s, _t) \ + { _n, _s, NULL, eeprom_field_print_ ## _t, eeprom_field_update_ ## _t } + +static void eeprom_field_print_ramsz(const struct eeprom_field *field) +{ + printf(PRINT_FIELD_SEGMENT, field->name); + printf("%u\n", get_unaligned_le32(field->buf)); +} + +static int eeprom_field_update_ramsz(struct eeprom_field *field, char *value) +{ + u32 sz; + + if (value[0] == '1' || value[0] == '2' || value[0] == '4') + sz = value[0] - '0'; + else + return -1; + + if (value[1] != '\0') + return -1; + + put_unaligned_le32(sz, field->buf); + + return 0; +} + +static void eeprom_field_print_region(const struct eeprom_field *field) +{ + eeprom_field_print_ascii(field); +} + +static int eeprom_field_update_region(struct eeprom_field *field, char *value) +{ + if (strlen(value) != 2) { + printf("%s: has to be 2 characters\n", field->name); + return -1; + } + + memcpy(field->buf, value, 2); + memset(&field->buf[2], '\0', 2); + + return 0; +} + +static void eeprom_field_print_ddr_speed(const struct eeprom_field *field) +{ + printf(PRINT_FIELD_SEGMENT, field->name); + + if (field->buf[0] == '\0' || field->buf[0] == 0xff) + puts("(empty, defaults to 1600K)\n"); + else + printf("%.5s\n", field->buf); +} + +bool omnia_valid_ddr_speed(const char *name); +void omnia_print_ddr_speeds(void); + +static int eeprom_field_update_ddr_speed(struct eeprom_field *field, + char *value) +{ + if (value[0] == '\0') { + /* setting default value */ + memset(field->buf, 0xff, field->size); + + return 0; + } + + if (!omnia_valid_ddr_speed(value)) { + printf("%s: invalid setting, supported values are:\n ", + field->name); + omnia_print_ddr_speeds(); + + return -1; + } + + strncpy(field->buf, value, field->size); + + return 0; +} + +static void eeprom_field_print_bool(const struct eeprom_field *field) +{ + unsigned char val = field->buf[0]; + + printf(PRINT_FIELD_SEGMENT, field->name); + + if (val == 0xff) + puts("(empty, defaults to 0)\n"); + else + printf("%u\n", val); +} + +static int eeprom_field_update_bool(struct eeprom_field *field, char *value) +{ + unsigned char *val = &field->buf[0]; + + if (value[0] == '\0') { + /* setting default value */ + *val = 0xff; + + return 0; + } + + if (value[1] != '\0') + return -1; + + if (value[0] == '1' || value[0] == '0') + *val = value[0] - '0'; + else + return -1; + + return 0; +} + +static struct eeprom_field omnia_layout[] = { + _DEF_FIELD("Magic constant", 4, bin), + _DEF_FIELD("RAM size in GB", 4, ramsz), + _DEF_FIELD("Wi-Fi Region", 4, region), + _DEF_FIELD("CRC32 checksum", 4, bin), + _DEF_FIELD("DDR speed", 5, ddr_speed), + _DEF_FIELD("Use old DDR training", 1, bool), + _DEF_FIELD("Extended reserved fields", 38, reserved), + _DEF_FIELD("Extended CRC32 checksum", 4, bin), +}; + +static struct eeprom_field *crc_field = &omnia_layout[3]; +static struct eeprom_field *ext_crc_field = + &omnia_layout[ARRAY_SIZE(omnia_layout) - 1]; + +static int omnia_update_field(struct eeprom_layout *layout, char *field_name, + char *new_data) +{ + struct eeprom_field *field; + int err; + + if (!new_data) + return 0; + + if (!field_name) + return -1; + + field = eeprom_layout_find_field(layout, field_name, true); + if (!field) + return -1; + + err = field->update(field, new_data); + if (err) { + printf("Invalid data for field %s\n", field_name); + return err; + } + + if (field < crc_field) { + u32 crc = crc32(0, layout->data, 12); + put_unaligned_le32(crc, crc_field->buf); + } + + if (field < ext_crc_field) { + u32 crc = crc32(0, layout->data, 60); + put_unaligned_le32(crc, ext_crc_field->buf); + } + + return 0; +} + +void eeprom_layout_assign(struct eeprom_layout *layout, int) +{ + layout->fields = omnia_layout; + layout->num_of_fields = ARRAY_SIZE(omnia_layout); + layout->update = omnia_update_field; + layout->data_size = 64; +} + +int eeprom_layout_detect(unsigned char *) +{ + /* Turris Omnia has only one version of EEPROM layout */ + return 0; +} diff --git a/board/CZ.NIC/turris_omnia/old_ddr3_training.c b/board/CZ.NIC/turris_omnia/old_ddr3_training.c new file mode 100644 index 00000000000..cdb3487ad9e --- /dev/null +++ b/board/CZ.NIC/turris_omnia/old_ddr3_training.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ + +#include <asm/arch/soc.h> +#include <asm/io.h> + +#include "../drivers/ddr/marvell/a38x/old/ddr3_init.h" + +static struct hws_topology_map board_topology_map_1g = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_NORMAL, /* temperature */ + HWS_TIM_2T} }, /* timing (force 2t) */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +static struct hws_topology_map board_topology_map_2g = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_8G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_NORMAL, /* temperature */ + HWS_TIM_2T} }, /* timing (force 2t) */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +/* defined in turris_omnia.c */ +extern int omnia_get_ram_size_gb(void); + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + if (omnia_get_ram_size_gb() == 2) + return &board_topology_map_2g; + else + return &board_topology_map_1g; +} + +__weak u32 sys_env_get_topology_update_info(struct topology_update_info *tui) +{ + return MV_OK; +} diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 4ee1a394b02..2f29d26edf8 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -429,12 +429,42 @@ struct omnia_eeprom { u32 ramsize; char region[4]; u32 crc; + + /* second part (only considered if crc2 is not all-ones) */ + char ddr_speed[5]; + u8 old_ddr_training; + u8 reserved[38]; + u32 crc2; }; +static bool is_omnia_eeprom_second_part_valid(const struct omnia_eeprom *oep) +{ + return oep->crc2 != 0xffffffff; +} + +static void make_omnia_eeprom_second_part_invalid(struct omnia_eeprom *oep) +{ + oep->crc2 = 0xffffffff; +} + +static bool check_eeprom_crc(const void *buf, size_t size, u32 expected, + const char *name) +{ + u32 crc; + + crc = crc32(0, buf, size); + if (crc != expected) { + printf("bad %s EEPROM CRC (stored %08x, computed %08x)\n", + name, expected, crc); + return false; + } + + return true; +} + static bool omnia_read_eeprom(struct omnia_eeprom *oep) { struct udevice *chip; - u32 crc; int ret; chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, @@ -455,17 +485,19 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep) return false; } - crc = crc32(0, (void *)oep, sizeof(*oep) - 4); - if (crc != oep->crc) { - printf("bad EEPROM CRC (stored %08x, computed %08x)\n", - oep->crc, crc); + if (!check_eeprom_crc(oep, offsetof(struct omnia_eeprom, crc), oep->crc, + "first")) return false; - } + + if (is_omnia_eeprom_second_part_valid(oep) && + !check_eeprom_crc(oep, offsetof(struct omnia_eeprom, crc2), + oep->crc2, "second")) + make_omnia_eeprom_second_part_invalid(oep); return true; } -static int omnia_get_ram_size_gb(void) +int omnia_get_ram_size_gb(void) { static int ram_size; struct omnia_eeprom oep; @@ -490,6 +522,39 @@ static int omnia_get_ram_size_gb(void) return ram_size; } +bool board_use_old_ddr3_training(void) +{ + struct omnia_eeprom oep; + + if (!omnia_read_eeprom(&oep)) + return false; + + if (!is_omnia_eeprom_second_part_valid(&oep)) + return false; + + return oep.old_ddr_training == 1; +} + +static const char *omnia_get_ddr_speed(void) +{ + struct omnia_eeprom oep; + static char speed[sizeof(oep.ddr_speed) + 1]; + + if (!omnia_read_eeprom(&oep)) + return NULL; + + if (!is_omnia_eeprom_second_part_valid(&oep)) + return NULL; + + if (!oep.ddr_speed[0] || oep.ddr_speed[0] == 0xff) + return NULL; + + memcpy(&speed, &oep.ddr_speed, sizeof(oep.ddr_speed)); + speed[sizeof(speed) - 1] = '\0'; + + return speed; +} + static const char * const omnia_get_mcu_type(void) { static char result[] = "xxxxxxx (with peripheral resets)"; @@ -604,12 +669,84 @@ static struct mv_ddr_topology_map board_topology_map_2g = { {0} /* timing parameters */ }; +static const struct omnia_ddr_speed { + char name[5]; + u8 speed_bin; + u8 freq; +} omnia_ddr_speeds[] = { + { "1066F", SPEED_BIN_DDR_1066F, MV_DDR_FREQ_533 }, + { "1333H", SPEED_BIN_DDR_1333H, MV_DDR_FREQ_667 }, + { "1600K", SPEED_BIN_DDR_1600K, MV_DDR_FREQ_800 }, +}; + +static const struct omnia_ddr_speed *find_ddr_speed_setting(const char *name) +{ + for (int i = 0; i < ARRAY_SIZE(omnia_ddr_speeds); ++i) + if (!strncmp(name, omnia_ddr_speeds[i].name, 5)) + return &omnia_ddr_speeds[i]; + + return NULL; +} + +bool omnia_valid_ddr_speed(const char *name) +{ + return find_ddr_speed_setting(name) != NULL; +} + +void omnia_print_ddr_speeds(void) +{ + for (int i = 0; i < ARRAY_SIZE(omnia_ddr_speeds); ++i) + printf("%.5s%s", omnia_ddr_speeds[i].name, + i == ARRAY_SIZE(omnia_ddr_speeds) - 1 ? "\n" : ", "); +} + +static void fixup_speed_in_ddr_topology(struct mv_ddr_topology_map *topology) +{ + typeof(topology->interface_params[0]) *params; + const struct omnia_ddr_speed *setting; + const char *speed; + static bool done; + + if (done) + return; + + done = true; + + speed = omnia_get_ddr_speed(); + if (!speed) + return; + + setting = find_ddr_speed_setting(speed); + if (!setting) { + printf("Unsupported value %s for DDR3 speed in EEPROM!\n", + speed); + return; + } + + params = &topology->interface_params[0]; + + /* don't inform if we are not changing the speed from the default one */ + if (params->speed_bin_index == setting->speed_bin) + return; + + printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed); + + params->speed_bin_index = setting->speed_bin; + params->memory_freq = setting->freq; +} + struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) { + struct mv_ddr_topology_map *topology; + if (omnia_get_ram_size_gb() == 2) - return &board_topology_map_2g; + topology = &board_topology_map_2g; else - return &board_topology_map_1g; + topology = &board_topology_map_1g; + + fixup_speed_in_ddr_topology(topology); + + return topology; } static int set_regdomain(void) @@ -978,11 +1115,21 @@ static int fixup_mcu_gpio_in_pcie_nodes(void *blob) return 0; } -static int fixup_mcu_gpio_in_eth_wan_node(void *blob) +static int get_phy_wan_node_offset(const void *blob) +{ + u32 phy_wan_phandle; + + phy_wan_phandle = fdt_getprop_u32_default(blob, "ethernet2", "phy-handle", 0); + if (!phy_wan_phandle) + return -FDT_ERR_NOTFOUND; + + return fdt_node_offset_by_phandle(blob, phy_wan_phandle); +} + +static int fixup_mcu_gpio_in_phy_wan_node(void *blob) { unsigned int mcu_phandle; - int eth_wan_node; - int ret; + int phy_wan_node, ret; ret = fdt_increase_size(blob, 64); if (ret < 0) { @@ -990,21 +1137,17 @@ static int fixup_mcu_gpio_in_eth_wan_node(void *blob) return ret; } - eth_wan_node = fdt_path_offset(blob, "ethernet2"); - if (eth_wan_node < 0) - return eth_wan_node; + phy_wan_node = get_phy_wan_node_offset(blob); + if (phy_wan_node < 0) + return phy_wan_node; mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu"); if (!mcu_phandle) return -FDT_ERR_NOPHANDLES; - /* insert: phy-reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ - ret = insert_mcu_gpio_prop(blob, eth_wan_node, "phy-reset-gpios", - mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW); - if (ret < 0) - return ret; - - return 0; + /* insert: reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ + return insert_mcu_gpio_prop(blob, phy_wan_node, "reset-gpios", + mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW); } static void fixup_atsha_node(void *blob) @@ -1033,7 +1176,7 @@ int board_fix_fdt(void *blob) { if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) { fixup_mcu_gpio_in_pcie_nodes(blob); - fixup_mcu_gpio_in_eth_wan_node(blob); + fixup_mcu_gpio_in_phy_wan_node(blob); } fixup_msata_port_nodes(blob); @@ -1218,14 +1361,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) int node; /* - * U-Boot's FDT blob contains phy-reset-gpios in ethernet2 - * node when MCU controls all peripherals resets. + * U-Boot's FDT blob contains reset-gpios in ethernet2 PHY node when MCU + * controls all peripherals resets. * Fixup MCU GPIO nodes in PCIe and eth wan nodes in this case. */ - node = fdt_path_offset(gd->fdt_blob, "ethernet2"); - if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "phy-reset-gpios", NULL)) { + node = get_phy_wan_node_offset(gd->fdt_blob); + if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "reset-gpios", NULL)) { fixup_mcu_gpio_in_pcie_nodes(blob); - fixup_mcu_gpio_in_eth_wan_node(blob); + fixup_mcu_gpio_in_phy_wan_node(blob); } fixup_spi_nor_partitions(blob); diff --git a/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS index 9b0afeef106..e96499e1612 100644 --- a/board/Marvell/mvebu_armada-37xx/MAINTAINERS +++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS @@ -9,3 +9,8 @@ ESPRESSOBin BOARD M: Konstantin Porotchkin <kostap@marvell.com> S: Maintained F: configs/mvebu_espressobin-88f3720_defconfig + +ESPRESSOBin Ultra BOARD +M: Ben Schneider <ben@bens.haus> +S: Maintained +F: configs/mvebu_espressobin_ultra-88f3720_defconfig diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c index fbd99918a7f..56ae39bc6a1 100644 --- a/board/amd/versal2/cmds.c +++ b/board/amd/versal2/cmds.c @@ -71,10 +71,9 @@ static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, return cmd_process_error(cmdtp, ret); } -static char versal2_help_text[] = +U_BOOT_LONGHELP(versal2, "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n" -; + "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text, U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index 099eea60c39..5c57b902d14 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,14 +6,12 @@ #include <abuf.h> #include <adc.h> #include <asm/io.h> -#include <command.h> #include <display.h> #include <dm.h> #include <dm/lists.h> #include <env.h> #include <fdt_support.h> #include <linux/delay.h> -#include <linux/iopoll.h> #include <mipi_dsi.h> #include <mmc.h> #include <panel.h> @@ -21,8 +19,6 @@ #include <stdlib.h> #include <video_bridge.h> -#define BOOT_BROM_DOWNLOAD 0xef08a53c - #define GPIO0_BASE 0xfdd60000 #define GPIO4_BASE 0xfe770000 #define GPIO_SWPORT_DR_L 0x0000 @@ -36,14 +32,6 @@ #define GPIO_WRITEMASK(bits) ((bits) << 16) -#define SARADC_BASE 0xfe720000 -#define SARADC_DATA 0x0000 -#define SARADC_STAS 0x0004 -#define SARADC_ADC_STATUS BIT(0) -#define SARADC_CTRL 0x0008 -#define SARADC_INPUT_SRC_MSK 0x7 -#define SARADC_POWER_CTRL BIT(3) - #define DTB_DIR "rockchip/" struct rg3xx_model { @@ -170,63 +158,11 @@ static const struct rg353_panel rg353_panel_details[] = { }; /* - * The device has internal eMMC, and while some devices have an exposed - * clk pin you can ground to force a bypass not all devices do. As a - * result it may be possible for some devices to become a perma-brick - * if a corrupted TPL or SPL stage with a valid header is flashed to - * the internal eMMC. Add functionality to read ADC channel 0 (the func - * button) as early as possible in the boot process to provide some - * protection against this. If we ever get an open TPL stage, we should - * consider moving this function there. - */ -void read_func_button(void) -{ - int ret; - u32 reg; - - /* Turn off SARADC to reset it. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* Enable channel 0 and power on SARADC. */ - writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL), - (SARADC_BASE + SARADC_CTRL)); - - /* - * Wait for data to be ready. Use timeout of 20000us from - * rockchip_saradc driver. - */ - ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg, - !(reg & SARADC_ADC_STATUS), 20000); - if (ret) { - printf("ADC Timeout"); - return; - } - - /* Read the data from the SARADC. */ - reg = readl((SARADC_BASE + SARADC_DATA)); - - /* Turn the SARADC back off so it's ready to be used again. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* - * If the value is less than 30 the button is being pressed. - * Reset the device back into Rockchip download mode. - */ - if (reg <= 30) { - printf("download key pressed, entering download mode..."); - writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); - do_reset(NULL, 0, 0, NULL); - } -}; - -/* * Start LED very early so user knows device is on. Set color * to red. */ void spl_board_init(void) { - read_func_button(); - /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ (GPIO_C7 | GPIO_C6 | GPIO_C5), diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig new file mode 100644 index 00000000000..d5fe4128289 --- /dev/null +++ b/board/asus/transformer-t20/Kconfig @@ -0,0 +1,12 @@ +if TARGET_TRANSFORMER_T20 + +config SYS_BOARD + default "transformer-t20" + +config SYS_VENDOR + default "asus" + +config SYS_CONFIG_NAME + default "transformer-t20" + +endif diff --git a/board/asus/transformer-t20/MAINTAINERS b/board/asus/transformer-t20/MAINTAINERS new file mode 100644 index 00000000000..7bf93570985 --- /dev/null +++ b/board/asus/transformer-t20/MAINTAINERS @@ -0,0 +1,8 @@ +TRANSFORMER T20 BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: arch/arm/dts/tegra20-asus-* +F: board/asus/transformer-t20/ +F: configs/transformer_t20_defconfig +F: doc/board/asus/transformer_t20.rst +F: include/configs/transformer-t20.h diff --git a/board/asus/transformer-t20/Makefile b/board/asus/transformer-t20/Makefile new file mode 100644 index 00000000000..8522f82c2bd --- /dev/null +++ b/board/asus/transformer-t20/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-y += transformer-t20.o diff --git a/board/asus/transformer-t20/configs/sl101.config b/board/asus/transformer-t20/configs/sl101.config new file mode 100644 index 00000000000..4f639e1b412 --- /dev/null +++ b/board/asus/transformer-t20/configs/sl101.config @@ -0,0 +1 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101" diff --git a/board/asus/transformer-t20/configs/tf101.config b/board/asus/transformer-t20/configs/tf101.config new file mode 100644 index 00000000000..44a1d1a3c10 --- /dev/null +++ b/board/asus/transformer-t20/configs/tf101.config @@ -0,0 +1 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101" diff --git a/board/asus/transformer-t20/configs/tf101g.config b/board/asus/transformer-t20/configs/tf101g.config new file mode 100644 index 00000000000..0ccf2498ccd --- /dev/null +++ b/board/asus/transformer-t20/configs/tf101g.config @@ -0,0 +1 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101g" diff --git a/board/asus/transformer-t20/transformer-t20.c b/board/asus/transformer-t20/transformer-t20.c new file mode 100644 index 00000000000..42fc563a0bf --- /dev/null +++ b/board/asus/transformer-t20/transformer-t20.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* T20 Transformers derive from Ventana board */ + +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/delay.h> + +#define TPS6586X_I2C_ADDRESS 0x34 +#define TPS6586X_SUPPLYENE 0x14 +#define EXITSLREQ_BIT BIT(1) +#define SLEEP_MODE_BIT BIT(3) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] &= ~EXITSLREQ_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= SLEEP_MODE_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + printf("Failed to power off!!!\n"); + return 1; +} +#endif diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig index b0e67dc8ef3..592b53e493c 100644 --- a/board/beagle/beagleplay/Kconfig +++ b/board/beagle/beagleplay/Kconfig @@ -12,6 +12,7 @@ config TARGET_AM625_A53_BEAGLEPLAY bool "BeagleBoard.org AM625 BeaglePlay running on A53" select ARM64 select BINMAN + select OF_SYSTEM_SETUP config TARGET_AM625_R5_BEAGLEPLAY bool "BeagleBoard.org AM625 BeaglePlay running on R5" diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index 8dbfc2f7d24..354bc987d12 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -12,7 +12,7 @@ set_led_state_start_load=led led-0 on; led led-1 off; led led-2 on; led led-3 off; led led-4 on boot=mmc mmcdev=1 -bootpart=1:1 +bootpart=1:2 bootdir=/boot boot_targets=mmc1 mmc0 bootmeths=script extlinux efi pxe diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c index 0da641834d4..33452d2ad5b 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610040 }, + { 0x3d400064, 0x300040 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400498, 0x7ff }, { 0x3d40049c, 0xe00 }, { 0x3d4004a0, 0x7ff }, - { 0x3d402064, 0x28001b }, + { 0x3d402064, 0x14001b }, { 0x3d4020dc, 0x12200004 }, - { 0x3d4020e0, 0x0 }, - { 0x3d402100, 0x7090b07 }, + { 0x3d4020e0, 0x400000 }, + { 0x3d402100, 0x7090507 }, { 0x3d402104, 0x20209 }, { 0x3d402108, 0x3030407 }, { 0x3d40210c, 0x2006 }, @@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x31f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1d70 }, { 0x54030, 0x4 }, - { 0x54031, 0x18 }, + { 0x54031, 0x58 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c index f845395ad97..ca14a474429 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610068 }, + { 0x3d400064, 0x300068 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -700,11 +700,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +888,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index 5110fed3119..6b92fe31c0e 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -66,6 +66,11 @@ unsigned long get_board_sys_clk(void) #endif } +int dram_init(void) +{ + return 0; +} + int board_postclk_init(void) { gd->cpu_clk = get_board_sys_clk(); diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index ebd45f9053f..4f4f537fee5 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -76,14 +76,25 @@ static bool dh_stm32_mac_is_in_ks8851(void) { - ofnode node; + struct udevice *udev; u32 reg, cider, ccr; + char path[256]; + ofnode node; + int ret; node = ofnode_path("ethernet1"); if (!ofnode_valid(node)) return false; - if (ofnode_device_is_compatible(node, "micrel,ks8851-mll")) + ret = ofnode_get_path(node, path, sizeof(path)); + if (ret) + return false; + + ret = uclass_get_device_by_of_path(UCLASS_ETH, path, &udev); + if (ret) + return false; + + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) return false; /* diff --git a/board/emulation/qemu-xtensa/Kconfig b/board/emulation/qemu-xtensa/Kconfig new file mode 100644 index 00000000000..8767b6fabbd --- /dev/null +++ b/board/emulation/qemu-xtensa/Kconfig @@ -0,0 +1,43 @@ +if TARGET_QEMU_XTENSA + +config SYS_BOARD + default "qemu-xtensa" + +config SYS_VENDOR + default "emulation" + +config SYS_CONFIG_NAME + default "qemu-xtensa" + +config TEXT_BASE + default 0x50000000 if (SYS_CPU = de212) + default 0xfe000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_EARLY_INIT_F + select DM + select CPU + select CPU_XTENSA + select CLK + select DM_SERIAL + select XTENSA_SEMIHOSTING + select XTENSA_SEMIHOSTING_SERIAL + imply BLK + imply VIRTIO + imply VIRTIO_PCI + imply VIRTIO_NET + imply VIRTIO_BLK + imply E1000 + imply PCI + imply PCI_INIT_R + imply NVME_PCI + imply PCIE_ECAM_GENERIC + imply SCSI + imply REMAKE_ELF + select OF_CONTROL + select OF_UPSTREAM + imply CMD_DM + imply CMD_PCI + +endif diff --git a/board/emulation/qemu-xtensa/MAINTAINERS b/board/emulation/qemu-xtensa/MAINTAINERS new file mode 100644 index 00000000000..6ffdfe85dee --- /dev/null +++ b/board/emulation/qemu-xtensa/MAINTAINERS @@ -0,0 +1,8 @@ +QEMU XTENSA 'VIRT' BOARD +M: Jiaxun Yang <jiaxun.yang@flygoat.com> +M: Max Filippov <jcmvbkbc@gmail.com> +S: Maintained +F: board/emulation/qemu-xtensa/ +F: board/emulation/common/ +F: include/configs/qemu-xtensa.h +F: configs/qemu-xtensa-dc233c_defconfig diff --git a/board/emulation/qemu-xtensa/Makefile b/board/emulation/qemu-xtensa/Makefile new file mode 100644 index 00000000000..0f33a65f6c6 --- /dev/null +++ b/board/emulation/qemu-xtensa/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024, Jiaxun Yang <jiaxun.yang@flygoat.com> + +obj-y += qemu-xtensa.o diff --git a/board/emulation/qemu-xtensa/qemu-xtensa.c b/board/emulation/qemu-xtensa/qemu-xtensa.c new file mode 100644 index 00000000000..0ca83341c25 --- /dev/null +++ b/board/emulation/qemu-xtensa/qemu-xtensa.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <dm.h> +#include <cpu.h> +#include <log.h> +#include <init.h> +#include <usb.h> +#include <virtio_types.h> +#include <virtio.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return gd->cpu_clk ? gd->cpu_clk : 40000000; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int board_early_init_f(void) +{ + struct cpu_plat *cpu_plat; + struct udevice *cpu = cpu_get_current_dev(); + + if (!cpu) + return -ENODEV; + + cpu_plat = dev_get_parent_plat(cpu); + if (!cpu_plat) + return -ENODEV; + + gd->cpu_clk = cpu_plat->timebase_freq; + return 0; +} + +int board_late_init(void) +{ + /* start usb so that usb keyboard can be used as input device */ + if (CONFIG_IS_ENABLED(USB_KEYBOARD)) + usb_init(); + + /* + * Make sure virtio bus is enumerated so that peripherals + * on the virtio bus can be discovered by their drivers + */ + virtio_init(); + + return 0; +} diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index d4192e5ab52..3344653ba2d 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -63,14 +63,14 @@ static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc, } /***************************************************/ -static char esbc_validate_help_text[] = +U_BOOT_LONGHELP(esbc_validate, "esbc_validate hdr_addr <hash_val> - Validates signature using\n" " RSA verification\n" " $hdr_addr Address of header of the image\n" " to be validated.\n" " $hash_val -Optional\n" " It provides Hash of public/srk key to be\n" - " used to verify signature.\n"; + " used to verify signature.\n"); U_BOOT_CMD( esbc_validate, 3, 0, do_esbc_validate, diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 53c3435c92f..bd8ce633772 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -28,44 +28,38 @@ static int veyron_init(void) int ret; ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } + if (ret) + return log_msg_ret("vdd", ret); /* Slowly raise to max CPU voltage to prevent overshoot */ ret = regulator_set_value(dev, 1200000); if (ret) - return ret; + return log_msg_ret("s12", ret); udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ ret = regulator_set_value(dev, 1400000); if (ret) - return ret; + return log_msg_ret("s14", ret); udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ ret = rockchip_get_clk(&clk.dev); if (ret) - return ret; + return log_msg_ret("clk", ret); clk.id = PLL_APLL; ret = clk_set_rate(&clk, 1800000000); if (IS_ERR_VALUE(ret)) - return ret; + return log_msg_ret("s18", ret); ret = regulator_get_by_platname("vcc33_sd", &dev); - if (ret) { - debug("Cannot get regulator name\n"); - return ret; - } + if (ret) + return log_msg_ret("vcc", ret); ret = regulator_set_value(dev, 3300000); if (ret) - return ret; + return log_msg_ret("s33", ret); ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("boo", ret); return 0; } @@ -80,7 +74,7 @@ int board_early_init_r(void) if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { ret = veyron_init(); if (ret) - return ret; + return log_msg_ret("vey", ret); } #endif /* diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c index 7851361c48c..07514778753 100644 --- a/board/kontron/sl28/cmds.c +++ b/board/kontron/sl28/cmds.c @@ -172,8 +172,8 @@ out: return CMD_RET_FAILURE; } -static char sl28_help_text[] = - "nvm [<hex>] - display/set the 16 non-volatile bits\n"; +U_BOOT_LONGHELP(sl28, + "nvm [<hex>] - display/set the 16 non-volatile bits\n"); U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text, U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm)); diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig new file mode 100644 index 00000000000..67644409fc1 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IDEAPAD_YOGA_11 + +config SYS_BOARD + default "ideapad-yoga-11" + +config SYS_VENDOR + default "lenovo" + +config SYS_CONFIG_NAME + default "ideapad-yoga-11" + +endif diff --git a/board/lenovo/ideapad-yoga-11/MAINTAINERS b/board/lenovo/ideapad-yoga-11/MAINTAINERS new file mode 100644 index 00000000000..77e82534a95 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/MAINTAINERS @@ -0,0 +1,7 @@ +Lenovo Ideapad Yoga 11 +M: Jonas Schwöbel <jonasschwoebel@yahoo.de> +S: Maintained +F: board/lenovo/ideapad-yoga-11/ +F: configs/ideapad-yoga-11_defconfig +F: doc/board/lenovo/ideapad-yoga-11.rst +F: include/configs/ideapad-yoga-11.h diff --git a/board/lenovo/ideapad-yoga-11/Makefile b/board/lenovo/ideapad-yoga-11/Makefile new file mode 100644 index 00000000000..186f1cb4ee5 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 +# Open Surface RT + +obj-$(CONFIG_SPL_BUILD) += ideapad-yoga-11-spl.o diff --git a/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c new file mode 100644 index 00000000000..b8b3964a708 --- /dev/null +++ b/board/lenovo/ideapad-yoga-11/ideapad-yoga-11-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ideapad Yoga 11 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET2_REG 0x02 +#define TPS62361B_SET2_DATA (0x4600 | TPS62361B_SET2_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET2_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS index 22f3b97d8b1..d092b5a8111 100644 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ b/board/microchip/mpfs_icicle/MAINTAINERS @@ -1,5 +1,5 @@ Microchip MPFS icicle -M: Padmarao Begari <padmarao.begari@microchip.com> +M: Conor Dooley <conor.dooley@microchip.com> M: Cyril Jean <cyril.jean@microchip.com> S: Maintained F: board/microchip/mpfs_icicle/ diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig new file mode 100644 index 00000000000..9e66897f6b1 --- /dev/null +++ b/board/microsoft/surface-rt/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SURFACE_RT + +config SYS_BOARD + default "surface-rt" + +config SYS_VENDOR + default "microsoft" + +config SYS_CONFIG_NAME + default "surface-rt" + +endif diff --git a/board/microsoft/surface-rt/MAINTAINERS b/board/microsoft/surface-rt/MAINTAINERS new file mode 100644 index 00000000000..1bbd896de92 --- /dev/null +++ b/board/microsoft/surface-rt/MAINTAINERS @@ -0,0 +1,7 @@ +Microsoft Surface RT +M: Jonas Schwöbel <jonasschwoebel@yahoo.de> +S: Maintained +F: board/microsoft/surface-rt/ +F: configs/surface-rt_defconfig +F: doc/board/microsoft/surface-rt.rst +F: include/configs/surface-rt.h diff --git a/board/microsoft/surface-rt/Makefile b/board/microsoft/surface-rt/Makefile new file mode 100644 index 00000000000..da4094a7df3 --- /dev/null +++ b/board/microsoft/surface-rt/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2021 +# Open Surface RT + +obj-$(CONFIG_SPL_BUILD) += surface-rt-spl.o diff --git a/board/microsoft/surface-rt/surface-rt-spl.c b/board/microsoft/surface-rt/surface-rt-spl.c new file mode 100644 index 00000000000..f327a80efba --- /dev/null +++ b/board/microsoft/surface-rt/surface-rt-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Surface RT SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/qualcomm/default.env b/board/qualcomm/default.env new file mode 100644 index 00000000000..dbf6f4e7260 --- /dev/null +++ b/board/qualcomm/default.env @@ -0,0 +1,11 @@ +stdin=serial,button-kbd +stdout=serial,vidconsole +stderr=serial,vidconsole +preboot=scsi scan; usb start +fastboot=fastboot -l $fastboot_addr_r usb 0 +do_boot=bootefi bootmgr +bootmenu_0=Boot first available device=run do_boot +bootmenu_1=Enable fastboot mode=run fastboot +bootmenu_2=Reset device=reset +menucmd=bootmenu +bootcmd=run do_boot diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index 219c8715bf1..ed8800a2663 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -3,6 +3,5 @@ M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/am335x/ F: include/configs/am335x_evm.h -F: configs/am335x_boneblack_vboot_defconfig F: configs/am335x_evm_defconfig F: configs/am335x_evm_spiboot_defconfig diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 4230f417d19..9359e0ac6bf 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -126,6 +126,35 @@ int board_phys_sdram_size(phys_size_t *size) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { + const char *canoscpath = "/oscillator"; + int freq = 40000000; /* 40 MHz is used on most variants */ + int canoscoff, ret; + + canoscoff = fdt_path_offset(blob, canoscpath); + if (canoscoff < 0) /* No CAN oscillator found. */ + goto exit; + + /* + * The following "prodid" (PID4 in Toradex naming) use + * a 20MHz CAN oscillator: + * - 0055, V1.1A, V1.1B, V1.1C and V1.1D + * - 0059, V1.1A and V1.1B + */ + if ((tdx_hw_tag.ver_major == 1 && tdx_hw_tag.ver_minor == 1) && + ((tdx_hw_tag.prodid == VERDIN_IMX8MMQ_IT && + tdx_hw_tag.ver_assembly <= 1) || /* 0059 rev. A or B */ + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT && + tdx_hw_tag.ver_assembly <= 3))) { /* 0055 rev. A/B/C/D */ + freq = 20000000; + } + + ret = fdt_setprop_u32(blob, canoscoff, "clock-frequency", freq); + if (ret < 0) { + printf("Failed to set CAN oscillator clock-frequency, ret=%d\n", + ret); + } + +exit: return ft_common_board_setup(blob, bd); } #endif diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig new file mode 100644 index 00000000000..45a1e5e057b --- /dev/null +++ b/board/wexler/qc750/Kconfig @@ -0,0 +1,12 @@ +if TARGET_QC750 + +config SYS_BOARD + default "qc750" + +config SYS_VENDOR + default "wexler" + +config SYS_CONFIG_NAME + default "qc750" + +endif diff --git a/board/wexler/qc750/MAINTAINERS b/board/wexler/qc750/MAINTAINERS new file mode 100644 index 00000000000..017f6f2b707 --- /dev/null +++ b/board/wexler/qc750/MAINTAINERS @@ -0,0 +1,7 @@ +QC750 BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/wexler/qc750/ +F: configs/qc750_defconfig +F: doc/board/wexler/qc750.rst +F: include/configs/qc750.h diff --git a/board/wexler/qc750/Makefile b/board/wexler/qc750/Makefile new file mode 100644 index 00000000000..4daefc4159a --- /dev/null +++ b/board/wexler/qc750/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2023 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_SPL_BUILD) += qc750-spl.o + +obj-y += qc750.o diff --git a/board/wexler/qc750/qc750-spl.c b/board/wexler/qc750/qc750-spl.c new file mode 100644 index 00000000000..707be7779eb --- /dev/null +++ b/board/wexler/qc750/qc750-spl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 QC750 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define MAX77663_I2C_ADDR (0x3c << 1) + +#define MAX77663_REG_SD0 0x16 +#define MAX77663_REG_SD0_DATA (0x2100 | MAX77663_REG_SD0) +#define MAX77663_REG_SD1 0x17 +#define MAX77663_REG_SD1_DATA (0x3000 | MAX77663_REG_SD1) +#define MAX77663_REG_LDO4 0x2b +#define MAX77663_REG_LDO4_DATA (0xE000 | MAX77663_REG_LDO4) + +#define MAX77663_REG_GPIO4 0x3a +#define MAX77663_REG_GPIO4_DATA (0x0100 | MAX77663_REG_GPIO4) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA); + + udelay(1000); + + /* Bring up VDD_CPU to 1.0125V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD0_DATA); + udelay(1000); + + /* Bring up VDD_RTC to 1.200V. */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_LDO4_DATA); + udelay(10 * 1000); + + /* Set 32k-out gpio state */ + tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA); +} diff --git a/board/wexler/qc750/qc750.c b/board/wexler/qc750/qc750.c new file mode 100644 index 00000000000..5234211aea3 --- /dev/null +++ b/board/wexler/qc750/qc750.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <fdt_support.h> + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 30a81376ac4..0b43407b9e9 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -701,11 +701,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) #define MAX_RAND_SIZE 8 int ft_board_setup(void *blob, struct bd_info *bd) { - size_t n = MAX_RAND_SIZE; - struct udevice *dev; - u8 buf[MAX_RAND_SIZE]; - int nodeoffset, ret; - static const struct node_info nodes[] = { { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, }, }; @@ -713,41 +708,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ)) fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { - debug("No RNG device\n"); - return 0; - } - - if (dm_rng_read(dev, buf, n)) { - debug("Reading RNG failed\n"); - return 0; - } - - if (!blob) { - debug("No FDT memory address configured. Please configure\n" - "the FDT address via \"fdt addr <address>\" command.\n" - "Aborting!\n"); - return 0; - } - - ret = fdt_check_header(blob); - if (ret < 0) { - debug("fdt_chosen: %s\n", fdt_strerror(ret)); - return ret; - } - - nodeoffset = fdt_find_or_add_subnode(blob, 0, "chosen"); - if (nodeoffset < 0) { - debug("Reading chosen node failed\n"); - return nodeoffset; - } - - ret = fdt_setprop(blob, nodeoffset, "kaslr-seed", buf, sizeof(buf)); - if (ret < 0) { - debug("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret)); - return ret; - } - return 0; } #endif diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c index 4d52084846b..e8b669f0fd4 100644 --- a/board/xilinx/versal-net/cmds.c +++ b/board/xilinx/versal-net/cmds.c @@ -71,10 +71,9 @@ static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, return cmd_process_error(cmdtp, ret); } -static char versalnet_help_text[] = +U_BOOT_LONGHELP(versalnet, "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n" -; + "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text, U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, |