diff options
Diffstat (limited to 'board')
36 files changed, 1179 insertions, 669 deletions
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index 153ed0e963b..144a08922b1 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -22,8 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; #if IS_ENABLED(CONFIG_VIDEO_VCXK) -unsigned long display_width; -unsigned long display_height; +extern unsigned long display_width; +extern unsigned long display_height; #endif /*---------------------------------------------------------------------------*/ diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 380e37be550..fb691931580 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -140,6 +140,7 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ +#if CONFIG_IS_ENABLED(BOOTSTAGE) #define GREEN_LED (1 << 14) #define ORANGE_LED (1 << 15) #define BOTH_LEDS (GREEN_LED | ORANGE_LED) @@ -169,3 +170,4 @@ void show_boot_progress(int val) break; } } +#endif diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index 4c19fa7195e..af8cab7bdc7 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -142,6 +142,7 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ +#if CONFIG_IS_ENABLED(BOOTSTAGE) #define GREEN_LED (1 << 14) #define ORANGE_LED (1 << 15) #define BOTH_LEDS (GREEN_LED | ORANGE_LED) @@ -175,3 +176,4 @@ void show_boot_progress(int val) break; } } +#endif diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile index 8c906e3f072..107e59bf0fa 100644 --- a/board/armltd/integrator/Makefile +++ b/board/armltd/integrator/Makefile @@ -10,5 +10,4 @@ obj-y := lowlevel_init.o obj-y += integrator.o -obj-$(CONFIG_PCI) += pci.o obj-y += timer.o diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 3e864e8e7a5..388795809df 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -181,7 +181,6 @@ int board_eth_init(struct bd_info *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif - rc += pci_eth_init(bis); return rc; } #endif diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c deleted file mode 100644 index 28efc33f1f4..00000000000 --- a/board/armltd/integrator/pci.c +++ /dev/null @@ -1,462 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2003 - * Texas Instruments, <www.ti.com> - * Kshitij Gupta <Kshitij@ti.com> - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, <philippe.robin@arm.com> - * - * (C) Copyright 2011 - * Linaro - * Linus Walleij <linus.walleij@linaro.org> - */ -#include <common.h> -#include <init.h> -#include <log.h> -#include <pci.h> -#include <asm/io.h> -#include <linux/bug.h> -#include <linux/delay.h> -#include "integrator-sc.h" -#include "pci_v3.h" - -#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 - -/* - * These are in the physical addresses on the CPU side, i.e. - * where we read and write stuff - you don't want to try to - * move these around - */ -#define PHYS_PCI_MEM_BASE 0x40000000 -#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ -#define PHYS_PCI_CONFIG_BASE 0x61000000 -#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ -#define SZ_256M 0x10000000 - -/* - * These are in the PCI BUS address space - * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor - * we follow the example of the kernel, because that is the address - * range that devices actually use - what would they be doing at - * 0x40000000? - */ -#define PCI_BUS_NONMEM_START 0x00000000 -#define PCI_BUS_NONMEM_SIZE SZ_256M - -#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) -#define PCI_BUS_PREMEM_SIZE SZ_256M - -#if PCI_BUS_NONMEM_START & 0x000fffff -#error PCI_BUS_NONMEM_START must be megabyte aligned -#endif -#if PCI_BUS_PREMEM_START & 0x000fffff -#error PCI_BUS_PREMEM_START must be megabyte aligned -#endif - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ -#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ -static struct pci_config_table pci_integrator_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif /* CONFIG_PCI_PNP */ - -/* V3 access routines */ -#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) -{ - unsigned int address, mapaddress; - unsigned int busnr = PCI_BUS(bdf); - unsigned int devfn = PCI_FUNC(bdf); - - /* - * Trap out illegal values - */ - if (offset > 255) - BUG(); - if (busnr > 255) - BUG(); - if (devfn > 255) - BUG(); - - if (busnr == 0) { - /* - * Linux calls the thing U-Boot calls "DEV" "SLOT" - * instead, but it's the same 5 bits - */ - int slot = PCI_DEV(bdf); - - /* - * local bus segment so need a type 0 config cycle - * - * build the PCI configuration "address" with one-hot in - * A31-A11 - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 are 0 (0) - */ - address = PCI_FUNC(bdf) << 8; - mapaddress = V3_LB_MAP_TYPE_CONFIG; - - if (slot > 12) - /* - * high order bits are handled by the MAP register - */ - mapaddress |= 1 << (slot - 5); - else - /* - * low order bits handled directly in the address - */ - address |= 1 << (slot + 11); - } else { - /* - * not the local bus segment so need a type 1 config cycle - * - * address: - * 23:16 = bus number - * 15:11 = slot number (7:3 of devfn) - * 10:8 = func number (2:0 of devfn) - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 from host bus (1) - */ - mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; - address = (busnr << 16) | (devfn << 8); - } - - /* - * Set up base0 to see all 512Mbytes of memory space (not - * prefetchable), this frees up base1 for re-use by - * configuration memory - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); - - /* - * Set up base1/map1 to point into configuration space. - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | - V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, mapaddress); - - return PHYS_PCI_CONFIG_BASE + address + offset; -} - -static void v3_close_config_window(void) -{ - /* - * Reassign base1 for use by prefetchable PCI memory - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* - * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); -} - -static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, - int offset, unsigned char *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readb(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_read__word(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned short *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readw(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_read_dword(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned int *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readl(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_byte(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned char val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writeb((u8)val, addr); - __raw_readb(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_word(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned short val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writew((u8)val, addr); - __raw_readw(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_dword(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned int val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writel((u8)val, addr); - __raw_readl(addr); - v3_close_config_window(); - return 0; -} - -struct pci_controller integrator_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_integrator_config_table, -#endif -}; - -void pci_init_board(void) -{ - struct pci_controller *hose = &integrator_hose; - u16 val; - - /* setting this register will take the V3 out of reset */ - __raw_writel(SC_PCI_PCIEN, SC_PCI); - - /* Wait for 230 ms (from spec) before accessing any V3 registers */ - mdelay(230); - - /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ - v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); - - /* Wait for the mailbox to settle */ - do { - v3_writeb(V3_MAIL_DATA, 0xAA); - v3_writeb(V3_MAIL_DATA + 4, 0x55); - } while (v3_readb(V3_MAIL_DATA) != 0xAA || - v3_readb(V3_MAIL_DATA + 4) != 0x55); - - /* Make sure that V3 register access is not locked, if it is, unlock it */ - if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) - v3_writew(V3_SYSTEM, 0xA05F); - - /* - * Ensure that the slave accesses from PCI are disabled while we - * setup memory windows - */ - val = v3_readw(V3_PCI_CMD); - val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); - v3_writew(V3_PCI_CMD, val); - - /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ - val = v3_readw(V3_SYSTEM); - val &= ~V3_SYSTEM_M_RST_OUT; - v3_writew(V3_SYSTEM, val); - - /* Make all accesses from PCI space retry until we're ready for them */ - val = v3_readw(V3_PCI_CFG); - val |= V3_PCI_CFG_M_RETRY_EN; - v3_writew(V3_PCI_CFG, val); - - /* - * Set up any V3 PCI Configuration Registers that we absolutely have to. - * LB_CFG controls Local Bus protocol. - * Enable LocalBus byte strobes for READ accesses too. - * set bit 7 BE_IMODE and bit 6 BE_OMODE - */ - val = v3_readw(V3_LB_CFG); - val |= 0x0C0; - v3_writew(V3_LB_CFG, val); - - /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ - val = v3_readw(V3_PCI_CMD); - val |= V3_COMMAND_M_MASTER_EN; - v3_writew(V3_PCI_CMD, val); - - /* - * PCI_MAP0 controls where the PCI to CPU memory window is on - * Local Bus - */ - v3_writel(V3_PCI_MAP0, - (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE)); - - /* PCI_BASE0 is the PCI address of the start of the window */ - v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); - - /* PCI_MAP1 is LOCAL address of the start of the window */ - v3_writel(V3_PCI_MAP1, - (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE)); - - /* PCI_BASE1 is the PCI address of the start of the window */ - v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); - - /* - * Set up memory the windows from local bus memory into PCI - * configuration, I/O and Memory regions. - * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. - */ - v3_writew(V3_LB_BASE2, - v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP2, 0); - - /* PCI Configuration, use LB_BASE1/LB_MAP1. */ - - /* - * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 - * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP0, - v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); - - /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* Dump PCI to local address space mappings */ - debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); - debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); - debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); - debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); - debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); - debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); - debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); - - /* - * Allow accesses to PCI Configuration space and set up A1, A0 for - * type 1 config cycles - */ - val = v3_readw(V3_PCI_CFG); - val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); - val |= V3_PCI_CFG_M_AD_LOW0; - v3_writew(V3_PCI_CFG, val); - - /* now we can allow incoming PCI MEMORY accesses */ - val = v3_readw(V3_PCI_CMD); - val |= V3_COMMAND_M_MEM_EN; - v3_writew(V3_PCI_CMD, val); - - /* - * Set RST_OUT to take the PCI bus is out of reset, PCI devices can - * now initialise. - */ - val = v3_readw(V3_SYSTEM); - val |= V3_SYSTEM_M_RST_OUT; - v3_writew(V3_SYSTEM, val); - - /* Lock the V3 system register so that no one else can play with it */ - val = v3_readw(V3_SYSTEM); - val |= V3_SYSTEM_M_LOCK; - v3_writew(V3_SYSTEM, val); - - /* - * Configure and register the PCI hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space, window 0 256 MB non-prefetchable */ - pci_set_region(hose->regions + 0, - PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, - SZ_256M, - PCI_REGION_MEM); - - /* System memory space, window 1 256 MB prefetchable */ - pci_set_region(hose->regions + 1, - PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, - SZ_256M, - PCI_REGION_MEM | - PCI_REGION_PREFETCH); - - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, - PCI_REGION_IO); - - /* PCI Memory - config space */ - pci_set_region(hose->regions + 3, - 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, - PCI_REGION_MEM); - /* PCI V3 regs */ - pci_set_region(hose->regions + 4, - 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, - PCI_REGION_MEM); - - hose->region_count = 5; - - pci_set_ops(hose, - pci_integrator_read_byte, - pci_integrator_read__word, - pci_integrator_read_dword, - pci_integrator_write_byte, - pci_integrator_write_word, - pci_integrator_write_dword); - - pci_register_hose(hose); - - pciauto_config_init(hose); - pciauto_config_device(hose, 0); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h deleted file mode 100644 index 8d09e6966db..00000000000 --- a/board/armltd/integrator/pci_v3.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * arch/arm/include/asm/hardware/pci_v3.h - * - * Internal header file PCI V3 chip - * - * Copyright (C) ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. - */ -#ifndef ASM_ARM_HARDWARE_PCI_V3_H -#define ASM_ARM_HARDWARE_PCI_V3_H - -/* ------------------------------------------------------------------------------- - * V3 Local Bus to PCI Bridge definitions - * ------------------------------------------------------------------------------- - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -/* PCI MAP register bits (PCI -> Local bus) */ -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -#endif diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index 86356e38751..13fd25e4071 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -188,7 +188,7 @@ static void __maybe_unused leds_set_booting(void) /* * Function to set the LEDs in the state "Bootloader error" */ -static void leds_set_failure(int state) +static void __maybe_unused leds_set_failure(int state) { #if defined(CONFIG_B_SAMPLE) /* Turn all blue and green LEDs off */ @@ -479,7 +479,7 @@ int board_eth_init(struct bd_info *bis) } #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS +#if CONFIG_IS_ENABLED(BOOTSTAGE) static void bosch_check_reset_pin(void) { if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) { @@ -525,9 +525,9 @@ void show_boot_progress(int val) break; } } +#endif void arch_preboot_os(void) { leds_set_finish(); } -#endif diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 34be601fdde..738b6bc25ce 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -271,7 +271,7 @@ int misc_init_r(void) } #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS +#if CONFIG_IS_ENABLED(BOOTSTAGE) void show_boot_progress(int progress) { if (progress > 0) diff --git a/board/ea/ea-lpc3250devkitv2/Kconfig b/board/ea/ea-lpc3250devkitv2/Kconfig new file mode 100644 index 00000000000..368ce027e62 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EA_LPC3250DEVKITV2 + +config SYS_BOARD + default "ea-lpc3250devkitv2" + +config SYS_VENDOR + default "ea" + +config SYS_SOC + default "lpc32xx" + +config SYS_CONFIG_NAME + default "ea-lpc3250devkitv2" + +endif diff --git a/board/ea/ea-lpc3250devkitv2/MAINTAINERS b/board/ea/ea-lpc3250devkitv2/MAINTAINERS new file mode 100644 index 00000000000..b4b9362f5b2 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/MAINTAINERS @@ -0,0 +1,9 @@ +EMBEDDED ARTISTS LPC3250 DEVKIT v2 +M: Trevor Woerner <twoerner@gmail.com> +S: Maintained +F: board/ea/ea-lpc3250devkitv2 +F: include/configs/ea-lpc3250devkitv2.h +F: configs/ea-lpc3250devkitv2_defconfig +F: arch/arm/dts/lpc32xx.dtsi +F: arch/arm/dts/lpc3250-ea3250.dts +F: arch/arm/dts/lpc3250-ea3250-u-boot.dtsi diff --git a/board/ea/ea-lpc3250devkitv2/Makefile b/board/ea/ea-lpc3250devkitv2/Makefile new file mode 100644 index 00000000000..a4a40b6d4fb --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com> + +obj-y += ea-lpc3250devkitv2.o diff --git a/board/ea/ea-lpc3250devkitv2/README.rst b/board/ea/ea-lpc3250devkitv2/README.rst new file mode 100644 index 00000000000..1b780003317 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/README.rst @@ -0,0 +1,186 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ToC: +- Introduction +- Booting +- Debugging +- i2c + + +Introduction +============ +The Embedded Artists LPC3250 Developer's Kit v2 features the LPC3250 SoC +which is based on the ARM926EJ-S CPU. The kit features a base board and +a removable OEM board which features the SoC. Details, schematics, and +documentation are available from the Embedded Artists product website: + + https://www.embeddedartists.com/products/lpc3250-developers-kit-v2/ + +The base board includes:: +- 200 pos, 0.6mm pitch SODIMM connector for OEM Board +- LCD expansion connector with control signals for touch screen interface +- Expansion connector with all OEM Board signals +- Ethernet connector (RJ45) +- CAN interface & connector (provision for second CAN interface, but not mounted) +- MMC/SD interface & connector +- USB1: OTG or Host interface & connector +- USB2: Device or Host interface & connector +- Provision for NXP JN5148 RF module (former Jennic) interface (RF module not included) +- Full modem RS232 (cannot be fully used on 32-bit databus OEM boards) +- RS422/485 interface & connector +- Provision for IrDA transceiver interface (transceiver not mounted) +- I2S audio codec (mic in, line in, line out, headphone out) +- SWD/JTAG connector +- Trace connector and pads for ETM connector +- Serial Expansion Connector, 14-pos connector with UART/I2C/SPI/GPIO pins +- Power supply, either via USB or external 5V DC +- Optional coin cell battery for RTC and LED on ALARM output (coin cell not included) +- OEM Board current measuring +- Parallel NOR flash on external memory bus +- 16-bit register and LEDs on external memory bus +- 5-key joystick +- LM75 temperature sensor (I2C connected) +- 5 push-button keys (four via I2C and one on ISP-ENABLE) +- 9 LEDs (8 via I2C and one on ISP-ENABLE) +- Trimming potentiometer to analog input +- USB-to-serial bridge on UART #0 (FT232R) and ISP functionality +- Reset push-button and LED +- Speaker output on analog output from OEM Board, or from I2S audio codec +- 160x150 mm in size + +The OEM board:: +- ARMv5 ARM926EJ-S @ 266 MHz with hard-float VFPv2 +- 256 KByte IRAM, 64 MByte SDRAM +- 128 MByte NAND flash +- 4 MByte NOR Flash +- Graphics Output: Parallel RGB +- Hardware 2D/3D Graphic: No +- Hardware Video: SW only +- Graphics input: No +- Audio: I2S +- Ethernet: 10/100 Mbps +- USB: 1x FS USB 2.0 OTG +- Wi-Fi: No +- FlexIO: No +- Serial: 2x I2C, 2x SPI, 7x UART +- ADC/PWM: 3 ch (10-bit) / 2 ch +- SD: MCI +- PCIe: No +- Serial ATA: No +- Size: 68 x 48 mm +- Connector: 200 pos SODIMM + + +Booting +======= +The processor will start its code execution from an internal ROM, +containing the boot code. This boot loader can load code from one of four +external sources to internal RAM (IRAM) at address 0x0:: +- UART5 +- SSP0 (in SPI mode) +- EMC Static CS0 memory +- NAND FLASH + +The ROM boot loader loads code as a single contiguous block at a maximum +size of 56 kByte. Programs larger than this size must be loaded in more +steps, for example, by a secondary boot loader. + +Kickstart Loader +---------------- +By default the Embedded Artists LPC3250 OEM Board is programmed with the +kickstart loader in block 0 of the NAND flash. The responsibility of this +loader is to load an application stored in block 1 and onwards of the NAND +flash. The kickstart loader will load the application into internal RAM +(IRAM) at address 0x0. + +Stage 1 Loader (s1l) +-------------------- +By default the Embedded Artists LPC3250 OEM Board is programmed with the +stage 1 loader (s1l) in block 1 of the NAND flash. This application will be +loaded by the kickstart loader when the LPC3250 OEM Board powers up. The +S1L loader will initialize the board, such as clocks and external memory +and then start a console where you can give input commands to the loader. +S1L offers the following booting options:: +- MMC/SD card +- UART5 +- NAND Flash + +U-Boot with kickstart+s1l +------------------------- +Out of the box, the easiest way to get U-Boot running on the EA LPC3250 +DevKit v2 board is to build the ea-lpc3250devkitv2_defconfig, copy the +resulting u-boot.bin to a vfat-formatted MMC/SD card, insert the MMC/SD card +into the MMC/SD card slot on the board, reset the board (SW1), and:: + + Embedded Artist 3250 Board (S1L 2.0) + Build date: Oct 31 2016 13:00:37 + + EA3250>load blk u-boot.bin raw 0x83000000 + File loaded successfully + + EA3250>exec 0x83000000 + + +Debugging +========= +JTAG debugging of the Embedded Artists LPC3250 Developer's Kit v2 board is +easy thanks to the included/populated 20-pin JTAG port on the main board (J8). +openocd 0.11 has been used with this board along with the ARM-USB-OCD-H JTAG +dongle from Olimex successfully as follows: + + # openocd \ + -f interface/ftdi/olimex-arm-usb-ocd-h.cfg \ + -f board/phytec_lpc3250.cfg + + +i2c +=== +Some of the LEDs on the board are connected via an I/O Expander (PCA9532) that +is attached to the i2c1 bus. Here is a sample session of toggling some of +these LEDs via i2c in U-Boot: + +show the existing i2c busses: + EA-LPC3250v2=> i2c bus + Bus 0: i2c@300 + Bus 1: i2c@400a0000 + Bus 2: i2c@400a8000 + +set i2c1 as the current bus: + EA-LPC3250v2=> i2c dev 1 + Setting bus to 1 + +see what potential devices are found with rudimentary probing on i2c1: + EA-LPC3250v2=> i2c probe + Valid chip addresses: 1A 1D 48 50 57 60 66 6E + +According to the schematics the i2c slave address of the PCA9532 is 0x60. + +dump all of the 10 registers from the I/O Expander; NOTE that the 0x10 in the +command specifies the self-incrementing mode of the PCA9532; also NOTE that +the values repeat themseves to fill out a full 16 bytes: + EA-LPC3250v2=> i2c md 0x60 0x10 10 + 0010: 00 ff 00 80 00 80 00 00 00 00 4f ff 00 80 00 80 ..........O..... + +turn on LEDs 23, 25, 27, and 29 (green): + EA-LPC3250v2=> i2c mw 0x60 9 0x55 + +turn on LEDs 22, 24, 26, and 28 (red): + EA-LPC3250v2=> i2c mw 0x60 8 0x55 + +dim the green LEDs (23, 25, 27, 29): + EA-LPC3250v2=> i2c mw 0x60 3 0x20 + EA-LPC3250v2=> i2c mw 0x60 9 0xaa + +turn off all LEDs (23-29): + EA-LPC3250v2=> i2c mw 0x60 8 0 + EA-LPC3250v2=> i2c mw 0x60 9 0 + +read value of switches (input): + EA-LPC3250v2=> i2c md 0x60 0 1 + 0000: 4f O +[none are pressed] + +press and hold SW2 while running the following: + EA-LPC3250v2=> i2c md 0x60 0 1 + 0000: 4e N +[SW2 is pressed] diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c new file mode 100644 index 00000000000..72cf46c749f --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for Embedded Artists LPC3250 DevKit v2 + * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com> + */ + +#include <init.h> +#include <common.h> +#include <asm/io.h> +#include <asm/global_data.h> + +#include <asm/arch/clk.h> +#include <asm/arch/wdt.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +int +board_early_init_f(void) +{ + lpc32xx_uart_init(CONFIG_CONS_INDEX); + if (IS_ENABLED(CONFIG_SYS_I2C_LPC32XX)) { + lpc32xx_i2c_init(1); + lpc32xx_i2c_init(2); + } + return 0; +} + +int +board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000; + return 0; +} + +int +dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M); + return 0; +} diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 624e92ef9c2..66b3d9a4651 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -176,7 +176,7 @@ int board_early_init_f(void) } #ifdef CONFIG_FSL_ESDHC -#if !(CONFIG_IS_ENABLED(DM_MMC)) +#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB)) int board_mmc_init(struct bd_info *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; @@ -217,6 +217,15 @@ int misc_init_r(void) return rc; } +int board_late_init(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_USB + clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000); +#endif + return 0; +} + #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h index c05f536806f..bd40cc319a8 100644 --- a/board/freescale/t102xrdb/cpld.h +++ b/board/freescale/t102xrdb/cpld.h @@ -21,7 +21,7 @@ struct cpld_data { u8 boot_override; /* 0x18 - Boot override register */ u8 boot_config1; /* 0x19 - Boot config override register*/ u8 boot_config2; /* 0x1A - Boot config override register*/ -} cpld_data_t; +}; /* Pointer to the CPLD register set */ diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index a816aef10a4..769883f9461 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -30,8 +30,7 @@ struct cpld_data { u8 boot_override; /* 0x18 - Boot override register */ u8 boot_config1; /* 0x19 - Boot config override register*/ u8 boot_config2; /* 0x1A - Boot config override register*/ -} cpld_data_t; - +}; /* Pointer to the CPLD register set */ diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index bd6c203742e..a623b1811fa 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -21,7 +21,7 @@ struct cpld_data { u8 boot_or; /* 0x16 - Boot config override register */ u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ -} cpld_data_t; +}; u8 cpld_read(unsigned int reg); void cpld_write(unsigned int reg, u8 value); diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index cc8118b4ad4..7c3a695cb25 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -155,6 +155,7 @@ int board_late_init(void) return ret; } +#if CONFIG_IS_ENABLED(BOOTSTAGE) #define GPIO_DR 0x0 #define GPIO_GDIR 0x4 #define GPIO_ALT1 0x1 @@ -203,3 +204,4 @@ void show_boot_progress(int status) gpio_direction_output(LED_RED, 1); } } +#endif diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig new file mode 100644 index 00000000000..193c890046e --- /dev/null +++ b/board/openpiton/riscv64/Kconfig @@ -0,0 +1,40 @@ +if TARGET_OPENPITON_RISCV64 + +config SYS_BOARD + default "riscv64" + +config SYS_VENDOR + default "openpiton" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "openpiton-riscv64" + +config SYS_TEXT_BASE + default 0x81000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x81000000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x82000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU_RISCV + imply RISCV_TIMER + imply SPL_SIFIVE_CLINT + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_SMP + imply SPL_MMC + imply SMP + imply SPL_RISCV_MMODE + +endif diff --git a/board/openpiton/riscv64/MAINTAINERS b/board/openpiton/riscv64/MAINTAINERS new file mode 100644 index 00000000000..f80f5b04957 --- /dev/null +++ b/board/openpiton/riscv64/MAINTAINERS @@ -0,0 +1,9 @@ +Openpiton BOARD +M: Tianrui Wei <tianrui-wei@outlook.com> +S: Maintained +F: board/openpiton/riscv64/ +F: include/configs/openpiton-riscv64.h +F: configs/openpiton_riscv64_defconfig +F: configs/openpiton_riscv64_spl_defconfig +F: drivers/mmc/piton_mmc.c +F: arch/riscv/dts/openpiton-riscv64.dts diff --git a/board/openpiton/riscv64/Makefile b/board/openpiton/riscv64/Makefile new file mode 100644 index 00000000000..3bffa75a9a4 --- /dev/null +++ b/board/openpiton/riscv64/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Tianrui Wei +# Tianrui Wei <tianrui-wei@outlook.com> +obj-y += openpiton-riscv64.o diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c new file mode 100644 index 00000000000..f2282d15488 --- /dev/null +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * Copyright (c) 2021 Tianrui Wei + * + * + * Authors: + * Pragnesh Patel <pragnesh.patel@sifive.com> + * Tianrui Wei <tianrui-wei@outlook.com> + */ +#include <common.h> +#include <init.h> +#include <configs/openpiton-riscv64.h> +#include <dm.h> +#include <spl.h> + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { + BOOT_DEVICE_MMC1, + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +int board_init(void) +{ + return 0; +} diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig index 88b5883cae7..fb2c1fbb58a 100644 --- a/board/sifive/unmatched/Kconfig +++ b/board/sifive/unmatched/Kconfig @@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_MSCC imply SYSRESET imply SYSRESET_GPIO + imply CMD_I2C endif diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile index 6308c80d643..e00b330e8ce 100644 --- a/board/sifive/unmatched/Makefile +++ b/board/sifive/unmatched/Makefile @@ -3,6 +3,7 @@ # Copyright (c) 2020-2021 SiFive, Inc obj-y += unmatched.o +obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o ifdef CONFIG_SPL_BUILD obj-y += spl.o diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c new file mode 100644 index 00000000000..a2151f15e04 --- /dev/null +++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 SiFive, Inc. + * + * Based on board/freescale/common/sys_eeprom.c: + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * Timur Tabi (timur@freescale.com) + */ + +#include <common.h> +#include <command.h> +#include <env.h> +#include <i2c.h> +#include <init.h> +#include <linux/ctype.h> +#include <linux/delay.h> +#include <u-boot/crc.h> + +#ifndef CONFIG_SYS_EEPROM_BUS_NUM +#error Requires CONFIG_SYS_EEPROM_BUS_NUM to be defined +#endif + +#define FORMAT_VERSION 0x1 + +/* Options for the manuf_test_status field */ +#define SIFIVE_MANUF_TEST_STATUS_UNKNOWN 0 +#define SIFIVE_MANUF_TEST_STATUS_PASS 1 +#define SIFIVE_MANUF_TEST_STATUS_FAIL 2 + +/* + * BYTES_PER_EEPROM_PAGE: the AT24C02 datasheet says that data can + * only be written in page mode, which means 8 bytes at a time + */ +#define BYTES_PER_EEPROM_PAGE 8 + +/* + * EEPROM_WRITE_DELAY_MS: the AT24C02 datasheet says it takes up to + * 5ms to complete a given write + */ +#define EEPROM_WRITE_DELAY_MS 5000 + +/* + * MAGIC_NUMBER_BYTES: number of bytes used by the magic number + */ +#define MAGIC_NUMBER_BYTES 4 + +/* + * SERIAL_NUMBER_BYTES: number of bytes used by the board serial + * number + */ +#define SERIAL_NUMBER_BYTES 16 + +/* + * MAC_ADDR_BYTES: number of bytes used by the Ethernet MAC address + */ +#define MAC_ADDR_BYTES 6 + +/* + * MAC_ADDR_STRLEN: length of mac address string + */ +#define MAC_ADDR_STRLEN 17 + +/* + * SiFive OUI. Registration Date is 2018-02-15 + */ +#define SIFIVE_OUI_PREFIX "70:B3:D5:92:F" + +/** + * static eeprom: EEPROM layout for the SiFive platform I2C format + */ +static struct __attribute__ ((__packed__)) sifive_eeprom { + u8 magic[MAGIC_NUMBER_BYTES]; + u8 format_ver; + u16 product_id; + u8 pcb_revision; + u8 bom_revision; + u8 bom_variant; + u8 serial[SERIAL_NUMBER_BYTES]; + u8 manuf_test_status; + u8 mac_addr[MAC_ADDR_BYTES]; + u32 crc; +} e; + +struct sifive_product { + u16 id; + const char *name; +}; + +/* Set to 1 if we've read EEPROM into memory */ +static int has_been_read; + +/* Magic number at the first four bytes of EEPROM */ +static const unsigned char magic[MAGIC_NUMBER_BYTES] = { 0xf1, 0x5e, 0x50, 0x45 }; + +/* Does the magic number match that of a SiFive EEPROM? */ +static inline int is_match_magic(void) +{ + return (memcmp(&e.magic, &magic, MAGIC_NUMBER_BYTES) == 0); +} + +/* Calculate the current CRC */ +static inline u32 calculate_crc32(void) +{ + return crc32(0, (void *)&e, sizeof(struct sifive_eeprom) - sizeof(e.crc)); +} + +/* This function should be called after each update to the EEPROM structure */ +static inline void update_crc(void) +{ + e.crc = calculate_crc32(); +} + +static struct sifive_product sifive_products[] = { + { 0, "Unknown"}, + { 2, "HiFive Unmatched" }, +}; + +/** + * dump_raw_eeprom - display the raw contents of the EEPROM + */ +static void dump_raw_eeprom(void) +{ + unsigned int i; + + printf("EEPROM dump: (0x%lx bytes)\n", sizeof(e)); + for (i = 0; i < sizeof(e); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&e)[i]); + if (((i % 16) == 15) || (i == sizeof(e) - 1)) + printf("\n"); + } +} + +/** + * show_eeprom - display the contents of the EEPROM + */ +static void show_eeprom(void) +{ + unsigned int i; + u32 crc; + const char *product_name = "Unknown"; + char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 }; + + if (!is_match_magic()) { + printf("Not a SiFive HiFive EEPROM data format - magic bytes don't match\n"); + dump_raw_eeprom(); + return; + }; + + snprintf(board_serial, sizeof(board_serial), "%s", e.serial); + + for (i = 0; i < ARRAY_SIZE(sifive_products); i++) { + if (sifive_products[i].id == e.product_id) { + product_name = sifive_products[i].name; + break; + } + }; + + printf("SiFive PCB EEPROM format v%u\n", e.format_ver); + printf("Product ID: %04hx (%s)\n", e.product_id, product_name); + printf("PCB revision: %x\n", e.pcb_revision); + printf("BOM revision: %c\n", e.bom_revision); + printf("BOM variant: %x\n", e.bom_variant); + printf("Serial number: %s\n", board_serial); + printf("Ethernet MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n", + e.mac_addr[0], e.mac_addr[1], e.mac_addr[2], + e.mac_addr[3], e.mac_addr[4], e.mac_addr[5]); + + crc = calculate_crc32(); + if (crc == e.crc) { + printf("CRC: %08x\n", e.crc); + } else { + printf("CRC: %08x (should be %08x)\n", e.crc, crc); + dump_raw_eeprom(); + } +} + +/** + * read_eeprom() - read the EEPROM into memory, if it hasn't been read already + */ +static int read_eeprom(void) +{ + int ret; + struct udevice *dev; + + if (has_been_read) + return 0; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + 1, + &dev); + if (!ret) + dm_i2c_read(dev, 0, (void *)&e, + sizeof(struct sifive_eeprom)); + + show_eeprom(); + + has_been_read = (ret == 0) ? 1 : 0; + + return ret; +} + +/** + * prog_eeprom() - write the EEPROM from memory + */ +static int prog_eeprom(void) +{ + int ret = 0; + unsigned int i; + void *p; + + if (!is_match_magic()) { + printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n"); + return 0; + } + + for (i = 0, p = &e; i < sizeof(e); + i += BYTES_PER_EEPROM_PAGE, p += BYTES_PER_EEPROM_PAGE) { + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); + if (!ret) + ret = dm_i2c_write(dev, i, p, + min((int)(sizeof(e) - i), + BYTES_PER_EEPROM_PAGE)); + + if (ret) + break; + + udelay(EEPROM_WRITE_DELAY_MS); + } + + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct sifive_eeprom e2; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + + if (ret) { + printf("Programming failed.\n"); + has_been_read = 0; + return -1; + } + + printf("Programming passed.\n"); + return 0; +} + +/** + * set_mac_address() - stores a MAC address into the local EEPROM copy + * + * This function takes a pointer to MAC address string + * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number), + * stores it in the MAC address field of the EEPROM local copy, and + * updates the local copy of the CRC. + */ +static void set_mac_address(char *string) +{ + unsigned int i; + + if (strncasecmp(SIFIVE_OUI_PREFIX, string, 13)) { + printf("The MAC address doesn't match SiFive OUI %s\n", + SIFIVE_OUI_PREFIX); + return; + } + + for (i = 0; *string && (i < MAC_ADDR_BYTES); i++) { + e.mac_addr[i] = simple_strtoul(string, &string, 16); + if (*string == ':') + string++; + } + + update_crc(); +} + +/** + * set_manuf_test_status() - stores a test status byte into the in-memory copy + * + * Takes a pointer to a manufacturing test status string ("unknown", + * "pass", "fail") and stores the corresponding numeric ID to the + * manuf_test_status field of the EEPROM local copy, and updates the + * CRC of the local copy. + */ +static void set_manuf_test_status(char *string) +{ + if (!strcasecmp(string, "unknown")) { + e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_UNKNOWN; + } else if (!strcasecmp(string, "pass")) { + e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_PASS; + } else if (!strcasecmp(string, "fail")) { + e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_FAIL; + } else { + printf("Usage: mac manuf_test_status (unknown|pass|fail)\n"); + return; + } + + update_crc(); +} + +/** + * set_pcb_revision() - stores a SiFive PCB revision into the local EEPROM copy + * + * Takes a pointer to a string representing the numeric PCB revision in + * decimal ("0" - "255"), stores it in the pcb_revision field of the + * EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_pcb_revision(char *string) +{ + unsigned long p; + + p = simple_strtoul(string, &string, 10); + if (p > U8_MAX) { + printf("%s must not be greater than %d\n", "PCB revision", + U8_MAX); + return; + } + + e.pcb_revision = p; + + update_crc(); +} + +/** + * set_bom_revision() - stores a SiFive BOM revision into the local EEPROM copy + * + * Takes a pointer to a uppercase ASCII character representing the BOM + * revision ("A" - "Z"), stores it in the bom_revision field of the + * EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_bom_revision(char *string) +{ + if (string[0] < 'A' || string[0] > 'Z') { + printf("BOM revision must be an uppercase letter between A and Z\n"); + return; + } + + e.bom_revision = string[0]; + + update_crc(); +} + +/** + * set_bom_variant() - stores a SiFive BOM variant into the local EEPROM copy + * + * Takes a pointer to a string representing the numeric BOM variant in + * decimal ("0" - "255"), stores it in the bom_variant field of the + * EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_bom_variant(char *string) +{ + unsigned long p; + + p = simple_strtoul(string, &string, 10); + if (p > U8_MAX) { + printf("%s must not be greater than %d\n", "BOM variant", + U8_MAX); + return; + } + + e.bom_variant = p; + + update_crc(); +} + +/** + * set_product_id() - stores a SiFive product ID into the local EEPROM copy + * + * Takes a pointer to a string representing the numeric product ID in + * decimal ("0" - "65535"), stores it in the product ID field of the + * EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_product_id(char *string) +{ + unsigned long p; + + p = simple_strtoul(string, &string, 10); + if (p > U16_MAX) { + printf("%s must not be greater than %d\n", "Product ID", + U16_MAX); + return; + } + + e.product_id = p; + + update_crc(); +} + +/** + * set_serial_number() - set the PCB serial number in the in-memory copy + * + * Set the board serial number in the in-memory EEPROM copy from the supplied + * string argument, and update the CRC. + */ +static void set_serial_number(char *string) +{ + if (strlen(string) > SERIAL_NUMBER_BYTES) { + printf("Serial number must not be greater than 16 bytes\n"); + return; + } + + memset(e.serial, 0, sizeof(e.serial)); + strncpy((char *)e.serial, string, sizeof(e.serial)); + update_crc(); +} + +/** + * init_local_copy() - initialize the in-memory EEPROM copy + * + * Initialize the in-memory EEPROM copy with the magic number. Must + * be done when preparing to initialize a blank EEPROM, or overwrite + * one with a corrupted magic number. + */ +static void init_local_copy(void) +{ + memset(&e, 0, sizeof(e)); + memcpy(e.magic, magic, sizeof(e.magic)); + e.format_ver = FORMAT_VERSION; + update_crc(); +} + +int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + char *cmd; + + if (argc == 1) { + show_eeprom(); + return 0; + } + + if (argc > 3) + return cmd_usage(cmdtp); + + cmd = argv[1]; + + /* Commands with no argument */ + if (!strcmp(cmd, "read_eeprom")) { + read_eeprom(); + return 0; + } else if (!strcmp(cmd, "initialize")) { + init_local_copy(); + return 0; + } else if (!strcmp(cmd, "write_eeprom")) { + prog_eeprom(); + return 0; + } + + if (argc != 3) + return cmd_usage(cmdtp); + + if (!is_match_magic()) { + printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n"); + return 0; + } + + if (!strcmp(cmd, "serial_number")) { + set_serial_number(argv[2]); + return 0; + } else if (!strcmp(cmd, "manuf_test_status")) { + set_manuf_test_status(argv[2]); + return 0; + } else if (!strcmp(cmd, "mac_address")) { + set_mac_address(argv[2]); + return 0; + } else if (!strcmp(cmd, "pcb_revision")) { + set_pcb_revision(argv[2]); + return 0; + } else if (!strcmp(cmd, "bom_variant")) { + set_bom_variant(argv[2]); + return 0; + } else if (!strcmp(cmd, "bom_revision")) { + set_bom_revision(argv[2]); + return 0; + } else if (!strcmp(cmd, "product_id")) { + set_product_id(argv[2]); + return 0; + } + + return cmd_usage(cmdtp); +} + +/** + * mac_read_from_eeprom() - read the MAC address from EEPROM + * + * This function reads the MAC address from EEPROM and sets the + * appropriate environment variables for each one read. + * + * The environment variables are only set if they haven't been set already. + * This ensures that any user-saved variables are never overwritten. + * + * This function must be called after relocation. + */ +int mac_read_from_eeprom(void) +{ + u32 crc; + char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 }; + + puts("EEPROM: "); + + if (read_eeprom()) { + printf("Read failed.\n"); + return 0; + } + + if (!is_match_magic()) { + printf("Invalid ID (%02x %02x %02x %02x)\n", + e.magic[0], e.magic[1], e.magic[2], e.magic[3]); + dump_raw_eeprom(); + return 0; + } + + crc = calculate_crc32(); + if (crc != e.crc) { + printf("CRC mismatch (%08x != %08x)\n", crc, e.crc); + dump_raw_eeprom(); + return 0; + } + + eth_env_set_enetaddr("ethaddr", e.mac_addr); + + if (!env_get("serial#")) { + snprintf(board_serial, sizeof(board_serial), "%s", e.serial); + env_set("serial#", board_serial); + } + + return 0; +} + +/** + * get_pcb_revision_from_eeprom - get the PCB revision + * + * Read the EEPROM to determine the board revision. + * + * This function is called before relocation, so we need to read a private + * copy of the EEPROM into a local variable on the stack. + */ +u8 get_pcb_revision_from_eeprom(void) +{ + struct __attribute__ ((__packed__)) board_eeprom { + u8 magic[MAGIC_NUMBER_BYTES]; + u8 format_ver; + u16 product_id; + u8 pcb_revision; + } be; + + int ret; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + 1, + &dev); + + if (!ret) + dm_i2c_read(dev, 0, (void *)&be, + sizeof(struct board_eeprom)); + + return be.pcb_revision; +} diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c index 5e1333b09a8..74134b03ee6 100644 --- a/board/sifive/unmatched/spl.c +++ b/board/sifive/unmatched/spl.c @@ -10,11 +10,14 @@ #include <spl.h> #include <misc.h> #include <log.h> +#include <fdtdec.h> +#include <dm/root.h> #include <linux/delay.h> #include <linux/io.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> #include <asm/arch/spl.h> +#include <asm/arch/eeprom.h> #define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) @@ -26,6 +29,16 @@ int spl_board_init_f(void) { int ret; +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) + int rescan; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } +#endif + ret = spl_soc_init(); if (ret) { debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret); @@ -79,7 +92,18 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { - /* boot using first FIT config */ - return 0; + /* + * Apply different DDR params on different board revision. + * Use PCB revision which is byte 0x7 in I2C platform EEPROM + * to distinguish that. + */ + if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 && + !strcmp(name, "hifive-unmatched-a00")) + return 0; + else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 && + !strcmp(name, "hifive-unmatched-a00-rev1")) + return 0; + + return -1; } #endif diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 00000000000..706b8dc0f1c --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 00000000000..aa672b6e052 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,14 @@ +DEVELOPER BOX +M: Masami Hiramatsu <masami.hiramatsu@linaro.org> +M: Jassi Brar <jaswinder.singh@linaro.org> +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developerbox_defconfig +F: drivers/i2c/synquacer_i2c.c +F: drivers/mmc/f_sdh30.c +F: drivers/net/sni_netsec.c +F: drivers/pci/pcie_ecam_synquacer.c +F: drivers/spi/spi-synquacer.c +F: include/configs/synquacer.h +F: doc/board/socionext/developerbox.rst diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile new file mode 100644 index 00000000000..4a46de995a0 --- /dev/null +++ b/board/socionext/developerbox/Makefile @@ -0,0 +1,9 @@ +# +# Author: Masami Hiramatsu <masami.hiramatsu@linaro.org> +# +# Copyright (C) 2021 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := developerbox.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c new file mode 100644 index 00000000000..34335baec36 --- /dev/null +++ b/board/socionext/developerbox/developerbox.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * u-boot/board/socionext/developerbox/developerbox.c + * + * Copyright (C) 2016-2017 Socionext Inc. + * Copyright (C) 2021 Linaro Ltd. + */ +#include <asm/types.h> +#include <asm/armv8/mmu.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <common.h> +#include <env_internal.h> +#include <fdt_support.h> +#include <log.h> + +static struct mm_region sc2a11_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 1st DDR block */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 2nd DDR place holder */ + 0, + }, { + /* 3rd DDR place holder */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sc2a11_mem_map; + +#define DDR_REGION_INDEX(i) (1 + (i)) +#define MAX_DDR_REGIONS 3 + +struct draminfo_entry { + u64 base; + u64 size; +}; + +struct draminfo { + u32 nr_regions; + u32 reserved; + struct draminfo_entry entry[3]; +}; + +struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#define LOAD_OFFSET 0x100 + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET; + + gd->env_addr = (ulong)&default_environment[0]; + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */ + fdt_del_node_and_alias(blob, "spi_nor"); + fdt_del_node_and_alias(blob, "i2c0"); + + return 0; +} + +/* + * DRAM configuration + */ + +int dram_init(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + struct mm_region *mr; + int i, ri; + + if (synquacer_draminfo->nr_regions < 1) { + log_err("Failed to get correct DRAM information\n"); + return -1; + } + + /* + * U-Boot RAM size must be under the first DRAM region so that it doesn't + * access secure memory which is at the end of the first DRAM region. + */ + gd->ram_size = ent[0].size; + + /* Update memory region maps */ + for (i = 0; i < synquacer_draminfo->nr_regions; i++) { + if (i >= MAX_DDR_REGIONS) + break; + + ri = DDR_REGION_INDEX(i); + mem_map[ri].phys = ent[i].base; + mem_map[ri].size = ent[i].size; + if (i == 0) + continue; + + mr = &mem_map[DDR_REGION_INDEX(0)]; + mem_map[ri].virt = mr->virt + mr->size; + mem_map[ri].attrs = mr->attrs; + } + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +int print_cpuinfo(void) +{ + printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); + return 0; +} diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c index 3b0de82db28..57ca9f659c1 100644 --- a/board/st/stv0991/stv0991.c +++ b/board/st/stv0991/stv0991.c @@ -37,7 +37,7 @@ U_BOOT_DRVINFO(stv09911_serials) = { }; #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS +#if CONFIG_IS_ENABLED(BOOTSTAGE) void show_boot_progress(int progress) { printf("%i\n", progress); diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 3c744b943f4..9d4ffb0f979 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -38,7 +38,7 @@ void reset_periph(void) int board_early_init_f(void) { - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); lpc32xx_i2c_init(1); lpc32xx_i2c_init(2); lpc32xx_ssp_init(); diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c index 47af78ae0b1..12e8ae9c39c 100644 --- a/board/timll/devkit3250/devkit3250_spl.c +++ b/board/timll/devkit3250/devkit3250_spl.c @@ -49,7 +49,7 @@ void spl_board_init(void) /* First of all silence buzzer controlled by GPO_20 */ writel((1 << 20), &gpio->p3_outp_clr); - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); preloader_console_init(); ddr_init(&dram_64mb); diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index bdcecff7308..5d12f84cfea 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -37,7 +37,7 @@ void reset_periph(void) int board_early_init_f(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* enable I2C, SSP, MAC, NAND */ lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ lpc32xx_ssp_init(); diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c index a31553a2d25..d9401145f27 100644 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = { void spl_board_init(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* initialize console */ preloader_console_init(); /* init DDR and NAND to chainload U-Boot */ |