diff options
Diffstat (limited to 'board')
288 files changed, 17476 insertions, 8188 deletions
diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index c0a163251b4..de206bdf1bc 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -7,6 +7,7 @@ * */ #include <cpu_func.h> +#include <env.h> #include <hang.h> #include <init.h> #include <spl.h> diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index b7588fa4eec..baee5afa46d 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -29,6 +29,7 @@ #include <linux/bitops.h> #include <linux/bitrev.h> #include <linux/delay.h> +#include <linux/if_ether.h> #include <u-boot/crc.h> #include "../drivers/ddr/marvell/a38x/ddr3_init.h" diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index df3fb6d2164..e44b713f96d 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -20,6 +20,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <linux/delay.h> +#include <linux/if_ether.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 01ba53cf68d..1bea5a60513 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -93,11 +93,6 @@ int board_early_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - int timer_init(void) { return 0; diff --git a/board/Synology/common/legacy.h b/board/Synology/common/legacy.h index 0a814324d09..f7ba225bd2b 100644 --- a/board/Synology/common/legacy.h +++ b/board/Synology/common/legacy.h @@ -8,6 +8,8 @@ #ifndef __SYNO_LEGACY_H #define __SYNO_LEGACY_H +#include <linux/if_ether.h> + /* Marvell uboot parameters */ #define ATAG_MV_UBOOT 0x41000403 #define VER_NUM 0x03040400 /* 3.4.4 */ diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index 1a4cea87e1a..02d6a4a1ea8 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> */ +#include <env.h> #include <init.h> #include <miiphy.h> #include <asm/global_data.h> diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index b9f47006d61..8c9e9830876 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -7,6 +7,7 @@ #include <dwc3-uboot.h> #include <efi.h> #include <efi_loader.h> +#include <env.h> #include <errno.h> #include <miiphy.h> #include <netdev.h> diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env index 0c9f9c4178a..90861e622ed 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env @@ -6,7 +6,7 @@ earlycon=lpuart32,0x5a060000 fdt_addr=0x83000000 boot_fdt=try fdt_file=imx8qm-dmsse20-a1.dtb -mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV) +mmcdev= __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index 50b35db5f6c..accd300df04 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -4,6 +4,7 @@ * Copyright 2019-2023 Kococonnector GmbH */ +#include <env.h> #include <errno.h> #include <linux/libfdt.h> #include <asm/io.h> diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 72967e69a84..7d91d288d2e 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -365,9 +365,11 @@ int dram_init(void) return 0; } +#if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { } +#endif #if defined(CONFIG_ENV_IS_NOWHERE) enum env_location env_get_location(enum env_operation op, int prio) diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index b770a1f8c53..9e87fb9f9d7 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -5,6 +5,7 @@ */ #include <dm.h> +#include <env.h> #include <init.h> #include <net.h> #include <asm/io.h> diff --git a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c index f9412071737..fc0057746e0 100644 --- a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c +++ b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c @@ -13,8 +13,3 @@ int mmc_get_env_dev(void) return 1; return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c index 1d9d4a929c2..9bdd2ab1780 100644 --- a/board/andestech/ae350/ae350.c +++ b/board/andestech/ae350/ae350.c @@ -6,6 +6,7 @@ #include <config.h> #include <cpu_func.h> +#include <env.h> #include <flash.h> #include <image.h> #include <init.h> diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 3ad77f51949..16d0e679c3e 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -77,11 +77,6 @@ static struct mm_region corstone1000_mem_map[] = { struct mm_region *mem_map = corstone1000_mem_map; -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE; diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 75bc6b0631f..12bb6defab2 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -70,11 +70,6 @@ int misc_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 6c374e25e32..3833af59b09 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -165,3 +165,11 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr) writel(addr, CONFIG_SYSFLAGS_ADDR); } #endif + +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig deleted file mode 100644 index a7c04cef83d..00000000000 --- a/board/astro/mcf5373l/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASTRO_MCF5373L - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "mcf5373l" - -config SYS_VENDOR - default "astro" - -config SYS_CONFIG_NAME - default "astro_mcf5373l" - -endif diff --git a/board/astro/mcf5373l/MAINTAINERS b/board/astro/mcf5373l/MAINTAINERS deleted file mode 100644 index 6c23da71968..00000000000 --- a/board/astro/mcf5373l/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MCF5373L BOARD -M: Wolfgang Wegner <w.wegner@astro-kom.de> -S: Maintained -F: board/astro/mcf5373l/ -F: include/configs/astro_mcf5373l.h -F: configs/astro_mcf5373l_defconfig diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile deleted file mode 100644 index d3ea0d06a8d..00000000000 --- a/board/astro/mcf5373l/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = mcf5373l.o fpga.o diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h deleted file mode 100644 index b55a6f785ce..00000000000 --- a/board/astro/mcf5373l/astro.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __ASTRO_H__ -#define __ASTRO_H__ - -/* in mcf5373l.c */ -int rs_serial_init(int port, int baud); -void astro_put_char(char ch); -int astro_is_char(void); -int astro_get_char(void); - -/* in fpga.c */ -int astro5373l_altera_load(void); -int astro5373l_xilinx_load(void); - -/* data structures used for communication (update.c) */ -typedef struct card_id { - char card_type; - char hardware_version; - char software_version; - char software_subversion; /* " ","a".."z" */ - char fpga_version_altera; - char fpga_version_xilinx; -} card_id_t; - -typedef struct { - unsigned char mode; - unsigned char deviation; - unsigned short freq; -} __attribute__ ((packed)) output_params_t; - -typedef struct { - unsigned short satfreq; - unsigned char satdatallg; - unsigned short symbolrate; - unsigned char viterbirate; - unsigned char symbolrate_l; - output_params_t output_params; - unsigned char reserve; - unsigned char card_error; - unsigned short dummy_ts_id; - unsigned char dummy_pat_ver; - unsigned char dummy_sdt_ver; -} __attribute__ ((packed)) parameters_t; - -#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c deleted file mode 100644 index 6e505c630d1..00000000000 --- a/board/astro/mcf5373l/fpga.c +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, - * w.wegner@astro-kom.de - * - * based on the files by - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * and - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - */ - -/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ - -#include <console.h> -#include <watchdog.h> -#include <altera.h> -#include <ACEX1K.h> -#include <spartan3.h> -#include <command.h> -#include <asm/immap_5329.h> -#include <asm/io.h> -#include "fpga.h" - -int altera_pre_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - - /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ - writeb(0xFE, &gpiop->pclrr_timer); - writeb(0xDF, &gpiop->pclrr_qspi); - return FPGA_SUCCESS; -} - -/* Set the state of CONFIG Pin */ -int altera_config_fn(int assert_config, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_config) - writeb(0x04, &gpiop->ppd_uart); - else - writeb(0xFB, &gpiop->pclrr_uart); - return FPGA_SUCCESS; -} - -/* Returns the state of STATUS Pin */ -int altera_status_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x08) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* Returns the state of CONF_DONE Pin */ -int altera_done_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x20) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* - * writes the complete buffer to the FPGA - * writing the complete buffer in one function is much faster, - * then calling it for every bit - */ -int altera_write_fn(const void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - while (bytecount < len) { - val = data[bytecount++]; - i = 8; - do { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x01) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val >>= 1; - i--; - } while (i > 0); - - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* called, when programming is aborted */ -int altera_abort_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - writeb(0x20, &gpiop->ppd_qspi); - writeb(0x08, &gpiop->ppd_uart); - return FPGA_SUCCESS; -} - -/* called, when programming was succesful */ -int altera_post_fn(int cookie) -{ - return altera_abort_fn(cookie); -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -Altera_CYC2_Passive_Serial_fns altera_fns = { - altera_pre_fn, - altera_config_fn, - altera_status_fn, - altera_done_fn, - altera_write_fn, - altera_abort_fn, - altera_post_fn -}; - -#define FPGA_COUNT 1 -Altera_desc altera_fpga[FPGA_COUNT] = { - {Altera_CYC2, - passive_serial, - 85903, - (void *)&altera_fns, - NULL, - 0} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_altera_load(void) -{ - int i; - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - altera_fns.pre = altera_pre_fn; - altera_fns.config = altera_config_fn; - altera_fns.status = altera_status_fn; - altera_fns.done = altera_done_fn; - altera_fns.write = altera_write_fn; - altera_fns.abort = altera_abort_fn; - altera_fns.post = altera_post_fn; - altera_fpga[i].iface_fns = (void *)&altera_fns; - fpga_add(fpga_altera, &altera_fpga[i]); - } - return 1; -} - -/* Set the FPGA's PROG_B line to the specified level */ -int xilinx_pgm_config_fn(int assert, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert) - writeb(0xFB, &gpiop->pclrr_uart); - else - writeb(0x04, &gpiop->ppd_uart); - return assert; -} - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int xilinx_init_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x08) == 0; -} - -/* Test the state of the active-high FPGA DONE pin */ -int xilinx_done_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; -} - -/* Abort an FPGA operation */ -int xilinx_abort_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - /* ensure all SPI peripherals and FPGAs are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x01, &gpiop->ppd_timer); - writeb(0x38, &gpiop->ppd_qspi); - return FPGA_FAIL; -} - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int xilinx_pre_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - writeb(0x01, &gpiop->ppd_timer); - - /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ - writeb(0xF7, &gpiop->pclrr_uart); - writeb(0xDF, &gpiop->pclrr_qspi); - return 0; -} - -/* - * FPGA post configuration function. Should perform a test if FPGA is running. - */ -int xilinx_post_config_fn(int cookie) -{ - int rc = 0; - - /* - * no test yet - */ - return rc; -} - -int xilinx_clk_config_fn(int assert_clk, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_clk) - writeb(0x04, &gpiop->ppd_qspi); - else - writeb(0xFB, &gpiop->pclrr_qspi); - return assert_clk; -} - -int xilinx_wr_config_fn(int assert_write, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_write) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - return assert_write; -} - -int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - for (bytecount = 0; bytecount < len; bytecount++) { - val = *(data++); - for (i = 8; i > 0; i--) { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x80) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val <<= 1; - } - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -xilinx_spartan3_slave_serial_fns xilinx_fns = { - xilinx_pre_config_fn, - xilinx_pgm_config_fn, - xilinx_clk_config_fn, - xilinx_init_config_fn, - xilinx_done_config_fn, - xilinx_wr_config_fn, - 0, - xilinx_fastwr_config_fn -}; - -xilinx_desc xilinx_fpga[FPGA_COUNT] = { - {xilinx_spartan3, - slave_serial, - XILINX_XC3S4000_SIZE, - (void *)&xilinx_fns, - 0, - &spartan3_op} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_xilinx_load(void) -{ - int i; - - fpga_init(); - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - xilinx_fns.pre = xilinx_pre_config_fn; - xilinx_fns.pgm = xilinx_pgm_config_fn; - xilinx_fns.clk = xilinx_clk_config_fn; - xilinx_fns.init = xilinx_init_config_fn; - xilinx_fns.done = xilinx_done_config_fn; - xilinx_fns.wr = xilinx_wr_config_fn; - xilinx_fns.bwr = xilinx_fastwr_config_fn; - xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; - fpga_add(fpga_xilinx, &xilinx_fpga[i]); - } - return 1; -} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c deleted file mode 100644 index 43fcbc65513..00000000000 --- a/board/astro/mcf5373l/mcf5373l.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l - */ - -#include <config.h> -#include <init.h> -#include <serial.h> -#include <time.h> -#include <watchdog.h> -#include <command.h> -#include <asm/global_data.h> -#include <asm/m5329.h> -#include <asm/immap_5329.h> -#include <asm/io.h> -#include <linux/delay.h> - -/* needed for astro bus: */ -#include <asm/uart.h> -#include "astro.h" - -DECLARE_GLOBAL_DATA_PTR; -extern void uart_port_conf(void); - -int checkboard(void) -{ - puts("Board: "); - puts("ASTRO MCF5373L (Urmel) Board\n"); - return 0; -} - -int dram_init(void) -{ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); - - /* - * GPIO configuration for bus should be set correctly from reset, - * so we do not care! First, set up address space: at this point, - * we should be running from internal SRAM; - * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, - * and do not care where it is - */ - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, - &sdp->cs0); - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, - &sdp->cs1); - /* - * I am not sure from the data sheet, but it seems burst length - * has to be 8 for the 16 bit data bus we use; - * so these values are for BL = 8 - */ - __raw_writel(0x33211530, &sdp->cfg1); - __raw_writel(0x56570000, &sdp->cfg2); - /* send PrechargeALL, REF and IREF remain cleared! */ - __raw_writel(0xE1462C02, &sdp->ctrl); - udelay(1); - /* refresh SDRAM twice */ - __raw_writel(0xE1462C04, &sdp->ctrl); - udelay(1); - __raw_writel(0xE1462C04, &sdp->ctrl); - /* init MR */ - __raw_writel(0x008D0000, &sdp->mode); - /* initialize EMR */ - __raw_writel(0x80010000, &sdp->mode); - /* wait until DLL is locked */ - udelay(1); - /* - * enable automatic refresh, lock mode register, - * clear iref and ipall - */ - __raw_writel(0x71462C00, &sdp->ctrl); - /* Dummy write to start SDRAM */ - writel(0, CFG_SYS_SDRAM_BASE); -#endif - - /* - * for get_ram_size() to work, both CS areas have to be - * configured, i.e. CS1 has to be explicitely disabled, else - * probing for memory will cause the SDRAM bus to hang! - * (Do not rely on the SDCS register(s) being set to 0x00000000 - * during reset as stated in the data sheet.) - */ - gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, - 0x80000000 - CFG_SYS_SDRAM_BASE); - - return 0; -} - -#define UART_BASE MMAP_UART0 -int rs_serial_init(int port, int baud) -{ - uart_t *uart; - u32 counter; - - switch (port) { - case 0: - uart = (uart_t *)(MMAP_UART0); - break; - case 1: - uart = (uart_t *)(MMAP_UART1); - break; - case 2: - uart = (uart_t *)(MMAP_UART2); - break; - default: - uart = (uart_t *)(MMAP_UART0); - } - - uart_port_conf(); - - /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ - writeb(UART_UCR_RESET_RX, &uart->ucr); - writeb(UART_UCR_RESET_TX, &uart->ucr); - writeb(UART_UCR_RESET_ERROR, &uart->ucr); - writeb(UART_UCR_RESET_MR, &uart->ucr); - __asm__ ("nop"); - - writeb(0, &uart->uimr); - - /* write to CSR: RX/TX baud rate from timers */ - writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); - - writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); - writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); - - /* Setting up BaudRate */ - counter = (u32) (gd->bus_clk / (baud)); - counter >>= 5; - - /* write to CTUR: divide counter upper byte */ - writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); - /* write to CTLR: divide counter lower byte */ - writeb((u8) (counter & 0x00ff), &uart->ubg2); - - writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); - - return 0; -} - -void astro_put_char(char ch) -{ - uart_t *uart; - unsigned long timer; - - uart = (uart_t *)(MMAP_UART0); - /* - * Wait for last character to go. Timeout of 6ms should - * be enough for our lowest baud rate of 2400. - */ - timer = get_timer(0); - while (get_timer(timer) < 6) { - if (readb(&uart->usr) & UART_USR_TXRDY) - break; - } - writeb(ch, &uart->utb); - - return; -} - -int astro_is_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - return readb(&uart->usr) & UART_USR_RXRDY; -} - -int astro_get_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; - return readb(&uart->urb); -} - -int misc_init_r(void) -{ - int retval = 0; - - puts("Configure Xilinx FPGA..."); - retval = astro5373l_xilinx_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - puts("Configure Altera FPGA..."); - retval = astro5373l_altera_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - return retval; -} diff --git a/board/atmel/sam9x75_curiosity/Kconfig b/board/atmel/sam9x75_curiosity/Kconfig new file mode 100644 index 00000000000..8ea93a21aa3 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAM9X75_CURIOSITY + +config SYS_BOARD + default "sam9x75_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sam9x75_curiosity" + +endif diff --git a/board/atmel/sam9x75_curiosity/MAINTAINERS b/board/atmel/sam9x75_curiosity/MAINTAINERS new file mode 100644 index 00000000000..f0dfdbe8d5c --- /dev/null +++ b/board/atmel/sam9x75_curiosity/MAINTAINERS @@ -0,0 +1,7 @@ +SAM9X75 CURIOSITY BOARD +M: Manikandan Muralidharan <manikandan.m@microchip.com> +S: Maintained +F: board/atmel/sam9x75_curiosity/ +F: include/configs/sam9x75_curiosity.h +F: arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi +F: configs/sam9x75_curiosity_mmc_defconfig diff --git a/board/atmel/sam9x75_curiosity/Makefile b/board/atmel/sam9x75_curiosity/Makefile new file mode 100644 index 00000000000..1f36d613229 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# Author: Manikandan Muralidharan <manikandan.m@microchip.com> + +obj-y += sam9x75_curiosity.o diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c new file mode 100644 index 00000000000..4e7c5667e21 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan <manikandan.m@microchip.com> + */ + +#include <debug_uart.h> +#include <init.h> +#include <asm/io.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_sfr.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_dbgu0_hw_init(void) +{ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 1); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 1); /* DTXD */ + + at91_periph_clk_enable(ATMEL_ID_DBGU); +} + +void board_debug_uart_init(void) +{ + board_dbgu0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 04de1257eca..897fab58eba 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; rgb_leds_init(); @@ -82,11 +82,14 @@ int misc_init_r(void) } #endif +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + int dram_init(void) { - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CFG_SYS_SDRAM_SIZE); - return 0; + return fdtdec_setup_mem_size_base(); } /* SPL */ diff --git a/board/atmel/sama7d65_curiosity/Kconfig b/board/atmel/sama7d65_curiosity/Kconfig new file mode 100644 index 00000000000..21ff432f2c1 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA7D65_CURIOSITY + +config SYS_BOARD + default "sama7d65_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama7d65_curiosity" + +endif diff --git a/board/atmel/sama7d65_curiosity/MAINTAINERS b/board/atmel/sama7d65_curiosity/MAINTAINERS new file mode 100644 index 00000000000..054af3c6541 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/MAINTAINERS @@ -0,0 +1,6 @@ +SAMA7D65 CURIOSITY BOARD +M: Ryan Wanner <ryan.wanner@microchip.com> +S: Maintained +F: board/atmel/sama7d65_curiosity.c +F: include/configs/sama7d65_curiosity.h +F: configs/sama7d65_curiosity_mmc1_defconfig diff --git a/board/atmel/sama7d65_curiosity/Makefile b/board/atmel/sama7d65_curiosity/Makefile new file mode 100644 index 00000000000..56d011d1d81 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries +# +# Author: Ryan Wanner <ryan.wanner@microchip.com> + +obj-y += sama7d65_curiosity.o diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c new file mode 100644 index 00000000000..713b1b9d959 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + * + */ + +#include <debug_uart.h> +#include <init.h> +#include <fdtdec.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama7d65.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 21, 0); /* LED BLUE */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 15, 1); /* LED GREEN */ +} + +int board_late_init(void) +{ + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_uart0_hw_init(void) +{ + /* FLEXCOM6 IO0 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 18, 0); + /* FLEXCOM6 IO1 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 19, 0); + + at91_periph_clk_enable(ATMEL_ID_FLEXCOM6); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + board_leds_init(); + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c index 204235a3f8e..6459a99cb9d 100644 --- a/board/beacon/imx8mm/imx8mm_beacon.c +++ b/board/beacon/imx8mm/imx8mm_beacon.c @@ -6,8 +6,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/beacon/imx8mn/imx8mn_beacon.c b/board/beacon/imx8mn/imx8mn_beacon.c index 204235a3f8e..6459a99cb9d 100644 --- a/board/beacon/imx8mn/imx8mn_beacon.c +++ b/board/beacon/imx8mn/imx8mn_beacon.c @@ -6,8 +6,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index 99eb8972cf3..500fcc58ed8 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -45,11 +45,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 78635810585..9bc9ca30e95 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beagle/beagley-ai/beagley-ai.c b/board/beagle/beagley-ai/beagley-ai.c index 9786f628f6d..26fa54e27bb 100644 --- a/board/beagle/beagley-ai/beagley-ai.c +++ b/board/beagle/beagley-ai/beagley-ai.c @@ -21,11 +21,6 @@ void set_dfu_alt_info(char *interface, char *devstr) } #endif -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 33ba7a7751c..ebbae27c0f9 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -32,7 +32,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <jffs2/load_kernel.h> -#include <mtd.h> #include <nand.h> #include <video.h> #include <video_console.h> diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h index a5e58186c9c..8ff68f5a64b 100644 --- a/board/bosch/shc/board.h +++ b/board/bosch/shc/board.h @@ -14,6 +14,8 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include <linux/if_ether.h> + /* Definition to control the GPIOs (for LEDs and Reset) */ #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) @@ -146,7 +148,6 @@ static inline int board_is_series(void) #define RESET_MASK (0x1 << 29) #define HDR_MAGIC 0x43485342 -#define HDR_ETH_ALEN 6 #define HDR_NAME_LEN 8 #define HDR_REV_LEN 8 #define HDR_SER_LEN 16 @@ -176,7 +177,7 @@ struct shc_eeprom { u32 magic; u16 version; u16 lenght; - uint8_t mac_addr[HDR_ETH_ALEN]; + uint8_t mac_addr[ETH_ALEN]; }; void enable_uart0_pin_mux(void); diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c index a6ced92565f..1ab6224011c 100644 --- a/board/broadcom/bcmbca/board.c +++ b/board/broadcom/bcmbca/board.c @@ -5,11 +5,6 @@ #include <fdtdec.h> -int board_init(void) -{ - return 0; -} - int dram_init(void) { if (fdtdec_setup_mem_size_base() != 0) diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 45cc62936ce..47a01227a35 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -31,11 +31,6 @@ int board_late_init(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index e655f610c84..e7313d8c431 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -32,11 +32,6 @@ union reg_value_union { const phys_addr_t *address; }; -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/bsh/imx6ulz_smm_m2/Kconfig b/board/bsh/imx6ulz_smm_m2/Kconfig index e38df7ce5cb..20971aa4fe1 100644 --- a/board/bsh/imx6ulz_smm_m2/Kconfig +++ b/board/bsh/imx6ulz_smm_m2/Kconfig @@ -9,4 +9,25 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6ulz_smm_m2" +choice + prompt "Memory Type (M2/M2B) board" + default BSH_M2_MEMORY + help + Memory type setup. + Please choose correct memory model here. + +config BSH_M2_MEMORY + bool "Enable for bsh m2 variant" + help + If this option is enabled, U-Boot will be configured to support + imx6ulz bsh m2 revision memories. + +config BSH_M2B_MEMORY + bool "Enable for bsh m2b variant" + help + If this option is enabled, U-Boot will be configured to support + imx6ulz bsh m2b revision memories. + +endchoice + endif diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS index 77a033c6cbb..a75cddd72f8 100644 --- a/board/bsh/imx6ulz_smm_m2/MAINTAINERS +++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/bsh/imx6ulz_smm_m2/ F: include/configs/imx6ulz_smm_m2.h F: configs/imx6ulz_smm_m2_defconfig +F: configs/imx6ulz_smm_m2b_defconfig diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile index 4f4d67f659d..233bbff4c16 100644 --- a/board/bsh/imx6ulz_smm_m2/Makefile +++ b/board/bsh/imx6ulz_smm_m2/Makefile @@ -2,4 +2,6 @@ # (C) Copyright 2021 Amarula Solutions B.V. obj-y := imx6ulz_smm_m2.o -obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_BSH_M2_MEMORY) += ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o +obj-$(CONFIG_BSH_M2B_MEMORY) += ddr3l_timing_256m_m2b.o ddr3l_timing_128m_m2b.o diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c index 66c3483adbf..f11654a8ceb 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c @@ -166,4 +166,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { struct dram_timing_info bsh_dram_timing_128mb = { .ddrc_cfg = ddr_ddrc_cfg_128mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), + .dram_size = SZ_128M, }; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c new file mode 100644 index 00000000000..f989e24f567 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured + * using Group Control Register IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:WINBOND + * Device Part Number:W631GU6RB-11 + * Clock Freq.: 400MHz + * Density per CS in Gb: 1 + * Chip Selects used:1 + * Total DRAM density (Gb)1 + * Number of Banks:8 + * Row address: 13 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00060002}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x414c0150}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040363e}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x40402a28}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the recommended default value, although out of reset + * value is 0. + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xf3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xf3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + {0x021b0018, 0x00201740}, /* MMDC0_MDMISC */ + {0x021b002C, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x002F1023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000043}, /* CS0_END */ + {0x021b0000, 0x82180000}, /* MMDC0_MDCTL */ + + /* Mode register writes for CS0 */ + {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */ + {0x021B001C, 0x04008040}, /* + * MMDC0_MDSCR, ZQ calibration + * command sent to device on CS0 + */ + + /* final DDR setup, before operation start: */ + {0x021b0020, 0x00000800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002556D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, + * MMDC will enter automatically to self-refresh + * while the number of idle cycle reached. + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially the + * configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_128mb = { + .ddrc_cfg = ddr_ddrc_cfg_128mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), + .dram_size = SZ_128M, +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c index 0fe5b90a673..5dfc9f5c70d 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c @@ -165,4 +165,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { struct dram_timing_info bsh_dram_timing_256mb = { .ddrc_cfg = ddr_ddrc_cfg_256mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), + .dram_size = SZ_256M, }; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c new file mode 100644 index 00000000000..c44f632b928 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ + + /* Address: */ + {0x020e0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be + * configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ + {0x020e0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ + {0x020e0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:WINBOND + * Device Part Number:W632GU6RB-11 + * Clock Freq.: 400MHz + * Density per CS in Gb: 2 + * Chip Selects used:1 + * Total DRAM density (Gb)2 + * Number of Banks:8 + * Row address: 14 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00070005}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x414c0150}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040383e}, /* MMDC_MPRDDLCTL */ + + /* Write calibration */ + {0x021b0850, 0x40402e2a}, /* MMDC_MPWRDLCTL */ + + {0x021B081C, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021B0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + {0x021B082C, 0xf3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021B0830, 0xf3333333}, /* MMDC_MPWRDQBY1DL */ + + {0x021B08C0, 0x00944009}, /* MMDC_MPDCCR */ + + /* Complete calibration by forced measurement: */ + {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* MMDC init: */ + {0x021b0004, 0x00020024}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x3F4352D3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + {0x021b0018, 0x00201740}, /* MMDC0_MDMISC */ + {0x021b002C, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x00431023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000047}, /* CS0_END */ + {0x021b0000, 0x83180000}, /* MMDC0_MDCTL */ + + /* Mode register writes for CS0 */ + {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */ + {0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration */ + + /* final DDR setup, before operation start: */ + {0x021b0020, 0x00000800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + {0x021b0004, 0x00025564}, /* MMDC0_MDPDC now SDCTL power down enabled */ + {0x021b0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */ + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially + * the configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_256mb = { + .ddrc_cfg = ddr_ddrc_cfg_256mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), + .dram_size = SZ_256M, +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c index f5989382f5a..4c2ffcd429d 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c @@ -165,4 +165,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { struct dram_timing_info bsh_dram_timing_512mb = { .ddrc_cfg = ddr_ddrc_cfg_512mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), + .dram_size = SZ_512M, }; diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index c330e4d6d39..7aea73f0f5d 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -52,28 +52,31 @@ static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info) } } +static const struct dram_timing_info *board_dram_timing[] = { +#if defined(CONFIG_M2_MEMORY) + &bsh_dram_timing_512mb, +#endif + &bsh_dram_timing_256mb, + &bsh_dram_timing_128mb, +}; + static void spl_dram_init(void) { /* Configure memory to maximum supported size for detection */ - ddr_cfg_write(&bsh_dram_timing_512mb); + ddr_cfg_write(board_dram_timing[0]); /* Detect memory physically present */ - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); - - /* Reconfigure memory for actual detected size */ - switch (gd->ram_size) { - case SZ_512M: - /* Already configured, nothing to do */ - break; - case SZ_256M: - udelay(1); - ddr_cfg_write(&bsh_dram_timing_256mb); - break; - case SZ_128M: - default: - udelay(1); - ddr_cfg_write(&bsh_dram_timing_128mb); - break; + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, board_dram_timing[0]->dram_size); + + if (board_dram_timing[0]->dram_size == gd->ram_size) + return; + + for (size_t index = 1; index < ARRAY_SIZE(board_dram_timing); index++) { + if (board_dram_timing[index]->dram_size == gd->ram_size) { + udelay(1); + ddr_cfg_write(board_dram_timing[index]); + break; + } } } diff --git a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h index 8da59881c83..06d6f2d76d8 100644 --- a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h +++ b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h @@ -18,6 +18,7 @@ struct dram_cfg_param { struct dram_timing_info { const struct dram_cfg_param *ddrc_cfg; unsigned int ddrc_cfg_num; + size_t dram_size; }; extern struct dram_timing_info bsh_dram_timing_128mb; diff --git a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c index c9989687399..c4a85c4aa44 100644 --- a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c +++ b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c @@ -6,11 +6,6 @@ #include <asm/arch/sys_proto.h> #include <env.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (is_usb_boot()) { diff --git a/board/canaan/k230_canmv/board.c b/board/canaan/k230_canmv/board.c index a705ee8f67b..7d012df214f 100644 --- a/board/canaan/k230_canmv/board.c +++ b/board/canaan/k230_canmv/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2025, Junhui Liu <junhui.liu@pigmoral.tech> */ -int board_init(void) -{ - return 0; -} diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index b1a805c1360..4c477ad551c 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -72,11 +72,6 @@ static struct mm_region thunderx_mem_map[] = { struct mm_region *mem_map = thunderx_mem_map; -int board_init(void) -{ - return 0; -} - int timer_init(void) { return 0; diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index 054e4e10867..03be02a2884 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -4,6 +4,7 @@ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com> */ #include <config.h> +#include <env.h> #include <errno.h> #include <linux/libfdt.h> #include <fsl_esdhc.h> diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile index f8170d9c653..7f1c8994d27 100644 --- a/board/congatec/common/Makefile +++ b/board/congatec/common/Makefile @@ -16,8 +16,8 @@ endif endif ifdef MINIMAL -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a else obj-y += mmc.o diff --git a/board/cssi/cmpc885/u-boot.lds b/board/cssi/cmpc885/u-boot.lds index 53f616fcfe1..167606357e0 100644 --- a/board/cssi/cmpc885/u-boot.lds +++ b/board/cssi/cmpc885/u-boot.lds @@ -18,8 +18,8 @@ SECTIONS { arch/powerpc/cpu/mpc8xx/start.o (.text) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - drivers/net/built-in.o (.text*) + arch/powerpc/lib/built-in.a (.text*) + drivers/net/built-in.a (.text*) . = DEFINED(env_offset) ? env_offset : .; env/embedded.o (.text.environment) diff --git a/board/cssi/mcr3000/u-boot.lds b/board/cssi/mcr3000/u-boot.lds index 24b535e724a..66afdebc0f7 100644 --- a/board/cssi/mcr3000/u-boot.lds +++ b/board/cssi/mcr3000/u-boot.lds @@ -18,8 +18,8 @@ SECTIONS { arch/powerpc/cpu/mpc8xx/start.o (.text) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - drivers/net/built-in.o (.text*) + arch/powerpc/lib/built-in.a (.text*) + drivers/net/built-in.a (.text*) . = DEFINED(env_offset) ? env_offset : .; env/embedded.o (.text.environment) diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index 9e35dc5d6cb..7d344792937 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -12,6 +12,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <dm/uclass.h> +#include <env.h> #include <hang.h> #include <i2c_eeprom.h> #include <image.h> diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 339702e8392..e271d060efa 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -16,11 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index 138acd36ad2..d6f0a917023 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -46,11 +46,6 @@ enum env_location env_get_location(enum env_operation op, int prio) return prio ? ENVL_UNKNOWN : ENVL_MMC; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 71010803f55..8c052c45007 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -5,6 +5,7 @@ */ #include <dm.h> +#include <env.h> #include <i2c_eeprom.h> #include <net.h> #include <u-boot/crc.h> diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 4275436b128..3a890c5920c 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -153,11 +153,6 @@ void dh_add_item_number_and_serial_to_env(struct eeprom_id_page *eip) } } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { u8 eeprom_buffer[DH_EEPROM_ID_PAGE_MAX_SIZE] = { 0 }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d30171f1fbe..f7347bbb826 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -27,7 +27,6 @@ #include <led.h> #include <memalign.h> #include <misc.h> -#include <mtd.h> #include <mtd_node.h> #include <netdev.h> #include <phy.h> diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c index 219efdddcb5..04b3bc8caf5 100644 --- a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c +++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c @@ -4,7 +4,3 @@ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c index 393fcaeb742..8a59f5ade13 100644 --- a/board/emulation/common/qemu_dfu.c +++ b/board/emulation/common/qemu_dfu.c @@ -7,6 +7,7 @@ #include <env.h> #include <memalign.h> #include <mtd.h> +#include <linux/sizes.h> #define DFU_ALT_BUF_LEN SZ_1K diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 31f5a775137..38f0ec5f2fb 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -102,11 +102,6 @@ static struct mm_region qemu_arm64_mem_map[] = { struct mm_region *mem_map = qemu_arm64_mem_map; #endif -int board_init(void) -{ - return 0; -} - int board_late_init(void) { /* diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 40d295dbf06..58de4a05296 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -170,9 +170,9 @@ int misc_init_r(void) * Detect the presence of the platform bus node, and * create a virtual memory mapping for it. */ - for (ret = uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); + for (uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); dev; - ret = uclass_find_next_device(&dev)) { + uclass_find_next_device(&dev)) { if (device_is_compatible(dev, "qemu,platform")) { struct simple_bus_plat *plat = dev_get_uclass_plat(dev); diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 70190ebe8fc..97c8211c100 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -28,11 +28,6 @@ int is_flash_available(void) } #endif -int board_init(void) -{ - return 0; -} - int board_late_init(void) { /* start usb so that usb keyboard can be used as input device */ diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.c b/board/emulation/qemu-sbsa/qemu-sbsa.c index cf1d5acf5cb..30b3a41a9e9 100644 --- a/board/emulation/qemu-sbsa/qemu-sbsa.c +++ b/board/emulation/qemu-sbsa/qemu-sbsa.c @@ -93,11 +93,6 @@ int board_late_init(void) return 0; } -int board_init(void) -{ - return 0; -} - /** * dtb_dt_qemu - Return the address of the QEMU provided FDT. * diff --git a/board/emulation/qemu-xtensa/qemu-xtensa.c b/board/emulation/qemu-xtensa/qemu-xtensa.c index 0ca83341c25..2e2a5a26d94 100644 --- a/board/emulation/qemu-xtensa/qemu-xtensa.c +++ b/board/emulation/qemu-xtensa/qemu-xtensa.c @@ -13,11 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - unsigned long get_board_sys_clk(void) { return gd->cpu_clk ? gd->cpu_clk : 40000000; diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index 56557d56429..82278a48ae8 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -34,12 +34,6 @@ int checkboard(void) return 0; } -/* board dependent setup after realloc */ -int board_init(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index b04e19e9428..ed102ae7bf7 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -14,8 +14,8 @@ endif endif ifdef MINIMAL -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a else # include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX I2C_COMMON= diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 194a0907e72..3d44357caf7 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -134,7 +134,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) /* Override weak funtion defined in SPL framework to enable validation * of main u-boot image before jumping to u-boot image. */ -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); uint32_t hdr_addr; diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 7815ba2dbce..04cad48f033 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <linux/compiler.h> #include <linux/time.h> +#include <linux/string.h> #include <i2c.h> #include "qixis.h" diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 784046ac4e0..0a0df6f34f8 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -136,8 +136,8 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 -#define QIXIS_DAT5_6_7 0X02 -#define QIXIS_DAT4 0X01 +#define QIXIS_DAT5_6_7 0x02 +#define QIXIS_DAT4 0x01 #define QIXIS_EVDD_BY_SDHC_VS 0x0c diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index d41db8d31d8..ecc20768cb5 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -3,6 +3,8 @@ * Copyright 2018 NXP */ +#include <config.h> +#include <efi_loader.h> #include <env.h> #include <init.h> #include <miiphy.h> @@ -15,6 +17,26 @@ DECLARE_GLOBAL_DATA_PTR; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \ + 0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MM-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.env b/board/freescale/imx8mm_evk/imx8mm_evk.env index 29690e75b15..299b8472c74 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.env +++ b/board/freescale/imx8mm_evk/imx8mm_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index c62d7a47e21..9d3f29f2253 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -5,9 +5,31 @@ #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <config.h> +#include <efi_loader.h> #include <env.h> #include <init.h> +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xcbabf44d, 0x12cc, 0x45dd, 0xb0, 0xc5, \ + 0x29, 0xc5, 0xb7, 0x42, 0x2d, 0x34) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MN-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.env b/board/freescale/imx8mn_evk/imx8mn_evk.env index 16a6543ffc6..487893f9287 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.env +++ b/board/freescale/imx8mn_evk/imx8mn_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 2ff067bc675..732c0fa561d 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -4,12 +4,29 @@ */ #include <asm/arch/sys_proto.h> +#include <config.h> +#include <efi_loader.h> #include <env.h> -int board_init(void) -{ - return 0; -} +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x928b33bc, 0xe58b, 0x4247, 0x9f, 0x1d, \ + 0x3b, 0xf1, 0xee, 0x1c, 0xda, 0xff) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MP-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_late_init(void) { diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.env b/board/freescale/imx8mp_evk/imx8mp_evk.env index f70e18fa9d9..18cdf3da056 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.env +++ b/board/freescale/imx8mp_evk/imx8mp_evk.env @@ -10,7 +10,7 @@ fdt_addr=0x43000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image ip_dyn=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 18e83d90a08..e90c56c33ff 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -7,6 +7,7 @@ #include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/iomux-v3.h> +#include <efi_loader.h> #include <env.h> #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) @@ -22,6 +23,26 @@ static iomux_v3_cfg_t const uart_pads[] = { IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x296119cf, 0xdd70, 0x43de, 0x8a, 0xc8, \ + 0xa7, 0x05, 0x1f, 0x31, 0x25, 0x77) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MQ-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.env b/board/freescale/imx8mq_evk/imx8mq_evk.env index dcfe1c2f2d4..cab8c6b70bf 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.env +++ b/board/freescale/imx8mq_evk/imx8mq_evk.env @@ -12,7 +12,7 @@ ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted; diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 0af61067263..4bf77a488cc 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include <env.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/imx8ulp-pins.h> diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c index 83bfca2f22d..cbd0a72bf4b 100644 --- a/board/freescale/imx91_evk/imx91_evk.c +++ b/board/freescale/imx91_evk/imx91_evk.c @@ -9,11 +9,6 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx91_evk/imx91_evk.env +++ b/board/freescale/imx91_evk/imx91_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS index 34ba278fcdf..eb6e669bd17 100644 --- a/board/freescale/imx93_evk/MAINTAINERS +++ b/board/freescale/imx93_evk/MAINTAINERS @@ -1,4 +1,4 @@ -i.MX93 MEK BOARD +i.MX93 EVK BOARD M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/imx93_evk/ diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index c9171df330e..d62f94dc418 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -4,6 +4,7 @@ */ #include <env.h> +#include <efi_loader.h> #include <init.h> #include <miiphy.h> #include <netdev.h> @@ -12,11 +13,8 @@ #include <asm/arch/sys_proto.h> #include <asm/arch-imx9/imx93_pins.h> #include <asm/arch/clock.h> -#include <power/pmic.h> #include <dm/device.h> #include <dm/uclass.h> -#include <usb.h> -#include <dwc3-uboot.h> DECLARE_GLOBAL_DATA_PTR; @@ -28,6 +26,26 @@ static iomux_v3_cfg_t const uart_pads[] = { MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); diff --git a/board/freescale/imx93_evk/imx93_evk.env b/board/freescale/imx93_evk/imx93_evk.env index 8c3aef6b557..d5ed216f54b 100644 --- a/board/freescale/imx93_evk/imx93_evk.env +++ b/board/freescale/imx93_evk/imx93_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_frdm/Kconfig b/board/freescale/imx93_frdm/Kconfig new file mode 100644 index 00000000000..5f5ac7f8f04 --- /dev/null +++ b/board/freescale/imx93_frdm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX93_FRDM + +config SYS_BOARD + default "imx93_frdm" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx93_frdm" + +endif diff --git a/board/freescale/imx93_frdm/MAINTAINERS b/board/freescale/imx93_frdm/MAINTAINERS new file mode 100644 index 00000000000..59595bb2118 --- /dev/null +++ b/board/freescale/imx93_frdm/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX93 FRDM BOARD +M: Fabio Estevam <festevam@gmail.com> +S: Maintained +F: board/freescale/imx93_frdm/ +F: include/configs/imx93_frdm.h +F: configs/imx93_frdm_defconfig diff --git a/board/freescale/imx93_frdm/Makefile b/board/freescale/imx93_frdm/Makefile new file mode 100644 index 00000000000..9612b1fa55b --- /dev/null +++ b/board/freescale/imx93_frdm/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_frdm.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +endif diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c new file mode 100644 index 00000000000..c74fd85712f --- /dev/null +++ b/board/freescale/imx93_frdm/imx93_frdm.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <env.h> +#include <efi_loader.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <dm/device.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-FRDM-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) || IS_ENABLED(CONFIG_ENV_IS_IN_NOWHERE)) + board_late_mmc_env_init(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "11X11_FRDM"); + env_set("board_rev", "iMX93"); + } + + return 0; +} diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env new file mode 100644 index 00000000000..528a953c8df --- /dev/null +++ b/board/freescale/imx93_frdm/imx93_frdm.env @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=1 +mmcpart=1 +mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console} root=${mmcroot} +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +boot_os=booti ${loadaddr} - ${fdt_addr_r} + +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + run mmcargs; + run loadimage; + run loadfdt; + run boot_os; + +scriptaddr=0x83500000 diff --git a/board/freescale/imx93_frdm/lpddr4_timing.h b/board/freescale/imx93_frdm/lpddr4_timing.h new file mode 100644 index 00000000000..192bc9e1519 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4_timing.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut <marex@denx.de> + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +extern struct dram_timing_info dram_timing_1GB; +extern struct dram_timing_info dram_timing_2GB; + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c new file mode 100644 index 00000000000..17549206ee4 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_7.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2E3233}, + {0x4e30010C, 0x0005C18B}, + {0x4e300124, 0x1C790000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A380E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x124F2100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816E4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x007B007B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c new file mode 100644 index 00000000000..cd129e12959 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24AB321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2EE233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C760000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x015B015B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x015B2213}, + {0x4e300308, 0x0A3C0E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x12552100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816B4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x00AA00AA}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + 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0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx93_frdm/spl.c b/board/freescale/imx93_frdm/spl.c new file mode 100644 index 00000000000..006c752d071 --- /dev/null +++ b/board/freescale/imx93_frdm/spl.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "lpddr4_timing.h" + +#include <init.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <dm/uclass-internal.h> +#include <linux/delay.h> +#include <power/pca9450.h> +#include <power/pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SRC_DDRC_SW_CTRL (0x44461020) +#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) + +static struct _drams { + u8 mr8; + struct dram_timing_info *pdram_timing; + char *name; +} frdm_drams[2] = { + {0x10, &dram_timing_1GB, "1GB DRAM" }, + {0x18, &dram_timing_2GB, "2GB DRAM" }, +}; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { + struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ret = ddr_init(ptiming); + if (ret == 0) { + if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { + printf("found DRAM %s matched\n", frdm_drams[i].name); + break; + } + + /* Power down and Power up DDR Mixer */ + + /* Clear PwrOkIn via DDRMIX register */ + setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + /* Power off the DDRMIX */ + setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + + udelay(50); + + /* Power up the DDRMIX */ + clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + } + } +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c index 388d99106db..503a8667245 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.c +++ b/board/freescale/imx93_qsb/imx93_qsb.c @@ -9,11 +9,6 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/board/freescale/imx93_qsb/imx93_qsb.env b/board/freescale/imx93_qsb/imx93_qsb.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.env +++ b/board/freescale/imx93_qsb/imx93_qsb.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env b/board/freescale/imx95_evk/imx95_19x19_evk.env index a002767e874..a7309d734b0 100644 --- a/board/freescale/imx95_evk/imx95_19x19_evk.env +++ b/board/freescale/imx95_evk/imx95_19x19_evk.env @@ -14,7 +14,7 @@ cntr_file=os_cntr_signed.bin boot_fit=no fdtfile=CONFIG_DEFAULT_FDT_FILE bootm_size=0x10000000 -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; diff --git a/board/freescale/imx95_evk/imx95_evk.c b/board/freescale/imx95_evk/imx95_evk.c index d5f5e310b6b..fe0111be508 100644 --- a/board/freescale/imx95_evk/imx95_evk.c +++ b/board/freescale/imx95_evk/imx95_evk.c @@ -15,11 +15,6 @@ int board_early_init_f(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index bda2f3ac3a6..39b6c6449cf 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -7,6 +7,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 7f8ca2e857f..26a5962bd6e 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -7,6 +7,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 446a79e6723..50c5320b55c 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -93,6 +93,7 @@ int testdram(void) #ifdef CONFIG_IDE #include <ata.h> +#include <ide.h> void ide_set_reset(int idereset) { atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c index 17095c34e92..a58ab93f27d 100644 --- a/board/freescale/mx6memcal/mx6memcal.c +++ b/board/freescale/mx6memcal/mx6memcal.c @@ -13,11 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int checkboard(void) { puts("Board: mx6memcal\n"); diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 3db167c0dad..bef4f901ff7 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Freescale Semiconductor, Inc. */ +#include <env.h> #include <init.h> #include <net.h> #include <asm/arch/clock.h> diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index 915a8b994d5..2bba377d4d4 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -12,6 +12,7 @@ */ #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index cc933ccd544..00ea9d8f503 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -9,6 +9,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index c2d526ae15a..038e40e2fae 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -12,6 +12,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index d2226af6278..838d88d977e 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -7,6 +7,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index f076350c1c5..258581eee96 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -16,6 +16,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/gateworks/fsa.c b/board/gateworks/fsa.c new file mode 100644 index 00000000000..1af8021057c --- /dev/null +++ b/board/gateworks/fsa.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Gateworks Corporation + */ + +#include <command.h> +#include <hexdump.h> +#include <i2c.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> // device_remove/device_unbind +#include <asm-generic/gpio.h> +#include <fdt_support.h> +#include <linux/delay.h> + +#include "fsa.h" + +static int fsa; +static struct udevice *fsa_gpiodevs[FSA_MAX] = { NULL }; + +/* find the ofnode of the FSA i2c bus */ +static ofnode fsa_get_ofnode(int fsa) +{ + char str[32]; + + /* by alias */ + snprintf(str, sizeof(str), "fsa%d", fsa); + return ofnode_get_aliases_node(str); +} + +static int fsa_get_dtnode(void *fdt, int fsa) +{ + char str[32]; + + /* by alias */ + snprintf(str, sizeof(str), "fsa%d", fsa); + return fdt_path_offset(fdt, fdt_get_alias(fdt, str)); +} + +static const char * const fsa_gpio_config_names[] = { "NC", "", "input", "output-low", + "output-high" }; + +static const char *fsa_gpio_config_name(struct fsa_gpio_desc *desc) +{ + if (desc->config < ARRAY_SIZE(fsa_gpio_config_names)) + return fsa_gpio_config_names[desc->config]; + return NULL; +}; + +static char *fsa_get_gpio_desc(struct fsa_gpio_desc *desc, char *str, int sz) +{ + str[0] = 0; + if (desc->source == 0xff) { + snprintf(str, sz, "fsa_gpio%d : %s %s", + desc->offset + 1, + desc->name, + fsa_gpio_config_name(desc)); + } else if (desc->config) { + snprintf(str, sz, "gpio@%02x_%02d: %s %s", + desc->source, + desc->offset, + desc->name, + fsa_gpio_config_name(desc)); + } + return str; +} + +static void fsa_show_gpio_descs(const char *prefix, int fsa, struct fsa_board_info *board_info, + struct fsa_user_info *user_info) +{ + char str[128]; + int i; + + /* display slot specific gpios */ + for (i = 0; i < board_info->sockgpios; i++) { + fsa_get_gpio_desc(&user_info->gpios[i], str, sizeof(str)); + printf("%s%-2d: %s\n", prefix, i, str); + } + /* display io-expander specific gpios */ + if (fsa_gpiodevs[fsa]) { + for (i = board_info->sockgpios; + i < (board_info->sockgpios + board_info->ioexpgpios); + i++) { + fsa_get_gpio_desc(&user_info->gpios[i], str, sizeof(str)); + printf("%s%-2d: %s\n", prefix, i, str); + } + } +} + +/* detect gpio expander by address and deal with enabling/disabling/adding gpio expander to dt */ +static int fsa_get_gpiodev(int fsa, int addr, struct udevice **devp) +{ + struct udevice *bus, *dev; + char gpio_name[32]; + int ret; + + ret = device_get_global_by_ofnode(fsa_get_ofnode(fsa), &bus); + if (ret) + return ret; + + sprintf(gpio_name, "gpio@%02x", addr); + + /* probe device on i2c bus */ + ret = dm_i2c_probe(bus, addr, 0, &dev); + switch (ret) { + case -EREMOTEIO: /* chip is not present on i2c bus */ + /* if device is in dt remove/unbind/disable it */ + ret = device_find_child_by_name(bus, gpio_name, &dev); + if (ret) + return ret; + ret = ofnode_set_enabled(dev_ofnode(dev), false); + if (ret) + return ret; + ret = device_unbind(dev); + if (ret) + return ret; + ret = device_remove(dev, DM_REMOVE_NORMAL); + if (ret) + return ret; + return ret; + case -ENOSYS: /* chip found but driver invalid */ + /* if device is in not in dt add/bind it */ + return ret; + case 0: /* chip responded and driver bound */ + break; + } + + if (devp) + *devp = dev; + return 0; +} + +/* add gpio's to gpio device: GPIO device must be probed before you can manipulate it */ +static int fsa_config_gpios(int fsa, struct fsa_user_info *info, int gpios, struct udevice *dev) +{ + struct fsa_gpio_desc *desc; + struct gpio_desc gdesc; + struct udevice *gdev; + int i, ret, flags; + char name[32]; + + /* configure GPIO's */ + for (i = 0; i < gpios; i++) { + desc = &info->gpios[i]; + if (desc->config < FSA_GPIO_INPUT) + continue; + memset(&gdesc, 0, sizeof(gdesc)); + + if (desc->source == 0xff) { + /* Board specific IMX8M GPIO's: find dev of controller by line-name */ + sprintf(name, "fsa%d_gpio%d", fsa, desc->offset + 1); + uclass_foreach_dev_probe(UCLASS_GPIO, gdev) { + ret = dev_read_stringlist_search(gdev, "gpio-line-names", name); + if (ret >= 0) { + gdesc.dev = gdev; + gdesc.offset = ret; + break; + } + } + } else { + /* port expander GPIOs */ + gdesc.dev = dev; + gdesc.offset = desc->offset; + } + + if (!gdesc.dev) + continue; + + sprintf(name, "fsa%d_%s", fsa, desc->name); + switch (desc->config) { + case FSA_GPIO_INPUT: + flags = GPIOD_IS_IN; + break; + case FSA_GPIO_OUTPUT_LOW: + flags = GPIOD_IS_OUT; + break; + case FSA_GPIO_OUTPUT_HIGH: + flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; + break; + } + if (!dm_gpio_request(&gdesc, name)) + dm_gpio_clrset_flags(&gdesc, GPIOD_MASK_DIR, flags); + } + + return 0; +} + +static int fsa_read_board_config(int fsa, struct fsa_board_info *info) +{ + struct udevice *dev; + int chksum; + int i, ret; + ofnode node; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@54"); + if (!ofnode_valid(node)) + return -EINVAL; + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + + /* read eeprom */ + ret = dm_i2c_read(dev, 0, (uint8_t *)info, sizeof(*info)); + if (ret) { + dev_err(dev, "read failed: %d\n", ret); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + dev_err(dev, "FSA%d EEPROM: Invalid User Config Checksum\n", fsa); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, info, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +static int fsa_read_user_config(int fsa, struct fsa_user_info *info) +{ + struct udevice *dev; + int chksum; + int i, ret; + ofnode node; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@55"); + if (!ofnode_valid(node)) + return -EINVAL; + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + + /* read eeprom */ + ret = dm_i2c_read(dev, 0, (uint8_t *)info, sizeof(*info)); + if (ret) { + dev_err(dev, "read failed: %d\n", ret); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + dev_err(dev, "FSA%d EEPROM: Invalid User Config Checksum\n", fsa); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, info, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +static int fsa_write_user_config(int fsa, struct fsa_user_info *info) +{ + struct udevice *bus, *dev; + int i, n, chunk, slave, base, ret; + ofnode node; + int chksum; + + /* create checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + info->chksum[0] = chksum >> 8; + info->chksum[1] = chksum & 0xff; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@55"); + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + bus = dev->parent; + base = dev_read_addr(dev); + + /* write in 16byte chunks (multi-byte writes fail larger than that) */ + chunk = 16; + slave = -1; + for (i = 0; i < sizeof(*info); i += chunk) { + /* select device based on offset */ + if ((base + (i / 256)) != slave) { + slave = base + (i / 256); + ret = i2c_get_chip(bus, slave, 1, &dev); + if (ret) { + dev_err(bus, "failed to get eeprom@0x%02x: %d\n", slave, ret); + return ret; + } + } + /* select byte count */ + n = sizeof(*info) - i; + if (n > chunk) + n = chunk; + ret = dm_i2c_write(dev, i % 256, (uint8_t *)info + i, n); + if (ret) { + dev_err(dev, "write failed: %d\n", ret); + return ret; + } + mdelay(11); + } + + return ret; +} + +static int fsa_detect(int fsa, struct fsa_board_info *board_info, struct fsa_user_info *user_info, + bool gpio) +{ + int ret; + + ret = fsa_read_board_config(fsa, board_info); + if (ret) + return ret; + if (user_info) { + ret = fsa_read_user_config(fsa, user_info); + if (ret) + return ret; + /* detect port expander */ + if (gpio && !fsa_get_gpiodev(fsa, 0x20, &fsa_gpiodevs[fsa])) + fsa_config_gpios(fsa, user_info, + board_info->sockgpios + board_info->ioexpgpios, + fsa_gpiodevs[fsa]); + } + + return ret; +} + +static int ft_fixup_stringlist_elem(void *fdt, int offset, const char *prop, int elem, + const char *val) +{ + const char *list, *end; + char *new, *buf; + int length; + int sz = 0; + int i = 0; + int ret; + + if (offset < 0 || elem < 0 || !val) { + printf("%s -EINVAL\n", __func__); + return -EINVAL; + } + + list = fdt_getprop(fdt, offset, prop, &length); + + /* no property or invalid params */ + if (!list || length < 0) { + printf("%s failed - no property\n", __func__); + return -EINVAL; + } + + /* create new buffer with enough space */ + buf = calloc(1, length + strlen(val)); + new = buf; + + /* iterate over current stringlist and build new list into buf */ + end = list + length; + while (list < end) { + length = strnlen(list, end - list) + 1; + sz += length; + /* insert new value into buf */ + if (elem == i) { + strcpy(new, val); + new += strlen(val) + 1; + } else { + strcpy(new, list); + new += length; + } + list += length; + i++; + } + length = new - buf; + ret = fdt_setprop(fdt, offset, prop, buf, length); + free(buf); + if (ret) + printf("%s failed %d\n", __func__, ret); + + return ret; +} + +static int ft_fixup_fsa_gpio_name(void *fdt, int offset, int fsa, int gpio, const char *name) +{ + const char *prop = "gpio-line-names"; + char str[32]; + + sprintf(str, "fsa%d_%s", fsa, name); + + if (!fdt_getprop(fdt, offset, prop, NULL)) { + char buf[16] = { 0 }; + + fdt_setprop(fdt, offset, prop, &buf, sizeof(buf)); + } + + return ft_fixup_stringlist_elem(fdt, offset, prop, gpio, str); +} + +static void fsa_show_details(int fsa, struct fsa_board_info *board, struct fsa_user_info *user) +{ + printf("FSA%d: %s\n", fsa, board->model); + printf("description: %s\n", user->desc); + printf("overlay: %s\n", user->overlay); + fsa_show_gpio_descs("\t", fsa, board, user); +} + +int fsa_init(void) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int fsa, ret; + + for (fsa = 1; fsa < FSA_MAX; fsa++) { + ret = fsa_detect(fsa, &board_info, &user_info, true); + if (!ret) + printf("FSA%d: %s %s\n", fsa, board_info.model, user_info.desc); + } + + return 0; +} + +int fsa_show(void) +{ + struct fsa_board_info board_info; + int fsa, ret; + + for (fsa = 1; fsa < FSA_MAX; fsa++) { + ret = fsa_detect(fsa, &board_info, NULL, false); + if (!ret) { + printf("FSA%d : %s %d %02x-%02x-%02x%02x\n", fsa, + board_info.model, board_info.serial, + board_info.mfgdate[0], board_info.mfgdate[1], + board_info.mfgdate[2], board_info.mfgdate[3]); + } + } + return 0; +} + +/* fixup gpio line names for fsa gpios */ +int fsa_ft_fixup(void *fdt) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int fsa, i, ret; + char path[128]; + char str[32]; + ofnode node; + int off; + + /* iterate over FSA's and rename gpio's */ + for (fsa = 1; fsa < FSA_MAX; fsa++) { + /* disable FSA ioexp node if disabled in controlling dt */ + off = fdt_subnode_offset(fdt, fsa_get_dtnode(fdt, fsa), "gpio@20"); + if (off >= 0) { + if (!fdt_get_path(fdt, off, path, sizeof(path))) { + node = ofnode_path(path); + if (ofnode_valid(node) && !ofnode_is_enabled(node)) + fdt_setprop_string(fdt, off, "status", "disabled"); + } + } + + /* detect FSA eeprom */ + if (fsa_detect(fsa, &board_info, &user_info, false)) + continue; + + /* configure GPIO's */ + for (i = 0; i < board_info.sockgpios + board_info.ioexpgpios; i++) { + if (user_info.gpios[i].config < FSA_GPIO_INPUT) + continue; + + if (user_info.gpios[i].source == 0xff) { + /* Board specific IMX8M GPIO's */ + for (off = fdt_node_offset_by_prop_value(fdt, 0, + "gpio-controller", NULL, + 0); + off >= 0; + off = fdt_node_offset_by_prop_value(fdt, off, + "gpio-controller", NULL, + 0) + ) { + sprintf(str, "fsa%d_gpio%d", fsa, + user_info.gpios[i].offset + 1); + ret = fdt_stringlist_search(fdt, off, "gpio-line-names", + str); + if (ret >= 0) { + ft_fixup_fsa_gpio_name(fdt, off, fsa, ret, + user_info.gpios[i].name); + break; + } + } + } else { + /* port expander GPIOs */ + off = fdt_subnode_offset(fdt, fsa_get_dtnode(fdt, fsa), "gpio@20"); + ft_fixup_fsa_gpio_name(fdt, off, fsa, user_info.gpios[i].offset, + user_info.gpios[i].name); + } + } + } + + return 0; +} + +static int do_fsa_dev(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int i; + + if (argc < 2) { + /* list FSAs */ + printf("detecting FSA Adapters:\n"); + for (i = 1; i < FSA_MAX; i++) { + if (!fsa_read_board_config(i, &board_info) && + !fsa_read_user_config(i, &user_info)) + printf("FSA%d : %s %s\n", i, board_info.model, user_info.desc); + } + } else { + /* select FSA */ + fsa = simple_strtoul(argv[1], NULL, 10); + } + + if (fsa) { + /* read FSA */ + if (!fsa_read_board_config(fsa, &board_info) && + !fsa_read_user_config(fsa, &user_info)) { + printf("selected:\n"); + fsa_show_details(fsa, &board_info, &user_info); + } else { + printf("FSA%d not detected\n", fsa); + fsa = 0; + } + } else { + printf("no FSA currently selected\n"); + } + + return 0; +} + +static int do_fsa_desc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + /* set */ + if (argc) { + strlcpy(user_info.desc, argv[0], sizeof(user_info.desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + } + + /* show */ + fsa_show_details(fsa, &board_info, &user_info); + + return CMD_RET_SUCCESS; +} + +static int do_fsa_overlay(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + /* set */ + if (argc) { + strlcpy(user_info.overlay, argv[0], sizeof(user_info.overlay)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + } + + /* show */ + fsa_show_details(fsa, &board_info, &user_info); + + return CMD_RET_SUCCESS; +} + +static int do_fsa_gpio(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + struct fsa_gpio_desc desc; + char str[64]; + int i, j; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + if (!argc) { + /* show all gpios */ + fsa_show_gpio_descs("\t", fsa, &board_info, &user_info); + return CMD_RET_SUCCESS; + } + + if (!isdigit(argv[0][0])) { + printf("invalid gpio offset: %s\n", argv[0]); + return CMD_RET_USAGE; + } + + memset(&desc, 0, sizeof(desc)); + i = simple_strtoul(argv[0], NULL, 10); + + if (i >= 0 && i < board_info.sockgpios) { + desc.offset = i; + desc.source = 0xff; + } else if (i >= board_info.sockgpios && + i < (board_info.sockgpios + board_info.ioexpgpios) && + fsa_gpiodevs[fsa]) { + desc.offset = i - board_info.sockgpios; + desc.source = 0x20; + } else { + printf("invalid index %d", i); + return CMD_RET_FAILURE; + } + + if (argc > 1) { + if (user_info.gpios[i].config == FSA_GPIO_NC) { + printf("can not alter NC gpio\n"); + return CMD_RET_FAILURE; + } + strlcpy(desc.name, argv[1], sizeof(desc.name)); + if (!*desc.name) { + printf("FSA%d %s erasing gpio %d\n", fsa, board_info.model, i); + memset(&user_info.gpios[i], 0, sizeof(desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + } + if (argc > 2) { + if (user_info.gpios[i].config == FSA_GPIO_NC) { + printf("can not alter NC gpio\n"); + return CMD_RET_FAILURE; + } + for (j = 1; j < ARRAY_SIZE(fsa_gpio_config_names); j++) { + if (!strcasecmp(argv[2], fsa_gpio_config_names[j])) { + desc.config = j; + break; + } + }; + if (j >= ARRAY_SIZE(fsa_gpio_config_names)) { + printf("invalid config type '%s\n", argv[2]); + return CMD_RET_FAILURE; + } + } + + /* show a specific gpio */ + if (argc == 1) { + printf("FSA%d %s showing gpio %d\n", fsa, board_info.model, i); + printf("%s\n", fsa_get_gpio_desc(&user_info.gpios[i], str, sizeof(str))); + return CMD_RET_SUCCESS; + } + + /* set a specific gpio */ + else if (argc == 3) { + printf("FSA%d %s updating gpio %d\n", fsa, board_info.model, i); + memcpy(&user_info.gpios[i], &desc, sizeof(desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + + return CMD_RET_USAGE; +} + +static struct cmd_tbl cmd_fsa_sub[] = { + U_BOOT_CMD_MKENT(dev, 1, 1, do_fsa_dev, "", ""), + U_BOOT_CMD_MKENT(gpio, 4, 1, do_fsa_gpio, "", ""), + U_BOOT_CMD_MKENT(description, 1, 1, do_fsa_desc, "", ""), + U_BOOT_CMD_MKENT(overlay, 1, 1, do_fsa_overlay, "", ""), +}; + +static int do_fsa(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + /* strip off leading fsa arg */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_fsa_sub, ARRAY_SIZE(cmd_fsa_sub)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + return CMD_RET_USAGE; +} + +U_BOOT_LONGHELP(fsa, + "dev [dev] - show or set current FSA adapter\n" + "fsa gpio - show current gpio descriptors\n" + "fsa gpio [<offset>]|[<offset> <source>] - show a specific gpio descriptor\n" + "fsa gpio [<offset> <name> <input|output-low|output-high> [source]] - set a gpio descriptor\n" + "fsa description [description] - show or set the FSA user description string\n" + "fsa overlay [overlay] - show or set the FSA overlay string\n" +); + +U_BOOT_CMD(fsa, 6, 1, do_fsa, + "Flexible Socket Adapter", + fsa_help_text +); diff --git a/board/gateworks/fsa.h b/board/gateworks/fsa.h new file mode 100644 index 00000000000..ddb64499d78 --- /dev/null +++ b/board/gateworks/fsa.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Gateworks Corporation + */ + +#ifndef _FSA_H_ +#define _FSA_H_ + +#define FSA_MAX 5 + +enum fsa_gpio_cfg { + FSA_GPIO_NC, + FSA_GPIO_UNCONFIGURED, + FSA_GPIO_INPUT, + FSA_GPIO_OUTPUT_LOW, + FSA_GPIO_OUTPUT_HIGH, +}; + +struct fsa_gpio_desc { + u8 offset; + u8 config; + u8 source; + char name[13]; +}; + +struct fsa_board_info { + char model[16]; /* 0x00: model string */ + u8 mac[6]; /* 0x10: MAC base */ + u8 macno; /* 0x16: number of mac addrs */ + u8 resv1; /* 0x17: reserved */ + u32 serial; /* 0x18: Serial Number */ + u8 mfgdate[4]; /* 0x1c: MFG date */ + u8 sockgpios; /* 0x20: number of socket gpio descriptors */ + u8 ioexpgpios; /* 0x21: number of io expander gpio descriptors */ + u8 resv2[220]; /* 0x22: reserved */ + u8 chksum[2]; /* 0xfe: */ +}; + +struct fsa_user_info { + char desc[32]; /* 0x000: user description */ + char overlay[16]; /* 0x020: dt-overlay suffice */ + struct fsa_gpio_desc gpios[20]; /* 0x030: gpio descriptors */ + u8 reserved[398]; /* 0x170: reserved */ + u8 chksum[2]; /* 0x2fe: */ +}; + +int fsa_init(void); +int fsa_show(void); +int fsa_ft_fixup(void *fdt); + +#endif // _FSA_H_ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 21a908c20dd..457d8281a66 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -6,6 +6,7 @@ */ #include <command.h> +#include <env.h> #include <fdt_support.h> #include <gsc.h> #include <hwconfig.h> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 3de4727b2ed..4385732a617 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -366,34 +366,34 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00480047, - .p0_mpwldectrl1 = 0X003D003F, + .p0_mpwldectrl0 = 0x00480047, + .p0_mpwldectrl1 = 0x003D003F, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0X423E0241, - .p0_mpdgctrl1 = 0X022B022C, + .p0_mpdgctrl0 = 0x423E0241, + .p0_mpdgctrl1 = 0x022B022C, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X49454A4A, + .p0_mprddlctl = 0x49454A4A, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X2E372C32, + .p0_mpwrdlctl = 0x2E372C32, }; static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00220021, - .p0_mpwldectrl1 = 0X00200030, - .p1_mpwldectrl0 = 0X002D0027, - .p1_mpwldectrl1 = 0X00150026, + .p0_mpwldectrl0 = 0x00220021, + .p0_mpwldectrl1 = 0x00200030, + .p1_mpwldectrl0 = 0x002D0027, + .p1_mpwldectrl1 = 0x00150026, /* Read DQS Gating calibration */ .p0_mpdgctrl0 = 0x43330342, .p0_mpdgctrl1 = 0x0339034A, .p1_mpdgctrl0 = 0x032F0325, .p1_mpdgctrl1 = 0x032F022E, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X3A2E3437, - .p1_mprddlctl = 0X35312F3F, + .p0_mprddlctl = 0x3A2E3437, + .p1_mprddlctl = 0x35312F3F, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X33363B37, - .p1_mpwrdlctl = 0X40304239, + .p0_mpwrdlctl = 0x33363B37, + .p1_mpwrdlctl = 0x40304239, }; static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile index ab69e07ba7b..1aaf0295d5c 100644 --- a/board/gateworks/venice/Makefile +++ b/board/gateworks/venice/Makefile @@ -5,6 +5,7 @@ # obj-y += venice.o eeprom.o +obj-y += ../fsa.o ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index afaabf34879..88bbc2e1af8 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -6,9 +6,11 @@ #include <gsc.h> #include <hexdump.h> #include <i2c.h> +#include <dm/device.h> #include <dm/uclass.h> #include "eeprom.h" +#include "../fsa.h" /* I2C */ #define SOM_EEPROM_BUSNO 0 @@ -18,7 +20,8 @@ struct venice_board_info som_info; struct venice_board_info base_info; -char venice_model[32]; +char venice_model[64]; +char venice_som_model[32]; char venice_baseboard_model[32]; u32 venice_serial; @@ -107,7 +110,7 @@ static int eeprom_read(int busno, int slave, int alen, struct venice_board_info /* validate checksum */ for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) chksum += buf[i]; - if ((info->chksum[0] != chksum >> 8) || + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || (info->chksum[1] != (chksum & 0xff))) { printf("EEPROM: I2C%d@0x%02x: Invalid Checksum\n", busno, slave); print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); @@ -126,6 +129,54 @@ static int eeprom_read(int busno, int slave, int alen, struct venice_board_info return 0; } +static int fsa_eeprom_read(const char *base, int fsa, struct fsa_board_info *info) +{ + int i; + int chksum; + unsigned char *buf = (unsigned char *)info; + struct udevice *dev, *bus; + int ret; + u8 reg; + + /* probe mux */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 2, &bus); + if (!ret) + ret = dm_i2c_probe(bus, 0x70, 0, &dev); + if (ret) + return ret; + /* steer mux */ + if (!strncmp(base, "GW82", 4)) { + if (fsa < 3) + reg = (fsa == 1) ? BIT(1) : BIT(0); + else + return -EINVAL; + } + dm_i2c_write(dev, 0x00, ®, 1); + + /* get eeprom */ + ret = dm_i2c_probe(bus, 0x54, 0, &dev); + if (ret) + return ret; + + /* read eeprom config section */ + ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info)); + if (ret) + return ret; + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += buf[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + printf("FSA%d EEPROM (board): %s: Invalid Checksum\n", fsa, dev->name); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + /* determine BOM revision from model */ int get_bom_rev(const char *str) { @@ -299,11 +350,13 @@ static int eeprom_info(bool verbose) base_info.mfgdate[0], base_info.mfgdate[1], base_info.mfgdate[2], base_info.mfgdate[3]); } + if (verbose) + fsa_show(); return 0; } -int venice_eeprom_init(int quiet) +struct venice_board_info *venice_eeprom_init(int quiet) { char rev_pcb; int rev_bom; @@ -315,6 +368,7 @@ int venice_eeprom_init(int quiet) memset(&som_info, 0, sizeof(som_info)); return 0; } + strlcpy(venice_som_model, som_info.model, sizeof(venice_som_model)); /* read optional baseboard EEPROM */ eeprom_read(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR, 2, &base_info); @@ -322,7 +376,7 @@ int venice_eeprom_init(int quiet) /* create model strings */ if (base_info.model[0]) { sprintf(venice_model, "GW%c%c%c%c-%c%c-", - som_info.model[2], /* family */ + base_info.model[2], /* family */ base_info.model[3], /* baseboard */ base_info.model[4], base_info.model[5], /* subload of baseboard */ som_info.model[4], som_info.model[5]); /* last 2digits of SOM */ @@ -347,10 +401,75 @@ int venice_eeprom_init(int quiet) } venice_serial = som_info.serial; + /* GW8xxx product family naming scheme */ + if (venice_model[2] == '8') { + struct fsa_board_info fsa_info; + int i = 0; + int fsa; + + /* baseboard */ + if (base_info.model[0]) { + rev_pcb = get_pcb_rev(base_info.model); + rev_bom = get_bom_rev(base_info.model); + venice_model[i++] = 'G'; + venice_model[i++] = 'W'; + venice_model[i++] = base_info.model[2]; /* baseboard */ + venice_model[i++] = base_info.model[3]; + venice_model[i++] = base_info.model[4]; /* subload */ + venice_model[i++] = base_info.model[5]; + venice_model[i++] = rev_pcb; + if (rev_bom) + venice_model[i++] = rev_bom; + venice_model[i++] = '-'; + venice_model[i++] = 'S'; + } else { + venice_model[i++] = 'G'; + venice_model[i++] = 'W'; + } + + /* som */ + rev_pcb = get_pcb_rev(som_info.model); + rev_bom = get_bom_rev(som_info.model); + venice_model[i++] = som_info.model[4]; + venice_model[i++] = som_info.model[5]; + venice_model[i++] = rev_pcb; + if (rev_bom) + venice_model[i++] = rev_bom; + + /* fsa */ + for (fsa = 1; fsa < FSA_MAX; fsa++) { + if (!fsa_eeprom_read(venice_model, fsa, &fsa_info)) { + venice_model[i++] = '-'; + venice_model[i++] = 'F'; + venice_model[i++] = '0' + fsa; + venice_model[i++] = fsa_info.model[5]; + venice_model[i++] = fsa_info.model[6]; + venice_model[i++] = fsa_info.model[8]; + if (fsa_info.model[9]) + venice_model[i++] = fsa_info.model[9]; + } + } + + /* append extra model info */ + if (som_info.config[0] >= 32 && som_info.config[0] < 0x7f) { + venice_model[i++] = '-'; + strlcpy(venice_model + i, som_info.config, (sizeof(venice_model) - i) - 1); + i += strlen(som_info.config); + if (i >= sizeof(venice_model)) + i = sizeof(venice_model) - 1; + } + venice_model[i++] = 0; + } + if (!quiet) eeprom_info(false); - return (16 << som_info.sdram_size); + if (!strncmp(venice_model, "GW7901-SP486", 12) && + strcmp(venice_model, "GW7901-SP486-C")) { + som_info.sdram_size++; + } + + return &som_info; } void board_gsc_info(void) @@ -363,6 +482,11 @@ const char *eeprom_get_model(void) return venice_model; } +const char *eeprom_get_som_model(void) +{ + return venice_som_model; +} + const char *eeprom_get_baseboard_model(void) { return venice_baseboard_model; diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h index bb7a5fa9ad1..817277f6276 100644 --- a/board/gateworks/venice/eeprom.h +++ b/board/gateworks/venice/eeprom.h @@ -18,14 +18,16 @@ struct venice_board_info { u8 sdram_size; /* 0x2B: (16 << n) MB */ u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */ u8 sdram_width; /* 0x2D: (8 << n) bit */ - u8 res3[2]; /* 0x2E */ + u8 sdram_variant; /* 0x2E */ + u8 res3[1]; /* 0x2D */ char model[16]; /* 0x30: model string */ - u8 res4[14]; /* 0x40 */ + u8 config[14]; /* 0x40: model config */ u8 chksum[2]; /* 0x4E */ }; -int venice_eeprom_init(int quiet); +struct venice_board_info *venice_eeprom_init(int quiet); const char *eeprom_get_model(void); +const char *eeprom_get_som_model(void); const char *eeprom_get_baseboard_model(void); const char *eeprom_get_dtb_name(int level, char *buf, int len); int eeprom_getmac(int index, uint8_t *enetaddr); diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index d19902f10ec..e4aa8b6821c 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -6,18 +6,7 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -#ifdef CONFIG_IMX8MM -extern struct dram_timing_info dram_timing_512mb; -extern struct dram_timing_info dram_timing_1gb; -extern struct dram_timing_info dram_timing_2gb; -extern struct dram_timing_info dram_timing_4gb; -#elif CONFIG_IMX8MN -extern struct dram_timing_info dram_timing_1gb_single_die; -extern struct dram_timing_info dram_timing_2gb_single_die; -extern struct dram_timing_info dram_timing_2gb_dual_die; -#elif CONFIG_IMX8MP -extern struct dram_timing_info dram_timing_1gb_single_die; -extern struct dram_timing_info dram_timing_4gb_dual_die; -#endif +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc); #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c index 3f2c090a94f..896a5c66eb6 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c @@ -6,9 +6,12 @@ */ #include <linux/kernel.h> +#include <string.h> #include <asm/arch/ddr.h> #include <asm/arch/lpddr4_define.h> +#include "eeprom.h" + /* ddr phy trained csr */ static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { { 0x200b2, 0x0 }, @@ -1333,7 +1336,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x203 }, + { 0x3d400020, 0x223 }, { 0x3d400024, 0x3a980 }, { 0x3d400064, 0x5b0062 }, { 0x3d4000d0, 0xc00305ba }, @@ -1385,7 +1388,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1 }, + { 0x3d402020, 0x21 }, { 0x3d402024, 0x7d00 }, { 0x3d402050, 0x20d040 }, { 0x3d402064, 0xc000d }, @@ -1410,7 +1413,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1 }, + { 0x3d403020, 0x21 }, { 0x3d403024, 0x1f40 }, { 0x3d403050, 0x20d040 }, { 0x3d403064, 0x30004 }, @@ -1459,9 +1462,9 @@ static struct dram_cfg_param ddr_ddrphy_cfg_512mb[] = { { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, - { 0x120a3, 0x4 }, + { 0x120a3, 0x2 }, { 0x120a4, 0x5 }, - { 0x120a5, 0x2 }, + { 0x120a5, 0x4 }, { 0x120a6, 0x7 }, { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, @@ -1830,7 +1833,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_512mb[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_512mb = { +static struct dram_timing_info dram_timing_512mb = { .ddrc_cfg = ddr_ddrc_cfg_512mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), .ddrphy_cfg = ddr_ddrphy_cfg_512mb, @@ -1889,6 +1892,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -2160,56 +2164,26 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x131f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, { 0x54034, 0x6600 }, @@ -2222,69 +2196,33 @@ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; /* P1 message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, @@ -2297,69 +2235,33 @@ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; /* P2 message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x102 }, { 0x54003, 0x64 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, @@ -2372,69 +2274,35 @@ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, { 0x5400d, 0x100 }, - { 0x5400e, 0x0 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, { 0x54034, 0x6600 }, @@ -2447,13 +2315,6 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; @@ -2489,7 +2350,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_1gb = { +static struct dram_timing_info dram_timing_1gb = { .ddrc_cfg = lpddr4_ddrc_cfg_1gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_1gb, @@ -2548,6 +2409,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -3005,7 +2867,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_4gb = { +static struct dram_timing_info dram_timing_4gb = { .ddrc_cfg = lpddr4_ddrc_cfg_4gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_4gb, @@ -3064,6 +2926,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -3140,12 +3003,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, @@ -3156,12 +3019,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x5 }, - { 0x130a3, 0x2 }, - { 0x130a4, 0x3 }, - { 0x130a5, 0x4 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -3521,7 +3384,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_2gb = { +static struct dram_timing_info dram_timing_2gb = { .ddrc_cfg = lpddr4_ddrc_cfg_2gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_2gb, @@ -3534,3 +3397,108 @@ struct dram_timing_info dram_timing_2gb = { .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz, + struct dram_cfg_param *patch, int patch_sz) +{ + int i, j; + + for (i = 0; i < cfg_sz; i++) + for (j = 0; j < patch_sz; j++) + if (cfg[i].reg == patch[j].reg) + cfg[i].val = patch[j].val; +} + +static struct dram_cfg_param ddr_ddrc_cfg_alt_patch[] = { + { 0x3d400020, 0x203}, + { 0x3d402020, 0x1}, + { 0x3d403020, 0x1} +}; + +static struct dram_cfg_param ddr_ddrphy_cfg_alt_patch[] = { + { 0x120a3, 0x4 }, + { 0x120a5, 0x2 }, +}; + +/* 4GB single Die patch (MT53E1G32D2FW-046 revC) */ +static struct dram_cfg_param ddr_ddrc_cfg_4gb_single_die_patch[] = { + { 0x3d400000, 0xa1080020 }, + { 0x3d400064, 0x5b011d }, + { 0x3d40011c, 0x402 }, + { 0x3d400138, 0x123 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400200, 0x1f }, + { 0x3d40021c, 0xf07 }, + { 0x3d402064, 0xc0026 }, + { 0x3d40211c, 0x302 }, + { 0x3d402138, 0x27 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403064, 0x3000a }, + { 0x3d40311c, 0x302 }, + { 0x3d403138, 0xa }, + { 0x3d4030f4, 0x599 } +}; + +static struct dram_cfg_param fsp_msg_4gb_single_die_patch[] = { + { 0x00054012, 0x110 }, + { 0x0005402c, 0x1 }, +}; + +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc) +{ + struct dram_timing_info *dram_timing; + int sizemb = (16 << info->sdram_size); + int i; + + switch (sizemb) { + case 512: + dram_timing = &dram_timing_512mb; + break; + case 1024: + dram_timing = &dram_timing_1gb; + break; + case 2048: + dram_timing = &dram_timing_2gb; + break; + case 4096: + dram_timing = &dram_timing_4gb; + if (info->sdram_variant == 1) { + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); + apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num, + ddr_ddrc_cfg_4gb_single_die_patch, + ARRAY_SIZE(ddr_ddrc_cfg_4gb_single_die_patch)); + for (i = 0; i < 4; i++) { + apply_cfg_patch(dram_timing->fsp_msg[i].fsp_cfg, + dram_timing->fsp_msg[i].fsp_cfg_num, + fsp_msg_4gb_single_die_patch, + ARRAY_SIZE(fsp_msg_4gb_single_die_patch)); + } + } else if (dram_desc) { + strlcpy(dram_desc, "dual-die", sz_desc); + } + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_1gb; + } + + /* apply ddrc/phy register changes for alternate dram bus layout */ + if (!strncmp(model, "GW7902", 6) || + !strncmp(model, "GW7903", 6) || + !strncmp(model, "GW7904", 6)) { + apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num, + ddr_ddrc_cfg_alt_patch, + ARRAY_SIZE(ddr_ddrc_cfg_alt_patch)); + + apply_cfg_patch(dram_timing->ddrphy_cfg, dram_timing->ddrphy_cfg_num, + ddr_ddrphy_cfg_alt_patch, + ARRAY_SIZE(ddr_ddrphy_cfg_alt_patch)); + } + + if (ddr_init(dram_timing)) + return NULL; + + return dram_timing; +} diff --git a/board/gateworks/venice/lpddr4_timing_imx8mn.c b/board/gateworks/venice/lpddr4_timing_imx8mn.c index 9ba2d2571ce..cad4fc0d31c 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mn.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mn.c @@ -1,8 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ #include <linux/kernel.h> +#include <string.h> #include <asm/arch/ddr.h> +#include "eeprom.h" + /* * Generated code from MX8M_DDR_tool v3.20 using RPAv15 */ @@ -1425,7 +1428,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_1gb_single_die = { +static struct dram_timing_info dram_timing_1gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, @@ -1890,7 +1893,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2gb_single_die = { +static struct dram_timing_info dram_timing_2gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_2gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_2gb_single_die, @@ -2354,7 +2357,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_dual_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2gb_dual_die = { +static struct dram_timing_info dram_timing_2gb_dual_die = { .ddrc_cfg = ddr_ddrc_cfg_2gb_dual_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_dual_die), .ddrphy_cfg = ddr_ddrphy_cfg_2gb_dual_die, @@ -2367,3 +2370,37 @@ struct dram_timing_info dram_timing_2gb_dual_die = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 400, 100, }, }; + +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc) +{ + struct dram_timing_info *dram_timing; + int sizemb = (16 << info->sdram_size); + + switch (sizemb) { + case 1024: + dram_timing = &dram_timing_1gb_single_die; + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); + break; + case 2048: + if (!strcmp(model, "GW7902-SP466-A") || + !strcmp(model, "GW7902-SP466-B")) { + dram_timing = &dram_timing_2gb_dual_die; + if (dram_desc) + strlcpy(dram_desc, "dual-die", sz_desc); + } else { + dram_timing = &dram_timing_2gb_single_die; + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); + } + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_2gb_dual_die; + } + if (ddr_init(dram_timing)) + return NULL; + + return dram_timing; +} diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 56c6e2b5cff..f2d5d9ce565 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1,8 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ #include <linux/kernel.h> +#include <string.h> #include <asm/arch/ddr.h> +#include "eeprom.h" + /* * Generated code from MX8M_DDR_tool v3.30 using MX8M_Plus RPAv7 */ @@ -1832,7 +1835,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_1gb_single_die = { +static struct dram_timing_info dram_timing_1gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, @@ -2364,7 +2367,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_4gb_dual_die = { +static struct dram_timing_info dram_timing_4gb_dual_die = { .ddrc_cfg = ddr_ddrc_cfg_4gb_dual_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4gb_dual_die), .ddrphy_cfg = ddr_ddrphy_cfg_4gb_dual_die, @@ -2377,3 +2380,30 @@ struct dram_timing_info dram_timing_4gb_dual_die = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 4000, 400, 100, }, }; + +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc) +{ + struct dram_timing_info *dram_timing; + int sizemb = (16 << info->sdram_size); + + switch (sizemb) { + case 1024: + dram_timing = &dram_timing_1gb_single_die; + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); + break; + case 4096: + dram_timing = &dram_timing_4gb_dual_die; + if (dram_desc) + strlcpy(dram_desc, "dual-die", sz_desc); + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_4gb_dual_die; + } + if (ddr_init(dram_timing)) + return NULL; + + return dram_timing; +} diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index bcdc1a2a468..2c303211d32 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -32,69 +32,6 @@ #define PCIE_RSTN IMX_GPIO_NR(4, 6) -static void spl_dram_init(int size) -{ - struct dram_timing_info *dram_timing; - - switch (size) { -#ifdef CONFIG_IMX8MM - case 512: - dram_timing = &dram_timing_512mb; - break; - case 1024: - dram_timing = &dram_timing_1gb; - break; - case 2048: - dram_timing = &dram_timing_2gb; - break; - case 4096: - dram_timing = &dram_timing_4gb; - break; - default: - printf("Unknown DDR configuration: %d MiB\n", size); - dram_timing = &dram_timing_1gb; - size = 1024; -#elif CONFIG_IMX8MN - case 1024: - dram_timing = &dram_timing_1gb_single_die; - break; - case 2048: - if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") || - !strcmp(eeprom_get_model(), "GW7902-SP466-B")) { - dram_timing = &dram_timing_2gb_dual_die; - } else { - dram_timing = &dram_timing_2gb_single_die; - } - break; - default: - printf("Unknown DDR configuration: %d MiB\n", size); - dram_timing = &dram_timing_2gb_dual_die; - size = 2048; -#elif CONFIG_IMX8MP - case 1024: - dram_timing = &dram_timing_1gb_single_die; - break; - case 4096: - dram_timing = &dram_timing_4gb_dual_die; - break; - default: - printf("Unknown DDR configuration: %d GiB\n", size); - dram_timing = &dram_timing_4gb_dual_die; - size = 4096; -#endif - } - - printf("DRAM : LPDDR4 "); - if (size > 512) - printf("%d GiB", size / 1024); - else - printf("%d MiB", size); - printf(" %dMT/s %dMHz\n", - dram_timing->fsp_msg[0].drate, - dram_timing->fsp_msg[0].drate / 2); - ddr_init(dram_timing); -} - /* * Model specific PMIC adjustments necessary prior to DRAM init * @@ -118,21 +55,23 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) return dm_i2c_write(dev, reg, &val, 1); } -static int power_init_board(struct udevice *gsc) +static int power_init_board(const char *model, struct udevice *gsc) { - const char *model = eeprom_get_model(); + const char *som = eeprom_get_som_model(); struct udevice *bus; struct udevice *dev; int ret; - /* Enable GSC voltage supervisor for new board models */ - if ((!strncmp(model, "GW7100", 6) && model[10] > 'D') || - (!strncmp(model, "GW7101", 6) && model[10] > 'D') || - (!strncmp(model, "GW7200", 6) && model[10] > 'E') || - (!strncmp(model, "GW7201", 6) && model[10] > 'E') || - (!strncmp(model, "GW7300", 6) && model[10] > 'E') || - (!strncmp(model, "GW7301", 6) && model[10] > 'E') || - (!strncmp(model, "GW740", 5) && model[7] > 'B')) { + /* Enable GSC voltage supervisor only for newew board models */ + if ((!strncmp(model, "GW7100", 6) && model[10] < 'E') || + (!strncmp(model, "GW7101", 6) && model[10] < 'E') || + (!strncmp(model, "GW7200", 6) && model[10] < 'F') || + (!strncmp(model, "GW7201", 6) && model[10] < 'F') || + (!strncmp(model, "GW7300", 6) && model[10] < 'F') || + (!strncmp(model, "GW7301", 6) && model[10] < 'F') || + (!strncmp(model, "GW740", 5) && model[7] < 'C')) { + printf("GSC : voltage supervisor disabled\n"); + } else { u8 ver; if (!dm_i2c_read(gsc, 14, &ver, 1) && ver > 62) { @@ -141,10 +80,7 @@ static int power_init_board(struct udevice *gsc) } } - if ((!strncmp(model, "GW71", 4)) || - (!strncmp(model, "GW72", 4)) || - (!strncmp(model, "GW73", 4)) || - (!strncmp(model, "GW75", 4))) { + if (!strncmp(som, "GW70", 4)) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); @@ -251,9 +187,12 @@ static int power_init_board(struct udevice *gsc) void board_init_f(ulong dummy) { + struct dram_timing_info *dram_timing; + struct venice_board_info *eeprom; struct udevice *bus, *dev; + const char *model; + char dram_desc[32]; int i, ret; - int dram_sz; arch_cpu_init(); @@ -311,13 +250,89 @@ void board_init_f(ulong dummy) break; mdelay(1); } - dram_sz = venice_eeprom_init(0); + eeprom = venice_eeprom_init(0); + model = eeprom_get_model(); /* PMIC */ - power_init_board(dev); + power_init_board(model, dev); /* DDR initialization */ - spl_dram_init(dram_sz); + dram_desc[0] = 0; + dram_timing = spl_dram_init(model, eeprom, dram_desc, sizeof(dram_desc)); + if (dram_timing) { + int dram_szmb = (16 << eeprom->sdram_size); + + printf("DRAM : LPDDR4 "); + if (dram_szmb > 512) + printf("%d GiB", dram_szmb / 1024); + else + printf("%d MiB", dram_szmb); + printf(" %dMT/s %dMHz %s", + dram_timing->fsp_msg[0].drate, + dram_timing->fsp_msg[0].drate / 2, + dram_desc[0] ? dram_desc : ""); + +#ifdef DEBUG + u8 mr[9] = { 0 }; + /* Read MR5-MR8 to obtain details about DRAM part (and verify DRAM working) */ + for (i = 5; i < 9; i++) + mr[i] = lpddr4_mr_read(0xf, i) & 0xff; + + printf(" (0x%02x%02x%02x%02x", mr[5], mr[6], mr[7], mr[8]); + /* MR5 MFG_ID */ + switch (mr[5]) { + case 0xff: + printf(" Micron"); + break; + default: + break; + } + /* MR8 OP[7:6] Width */ + i = 0; + switch ((mr[8] >> 6) & 0x3) { + case 0: + i = 16; + break; + case 1: + i = 8; + break; + } + if (i) + printf(" x%d", i); + /* MR8 OP[5:2] Density */ + i = 0; + switch ((mr[8] >> 2) & 0xf) { + case 0: + i = 4; + break; + case 1: + i = 6; + break; + case 2: + i = 8; + break; + case 3: + i = 12; + break; + case 4: + i = 16; + break; + case 5: + i = 24; + break; + case 6: + i = 32; + break; + default: + break; + } + if (i) + printf(" %dGb per die", i); +#endif + puts(")\n"); + } else { + hang(); + } board_init_r(NULL, 0); } diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 98b33624f04..6a24f618ae2 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -3,6 +3,7 @@ * Copyright 2021 Gateworks Corporation */ +#include <env.h> #include <fdt_support.h> #include <init.h> #include <led.h> @@ -14,6 +15,7 @@ #include <asm/mach-imx/boot_mode.h> #include "eeprom.h" +#include "../fsa.h" int board_phys_sdram_size(phys_size_t *size) { @@ -75,6 +77,9 @@ int board_init(void) { venice_eeprom_init(1); + /* detect and configure FSA adapters */ + fsa_init(); + return 0; } @@ -221,6 +226,9 @@ int ft_board_setup(void *fdt, struct bd_info *bd) /* set board model dt prop */ fdt_setprop_string(fdt, 0, "board", eeprom_get_model()); + /* fixups for FSA adapters */ + fsa_ft_fixup(fdt); + if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); path = fdt_get_alias(fdt, "ethernet1"); diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index c1aacd1458b..ddb7304d493 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/mach-imx/video.h> #include <command.h> +#include <env.h> #include <i2c.h> #include <input.h> #include <ipu_pixfmt.h> diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c index 4d3049689d3..d8ffdd25b38 100644 --- a/board/google/chameleonv3/board.c +++ b/board/google/chameleonv3/board.c @@ -2,6 +2,8 @@ /* * Copyright 2022 Google LLC */ + +#include <env.h> #include <net.h> #include <errno.h> #include "mercury_aa1.h" diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index db96534857c..b4053fa097d 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -11,13 +11,13 @@ #include <dm.h> #include <event.h> #include <init.h> +#include <intel_gnvs.h> #include <log.h> #include <sysinfo.h> #include <acpi/acpigen.h> #include <asm-generic/gpio.h> #include <asm/acpi_nhlt.h> #include <asm/cb_sysinfo.h> -#include <asm/intel_gnvs.h> #include <asm/intel_pinctrl.h> #include <dm/acpi.h> #include <linux/delay.h> diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index c2a44b4aa2d..492d1dc1d8c 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -84,7 +84,7 @@ static int mmc_get_env_devno(void) /* If not boot from sd/mmc, use default value */ if (bootsel != 1) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ dev_no = (soc_sbmr & 0x00001800) >> 11; diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 29165266630..5e60ab9d7b7 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -372,11 +372,6 @@ int misc_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MMC static int init_dwmmc(void) diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 4a72ab5ceca..0ffa964178f 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -6,7 +6,6 @@ #include <config.h> #include <fdt_support.h> -#include <ide.h> #include <init.h> #include <net.h> #include <netdev.h> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a35a7cd3b1f..c21b083b62a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -7,6 +7,7 @@ #include <env.h> #include <init.h> #include <malloc.h> +#include <mtd.h> #include <net.h> #include <status_led.h> #include <dm.h> diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 41458813858..b68c10f85e4 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -29,14 +29,6 @@ config KM_PHRAM help Start address of the physical RAM, which is the mounted /var folder. -config KM_RESERVED_PRAM - hex "Reserved RAM" - default 0x0 if MPC83xx - default 0x1000 if MPC85xx || ARCH_LS1021A - depends on !ARCH_SOCFPGA - help - Reserved physical RAM area at the end of memory for special purposes. - config KM_CRAMFS_ADDR hex "CRAMFS Address" default 0x83000000 if ARCH_LS1021A diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 25897af2d8a..4bdaf90deff 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -53,7 +53,7 @@ int set_km_env(void) char *p; pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; + CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf(envval, "0x%x", pnvramaddr); env_set("pnvramaddr", envval); @@ -61,12 +61,10 @@ int set_km_env(void) p = env_get("rootfssize"); if (p) strict_strtoul(p, 16, &rootfssize); - pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + - CONFIG_KM_PNVRAM) / 0x400; + pram = (rootfssize + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / 0x400; env_set_ulong("pram", pram); - varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); sprintf(envval, "0x%x", varaddr); env_set("varaddr", envval); diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index c8299483299..f8f8d5edede 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -18,6 +18,11 @@ #define DIRECT_OFF 0x18 #define GPRT_OFF 0x1c +// used to keep track of the user settings for the input/output +static u32 gprt_user[2] = { 0x0, 0x0 }; +// convert the bank offset to the correct static user gprt +#define QRIO_USER_GRPT_BANK(bank) gprt_user[(bank - 0x40) / 0x20] + void show_qrio(void) { void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; @@ -72,12 +77,13 @@ void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) mask = 1U << gpio_nr; - gprt = in_be32(qrio_base + port_off + GPRT_OFF); + gprt = QRIO_USER_GRPT_BANK(port_off); if (value) gprt |= mask; else gprt &= ~mask; + QRIO_USER_GRPT_BANK(port_off) = gprt; out_be32(qrio_base + port_off + GPRT_OFF, gprt); } diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 783853d5c6f..0f43ebfec4d 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -6,6 +6,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include <env.h> #include <event.h> #include <asm/cache.h> #include <asm/fsl_fdt.h> diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS index ed5baf269a7..7d80cfbf64f 100644 --- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -1,6 +1,6 @@ Hitachi Power Grids LS102XA BOARD -M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> -M: Rainer Boschung <rainer.boschung@hitachienergy.com> +M: Holger Brunck <holger.brunck@hitachienergy.com> +M: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com> S: Maintained F: board/keymile/pg-wcom-ls102xa/ F: board/keymile/common/ diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env index 1054dbf9f54..c1c73b7da49 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env @@ -1,3 +1,4 @@ #include <env/pg-wcom/ls102xa.env> hostname=EXPU1 +netdev=eth2 diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 409a55ebda6..7db75f4df3e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -38,7 +38,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int checkboard(void) { show_qrio(); - + i2c_deblock_gpio_cfg(); return 0; } @@ -96,8 +96,6 @@ int board_early_init_f(void) qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false); - i2c_deblock_gpio_cfg(); - /* enable the Unit LED (red) & Boot LED (on) */ qrio_set_leds(); diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env index 1232fe9da8b..bbfa8194a7e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env @@ -1,3 +1,4 @@ #include <env/pg-wcom/ls102xa.env> hostname=SELI8 +netdev=eth2 diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index b1758858705..33e5337bcbc 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -204,7 +204,7 @@ static struct mx6_ddr3_cfg mem_512M_ddr = { static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = { .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0X01440144, + .p0_mpdgctrl0 = 0x01440144, .p0_mprddlctl = 0x40405454, .p0_mpwrdlctl = 0x40404E4C, }; diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 8dcc2ea54f6..2e387038395 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -116,11 +116,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size); } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (!fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-n802x-som") || diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 0baf5c63f18..8a9502037fb 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -51,11 +51,6 @@ int board_early_init_f(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_eth_init(struct bd_info *bis) { return pci_eth_init(bis); diff --git a/board/lg/star/star.c b/board/lg/star/star.c index dc593754101..0b4a433a5df 100644 --- a/board/lg/star/star.c +++ b/board/lg/star/star.c @@ -9,6 +9,7 @@ #include <fdt_support.h> #include <log.h> #include <spl_gpio.h> +#include <asm/gpio.h> static int star_fix_panel(void *fdt) { diff --git a/board/liebherr/btt/Kconfig b/board/liebherr/btt/Kconfig new file mode 100644 index 00000000000..ff35dd04532 --- /dev/null +++ b/board/liebherr/btt/Kconfig @@ -0,0 +1,24 @@ +if TARGET_BTT + +config SYS_BOARD + default "btt" + +config SYS_VENDOR + default "liebherr" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "btt" + +config ENV_SIZE + default 0x2000 + +config ENV_SECT_SIZE + default 0x10000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x80000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/liebherr/btt/MAINTAINERS b/board/liebherr/btt/MAINTAINERS new file mode 100644 index 00000000000..b4afed5aaeb --- /dev/null +++ b/board/liebherr/btt/MAINTAINERS @@ -0,0 +1,6 @@ +BTT BOARD +M: Lukasz Majewski <lukma@denx.de> +S: Maintained +F: board/liebherr/btt/ +F: include/configs/btt.h +F: configs/imx28_btt3_defconfig diff --git a/board/liebherr/btt/Makefile b/board/liebherr/btt/Makefile new file mode 100644 index 00000000000..a8ab657a9e0 --- /dev/null +++ b/board/liebherr/btt/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2025 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := btt.o +obj-$(CONFIG_XPL_BUILD) += spl_btt.o diff --git a/board/liebherr/btt/boot_img_scr.h b/board/liebherr/btt/boot_img_scr.h new file mode 100644 index 00000000000..baa3072b49c --- /dev/null +++ b/board/liebherr/btt/boot_img_scr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Struct for boot image source description for placing in last + * two SPI NOR flash sectors on legcom. + */ + +struct boot_img_src { + u8 magic; /* Must be 'B' = 0x42 */ + u8 flags; /* flags to specify mmcblk[0|1] boot[0|1] */ + u8 crc8; /* CRC-8 over above two bytes */ +} __packed; + +/* + * Bit definition in boot_img_src.flags: + * Bit 0: mmcblk device 0 or 1 (1 - if this bit set) + * Bit 1: mmcblk boot partition 0 or 1. + * for eMMC: boot0 if this bit is cleared, boot1 - if set + * for SD-card the boot partition value will always be 0 + * (independent of the value of this bit) + * + */ +#define BOOT_SRC_MMC1 BIT(0) +#define BOOT_SRC_PART1 BIT(1) + +/* Offset of the first boot image source descriptor in SPI NOR */ +#define SPI_FLASH_BOOT_SRC_OFFS 0xFE0000 +#define SPI_FLASH_SECTOR_SIZE 0x10000 diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c new file mode 100644 index 00000000000..e05e333ac7e --- /dev/null +++ b/board/liebherr/btt/btt.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * BTT[3C] iMX28 board + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include <fdt_support.h> +#include <init.h> +#include <log.h> +#include <net.h> +#include <env.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <netdev.h> +#include <errno.h> +#include <serial.h> +#include <u-boot/crc.h> +#include "boot_img_scr.h" + +#include <spi.h> +#include <spi_flash.h> + +#ifdef CONFIG_XPL_BUILD +#include <spl.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ + +static void init_clocks(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + /* SSP3 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); +} + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +void board_init_f(ulong arg) +{ + init_clocks(); + spl_early_init(); + preloader_console_init(); +} + +static struct boot_img_src img_src[2]; +static int spi_load_boot_info(void) +{ + struct spi_flash *flash; + int err; + + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!flash) { + printf("%s: SPI probe err\n", __func__); + return -ENODEV; + } + + /* + * Load both boot info structs from SPI flash + */ + err = spi_flash_read(flash, SPI_FLASH_BOOT_SRC_OFFS, + sizeof(img_src[0]), + (void *)&img_src[0]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + err = spi_flash_read(flash, + SPI_FLASH_BOOT_SRC_OFFS + SPI_FLASH_SECTOR_SIZE, + sizeof(img_src[0]), + (void *)&img_src[1]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + debug("%s: BI0 0x%x 0x%x 0x%x\n", __func__, + img_src[0].magic, img_src[0].flags, img_src[0].crc8); + + debug("%s: BI1 0x%x 0x%x 0x%x\n", __func__, + img_src[1].magic, img_src[1].flags, img_src[1].crc8); + + return 0; +} + +#define BTT_MONITORING_DEVICE_TIMEOUT 100 +static int rescue_val; + +void spl_board_init(void) +{ + struct gpio_desc phy_rst, boot, rescue, wifi_en, bt_en; + int ret, i; + + /* + * On the new HW version of BTTC/3 (with LAN8720ai PHY) the !RST pin + * (15) is pulled LOW by external resistor. As a result it needs to be + * set HIGH as soon as possible to allow correct generation of RESET + * pulse. + * + * In the old BTTC (with TLK105 PHY) the RC circuit was used instead + * to set the RESET pin to HIGH after 100us, so there was no need to + * set it explicitly. + */ + ret = dm_gpio_lookup_name("GPIO4_12", &phy_rst); + if (ret) + printf("Cannot get GPIO4_12\n"); + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) + printf("Cannot request GPIO4_12\n"); + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls WL_EN (wifi) to LOW. On the BTT3 + * it is directly connected to Jody module without any externa pull up + * down register. + */ + ret = dm_gpio_lookup_name("GPIO0_27", &wifi_en); + if (ret) + printf("Cannot get GPIO0_27\n"); + + ret = dm_gpio_request(&wifi_en, "wifi-en"); + if (ret) + printf("Cannot request GPIO0_27\n"); + + dm_gpio_set_dir_flags(&wifi_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls BT_EN (Bluetooth) to LOW. On the + * BTT3 it is connected to Jody module via RC circuit (after some R*C + * time this pin is set to HIGH). However, the manual recommends setting + * it high from LOW state. + */ + ret = dm_gpio_lookup_name("GPIO3_27", &bt_en); + if (ret) + printf("Cannot get GPIO3_27\n"); + + ret = dm_gpio_request(&bt_en, "bt-en"); + if (ret) + printf("Cannot request GPIO3_27\n"); + + dm_gpio_set_dir_flags(&bt_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* 'boot' and 'rescue' pins */ + ret = dm_gpio_lookup_name("GPIO4_9", &boot); + if (ret) + printf("Cannot get GPIO4_9\n"); + + ret = dm_gpio_request(&boot, "boot"); + if (ret) + printf("Cannot request GPIO4_9\n"); + + dm_gpio_set_dir_flags(&boot, GPIOD_IS_IN); + + ret = dm_gpio_lookup_name("GPIO4_11", &rescue); + if (ret) + printf("Cannot get GPIO4_11\n"); + + ret = dm_gpio_request(&rescue, "rescue"); + if (ret) + printf("Cannot request GPIO4_11\n"); + + dm_gpio_set_dir_flags(&rescue, GPIOD_IS_IN); + + /* Wait for ready signal from system "monitoring" device */ + for (i = 0; i < BTT_MONITORING_DEVICE_TIMEOUT; i++) { + if (dm_gpio_get_value(&boot)) + break; + mdelay(10); + } + + rescue_val = dm_gpio_get_value(&rescue); +} + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int i, src_idx = -1, ret; + + ret = spi_load_boot_info(); + if (ret) { + printf("%s: Cannot read BTT boot info! [%d]\n", __func__, ret); + /* To avoid bricking board - by default boot from boot0 eMMC */ + return 1; + } + + for (i = 0; i < 2; i++) { + if (img_src[i].magic == 'B' && + img_src[i].crc8 == crc8(0, &img_src[i].magic, 2)) { + src_idx = i; + break; + } + } + + debug("%s: src idx: %d\n", __func__, src_idx); + + if (src_idx < 0) + /* + * Always use eMMC (mmcblkX) boot0 if no + * valid image source description found + */ + return 1; + + if (img_src[src_idx].flags & BOOT_SRC_PART1) + return 2; + + return 1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; +} + +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + debug("%s: rescue: %d\n", __func__, rescue_val); + return rescue_val; +} +#else + +/* + * Providing proper board name - i.e. 'bttc' vs 'btt3' + * The distinction is made on the size of DRAM memory - i.e. + * bttc has only 128 MiB, whereas btt3 has 256 MiB. + */ +#define STR_BTTC "bttc" +#define STR_BTT3 "btt3" + +static const char *get_board_name(void) +{ + if (gd->bd->bi_dram[0].size == SZ_128M) + return STR_BTTC; + + return STR_BTT3; +} + +/* + * Reading the HW ID number for BTT3 device + * + * GPIOs from Port 4: + * E0: GPIO4_10 + * E1: GPIO4_5 + * E2: GPIO4_14 + * E3: GPIO4_15 + * are used on BTT3 to store HW revision information. + * + * From rev 1+ the REV GPIOs are properly connected on the PCB, so PULL UPs + * shall be disabled (as they are by default on pins' SPL configuration) + *. + * Rev 0: - read all '1' (first production version without HW rev set) + * Rev 1: - read 0x1 (E0 set) + * Rev 2: - read 0x2 (E1 set) + * + */ +#define BTT3_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((4) * 0x10))) +#define BTT3_HW_ID_E0 BIT(10) +#define BTT3_HW_ID_E1 BIT(5) +#define BTT3_HW_ID_E2 BIT(14) +#define BTT3_HW_ID_E3 BIT(15) + +static u8 get_som_rev(void) +{ + struct mxs_register_32 *reg = + (struct mxs_register_32 *)BTT3_HW_ID_GPIO_PORT; + u32 tmp = ~readl(®->reg); + u8 id = 0; + + if (tmp & BTT3_HW_ID_E0) + id += 1; + + if (tmp & BTT3_HW_ID_E1) + id += 2; + + if (tmp & BTT3_HW_ID_E2) + id += 4; + + if (tmp & BTT3_HW_ID_E3) + id += 8; + + /* + * Special case for first production BTT3 version, without HW + * revision support (so it reads 0x0s as pullups are disabled + * and hence 0xF is set for ID) + */ + if (id == 0xF) + id = 0; + + return id; +} + +int board_early_init_f(void) +{ + init_clocks(); + + return 0; +} + +int board_init(void) +{ + struct gpio_desc phy_rst; + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + cpu_eth_init(NULL); + + /* PHY INT#/PWDN# */ + ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst); + if (ret) { + printf("Cannot get GPIO4_13\n"); + return ret; + } + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_13\n"); + return ret; + } + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN); + udelay(1000); + + return 0; +} + +#if defined(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + int ret = env_set_ulong("board_som_rev", get_som_rev()); + + if (ret) + printf("Cannot set BTT's SoM revision env variable!\n"); + + ret = env_set("arch", get_board_name()); + if (ret) + printf("Cannot set SoM 'arch' env variable!\n"); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO) +int checkboard(void) +{ + printf("Board: LWE BTT SoM HW rev %d\n", get_som_rev()); + + return 0; +} +#endif + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#if defined(CONFIG_OF_BOARD) +int board_fdt_blob_setup(void **fdtp) +{ + /* + * The only purpose of this function is the specific BTT's DTB + * setup in u-boot proper. To be more specific - the SPL + * cannot support DTB selection due to size constraints + * (SPL < 50 KiB). + * + * Hence, the DTB selection is done in u-boot, which due to + * board's partition sizes (and backward compatibility) has also + * size constrain (~448 KiB). + * + * To support multiple DTBs appended, the compression has been used + * for them. Unfortunately, the initf_malloc() is called + * after the DTB needs to be selected. To fix this problem for this + * particular setup (i.e. BTT board) the initf_malloc() is called here. + */ + initf_malloc(); + + return -EEXIST; +} +#endif + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + u8 rev_id = get_som_rev(); + char board[12]; + + sprintf(board, "imx28-btt3-%d", rev_id); + + if (!strncmp(name, board, sizeof(board))) + return 0; + + return -EINVAL; +} +#endif + +/* + * NOTE: + * + * IMX28 clock "stub" DM driver! + * + * Only used for SPL stage, which is NOT using DM; serial and + * eMMC configuration. + * + * It is required for SPL_OF_PLATDATA proper code generation as, + * this device has hard constrain on the size of the SPL binary + * (u-boot.sb). + */ +static const struct udevice_id imx28_clk_ids[] = { + { .compatible = "fsl,imx28-clkctrl", }, + { } +}; + +U_BOOT_DRIVER(fsl_imx28_clkctrl) = { + .name = "fsl_imx28_clkctrl", + .id = UCLASS_CLK, + .of_match = imx28_clk_ids, +}; +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/liebherr/btt/btt.env b/board/liebherr/btt/btt.env new file mode 100644 index 00000000000..aaf0b8415d1 --- /dev/null +++ b/board/liebherr/btt/btt.env @@ -0,0 +1,139 @@ +bootmode=update +bootpri=mmc_mmc +bootsec=sf_swu +consdev=ttyAMA0 +baudrate=115200 +dtbfile=imx28-btt3-1.dtb +rootdev=/dev/mmcblk0p2 +netdev=eth0 +swufile=swupdate-image-btt3-upd.itb +sf_kernel_offset=0xA0000 +sf_swu_size=0xF40000 +ethact=FEC +arch=btt3 +lwe_env= + if dhcp ${loadaddr} ${hostname}/${lwe_uenv} ; then + source ${loadaddr}; + fi +lwe_uenv=env_uboot_btt3.bin +do_update_mmc= + if mmc rescan ; then + mmc dev 0 ${update_mmc_part} ; + if dhcp ${hostname}/${update_filename} ; then + setexpr fw_sz ${filesize} / 0x200 ; + setexpr fw_sz ${fw_sz} + 1 ; + mmc write ${loadaddr} ${update_offset} ${fw_sz} ; + fi ; + fi +do_update_sf= + if sf probe ; then + if dhcp ${hostname}/${update_filename} ; then + sf erase ${update_offset} +${filesize} ; + sf write ${loadaddr} ${update_offset} ${filesize} ; + fi ; + fi +factory_reset= + if sf probe ; then + run update_swu ; + setenv bootmode update ; + saveenv ; + fi +update_spl_filename=u-boot.sb +update_spl= + setenv update_filename ${update_spl_filename} ; + setenv update_offset 0 ; + run do_update_sf +update_uboot_filename=u-boot.img +update_uboot= + setenv update_filename ${update_uboot_filename} ; + setenv update_offset 0x10000 ; + run do_update_sf ; + setenv update_mmc_part 1 ; + setenv update_offset 0 ; + run do_update_mmc ; + setenv update_mmc_part 2 ; + run do_update_mmc +update_kernel_filename=uImage +update_kernel= + setenv update_mmc_part 1 ; + setenv update_filename ${update_kernel_filename} ; + setenv update_offset 0x800 ; + run do_update_mmc ; + setenv update_filename ${dtbfile} ; + setenv update_offset 0x400 ; + run do_update_mmc +update_swu= + setenv update_filename ${swufile} ; + setenv update_offset ${sf_kernel_offset} ; + run do_update_sf +addcons= + setenv bootargs ${bootargs} + console=${consdev},${baudrate} +addip= + setenv bootargs ${bootargs} + ip=${ipaddr}:${serverip}:${gatewayip}: + ${netmask}:${hostname}:${netdev}:off +addmisc= + setenv bootargs ${bootargs} ${miscargs} +addargs=run addcons addmisc +mmcload= + mmc rescan ; + mmc dev 0 1 ; + mmc read ${loadaddr} 0x800 0x2000 ; + mmc read ${dtbaddr} 0x400 0x80 +netload= + dhcp ${loadaddr} ${hostname}/${bootfile} ; + tftp ${dtbaddr} ${hostname}/${dtbfile} +usbload= + usb start ; + load usb 0:1 ${loadaddr} ${bootfile} +miscargs=panic=1 +mmcargs=setenv bootargs root=${rootdev} rw rootwait +nfsargs= + setenv bootargs root=/dev/nfs rw + nfsroot=${serverip}:${rootpath},v3,tcp +mmc_mmc= + if run mmcload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +mmc_nfs= + if run mmcload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_mmc= + if run sfload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_swu= + if sf probe ; then + sf read ${loadaddr} ${sf_kernel_offset} ${sf_swu_size} ; + setenv bootargs root=/dev/ram0 rw ; + run addargs ; + bootm ${loadaddr}#conf-imx28-${arch}-${board_som_rev}.dtb ; + fi +net_mmc= + if run netload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +net_nfs= + if run netload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +prebootcmd= + if test ${envsaved} != y ; then ; + setenv envsaved y ; + saveenv ; + fi ; + if test ${bootmode} = normal ; then + setenv bootdelay 0 ; + setenv bootpri mmc_mmc ; + elif test ${bootmode} = devel ; then + setenv bootdelay 3 ; + setenv bootpri net_mmc ; + else + if test ${bootmode} != update ; then + echo Warning: unknown bootmode ${bootmode} ; + fi ; + setenv bootdelay 1 ; + setenv bootpri sf_swu ; + fi diff --git a/board/liebherr/btt/spl_btt.c b/board/liebherr/btt/spl_btt.c new file mode 100644 index 00000000000..da17e186b06 --- /dev/null +++ b/board/liebherr/btt/spl_btt.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DENX M28 Boot setup + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_BOOT (MXS_PAD_3V3) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +/* HW_PINCTRL_EMI_DS_CTRL */ +#define EMI_DS_CTRL_CLR 0x3FFF +#define EMI_DS_CTRL_SLICE0_SHIFT 0 +#define EMI_DS_CTRL_SLICE1_SHIFT 2 +#define EMI_DS_CTRL_SLICE2_SHIFT 4 +#define EMI_DS_CTRL_SLICE3_SHIFT 6 +#define EMI_DS_CTRL_DUALPAD_SHIFT 8 +#define EMI_DS_CTRL_CONTROL_SHIFT 10 +#define EMI_DS_CTRL_ADDRESS_SHIFT 12 +#define EMI_DS_CTRL_MA_20 0x10 + +/* + * The BTT devide can be boot in several ways; U-Boot's 'falcon' mode, + * normal boot (through U-Boot proper) and also via recovery system. + * + * To fix some HW issues on the device, as well as providing all the + * above boot method's the same "start" state when kernel starts it + * has been decided to configure PINMUXes for all relevant IP blocks + * (and GPIOs during early SPI state). + * + * It also shall be mentioned, that during early SPL stage, the BTT + * device needs to cooperate with uC based co-processor - this + * requires correct pins configuration. + */ +static const iomux_cfg_t iomux_setup[] = { + /* AUART0 IRDA */ + MX28_PAD_AUART0_RX__AUART0_RX, + MX28_PAD_AUART0_TX__AUART0_TX, + + /* AUART 4 RS422 */ + MX28_PAD_AUART0_CTS__AUART4_RX, + MX28_PAD_AUART0_RTS__AUART4_TX, + + /* USB0 */ + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT, + MX28_PAD_AUART1_RTS__USB0_ID, + MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */ + + /* USB1 */ + MX28_PAD_PWM2__USB1_OVERCURRENT, + + /* eMMC */ + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */ + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* DIG Keys */ + MX28_PAD_GPMI_D00__GPIO_0_0, + MX28_PAD_GPMI_D01__GPIO_0_1, + MX28_PAD_GPMI_D02__GPIO_0_2, + MX28_PAD_GPMI_D03__GPIO_0_3, + MX28_PAD_GPMI_D04__GPIO_0_4, + MX28_PAD_GPMI_D05__GPIO_0_5, + MX28_PAD_GPMI_D06__GPIO_0_6, + MX28_PAD_GPMI_D07__GPIO_0_7, + + /* ADR_0-2 */ + MX28_PAD_GPMI_CE1N__GPIO_0_17, + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + + /* Read Keys */ + MX28_PAD_GPMI_RDY0__GPIO_0_20, + + /* LATCH_EN */ + MX28_PAD_GPMI_RDY1__GPIO_0_21, + + /* Power off */ + MX28_PAD_GPMI_RDN__GPIO_0_24, + + /* WIFI EN */ + MX28_PAD_GPMI_CLE__GPIO_0_27, + + /* I2C1 Touch */ + MX28_PAD_AUART2_CTS__GPIO_3_10, + MX28_PAD_AUART2_RTS__GPIO_3_11, + MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */ + MX28_PAD_GPMI_RDY3__GPIO_0_23, /* Touch INT */ + + /* TIVA */ + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT, + MX28_PAD_SSP2_MISO__SSP2_D0, + MX28_PAD_SSP2_MOSI__SSP2_CMD, + MX28_PAD_SSP2_SCK__SSP2_SCK, + MX28_PAD_SSP2_SS0__SSP2_D3, + MX28_PAD_SSP2_SS1__GPIO_2_20, + MX28_PAD_SSP2_SS2__GPIO_2_21, + + /* SPI3 NOR-Flash */ + MX28_PAD_AUART1_TX__SSP3_CARD_DETECT, + MX28_PAD_AUART2_RX__SSP3_D1, + MX28_PAD_AUART2_TX__SSP3_D2, + MX28_PAD_SSP3_MISO__SSP3_D0, + MX28_PAD_SSP3_MOSI__SSP3_CMD, + MX28_PAD_SSP3_SCK__SSP3_SCK, + MX28_PAD_SSP3_SS0__SSP3_D3, + + /* NOR-Flash CMD */ + MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */ + MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */ + + /* I2C0 Codec */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* I2S Codec */ + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK, + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK, + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK, + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0, + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0, + + /* BT_EN */ + MX28_PAD_SPDIF__GPIO_3_27, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* Uart3 Bluetooth-Interface */ + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + + /* framebuffer */ + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + + /* DUART RS232 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* Backlight */ + MX28_PAD_PWM3__PWM_3, + + /* FEC Ethernet */ + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */ + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__GPIO_4_12, /* PHY reset */ + + /* boot/rescue pins */ + MX28_PAD_ENET0_RXD2__GPIO_4_9, + MX28_PAD_ENET0_TXD2__GPIO_4_11, + + /* HW revision setup pins - by default pullup DISABLED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, + MX28_PAD_ENET0_COL__GPIO_4_14, + MX28_PAD_ENET0_CRS__GPIO_4_15, +}; + +u32 mxs_dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8, + 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322, + 0x02040203, 0x00c8002b, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000102, + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + 0x07400300, 0x07400300, 0x07400300, 0x00000005, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000001, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00030404, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040101, 0x21002103, 0x00061200, + 0x06120612, 0x00000642, 0x00000000, 0x00000004, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0xffffffff +}; + +#ifndef CONFIG_SPL_FRAMEWORK +void board_init_ll(const u32 arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#else +void lowlevel_init(void) +{ + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set EMI drive strength - the HW_PINCTRL_EMI_DS_CTRL */ + writel(EMI_DS_CTRL_CLR, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr); + writel(EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE0_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE1_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE2_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE3_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_DUALPAD_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_CONTROL_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_ADDRESS_SHIFT, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#endif diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index b1f6881275d..e612d9e9ce0 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -5,6 +5,7 @@ * Richard Hu <hakahu@gmail.com> */ +#include <env.h> #include <image.h> #include <init.h> #include <asm/arch/clock.h> diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 1d4f165fd13..9630e7f576b 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -13,6 +13,7 @@ * */ +#include <env.h> #include <fdt_support.h> #include <init.h> #include <log.h> diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 9d24c8cd412..405f393aade 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -10,8 +10,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7981/mt7981_rfb.c b/board/mediatek/mt7981/mt7981_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7981/mt7981_rfb.c +++ b/board/mediatek/mt7981/mt7981_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7986/mt7986_rfb.c b/board/mediatek/mt7986/mt7986_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7986/mt7986_rfb.c +++ b/board/mediatek/mt7986/mt7986_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7987/mt7987_rfb.c b/board/mediatek/mt7987/mt7987_rfb.c index fcb844deed8..c5cb33f06f7 100644 --- a/board/mediatek/mt7987/mt7987_rfb.c +++ b/board/mediatek/mt7987/mt7987_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7988/mt7988_rfb.c b/board/mediatek/mt7988/mt7988_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7988/mt7988_rfb.c +++ b/board/mediatek/mt7988/mt7988_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt8365_evk/mt8365_evk.c b/board/mediatek/mt8365_evk/mt8365_evk.c index 723a50fec00..41a6febf03d 100644 --- a/board/mediatek/mt8365_evk/mt8365_evk.c +++ b/board/mediatek/mt8365_evk/mt8365_evk.c @@ -6,11 +6,6 @@ #include <asm/armv8/mmu.h> -int board_init(void) -{ - return 0; -} - static struct mm_region mt8365_evk_mem_map[] = { { /* DDR */ diff --git a/board/mediatek/mt8516/mt8516_pumpkin.c b/board/mediatek/mt8516/mt8516_pumpkin.c index 930bfec3483..c383d194357 100644 --- a/board/mediatek/mt8516/mt8516_pumpkin.c +++ b/board/mediatek/mt8516/mt8516_pumpkin.c @@ -6,11 +6,6 @@ #include <dm.h> #include <net.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/menlo/mx8menlo/Makefile b/board/menlo/mx8menlo/Makefile index 62939395ba1..c71fa9edfd9 100644 --- a/board/menlo/mx8menlo/Makefile +++ b/board/menlo/mx8menlo/Makefile @@ -16,8 +16,8 @@ endif # Common for all Toradex modules ifeq ($(CONFIG_XPL_BUILD),y) -# Necessary to create built-in.o -obj- := __dummy__.o +# Necessary to create built-in.a +obj- := __dummy__.a else obj-$(CONFIG_TDX_CFG_BLOCK) += ../../toradex/common/tdx-cfg-block.o obj-y += ../../toradex/common/tdx-common.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 4d7d843dfa3..ba622e38ee5 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -9,6 +9,7 @@ #include <init.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,77 @@ static void read_device_serial_number(u8 *response, u8 response_size) response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); } +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char copy[64]; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + /* + * The naming scheme for compatibles doesn't produce anything + * close to this long. + */ + if (len >= 64) + return -EINVAL; + + strncpy(copy, compat, 64); + strtok(copy, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + int board_init(void) { /* For now nothing to do here. */ diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 699e5ca54a7..16dbaa96e8c 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -22,11 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_size_t get_effective_memsize(void) { /* Use bank0 only */ diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 2faa34954eb..0a3c052a019 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -14,11 +14,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int dram_init(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c index 4c957e88992..62007f2f81d 100644 --- a/board/openpiton/riscv64/openpiton-riscv64.c +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -25,8 +25,3 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[i] = boot_devices[i]; } #endif - -int board_init(void) -{ - return 0; -} diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 8126f7356e1..948f9dab626 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -3,8 +3,8 @@ # Author: Teresa Remmet <t.remmet@phytec.de> ifdef CONFIG_XPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 828973a8e28..7f34d71d530 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -94,7 +94,7 @@ int mmc_get_env_dev(void) return 1; }; - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } #endif @@ -121,24 +121,37 @@ enum env_location env_get_location(enum env_operation op, int prio) } #if IS_ENABLED(CONFIG_BOARD_LATE_INIT) -int board_late_init(void) +/** + * Ensure the boot order favors the device we just booted from. + * If boot_targets is still at its default value, move the current + * boot device to the front of the list. Otherwise, leave any customized + * order untouched. + */ +static void boot_targets_setup(void) { u32 boot_device = get_boot_device(); + const char *boot_targets = NULL; + char boot_targets_default[100]; + int ret; switch (boot_device) { case BOOT_DEVICE_MMC1: env_set_ulong("mmcdev", 0); env_set("boot", "mmc"); + boot_targets = "mmc0 mmc1 spi_flash dhcp"; break; case BOOT_DEVICE_MMC2: env_set_ulong("mmcdev", 1); env_set("boot", "mmc"); + boot_targets = "mmc1 mmc0 spi_flash dhcp"; break; case BOOT_DEVICE_SPI: env_set("boot", "spi"); + boot_targets = "spi_flash mmc0 mmc1 dhcp"; break; case BOOT_DEVICE_ETHERNET: env_set("boot", "net"); + boot_targets = "dhcp mmc0 mmc1 spi_flash"; break; case BOOT_DEVICE_UART: env_set("boot", "uart"); @@ -148,26 +161,49 @@ int board_late_init(void) break; }; - if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { - struct phytec_api3_element *block_element; - struct phytec_eeprom_data data; - int ret; - - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); - if (ret || !data.valid) - return 0; - - PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { - switch (block_element->block_type) { - case PHYTEC_API3_BLOCK_MAC: - phytec_blocks_add_mac_to_env(block_element); - break; - default: - debug("%s: Unknown block type %i\n", __func__, - block_element->block_type); - } + if (!boot_targets) + return; + + ret = env_get_default_into("boot_targets", boot_targets_default, sizeof(boot_targets_default)); + if (ret < 0) + boot_targets_default[0] = '\0'; + + if (strcmp(boot_targets_default, env_get("boot_targets"))) { + debug("boot_targets not default, don't change it\n"); + return; + } + + env_set("boot_targets", boot_targets); +} + +static void setup_mac_from_eeprom(void) +{ + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); } } +} + +int board_late_init(void) +{ + boot_targets_setup(); + + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + setup_mac_from_eeprom(); #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) configure_capsule_updates(); diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c index 5f3c27ef0c2..b44ff85972f 100644 --- a/board/phytec/common/phytec_som_detection_blocks.c +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -4,6 +4,7 @@ * Author: Daniel Schultz <d.schultz@phytec.de> */ +#include <env.h> #include <malloc.h> #include <u-boot/crc.h> #include <net.h> diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c index 14b8959c07a..3e1c4102cc1 100644 --- a/board/phytec/phycore_am62ax/phycore-am62ax.c +++ b/board/phytec/phycore_am62ax/phycore-am62ax.c @@ -11,11 +11,6 @@ #include "../common/am6_som_detection.h" -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 40787b0cbcb..797904013dc 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -24,3 +24,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index b199fdaa59b..51da864aa80 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - static u8 phytec_get_am62_ddr_size_default(void) { int ret; diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 5c48e856685..797904013dc 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -10,6 +10,7 @@ fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 +fit_addr_r=0x90000000 fdtfile=CONFIG_DEFAULT_FDT_FILE mmcdev=1 @@ -23,3 +24,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/rm-cfg.yaml b/board/phytec/phycore_am62x/rm-cfg.yaml index e4221f82f92..26d99b03b80 100644 --- a/board/phytec/phycore_am62x/rm-cfg.yaml +++ b/board/phytec/phycore_am62x/rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62 +# Resource management configuration for AM62X # --- @@ -244,7 +244,7 @@ rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 960 + resasg_entries_size: 976 reserved: 0 resasg_entries: - @@ -285,11 +285,23 @@ rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 4 + num_resource: 2 type: 320 host_id: 12 reserved: 0 - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 + - start_resource: 4 num_resource: 4 type: 320 @@ -501,13 +513,13 @@ rm-cfg: reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -543,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 627 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index f14c87f5c72..33c39376ceb 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - static u8 phytec_get_am64_ddr_size_default(void) { int ret; diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index d69dfe75674..36ab16e2f7a 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -9,6 +9,7 @@ fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 +fit_addr_r=0x90000000 fdtfile=CONFIG_DEFAULT_FDT_FILE mmcdev=1 @@ -22,3 +23,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index a7d14e774a0..b3f09154328 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -1,65 +1,15 @@ -#include <env/phytec/rauc.env> - -bootcmd= - mmc dev ${mmcdev}; - if mmc rescan; then - if test ${doraucboot} = 1; then - run raucinit; - fi; - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; -console=ttymxc2,115200 +console=ttymxc2,CONFIG_BAUDRATE emmc_dev=2 -fdt_addr_r=0x48000000 fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 ip_dyn=yes -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcargs= - setenv bootargs console=${console} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw -mmcautodetect=yes -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if run loadfdt; then - if test ${dofitboot} = 1; then - booti ${loadaddr} - ${fdt_addr_r} - else - echo WARN: Cannot load the DT; - fi; - fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV -mmcpart=1 -mmcroot=2 -netargs= - setenv bootargs console=${console} root=/dev/nfs ip=dhcp - nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - run netargs; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; nfsroot=/srv/nfs -update_bootimg= - mmc dev ${mmcdev}; - if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then - setexpr fw_sz ${filesize} / 0x200; - mmc write ${loadaddr} ${update_offset} ${fw_sz}; - fi; -update_filename=flash.bin -update_offset=0x42 diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index 2c12fc65432..9a129a0a4bf 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -1,82 +1,28 @@ -#include <env/phytec/rauc.env> -#include <env/phytec/overlays.env> - bootcmd= if test ${dofastboot} = 1; then fastboot 0; fi; - mmc dev ${mmcdev}; - if mmc rescan; then - run spiprobe; - if test ${doraucboot} = 1; then - run raucinit; - fi; - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; -console=ttymxc0,115200 + bootflow scan -lb; +bootmeths=script efi +boot_targets=mmc2 mmc1 usb ethernet bootenv_addr_r=0x49100000 -fdtoverlay_addr_r=0x49000000 +boot_script_dhcp=boot.scr.uimg +console=ttymxc0,115200 dofastboot=0 -emmc_dev=2 fastboot_raw_partition_all=0 4194304 fastboot_raw_partition_bootloader=64 8128 fdt_addr_r=0x48000000 fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image +fdtoverlay_addr_r=0x49000000 ip_dyn=yes +kernel_addr_r=0x5A080000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 mtdparts=30bb0000.spi:3840k(u-boot),128k(env),128k(env_redund),-(none) mtdids=nor0=30bb0000.spi -spiprobe=true -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -mmcargs= - setenv bootargs ${mcore_clk} console=${console} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw mmcautodetect=yes -mmcboot= - echo Booting from mmc ...; - if test ${no_bootenv} = 0; then - if run mmc_load_bootenv; then - env import -t ${bootenv_addr_r} ${filesize}; - fi; - fi; - run mmcargs; - if run loadfdt; then - run mmc_apply_overlays; - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV -mmcpart=1 -mmcroot=2 -netargs= - setenv bootargs ${mcore_clk} console=${console} root=/dev/nfs ip=dhcp - nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${no_bootenv} = 0; then - if run net_load_bootenv; then - env import -t ${bootenv_addr_r} ${filesize}; - fi; - fi; - ${get_cmd} ${loadaddr} ${image}; - run netargs; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run net_apply_overlays; - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX nfsroot=/srv/nfs -prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted -sd_dev=1 +pxefile_addr_r=0x58600000 +ramdisk_addr_r=0x5E000000 +scriptaddr=0x40000000 diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index a55795e0603..8d2caf8bbef 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -6,10 +6,7 @@ * Copyright (C) 2024 PHYTEC Messtechnik GmbH */ -#include <asm/arch-imx9/ccm_regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch-imx9/imx93_pins.h> -#include <asm/arch/clock.h> #include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env index 3b2f30118e7..7b0a90e6447 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx93/phycore_imx93.env @@ -23,7 +23,7 @@ bootenv_addr_r=0x90500000 fdtfile=CONFIG_DEFAULT_FDT_FILE ip_dyn=yes prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 mmcautodetect=yes diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index a4d2aaac320..7b5d38d438f 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -14,9 +14,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> #include <asm/sections.h> -#include <hang.h> #include <init.h> -#include <log.h> #include <power/pmic.h> #include <power/pca9450.h> #include <spl.h> @@ -25,11 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * Will be part of drivers/power/regulator/pca9450.c - * when pca9451a support is added. - */ -#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5) #define EEPROM_ADDR 0x50 /* diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 01e210fcdd1..9fc63febdac 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -37,11 +37,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index fbbf6789b50..6824454cdf4 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -50,11 +50,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 0ea335e7486..3984ddc4594 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -32,11 +32,6 @@ int dram_init(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 8ca8792fa42..5178ee6929d 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -6,6 +6,7 @@ #include <malloc.h> #include <errno.h> +#include <env.h> #include <asm/io.h> #include <miiphy.h> #include <asm/mach-imx/iomux-v3.h> diff --git a/board/qualcomm/MAINTAINERS b/board/qualcomm/MAINTAINERS new file mode 100644 index 00000000000..3767a2a7949 --- /dev/null +++ b/board/qualcomm/MAINTAINERS @@ -0,0 +1,24 @@ +# This MAINTAINERS file is for folks with an interest in a particular platform +# or board under ARM SNAPDRAGON + +QUALCOMM DRAGONWING QCS615 +M: Aswin Murugan <aswin.murugan@oss.qualcomm.com> +S: Maintained +N: qcs615 + +# RB3 Gen 2 and similar boards +QUALCOMM DRAGONWING QCS6490 +M: Casey Connolly <casey.connolly@linaro.org> +S: Maintained +N: qcs6490 +N: sc7280 + +QUALCOMM DRAGONWING QCS8300 +M: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> +S: Maintained +N: qcs8300 + +QUALCOMM DRAGONWING QCS9100 +M: Varadarajan Narayanan <quic_varada@quicinc.com> +S: Maintained +N: qcs9100 diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config index 913c91757c1..d24094eefdd 100644 --- a/board/qualcomm/qcom-phone.config +++ b/board/qualcomm/qcom-phone.config @@ -1,5 +1,5 @@ # Settings for phones -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/qcom-phone.env" +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/qcom-phone.env" # Hang on panic so the error message can be read CONFIG_PANIC_HANG=y # We use pause in various places to allow text to be read diff --git a/board/raidsonic/ib62x0/MAINTAINERS b/board/raidsonic/ib62x0/MAINTAINERS index 423aa0cf253..2822eb0d29d 100644 --- a/board/raidsonic/ib62x0/MAINTAINERS +++ b/board/raidsonic/ib62x0/MAINTAINERS @@ -1,5 +1,5 @@ IB62X0 BOARD -M: Luka Perkov <luka@openwrt.org> +M: Tony Dinh <mibodhi@gmail.com> S: Maintained F: board/raidsonic/ib62x0/ F: include/configs/ib62x0.h diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 5e51b691178..1849c995aee 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -5,6 +5,7 @@ # # R-Car SoCs +ifndef CONFIG_RZA1 ifndef CONFIG_RZG2L # 32 bit SoCs @@ -45,3 +46,10 @@ endif endif endif +endif + +# RZ/A1 SoCs +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index 69229ea3cb0..bcb03792494 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -36,6 +36,8 @@ int dram_init(void) return ret; } +__weak void renesas_dram_init_banksize(void) { } + int dram_init_banksize(void) { int bank; @@ -58,6 +60,8 @@ int dram_init_banksize(void) break; } + renesas_dram_init_banksize(); + return 0; } diff --git a/board/renesas/common/rcar64-spl.c b/board/renesas/common/rcar64-spl.c index 76f2bde924e..d8f05d2ffbe 100644 --- a/board/renesas/common/rcar64-spl.c +++ b/board/renesas/common/rcar64-spl.c @@ -6,7 +6,7 @@ #include <image.h> #include <spl.h> -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { diff --git a/board/renesas/common/rza1-common.c b/board/renesas/common/rza1-common.c new file mode 100644 index 00000000000..5027319a58a --- /dev/null +++ b/board/renesas/common/rza1-common.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <init.h> +#include <asm/io.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/common/rza1-lowlevel_init.S index b83c4e86867..b83c4e86867 100644 --- a/board/renesas/grpeach/lowlevel_init.S +++ b/board/renesas/common/rza1-lowlevel_init.S diff --git a/board/renesas/genmai/Kconfig b/board/renesas/genmai/Kconfig new file mode 100644 index 00000000000..4e67a9b325a --- /dev/null +++ b/board/renesas/genmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENMAI + +config SYS_BOARD + default "genmai" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "genmai" + +endif diff --git a/board/renesas/genmai/MAINTAINERS b/board/renesas/genmai/MAINTAINERS new file mode 100644 index 00000000000..1f1c2944632 --- /dev/null +++ b/board/renesas/genmai/MAINTAINERS @@ -0,0 +1,5 @@ +GENMAI BOARD +M: Magnus Damm <damm@opensource.se> +S: Maintained +F: arch/arm/dts/r7s72100* +N: genmai diff --git a/board/renesas/genmai/Makefile b/board/renesas/genmai/Makefile new file mode 100644 index 00000000000..73f5e45affd --- /dev/null +++ b/board/renesas/genmai/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Magnus Damm <damm@opensource.se> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := genmai.o diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c new file mode 100644 index 00000000000..8153aed15e3 --- /dev/null +++ b/board/renesas/genmai/genmai.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Magnus Damm <damm@opensource.se> + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> + +#define RZA1_BCR_BASE 0x3FFFC000 +#define CS0BCR (RZA1_BCR_BASE + 0x04) +#define CS0WCR (RZA1_BCR_BASE + 0x28) +#define CS1BCR (RZA1_BCR_BASE + 0x08) +#define CS1WCR (RZA1_BCR_BASE + 0x2c) + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* setup NOR Flash on CS0 and CS1 */ + writel(0x00000b40, CS0WCR); + writel(0x10000c00, CS0BCR); + writel(0x00000b40, CS1WCR); + writel(0x10000c00, CS1BCR); + return 0; +} + +/* + * The Genmai DT will most likely contain memory nodes describing the external + * SDRAM memory connected to CS2 and CS3, however we do not yet have any code + * in U-Boot to setup the memory controller. For now ignore DT and make use of + * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE. + */ + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + gd->ram_size = 10 << 20; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile index 48e185ce3e8..89f8e0e8544 100644 --- a/board/renesas/grpeach/Makefile +++ b/board/renesas/grpeach/Makefile @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a0..3a6393fdce1 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include <cpu_func.h> #include <errno.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ int dram_init_banksize(void) return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c index 78b8cb4ac34..6ea903f2d62 100644 --- a/board/renesas/r2dplus/r2dplus.c +++ b/board/renesas/r2dplus/r2dplus.c @@ -17,11 +17,6 @@ int checkboard(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 0f6d6e7f514..509c5dbb156 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -51,8 +51,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/renesas/sparrowhawk/Kconfig b/board/renesas/sparrowhawk/Kconfig new file mode 100644 index 00000000000..6b7aba348df --- /dev/null +++ b/board/renesas/sparrowhawk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SPARROWHAWK + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "sparrowhawk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "sparrowhawk" + +endif diff --git a/board/renesas/sparrowhawk/MAINTAINERS b/board/renesas/sparrowhawk/MAINTAINERS new file mode 100644 index 00000000000..9f759aefab8 --- /dev/null +++ b/board/renesas/sparrowhawk/MAINTAINERS @@ -0,0 +1,7 @@ +SPARROWHAWK BOARD +M: Marek Vasut <marek.vasut+renesas@mailbox.org> +S: Maintained +F: arch/arm/dts/r8a779g3* +F: board/renesas/sparrowhawk/ +F: configs/r8a779g3_sparrowhawk_defconfig +F: include/configs/sparrowhawk.h diff --git a/board/renesas/sparrowhawk/Makefile b/board/renesas/sparrowhawk/Makefile new file mode 100644 index 00000000000..90da9e02537 --- /dev/null +++ b/board/renesas/sparrowhawk/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/sparrowhawk/Makefile +# +# Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sparrowhawk.o diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c new file mode 100644 index 00000000000..8e72b5424d1 --- /dev/null +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> + */ + +#include <asm/io.h> +#include <compiler.h> +#include <dbsc5.h> +#include <spl.h> + +#if defined(CONFIG_XPL_BUILD) + +static const struct renesas_dbsc5_board_config +renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config = { + /* RENESAS V4H Sparrow Hawk (64Gbit 1rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26157084, 0x12306854 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02431065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x70423856 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264031, 0x40587236 }, + .bdcfg_dm_swap = { 0x07, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x68023745 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +static const struct renesas_dbsc5_board_config +renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config = { + /* RENESAS V4H Sparrow Hawk (64Gbit 2rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26157084, 0x12306854 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x02431065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x70423856 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264031, 0x40587236 }, + .bdcfg_dm_swap = { 0x07, 0x01 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0x06 }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x68023745 }, + .bdcfg_dm_swap = { 0x00, 0x01 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +const struct renesas_dbsc5_board_config * +dbsc5_get_board_data(struct udevice *dev, const u32 modemr0) +{ + /* + * MD[19] is used to discern between 5500 Mbps and 6400 Mbps operation. + * + * Boards with 1 rank of DRAM can operate at 6400 Mbps, those are the + * Sparrow Hawk boards with 8 GiB of DRAM. Boards with 2 ranks of DRAM + * are limited to 5500 Mbps operation, those are the boards with 16 GiB + * of DRAM. + * + * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk + * board variants from each other automatically. + */ + if (modemr0 & BIT(19)) + return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config; + else + return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config; +} + +#endif + +#define RST_MODEMR0 0xe6160000 + +DECLARE_GLOBAL_DATA_PTR; + +void renesas_dram_init_banksize(void) +{ + const u32 modemr0 = readl(RST_MODEMR0); + int bank; + + /* 8 GiB device, do nothing. */ + if (!(modemr0 & BIT(19))) + return; + + /* 16 GiB device, adjust memory map. */ + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (gd->bd->bi_dram[bank].start == 0x480000000ULL) + gd->bd->bi_dram[bank].size = 0x180000000ULL; + else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) + gd->bd->bi_dram[bank].size = 0x200000000ULL; + } +} diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index fbee2c39771..602216854ba 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include <env.h> #include <miiphy.h> #include <asm-generic/gpio.h> #include <asm/arch/imx8mq_pins.h> diff --git a/board/samsung/coreprimevelte/MAINTAINERS b/board/samsung/coreprimevelte/MAINTAINERS index 0902117e8b3..9dccd041ffb 100644 --- a/board/samsung/coreprimevelte/MAINTAINERS +++ b/board/samsung/coreprimevelte/MAINTAINERS @@ -1,5 +1,5 @@ Samsung Galaxy Core Prime VE LTE support -M: Duje Mihanović <duje.mihanovic@skole.hr> +M: Duje Mihanović <duje@dujemihanovic.xyz> S: Maintained T: git git://git.dujemihanovic.xyz/u-boot.git F: board/samsung/coreprimevelte/ diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index 0bef68d2fb2..a6c264d1248 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -4,9 +4,57 @@ * Author: Sam Protsenko <semen.protsenko@linaro.org> */ +#include <efi_loader.h> +#include <env.h> #include <init.h> +#include <mapmem.h> +#include <asm/io.h> #include "fw.h" +/* OTP Controller base address and register offsets */ +#define EXYNOS850_OTP_BASE 0x10000000 +#define OTP_CHIPID0 0x4 +#define OTP_CHIPID1 0x8 + +struct efi_fw_image fw_images[] = { + { + .image_type_id = E850_96_FWBL1_IMAGE_GUID, + .fw_name = u"E850-96-FWBL1", + .image_index = 1, + }, + { + .image_type_id = E850_96_EPBL_IMAGE_GUID, + .fw_name = u"E850-96-EPBL", + .image_index = 2, + }, + { + .image_type_id = E850_96_BL2_IMAGE_GUID, + .fw_name = u"E850-96-BL2", + .image_index = 3, + }, + { + .image_type_id = E850_96_BOOTLOADER_IMAGE_GUID, + .fw_name = u"E850-96-BOOTLOADER", + .image_index = 4, + }, + { + .image_type_id = E850_96_EL3_MON_IMAGE_GUID, + .fw_name = u"E850-96-EL3-MON", + .image_index = 5, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=" + "fwbl1.img raw 0x0 0x18 mmcpart 1;" + "epbl.img raw 0x18 0x98 mmcpart 1;" + "bl2.img raw 0xb0 0x200 mmcpart 1;" + "bootloader.img raw 0x438 0x1000 mmcpart 1;" + "el3_mon.img raw 0x1438 0x200 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + int dram_init(void) { return fdtdec_setup_mem_size_base(); @@ -17,10 +65,43 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -int board_init(void) +/* Read the unique SoC ID from OTP registers */ +static u64 get_chip_id(void) +{ + void __iomem *otp_base; + u64 val; + + otp_base = map_sysmem(EXYNOS850_OTP_BASE, 12); + val = readl(otp_base + OTP_CHIPID0); + val |= (u64)readl(otp_base + OTP_CHIPID1) << 32UL; + unmap_sysmem(otp_base); + + return val; +} + +static void setup_serial(void) +{ + char serial_str[17] = { 0 }; + u64 serial_num; + + if (env_get("serial#")) + return; + + serial_num = get_chip_id(); + snprintf(serial_str, sizeof(serial_str), "%016llx", serial_num); + env_set("serial#", serial_str); +} + +int board_late_init(void) { int err; + setup_serial(); + + /* + * Do this in board_late_init() to make sure MMC is not probed before + * efi_init_early(). + */ err = load_ldfw(); if (err) printf("ERROR: LDFW loading failed (%d)\n", err); diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index 5ac76bcef02..aed7a71046d 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -7,5 +7,49 @@ pxefile_addr_r=0x8c200000 ramdisk_addr_r=0x8c300000 fdtfile=CONFIG_DEFAULT_FDT_FILE +dfu_alt_info= + rawemmc raw 0 0x747c000 mmcpart 1; + esp part 0 1; + rootfs part 0 2; + fwbl1 raw 0x0 0x18 mmcpart 1; + epbl raw 0x18 0x98 mmcpart 1; + bl2 raw 0xb0 0x200 mmcpart 1; + dram_train raw 0x2b0 0x20 mmcpart 1; + ect_test raw 0x2d0 0x64 mmcpart 1; + acpm_test raw 0x334 0x104 mmcpart 1; + bootloader raw 0x438 0x1000 mmcpart 1; + el3_mon raw 0x1438 0x200 mmcpart 1 + partitions=name=esp,start=512K,size=128M,bootable,type=system; partitions+=name=rootfs,size=-,bootable,type=linux + +partitions_android=name=esp,start=512K,size=128M,bootable,type=system; +partitions_android+=name=efs,size=20M,uuid=${uuid_gpt_efs}; +partitions_android+=name=env,size=16K,uuid=${uuid_gpt_env}; +partitions_android+=name=kernel,size=30M,uuid=${uuid_gpt_kernel}; +partitions_android+=name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk}; +partitions_android+=name=dtbo_a,size=1M,uuid=${uuid_gpt_dtbo}; +partitions_android+=name=dtbo_b,size=1M,uuid=${uuid_gpt_dtbo}; +partitions_android+=name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw}; +partitions_android+=name=keystorage,size=8K,uuid=${uuid_gpt_keystorage}; +partitions_android+=name=tzsw,size=1M,uuid=${uuid_gpt_tzsw}; +partitions_android+=name=harx,size=2M,uuid=${uuid_gpt_harx}; +partitions_android+=name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp}; +partitions_android+=name=logo,size=40M,uuid=${uuid_gpt_logo}; +partitions_android+=name=super,size=3600M,uuid=${uuid_gpt_super}; +partitions_android+=name=cache,size=300M,uuid=${uuid_gpt_cache}; +partitions_android+=name=modem,size=100M,uuid=${uuid_gpt_modem}; +partitions_android+=name=boot_a,size=100M,uuid=${uuid_gpt_boot}; +partitions_android+=name=boot_b,size=100M,uuid=${uuid_gpt_boot}; +partitions_android+=name=persist,size=30M,uuid=${uuid_gpt_persist}; +partitions_android+=name=recovery_a,size=40M,uuid=${uuid_gpt_recovery}; +partitions_android+=name=recovery_b,size=40M,uuid=${uuid_gpt_recovery}; +partitions_android+=name=misc,size=40M,uuid=${uuid_gpt_misc}; +partitions_android+=name=mnv,size=20M,uuid=${uuid_gpt_mnv}; +partitions_android+=name=frp,size=512K,uuid=${uuid_gpt_frp}; +partitions_android+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta}; +partitions_android+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta}; +partitions_android+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; +partitions_android+=name=dtb_a,size=1M,uuid=${uuid_gpt_dtb}; +partitions_android+=name=dtb_b,size=1M,uuid=${uuid_gpt_dtb}; +partitions_android+=name=userdata,size=-,uuid=${uuid_gpt_userdata} diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 940f689a601..30c637e322a 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -3,8 +3,8 @@ # Copyright (C) 2011 Samsung Electronics ifdef CONFIG_XPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a hostprogs-y := tools/mkorigenspl always := $(hostprogs-y) diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index b7f9d5a254c..360300a7851 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -3,8 +3,8 @@ # Copyright (C) 2011 Samsung Electronics ifdef CONFIG_XPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a hostprogs-y := tools/mksmdkv310spl always := $(hostprogs-y) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index d97945e58fc..0dc23a27dfc 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -101,12 +101,6 @@ enum env_location env_get_location(enum env_operation op, int prio) int dram_init(void) { - gd->ram_size = CFG_SYS_SDRAM_SIZE; - return 0; -} - -int board_init(void) -{ return 0; } diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index 3b4bd64dd00..9c8c7a6ecdc 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,6 +1,5 @@ CAPRICORN BOARD M: Alexander Sverdlin <alexander.sverdlin@siemens.com> -M: Anatolij Gustschin <agust@denx.de> M: Heiko Schocher <hs@denx.de> M: Walter Schweizer <walter.schweizer@siemens.com> S: Maintained diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c index daf0bb930ec..939ff81797d 100644 --- a/board/siemens/common/board_am335x.c +++ b/board/siemens/common/board_am335x.c @@ -10,6 +10,7 @@ */ #include <command.h> +#include <env.h> #include <serial.h> #include <watchdog.h> #include <asm/arch/clock.h> diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index d827f728a08..c75f4a0d084 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -11,6 +11,7 @@ #include <config.h> #include <bootstage.h> #include <dm.h> +#include <env.h> #include <fdt_support.h> #include <i2c.h> #include <led.h> @@ -366,11 +367,6 @@ static void m2_connector_setup(void) m2_overlay_prepare(); } -int board_init(void) -{ - return 0; -} - int dram_init(void) { struct udevice *sysinfo; diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index 08077a1f9e1..f76e1ae75a1 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -43,8 +43,3 @@ int board_early_init_f(void) { return sram_init(); } - -int board_init(void) -{ - return 0; -} diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c index a8b111477ef..5d2f40f241c 100644 --- a/board/socionext/developerbox/fwu_plat.c +++ b/board/socionext/developerbox/fwu_plat.c @@ -4,6 +4,7 @@ */ #include <efi_loader.h> +#include <env.h> #include <fwu.h> #include <fwu_mdata.h> #include <memalign.h> diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c index eaa47be1739..e6099d35dbf 100644 --- a/board/sophgo/licheerv_nano/board.c +++ b/board/sophgo/licheerv_nano/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c index 2631cdd49e0..ea416621544 100644 --- a/board/spacemit/bananapi-f3/board.c +++ b/board/spacemit/bananapi-f3/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index 8ad593cccdd..f5174720434 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -32,11 +32,6 @@ void enable_caches(void) } #endif -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_USB_DWC3 int g_dnl_board_usb_cable_connected(void) { diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 22d751b44d3..4b0defda1ec 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -45,11 +45,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index db59ebb838e..88c825334a8 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -39,11 +39,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 134d207d95d..7aab7f71d0c 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -39,11 +39,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 35ef9ff9e28..d00f55379c5 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -34,8 +34,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 35ef9ff9e28..d00f55379c5 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -34,8 +34,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h747-disco/Kconfig b/board/st/stm32h747-disco/Kconfig new file mode 100644 index 00000000000..a7b2c09a327 --- /dev/null +++ b/board/st/stm32h747-disco/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STM32H747_DISCO + +config SYS_BOARD + default "stm32h747-disco" + +config SYS_VENDOR + default "st" + +config SYS_SOC + default "stm32h7" + +config SYS_CONFIG_NAME + default "stm32h747-disco" + +endif diff --git a/board/st/stm32h747-disco/MAINTAINERS b/board/st/stm32h747-disco/MAINTAINERS new file mode 100644 index 00000000000..d48649f773f --- /dev/null +++ b/board/st/stm32h747-disco/MAINTAINERS @@ -0,0 +1,7 @@ +STM32H747 DISCOVERY BOARD +M: Dario Binacchi <dario.binacchi@amarulasolutions.com> +S: Maintained +F: board/st/stm32h747-disco +F: include/configs/stm32h747-disco.h +F: configs/stm32h747-disco_defconfig +F: arch/arm/dts/stm32h747* diff --git a/board/st/stm32h747-disco/Makefile b/board/st/stm32h747-disco/Makefile new file mode 100644 index 00000000000..e11f052cc88 --- /dev/null +++ b/board/st/stm32h747-disco/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com> +# + +obj-y := stm32h747-disco.o diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c new file mode 100644 index 00000000000..645685a64f1 --- /dev/null +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * stm32h747i-disco support + * + * Copyright (C) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include <dm.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + if (fdtdec_setup_mem_size_base() != 0) + ret = -EINVAL; + + return ret; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 75aa4d139fb..31c85c6816e 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -44,8 +44,3 @@ int board_late_init(void) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 15fb9e4b062..ab7af69d472 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -828,7 +828,7 @@ const char *env_ext4_get_dev_part(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 2547f2e4bb7..a72056e12d6 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -183,7 +183,7 @@ int mmc_get_boot(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 84799879e85..e00b54f4535 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -137,6 +137,11 @@ M: Chris Morgan <macromorgan@hotmail.com> S: Maintained F: configs/anbernic_rg35xx_h700_defconfig +AVAOTA A1 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/avaota-a1_defconfig + BANANAPI M1 PLUS M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained @@ -296,6 +301,11 @@ M: Adam Sampson <ats@offog.org> S: Maintained F: configs/Linksprite_pcDuino3_Nano_defconfig +LIONTRON H-A133L BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/liontron-h-a133l_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained @@ -526,6 +536,11 @@ M: Quentin Schulz <quentin.schulz@free-electrons.com> S: Maintained F: configs/parrot_r16_defconfig +RADXA CUBIE A5E BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/radxa-cubie-a5e_defconfig + SINLINX SINA31s BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained @@ -586,6 +601,11 @@ M: Andre Przywara <andre.przywara@arm.com> S: Maintained F: configs/x96_mate_defconfig +X96Q PRO+ TV BOX +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/x96q_pro_plus_defconfig + YONES TOPTECH BD1078 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained @@ -596,6 +616,11 @@ M: Peter Korsgaard <peter@korsgaard.com> S: Maintained F: configs/Yones_Toptech_BS1078_V2_defconfig +YUZUKIHD CHAMELEON BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/yuzukihd-chameleon_defconfig + ZEROPI BOARD M: Yu-Tung Chang <mtwget@gmail.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ac9cefc6eac..2929bc17f08 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -114,10 +114,14 @@ void i2c_init_board(void) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); -#elif CONFIG_MACH_SUN50I_H616 +#elif defined(CONFIG_MACH_SUN50I_H616) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); +#elif CONFIG_MACH_SUN55I_A523 + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_GPL_R_TWI); #else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); @@ -435,7 +439,8 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } -#elif defined(CONFIG_MACH_SUN50I_H616) +#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \ + defined(CONFIG_MACH_SUN55I_A523) /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) @@ -516,7 +521,7 @@ int board_mmc_init(struct bd_info *bis) return 0; } -#ifdef CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX int mmc_get_env_dev(void) { switch (sunxi_get_boot_device()) { @@ -525,7 +530,7 @@ int mmc_get_env_dev(void) case BOOT_DEVICE_MMC2: return 1; default: - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } } #endif diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index d0f739c624a..cf6b7fcbd95 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 NXP Semiconductors */ +#include <env.h> #include <init.h> #include <net.h> #include <asm/arch/clock.h> diff --git a/board/terasic/de1-soc/MAINTAINERS b/board/terasic/de1-soc/MAINTAINERS index 1e726e93603..6e7eee9c3e3 100644 --- a/board/terasic/de1-soc/MAINTAINERS +++ b/board/terasic/de1-soc/MAINTAINERS @@ -1,5 +1,5 @@ DE1-SoC BOARD -M: Anatolij Gustschin <agust@denx.de> +M: Anatolij Gustschin <ag.dev.uboot@gmail.com> S: Maintained F: board/terasic/de1-soc/ F: include/configs/socfpga_de1_soc.h diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c index 25dfa387c36..d75fa6f3eff 100644 --- a/board/thead/th1520_lpi4a/spl.c +++ b/board/thead/th1520_lpi4a/spl.c @@ -39,6 +39,9 @@ void board_init_f(ulong dummy) if (ret) panic("failed to bind CPU: %d\n", ret); + riscv_cpu_setup(); + th1520_kick_secondary_cores(); + spl_dram_init(); icache_enable(); diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 960de15398f..d2d87c304f6 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -274,6 +274,47 @@ static struct module_pin_mux uart3_icev2_pin_mux[] = { {-1}, }; +#if (IS_ENABLED(CONFIG_AM335X_LCD)) +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0))}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0))}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0))}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0))}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0))}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0))}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0))}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0))}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0))}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0))}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0))}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0))}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0))}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0))}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0))}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0))}, /* LCD-Data(15) */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD-Data(23) */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD-CLK */ + {-1}, +}; +#endif + +#if (IS_ENABLED(CONFIG_PWM_TI_ECAP)) +static struct module_pin_mux ecap_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, /* ecap0_in_pwm0_out */ + {-1}, +}; +#endif + #if defined(CONFIG_NOR_BOOT) void enable_norboot_pin_mux(void) { @@ -389,6 +430,13 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } + #if IS_ENABLED(CONFIG_AM335X_LCD) + configure_module_pin_mux(lcd_pin_mux); + #endif + + #if IS_ENABLED(CONFIG_PWM_TI_ECAP) + configure_module_pin_mux(ecap_pin_mux); + #endif } else if (board_is_idk()) { /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); @@ -408,6 +456,9 @@ void enable_board_pin_mux(void) if (subtype_id == 'L') configure_module_pin_mux(spi0_pin_mux); + } else if (board_is_bbge()) { + /* Beaglebone Green Eco pinmux */ + configure_module_pin_mux(rgmii1_pin_mux); } else { /* Beaglebone LT pinmux */ configure_module_pin_mux(mii1_pin_mux); diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 3351544c5b3..a445f983255 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -16,11 +16,6 @@ #include "../common/fdt_ops.h" -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 379d1a5b316..2e85363cf5f 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 3051a0a27a1..d7b07a0d34d 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -74,11 +74,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 35fd30dbceb..8e89b3b15df 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -54,11 +54,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { diff --git a/board/ti/am64x/rm-cfg.yaml b/board/ti/am64x/rm-cfg.yaml index 88b37b5972c..1cc4cd34430 100644 --- a/board/ti/am64x/rm-cfg.yaml +++ b/board/ti/am64x/rm-cfg.yaml @@ -1,1215 +1,1215 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM64x +# Resource management configuration for AM64X # --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 12 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 2 - host_id: 30 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 3 - host_id: 36 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 4 - host_id: 38 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 5 - host_id: 41 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 6 - host_id: 43 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 7 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 8 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 9 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 10 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 11 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 12 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 13 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 14 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 15 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 16 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 17 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 18 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 19 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 20 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 21 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 22 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 23 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 24 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 25 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 26 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 27 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 28 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 29 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 - - # 30 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - 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reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 2124 + host_id: 41 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 2124 + host_id: 43 + reserved: 0 + - + start_resource: 28 + num_resource: 4 + type: 2124 + host_id: 128 + reserved: 0 diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 6658794a137..5c45a33eac9 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -45,11 +45,6 @@ enum { DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index ca1aa80f2f0..b057f3b2269 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -10,6 +10,8 @@ /* TI EEPROM MAGIC Header identifier */ #include <linux/bitops.h> +#include <linux/if_ether.h> + #define TI_EEPROM_HEADER_MAGIC 0xEE3355AA #define TI_DEAD_EEPROM_MAGIC 0xADEAD12C @@ -18,7 +20,7 @@ #define TI_EEPROM_HDR_SERIAL_LEN 12 #define TI_EEPROM_HDR_CONFIG_LEN 32 #define TI_EEPROM_HDR_NO_OF_MAC_ADDR 3 -#define TI_EEPROM_HDR_ETH_ALEN 6 +#define TI_EEPROM_HDR_ETH_ALEN ETH_ALEN /** * struct ti_am_eeprom - This structure holds data read in from the diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index 6cc92bf0d8d..292fc72fd58 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -36,5 +36,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J7200_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw +rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif diff --git a/board/ti/j7200/rm-cfg.yaml b/board/ti/j7200/rm-cfg.yaml index f83184bbfc0..9da0ea91ada 100644 --- a/board/ti/j7200/rm-cfg.yaml +++ b/board/ti/j7200/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J7200 # @@ -7,1779 +7,1779 @@ --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 3 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 2 - host_id: 5 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 3 - host_id: 12 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 4 - host_id: 13 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 5 - host_id: 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type: 15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 0525f6e6f97..1527eaf1e16 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -8,6 +8,7 @@ */ #include <efi_loader.h> +#include <env.h> #include <generic-phy.h> #include <image.h> #include <net.h> @@ -65,11 +66,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index e5b4225b3ce..ead7fbdb212 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -38,5 +38,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J721E_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw +rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml index 0163e3e1717..88ec2026db0 100644 --- a/board/ti/j721e/rm-cfg.yaml +++ b/board/ti/j721e/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721E # @@ -7,2751 +7,2751 @@ --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 3 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 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reserved: 0 + - + start_resource: 38 + num_resource: 1 + type: 15117 + host_id: 26 + reserved: 0 + - + start_resource: 39 + num_resource: 1 + type: 15117 + host_id: 28 + reserved: 0 + - + start_resource: 40 + num_resource: 2 + type: 15117 + host_id: 35 + reserved: 0 + - + start_resource: 42 + num_resource: 1 + type: 15117 + host_id: 37 + reserved: 0 + - + start_resource: 43 + num_resource: 3 + type: 15117 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 12 + num_resource: 20 + type: 15168 + host_id: 3 + reserved: 0 + - + start_resource: 36 + num_resource: 28 + type: 15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 8c8f8e2a265..5d3b84607d8 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -28,11 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index a6b22550809..abd4faea6ee 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -24,6 +24,6 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw #endif rd_spec=- -rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw +rproc_fw_binaries= 1 /lib/firmware/j721s2-mcu-r5f0_1-fw 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index f085ecfd37e..d2b94913c12 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -15,11 +15,6 @@ #include <asm/arch/k3-ddr.h> #include "../common/fdt_ops.h" -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index e32beb84795..62730adf216 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J722S # @@ -16,224 +16,224 @@ rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 3 host_id: 22 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 4 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 5 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 6 host_id: 38 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml index 4a2af0ebcaf..7b2e58a89b3 100644 --- a/board/ti/j722s/tifs-rm-cfg.yaml +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J722S # @@ -16,224 +16,224 @@ tifs-rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - #1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #2 + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #3 + - # 3 host_id: 22 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #4 + - # 4 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #5 + - # 5 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #6 + - # 6 host_id: 38 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #7 + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #8 + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #9 + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #10 + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #11 + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #12 + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #13 + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #14 + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #15 + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #16 + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #17 + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #18 + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #19 + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #20 + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #21 + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #22 + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #23 + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #24 + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #25 + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #26 + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #27 + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #28 + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #29 + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #30 + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #31 + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #32 + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 @@ -248,746 +248,746 @@ tifs-rm-cfg: reserved: 0 resasg_entries: - - start_resource: 0 - num_resource: 16 - type: 1677 - host_id: 12 - reserved: 0 - - - start_resource: 16 - num_resource: 6 - type: 1677 - host_id: 20 - reserved: 0 - - - start_resource: 16 - num_resource: 6 - type: 1677 - host_id: 36 - reserved: 0 - - - start_resource: 22 - num_resource: 2 - type: 1677 - host_id: 30 - reserved: 0 - - - start_resource: 24 - num_resource: 4 - type: 1677 - host_id: 22 - reserved: 0 - - - start_resource: 28 - num_resource: 4 - type: 1677 - host_id: 38 - reserved: 0 - - - start_resource: 57 - num_resource: 16 - type: 1678 - host_id: 12 - reserved: 0 - - - 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host_id: 38 + reserved: 0 + - + start_resource: 1536 + num_resource: 8 + type: 12823 + host_id: 128 + reserved: 0 + - + start_resource: 2048 + num_resource: 8 + type: 12824 + host_id: 128 + reserved: 0 + - + start_resource: 2560 + num_resource: 8 + type: 12825 + host_id: 128 + reserved: 0 + - + start_resource: 3072 + num_resource: 32 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 32 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 32 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index c8d01bf0ca8..6335676081a 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 9e1741be424..2f1a5f549d1 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -21,7 +21,7 @@ bootdir=/boot rd_spec=- #if CONFIG_TARGET_J784S4_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw +rproc_fw_binaries= 1 /lib/firmware/j784s4-mcu-r5f0_1-fw 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw #elif CONFIG_TARGET_J742S2_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw +rproc_fw_binaries= 1 /lib/firmware/j742s2-mcu-r5f0_1-fw 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw #endif diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 4557ed1f1f2..168840764a1 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -36,7 +36,7 @@ #define VCC_USBO1 TEGRA_GPIO(T, 5) #define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4) -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) { diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index 698b05bc5ad..8721276bed8 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -11,6 +11,7 @@ #include <command.h> #include <console.h> #include <fuse.h> +#include <linux/string.h> static int mfgr_fuse(void) { diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 02e8f8eb1fe..2c785da41ea 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; static int pci_reset_status; #endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index 698b05bc5ad..8721276bed8 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -11,6 +11,7 @@ #include <command.h> #include <console.h> #include <fuse.h> +#include <linux/string.h> static int mfgr_fuse(void) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 7de29e3abfb..69a8a18d3a7 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -4,6 +4,7 @@ */ #include <cpu_func.h> +#include <env.h> #include <init.h> #include <net.h> #include <asm/arch/clock.h> diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index d432fd2b843..05c3377a60b 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #define PMU_SUPPLYENE_SYSINEN (1<<5) #define PMU_SUPPLYENE_EXITSLREQ (1<<1) -int arch_misc_init(void) +int misc_init_r(void) { /* Disable PMIC sleep mode on low supply voltage */ struct udevice *dev; diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 342673ac506..1b091ea1694 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -18,7 +18,7 @@ #include "pinmux-config-colibri_t30.h" #include "../common/tdx-common.h" -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile index 7e3905445a5..24496a7c997 100644 --- a/board/toradex/common/Makefile +++ b/board/toradex/common/Makefile @@ -3,8 +3,8 @@ # Common for all Toradex modules ifeq ($(CONFIG_XPL_BUILD),y) -# Necessary to create built-in.o -obj- := __dummy__.o +# Necessary to create built-in.a +obj- := __dummy__.a else obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o obj-y += tdx-common.o diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 6c1cea77c8c..869656eee7a 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -166,6 +166,24 @@ const struct toradex_som toradex_modules[] = { { APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, { SMARC_IMX95_HEXA_8GB_WB_IT, "SMARC iMX95 Hexa 8GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, { SMARC_IMX8MPQ_4GB_WB_IT, "SMARC iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { AQUILA_IMX95_HEXA_16GB_WB_IT, "Aquila iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(AQUILA_IMX95) }, + { VERDIN_AM62PQ_2G_WIFI_BT_IT, "Verdin AM62P Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62P_A53) }, + { SMARC_IMX95_HEXA_8GB_IT, "SMARC iMX95 Hexa 8GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_4GB_WB_IT, "SMARC iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_4GB_ET, "SMARC iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_2GB_WB_IT, "SMARC iMX95 Hexa 2GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_2GB_ET, "SMARC iMX95 Hexa 2GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX8MPQ_4GB_IT, "SMARC iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQ_2GB_WB_IT, "SMARC iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQ_2GB_IT, "SMARC iMX8M Plus Quad 2GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQL_1GB_WB_ET, "SMARC iMX8M Plus Quadlite 1GB WB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQL_1GB_ET, "SMARC iMX8M Plus Quadlite 1GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { AQUILA_AM69O_32GB_IT, "Aquila AM69 Octa 32GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_16GB_WB_IT, "Aquila AM69 Octa 16GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_16GB_IT, "Aquila AM69 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_8GB_WB_IT, "Aquila AM69 Octa 8GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_8GB_IT, "Aquila AM69 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX8MMQ_WB_IT_64G, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index f4dd853306b..d002b969bdf 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -124,6 +124,24 @@ enum { APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, /* 95 */ SMARC_IMX95_HEXA_8GB_WB_IT, SMARC_IMX8MPQ_4GB_WB_IT, + AQUILA_IMX95_HEXA_16GB_WB_IT, + VERDIN_AM62PQ_2G_WIFI_BT_IT, /* 99 */ + SMARC_IMX95_HEXA_8GB_IT = 201, + SMARC_IMX95_HEXA_4GB_WB_IT, + SMARC_IMX95_HEXA_4GB_ET, + SMARC_IMX95_HEXA_2GB_WB_IT, + SMARC_IMX95_HEXA_2GB_ET, /* 205 */ + SMARC_IMX8MPQ_4GB_IT, + SMARC_IMX8MPQ_2GB_WB_IT, + SMARC_IMX8MPQ_2GB_IT, + SMARC_IMX8MPQL_1GB_WB_ET, + SMARC_IMX8MPQL_1GB_ET, /* 210 */ + AQUILA_AM69O_32GB_IT, + AQUILA_AM69O_16GB_WB_IT, + AQUILA_AM69O_16GB_IT, + AQUILA_AM69O_8GB_WB_IT, + AQUILA_AM69O_8GB_IT, /* 215 */ + VERDIN_IMX8MMQ_WB_IT_64G, }; enum { diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c index bbe371516cc..915b413b15e 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.c +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c @@ -10,11 +10,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int board_phys_sdram_size(phys_size_t *size) { if (!size) diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 7b2eecbf659..069aa6c7909 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -15,17 +15,13 @@ #include <init.h> #include <k3-ddrss.h> #include <spl.h> +#include <linux/sizes.h> #include <asm/arch/k3-ddr.h> #include "../common/tdx-cfg-block.h" DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); @@ -94,7 +90,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig new file mode 100644 index 00000000000..7bf0133b669 --- /dev/null +++ b/board/toradex/verdin-am62p/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +choice + prompt "Toradex Verdin AM62P based boards" + optional + +config TARGET_VERDIN_AM62P_A53 + bool "Toradex Verdin AM62P running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + +config TARGET_VERDIN_AM62P_R5 + bool "Toradex Verdin AM62P running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_VERDIN_AM62P_A53 + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_EXTRA + default y + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif + +if TARGET_VERDIN_AM62P_R5 + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +endif diff --git a/board/toradex/verdin-am62p/MAINTAINERS b/board/toradex/verdin-am62p/MAINTAINERS new file mode 100644 index 00000000000..97094e0e756 --- /dev/null +++ b/board/toradex/verdin-am62p/MAINTAINERS @@ -0,0 +1,17 @@ +Verdin AM62P +M: Francesco Dolcini <francesco.dolcini@toradex.com> +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p +S: Maintained +F: arch/arm/dts/k3-am62p-verdin-dev.dtsi +F: arch/arm/dts/k3-am62p-verdin-wifi.dtsi +F: arch/arm/dts/k3-am62p-verdin.dtsi +F: arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi +F: arch/arm/dts/k3-am62p5-verdin-r5.dts +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts +F: board/toradex/verdin-am62p/ +F: configs/verdin-am62p_a53_defconfig +F: configs/verdin-am62p_r5_defconfig +F: doc/board/toradex/verdin-am62p.rst +F: include/configs/verdin-am62p.h diff --git a/board/toradex/verdin-am62p/Makefile b/board/toradex/verdin-am62p/Makefile new file mode 100644 index 00000000000..2eef6f4f592 --- /dev/null +++ b/board/toradex/verdin-am62p/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +obj-y += verdin-am62p.o diff --git a/board/toradex/verdin-am62p/board-cfg.yaml b/board/toradex/verdin-am62p/board-cfg.yaml new file mode 100644 index 00000000000..d539011aff9 --- /dev/null +++ b/board/toradex/verdin-am62p/board-cfg.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62Px SoCs +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/toradex/verdin-am62p/pm-cfg.yaml b/board/toradex/verdin-am62p/pm-cfg.yaml new file mode 100644 index 00000000000..3ff27ce702c --- /dev/null +++ b/board/toradex/verdin-am62p/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62Px +# +# +--- +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/toradex/verdin-am62p/rm-cfg.yaml b/board/toradex/verdin-am62p/rm-cfg.yaml new file mode 100644 index 00000000000..73da85eeade --- /dev/null +++ b/board/toradex/verdin-am62p/rm-cfg.yaml @@ -0,0 +1,1083 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 1112 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 16 + type: 192 + host_id: 12 + reserved: 0 + - + start_resource: 34 + num_resource: 2 + type: 192 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 320 + host_id: 12 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 + - + start_resource: 4 + num_resource: 4 + type: 320 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 26 + type: 384 + host_id: 128 + reserved: 0 + - + start_resource: 50176 + num_resource: 164 + type: 1666 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 1667 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 1676 + host_id: 12 + reserved: 0 + - + start_resource: 2 + num_resource: 1 + type: 1676 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 1 + type: 1676 + host_id: 36 + reserved: 0 + - + start_resource: 3 + num_resource: 1 + type: 1676 + host_id: 30 + reserved: 0 + - + start_resource: 4 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 22 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 28 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 30 + num_resource: 2 + type: 1677 + host_id: 128 + reserved: 0 + - + start_resource: 57 + num_resource: 18 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 75 + num_resource: 5 + type: 1678 + host_id: 35 + reserved: 0 + - + start_resource: 75 + num_resource: 5 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 80 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - + start_resource: 32 + num_resource: 12 + type: 1679 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 36 + reserved: 0 + - + start_resource: 50 + num_resource: 2 + type: 1679 + host_id: 30 + reserved: 0 + - + start_resource: 52 + num_resource: 5 + type: 1679 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 1695 + host_id: 12 + reserved: 0 + - + start_resource: 2 + num_resource: 1 + type: 1695 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 1 + type: 1695 + host_id: 36 + reserved: 0 + - + start_resource: 3 + num_resource: 1 + type: 1695 + host_id: 30 + reserved: 0 + - + start_resource: 4 + num_resource: 18 + type: 1696 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 6 + type: 1696 + host_id: 35 + reserved: 0 + - + start_resource: 22 + num_resource: 6 + type: 1696 + host_id: 36 + reserved: 0 + - + start_resource: 28 + num_resource: 2 + type: 1696 + host_id: 30 + reserved: 0 + - + start_resource: 30 + num_resource: 2 + type: 1696 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1697 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 5 + type: 1697 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 5 + type: 1697 + host_id: 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type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 12288 + num_resource: 128 + type: 12813 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/sec-cfg.yaml b/board/toradex/verdin-am62p/sec-cfg.yaml new file mode 100644 index 00000000000..bfd6a4e5dbd --- /dev/null +++ b/board/toradex/verdin-am62p/sec-cfg.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62Px +# +--- +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - # 1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - # 1 + host_id: 0 + supervisor_host_id: 0 + - # 2 + host_id: 0 + supervisor_host_id: 0 + - # 3 + host_id: 0 + supervisor_host_id: 0 + - # 4 + host_id: 0 + supervisor_host_id: 0 + - # 5 + host_id: 0 + supervisor_host_id: 0 + - # 6 + host_id: 0 + supervisor_host_id: 0 + - # 7 + host_id: 0 + supervisor_host_id: 0 + - # 8 + host_id: 0 + supervisor_host_id: 0 + - # 9 + host_id: 0 + supervisor_host_id: 0 + - # 10 + host_id: 0 + supervisor_host_id: 0 + - # 11 + host_id: 0 + supervisor_host_id: 0 + - # 12 + host_id: 0 + supervisor_host_id: 0 + - # 13 + host_id: 0 + supervisor_host_id: 0 + - # 14 + host_id: 0 + supervisor_host_id: 0 + - # 15 + host_id: 0 + supervisor_host_id: 0 + - # 16 + host_id: 0 + supervisor_host_id: 0 + - # 17 + host_id: 0 + supervisor_host_id: 0 + - # 18 + host_id: 0 + supervisor_host_id: 0 + - # 19 + host_id: 0 + supervisor_host_id: 0 + - # 20 + host_id: 0 + supervisor_host_id: 0 + - # 21 + host_id: 0 + supervisor_host_id: 0 + - # 22 + host_id: 0 + supervisor_host_id: 0 + - # 23 + host_id: 0 + supervisor_host_id: 0 + - # 24 + host_id: 0 + supervisor_host_id: 0 + - # 25 + host_id: 0 + supervisor_host_id: 0 + - # 26 + host_id: 0 + supervisor_host_id: 0 + - # 27 + host_id: 0 + supervisor_host_id: 0 + - # 28 + host_id: 0 + supervisor_host_id: 0 + - # 29 + host_id: 0 + supervisor_host_id: 0 + - # 30 + host_id: 0 + supervisor_host_id: 0 + - # 31 + host_id: 0 + supervisor_host_id: 0 + - # 32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - # 1 + host_id: 0 + host_perms: 0 + - # 2 + host_id: 0 + host_perms: 0 + - # 3 + host_id: 0 + host_perms: 0 + - # 4 + host_id: 0 + host_perms: 0 + - # 5 + host_id: 0 + host_perms: 0 + - # 6 + host_id: 0 + host_perms: 0 + - # 7 + host_id: 0 + host_perms: 0 + - # 8 + host_id: 0 + host_perms: 0 + - # 9 + host_id: 0 + host_perms: 0 + - # 10 + host_id: 0 + host_perms: 0 + - # 11 + host_id: 0 + host_perms: 0 + - # 12 + host_id: 0 + host_perms: 0 + - # 13 + host_id: 0 + host_perms: 0 + - # 14 + host_id: 0 + host_perms: 0 + - # 15 + host_id: 0 + host_perms: 0 + - # 16 + host_id: 0 + host_perms: 0 + - # 17 + host_id: 0 + host_perms: 0 + - # 18 + host_id: 0 + host_perms: 0 + - # 19 + host_id: 0 + host_perms: 0 + - # 20 + host_id: 0 + host_perms: 0 + - # 21 + host_id: 0 + host_perms: 0 + - # 22 + host_id: 0 + host_perms: 0 + - # 23 + host_id: 0 + host_perms: 0 + - # 24 + host_id: 0 + host_perms: 0 + - # 25 + host_id: 0 + host_perms: 0 + - # 26 + host_id: 0 + host_perms: 0 + - # 27 + host_id: 0 + host_perms: 0 + - # 28 + host_id: 0 + host_perms: 0 + - # 29 + host_id: 0 + host_perms: 0 + - # 30 + host_id: 0 + host_perms: 0 + - # 31 + host_id: 0 + host_perms: 0 + - # 32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..80269748057 --- /dev/null +++ b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml @@ -0,0 +1,927 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 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b/board/toradex/verdin-am62p/verdin-am62p.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Board specific initialization for Verdin AM62P SoM + * + * Copyright 2025 Toradex - https://www.toradex.com/ + * + */ + +#include <config.h> +#include <asm/arch/hardware.h> +#include <asm/arch/k3-common-fdt.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm/uclass.h> +#include <env.h> +#include <fdt_support.h> +#include <init.h> +#include <k3-ddrss.h> +#include <spl.h> +#include <linux/sizes.h> + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; +static u8 hw_cfg; + +static void read_hw_cfg(void) +{ + struct gpio_desc gpio_hw_cfg; + static const int gpios[] = { 58, 61, 62 }; /* HW_CFG0, HW_CFG1, HW_CFG2 */ + char gpio_name[20]; + int i; + + printf("HW CFG: "); + + for (i = 0; i < ARRAY_SIZE(gpios); i++) { + snprintf(gpio_name, sizeof(gpio_name), "gpio@600000_%d", gpios[i]); + + if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { + printf("Lookup error: GPIO %d\n", gpios[i]); + continue; + } + + if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { + printf("GPIO request error: %d\n", gpios[i]); + continue; + } + + if (dm_gpio_get_value(&gpio_hw_cfg) == 1) + hw_cfg |= BIT(i); + + dm_gpio_free(NULL, &gpio_hw_cfg); + } + + printf("0x%02x\n", hw_cfg); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); + + if (gd->ram_size < SZ_1G) + puts("## WARNING: Less than 1GB RAM detected\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + /* Use the detected RAM size, we only support 1 bank right now. */ + gd->bd->bi_dram[0].size = gd->ram_size; + + return ret; +} + +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP_EXTENDED) +void ft_board_setup_ex(void *blob, struct bd_info *bd) +{ + fdt_fixup_thermal_critical_trips_k3(blob, 105); +} +#endif + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62PQ_2G_WIFI_BT_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (!env_variant || strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4) + +void spl_board_init(void) +{ + u32 val; + + /* + * We use the 32k FOUT from the Epson RX8130CE RTC chip, + * configure LFXOSC accordingly, see AM62P datasheet, + * Table 6-23, LFXOSC Modes of Operation. + */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL; + val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL; + writel(val, MCU_CTRL_LFXOSC_CTRL); + /* Make sure to mux up to take the SoC 32k from the LFOSC input */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + read_hw_cfg(); +} diff --git a/board/toradex/verdin-am62p/verdin-am62p.env b/board/toradex/verdin-am62p/verdin-am62p.env new file mode 100644 index 00000000000..f8b7363dcf5 --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.env @@ -0,0 +1,41 @@ +#define CFG_RAMDISK_ADDR_R 0x90300000 +#define CFG_SCRIPTADDR 0x90280000 + +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyS2 +fdt_addr_r=0x90200000 +fdt_board=dev +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80200000 +kernel_comp_size=0x08000000 +ramdisk_addr_r=CFG_RAMDISK_ADDR_R +scriptaddr=CFG_SCRIPTADDR + +dfu_alt_info_ram= + tispl.bin ram 0x80080000 0x200000; + u-boot.img ram 0x81000000 0x400000; + loadaddr ram CONFIG_SYS_LOAD_ADDR 0x80000; + scriptaddr ram CFG_SCRIPTADDR 0x80000; + ramdisk_addr_r ram CFG_RAMDISK_ADDR_R 0x8000000 + +update_tiboot3= + askenv confirm Did you load tiboot3.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; + fi + +update_tispl= + askenv confirm Did you load tispl.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; + fi + +update_uboot= + askenv confirm Did you load u-boot.img (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; + fi diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 1020078afea..3c2d0ba1dd4 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -53,7 +53,9 @@ void spl_dram_init(void) void spl_board_init(void) { +#if IS_ENABLED(CONFIG_ARCH_MISC_INIT) arch_misc_init(); +#endif } #ifdef CONFIG_SPL_LOAD_FIT diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 9359e0ac6bf..b4402415845 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -3,7 +3,7 @@ * Copyright 2020-2021 Toradex */ -#include <config.h> +#include <env.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> @@ -85,7 +85,8 @@ static void select_dt_from_module_version(void) is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET); + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WB_IT_64G); } switch (get_pcb_revision()) { @@ -100,7 +101,7 @@ static void select_dt_from_module_version(void) break; } - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e57ec3b6896..34ce25512e8 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -90,7 +90,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 80c84e64241..14aa93c527b 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -44,11 +44,6 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed; -int board_init(void) -{ - return 0; -} - int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 216a022aa15..174752f6b07 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -33,11 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define GUEST_VIRTIO_MMIO_BASE 0x2000000 #define GUEST_VIRTIO_MMIO_SIZE 0x100000 -int board_init(void) -{ - return 0; -} - /* * Use fdt provided by Xen: according to * https://www.kernel.org/doc/Documentation/arm64/booting.txt diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 8ffe7429901..ceb58da6d3c 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -712,3 +712,34 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } #endif + +#if IS_ENABLED(CONFIG_BOARD_RNG_SEED) +/* Use hardware rng to seed Linux random. */ +__weak int board_rng_seed(struct abuf *buf) +{ + struct udevice *dev; + ulong len = 64; + u64 *data; + + if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { + printf("No RNG device\n"); + return -ENODEV; + } + + data = malloc(len); + if (!data) { + printf("Out of memory\n"); + return -ENOMEM; + } + + if (dm_rng_read(dev, data, len)) { + printf("Reading RNG failed\n"); + free(data); + return -EIO; + } + + abuf_init_set(buf, data, len); + + return 0; +} +#endif diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index c478f7e04a0..ed3fe16af7b 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -7,11 +7,6 @@ #include <spl.h> -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_SPL u32 spl_boot_device(void) { diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 735ef3cd1be..789b945d462 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -14,6 +14,7 @@ #include <efi_loader.h> #include <init.h> #include <log.h> +#include <mtd.h> #include <net.h> #include <sata.h> #include <ahci.h> diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c index 0c62b0013c4..c34a7c5ecae 100644 --- a/board/xilinx/zynqmp_r5/board.c +++ b/board/xilinx/zynqmp_r5/board.c @@ -7,11 +7,6 @@ #include <init.h> #include <linux/errno.h> -int board_init(void) -{ - return 0; -} - int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); |