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-rw-r--r--board/atmel/sama5d4_xplained/sama5d4_xplained.c11
-rw-r--r--board/atmel/sama5d4ek/sama5d4ek.c11
-rw-r--r--board/freescale/ls1021aqds/MAINTAINERS1
-rw-r--r--board/freescale/ls1021aqds/Makefile1
-rw-r--r--board/freescale/ls1021aqds/dcu.c92
-rw-r--r--board/freescale/ls1021aqds/ddr.c17
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c86
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds_qixis.h2
-rw-r--r--board/freescale/ls1021atwr/MAINTAINERS1
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c25
-rw-r--r--board/iomega/iconnect/kwbimage.cfg4
-rw-r--r--board/raidsonic/ib62x0/kwbimage.cfg22
-rw-r--r--board/siemens/corvus/board.c12
-rw-r--r--board/siemens/taurus/taurus.c24
-rw-r--r--board/xilinx/zynq/board.c14
15 files changed, 276 insertions, 47 deletions
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 2758c5cbcd6..1c5b92c8b58 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -10,6 +10,7 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
@@ -294,6 +295,9 @@ int board_init(void)
#ifdef CONFIG_CMD_USB
sama5d4_xplained_usb_hw_init();
#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ at91_udp_hw_init();
+#endif
return 0;
}
@@ -313,5 +317,12 @@ int board_eth_init(bd_t *bis)
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+ usb_eth_initialize(bis);
+#endif
+#endif
+
return rc;
}
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index d3039c021af..d8ff6489574 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -10,6 +10,7 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
@@ -293,6 +294,9 @@ int board_init(void)
#ifdef CONFIG_CMD_USB
sama5d4ek_usb_hw_init();
#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ at91_udp_hw_init();
+#endif
return 0;
}
@@ -312,5 +316,12 @@ int board_eth_init(bd_t *bis)
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+ usb_eth_initialize(bis);
+#endif
+#endif
+
return rc;
}
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 638833dc412..661526b9933 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -6,6 +6,7 @@ F: include/configs/ls1021aqds.h
F: configs/ls1021aqds_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F: configs/ls1021aqds_nor_lpuart_defconfig
F: configs/ls1021aqds_sdcard_defconfig
F: configs/ls1021aqds_qspi_defconfig
F: configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index 3b6903c83bc..ab0234412cb 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -7,3 +7,4 @@
obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
new file mode 100644
index 00000000000..90f5bc04452
--- /dev/null
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include "div64.h"
+#include "../common/diu_ch7301.h"
+#include "ls1021aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd->bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 1000000000);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+ int ret;
+ u8 ch;
+
+ /* Mux I2C3+I2C4 as HSYNC+VSYNC */
+ ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+ 1, &ch, 1);
+ if (ret) {
+ printf("Error: failed to read I2C @%02x\n",
+ CONFIG_SYS_I2C_QIXIS_ADDR);
+ return ret;
+ }
+ ch &= 0x1F;
+ ch |= 0xA0;
+ ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+ 1, &ch, 1);
+ if (ret) {
+ printf("Error: failed to write I2C @%02x\n",
+ CONFIG_SYS_I2C_QIXIS_ADDR);
+ return ret;
+ }
+
+ if (strncmp(port, "hdmi", 4) == 0) {
+ unsigned long pixval;
+
+ name = "HDMI";
+
+ pixval = 1000000000 / dcu_fb_videomode->pixclock;
+ pixval *= 1000;
+
+ i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+ select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+ diu_set_dvi_encoder(pixval);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ } else {
+ return 0;
+ }
+
+ printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index a539ff97913..6435bf9ad18 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
}
#endif
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -159,6 +171,11 @@ phys_size_t initdram(int board_type)
#else
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 152da2d3e89..20eade46514 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -20,6 +20,7 @@
#include <fsl_sec.h>
#include <spl.h>
+#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#ifdef CONFIG_U_QE
@@ -48,6 +49,12 @@ enum {
MUX_TYPE_SD_PC_SG_SG,
};
+enum {
+ GE0_CLK125,
+ GE2_CLK125,
+ GE1_CLK125,
+};
+
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
@@ -177,7 +184,6 @@ int board_early_init_f(void)
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
@@ -188,6 +194,24 @@ int board_early_init_f(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+#ifdef CONFIG_FSL_DCU_FB
+ out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
@@ -195,6 +219,11 @@ int board_early_init_f(void)
* allow barrier transaction to DDR again */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
return 0;
}
@@ -228,6 +257,11 @@ void board_init_f(ulong dummy)
get_clocks();
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
@@ -241,6 +275,32 @@ void board_init_f(ulong dummy)
}
#endif
+void config_etseccm_source(int etsec_gtx_125_mux)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ switch (etsec_gtx_125_mux) {
+ case GE0_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
+ debug("etseccm set to GE0_CLK125\n");
+ break;
+
+ case GE2_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+ debug("etseccm set to GE2_CLK125\n");
+ break;
+
+ case GE1_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
+ debug("etseccm set to GE1_CLK125\n");
+ break;
+
+ default:
+ printf("Error! trying to set etseccm to invalid value\n");
+ break;
+ }
+}
+
int config_board_mux(int ctrl_type)
{
u8 reg12, reg14;
@@ -250,6 +310,7 @@ int config_board_mux(int ctrl_type)
switch (ctrl_type) {
case MUX_TYPE_CAN:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
break;
case MUX_TYPE_IIC2:
@@ -259,6 +320,7 @@ int config_board_mux(int ctrl_type)
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
break;
case MUX_TYPE_SAI:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
break;
case MUX_TYPE_SDHC:
@@ -471,13 +533,6 @@ int board_init(void)
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -500,6 +555,21 @@ int board_init(void)
return 0;
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
index 09b3be2f9c2..8e482eb0b07 100644
--- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h
+++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
@@ -32,4 +32,6 @@
#define QIXIS_SRDS1CLK_100 0x0
+#define QIXIS_DCU_BRDCFG5 0x55
+
#endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index 91767065faa..e9f6f0a973a 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -5,5 +5,6 @@ F: board/freescale/ls1021atwr/
F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F: configs/ls1021atwr_nor_lpuart_defconfig
F: configs/ls1021atwr_sdcard_defconfig
F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 027b67e6d58..bc8b00686c7 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -263,6 +263,7 @@ int config_serdes_mux(void)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -281,6 +282,20 @@ int board_early_init_f(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
return 0;
}
@@ -405,16 +420,6 @@ struct smmu_stream_id dev_stream_id[] = {
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#ifndef CONFIG_QSPI_BOOT
diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
index 3c63a03d3f4..f4260fa5043 100644
--- a/board/iomega/iconnect/kwbimage.cfg
+++ b/board/iomega/iconnect/kwbimage.cfg
@@ -20,7 +20,7 @@ NAND_PAGE_SIZE 0x0800
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xffd100e0 0x1b1b1b9b
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xffd01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
# bit23-14: 0x0,
@@ -87,7 +87,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode
# bit6-4: 0x4, CL=5
# bit7: 0x0, TestMode=0 normal
# bit8: 0x0, DLL reset=0 normal
-# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit11-9: 0x6, auto-precharge write recovery
# bit12: 0x0, PD must be zero
# bit31-13: 0x0, required
diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
index 596071f9b35..ec00c15af3d 100644
--- a/board/raidsonic/ib62x0/kwbimage.cfg
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -11,7 +11,7 @@
#
# Boot Media configurations
-BOOT_FROM nand # change from nand to uart if building UART image
+BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
@@ -21,12 +21,12 @@ NAND_PAGE_SIZE 0x0800
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xffd100e0 0x1b1b1b9b
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xffd01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
# bit23-14: 0x0,
-# bit24: 0x1, enable exit self refresh mode on DDR access
-# bit25: 0x1, required
+# bit24: 0x1, enable exit self refresh mode on DDR access
+# bit25: 0x1, required
# bit29-26: 0x0,
# bit31-30: 0x1,
@@ -64,10 +64,10 @@ DATA 0xffd01410 0x0000000c # DDR Address Control
# bit3-2: 11, Cs0size (1Gb)
# bit5-4: 00, Cs1width (x8)
# bit7-6: 11, Cs1size (1Gb)
-# bit9-8: 00, Cs2width (nonexistent
-# bit11-10: 00, Cs2size (nonexistent
-# bit13-12: 00, Cs3width (nonexistent
-# bit15-14: 00, Cs3size (nonexistent
+# bit9-8: 00, Cs2width (nonexistent)
+# bit11-10: 00, Cs2size (nonexistent)
+# bit13-12: 00, Cs3width (nonexistent)
+# bit15-14: 00, Cs3size (nonexistent)
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
@@ -88,7 +88,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode
# bit6-4: 0x4, CL=5
# bit7: 0x0, TestMode=0 normal
# bit8: 0x0, DLL reset=0 normal
-# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit11-9: 0x6, auto-precharge write recovery
# bit12: 0x0, PD must be zero
# bit31-13: 0x0, required
@@ -148,8 +148,8 @@ DATA 0xffd0149c 0x0000e803 # CPU ODT Control
DATA 0xffd01480 0x00000001 # DDR Initialization Control
# bit0: 0x1, enable DDR init upon this register write
-DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
-DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
+DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
# End of Header extension
DATA 0x0 0x0
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 0a11540cca0..f3f6dae459a 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -43,13 +43,13 @@ static void corvus_nand_hw_init(void)
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
&smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
@@ -62,9 +62,11 @@ static void corvus_nand_hw_init(void)
&smc->cs[3].mode);
at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
}
#if defined(CONFIG_SPL_BUILD)
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index b8ff4781102..013dac2e2fb 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -68,6 +68,7 @@ static void taurus_nand_hw_init(void)
#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>
+#include <spi_flash.h>
void matrix_init(void)
{
@@ -81,23 +82,28 @@ void matrix_init(void)
void at91_spl_board_init(void)
{
taurus_nand_hw_init();
+ at91_spi0_hw_init(TAURUS_SPI_MASK);
/* Configure recovery button PINs */
at91_set_gpio_input(AT91_PIN_PA31, 1);
/* check if button is pressed */
if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
- u32 boot_device;
+ struct spi_flash *flash;
debug("Recovery button pressed\n");
- boot_device = spl_boot_device();
- switch (boot_device) {
-#ifdef CONFIG_SPL_NAND_SUPPORT
- case BOOT_DEVICE_NAND:
- nand_init();
- spl_nand_erase_one(0, 0);
- break;
-#endif
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
+ 0,
+ CONFIG_SF_DEFAULT_SPEED,
+ SPI_MODE_3);
+ if (!flash) {
+ puts("no flash\n");
+ } else {
+ puts("erase spi flash sector 0\n");
+ spi_flash_erase(flash, 0,
+ CONFIG_SYS_NAND_U_BOOT_SIZE);
}
}
}
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 3a2198f8e83..738c31c6ee1 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -91,6 +91,14 @@ int board_late_init(void)
return 0;
}
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board:\tXilinx Zynq\n");
+ return 0;
+}
+#endif
+
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
@@ -115,11 +123,13 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
- CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
+ CONFIG_ZYNQ_GEM_PHY_ADDR0,
+ CONFIG_ZYNQ_GEM_EMIO0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
- CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
+ CONFIG_ZYNQ_GEM_PHY_ADDR1,
+ CONFIG_ZYNQ_GEM_EMIO1);
# endif
#endif
return ret;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 08:55:01 +0000