diff options
Diffstat (limited to 'board')
113 files changed, 3266 insertions, 7665 deletions
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index 78d0edc66d8..a62bf9f1896 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -13,10 +13,11 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +#define MII_MARVELL_PHY_PAGE 22 + #define MV88E1116_LED_FCTRL_REG 10 #define MV88E1116_CPRSP_CR3_REG 21 #define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5) @@ -31,15 +32,44 @@ void mv_phy_88e1116_init(const char *name, u16 phyaddr) * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); if (miiphy_reset(name, phyaddr) == 0) printf("88E1116 Initialized on %s\n", name); } + +void mv_phy_88e1318_init(const char *name, u16 phyaddr) +{ + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* + * Set control mode 4 for LED[0]. + */ + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); + miiphy_read(name, phyaddr, 16, ®); + reg |= 0xf; + miiphy_write(name, phyaddr, 16, reg); + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); + + if (miiphy_reset(name, phyaddr) == 0) + printf("88E1318 Initialized on %s\n", name); +} #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h index 2edd5abbcd0..85e433c9316 100644 --- a/board/LaCie/common/common.h +++ b/board/LaCie/common/common.h @@ -12,6 +12,7 @@ #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) void mv_phy_88e1116_init(const char *name, u16 phyaddr); +void mv_phy_88e1318_init(const char *name, u16 phyaddr); #endif #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) int lacie_read_mac_address(uchar *mac); diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg new file mode 100644 index 00000000000..d008eb0ab0b --- /dev/null +++ b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x34143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000DDDD # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 68e8a770c79..101a80a70ab 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -107,7 +107,11 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { +#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) + mv_phy_88e1318_init("egiga0", 0); +#else mv_phy_88e1116_init("egiga0", 8); +#endif } #endif diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 3e7f406ffb1..1327c62a75a 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -32,6 +32,9 @@ #include <common.h> #include <command.h> +#include <serial.h> +#include <linux/compiler.h> + #include "../include/memory.h" #include "serial.h" @@ -48,9 +51,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_MPSC - - -int serial_init (void) +static int marvell_serial_init(void) { #if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) int clock_divisor = 230400 / gd->baudrate; @@ -68,7 +69,7 @@ int serial_init (void) return (0); } -void serial_putc (const char c) +static void marvell_serial_putc(const char c) { if (c == '\n') mpsc_putchar ('\r'); @@ -76,24 +77,24 @@ void serial_putc (const char c) mpsc_putchar (c); } -int serial_getc (void) +static int marvell_serial_getc(void) { return mpsc_getchar (); } -int serial_tstc (void) +static int marvell_serial_tstc(void) { return mpsc_test_char (); } -void serial_setbrg (void) +static void marvell_serial_setbrg(void) { galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } #else /* ! CONFIG_MPSC */ -int serial_init (void) +static int marvell_serial_init(void) { int clock_divisor = 230400 / gd->baudrate; @@ -106,7 +107,7 @@ int serial_init (void) return (0); } -void serial_putc (const char c) +static void marvell_serial_putc(const char c) { if (c == '\n') NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); @@ -114,17 +115,17 @@ void serial_putc (const char c) NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } -int serial_getc (void) +static int marvell_serial_getc(void) { return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } -int serial_tstc (void) +static int marvell_serial_tstc(void) { return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } -void serial_setbrg (void) +static void marvell_serial_setbrg(void) { int clock_divisor = 230400 / gd->baudrate; @@ -138,13 +139,34 @@ void serial_setbrg (void) #endif /* CONFIG_MPSC */ -void serial_puts (const char *s) +static void marvell_serial_puts(const char *s) { while (*s) { serial_putc (*s++); } } +static struct serial_device marvell_serial_drv = { + .name = "marvell_serial", + .start = marvell_serial_init, + .stop = NULL, + .setbrg = marvell_serial_setbrg, + .putc = marvell_serial_putc, + .puts = marvell_serial_puts, + .getc = marvell_serial_getc, + .tstc = marvell_serial_tstc, +}; + +void marvell_serial_initialize(void) +{ + serial_register(&marvell_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &marvell_serial_drv; +} + #if defined(CONFIG_CMD_KGDB) void kgdb_serial_init (void) { diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S index f04b36bafd0..cf9c225e6dd 100644 --- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S +++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S @@ -330,7 +330,7 @@ init_dbsc3_ctrl_533: DBKIND_A: .long 0xFE800020 DBKIND_D: .long 0x00000005 DBCONF_A: .long 0xFE800024 -DBCONF_D: .long 0x0D020901 +DBCONF_D: .long 0x0D020A01 DBTR0_A: .long 0xFE800040 DBTR0_D_533:.long 0x00000004 diff --git a/board/tqc/tqm85xx/Makefile b/board/altera/socfpga_cyclone5/Makefile index 0a5501fda0e..43bbc3785f4 100644 --- a/board/tqc/tqm85xx/Makefile +++ b/board/altera/socfpga_cyclone5/Makefile @@ -1,6 +1,7 @@ # # (C) Copyright 2001-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> # # See file CREDITS for list of people who contributed to this # project. @@ -25,21 +26,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS-y += $(BOARD).o -COBJS-y += sdram.o -COBJS-y += law.o -COBJS-y += tlb.o +COBJS := socfpga_cyclone5.o -COBJS-$(CONFIG_NAND) += nand.o - -COBJS := $(COBJS-y) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file mode 100644 index 00000000000..7725be12f4e --- /dev/null +++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Platform\n"); + return 0; +} + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +/* + * DesignWare Ethernet initialization + */ +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c deleted file mode 100644 index dbcb34b8f01..00000000000 --- a/board/amirix/ap1000/ap1000.c +++ /dev/null @@ -1,704 +0,0 @@ -/* - * amirix.c: ppcboot platform support for AMIRIX board - * - * Copyright 2002 Mind NV - * Copyright 2003 AMIRIX Systems Inc. - * - * http://www.mind.be/ - * http://www.amirix.com/ - * - * Author : Peter De Schrijver (p2@mind.be) - * Frank Smith (smith@amirix.com) - * - * Derived from : Other platform support files in this tree, ml2 - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/processor.h> - -#include "powerspan.h" -#include "ap1000.h" - -int board_pre_init (void) -{ - return 0; -} - -/** serial number and platform display at startup */ -int checkboard (void) -{ - char buf[64]; - int l = getenv_f("serial#", buf, sizeof(buf)); - - /* After a loadace command, the SystemAce control register is left in a wonky state. */ - /* this code did not work in board_pre_init */ - unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; - unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; - unsigned int device = (*revision_reg_ptr & AP1xx_TARGET_MASK); - - p[SYSACE_CTRLREG0] = 0x0; - - /* add platform and device to banner */ - switch (device) { - case AP1xx_AP107_TARGET: - puts (AP1xx_AP107_TARGET_STR); - break; - case AP1xx_AP120_TARGET: - puts (AP1xx_AP120_TARGET_STR); - break; - case AP1xx_AP130_TARGET: - puts (AP1xx_AP130_TARGET_STR); - break; - case AP1xx_AP1070_TARGET: - puts (AP1xx_AP1070_TARGET_STR); - break; - case AP1xx_AP1100_TARGET: - puts (AP1xx_AP1100_TARGET_STR); - break; - default: - puts (AP1xx_UNKNOWN_STR); - break; - } - puts (AP1xx_TARGET_STR); - puts (" with "); - - switch (get_platform ()) { - case AP100_BASELINE_PLATFORM: - case AP1000_BASELINE_PLATFORM: - puts (AP1xx_BASELINE_PLATFORM_STR); - break; - case AP1xx_QUADGE_PLATFORM: - puts (AP1xx_QUADGE_PLATFORM_STR); - break; - case AP1xx_MGT_REF_PLATFORM: - puts (AP1xx_MGT_REF_PLATFORM_STR); - break; - case AP1xx_STANDARD_PLATFORM: - puts (AP1xx_STANDARD_PLATFORM_STR); - break; - case AP1xx_DUAL_PLATFORM: - puts (AP1xx_DUAL_PLATFORM_STR); - break; - case AP1xx_BASE_SRAM_PLATFORM: - puts (AP1xx_BASE_SRAM_PLATFORM_STR); - break; - case AP1xx_PCI_PCB_TESTPLATFORM: - case AP1000_PCI_PCB_TESTPLATFORM: - puts (AP1xx_PCI_PCB_TESTPLATFORM_STR); - break; - case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM: - puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR); - break; - case AP1xx_SFP_MEZZ_TESTPLATFORM: - puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR); - break; - default: - puts (AP1xx_UNKNOWN_STR); - break; - } - - if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) { - puts (AP1xx_TESTPLATFORM_STR); - } else { - puts (AP1xx_PLATFORM_STR); - } - - putc ('\n'); - - puts ("Serial#: "); - - if (l < 0) { - printf ("### No HW ID - assuming AMIRIX"); - } else { - int i; - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') { - buf[i] = '\0'; - break; - } - } - - puts(buf); - } - - putc ('\n'); - - return (0); -} - - -phys_size_t initdram (int board_type) -{ - char buf[64]; - int i = getenv_f("dramsize", buf, sizeof(buf)); - - if (i > 0) { - char *s = buf; - if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { - s += 2; - } - return (long int)simple_strtoul (s, NULL, 16); - } else { - /* give all 64 MB */ - return 64 * 1024 * 1024; - } -} - -unsigned int get_platform (void) -{ - unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; - - return (*revision_reg_ptr & AP1xx_PLATFORM_MASK); -} - -#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */ -/* - This function loads FPGA configurations from the SystemACE CompactFlash -*/ -int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; - int cfg; - - if ((p[SYSACE_STATREG0] & 0x10) == 0) { - p[SYSACE_CTRLREG0] = 0x80; - printf ("\nNo CompactFlash Detected\n\n"); - p[SYSACE_CTRLREG0] = 0x00; - return 1; - } - - /* reset configuration controller: | 0x80 */ - /* select cpflash & ~0x40 */ - /* cfg start | 0x20 */ - /* wait for cfgstart & ~0x10 */ - /* force cfgmode: | 0x08 */ - /* do no force cfgaddr: & ~0x04 */ - /* clear mpulock: & ~0x02 */ - /* do not force lock request & ~0x01 */ - - p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08; - p[SYSACE_CTRLREG1] = 0x00; - - /* force config address if arg2 exists */ - if (argc == 2) { - cfg = simple_strtoul (argv[1], NULL, 10); - - if (cfg > 7) { - printf ("\nInvalid Configuration\n\n"); - p[SYSACE_CTRLREG0] = 0x00; - return 1; - } - /* Set config address */ - p[SYSACE_CTRLREG1] = (cfg << 5); - /* force cfgaddr */ - p[SYSACE_CTRLREG0] |= 0x04; - - } else { - cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5; - } - - /* release configuration controller */ - printf ("\nLoading V2PRO with config %d...\n", cfg); - p[SYSACE_CTRLREG0] &= ~0x80; - - - while ((p[SYSACE_STATREG1] & 0x01) == 0) { - - if (p[SYSACE_ERRREG0] & 0x80) { - /* attempting to load an invalid configuration makes the cpflash */ - /* appear to be removed. Reset here to avoid that problem */ - p[SYSACE_CTRLREG0] = 0x80; - printf ("\nConfiguration %d Read Error\n\n", cfg); - p[SYSACE_CTRLREG0] = 0x00; - return 1; - } - } - - p[SYSACE_CTRLREG0] |= 0x20; - - return 0; -} -#endif - -/** Console command to display and set the software reconfigure byte - * <pre> - * swconfig - display the current value of the software reconfigure byte - * swconfig [#] - change the software reconfigure byte to # - * </pre> - * @param *cmdtp [IN] as passed by run_command (ignored) - * @param flag [IN] as passed by run_command (ignored) - * @param argc [IN] as passed by run_command if 1, display, if 2 change - * @param *argv[] [IN] contains the parameters to use - * @return - * <pre> - * 0 if passed - * -1 if failed - * </pre> - */ -int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned char *sector_buffer = NULL; - unsigned char input_char; - int write_result; - unsigned int input_uint; - - /* display value if no argument */ - if (argc < 2) { - printf ("Software configuration byte is currently: 0x%02x\n", - *((unsigned char *) (SW_BYTE_SECTOR_ADDR + - SW_BYTE_SECTOR_OFFSET))); - return 0; - } else if (argc > 3) { - printf ("Too many arguments\n"); - return -1; - } - - /* if 3 arguments, 3rd argument is the address to use */ - if (argc == 3) { - input_uint = simple_strtoul (argv[1], NULL, 16); - sector_buffer = (unsigned char *) input_uint; - } else { - sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR; - } - - input_char = simple_strtoul (argv[1], NULL, 0); - if ((input_char & ~SW_BYTE_MASK) != 0) { - printf ("Input of 0x%02x will be masked to 0x%02x\n", - input_char, (input_char & SW_BYTE_MASK)); - input_char = input_char & SW_BYTE_MASK; - } - - memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR, - SW_BYTE_SECTOR_SIZE); - sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char; - - - printf ("Erasing Flash..."); - if (flash_sect_erase - (SW_BYTE_SECTOR_ADDR, - (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) { - return -1; - } - - printf ("Writing to Flash... "); - write_result = - flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR, - SW_BYTE_SECTOR_SIZE); - if (write_result != 0) { - flash_perror (write_result); - return -1; - } else { - printf ("done\n"); - printf ("Software configuration byte is now: 0x%02x\n", - *((unsigned char *) (SW_BYTE_SECTOR_ADDR + - SW_BYTE_SECTOR_OFFSET))); - } - - return 0; -} - -#define ONE_SECOND 1000000 - -int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - int pause_time; - unsigned int delay_time; - int break_loop = 0; - - /* display value if no argument */ - if (argc < 2) { - pause_time = 1; - } - - else if (argc > 2) { - printf ("Too many arguments\n"); - return -1; - } else { - pause_time = simple_strtoul (argv[1], NULL, 0); - } - - printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time); - delay_time = pause_time * ONE_SECOND; - while (break_loop == 0) { - udelay (delay_time); - if (serial_tstc () != 0) { - break_loop = 1; - /* eat user key presses */ - while (serial_tstc () != 0) { - serial_getc (); - } - } - } - - return 0; -} - -int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n", - *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))); - udelay (1000); - *((unsigned char *) AP1000_CPLD_BASE) = 1; - - return 0; -} - -#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125) -#define TEMP_BUSY_BIT 0x80 -#define TEMP_LHIGH_BIT 0x40 -#define TEMP_LLOW_BIT 0x20 -#define TEMP_EHIGH_BIT 0x10 -#define TEMP_ELOW_BIT 0x08 -#define TEMP_OPEN_BIT 0x04 -#define TEMP_ETHERM_BIT 0x02 -#define TEMP_LTHERM_BIT 0x01 - -int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - char cmd; - int ret_val = 0; - unsigned char temp_byte; - int temp; - int temp_low; - int low; - int low_low; - int high; - int high_low; - int therm; - unsigned char user_data[4] = { 0 }; - int user_data_count = 0; - int ii; - - if (argc > 1) { - cmd = argv[1][0]; - } else { - cmd = 's'; /* default to status */ - } - - user_data_count = argc - 2; - for (ii = 0; ii < user_data_count; ii++) { - user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0); - } - switch (cmd) { - case 's': - if (I2CAccess - (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Status : 0x%02x ", temp_byte); - if (temp_byte & TEMP_BUSY_BIT) - printf ("BUSY "); - - if (temp_byte & TEMP_LHIGH_BIT) - printf ("LHIGH "); - - if (temp_byte & TEMP_LLOW_BIT) - printf ("LLOW "); - - if (temp_byte & TEMP_EHIGH_BIT) - printf ("EHIGH "); - - if (temp_byte & TEMP_ELOW_BIT) - printf ("ELOW "); - - if (temp_byte & TEMP_OPEN_BIT) - printf ("OPEN "); - - if (temp_byte & TEMP_ETHERM_BIT) - printf ("ETHERM "); - - if (temp_byte & TEMP_LTHERM_BIT) - printf ("LTHERM"); - - printf ("\n"); - - if (I2CAccess - (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Config : 0x%02x ", temp_byte); - - if (I2CAccess - (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - printf ("\n"); - goto fail; - } - printf ("Conversion: 0x%02x\n", temp_byte); - if (I2CAccess - (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Cons Alert: 0x%02x ", temp_byte); - - if (I2CAccess - (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - printf ("\n"); - goto fail; - } - printf ("Therm Hyst: %d\n", temp_byte); - - if (I2CAccess - (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - temp = temp_byte; - if (I2CAccess - (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - low = temp_byte; - if (I2CAccess - (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - high = temp_byte; - if (I2CAccess - (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - therm = temp_byte; - printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm); - - if (I2CAccess - (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - temp = temp_byte; - if (I2CAccess - (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - temp_low = temp_byte; - if (I2CAccess - (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - low = temp_byte; - if (I2CAccess - (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - low_low = temp_byte; - if (I2CAccess - (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - high = temp_byte; - if (I2CAccess - (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - high_low = temp_byte; - if (I2CAccess - (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - therm = temp_byte; - if (I2CAccess - (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte); - break; - case 'l': /* alter local limits : low, high, therm */ - if (argc < 3) { - goto usage; - } - - /* low */ - if (I2CAccess - (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[0], I2C_WRITE) != 0) { - goto fail; - } - - if (user_data_count > 1) { - /* high */ - if (I2CAccess - (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[1], I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 2) { - /* therm */ - if (I2CAccess - (0x20, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[2], - I2C_WRITE) != 0) { - goto fail; - } - } - break; - case 'e': /* alter external limits: low, high, therm, offset */ - if (argc < 3) { - goto usage; - } - - /* low */ - if (I2CAccess - (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[0], I2C_WRITE) != 0) { - goto fail; - } - - if (user_data_count > 1) { - /* high */ - if (I2CAccess - (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[1], I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 2) { - /* therm */ - if (I2CAccess - (0x19, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[2], - I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 3) { - /* offset */ - if (I2CAccess - (0x11, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[3], - I2C_WRITE) != 0) { - goto fail; - } - } - break; - case 'c': /* alter config settings: config, conv, cons alert, therm hyst */ - if (argc < 3) { - goto usage; - } - - /* config */ - if (I2CAccess - (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[0], I2C_WRITE) != 0) { - goto fail; - } - - if (user_data_count > 1) { - /* conversion */ - if (I2CAccess - (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[1], I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 2) { - /* cons alert */ - if (I2CAccess - (0x22, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[2], - I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 3) { - /* therm hyst */ - if (I2CAccess - (0x21, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[3], - I2C_WRITE) != 0) { - goto fail; - } - } - break; - default: - goto usage; - } - - goto done; -fail: - printf ("Access to sensor failed\n"); - ret_val = -1; - goto done; -usage: - printf ("Usage:\n%s\n", cmdtp->help); - -done: - return ret_val; -} - -U_BOOT_CMD (temp, 6, 0, do_temp_sensor, - "interact with the temperature sensor", - "temp [s]\n" - " - Show status.\n" - "temp l LOW [HIGH] [THERM]\n" - " - Set local limits.\n" - "temp e LOW [HIGH] [THERM] [OFFSET]\n" - " - Set external limits.\n" - "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n" - " - Set config options.\n" - "\n" - "All values can be decimal or hex (hex preceded with 0x).\n" - "Only whole numbers are supported for external limits."); - -#if 0 -U_BOOT_CMD (loadace, 2, 0, do_loadace, - "load fpga configuration from System ACE compact flash", - "N\n" - " - Load configuration N (0-7) from System ACE compact flash\n" - "loadace\n" " - loads default configuration"); -#endif - -U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte, - "display or modify the software configuration byte", - "N [ADDRESS]\n" - " - set software configuration byte to N, optionally use ADDRESS as\n" - " location of buffer for flash copy\n" - "swconfig\n" " - display software configuration byte"); - -U_BOOT_CMD (pause, 2, 0, do_pause, - "sleep processor until any key is pressed with poll time of N seconds", - "N\n" - " - sleep processor until any key is pressed with poll time of N seconds\n" - "pause\n" - " - sleep processor until any key is pressed with poll time of 1 second"); - -U_BOOT_CMD (swrecon, 1, 0, do_swreconfig, - "trigger a board reconfigure to the software selected configuration", - "\n" - " - trigger a board reconfigure to the software selected configuration"); - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h deleted file mode 100644 index d294816d26c..00000000000 --- a/board/amirix/ap1000/ap1000.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally - * - * Author : James MacAulay - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#ifndef __AP1000_H -#define __AP1000_H - -/* - * Revision Register stuff - */ -#define AP1xx_FPGA_REV_ADDR 0x29000000 - -#define AP1xx_PLATFORM_MASK 0xFF000000 -#define AP100_BASELINE_PLATFORM 0x01000000 -#define AP1xx_QUADGE_PLATFORM 0x02000000 -#define AP1xx_MGT_REF_PLATFORM 0x03000000 -#define AP1xx_STANDARD_PLATFORM 0x04000000 -#define AP1xx_DUAL_PLATFORM 0x05000000 -#define AP1xx_BASE_SRAM_PLATFORM 0x06000000 - -#define AP1000_BASELINE_PLATFORM 0x21000000 - -#define AP1xx_TESTPLATFORM_MASK 0xC0000000 -#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000 -#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000 -#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000 - -#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000 - -#define AP1xx_TARGET_MASK 0x00FF0000 -#define AP1xx_AP107_TARGET 0x00010000 -#define AP1xx_AP120_TARGET 0x00020000 -#define AP1xx_AP130_TARGET 0x00030000 -#define AP1xx_AP1070_TARGET 0x00040000 -#define AP1xx_AP1100_TARGET 0x00050000 - -#define AP1xx_UNKNOWN_STR "Unknown" - -#define AP1xx_PLATFORM_STR " Platform" -#define AP1xx_BASELINE_PLATFORM_STR "Baseline" -#define AP1xx_QUADGE_PLATFORM_STR "Quad GE" -#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference" -#define AP1xx_STANDARD_PLATFORM_STR "Standard" -#define AP1xx_DUAL_PLATFORM_STR "Dual" -#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM" - -#define AP1xx_TESTPLATFORM_STR " Test Platform" -#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base" -#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine" -#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine" - -#define AP1xx_TARGET_STR " Board" -#define AP1xx_AP107_TARGET_STR "AP107" -#define AP1xx_AP120_TARGET_STR "AP120" -#define AP1xx_AP130_TARGET_STR "AP130" - -#define AP1xx_AP1070_TARGET_STR "AP1070" -#define AP1xx_AP1100_TARGET_STR "AP1100" - -/* - * Flash Stuff - */ -#define AP1xx_PROGRAM_FLASH_INDEX 0 -#define AP1xx_CONFIG_FLASH_INDEX 1 - -/* - * System Ace Stuff - */ -#define AP1000_SYSACE_REGBASE 0x28000000 - -#define SYSACE_STATREG0 0x04 /* 7:0 */ -#define SYSACE_STATREG1 0x05 /* 15:8 */ -#define SYSACE_STATREG2 0x06 /* 23:16 */ -#define SYSACE_STATREG3 0x07 /* 31:24 */ - -#define SYSACE_ERRREG0 0x08 /* 7:0 */ -#define SYSACE_ERRREG1 0x09 /* 15:8 */ -#define SYSACE_ERRREG2 0x0a /* 23:16 */ -#define SYSACE_ERRREG3 0x0b /* 31:24 */ - -#define SYSACE_CTRLREG0 0x18 /* 7:0 */ -#define SYSACE_CTRLREG1 0x19 /* 15:8 */ -#define SYSACE_CTRLREG2 0x1A /* 23:16 */ -#define SYSACE_CTRLREG3 0x1B /* 31:24 */ - -/* - * Software reconfig thing - */ -#define SW_BYTE_SECTOR_ADDR 0x24FE0000 -#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF -#define SW_BYTE_SECTOR_SIZE 0x00020000 -#define SW_BYTE_MASK 0x00000003 - -#define DEFAULT_TEMP_ADDR 0x00100000 - -#define AP1000_CPLD_BASE 0x26000000 - -/* PowerSpan II Stuff */ -#define PSII_SYNC() asm("eieio") -#define PSPAN_BASEADDR 0x30000000 -#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \ - 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \ - 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \ - 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \ - 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \ - 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \ - 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \ - 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \ - 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \ - 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \ - 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \ - 0x00, /* Byte 15 - Vital Product Data Disabled. */ \ - 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \ - 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \ - 0x00, /* Byte 18 - I2O disabled */ \ - 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \ - 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \ - 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \ - 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \ - 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \ - 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \ - 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \ - /* Long Load Information */ \ - 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \ - 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \ - 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \ - 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \ - 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \ - 0x01, /* Byte 39 - Power span revision 1. */ \ - 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \ - 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \ - 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \ - 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \ - 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \ - 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \ - 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \ - 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \ - 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \ - 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \ - 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \ - 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \ - 0x01, /* Byte 59 - PCI-2 class revision 1 */ \ - 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */ - - -#define EEPROM_LENGTH 64 /* Long Load */ - -#define I2C_SENSOR_DEV 0x9 -#define I2C_SENSOR_CHIP_SEL 0x4 - -/* - * Board Functions - */ -void set_eat_machine_checks(int a_flag); -int get_eat_machine_checks(void); -unsigned int get_platform(void); -void* memcpyb(void * dest,const void *src,size_t count); -int process_bootflag(ulong bootflag); -void user_led_on(void); -void user_led_off(void); - -#endif /* __COMMON_H_ */ diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c deleted file mode 100644 index bf8877ec6a1..00000000000 --- a/board/amirix/ap1000/flash.c +++ /dev/null @@ -1,900 +0,0 @@ -/** - * @file flash.c - */ - -/* - * (C) Copyright 2003 - * AMIRIX Systems Inc. - * - * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c - * - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char *cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isequal (flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isset (flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_detect_cfi (flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t * info, ulong dest, - cfiword_t cword); -static int flash_full_status_check (flash_info_t * info, ulong sector, - ulong tout, char *prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, - int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -uchar *flash_make_addr (flash_info_t * info, int sect, int offset) -{ - return ((uchar *) (info->start[sect] + (offset * info->chipwidth))); -} - -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -uchar flash_read_uchar (flash_info_t * info, uchar offset) -{ - if (info->portwidth == FLASH_CFI_8BIT) { - volatile uchar *cp; - uchar c; - - cp = flash_make_addr (info, 0, offset); - c = *cp; -#ifdef DEBUG_FLASH - printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n", - offset, (unsigned int) cp, c); -#endif - return (c); - - } else if (info->portwidth == FLASH_CFI_16BIT) { - volatile ushort *sp; - ushort s; - uchar c; - - sp = (ushort *) flash_make_addr (info, 0, offset); - s = *sp; - c = (uchar) s; -#ifdef DEBUG_FLASH - printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c); -#endif - return (c); - - } - - return 0; -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset) -{ - if (info->portwidth == FLASH_CFI_8BIT) { - volatile uchar *cp; - uchar c0, c1; - ushort s; - - cp = flash_make_addr (info, 0, offset); - c1 = cp[2]; - c0 = cp[0]; - s = c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s); -#endif - return (s); - - } else if (info->portwidth == FLASH_CFI_16BIT) { - volatile ushort *sp; - ushort s; - uchar c0, c1; - - sp = (ushort *) flash_make_addr (info, 0, offset); - s = *sp; - c1 = (uchar) sp[1]; - c0 = (uchar) sp[0]; - s = c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s); -#endif - return (s); - - } - - return 0; -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long (flash_info_t * info, int sect, uchar offset) -{ - if (info->portwidth == FLASH_CFI_8BIT) { - volatile uchar *cp; - uchar c0, c1, c2, c3; - ulong l; - - cp = flash_make_addr (info, 0, offset); - c3 = cp[6]; - c2 = cp[4]; - c1 = cp[2]; - c0 = cp[0]; - l = c3 << 24 | c2 << 16 | c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l); -#endif - return (l); - - } else if (info->portwidth == FLASH_CFI_16BIT) { - volatile ushort *sp; - uchar c0, c1, c2, c3; - ulong l; - - sp = (ushort *) flash_make_addr (info, 0, offset); - c3 = (uchar) sp[3]; - c2 = (uchar) sp[2]; - c1 = (uchar) sp[1]; - c0 = (uchar) sp[0]; - l = c3 << 24 | c2 << 16 | c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l); -#endif - return (l); - - } - - return 0; -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - - size = 0; - - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[0].portwidth = FLASH_CFI_16BIT; - flash_info[0].chipwidth = FLASH_CFI_16BIT; - size += flash_info[0].size = flash_get_size (CONFIG_SYS_PROGFLASH_BASE, 0); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20); - }; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].portwidth = FLASH_CFI_8BIT; - flash_info[1].chipwidth = FLASH_CFI_16BIT; - size += flash_info[1].size = flash_get_size (CONFIG_SYS_CONFFLASH_BASE, 1); - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20); - }; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd (info, sect, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sect, 0, - FLASH_CMD_BLOCK_ERASE); - flash_write_cmd (info, sect, 0, - FLASH_CMD_ERASE_CONFIRM); - - if (flash_full_status_check - (info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf ("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf ("CFI conformant FLASH (x%d device in x%d mode)", - (info->chipwidth << 3), (info->portwidth << 3)); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if ((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for (i = 0; i < aln; ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); - - for (; (i < info->portwidth) && (cnt > 0); i++) { - flash_add_byte (info, &cword, *src++); - cnt--; - cp++; - } - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); - if ((rc = flash_write_cfiword (info, wp, cword)) != 0) - return rc; - wp = cp; - } -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while (cnt >= info->portwidth) { - i = info->buffer_size > cnt ? cnt : info->buffer_size; - if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -= i; - } -#else - /* handle the aligned part */ - while (cnt >= info->portwidth) { - cword.l = 0; - for (i = 0; i < info->portwidth; i++) { - flash_add_byte (info, &cword, *src++); - } - if ((rc = flash_write_cfiword (info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { - flash_add_byte (info, &cword, *src++); - --cnt; - } - for (; i < info->portwidth; ++i, ++cp) { - flash_add_byte (info, &cword, (*(uchar *) cp)); - } - - return flash_write_cfiword (info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if ((retcode = - flash_full_status_check (info, sector, info->erase_blk_tout, - prot ? "protect" : "unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if (prot == 0) { - int i; - - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) - flash_real_protect (info, i, 1); - } - } - } - - return retcode; -} - -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check (flash_info_t * info, ulong sector, ulong tout, - char *prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer (start) > info->erase_blk_tout) { - printf ("Flash %s timeout at address %lx\n", prompt, - info->start[sector]); - flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check (flash_info_t * info, ulong sector, - ulong tout, char *prompt) -{ - int retcode; - - retcode = flash_status_check (info, sector, tout, prompt); - if ((retcode == ERR_OK) - && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf ("Flash %s error at address %lx\n", prompt, - info->start[sector]); - if (flash_isset - (info, sector, 0, - FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { - printf ("Command Sequence Error.\n"); - } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { - printf ("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { - printf ("Locking Error\n"); - } - if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { - printf ("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) - printf ("Vpp Low Error.\n"); - } - flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); - return retcode; -} - -/*----------------------------------------------------------------------- - */ -static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) -{ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) -{ - /*int i; */ - uchar *cp = (uchar *) cmdbuf; - - /* for(i=0; i< info->portwidth; i++) */ - /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */ - if (info->portwidth == FLASH_CFI_8BIT - && info->chipwidth == FLASH_CFI_16BIT) { - cp[0] = cmd; - } else if (info->portwidth == FLASH_CFI_16BIT - && info->chipwidth == FLASH_CFI_16BIT) { - cp[0] = '\0'; - cp[1] = cmd; - }; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - - addr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal (flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - */ -static int flash_isset (flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi (flash_info_t * info) -{ - -#if 0 - for (info->portwidth = FLASH_CFI_8BIT; - info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { - for (info->chipwidth = FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd (info, 0, FLASH_OFFSET_CFI, - FLASH_CMD_CFI); - if (flash_isequal - (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, - FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, - FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } -#endif - flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && - flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { - return 1; - } else { - return 0; - }; -} - -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if (flash_detect_cfi (info)) { -#ifdef DEBUG_FLASH - printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = 1; /* info->portwidth / info->chipwidth; */ - num_erase_regions = - flash_read_uchar (info, - FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf ("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for (i = 0; i < num_erase_regions; i++) { - if (i > NUM_ERASE_REGIONS) { - printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long (info, 0, - FLASH_OFFSET_ERASE_REGIONS); - erase_region_count = (tmp & 0xffff) + 1; - tmp >>= 16; - erase_region_size = - (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; - for (j = 0; j < erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = - flash_isset (info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = - (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * - size_ratio; - info->buffer_size = - (1 << - flash_read_ushort (info, 0, - FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = - (tmp * - (1 << - flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = - (tmp * - (1 << - flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); - info->write_tout = - (tmp * - (1 << - flash_read_uchar (info, - FLASH_OFFSET_WMAX_TOUT))) / 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t * info, ulong dest, - cfiword_t cword) -{ - cfiptr_t cptr; - int flag; - - cptr.cp = (uchar *) dest; - - /* Check if Flash is (sufficiently) erased */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if (!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); - - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - return flash_full_status_check (info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector (flash_info_t * info, ulong addr) -{ - int sector; - - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, - int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector (info, dest); - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = - flash_status_check (info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd (info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = - flash_full_status_check (info, sector, - info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S deleted file mode 100644 index eac7cd3c101..00000000000 --- a/board/amirix/ap1000/init.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * init.S: Stubs for ppcboot initialization - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c deleted file mode 100644 index d021164f981..00000000000 --- a/board/amirix/ap1000/pci.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2003 - * AMIRIX Systems Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <pci.h> - -#define PCI_MEM_82559ER_CSR_BASE 0x30200000 -#define PCI_IO_82559ER_CSR_BASE 0x40000200 - -/** AP1100 specific values */ -#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */ -#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */ -#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */ -#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */ -#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */ -#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */ -#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */ -#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */ - -/* static int G_verbosity_level = 1; */ -#define G_verbosity_level 1 - -void write1 (unsigned long addr, unsigned char val) -{ - volatile unsigned char *p = (volatile unsigned char *) addr; - - if (G_verbosity_level > 1) - printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr, - val); - *p = val; - asm ("eieio"); -} - -unsigned char read1 (unsigned long addr) -{ - unsigned char val; - volatile unsigned char *p = (volatile unsigned char *) addr; - - if (G_verbosity_level > 1) - printf ("read1: addr=%08x ", (unsigned int) addr); - val = *p; - asm ("eieio"); - if (G_verbosity_level > 1) - printf ("val=%08x\n", val); - return val; -} - -void write2 (unsigned long addr, unsigned short val) -{ - volatile unsigned short *p = (volatile unsigned short *) addr; - - if (G_verbosity_level > 1) - printf ("write2: addr=%08x val=%04x -> *p=%04x\n", - (unsigned int) addr, val, - ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); - - *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - asm ("eieio"); -} - -unsigned short read2 (unsigned long addr) -{ - unsigned short val; - volatile unsigned short *p = (volatile unsigned short *) addr; - - if (G_verbosity_level > 1) - printf ("read2: addr=%08x ", (unsigned int) addr); - val = *p; - val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - asm ("eieio"); - if (G_verbosity_level > 1) - printf ("*p=%04x -> val=%04x\n", - ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val); - return val; -} - -void write4 (unsigned long addr, unsigned long val) -{ - volatile unsigned long *p = (volatile unsigned long *) addr; - - if (G_verbosity_level > 1) - printf ("write4: addr=%08x val=%08x -> *p=%08x\n", - (unsigned int) addr, (unsigned int) val, - (unsigned int) (((val & 0xFF000000) >> 24) | - ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | - ((val & 0x0000FF00) << 8))); - - *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - asm ("eieio"); -} - -unsigned long read4 (unsigned long addr) -{ - unsigned long val; - volatile unsigned long *p = (volatile unsigned long *) addr; - - if (G_verbosity_level > 1) - printf ("read4: addr=%08x", (unsigned int) addr); - - val = *p; - val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - asm ("eieio"); - - if (G_verbosity_level > 1) - printf ("*p=%04x -> val=%04x\n", - (unsigned int) (((val & 0xFF000000) >> 24) | - ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | - ((val & 0x0000FF00) << 8)), - (unsigned int) val); - return val; -} - -void write4be (unsigned long addr, unsigned long val) -{ - volatile unsigned long *p = (volatile unsigned long *) addr; - - if (G_verbosity_level > 1) - printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr, - (unsigned int) val); - *p = val; - asm ("eieio"); -} - -/** One byte configuration write on PSII. - * Currently fixes destination PCI bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Address of location for received byte. - * @return Always Zero. - */ -static int psII_read_config_byte (struct pci_controller *hose, - pci_dev_t dev, int reg, u8 * val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - *val = read1 (PSII_CONFIG_DATA + (reg & 0x03)); - return (0); -} - -/** One byte configuration write on PSII. - * Currently fixes destination bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Output byte. - * @return Always Zero. - */ -static int psII_write_config_byte (struct pci_controller *hose, - pci_dev_t dev, int reg, u8 val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val); - - return (0); -} - -/** One word (16 bit) configuration read on PSII. - * Currently fixes destination PCI bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Address of location for received word. - * @return Always Zero. - */ -static int psII_read_config_word (struct pci_controller *hose, - pci_dev_t dev, int reg, u16 * val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - *val = read2 (PSII_CONFIG_DATA + (reg & 0x03)); - return (0); -} - -/** One word (16 bit) configuration write on PSII. - * Currently fixes destination bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Output word. - * @return Always Zero. - */ -static int psII_write_config_word (struct pci_controller *hose, - pci_dev_t dev, int reg, u16 val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val); - - return (0); -} - -/** One DWord (32 bit) configuration read on PSII. - * Currently fixes destination PCI bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Address of location for received byte. - * @return Always Zero. - */ -static int psII_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int reg, u32 * val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - *val = read4 (PSII_CONFIG_DATA); - return (0); -} - -/** One DWord (32 bit) configuration write on PSII. - * Currently fixes destination bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Output Dword. - * @return Always Zero. - */ -static int psII_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int reg, u32 val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - write4 (PSII_CONFIG_DATA, (unsigned long) val); - - return (0); -} - -static struct pci_config_table ap1000_config_table[] = { -#ifdef CONFIG_AP1000 - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS (CONFIG_SYS_ETH_DEV_FN), PCI_DEV (CONFIG_SYS_ETH_DEV_FN), - PCI_FUNC (CONFIG_SYS_ETH_DEV_FN), - pci_cfgfunc_config_device, - {CONFIG_SYS_ETH_IOBASE, CONFIG_SYS_ETH_MEMBASE, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, -#endif - {} -}; - -static struct pci_controller psII_hose = { - config_table:ap1000_config_table, -}; - -void pci_init_board (void) -{ - struct pci_controller *hose = &psII_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region (hose->regions + 0, - AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, - AP1000_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI Memory space */ - pci_set_region (hose->regions + 1, - PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, - PSII_PCI_MEM_SIZE, PCI_REGION_MEM); - - /* No IO Memory space - for now */ - - pci_set_ops (hose, - psII_read_config_byte, - psII_read_config_word, - psII_read_config_dword, - psII_write_config_byte, - psII_write_config_word, psII_write_config_dword); - - hose->region_count = 2; - - pci_register_hose (hose); - - hose->last_busno = pci_hose_scan (hose); -} diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c deleted file mode 100644 index 55451b11f0a..00000000000 --- a/board/amirix/ap1000/powerspan.c +++ /dev/null @@ -1,750 +0,0 @@ -/** - * @file powerspan.c Source file for PowerSpan II code. - */ - -/* - * (C) Copyright 2005 - * AMIRIX Systems Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include "powerspan.h" -#define tolower(x) x -#include "ap1000.h" - -#ifdef INCLUDE_PCI - -/** Write one byte with byte swapping. - * @param addr [IN] the address to write to - * @param val [IN] the value to write - */ -void write1 (unsigned long addr, unsigned char val) -{ - volatile unsigned char *p = (volatile unsigned char *) addr; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("write1: addr=%08x val=%02x\n", addr, val); - } -#endif - *p = val; - PSII_SYNC (); -} - -/** Read one byte with byte swapping. - * @param addr [IN] the address to read from - * @return the value at addr - */ -unsigned char read1 (unsigned long addr) -{ - unsigned char val; - volatile unsigned char *p = (volatile unsigned char *) addr; - - val = *p; - PSII_SYNC (); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("read1: addr=%08x val=%02x\n", addr, val); - } -#endif - return val; -} - -/** Write one 2-byte word with byte swapping. - * @param addr [IN] the address to write to - * @param val [IN] the value to write - */ -void write2 (unsigned long addr, unsigned short val) -{ - volatile unsigned short *p = (volatile unsigned short *) addr; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val, - ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); - } -#endif - *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - PSII_SYNC (); -} - -/** Read one 2-byte word with byte swapping. - * @param addr [IN] the address to read from - * @return the value at addr - */ -unsigned short read2 (unsigned long addr) -{ - unsigned short val; - volatile unsigned short *p = (volatile unsigned short *) addr; - - val = *p; - val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - PSII_SYNC (); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p, - val); - } -#endif - return val; -} - -/** Write one 4-byte word with byte swapping. - * @param addr [IN] the address to write to - * @param val [IN] the value to write - */ -void write4 (unsigned long addr, unsigned long val) -{ - volatile unsigned long *p = (volatile unsigned long *) addr; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val, - ((val & 0xFF000000) >> 24) | - ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | - ((val & 0x0000FF00) << 8)); - } -#endif - *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - PSII_SYNC (); -} - -/** Read one 4-byte word with byte swapping. - * @param addr [IN] the address to read from - * @return the value at addr - */ -unsigned long read4 (unsigned long addr) -{ - unsigned long val; - volatile unsigned long *p = (volatile unsigned long *) addr; - - val = *p; - val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - PSII_SYNC (); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p, - val); - } -#endif - return val; -} - -int PCIReadConfig (int bus, int dev, int fn, int reg, int width, - unsigned long *val) -{ - unsigned int conAdrVal; - unsigned int conDataReg = REG_CONFIG_DATA; - unsigned int status; - int ret_val = 0; - - - /* DEST bit hardcoded to 1: local pci is PCI-2 */ - /* TYPE bit is hardcoded to 1: all config cycles are local */ - conAdrVal = (1 << 24) - | ((bus & 0xFF) << 16) - | ((dev & 0xFF) << 11) - | ((fn & 0x07) << 8) - | (reg & 0xFC); - - /* clear any pending master aborts */ - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - - /* Load the conAdrVal value first, then read from pb_conf_data */ - write4 (REG_CONFIG_ADDRESS, conAdrVal); - PSII_SYNC (); - - - /* Note: documentation does not match the pspan library code */ - /* Note: *pData comes back as -1 if device is not present */ - switch (width) { - case 4: - *(unsigned int *) val = read4 (conDataReg); - break; - case 2: - *(unsigned short *) val = read2 (conDataReg); - break; - case 1: - *(unsigned char *) val = read1 (conDataReg); - break; - default: - ret_val = ILLEGAL_REG_OFFSET; - break; - } - PSII_SYNC (); - - /* clear any pending master aborts */ - status = read4 (REG_P1_CSR); - if (status & CLEAR_MASTER_ABORT) { - ret_val = NO_DEVICE_FOUND; - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - } - - return ret_val; -} - - -int PCIWriteConfig (int bus, int dev, int fn, int reg, int width, - unsigned long val) -{ - unsigned int conAdrVal; - unsigned int conDataReg = REG_CONFIG_DATA; - unsigned int status; - int ret_val = 0; - - - /* DEST bit hardcoded to 1: local pci is PCI-2 */ - /* TYPE bit is hardcoded to 1: all config cycles are local */ - conAdrVal = (1 << 24) - | ((bus & 0xFF) << 16) - | ((dev & 0xFF) << 11) - | ((fn & 0x07) << 8) - | (reg & 0xFC); - - /* clear any pending master aborts */ - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - - /* Load the conAdrVal value first, then read from pb_conf_data */ - write4 (REG_CONFIG_ADDRESS, conAdrVal); - PSII_SYNC (); - - - /* Note: documentation does not match the pspan library code */ - /* Note: *pData comes back as -1 if device is not present */ - switch (width) { - case 4: - write4 (conDataReg, val); - break; - case 2: - write2 (conDataReg, val); - break; - case 1: - write1 (conDataReg, val); - break; - default: - ret_val = ILLEGAL_REG_OFFSET; - break; - } - PSII_SYNC (); - - /* clear any pending master aborts */ - status = read4 (REG_P1_CSR); - if (status & CLEAR_MASTER_ABORT) { - ret_val = NO_DEVICE_FOUND; - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - } - - return ret_val; -} - - -int pci_read_config_byte (int bus, int dev, int fn, int reg, - unsigned char *val) -{ - unsigned long read_val; - int ret_val; - - ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val); - *val = read_val & 0xFF; - - return ret_val; -} - -int pci_write_config_byte (int bus, int dev, int fn, int reg, - unsigned char val) -{ - return PCIWriteConfig (bus, dev, fn, reg, 1, val); -} - -int pci_read_config_word (int bus, int dev, int fn, int reg, - unsigned short *val) -{ - unsigned long read_val; - int ret_val; - - ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val); - *val = read_val & 0xFFFF; - - return ret_val; -} - -int pci_write_config_word (int bus, int dev, int fn, int reg, - unsigned short val) -{ - return PCIWriteConfig (bus, dev, fn, reg, 2, val); -} - -int pci_read_config_dword (int bus, int dev, int fn, int reg, - unsigned long *val) -{ - return PCIReadConfig (bus, dev, fn, reg, 4, val); -} - -int pci_write_config_dword (int bus, int dev, int fn, int reg, - unsigned long val) -{ - return PCIWriteConfig (bus, dev, fn, reg, 4, val); -} - -#endif /* INCLUDE_PCI */ - -int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode, - unsigned char theChipSel, unsigned char *theValue, int RWFlag) -{ - int ret_val = 0; - unsigned int reg_value; - - reg_value = PowerSpanRead (REG_I2C_CSR); - - if (reg_value & I2C_CSR_ACT) { - printf ("Error: I2C busy\n"); - ret_val = I2C_BUSY; - } else { - reg_value = ((theI2CAddress & 0xFF) << 24) - | ((theDevCode & 0x0F) << 12) - | ((theChipSel & 0x07) << 9) - | I2C_CSR_ERR; - if (RWFlag == I2C_WRITE) { - reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16); - } - - PowerSpanWrite (REG_I2C_CSR, reg_value); - udelay (1); - - do { - reg_value = PowerSpanRead (REG_I2C_CSR); - - if ((reg_value & I2C_CSR_ACT) == 0) { - if (reg_value & I2C_CSR_ERR) { - ret_val = I2C_ERR; - } else { - *theValue = - (reg_value & I2C_CSR_DATA) >> - 16; - } - } - } while (reg_value & I2C_CSR_ACT); - } - - return ret_val; -} - -int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue) -{ - return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, - theValue, I2C_READ); -} - -int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue) -{ - return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, - &theValue, I2C_WRITE); -} - -int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - char cmd; - int ret_val = 0; - unsigned int address = 0; - unsigned char value = 1; - unsigned char read_value; - int ii; - int error = 0; - unsigned char *mem_ptr; - unsigned char default_eeprom[] = EEPROM_DEFAULT; - - if (argc < 2) { - goto usage; - } - - cmd = argv[1][0]; - if (argc > 2) { - address = simple_strtoul (argv[2], NULL, 16); - if (argc > 3) { - value = simple_strtoul (argv[3], NULL, 16) & 0xFF; - } - } - - switch (cmd) { - case 'r': - if (address > 256) { - printf ("Illegal Address\n"); - goto usage; - } - printf ("@0x%x: ", address); - for (ii = 0; ii < value; ii++) { - if (EEPROMRead (address + ii, &read_value) != - 0) { - printf ("Read Error\n"); - } else { - printf ("0x%02x ", read_value); - } - - if (((ii + 1) % 16) == 0) { - printf ("\n"); - } - } - printf ("\n"); - break; - case 'w': - if (address > 256) { - printf ("Illegal Address\n"); - goto usage; - } - if (argc < 4) { - goto usage; - } - if (EEPROMWrite (address, value) != 0) { - printf ("Write Error\n"); - } - break; - case 'g': - if (argc != 3) { - goto usage; - } - mem_ptr = (unsigned char *) address; - for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); - ii++) { - if (EEPROMRead (ii, &read_value) != 0) { - printf ("Read Error\n"); - error = 1; - } else { - *mem_ptr = read_value; - mem_ptr++; - } - } - break; - case 'p': - if (argc != 3) { - goto usage; - } - mem_ptr = (unsigned char *) address; - for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); - ii++) { - if (EEPROMWrite (ii, *mem_ptr) != 0) { - printf ("Write Error\n"); - error = 1; - } - - mem_ptr++; - } - break; - case 'd': - if (argc != 2) { - goto usage; - } - for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); - ii++) { - if (EEPROMWrite (ii, default_eeprom[ii]) != 0) { - printf ("Write Error\n"); - error = 1; - } - } - break; - default: - goto usage; - } - - goto done; - usage: - printf ("Usage:\n%s\n", cmdtp->help); - - done: - return ret_val; - -} - -U_BOOT_CMD (eeprom, 4, 0, do_eeprom, - "read/write/copy to/from the PowerSpan II eeprom", - "eeprom r OFF [NUM]\n" - " - read NUM words starting at OFF\n" - "eeprom w OFF VAL\n" - " - write word VAL at offset OFF\n" - "eeprom g ADD\n" - " - store contents of eeprom at address ADD\n" - "eeprom p ADD\n" - " - put data stored at address ADD into the eeprom\n" - "eeprom d\n" " - return eeprom to default contents"); - -unsigned int PowerSpanRead (unsigned int theOffset) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); - unsigned int ret_val; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanRead: offset=%08x ", theOffset); - } -#endif - ret_val = *ptr; - PSII_SYNC (); - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("value=%08x\n", ret_val); - } -#endif - - return ret_val; -} - -void PowerSpanWrite (unsigned int theOffset, unsigned int theValue) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset, - theValue); - } -#endif - *ptr = theValue; - PSII_SYNC (); -} - -/** - * Sets the indicated bits in the indicated register. - * @param theOffset [IN] the register to access. - * @param theMask [IN] bits set in theMask will be set in the register. - */ -void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); - unsigned int register_value; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanSetBits: offset=%08x mask=%02x\n", - theOffset, theMask); - } -#endif - register_value = *ptr; - PSII_SYNC (); - - register_value |= theMask; - *ptr = register_value; - PSII_SYNC (); -} - -/** - * Clears the indicated bits in the indicated register. - * @param theOffset [IN] the register to access. - * @param theMask [IN] bits set in theMask will be cleared in the register. - */ -void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); - unsigned int register_value; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanClearBits: offset=%08x mask=%02x\n", - theOffset, theMask); - } -#endif - register_value = *ptr; - PSII_SYNC (); - - register_value &= ~theMask; - *ptr = register_value; - PSII_SYNC (); -} - -/** - * Configures a slave image on the local bus, based on the parameters and some hardcoded system values. - * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they - * are outgoing from the standpoint of the local bus. - * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7). - * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]). - * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. - * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). - * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). - * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). - */ -int SetSlaveImage (int theImageIndex, unsigned int theBlockSize, - int theMemIOFlag, int theEndianness, - unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr) -{ - unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF; - unsigned int reg_value = 0; - - /* Make sure that the Slave Image is disabled */ - PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset), - PB_SLAVE_CSR_IMG_EN); - - /* Setup the mask required for requested PB Slave Image configuration */ - reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24); - if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) { - reg_value |= PB_SLAVE_CSR_MEM_IO; - } - - /* hardcoding the following: - TA_EN = 1 - MD_EN = 0 - MODE = 0 - PRKEEP = 0 - RD_AMT = 0 - */ - PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value); - - /* these values are not checked by software */ - PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr); - PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr); - - /* Enable the Slave Image */ - PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset), - PB_SLAVE_CSR_IMG_EN); - - return 0; -} - -/** - * Configures a target image on the local bus, based on the parameters and some hardcoded system values. - * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they - * are incoming from the standpoint of the local bus. - * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI - * base address will not be updated; makes sense given that the hosts own memory should be mapped to - * PCI address 0x00000000. - * @param theImageIndex [IN] the PowerSpan II image to set. - * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]). - * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. - * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). - * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). - * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). - */ -int SetTargetImage (int theImageIndex, unsigned int theBlockSize, - int theMemIOFlag, int theEndianness, - unsigned int theLocalBaseAddr, - unsigned int thePCIBaseAddr) -{ - unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF; - unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF; - unsigned int reg_value = 0; - - /* Make sure that the Slave Image is disabled */ - PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset), - PB_SLAVE_CSR_IMG_EN); - - /* Setup the mask required for requested PB Slave Image configuration */ - reg_value = - PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) | - PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness; - if (theMemIOFlag == PX_TGT_USE_MEM_IO) { - reg_value |= PX_TGT_MEM_IO; - } - - /* hardcoding the following: - TA_EN = 1 - BAR_EN = 1 - MD_EN = 0 - MODE = 0 - DEST = 0 - RTT = 01010 - GBL = 0 - CI = 0 - WTT = 00010 - PRKEEP = 0 - MRA = 0 - RD_AMT = 0 - */ - PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value); - - PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset), - theLocalBaseAddr); - - if (thePCIBaseAddr != (unsigned int) NULL) { - PowerSpanWrite ((REGS_P1_BST + pci_reg_offset), - thePCIBaseAddr); - } - - /* Enable the Slave Image */ - PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset), - PB_SLAVE_CSR_IMG_EN); - - return 0; -} - -int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - char cmd; - int ret_val = 1; - unsigned int image_index; - unsigned int block_size; - unsigned int mem_io; - unsigned int local_addr; - unsigned int pci_addr; - int endianness; - - if (argc != 8) { - goto usage; - } - - cmd = argv[1][0]; - image_index = simple_strtoul (argv[2], NULL, 16); - block_size = simple_strtoul (argv[3], NULL, 16); - mem_io = simple_strtoul (argv[4], NULL, 16); - endianness = argv[5][0]; - local_addr = simple_strtoul (argv[6], NULL, 16); - pci_addr = simple_strtoul (argv[7], NULL, 16); - - - switch (cmd) { - case 'i': - if (tolower (endianness) == 'b') { - endianness = PX_TGT_CSR_BIG_END; - } else if (tolower (endianness) == 'l') { - endianness = PX_TGT_CSR_TRUE_LEND; - } else { - goto usage; - } - SetTargetImage (image_index, block_size, mem_io, - endianness, local_addr, pci_addr); - break; - case 'o': - if (tolower (endianness) == 'b') { - endianness = PB_SLAVE_CSR_BIG_END; - } else if (tolower (endianness) == 'l') { - endianness = PB_SLAVE_CSR_TRUE_LEND; - } else { - goto usage; - } - SetSlaveImage (image_index, block_size, mem_io, - endianness, local_addr, pci_addr); - break; - default: - goto usage; - } - - goto done; -usage: - printf ("Usage:\n%s\n", cmdtp->help); - -done: - return ret_val; -} diff --git a/board/amirix/ap1000/powerspan.h b/board/amirix/ap1000/powerspan.h deleted file mode 100644 index 4e9a8c1bd86..00000000000 --- a/board/amirix/ap1000/powerspan.h +++ /dev/null @@ -1,170 +0,0 @@ -/** - * @file powerspan.h Header file for PowerSpan II code. - */ - -/* - * (C) Copyright 2005 - * AMIRIX Systems Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef POWERSPAN_H -#define POWERSPAN_H - -#define CLEAR_MASTER_ABORT 0xdeadbeef -#define NO_DEVICE_FOUND -1 -#define ILLEGAL_REG_OFFSET -2 -#define I2C_BUSY -3 -#define I2C_ERR -4 - -#define REG_P1_CSR 0x004 -#define REGS_P1_BST 0x018 -#define REG_P1_ERR_CSR 0x150 -#define REG_P1_MISC_CSR 0x160 -#define REGS_P1_TGT_CSR 0x100 -#define REGS_P1_TGT_TADDR 0x104 -#define REGS_PB_SLAVE_CSR 0x200 -#define REGS_PB_SLAVE_TADDR 0x204 -#define REGS_PB_SLAVE_BADDR 0x208 -#define REG_CONFIG_ADDRESS 0x290 -#define REG_CONFIG_DATA 0x294 -#define REG_PB_ERR_CSR 0x2B0 -#define REG_PB_MISC_CSR 0x2C0 -#define REG_MISC_CSR 0x400 -#define REG_I2C_CSR 0x408 -#define REG_RESET_CSR 0x40C -#define REG_ISR0 0x410 -#define REG_ISR1 0x414 -#define REG_IER0 0x418 -#define REG_MBOX_MAP 0x420 -#define REG_HW_MAP 0x42C -#define REG_IDR 0x444 - -#define CSR_MEMORY_SPACE_ENABLE 0x00000002 -#define CSR_PCI_MASTER_ENABLE 0x00000004 - -#define P1_BST_OFF 0x04 - -#define PX_ERR_ERR_STATUS 0x01000000 - -#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00 -#define PX_MISC_CSR_MAX_RETRY 0x00000F00 -#define PX_MISC_REG_BAR_ENABLE 0x00008000 -#define PB_MISC_TEA_ENABLE 0x00000010 -#define PB_MISC_MAC_TEA 0x00000040 - -#define P1_TGT_IMAGE_OFF 0x010 -#define PX_TGT_CSR_IMG_EN 0x80000000 -#define PX_TGT_CSR_TA_EN 0x40000000 -#define PX_TGT_CSR_BAR_EN 0x20000000 -#define PX_TGT_CSR_MD_EN 0x10000000 -#define PX_TGT_CSR_MODE 0x00800000 -#define PX_TGT_CSR_DEST 0x00400000 -#define PX_TGT_CSR_MEM_IO 0x00200000 -#define PX_TGT_CSR_GBL 0x00080000 -#define PX_TGT_CSR_CL 0x00040000 -#define PX_TGT_CSR_PRKEEP 0x00000080 - -#define PX_TGT_CSR_BS_MASK 0x0F000000 -#define PX_TGT_MEM_IO 0x00200000 -#define PX_TGT_CSR_RTT_MASK 0x001F0000 -#define PX_TGT_CSR_RTT_READ 0x000A0000 -#define PX_TGT_CSR_WTT_MASK 0x00001F00 -#define PX_TGT_CSR_WTT_WFLUSH 0x00000200 -#define PX_TGT_CSR_END_MASK 0x00000060 -#define PX_TGT_CSR_BIG_END 0x00000040 -#define PX_TGT_CSR_TRUE_LEND 0x00000060 -#define PX_TGT_CSR_RDAMT_MASK 0x00000007 - -#define PX_TGT_CSR_BS_64MB 0xa -#define PX_TGT_CSR_BS_16MB 0x8 - -#define PX_TGT_USE_MEM_IO 1 -#define PX_TGT_NOT_MEM_IO 0 - -#define PB_SLAVE_IMAGE_OFF 0x010 -#define PB_SLAVE_CSR_IMG_EN 0x80000000 -#define PB_SLAVE_CSR_TA_EN 0x40000000 -#define PB_SLAVE_CSR_MD_EN 0x20000000 -#define PB_SLAVE_CSR_MODE 0x00800000 -#define PB_SLAVE_CSR_DEST 0x00400000 -#define PB_SLAVE_CSR_MEM_IO 0x00200000 -#define PB_SLAVE_CSR_PRKEEP 0x00000080 - -#define PB_SLAVE_CSR_BS_MASK 0x1F000000 -#define PB_SLAVE_CSR_END_MASK 0x00000060 -#define PB_SLAVE_CSR_BIG_END 0x00000040 -#define PB_SLAVE_CSR_TRUE_LEND 0x00000060 -#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007 - -#define PB_SLAVE_USE_MEM_IO 1 -#define PB_SLAVE_NOT_MEM_IO 0 - - -#define MISC_CSR_PCI1_LOCK 0x00000080 - -#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */ -#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */ -#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */ -#define I2C_CSR_CS 0x00000E00 /* Chip Select */ -#define I2C_CSR_RW 0x00000100 /* Read/Write */ -#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */ -#define I2C_CSR_ERR 0x00000040 /* Error */ - -#define I2C_EEPROM_DEV 0xa -#define I2C_EEPROM_CHIP_SEL 0 - -#define I2C_READ 0 -#define I2C_WRITE 1 - -#define RESET_CSR_EEPROM_LOAD 0x00000010 - -#define ISR_CLEAR_ALL 0xFFFFFFFF - -#define IER0_DMA_INTS_EN 0x0F000000 -#define IER0_PCI_1_EN 0x00400000 -#define IER0_HW_INTS_EN 0x003F0000 -#define IER0_MB_INTS_EN 0x000000FF -#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN) - -#define MBOX_MAP_TO_INT4 0xCCCCCCCC - -#define HW_MAP_HW4_TO_INT4 0x000C0000 - -#define IDR_PCI_A_OUT 0x40000000 -#define IDR_MBOX_OUT 0x10000000 - - -int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val); -int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val); -int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val); -int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val); -int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val); -int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val); - -unsigned int PowerSpanRead(unsigned int theOffset); -void PowerSpanWrite(unsigned int theOffset, unsigned int theValue); - -int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag); - -int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val); -int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val); - -int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); -int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); - -#endif diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c deleted file mode 100644 index 87003be9c12..00000000000 --- a/board/amirix/ap1000/serial.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2002 - * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/u-boot.h> -#include <asm/processor.h> -#include <command.h> -#include <config.h> - -#include <ns16550.h> - -DECLARE_GLOBAL_DATA_PTR; - -const NS16550_t COM_PORTS[] = - { (NS16550_t) CONFIG_SYS_NS16550_COM1, (NS16550_t) CONFIG_SYS_NS16550_COM2 }; - -#undef CONFIG_SYS_DUART_CHAN -#define CONFIG_SYS_DUART_CHAN gComPort -static int gComPort = 0; - -int serial_init (void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - - (void) NS16550_init (COM_PORTS[0], clock_divisor); - gComPort = 0; - - return 0; -} - -void serial_putc (const char c) -{ - if (c == '\n') { - NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - } - - NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); -} - -int serial_getc (void) -{ - return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -int serial_tstc (void) -{ - return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -void serial_setbrg (void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds deleted file mode 100644 index cd8f5cebab5..00000000000 --- a/board/amirix/ap1000/u-boot.lds +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/amirix/ap1000/init.o (.text) - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile new file mode 100644 index 00000000000..9f9618b518b --- /dev/null +++ b/board/atmark-techno/armadillo-800eva/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += armadillo-800eva.o +COBJS := $(COBJS-y) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c new file mode 100644 index 00000000000..0e9c22296a3 --- /dev/null +++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> + +#define s_init_wait(cnt) \ + ({ \ + volatile u32 i = 0x10000 * cnt; \ + while (i > 0) \ + i--; \ + }) + +#define USBCR1 0xE605810A + +void s_init(void) +{ + struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE; + struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE; + struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE; + struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE; + struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE; + struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE; + + /* Watchdog init */ + writew(0xA500, &rwdt0->rwtcsra0); + writew(0xA500, &rwdt1->rwtcsra0); + + /* CPG */ + writel(0xFF800080, &cpg->rmstpcr4); + writel(0xFF800080, &cpg->smstpcr4); + + /* USB clock */ + writel(0x00000080, &cpg->usbckcr); + s_init_wait(1); + + /* USBCR1 */ + writew(0x0710, USBCR1); + + /* FRQCR */ + writel(0x00000000, &cpg->frqcrb); + writel(0x62030533, &cpg->frqcra); + writel(0x208A354E, &cpg->frqcrc); + writel(0x80331050, &cpg->frqcrb); + s_init_wait(1); + + writel(0x00000000, &cpg->frqcrd); + s_init_wait(1); + + /* SUBClk */ + writel(0x0000010B, &cpg->subckcr); + + /* PLL */ + writel(0x00004004, &cpg->pllc01cr); + s_init_wait(1); + + writel(0xa0000000, &cpg->pllc2cr); + s_init_wait(2); + + /* BSC */ + writel(0x0000001B, &bsc->cmncr); + + writel(0x20000000, &dbsc->dbcmd); + writel(0x10009C40, &dbsc->dbcmd); + s_init_wait(1); + + writel(0x00000007, &dbsc->dbkind); + writel(0x0E030A02, &dbsc->dbconf0); + writel(0x00000001, &dbsc->dbphytype); + writel(0x00000000, &dbsc->dbbl); + writel(0x00000006, &dbsc->dbtr0); + writel(0x00000005, &dbsc->dbtr1); + writel(0x00000000, &dbsc->dbtr2); + writel(0x00000006, &dbsc->dbtr3); + writel(0x00080006, &dbsc->dbtr4); + writel(0x00000015, &dbsc->dbtr5); + writel(0x0000000f, &dbsc->dbtr6); + writel(0x00000004, &dbsc->dbtr7); + writel(0x00000018, &dbsc->dbtr8); + writel(0x00000006, &dbsc->dbtr9); + writel(0x00000006, &dbsc->dbtr10); + writel(0x0000000F, &dbsc->dbtr11); + writel(0x0000000D, &dbsc->dbtr12); + writel(0x000000A0, &dbsc->dbtr13); + writel(0x000A0003, &dbsc->dbtr14); + writel(0x00000003, &dbsc->dbtr15); + writel(0x40005005, &dbsc->dbtr16); + writel(0x0C0C0000, &dbsc->dbtr17); + writel(0x00000200, &dbsc->dbtr18); + writel(0x00000040, &dbsc->dbtr19); + writel(0x00000001, &dbsc->dbrnk0); + writel(0x00000110, &dbsc->dbdficnt); + writel(0x00000101, &ddrp->funcctrl); + writel(0x00000001, &ddrp->dllctrl); + writel(0x00000186, &ddrp->zqcalctrl); + writel(0xB3440051, &ddrp->zqodtctrl); + writel(0x94449443, &ddrp->rdctrl); + writel(0x000000C0, &ddrp->rdtmg); + writel(0x00000101, &ddrp->fifoinit); + writel(0x02060506, &ddrp->outctrl); + writel(0x00004646, &ddrp->dqcalofs1); + writel(0x00004646, &ddrp->dqcalofs2); + writel(0x800000aa, &ddrp->dqcalexp); + writel(0x00000000, &ddrp->dllctrl); + writel(0x00000000, DDRPNCNT); + + writel(0x0000000C, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00000002, DDRPNCNT); + + writel(0x0000000C, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00000187, &ddrp->zqcalctrl); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00000010, &dbsc->dbdficnt); + writel(0x02060507, &ddrp->outctrl); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x21009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x00009C40, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x11000044, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x2A000000, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x2B000000, &dbsc->dbcmd); + readl(&dbsc->dbwait); + + writel(0x29000004, &dbsc->dbcmd); + readl(&dbsc->dbwait); + + writel(0x28001520, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x03000200, &dbsc->dbcmd); + readl(&dbsc->dbwait); + s_init_wait(1); + + writel(0x000001FF, &dbsc->dbrfcnf0); + writel(0x00010C30, &dbsc->dbrfcnf1); + writel(0x00000000, &dbsc->dbrfcnf2); + + writel(0x00000001, &dbsc->dbrfen); + writel(0x00000001, &dbsc->dbacen); + + /* BSC */ + writel(0x00410400, &bsc->cs0bcr); + writel(0x00410400, &bsc->cs2bcr); + writel(0x00410400, &bsc->cs5bbcr); + writel(0x02CB0400, &bsc->cs6abcr); + + writel(0x00000440, &bsc->cs0wcr); + writel(0x00000440, &bsc->cs2wcr); + writel(0x00000240, &bsc->cs5bwcr); + writel(0x00000240, &bsc->cs6awcr); + + writel(0x00000005, &bsc->rbwtcnt); + writel(0x00000002, &bsc->cs0wcr2); + writel(0x00000002, &bsc->cs2wcr2); + writel(0x00000002, &bsc->cs4wcr2); +} + +#define GPIO_ICCR (0xE60581A0) +#define ICCR_15BIT (1 << 15) /* any time 1 */ +#define IIC0_CONTA (1 << 7) +#define IIC0_CONTB (1 << 6) +#define IIC1_CONTA (1 << 5) +#define IIC1_CONTB (1 << 4) +#define IIC0_PS33E (1 << 1) +#define IIC1_PS33E (1 << 0) +#define GPIO_ICCR_DATA \ + (ICCR_15BIT | \ + IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \ + IIC1_CONTB | IIC0_PS33E | IIC1_PS33E) + +#define MSTPCR1 0xE6150134 +#define TMU0_MSTP125 (1 << 25) +#define I2C0_MSTP116 (1 << 16) + +#define MSTPCR3 0xE615013C +#define I2C1_MSTP323 (1 << 23) +#define GETHER_MSTP309 (1 << 9) + +#define GPIO_SCIFA1_TXD (0xE60520C4) +#define GPIO_SCIFA1_RXD (0xE60520C3) + +int board_early_init_f(void) +{ + /* TMU */ + clrbits_le32(MSTPCR1, TMU0_MSTP125); + + /* GETHER */ + clrbits_le32(MSTPCR3, GETHER_MSTP309); + + /* I2C 0/1 */ + clrbits_le32(MSTPCR1, I2C0_MSTP116); + clrbits_le32(MSTPCR3, I2C1_MSTP323); + + /* SCIFA1 */ + writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */ + writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */ + + /* IICCR */ + writew(GPIO_ICCR_DATA, GPIO_ICCR); + + return 0; +} + +DECLARE_GLOBAL_DATA_PTR; +int board_init(void) +{ + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA; + /* adress of boot parameters */ + gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7740_pinmux_init(); + + /* GETHER Enable */ + gpio_request(GPIO_FN_ET_CRS, NULL); + gpio_request(GPIO_FN_ET_MDC, NULL); + gpio_request(GPIO_FN_ET_MDIO, NULL); + gpio_request(GPIO_FN_ET_TX_ER, NULL); + gpio_request(GPIO_FN_ET_RX_ER, NULL); + gpio_request(GPIO_FN_ET_ERXD0, NULL); + gpio_request(GPIO_FN_ET_ERXD1, NULL); + gpio_request(GPIO_FN_ET_ERXD2, NULL); + gpio_request(GPIO_FN_ET_ERXD3, NULL); + gpio_request(GPIO_FN_ET_TX_CLK, NULL); + gpio_request(GPIO_FN_ET_TX_EN, NULL); + gpio_request(GPIO_FN_ET_ETXD0, NULL); + gpio_request(GPIO_FN_ET_ETXD1, NULL); + gpio_request(GPIO_FN_ET_ETXD2, NULL); + gpio_request(GPIO_FN_ET_ETXD3, NULL); + gpio_request(GPIO_FN_ET_PHY_INT, NULL); + gpio_request(GPIO_FN_ET_COL, NULL); + gpio_request(GPIO_FN_ET_RX_DV, NULL); + gpio_request(GPIO_FN_ET_RX_CLK, NULL); + + gpio_request(GPIO_PORT18, NULL); /* PHY_RST */ + gpio_direction_output(GPIO_PORT18, 1); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +int board_late_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index ae408bc9db1..06028aa01e8 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -62,6 +62,10 @@ static void at91sam9x5ek_nand_hw_init(void) csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; /* NAND flash on D16 */ csa |= AT91_MATRIX_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 93f12ea4f19..e6a932ec3c7 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -27,27 +27,19 @@ #include <ns16550.h> #include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/board.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/uart.h> -#include <asm/arch/mmc.h> - +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/board.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/mmc.h> +#include <asm/arch-tegra/sys_proto.h> +#include <asm/arch-tegra/uart.h> #ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Tamonten - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) diff --git a/board/avionic-design/dts/tegra20-medcom.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index fc52f9ce4e1..f916122421a 100644 --- a/board/avionic-design/dts/tegra20-medcom.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -4,7 +4,7 @@ / { model = "Avionic Design Medcom-Wide"; - compatible = "avionic-design,medcom", "nvidia,tegra20"; + compatible = "ad,medcom-wide", "nvidia,tegra20"; aliases { usb0 = "/usb@c5008000"; diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index cef49ad8048..78c394f9358 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -4,7 +4,7 @@ / { model = "Avionic Design Plutux"; - compatible = "avionic-design,plutux", "nvidia,tegra20"; + compatible = "ad,plutux", "nvidia,tegra20"; aliases { usb0 = "/usb@c5008000"; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index bb3851b57d1..50ea3b51e4a 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -4,7 +4,7 @@ / { model = "Avionic Design Tamonten Evaluation Carrier"; - compatible = "avionic-design,tec", "nvidia,tegra20"; + compatible = "ad,tec", "nvidia,tegra20"; aliases { usb0 = "/usb@c5008000"; diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom-wide/Makefile index 864bc0ec01c..864bc0ec01c 100644 --- a/board/avionic-design/medcom/Makefile +++ b/board/avionic-design/medcom-wide/Makefile diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index f360323c9b7..c934988cc28 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -53,11 +53,6 @@ int board_init(void) return 0; } -struct serial_device *default_serial_console(void) -{ - return &serial_stuart_device; -} - int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/bmw/serial.c b/board/bmw/serial.c index 0c97f1288f1..08f449c8642 100644 --- a/board/bmw/serial.c +++ b/board/bmw/serial.c @@ -22,6 +22,9 @@ */ #include <common.h> +#include <serial.h> +#include <linux/compiler.h> + #include "ns16550.h" DECLARE_GLOBAL_DATA_PTR; @@ -38,7 +41,7 @@ static struct NS16550 *console = extern ulong get_bus_freq (ulong); -int serial_init (void) +static int bmw_serial_init(void) { int clock_divisor = gd->bus_clk / 16 / gd->baudrate; @@ -47,7 +50,7 @@ int serial_init (void) return (0); } -void serial_putc (const char c) +static void bmw_serial_putc(const char c) { if (c == '\n') { serial_putc ('\r'); @@ -55,7 +58,7 @@ void serial_putc (const char c) NS16550_putc (console, c); } -void serial_puts (const char *s) +static void bmw_serial_puts(const char *s) { while (*s) { serial_putc (*s++); @@ -63,19 +66,40 @@ void serial_puts (const char *s) } -int serial_getc (void) +static int bmw_serial_getc(void) { return NS16550_getc (console); } -int serial_tstc (void) +static int bmw_serial_tstc(void) { return NS16550_tstc (console); } -void serial_setbrg (void) +static void bmw_serial_setbrg(void) { int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate; NS16550_reinit (console, clock_divisor); } + +static struct serial_device bmw_serial_drv = { + .name = "bmw_serial", + .start = bmw_serial_init, + .stop = NULL, + .setbrg = bmw_serial_setbrg, + .putc = bmw_serial_putc, + .puts = bmw_serial_puts, + .getc = bmw_serial_getc, + .tstc = bmw_serial_tstc, +}; + +void bmw_serial_initialize(void) +{ + serial_register(&bmw_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &bmw_serial_drv; +} diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index b3f31d6b697..57776fb0774 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -195,9 +195,11 @@ int board_init(void) static void check_power_switch(void) { if (kw_gpio_get_value(GPIO_POWER_SWITCH)) { - /* turn off HDD and USB power */ + /* turn off fan, HDD and USB power */ kw_gpio_set_value(GPIO_HDD_POWER, 0); kw_gpio_set_value(GPIO_USB_VBUS, 0); + kw_gpio_set_value(GPIO_FAN_HIGH, 1); + kw_gpio_set_value(GPIO_FAN_LOW, 1); set_led(LED_OFF); /* loop until released */ @@ -207,6 +209,8 @@ static void check_power_switch(void) /* turn power on again */ kw_gpio_set_value(GPIO_HDD_POWER, 1); kw_gpio_set_value(GPIO_USB_VBUS, 1); + kw_gpio_set_value(GPIO_FAN_HIGH, 0); + kw_gpio_set_value(GPIO_FAN_LOW, 0); set_led(LED_POWER_BLINKING); } } diff --git a/board/cogent/serial.c b/board/cogent/serial.c index d9c27beee88..cd4a976f89e 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -5,6 +5,8 @@ #include <common.h> #include <board/cogent/serial.h> +#include <serial.h> +#include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -25,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial #endif -int serial_init (void) +static int cogent_serial_init(void) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; @@ -38,7 +40,7 @@ int serial_init (void) return (0); } -void serial_setbrg (void) +static void cogent_serial_setbrg(void) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; unsigned int divisor; @@ -54,7 +56,7 @@ void serial_setbrg (void) cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */ } -void serial_putc (const char c) +static void cogent_serial_putc(const char c) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; @@ -66,13 +68,13 @@ void serial_putc (const char c) cma_mb_reg_write (&mbsp->ser_thr, c); } -void serial_puts (const char *s) +static void cogent_serial_puts(const char *s) { while (*s != '\0') serial_putc (*s++); } -int serial_getc (void) +static int cogent_serial_getc(void) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; @@ -81,13 +83,33 @@ int serial_getc (void) return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f); } -int serial_tstc (void) +static int cogent_serial_tstc(void) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0); } +static struct serial_device cogent_serial_drv = { + .name = "cogent_serial", + .start = cogent_serial_init, + .stop = NULL, + .setbrg = cogent_serial_setbrg, + .putc = cogent_serial_putc, + .puts = cogent_serial_puts, + .getc = cogent_serial_getc, + .tstc = cogent_serial_tstc, +}; + +void cogent_serial_initialize(void) +{ + serial_register(&cogent_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &cogent_serial_drv; +} #endif /* CONS_NONE */ #if defined(CONFIG_CMD_KGDB) && \ diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 0f8f1670172..0725989de06 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -16,21 +16,14 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> #include <asm/arch/pinmux.h> -#include <asm/arch/mmc.h> +#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> #ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Paz00 - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} #ifdef CONFIG_TEGRA_MMC /* diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 893cca8c19b..9ef66fd8653 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -22,25 +22,18 @@ */ #include <common.h> -#include <i2c.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/mmc.h> +#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> +#include <i2c.h> #ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on TrimSlice - no UART-related GPIOs. - */ -void gpio_config_uart(void) -{ -} void pin_mux_spi(void) { diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 7e000404ee6..0edd9102106 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -176,6 +176,9 @@ int board_early_init_f(void) if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) return 1; + /* Set DISP_ON high to enable LCD output*/ + gpio_direction_output(97, 1); + /* Set the RESETOUTn low */ gpio_direction_output(111, 0); @@ -188,9 +191,6 @@ int board_early_init_f(void) /* Set LCD_B_PWR low to power down LCD Backlight*/ gpio_direction_output(102, 0); - /* Set DISP_ON low to disable LCD output*/ - gpio_direction_output(97, 0); - #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -250,15 +250,19 @@ int board_early_init_f(void) writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff, &davinci_syscfg_regs->mstpri[2]); - /* Set LCD_B_PWR low to power up LCD Backlight*/ - gpio_set_value(102, 1); - - /* Set DISP_ON low to disable LCD output*/ - gpio_set_value(97, 1); return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_init(void) { /* arch number of the board */ @@ -276,6 +280,9 @@ int board_init(void) int board_late_init(void) { + unsigned char buf[2]; + int ret; + /* PinMux for HALTEN */ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) return 1; @@ -283,8 +290,15 @@ int board_late_init(void) /* Set HALTEN to high */ gpio_direction_output(134, 1); - setenv("stdout", "serial"); + /* Set fixed contrast settings for LCD via I2C potentiometer */ + buf[0] = 0x00; + buf[1] = 0xd7; + ret = i2c_write(0x2e, 6, 1, buf, 2); + if (ret) + puts("\nContrast Settings FAILED\n"); + /* Set LCD_B_PWR high to power up LCD Backlight*/ + gpio_set_value(102, 1); return 0; } #endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index e1af37e1d8a..25f8950e9ad 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -35,6 +35,9 @@ #include <common.h> #include <command.h> +#include <serial.h> +#include <linux/compiler.h> + #include "../../Marvell/include/memory.h" #include "serial.h" @@ -42,14 +45,14 @@ DECLARE_GLOBAL_DATA_PTR; -int serial_init (void) +static int cpci750_serial_init(void) { mpsc_init (gd->baudrate); return (0); } -void serial_putc (const char c) +static void cpci750_serial_putc(const char c) { if (c == '\n') mpsc_putchar ('\r'); @@ -57,29 +60,50 @@ void serial_putc (const char c) mpsc_putchar (c); } -int serial_getc (void) +static int cpci750_serial_getc(void) { return mpsc_getchar (); } -int serial_tstc (void) +static int cpci750_serial_tstc(void) { return mpsc_test_char (); } -void serial_setbrg (void) +static void cpci750_serial_setbrg(void) { galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } -void serial_puts (const char *s) +static void cpci750_serial_puts(const char *s) { while (*s) { serial_putc (*s++); } } +static struct serial_device cpci750_serial_drv = { + .name = "cpci750_serial", + .start = cpci750_serial_init, + .stop = NULL, + .setbrg = cpci750_serial_setbrg, + .putc = cpci750_serial_putc, + .puts = cpci750_serial_puts, + .getc = cpci750_serial_getc, + .tstc = cpci750_serial_tstc, +}; + +void cpci750_serial_initialize(void) +{ + serial_register(&cpci750_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &cpci750_serial_drv; +} + #if defined(CONFIG_CMD_KGDB) void kgdb_serial_init (void) { diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index a60809a1dd6..279d7d4ff6a 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -415,7 +415,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, #if defined(CONFIG_PRAM) #include <environment.h> -extern env_t *env_ptr; int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index 9d711151f0c..9fd429864a7 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -30,6 +30,8 @@ #include <common.h> #include <command.h> #include <galileo/memory.h> +#include <serial.h> +#include <linux/compiler.h> #if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) #include <ns16550.h> @@ -48,7 +50,7 @@ const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1, #ifdef CONFIG_MPSC -int serial_init (void) +static int evb64260_serial_init(void) { #if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; @@ -66,8 +68,7 @@ int serial_init (void) return (0); } -void -serial_putc(const char c) +static void evb64260_serial_putc(const char c) { if (c == '\n') mpsc_putchar('\r'); @@ -75,27 +76,24 @@ serial_putc(const char c) mpsc_putchar(c); } -int -serial_getc(void) +static int evb64260_serial_getc(void) { return mpsc_getchar(); } -int -serial_tstc(void) +static int evb64260_serial_tstc(void) { return mpsc_test_char(); } -void -serial_setbrg (void) +static void evb64260_serial_setbrg(void) { galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); } #else /* ! CONFIG_MPSC */ -int serial_init (void) +static int evb64260_serial_init(void) { int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; @@ -109,8 +107,7 @@ int serial_init (void) return (0); } -void -serial_putc(const char c) +static void evb64260_serial_putc(const char c) { if (c == '\n') NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); @@ -118,20 +115,17 @@ serial_putc(const char c) NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } -int -serial_getc(void) +static int evb64260_serial_getc(void) { return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); } -int -serial_tstc(void) +static int evb64260_serial_tstc(void) { return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); } -void -serial_setbrg (void) +static void evb64260_serial_setbrg(void) { int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; @@ -145,14 +139,34 @@ serial_setbrg (void) #endif /* CONFIG_MPSC */ -void -serial_puts (const char *s) +static void evb64260_serial_puts(const char *s) { while (*s) { serial_putc (*s++); } } +static struct serial_device evb64260_serial_drv = { + .name = "evb64260_serial", + .start = evb64260_serial_init, + .stop = NULL, + .setbrg = evb64260_serial_setbrg, + .putc = evb64260_serial_putc, + .puts = evb64260_serial_puts, + .getc = evb64260_serial_getc, + .tstc = evb64260_serial_tstc, +}; + +void evb64260_serial_initialize(void) +{ + serial_register(&evb64260_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &evb64260_serial_drv; +} + #if defined(CONFIG_CMD_KGDB) void kgdb_serial_init(void) diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 62498abca39..62498abca39 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index d782aea61b8..6e719ffc39f 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_NET -#define MII_OPMODE_STRAP_OVERRIDE 0x16 -#define MII_PHY_CTRL1 0x1e -#define MII_PHY_CTRL2 0x1f - -int fecmxc_mii_postcall(int phy) -{ - miiphy_write("FEC1", phy, MII_BMCR, 0x9000); - miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); - if (phy == 3) - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); - return 0; -} - int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis) return -EINVAL; } - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - puts("FEC MXS: Unable to register FEC0 mii postcall\n"); - return ret; - } - dev = eth_get_dev_by_name("FEC1"); if (!dev) { puts("FEC MXS: Unable to get FEC1 device entry\n"); return -EINVAL; } - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - puts("FEC MXS: Unable to register FEC1 mii postcall\n"); - return ret; - } - return ret; } diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S index 5c18bc19648..29720658225 100644 --- a/board/freescale/mx31ads/lowlevel_init.S +++ b/board/freescale/mx31ads/lowlevel_init.S @@ -246,8 +246,8 @@ lowlevel_init: /* COSR */ str r1, [r0, #0x1c] - /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */ -/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ + /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ +/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ /* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 7a0682a7e96..a94701cbf17 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -60,6 +60,14 @@ int dram_init(void) return 0; } +u32 get_board_rev(void) +{ + u32 rev = get_cpu_rev(); + if (!gpio_get_value(IMX_GPIO_NR(1, 22))) + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; +} + static void setup_iomux_uart(void) { unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 8f821255902..65432099a1e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -394,7 +394,7 @@ static int power_init(void) static void clock_1GHz(void) { int ret; - u32 ref_clk = CONFIG_SYS_MX5_HCLK; + u32 ref_clk = MXC_HCLK; /* * After increasing voltage to 1.25V, we can switch * CPU clock to 1GHz and DDR to 400MHz safely diff --git a/board/freescale/mx6qsabreauto/Makefile b/board/freescale/mx6qsabreauto/Makefile new file mode 100644 index 00000000000..f5528b3045c --- /dev/null +++ b/board/freescale/mx6qsabreauto/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx6qsabreauto.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg new file mode 100644 index 00000000000..d909aa8208f --- /dev/null +++ b/board/freescale/mx6qsabreauto/imximage.cfg @@ -0,0 +1,159 @@ +# Copyright (C) 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register +DATA 4 0x020e05a8 0x00000028 +DATA 4 0x020e05b0 0x00000028 +DATA 4 0x020e0524 0x00000028 +DATA 4 0x020e051c 0x00000028 + +DATA 4 0x020e0518 0x00000028 +DATA 4 0x020e050c 0x00000028 +DATA 4 0x020e05b8 0x00000028 +DATA 4 0x020e05c0 0x00000028 + +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 + +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 + +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 + +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e0590 0x00000030 +DATA 4 0x020e0598 0x00000030 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e0788 0x00000028 + +DATA 4 0x020e0794 0x00000028 +DATA 4 0x020e079c 0x00000028 +DATA 4 0x020e07a0 0x00000028 +DATA 4 0x020e07a4 0x00000028 + +DATA 4 0x020e07a8 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00001740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x8A8F7975 +DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x008F0E21 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x09408030 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00000007 +DATA 4 0x021b4818 0x00000007 + +# Calibration values based on ARD and 528MHz +DATA 4 0x021b083c 0x434B0358 +DATA 4 0x021b0840 0x033D033C +DATA 4 0x021b483c 0x03520362 +DATA 4 0x021b4840 0x03480318 +DATA 4 0x021b0848 0x41383A3C +DATA 4 0x021b4848 0x3F3C374A +DATA 4 0x021b0850 0x42434444 +DATA 4 0x021b4850 0x4932473A + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b0004 0x00025576 + +DATA 4 0x021b001c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c new file mode 100644 index 00000000000..fcd83dc59b9 --- /dev/null +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6x_pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t uart4_pads[] = { + MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t enet_pads[] = { + MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +iomux_v3_cfg_t usdhc3_pads[] = { + MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + gpio_direction_input(IMX_GPIO_NR(6, 15)); + return !gpio_get_value(IMX_GPIO_NR(6, 15)); +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return 0; +} + +u32 get_board_rev(void) +{ + return 0x63000; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6Q-Sabreauto\n"); + + return 0; +} diff --git a/board/freescale/mx6qsabresd/Makefile b/board/freescale/mx6qsabresd/Makefile new file mode 100644 index 00000000000..569377260a6 --- /dev/null +++ b/board/freescale/mx6qsabresd/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx6qsabresd.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c new file mode 100644 index 00000000000..03a68573235 --- /dev/null +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6x_pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t uart1_pads[] = { + MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t enet_pads[] = { + MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8031 PHY Reset */ + MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); +} + +iomux_v3_cfg_t usdhc3_pads[] = { + MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + gpio_direction_input(IMX_GPIO_NR(2, 0)); + return !gpio_get_value(IMX_GPIO_NR(2, 0)); +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return 0; +} + +u32 get_board_rev(void) +{ + return 0x63000; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6Q-SabreSD\n"); + + return 0; +} diff --git a/board/gth2/Makefile b/board/friendlyarm/mini2440/Makefile index 77965fbba68..b88e5690749 100644 --- a/board/gth2/Makefile +++ b/board/friendlyarm/mini2440/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2005-2006 +# (C) Copyright 2012 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o ee_access.o -SOBJS = lowlevel_init.o +COBJS := mini2440.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 00000000000..e97d981cab1 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * (C) Copyright 2009 + * Michel Pollet <buserror@gmail.com> + * + * (C) Copyright 2012 + * Gabriel Huau <contact@huau-gabriel.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/s3c2440.h> +#include <asm/arch/iomux.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <netdev.h> +#include "mini2440.h" + +DECLARE_GLOBAL_DATA_PTR; + +static inline void pll_delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +int board_early_init_f(void) +{ + struct s3c24x0_clock_power * const clk_power = + s3c24x0_get_base_clock_power(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ + clk_power->clkdivn = CLKDIVN_VAL; + + /* configure UPLL */ + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + /* some delay between MPLL and UPLL */ + pll_delay(100); + + /* configure MPLL */ + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + pll_delay(10000); + + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); + + /* IOMUX Port H : UART Configuration */ + gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | + IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; + + gpio_direction_output(GPH8, 0); + gpio_direction_output(GPH9, 0); + gpio_direction_output(GPH10, 0); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; + + return 0; +} + +int dram_init(void) +{ + struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); + + /* + * Configuring bus width and timing + * Initialize clocks for each bank 0..5 + * Bank 3 and 4 are used for DM9000 + */ + writel(BANK_CONF, &memctl->bwscon); + writel(B0_CONF, &memctl->bankcon[0]); + writel(B1_CONF, &memctl->bankcon[1]); + writel(B2_CONF, &memctl->bankcon[2]); + writel(B3_CONF, &memctl->bankcon[3]); + writel(B4_CONF, &memctl->bankcon[4]); + writel(B5_CONF, &memctl->bankcon[5]); + + /* Bank 6 and 7 are used for DRAM */ + writel(SDRAM_64MB, &memctl->bankcon[6]); + writel(SDRAM_64MB, &memctl->bankcon[7]); + + writel(MEM_TIMING, &memctl->refresh); + writel(BANKSIZE_CONF, &memctl->banksize); + writel(B6_MRSR, &memctl->mrsrb6); + writel(B7_MRSR, &memctl->mrsrb7); + + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_DM9000 + return dm9000_initialize(bis); +#else + return 0; +#endif +} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h new file mode 100644 index 00000000000..db386eac01f --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.h @@ -0,0 +1,144 @@ +#ifndef __MINI2440_BOARD_CONF_H__ +#define __MINI2440_BOARD_CONF_H__ + +/* PLL Parameters */ +#define CLKDIVN_VAL 7 +#define M_MDIV 0x7f +#define M_PDIV 0x2 +#define M_SDIV 0x1 + +#define U_M_MDIV 0x38 +#define U_M_PDIV 0x2 +#define U_M_SDIV 0x2 + +/* BWSCON */ +#define DW8 0x0 +#define DW16 0x1 +#define DW32 0x2 +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16 + WAIT + UBLB) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* + * Bank Configuration + */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 /* 0clk */ +#define B0_PMC 0x0 /* normal */ + +#define B1_Tacs 0x0 +#define B1_Tcos 0x0 +#define B1_Tacc 0x7 +#define B1_Tcoh 0x0 +#define B1_Tah 0x0 +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x3 /* 4clk */ +#define B3_Tacp 0x0 +#define B3_PMC 0x0 + +#define B4_Tacs 0x0 +#define B4_Tcos 0x3 +#define B4_Tacc 0x7 +#define B4_Tcoh 0x1 +#define B4_Tah 0x3 +#define B4_Tacp 0x0 +#define B4_PMC 0x0 + +#define B5_Tacs 0x0 +#define B5_Tcos 0x0 +#define B5_Tacc 0x7 +#define B5_Tcoh 0x0 +#define B5_Tah 0x0 +#define B5_Tacp 0x0 +#define B5_PMC 0x0 + +/* + * SDRAM Configuration + */ +#define SDRAM_MT 0x3 /* SDRAM */ +#define SDRAM_Trcd 0x0 /* 2clk */ +#define SDRAM_SCAN_9 0x1 /* 9bit */ +#define SDRAM_SCAN_10 0x2 /* 10bit */ + +#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) + +/* + * Refresh Parameter + */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x1 /* 3clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x0 /* unused */ +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ + +/* + * MRSR Parameter + */ +#define BL 0x0 +#define BT 0x0 +#define CL 0x3 /* 3 clocks */ +#define TM 0x0 +#define WBL 0x0 + +/* + * BankSize Parameter + */ +#define BK76MAP 0x2 /* 128MB/128MB */ +#define SCLK_EN 0x1 /* SCLK active */ +#define SCKE_EN 0x1 /* SDRAM power down mode enable */ +#define BURST_EN 0x1 /* Burst enable */ + +/* + * Register values + */ +#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ + (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \ + (B7_BWSCON<<28))) + +#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ + (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) +#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ + (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) +#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ + (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) +#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ + (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) +#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ + (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) +#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ + (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) + +#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ + (Trc<<18) + (Tchr<<16) + REFCNT + +#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) +#define B6_MRSR (CL<<4) +#define B7_MRSR (CL<<4) + +#endif diff --git a/board/gth2/config.mk b/board/gth2/config.mk deleted file mode 100644 index c9050492ec0..00000000000 --- a/board/gth2/config.mk +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2004-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# AMD Alchemy AU1000, MIPS32 core -# - -ifeq ($(TBASE),0) -CONFIG_SYS_TEXT_BASE = 0 -else -ifeq ($(TBASE),1) -CONFIG_SYS_TEXT_BASE = 0xbfc10070 -else -ifeq ($(TBASE),2) -CONFIG_SYS_TEXT_BASE = 0xbfc30070 -else -## Only to make ordinary make work -CONFIG_SYS_TEXT_BASE = 0x90000000 -endif -endif -endif diff --git a/board/gth2/ee_access.c b/board/gth2/ee_access.c deleted file mode 100644 index d4798c4ba3f..00000000000 --- a/board/gth2/ee_access.c +++ /dev/null @@ -1,347 +0,0 @@ -/* Module for handling DALLAS DS2438, smart battery monitor - Chip can store up to 40 bytes of user data in EEPROM, - perform temp, voltage and current measurements. - Chip also contains a unique serial number. - - Always read/write LSb first - - For documentaion, see data sheet for DS2438, 2438.pdf - - By Thomas.Lange@corelatus.com 001025 - - Copyright (C) 2000-2005 Corelatus AB */ - -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/au1x00.h> -#include <asm/io.h> -#include "ee_dev.h" -#include "ee_access.h" - -/* static int Debug = 1; */ -#undef E_DEBUG -#define E_DEBUG(fmt,args...) /* */ -/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */ - -/* We dont have kernel functions */ -#define printk printf -#define KERN_DEBUG -#define KERN_ERR -#define EIO 1 - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */ - -static u8 crc_lookup[256] = { - 0, 94, 188, 226, 97, 63, 221, 131, - 194, 156, 126, 32, 163, 253, 31, 65, - 157, 195, 33, 127, 252, 162, 64, 30, - 95, 1, 227, 189, 62, 96, 130, 220, - 35, 125, 159, 193, 66, 28, 254, 160, - 225, 191, 93, 3, 128, 222, 60, 98, - 190, 224, 2, 92, 223, 129, 99, 61, - 124, 34, 192, 158, 29, 67, 161, 255, - 70, 24, 250, 164, 39, 121, 155, 197, - 132, 218, 56, 102, 229, 187, 89, 7, - 219, 133, 103, 57, 186, 228, 6, 88, - 25, 71, 165, 251, 120, 38, 196, 154, - 101, 59, 217, 135, 4, 90, 184, 230, - 167, 249, 27, 69, 198, 152, 122, 36, - 248, 166, 68, 26, 153, 199, 37, 123, - 58, 100, 134, 216, 91, 5, 231, 185, - 140, 210, 48, 110, 237, 179, 81, 15, - 78, 16, 242, 172, 47, 113, 147, 205, - 17, 79, 173, 243, 112, 46, 204, 146, - 211, 141, 111, 49, 178, 236, 14, 80, - 175, 241, 19, 77, 206, 144, 114, 44, - 109, 51, 209, 143, 12, 82, 176, 238, - 50, 108, 142, 208, 83, 13, 239, 177, - 240, 174, 76, 18, 145, 207, 45, 115, - 202, 148, 118, 40, 171, 245, 23, 73, - 8, 86, 180, 234, 105, 55, 213, 139, - 87, 9, 235, 181, 54, 104, 138, 212, - 149, 203, 41, 119, 244, 170, 72, 22, - 233, 183, 85, 11, 136, 214, 52, 106, - 43, 117, 151, 201, 74, 20, 246, 168, - 116, 42, 200, 150, 21, 75, 169, 247, - 182, 232, 10, 84, 215, 137, 107, 53 -}; - -static void -write_gpio_data(int value ){ - if(value){ - /* Tristate */ - gpio_tristate(GPIO_EEDQ); - } - else{ - /* Drive 0 */ - gpio_clear(GPIO_EEDQ); - } -} - -static u8 make_new_crc( u8 Old_crc, u8 New_value ){ - /* Compute a new checksum with new byte, using previous checksum as input - See DS app note 17, understanding and using cyclic redundancy checks... - Also see DS2438, page 11 */ - return( crc_lookup[Old_crc ^ New_value ]); -} - -int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ - /* Check if the checksum for this buffer is correct */ - u8 Curr_crc=0; - int i; - u8 *Curr_byte = Buffer; - - for(i=0;i<Len;i++){ - Curr_crc = make_new_crc( Curr_crc, *Curr_byte); - Curr_byte++; - } - E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); - - if(Curr_crc == Crc){ - /* Good */ - return(TRUE); - } - printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc); - return(FALSE); -} - -static void -set_idle(void){ - /* Send idle and keep start time - Continous 1 is idle */ - WRITE_PORT(1); -} - - -static int -do_cpu_reset(void){ - /* Release reset and verify that chip responds with presence pulse */ - int Retries=0; - while(Retries<15){ - udelay(RESET_LOW_TIME); - - /* Send reset */ - WRITE_PORT(0); - udelay(RESET_LOW_TIME); - - /* Release reset */ - WRITE_PORT(1); - - /* Wait for EEPROM to drive output */ - udelay(PRESENCE_TIMEOUT); - if(!READ_PORT){ - /* Ok, EEPROM is driving a 0 */ - E_DEBUG("Presence detected\n"); - if(Retries){ - E_DEBUG("Retries %d\n",Retries); - } - /* Make sure chip releases pin */ - udelay(PRESENCE_LOW_TIME); - return 0; - } - Retries++; - } - - printk(KERN_ERR"eeprom did not respond when releasing reset\n"); - - /* Make sure chip releases pin */ - udelay(PRESENCE_LOW_TIME); - - /* Set to idle again */ - set_idle(); - - return(-EIO); -} - -static u8 -read_cpu_byte(void){ - /* Read a single byte from EEPROM - Read LSb first */ - int i; - int Value; - u8 Result=0; - u32 Flags; - - E_DEBUG("Reading byte\n"); - - for(i=0;i<8;i++){ - /* Small delay between pulses */ - udelay(1); - -#ifdef __KERNEL__ - /* Disable irq */ - save_flags(Flags); - cli(); -#endif - - /* Pull down pin short time to start read - See page 26 in data sheet */ - - WRITE_PORT(0); - udelay(READ_LOW); - WRITE_PORT(1); - - /* Wait for chip to drive pin */ - udelay(READ_TIMEOUT); - - Value = READ_PORT; - if(Value) - Value=1; - -#ifdef __KERNEL__ - /* Enable irq */ - restore_flags(Flags); -#endif - - /* Wait for chip to release pin */ - udelay(TOTAL_READ_LOW-READ_TIMEOUT); - - /* LSb first */ - Result|=Value<<i; - /* E_DEBUG("Read %d\n",Value); */ - - } - - E_DEBUG("Read byte 0x%x\n",Result); - - return(Result); -} - -static void -write_cpu_byte(u8 Byte){ - /* Write a single byte to EEPROM - Write LSb first */ - int i; - int Value; - u32 Flags; - - E_DEBUG("Writing byte 0x%x\n",Byte); - - for(i=0;i<8;i++){ - /* Small delay between pulses */ - udelay(1); - Value = Byte&1; - -#ifdef __KERNEL__ - /* Disable irq */ - save_flags(Flags); - cli(); -#endif - - /* Pull down pin short time for a 1, long time for a 0 - See page 26 in data sheet */ - - WRITE_PORT(0); - if(Value){ - /* Write a 1 */ - udelay(WRITE_1_LOW); - } - else{ - /* Write a 0 */ - udelay(WRITE_0_LOW); - } - - WRITE_PORT(1); - -#ifdef __KERNEL__ - /* Enable irq */ - restore_flags(Flags); -#endif - - if(Value) - /* Wait for chip to read the 1 */ - udelay(TOTAL_WRITE_LOW-WRITE_1_LOW); - - /* E_DEBUG("Wrote %d\n",Value); */ - Byte>>=1; - } -} - -int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){ - /* Execute this command string, including - giving reset and setting to idle after command - if Rx_len is set, we read out data from EEPROM */ - int i; - - E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len ); - - if(do_cpu_reset()){ - /* Failed! */ - return(-EIO); - } - - if(Send_skip) - /* Always send SKIP_ROM first to tell chip we are sending a command, - except when we read out rom data for chip */ - write_cpu_byte(SKIP_ROM); - - /* Always have Tx data */ - for(i=0;i<Tx_len;i++){ - write_cpu_byte(Tx[i]); - } - - if(Rx_len){ - for(i=0;i<Rx_len;i++){ - Rx[i]=read_cpu_byte(); - } - } - - set_idle(); - - E_DEBUG("Command done\n"); - - return(0); -} - -int ee_init_cpu_data(void){ - int i; - u8 Tx[10]; - - /* Leave it floting since altera is driving the same pin */ - set_idle(); - - /* Copy all User EEPROM data to scratchpad */ - for(i=0;i<USER_PAGES;i++){ - Tx[0]=RECALL_MEMORY; - Tx[1]=EE_USER_PAGE_0+i; - if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); - } - - /* Make sure chip doesnt store measurements in NVRAM */ - Tx[0]=WRITE_SCRATCHPAD; - Tx[1]=0; /* Page */ - Tx[2]=9; - if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO); - - Tx[0]=COPY_SCRATCHPAD; - if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO); - - for(i=0;i<10;i++){ - udelay(1000); - } - - return(0); -} diff --git a/board/gth2/ee_access.h b/board/gth2/ee_access.h deleted file mode 100644 index 926199de3cc..00000000000 --- a/board/gth2/ee_access.h +++ /dev/null @@ -1,30 +0,0 @@ -/* By Thomas.Lange@Corelatus.com 001025 */ - -/* Definitions for EEPROM/VOLT METER DS2438 */ -/* Copyright (C) 2000-2005 Corelatus AB */ - -#ifndef INCeeaccessh -#define INCeeaccessh - -#include <asm/types.h> -#include "ee_dev.h" - -int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ); -int ee_init_cpu_data(void); - -int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ); - -/* Defs for altera reg */ -#define EE_WRITE_SHIFT 8 /* bits to shift left */ -#define EE_READ_SHIFT 16 /* bits to shift left */ -#define EE_DONE 0x80000000 -#define EE_BUSY 0x40000000 -#define EE_ERROR 0x20000000 - -/* Commands */ -#define EE_CMD_NOP 0 -#define EE_CMD_INIT_RES 1 -#define EE_CMD_WR_BYTE 2 -#define EE_CMD_RD_BYTE 3 - -#endif /* INCeeaccessh */ diff --git a/board/gth2/ee_dev.h b/board/gth2/ee_dev.h deleted file mode 100644 index 89ef2f82c89..00000000000 --- a/board/gth2/ee_dev.h +++ /dev/null @@ -1,96 +0,0 @@ -/* By Thomas.Lange@Corelatus.com 001025 */ -/* Definitions for EEPROM/VOLT METER DS2438 */ -/* Copyright (C) 2000-2005 Corelatus AB */ - -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef INCeedevh -#define INCeedevh - -#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) - -/* MIPS */ -#define WRITE_PORT(Value) write_gpio_data(Value) - -#define READ_PORT (gpio_read()&GPIO_EEDQ) - -/* 64 bytes chip */ -#define EE_CHIP_SIZE 64 - -/* Board with new current resistor */ -#define EE_GTH_0304 1 - -/* new dsp and 64 MB SDRAM */ -#define EE_DSP_64 0x10 - -/* microsecs */ -/* Pull line down at least this long for reset pulse */ -#define RESET_LOW_TIME 490 - -/* Read presence pulse after we release reset pulse */ -#define PRESENCE_TIMEOUT 100 -#define PRESENCE_LOW_TIME 200 - -#define WRITE_0_LOW 60 -#define WRITE_1_LOW 1 -#define TOTAL_WRITE_LOW 60 - -#define READ_LOW 1 -#define READ_TIMEOUT 10 -#define TOTAL_READ_LOW 70 - -/* Rom function commands */ -#define READ_ROM 0x33 -#define MATCH_ROM 0x55 -#define SKIP_ROM 0xCC -#define SEARCH_ROM 0xF0 - - -/* Memory_command_function */ -#define WRITE_SCRATCHPAD 0x4E -#define READ_SCRATCHPAD 0xBE -#define COPY_SCRATCHPAD 0x48 -#define RECALL_MEMORY 0xB8 -#define CONVERT_TEMP 0x44 -#define CONVERT_VOLTAGE 0xB4 - -/* Chip is divided in 8 pages, 8 bytes each */ - -#define EE_PAGE_SIZE 8 - -/* All chip data we want are in page 0 */ - -/* Bytes in page 0 */ -#define EE_P0_STATUS 0 -#define EE_P0_TEMP_LSB 1 -#define EE_P0_TEMP_MSB 2 -#define EE_P0_VOLT_LSB 3 -#define EE_P0_VOLT_MSB 4 -#define EE_P0_CURRENT_LSB 5 -#define EE_P0_CURRENT_MSB 6 - - -/* 40 byte user data is located at page 3-7 */ -#define EE_USER_PAGE_0 3 -#define USER_PAGES 5 - -/* Layout of gth user pages usage */ -/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */ - -#define EE_ETHERNET_OFFSET 0 - -#endif /* INCeedevh */ diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c deleted file mode 100644 index 8c3b55af429..00000000000 --- a/board/gth2/gth2.c +++ /dev/null @@ -1,437 +0,0 @@ -/* - * (C) Copyright 2005 - * Thomas.Lange@corelatus.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/au1x00.h> -#include <asm/addrspace.h> -#include <asm/mipsregs.h> -#include <asm/io.h> -#include <watchdog.h> - -#include "ee_access.h" - -static int wdi_status = 0; - -#define SDRAM_SIZE ((64*1024*1024)-(12*4096)) - - -#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096)) - -void inline log_serial_char(char c){ - char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; - int serial_log_offset; - u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; - - serial_log_offset = *serial_log_offsetp; - - *(serial_log_buffer + serial_log_offset) = c; - - serial_log_offset++; - - if(serial_log_offset >= 4096){ - serial_log_offset = 4; - } - *serial_log_offsetp = serial_log_offset; -} - -void init_log_serial(void){ - char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; - u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER; - - /* Copy buffer from last run */ - memcpy(serial_log_buffer + 4096, - serial_log_buffer, - 4096); - - memset(serial_log_buffer, 0, 4096); - - *serial_log_offsetp = 4; -} - - -void hw_watchdog_reset(void){ - volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; - volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR; - if(wdi_status){ - *sys_outputset = GPIO_CPU_LED|GPIO_WDI; - wdi_status = 0; - } - else{ - *sys_outputclear = GPIO_CPU_LED|GPIO_WDI; - wdi_status = 1; - } -} - -phys_size_t initdram(int board_type) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - - WATCHDOG_RESET(); - - return (SDRAM_SIZE); -} - -/* In arch/mips/cpu/cpu.c */ -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); - -void set_ledcard(u32 value){ - /* Clock 24 bits to led card */ - int i; - volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; - volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR; - - /* Start with known values */ - *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD; - - for(i=0;i<24;i++){ - if(value&0x00800000){ - *sys_outputset = GPIO_LEDD; - } - else{ - *sys_outputclr = GPIO_LEDD; - } - udelay(1); - *sys_outputset = GPIO_LEDCLK; - udelay(1); - *sys_outputclr = GPIO_LEDCLK; - udelay(1); - - value<<=1; - } - /* Data is enable output */ - *sys_outputset = GPIO_LEDD; -} - -int checkboard (void) -{ - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; - volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET; - volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR; - u32 proc_id; - - WATCHDOG_RESET(); - - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - - proc_id = read_c0_prid(); - - switch (proc_id >> 24) { - case 0: - puts ("Board: GTH2\n"); - printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - default: - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); - } - - set_io_port_base(0); - -#ifdef CONFIG_IDE_PCMCIA - /* PCMCIA is on a 36 bit physical address. - We need to map it into a 32 bit addresses */ - write_one_tlb(20, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ - 0x3C000017, /* Lo0 */ - 0x3C200017); /* Lo1 */ - - write_one_tlb(21, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ - 0x3D000017, /* Lo0 */ - 0x3D200017); /* Lo1 */ - - write_one_tlb(22, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ - 0x3E000017, /* Lo0 */ - 0x3E200017); /* Lo1 */ - -#endif /* CONFIG_IDE_PCMCIA */ - - /* Wait for GPIO ports to become stable */ - udelay(5000); /* FIXME */ - - /* Release reset of ethernet PHY chips */ - /* Always do this, because linux does not know about it */ - *sys_outputset = GPIO_ERESET; - - /* Kill FPGA:s */ - *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG; - udelay(2); - *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG; - - /* Turn front led yellow */ - set_ledcard(0x00100000); - - return 0; -} - -#define POWER_OFFSET 0xF0000 -#define SW_WATCHDOG_REASON 13 - -#define BOOTDATA_OFFSET 0xF8000 -#define MAX_ATTEMPTS 5 - -#define FAILSAFE_BOOT 1 -#define SYSTEM_BOOT 2 -#define SYSTEM2_BOOT 3 - -#define WRITE_FLASH16(a, d) \ -do \ -{ \ - *((volatile u16 *) (a)) = (d);\ - } while(0) - -static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) -{ - u16 data; - volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE); - - switch(System){ - case FAILSAFE_BOOT: - printf ("Setting failsafe boot in flash\n"); - break; - case SYSTEM_BOOT: - printf ("Setting system boot in flash\n"); - break; - case SYSTEM2_BOOT: - printf ("Setting system2 boot in flash\n"); - break; - default: - printf ("Invalid system data %u, setting failsafe\n", System); - System = FAILSAFE_BOOT; - } - - if ((Count < 1) | (Count > MAX_ATTEMPTS)) { - printf ("Invalid boot count %u, setting 1\n", Count); - Count = 1; - } - - printf ("Boot attempt %d\n", Count); - - data = (System << 8) | Count; - /* AMD 16 bit */ - WRITE_FLASH16 (&flash[0x555], 0xAAAA); - WRITE_FLASH16 (&flash[0x2AA], 0x5555); - WRITE_FLASH16 (&flash[0x555], 0xA0A0); - - WRITE_FLASH16 (addr, data); -} - -static int random_system(void){ - /* EEPROM read failed. Just try to choose one - system release and hope it works */ - - /* FIXME */ - return(SYSTEM_BOOT); -} - -static int switch_system(int old_system){ - u8 Rx[10]; - u8 Tx[5]; - int valid_release; - - if(old_system==FAILSAFE_BOOT){ - /* Find out which system release to use */ - - /* Copy from nvram to scratchpad */ - Tx[0] = RECALL_MEMORY; - Tx[1] = 7; /* Page */ - if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) { - printf ("EE user page 7 recall failed\n"); - return (random_system()); - } - - Tx[0] = READ_SCRATCHPAD; - if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) { - printf ("EE user page 7 read failed\n"); - return (random_system()); - } - /* Crc in 9:th byte */ - if (!ee_crc_ok (Rx, 8, *(Rx + 8))) { - printf ("EE read failed, page 7. CRC error\n"); - return (random_system()); - } - - valid_release = Rx[7]; - if((valid_release==0xFF)| - ((valid_release&1) == 0)){ - return(SYSTEM_BOOT); - } - else{ - return(SYSTEM2_BOOT); - } - } - else{ - return(FAILSAFE_BOOT); - } -} - -static void check_boot_tries (void) -{ - /* Count the number of boot attemps - switch system if too many */ - - int i; - volatile u16 *addr; - volatile u16 data; - u8 system = FAILSAFE_BOOT; - u8 count; - - addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET); - - if (*addr == 0xFFFF) { - printf ("*** No bootdata exists. ***\n"); - write_bootdata (addr, FAILSAFE_BOOT, 1); - } else { - /* Search for latest written bootdata */ - i = 0; - while ((*(addr + 1) != 0xFFFF) & (i < 8000)) { - addr++; - i++; - } - if (i >= 8000) { - /* Whoa, dont write any more */ - printf ("*** No bootdata found. Not updating flash***\n"); - } else { - /* See how many times we have tried to boot real system */ - data = *addr; - system = data >> 8; - count = data & 0xFF; - if ((system != SYSTEM_BOOT) & - (system != SYSTEM2_BOOT) & - (system != FAILSAFE_BOOT)) { - printf ("*** Wrong system %d\n", system); - system = FAILSAFE_BOOT; - count = 1; - } else { - switch (count) { - case 0: - case 1: - case 2: - case 3: - case 4: - /* Try same system again if needed */ - count++; - break; - - case 5: - /* Switch system and reset tries */ - count = 1; - system = switch_system(system); - printf ("***Too many boot attempts, switching system***\n"); - break; - default: - /* Switch system, start over and hope it works */ - printf ("***Unexpected data on addr 0x%x, %u***\n", - (u32) addr, data); - count = 1; - system = switch_system(system); - } - } - write_bootdata (addr + 1, system, count); - } - } - switch(system){ - case FAILSAFE_BOOT: - printf ("Booting failsafe system\n"); - setenv ("bootargs", "panic=1 root=/dev/hda7"); - setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm"); - break; - - case SYSTEM_BOOT: - printf ("Using normal system\n"); - setenv ("bootargs", "panic=1 root=/dev/hda4"); - setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm"); - break; - - case SYSTEM2_BOOT: - printf ("Using normal system2\n"); - setenv ("bootargs", "panic=1 root=/dev/hda9"); - setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm"); - break; - default: - printf ("Invalid system %d\n", system); - printf ("Hanging\n"); - while(1); - } -} - -int misc_init_r(void){ - u8 Rx[80]; - u8 Tx[5]; - int page; - int read = 0; - - WATCHDOG_RESET(); - - if (ee_init_cpu_data ()) { - printf ("EEPROM init failed\n"); - return (0); - } - - /* Check which release to boot */ - check_boot_tries (); - - /* Read the pages where ethernet address is stored */ - - for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) { - /* Copy from nvram to scratchpad */ - Tx[0] = RECALL_MEMORY; - Tx[1] = page; - if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) { - printf ("EE user page %d recall failed\n", page); - return (0); - } - - Tx[0] = READ_SCRATCHPAD; - if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) { - printf ("EE user page %d read failed\n", page); - return (0); - } - /* Crc in 9:th byte */ - if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) { - printf ("EE read failed, page %d. CRC error\n", page); - return (0); - } - read += 8; - } - - /* Add eos after eth addr */ - Rx[17] = 0; - - printf ("Ethernet addr read from eeprom: %s\n\n", Rx); - - if ((Rx[2] != ':') | - (Rx[5] != ':') | - (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { - printf ("*** ethernet addr invalid, using default ***\n"); - } else { - setenv ("ethaddr", (char *)Rx); - } - return (0); -} diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S deleted file mode 100644 index bc31c005312..00000000000 --- a/board/gth2/lowlevel_init.S +++ /dev/null @@ -1,457 +0,0 @@ -/* Memory sub-system initialization code */ - -#include <config.h> -#include <asm/regdef.h> -#include <asm/au1x00.h> -#include <asm/mipsregs.h> - -#define CP0_Config0 $16 -#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000) -#define GPIO_RJ1LY (1<<22) -#define GPIO_CFRESET (1<<10) - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - - /* No workaround if running from ram */ - lui t0, 0xffc0 - lui t3, 0xbfc0 - and t1, ra, t0 - bne t1, t3, noCacheJump - nop - - /*** From AMD YAMON ***/ - /* - * Step 8) Initialize the caches - */ - li t0, (16*1024) - li t1, 32 - li t2, 0x80000000 - addu t3, t0, t2 -cacheloop: - cache 0, 0(t2) - cache 1, 0(t2) - addu t2, t1 - bne t2, t3, cacheloop - nop - - /* Save return address */ - move t3, ra - - /* Run from cacheable space now */ - bal cachehere - nop -cachehere: - li t1, ~0x20000000 /* convert to KSEG0 */ - and t0, ra, t1 - addi t0, 5*4 /* 5 insns beyond cachehere */ - jr t0 - nop - - /* Restore return address */ - move ra, t3 - - /* - * Step 9) Initialize the TLB - */ - li t0, 0 # index value - li t1, 0x00000000 # entryhi value - li t2, 32 # 32 entries - -tlbloop: - /* Probe TLB for matching EntryHi */ - mtc0 t1, CP0_ENTRYHI - tlbp - nop - - /* Examine Index[P], 1=no matching entry */ - mfc0 t3, CP0_INDEX - li t4, 0x80000000 - and t3, t4, t3 - addiu t1, t1, 1 # increment t1 (asid) - beq zero, t3, tlbloop - nop - - /* Initialize the TLB entry */ - mtc0 t0, CP0_INDEX - mtc0 zero, CP0_ENTRYLO0 - mtc0 zero, CP0_ENTRYLO1 - mtc0 zero, CP0_PAGEMASK - tlbwi - - /* Do it again */ - addiu t0, t0, 1 - bne t0, t2, tlbloop - nop - - /* First setup pll:s to make serial work ok */ - /* We have a 12.5 MHz crystal */ - li t0, SYS_CPUPLL - li t1, 0x28 /* CPU clock, 500 MHz */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 0 - sw t1, 0(t0) /* aux pll */ - sync - - /* Static memory controller */ - /* RCE0 - can not change while fetching, do so from icache */ - move t2, ra /* Store return address */ - bal getAddr - nop - -getAddr: - move t1, ra - move ra, t2 /* Move return addess back */ - - cache 0x14,0(t1) - cache 0x14,32(t1) - /*** /From YAMON ***/ - -noCacheJump: - - /* Static memory controller */ - - /* RCE0 AMD 29LV800 Flash */ - li t0, MEM_STCFG0 - li t1, 0x00000243 - sw t1, 0(t0) - - li t0, MEM_STTIME0 - li t1, 0x040181D7 /* FIXME */ - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11E03F80 - sw t1, 0(t0) - - /* RCE1 PCMCIA 250ns */ - li t0, MEM_STCFG1 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10000000 - sw t1, 0(t0) - - /* RCE2 CP Altera */ - li t0, MEM_STCFG2 - li t1, 0x00000280 /* BE, EW */ - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x0303000c - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f80 /* 1 MB */ - sw t1, 0(t0) - - /* RCE3 DP Altera */ - li t0, MEM_STCFG3 - li t1, 0x00000280 /* BE, EW */ - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x0303000c - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10e03f80 /* 1 MB */ - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - -/* SDCS 0 SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x592CD1 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00000000 - sw t1, 0(t0) - -/* 64 MB SDRAM at addr 0 */ - li t0, MEM_SDADDR0 - li t1, 0x001003F0 - sw t1, 0(t0) - - - li t0, MEM_SDADDR1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x00000000 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x880007A1 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x8A0007A1 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - /* Setup GPIO pins */ - - li t0, SYS_PINFUNC - li t1, 0x00007025 /* 0x8080 */ - sw t1, 0(t0) - - li t0, SYS_TRIOUTCLR - li t1, 0xFFFFFFFF /* 0x1FFF */ - sw t1, 0(t0) - - /* Turn yellow front led on */ - /* Release reset on CF */ - li t0, SYS_OUTPUTCLR - li t1, GPIO_RJ1LG - sw t1, 0(t0) - li t0, SYS_OUTPUTSET - li t1, GPIO_RJ1LY|GPIO_CFRESET - sw t1, 0(t0) - sync - j clearmem - nop - -#if 0 - .globl memtest -#endif -memtest: - /* Fill memory with address */ - li t0, 0x80000000 - li t1, 0xFFF000 /* 64 MB */ -mt0: sw t0, 0(t0) - add t1, -1 - add t0, 4 - bne t1, zero, mt0 - nop - nop - /* Verify addr */ - li t0, 0x80000000 - li t1, 0xFFF000 /* 64 MB */ -mt1: lw t2, 0(t0) - bne t0, t2, memhang - add t1, -1 - add t0, 4 - bne t1, zero, mt1 - nop - nop -#if 0 - .globl clearmem -#endif -clearmem: - /* Clear memory */ - li t0, 0x80000000 - li t1, 0xFFF000 /* 64 MB */ -mtc: sw zero, 0(t0) - add t1, -1 - add t0, 4 - bne t1, zero, mtc - nop - nop -memtestend: - jr ra - nop - -memhang: - b memhang - nop diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds deleted file mode 100644 index 9fc417f3bca..00000000000 --- a/board/gth2/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - .sdata : { *(.sdata*) } - - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss*) } - .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } - uboot_end = .; -} diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c index 02e75edb402..143fcefedf5 100644 --- a/board/hale/tt01/tt01.c +++ b/board/hale/tt01/tt01.c @@ -52,7 +52,7 @@ static void board_setup_clocks(void) writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); /* Set up clock to 532MHz */ - writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0), &ccm->pdr0); diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 454ff0a8468..7c9d34ab842 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -46,12 +46,12 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(void) +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata); + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); } -int ehci_hcd_stop(void) +int ehci_hcd_stop(int index) { return omap_ehci_hcd_stop(); } diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S index c47137d097a..4dd78b660a4 100644 --- a/board/imx31_phycore/lowlevel_init.S +++ b/board/imx31_phycore/lowlevel_init.S @@ -54,7 +54,7 @@ lowlevel_init: REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) + REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile new file mode 100644 index 00000000000..f77fcfb9901 --- /dev/null +++ b/board/iomega/iconnect/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := iconnect.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c new file mode 100644 index 00000000000..6ee2128aab8 --- /dev/null +++ b/board/iomega/iconnect/iconnect.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik@neratec.com> + * Luka Perkov <uboot@lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "iconnect.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, /* Reset signal */ + MPP7_GPO, + MPP8_TW_SDA, /* I2C */ + MPP9_TW_SCK, /* I2C */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* Reset button */ + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GPIO, /* OTB button */ + MPP36_AUDIO_SPDIFI, + MPP37_AUDIO_SPDIFO, + MPP38_GPIO, + MPP39_TDM_SPI_CS0, + MPP40_TDM_SPI_SCK, + MPP41_GPIO, /* LED brightness */ + MPP42_GPIO, /* LED power (blue) */ + MPP43_GPIO, /* LED power (red) */ + MPP44_GPIO, /* LED USB 1 */ + MPP45_GPIO, /* LED USB 2 */ + MPP46_GPIO, /* LED USB 3 */ + MPP47_GPIO, /* LED USB 4 */ + MPP48_GPIO, /* LED OTB */ + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h new file mode 100644 index 00000000000..2fb3e5ed8f2 --- /dev/null +++ b/board/iomega/iconnect/iconnect.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik@neratec.com> + * Luka Perkov <uboot@lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ICONNECT_H +#define __ICONNECT_H + +#define ICONNECT_OE_LOW (~(1 << 7)) +#define ICONNECT_OE_HIGH (~(1 << 10)) +#define ICONNECT_OE_VAL_LOW (0) +#define ICONNECT_OE_VAL_HIGH (1 << 10) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __ICONNECT_H */ diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg new file mode 100644 index 00000000000..6c9dfe3d31d --- /dev/null +++ b/board/iomega/iconnect/kwbimage.cfg @@ -0,0 +1,165 @@ +# +# (C) Copyright 2009-2012 +# Wojciech Dubowik <wojciech.dubowik@neratec.com> +# Luka Perkov <uboot@lukaperkov.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) +# bit23-14: 0x0, +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required +# bit29-26: 0x0, +# bit31-30: 0x1, + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit4: 0x0, addr/cmd in smame cycle +# bit5: 0x0, clk is driven during self refresh, we don't care for APX +# bit6: 0x0, use recommended falling edge of clk for addr/cmd +# bit14: 0x0, input buffer always powered up +# bit18: 0x1, cpu lock transaction enabled +# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 0x3, required +# bit31: 0x0, no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11-8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: 0x0, required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width (x8) +# bit3-2: 11, Cs0size (1Gb) +# bit5-4: 00, Cs1width (x8) +# bit7-6: 11, Cs1size (1Gb) +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0x0, required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0x0, required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0x0, required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 0x2, BurstLen=2 required +# bit3: 0x0, BurstType=0 required +# bit6-4: 0x4, CL=5 +# bit7: 0x0, TestMode=0 normal +# bit8: 0x0, DLL reset=0 normal +# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit12: 0x0, PD must be zero +# bit31-13: 0x0, required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 0x0, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 0x0, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0x0, required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 0x7, required +# bit3: 0x1, MBUS Burst Chop disabled +# bit6-4: 0x7, required +# bit7: 0x0, +# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0x0, no half clock cycle addition to dataout +# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf, required +# bit31-16: 0x0, required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 0x1, Window enabled +# bit1: 0x0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above +# bit3-2: 0x1, ODT1 active NEVER! +# bit31-4: 0x0, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +# bit0: 0x1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S index 823df10701e..3e46ed9774f 100644 --- a/board/karo/tx25/lowlevel_init.S +++ b/board/karo/tx25/lowlevel_init.S @@ -22,37 +22,7 @@ */ #include <asm/macro.h> - -.macro init_aips - write32 0x43f00000, 0x77777777 - write32 0x43f00004, 0x77777777 - write32 0x43f00000, 0x77777777 - write32 0x53f00004, 0x77777777 -.endm - -.macro init_max - write32 0x43f04000, 0x43210 - write32 0x43f04100, 0x43210 - write32 0x43f04200, 0x43210 - write32 0x43f04300, 0x43210 - write32 0x43f04400, 0x43210 - - write32 0x43f04010, 0x10 - write32 0x43f04110, 0x10 - write32 0x43f04210, 0x10 - write32 0x43f04310, 0x10 - write32 0x43f04410, 0x10 - - write32 0x43f04800, 0x0 - write32 0x43f04900, 0x0 - write32 0x43f04a00, 0x0 - write32 0x43f04b00, 0x0 - write32 0x43f04c00, 0x0 -.endm - -.macro init_m3if - write32 0xb8003000, 0x1 -.endm +#include <asm/arch/macro.h> .macro init_clocks /* @@ -64,9 +34,19 @@ * 0x00600000 makes CLKO parent clk the USB clk */ write32 0x53f80064, 0x45600000 + + /* CCTL: ARM = 399 MHz, AHB = 133 MHz */ write32 0x53f80008, 0x20034000 /* + * PCDR2: NFC = 33.25 MHz + * This is required for the NAND Flash of this board, which is a Samsung + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with + * the NFC driver in symmetric (i.e. one-cycle) mode. + */ + write32 0x53f80020, 0x01010103 + + /* * enable all implemented clocks in all three * clock control registers */ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index be8f51c2fc4..0c4dddc6173 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -250,7 +250,8 @@ int board_early_init_f(void) tmp = readl(KW_GPIO0_BASE + 4); writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); #endif - + /* adjust SDRAM size for bank 0 */ + kw_sdram_size_adjust(0); kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -365,6 +366,71 @@ void reset_phy(void) /* reset the phy */ miiphy_reset(name, CONFIG_PHY_BASE_ADR); } +#elif defined(CONFIG_KM_PIGGY4_88E6352) + +#include <mv88e6352.h> + +#if defined(CONFIG_KM_NUSA) +struct mv88e_sw_reg extsw_conf[] = { + /* + * port 0, PIGGY4, autoneg + * first the fix for the 1000Mbits Autoneg, this is from + * a Marvell errata, the regs are undocumented + */ + { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, + { PHY(0), PHY_STATUS, AN1000FIX }, + { PHY(0), PHY_PAGE, 0 }, + /* now the real port and phy configuration */ + { PORT(0), PORT_PHY, NO_SPEED_FOR }, + { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(0), PHY_1000_CTRL, NO_ADV }, + { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, + { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | + FULL_DUPLEX }, + /* port 1, unused */ + { PORT(1), PORT_CTRL, PORT_DIS }, + { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 2, unused */ + { PORT(2), PORT_CTRL, PORT_DIS }, + { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 3, unused */ + { PORT(3), PORT_CTRL, PORT_DIS }, + { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 4, ICNEV, SerDes, SGMII */ + { PORT(4), PORT_STATUS, NO_PHY_DETECT }, + { PORT(4), PORT_PHY, SPEED_1000_FOR }, + { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, + { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, + /* port 5, CPU_RGMII */ + { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | + FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | + FULL_DPX_FOR | SPEED_1000_FOR }, + { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, + /* port 6, unused, this port has no phy */ + { PORT(6), PORT_CTRL, PORT_DIS }, +}; +#else +struct mv88e_sw_reg extsw_conf[] = {}; +#endif + +void reset_phy(void) +{ +#if defined(CONFIG_KM_MVEXTSW_ADDR) + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, + ARRAY_SIZE(extsw_conf)); + mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); +#endif +} + #else /* Configure and enable MV88E1118 PHY on the piggy*/ void reset_phy(void) diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile new file mode 100644 index 00000000000..bae79f50881 --- /dev/null +++ b/board/kmc/kzm9g/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +# (C) Copyright 2012 Renesas Solutions Corp. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := kzm9g.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj) .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c new file mode 100644 index 00000000000..525c97aea6f --- /dev/null +++ b/board/kmc/kzm9g/kzm9g.c @@ -0,0 +1,377 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <netdev.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CS0BCR_D (0x06C00400) +#define CS4BCR_D (0x16c90400) +#define CS0WCR_D (0x55062C42) +#define CS4WCR_D (0x1e071dc3) + +#define CMNCR_BROMMD0 (1 << 21) +#define CMNCR_BROMMD1 (1 << 22) +#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) +#define VCLKCR1_D (0x27) + +#define SMSTPCR1_CMT0 (1 << 24) +#define SMSTPCR1_I2C0 (1 << 16) +#define SMSTPCR3_USB (1 << 22) + +#define PORT32CR (0xE6051020) +#define PORT33CR (0xE6051021) +#define PORT34CR (0xE6051022) +#define PORT35CR (0xE6051023) + +static int cmp_loop(u32 *addr, u32 data, u32 cmp) +{ + int err = -1; + int timeout = 100; + u32 value; + + while (timeout > 0) { + value = readl(addr); + if ((value & data) == cmp) { + err = 0; + break; + } + timeout--; + } + + return err; +} + +/* SBSC Init function */ +static void sbsc_init(struct sh73a0_sbsc *sbsc) +{ + writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); + writel(0x5, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + writel(0xacc90159, &sbsc->sdcr0); + writel(0x00010059, &sbsc->sdcr1); + writel(0x50874114, &sbsc->sdwcrc0); + writel(0x33199b37, &sbsc->sdwcrc1); + writel(0x008f2313, &sbsc->sdwcrc2); + writel(0x31020707, &sbsc->sdwcr00); + writel(0x0017040a, &sbsc->sdwcr01); + writel(0x31020707, &sbsc->sdwcr10); + writel(0x0017040a, &sbsc->sdwcr11); + writel(0x05555555, &sbsc->sddrvcr0); + writel(0x30000000, &sbsc->sdwcr2); + + writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); + cmp_loop(&sbsc->sdpcr, 0x80, 0x80); + + writel(0x00002710, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + writel(0x0000003f, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x000001f4, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + writel(0x0000ff0a, &sbsc->sdmracr0); + if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) + writel(0x0, SDMRA3A); + else + writel(0x0, SDMRA3B); + + writel(0x00000032, &sbsc->sdgencnt); + cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); + + if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { + writel(0x00002201, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x00000402, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x00000403, &sbsc->sdmracr0); + writel(0x0, SDMRA1A); + writel(0x0, SDMRA2A); + } else { + writel(0x00002201, &sbsc->sdmracr0); + writel(0x0, SDMRA1B); + writel(0x00000402, &sbsc->sdmracr0); + writel(0x0, SDMRA1B); + writel(0x00000403, &sbsc->sdmracr0); + writel(0x0, SDMRA1B); + writel(0x0, SDMRA2B); + } + + writel(0x88800004, &sbsc->sdmrtmpcr); + writel(0x00000004, &sbsc->sdmrtmpmsk); + writel(0xa55a0032, &sbsc->rtcor); + writel(0xa55a000c, &sbsc->rtcorh); + writel(0xa55a2048, &sbsc->rtcsr); + writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); + writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); + writel(0xfff20000, &sbsc->zqccr); + + /* SCBS2 only */ + if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { + writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); + writel(0xa5390000, &sbsc->dphycnt1); + writel(0x00001200, &sbsc->dphycnt0); + writel(0x07ce0000, &sbsc->dphycnt1); + writel(0x00001247, &sbsc->dphycnt0); + cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); + writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); + } +} + +void s_init(void) +{ + struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; + struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; + struct sh73a0_sbsc_cpg_srcr *cpg_srcr = + (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; + struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; + struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + struct sh73a0_hpb_bscr *hpb_bscr = + (struct sh73a0_hpb_bscr *)HPBSCR_BASE; + + /* Watchdog init */ + writew(0xA507, &rwdt->rwtcsra0); + + /* Secure control register Init */ + #define LIFEC_SEC_SRC_BIT (1 << 15) + writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); + + clrbits_le32(&cpg->smstpcr3, (1 << 15)); + clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); + clrbits_le32(&cpg->smstpcr2, (1 << 18)); + clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); + writel(0x0, &cpg->pllecr); + + cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); + cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); + + writel(0x2D000000, &cpg->pll0cr); + writel(0x17100000, &cpg->pll1cr); + writel(0x96235880, &cpg->frqcrb); + cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); + + writel(0xB, &cpg->flckcr); + clrbits_le32(&cpg->smstpcr0, (1 << 1)); + + clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); + writel(0x0514, &hpb_bscr->smgpiotime); + writel(0x0514, &hpb_bscr->smcmt2time); + writel(0x0514, &hpb_bscr->smcpgtime); + writel(0x0514, &hpb_bscr->smsysctime); + + writel(0x00092000, &cpg->dvfscr4); + writel(0x000000DC, &cpg->dvfscr5); + writel(0x0, &cpg->pllecr); + cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); + + /* FRQCR Init */ + writel(0x0012453C, &cpg->frqcra); + writel(0x80331350, &cpg->frqcrb); + cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); + writel(0x00000B0B, &cpg->frqcrd); + cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); + + /* Clock Init */ + writel(0x00000003, PCLKCR); + writel(0x0000012F, &cpg->vclkcr1); + writel(0x00000119, &cpg->vclkcr2); + writel(0x00000119, &cpg->vclkcr3); + writel(0x00000002, &cpg->zbckcr); + writel(0x00000005, &cpg->flckcr); + writel(0x00000080, &cpg->sd0ckcr); + writel(0x00000080, &cpg->sd1ckcr); + writel(0x00000080, &cpg->sd2ckcr); + writel(0x0000003F, &cpg->fsiackcr); + writel(0x0000003F, &cpg->fsibckcr); + writel(0x00000080, &cpg->subckcr); + writel(0x0000000B, &cpg->spuackcr); + writel(0x0000000B, &cpg->spuvckcr); + writel(0x0000013F, &cpg->msuckcr); + writel(0x00000080, &cpg->hsickcr); + writel(0x0000003F, &cpg->mfck1cr); + writel(0x0000003F, &cpg->mfck2cr); + writel(0x00000107, &cpg->dsitckcr); + writel(0x00000313, &cpg->dsi0pckcr); + writel(0x0000130D, &cpg->dsi1pckcr); + writel(0x2A800E0E, &cpg->dsi0phycr); + writel(0x1E000000, &cpg->pll0cr); + writel(0x2D000000, &cpg->pll0cr); + writel(0x17100000, &cpg->pll1cr); + writel(0x27000080, &cpg->pll2cr); + writel(0x1D000000, &cpg->pll3cr); + writel(0x00080000, &cpg->pll0stpcr); + writel(0x000120C0, &cpg->pll1stpcr); + writel(0x00012000, &cpg->pll2stpcr); + writel(0x00000030, &cpg->pll3stpcr); + + writel(0x0000000B, &cpg->pllecr); + cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); + + writel(0x000120F0, &cpg->dvfscr3); + writel(0x00000020, &cpg->mpmode); + writel(0x0000028A, &cpg->vrefcr); + writel(0xE4628087, &cpg->rmstpcr0); + writel(0xFFFFFFFF, &cpg->rmstpcr1); + writel(0x53FFFFFF, &cpg->rmstpcr2); + writel(0xFFFFFFFF, &cpg->rmstpcr3); + writel(0x00800D3D, &cpg->rmstpcr4); + writel(0xFFFFF3FF, &cpg->rmstpcr5); + writel(0x00000000, &cpg->smstpcr2); + writel(0x00040000, &cpg_srcr->srcr2); + + clrbits_le32(&cpg->pllecr, (1 << 3)); + cmp_loop(&cpg->pllecr, 0x00000800, 0x0); + + writel(0x00000001, &hpb->hpbctrl6); + cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); + + writel(0x00001414, &cpg->frqcrd); + cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); + + writel(0x1d000000, &cpg->pll3cr); + setbits_le32(&cpg->pllecr, (1 << 3)); + cmp_loop(&cpg->pllecr, 0x800, 0x800); + + /* SBSC1 Init*/ + sbsc_init(sbsc1); + + /* SBSC2 Init*/ + sbsc_init(sbsc2); + + writel(0x00000b0b, &cpg->frqcrd); + cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); + writel(0xfffffffc, &cpg->cpgxxcs4); +} + +int board_early_init_f(void) +{ + struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; + struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; + struct sh73a0_sbsc_cpg_srcr *cpg_srcr = + (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; + + writel(CS0BCR_D, &bsc->cs0bcr); + writel(CS4BCR_D, &bsc->cs4bcr); + writel(CS0WCR_D, &bsc->cs0wcr); + writel(CS4WCR_D, &bsc->cs4wcr); + + clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); + + clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); + clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); + clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); + clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); + writel(VCLKCR1_D, &cpg->vclkcr1); + + /* Setup SCIF4 / workaround */ + writeb(0x12, PORT32CR); + writeb(0x22, PORT33CR); + writeb(0x12, PORT34CR); + writeb(0x22, PORT35CR); + + return 0; +} + +int board_init(void) +{ + sh73a0_pinmux_init(); + + /* SCIFA 4 */ + gpio_request(GPIO_FN_SCIFA4_TXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); + gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); + + /* Ethernet/SMSC */ + gpio_request(GPIO_PORT224, NULL); + gpio_direction_input(GPIO_PORT224); + + /* SMSC/USB */ + gpio_request(GPIO_FN_CS4_, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCCMD0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_1_PU, NULL); + gpio_request(GPIO_FN_MMCD0_2_PU, NULL); + gpio_request(GPIO_FN_MMCD0_3_PU, NULL); + gpio_request(GPIO_FN_MMCD0_4_PU, NULL); + gpio_request(GPIO_FN_MMCD0_5_PU, NULL); + gpio_request(GPIO_FN_MMCD0_6_PU, NULL); + gpio_request(GPIO_FN_MMCD0_7_PU, NULL); + + /* SDHI */ + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); + gpio_request(GPIO_PORT15, NULL); + gpio_direction_output(GPIO_PORT15, 1); + + /* I2C */ + gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); + gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); + + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#ifdef CONFIG_SMC911X + ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return ret; +} + +void reset_cpu(ulong addr) +{ + /* Soft Power On Reset */ + writel((1 << 31), RESCNT2); +} diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S index 95b0c080c5d..0ce890549ea 100644 --- a/board/logicpd/imx31_litekit/lowlevel_init.S +++ b/board/logicpd/imx31_litekit/lowlevel_init.S @@ -54,7 +54,7 @@ lowlevel_init: REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0) + REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0) REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23) REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) diff --git a/board/logicpd/zoom2/zoom2_serial.c b/board/logicpd/zoom2/zoom2_serial.c index 74f165fa25f..9b7aea85902 100644 --- a/board/logicpd/zoom2/zoom2_serial.c +++ b/board/logicpd/zoom2/zoom2_serial.c @@ -135,5 +135,10 @@ QUAD_INIT (3) struct serial_device *default_serial_console(void) { - return ZOOM2_DEFAULT_SERIAL_DEVICE; + switch (ZOOM2_DEFAULT_SERIAL_DEVICE) { + case 0: return &zoom2_serial_device0; + case 1: return &zoom2_serial_device1; + case 2: return &zoom2_serial_device2; + case 3: return &zoom2_serial_device3; + } } diff --git a/board/logicpd/zoom2/zoom2_serial.h b/board/logicpd/zoom2/zoom2_serial.h index 4e30587066c..482fe2ec9d8 100644 --- a/board/logicpd/zoom2/zoom2_serial.h +++ b/board/logicpd/zoom2/zoom2_serial.h @@ -22,6 +22,8 @@ #ifndef ZOOM2_SERIAL_H #define ZOOM2_SERIAL_H +#include <linux/stringify.h> + extern int zoom2_debug_board_connected (void); #define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */ @@ -31,9 +33,6 @@ extern int zoom2_debug_board_connected (void); #define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) #define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) -#define S(a) #a -#define N(a) S(quad##a) - #define QUAD_INIT(n) \ int quad_init_##n(void) \ { \ @@ -61,14 +60,14 @@ int quad_tstc_##n(void) \ } \ struct serial_device zoom2_serial_device##n = \ { \ - N(n), \ - quad_init_##n, \ - NULL, \ - quad_setbrg_##n, \ - quad_getc_##n, \ - quad_tstc_##n, \ - quad_putc_##n, \ - quad_puts_##n, \ + .name = __stringify(n), \ + .start = quad_init_##n, \ + .stop = NULL, \ + .setbrg = quad_setbrg_##n, \ + .getc = quad_getc_##n, \ + .tstc = quad_tstc_##n, \ + .putc = quad_putc_##n, \ + .puts = quad_puts_##n, \ }; #endif /* ZOOM2_SERIAL_H */ diff --git a/board/ml2/flash.c b/board/ml2/flash.c deleted file mode 100644 index c125d418d3b..00000000000 --- a/board/ml2/flash.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * flash.c: Support code for the flash chips on the Xilinx ML2 board - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire program - * is licensed under the GPL. - * - */ - -#include <common.h> -#include <asm/u-boot.h> -#include <configs/ML2.h> - -#define FLASH_BANK_SIZE (64*1024*1024) - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define SECT_SIZE (512*1024) - -#define CMD_READ_ARRAY 0x00FF00FF00FF00FULL -#define CMD_IDENTIFY 0x0090009000900090ULL -#define CMD_ERASE_SETUP 0x0020002000200020ULL -#define CMD_ERASE_CONFIRM 0x00D000D000D000D0ULL -#define CMD_PROGRAM 0x0040004000400040ULL -#define CMD_RESUME 0x00D000D000D000D0ULL -#define CMD_SUSPEND 0x00B000B000B000B0ULL -#define CMD_STATUS_READ 0x0070007000700070ULL -#define CMD_STATUS_RESET 0x0050005000500050ULL - -#define BIT_BUSY 0x0080008000800080ULL -#define BIT_ERASE_SUSPEND 0x004000400400040ULL -#define BIT_ERASE_ERROR 0x0020002000200020ULL -#define BIT_PROGRAM_ERROR 0x0010001000100010ULL -#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL -#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL -#define BIT_PROTECT_ERROR 0x0002000200020002ULL -#define BIT_UNDEFINED 0x0001000100010001ULL - -#define BIT_SEQUENCE_ERROR 0x0030003000300030ULL - -#define BIT_TIMEOUT 0x80000000 - - -inline void eieio(void) { - - __asm__ __volatile__ ("eieio" : : : "memory"); - -} - -ulong flash_init(void) { - - int i, j; - ulong size = 0; - - for(i=0;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i==0) - flashbase = CONFIG_SYS_FLASH_BASE; - else - panic("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) - flash_info[i].start[j]=flashbase + j * SECT_SIZE; - - size += flash_info[i].size; - } - - return size; -} - -void flash_print_info (flash_info_t *info) { - - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("Intel: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): - printf("4x 28F128J3A (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - printf("\n "); - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -int flash_error (unsigned long long code) { - - if (code & BIT_TIMEOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if (~code & BIT_BUSY) { - printf ("Busy\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_VPP_RANGE_ERROR) { - printf ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_PROTECT_ERROR) { - printf ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_SEQUENCE_ERROR) { - printf ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_ERASE_ERROR) { - printf ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_PROGRAM_ERROR) { - printf ("Program error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_ERASE_SUSPEND) { - printf ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_PROGRAM_SUSPEND) { - printf ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - return ERR_OK; - -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) { - - int rc = ERR_OK; - int sect; - unsigned long long result; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - for (sect=s_first; sect<=s_last; ++sect) - if (info->protect[sect]) - return ERR_PROTECTED; - - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - volatile unsigned long long *addr= - (unsigned long long *)(info->start[sect]); - - printf("Erasing sector %2d ... ", sect); - - *addr=CMD_STATUS_RESET; - eieio(); - *addr=CMD_ERASE_SETUP; - eieio(); - *addr=CMD_ERASE_CONFIRM; - eieio(); - - do { - result = *addr; - } while(~result & BIT_BUSY); - - *addr=CMD_READ_ARRAY; - - if ((rc = flash_error(result)) == ERR_OK) - printf("ok.\n"); - else - break; - } - - if (ctrlc()) - printf("User Interrupt!\n"); - - return rc; -} - -static int write_word (flash_info_t *info, ulong dest, unsigned long long data) { - - volatile unsigned long long *addr=(unsigned long long *)dest; - unsigned long long result; - int rc = ERR_OK; - - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - *addr=CMD_STATUS_RESET; - eieio(); - *addr=CMD_PROGRAM; - eieio(); - *addr=data; - eieio(); - - do { - result = *addr; - } while(~result & BIT_BUSY); - - *addr=CMD_READ_ARRAY; - - rc = flash_error(result); - - return rc; - -} - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - - ulong cp, wp; - unsigned long long data; - int l; - int i,rc; - - wp=(addr & ~7); - - if((l=addr-wp) != 0) { - data=0; - for(i=0,cp=wp;i<l;++i,++cp) - data = (data >> 8) | (*(uchar *)cp << 24); - - for (; i<8 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - - for (; i<8; ++i, ++cp) - data = (data >> 8) | (*(uchar *)cp << 24); - - if ((rc = write_word(info, wp, data)) != 0) - return rc; - - wp+=8; - } - - while(cnt>=8) { - data = *((unsigned long long *)src); - if ((rc = write_word(info, wp, data)) != 0) - return rc; - src+=8; - wp+=8; - cnt-=8; - } - - if(cnt == 0) - return ERR_OK; - - data = 0; - for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<8; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_word(info, wp, data); - -} diff --git a/board/ml2/init.S b/board/ml2/init.S deleted file mode 100644 index 91d053c96ef..00000000000 --- a/board/ml2/init.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * init.S: Stubs for U-Boot initialization - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr diff --git a/board/ml2/ml2.c b/board/ml2/ml2.c deleted file mode 100644 index 319dca09db0..00000000000 --- a/board/ml2/ml2.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * ml2.c: U-Boot platform support for Xilinx ML2 board - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * Derived from : Other platform support files in this tree - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include <common.h> -#include <asm/processor.h> - - -int board_early_init_f (void) -{ - return 0; -} - - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0 || strncmp(buf, "ML2", 9)) { - printf ("### No HW ID - assuming ML2"); - } else { - for (i = 0; i < l; i++) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - } - putc ('\n'); - - return (0); -} - - -phys_size_t initdram (int board_type) -{ - return 32 * 1024 * 1024; -} - -int testdram (void) -{ - printf ("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/ml2/serial.c b/board/ml2/serial.c deleted file mode 100644 index d9113ab9381..00000000000 --- a/board/ml2/serial.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2002 - * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/u-boot.h> -#include <asm/processor.h> -#include <command.h> -#include <configs/ML2.h> - -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) -#include <ns16550.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1, - (NS16550_t) CONFIG_SYS_NS16550_COM2 -}; -#endif - -int serial_init (void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - (void) NS16550_init (COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - (void) NS16550_init (COM_PORTS[1], clock_divisor); -#endif - return 0; - -} - -void serial_putc (const char c) -{ - if (c == '\n') - NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - - NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); -} - -int serial_getc (void) -{ - return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -int serial_tstc (void) -{ - return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); -} - -void serial_setbrg (void) -{ - int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CONFIG_SYS_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CONFIG_SYS_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds deleted file mode 100644 index 9f9ddb8bf01..00000000000 --- a/board/ml2/u-boot.lds +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug deleted file mode 100644 index fcf8ebbf8ec..00000000000 --- a/board/ml2/u-boot.lds.debug +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index ddca5873698..254f263cabc 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -602,7 +602,7 @@ void handle_usb_interrupt(void) /* init uhci */ -int usb_lowlevel_init(void) +int usb_lowlevel_init(int index, void **controller) { unsigned char temp; int busdevfunc; @@ -632,7 +632,7 @@ int usb_lowlevel_init(void) /* stop uhci */ -int usb_lowlevel_stop(void) +int usb_lowlevel_stop(int index) { if(irqvec==-1) return 1; diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index afe832a5295..2c7cd0d401f 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -25,22 +25,21 @@ #include <ns16550.h> #include <linux/compiler.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/sys_proto.h> - -#include <asm/arch/board.h> -#include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> +#include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/pmc.h> #include <asm/arch/pmu.h> -#include <asm/arch/uart.h> -#include <asm/arch/warmboot.h> -#include <spi.h> +#include <asm/arch/tegra.h> #include <asm/arch/usb.h> +#include <asm/arch-tegra/board.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/sys_proto.h> +#include <asm/arch-tegra/uart.h> +#include <asm/arch-tegra/warmboot.h> +#include <spi.h> #include <i2c.h> -#include "board.h" #include "emc.h" DECLARE_GLOBAL_DATA_PTR; @@ -72,6 +71,20 @@ void __pin_mux_spi(void) void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); +void __gpio_early_init_uart(void) +{ +} + +void gpio_early_init_uart(void) +__attribute__((weak, alias("__gpio_early_init_uart"))); + +void __pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); +} + +void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand"))); + /* * Routine: power_det_init * Description: turn off power detects @@ -132,6 +145,10 @@ int board_init(void) board_usb_init(gd->fdt_blob); #endif +#ifdef CONFIG_TEGRA_NAND + pin_mux_nand(); +#endif + #ifdef CONFIG_TEGRA_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ warmboot_save_sdram_params(); @@ -156,11 +173,8 @@ int board_early_init_f(void) /* Initialize periph GPIOs */ gpio_early_init(); -#ifdef CONFIG_SPI_UART_SWITCH gpio_early_init_uart(); -#else - gpio_config_uart(); -#endif + return 0; } #endif /* EARLY_INIT */ diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 739d4bd4420..26b6ec7c3b5 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -22,13 +22,13 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ap20.h> -#include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/pmu.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c index 6b2175879ba..e9d445d9e26 100644 --- a/board/nvidia/common/uart-spi-switch.c +++ b/board/nvidia/common/uart-spi-switch.c @@ -24,9 +24,9 @@ #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart-spi-switch.h> -#include <asm/arch/tegra20.h> -#include <asm/arch/tegra_spi.h> - +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_spi.h> +#include <asm/arch-tegra/board.h> /* position of the UART/SPI select switch */ enum spi_uart_switch { diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index b4a811dc5f9..32ed9bb7d1a 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -23,23 +23,16 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/mmc.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> #ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Harmony - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} #ifdef CONFIG_TEGRA_MMC /* diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 667f60a9bb9..4e8a183b8be 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -23,11 +23,11 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/mmc.h> +#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> #ifdef CONFIG_TEGRA_MMC #include <mmc.h> @@ -46,7 +46,7 @@ static void gpio_config_uart_seaboard(void) gpio_direction_output(GPIO_PI3, 0); } -void gpio_config_uart(void) +void gpio_early_init_uart(void) { if (machine_is_ventana()) return; diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 598b2e5ce25..592cd6b496d 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -22,25 +22,18 @@ */ #include <common.h> -#include <i2c.h> #include <asm/io.h> -#include <asm/arch/tegra20.h> +#include <asm/arch/tegra.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch/mmc.h> +#include <asm/arch-tegra/mmc.h> #include <asm/gpio.h> +#include <i2c.h> #ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Whistler - no UART-related GPIOs. - */ -void gpio_config_uart(void) -{ -} /* * Routine: pin_mux_mmc diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c index 2f1ad200808..57b4f5f6232 100644 --- a/board/palmld/palmld.c +++ b/board/palmld/palmld.c @@ -52,11 +52,6 @@ int board_init(void) return 0; } -struct serial_device *default_serial_console(void) -{ - return &serial_ffuart_device; -} - int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index 4adf152a4ed..b23eec805e7 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -51,11 +51,6 @@ int board_init(void) return 0; } -struct serial_device *default_serial_console(void) -{ - return &serial_ffuart_device; -} - int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c index 6ef38f437bf..aa3c908c638 100644 --- a/board/pcippc2/sconsole.c +++ b/board/pcippc2/sconsole.c @@ -23,6 +23,8 @@ #include <config.h> #include <common.h> +#include <serial.h> +#include <linux/compiler.h> #include "sconsole.h" @@ -34,7 +36,7 @@ int (*sconsole_getc) (void) = 0; int (*sconsole_tstc) (void) = 0; void (*sconsole_setbrg) (void) = 0; -int serial_init (void) +static int sconsole_serial_init(void) { sconsole_buffer_t *sb = SCONSOLE_BUFFER; @@ -46,7 +48,7 @@ int serial_init (void) return (0); } -void serial_putc (char c) +static void sconsole_serial_putc(char c) { if (sconsole_putc) { (*sconsole_putc) (c); @@ -65,7 +67,7 @@ void serial_putc (char c) } } -void serial_puts (const char *s) +static void sconsole_serial_puts(const char *s) { if (sconsole_puts) { (*sconsole_puts) (s); @@ -84,7 +86,7 @@ void serial_puts (const char *s) } } -int serial_getc (void) +static int sconsole_serial_getc(void) { if (sconsole_getc) { return (*sconsole_getc) (); @@ -93,7 +95,7 @@ int serial_getc (void) } } -int serial_tstc (void) +static int sconsole_serial_tstc(void) { if (sconsole_tstc) { return (*sconsole_tstc) (); @@ -102,7 +104,7 @@ int serial_tstc (void) } } -void serial_setbrg (void) +static void sconsole_serial_setbrg(void) { if (sconsole_setbrg) { (*sconsole_setbrg) (); @@ -113,6 +115,27 @@ void serial_setbrg (void) } } +static struct serial_device sconsole_serial_drv = { + .name = "sconsole_serial", + .start = sconsole_serial_init, + .stop = NULL, + .setbrg = sconsole_serial_setbrg, + .putc = sconsole_serial_putc, + .puts = sconsole_serial_puts, + .getc = sconsole_serial_getc, + .tstc = sconsole_serial_tstc, +}; + +void sconsole_serial_initialize(void) +{ + serial_register(&sconsole_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &sconsole_serial_drv; +} + int sconsole_get_baudrate (void) { sconsole_buffer_t *sb = SCONSOLE_BUFFER; diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index 2082ad48a27..a2a132344f5 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -172,9 +172,7 @@ phys_size_t initdram (int board_type) return msize; } -#if defined(CONFIG_SERIAL_MULTI) static int set_lcd_brightness(char *); -#endif int misc_init_r(void) { @@ -237,9 +235,7 @@ int misc_init_r(void) #endif #ifdef CONFIG_FSL_DIU_FB -#if defined(CONFIG_SERIAL_MULTI) set_lcd_brightness(0); -#endif /* Switch LCD-Backlight and LVDS-Interface on */ setbits_be32(&im->gpio.gpdir, 0x01040000); clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000); @@ -608,7 +604,6 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -#if defined(CONFIG_SERIAL_MULTI) /* * If argument is NULL, set the LCD brightness to the * value from "brightness" environment variable. Set @@ -685,4 +680,3 @@ U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness, "set LCD brightness", "<brightness> - set LCD backlight level to <brightness>.\n" ); -#endif /* CONFIG_SERIAL_MULTI */ diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c index e1af37e1d8a..2f4d294b9d2 100644 --- a/board/prodrive/p3mx/serial.c +++ b/board/prodrive/p3mx/serial.c @@ -35,6 +35,9 @@ #include <common.h> #include <command.h> +#include <serial.h> +#include <linux/compiler.h> + #include "../../Marvell/include/memory.h" #include "serial.h" @@ -42,14 +45,14 @@ DECLARE_GLOBAL_DATA_PTR; -int serial_init (void) +static int p3mx_serial_init(void) { mpsc_init (gd->baudrate); return (0); } -void serial_putc (const char c) +static void p3mx_serial_putc(const char c) { if (c == '\n') mpsc_putchar ('\r'); @@ -57,29 +60,50 @@ void serial_putc (const char c) mpsc_putchar (c); } -int serial_getc (void) +static int p3mx_serial_getc(void) { return mpsc_getchar (); } -int serial_tstc (void) +static int p3mx_serial_tstc(void) { return mpsc_test_char (); } -void serial_setbrg (void) +static void p3mx_serial_setbrg(void) { galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } -void serial_puts (const char *s) +static void p3mx_serial_puts(const char *s) { while (*s) { serial_putc (*s++); } } +static struct serial_device p3mx_serial_drv = { + .name = "p3mx_serial", + .start = p3mx_serial_init, + .stop = NULL, + .setbrg = p3mx_serial_setbrg, + .putc = p3mx_serial_putc, + .puts = p3mx_serial_puts, + .getc = p3mx_serial_getc, + .tstc = p3mx_serial_tstc, +}; + +void p3mx_serial_initialize(void) +{ + serial_register(&p3mx_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &p3mx_serial_drv; +} + #if defined(CONFIG_CMD_KGDB) void kgdb_serial_init (void) { diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 1164d6bf3ff..b7e6e4107c5 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -23,6 +23,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> @@ -41,6 +42,8 @@ int board_early_init_f(void) IB62x0_OE_VAL_HIGH, IB62x0_OE_LOW, IB62x0_OE_HIGH); + /* Set SATA activity LEDs to default off */ + writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); /* Multi-Purpose Pins Functionality configuration */ u32 kwmpp_config[] = { MPP0_NF_IO2, diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h index 0c30690697f..0118c2b69ac 100644 --- a/board/raidsonic/ib62x0/ib62x0.h +++ b/board/raidsonic/ib62x0/ib62x0.h @@ -37,4 +37,8 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +/* SATAHC related */ +#define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C) +#define MVSATAHC_LED_POLARITY_CTRL (1 << 3) + #endif /* __IB62x0_H */ diff --git a/board/ml2/Makefile b/board/spear/x600/Makefile index f4df3aca994..8c4e7e2987c 100644 --- a/board/ml2/Makefile +++ b/board/spear/x600/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,14 +25,16 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o serial.o -SOBJS = init.o +ifndef CONFIG_SPL_BUILD +COBJS := fpga.o $(BOARD).o +endif +SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ######################################################################### diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c new file mode 100644 index 00000000000..85eb31be7bc --- /dev/null +++ b/board/spear/x600/fpga.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spartan3.h> +#include <command.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_ssp.h> + +/* + * FPGA program pin configuration on X600: + * + * Only PROG and DONE are connected to GPIOs. INIT is not connected to the + * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use + * 16bit serial writes via this SSP port to write the data bits into the + * FPGA. + */ +#define CONFIG_SYS_FPGA_PROG 2 +#define CONFIG_SYS_FPGA_DONE 3 + +/* + * Set the active-low FPGA reset signal. + */ +static void fpga_reset(int assert) +{ + /* + * On x600 we have no means to toggle the FPGA reset signal + */ + debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert); +} + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +static int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); + + gpio_set_value(CONFIG_SYS_FPGA_PROG, assert); + + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +static int fpga_init_fn(int cookie) +{ + static int state; + + debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state); + + /* + * On x600, the FPGA INIT signal is not connected to the SoC. + * We can't read the INIT status. Let's return the "correct" + * INIT signal state generated via a local state-machine. + */ + if (++state == 1) { + return 1; + } else { + state = 0; + return 0; + } +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +static int fpga_done_fn(int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + + /* + * Wait for Tx-FIFO to become empty before looking for DONE + */ + while (!(readl(&ssp->sspsr) & SSPSR_TFE)) + ; + + if (gpio_get_value(CONFIG_SYS_FPGA_DONE)) + return 1; + else + return 0; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +static int fpga_pre_config_fn(int cookie) +{ + debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); + fpga_reset(TRUE); + + return 0; +} + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +static int fpga_post_config_fn(int cookie) +{ + int rc = 0; + + debug("%s:%d: FPGA post configuration\n", __func__, __LINE__); + + fpga_reset(TRUE); + udelay(100); + fpga_reset(FALSE); + udelay(100); + + return rc; +} + +static int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + /* + * No dedicated clock signal on x600 (data & clock generated) + * in SSP interface. So we don't have to do anything here. + */ + return assert_clk; +} + +static int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + static int count; + static u16 data; + + /* + * First collect 16 bits of data + */ + data = data << 1; + if (assert_write) + data |= 1; + + /* + * If 16 bits are not available, return for more bits + */ + count++; + if (count != 16) + return assert_write; + + count = 0; + + /* + * Wait for Tx-FIFO to become ready + */ + while (!(readl(&ssp->sspsr) & SSPSR_TNF)) + ; + + /* Send 16 bits to FPGA via SSP bus */ + writel(data, &ssp->sspdr); + + return assert_write; +} + +static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_post_config_fn, +}; + +static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) +}; + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +static void fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__); + fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ +} + +static int expi_setup(int freq) +{ + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + int pll2_m, pll2_n, pll2_p, expi_x, expi_y; + + pll2_m = (freq * 2) / 1000; + pll2_n = 15; + pll2_p = 1; + expi_x = 1; + expi_y = 2; + + /* + * Disable reset, Low compression, Disable retiming, Enable Expi, + * Enable soft reset, DMA, PLL2, Internal + */ + writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST | + EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 | + EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24), + &misc->expi_clk_cfg); + + /* + * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters, + * Enable PLL2, Disable reset + */ + writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq); + writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE | + PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl); + + /* + * Disable soft reset + */ + clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST); + + return 0; +} + +/* + * Initialize the fpga + */ +int x600_init_fpga(void) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Enable SSP2 clock */ + writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB, + &misc->periph1_clken); + + /* Set EXPI clock to 45 MHz */ + expi_setup(45000); + + /* Configure GPIO directions */ + gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0); + gpio_direction_input(CONFIG_SYS_FPGA_DONE); + + writel(SSPCR0_DSS_16BITS, &ssp->sspcr0); + writel(SSPCR1_SSE, &ssp->sspcr1); + + /* + * Set lowest prescale divisor value (CPSDVSR) of 2 for max download + * speed. + * + * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1)) + * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz. + */ + writel(2, &ssp->sspcpsr); + + fpga_init(); + fpga_serialslave_init(); + + debug("%s:%d: Adding fpga 0\n", __func__, __LINE__); + fpga_add(fpga_xilinx, &fpga[0]); + + return 0; +} diff --git a/board/nvidia/common/board.h b/board/spear/x600/fpga.h index dada4c4f9cb..2b1855716bd 100644 --- a/board/nvidia/common/board.h +++ b/board/spear/x600/fpga.h @@ -1,6 +1,5 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> + * Copyright (C) 2012 Stefan Roese <sr@denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -21,17 +20,4 @@ * MA 02111-1307 USA */ -#ifndef _BOARD_H_ -#define _BOARD_H_ - -void gpio_config_uart(void); -void gpio_early_init(void); -void gpio_early_init_uart(void); - -/* - * Set up any pin muxing needed for USB (for now, since fdt doesn't support - * it). Boards can overwrite the default fucction which does nothing. - */ -void pin_mux_usb(void); - -#endif /* BOARD_H */ +int x600_init_fpga(void); diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c new file mode 100644 index 00000000000..96ec0ad8a5d --- /dev/null +++ b/board/spear/x600/x600.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <netdev.h> +#include <phy.h> +#include <rtc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <linux/mtd/fsmc_nand.h> +#include "fpga.h" + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +int board_init(void) +{ + /* + * X600 is equipped with an M41T82 RTC. This RTC has the + * HT bit (Halt Update), which needs to be cleared upon + * power-up. Otherwise the RTC is halted. + */ + rtc_reset(); + + return spear_board_init(MACH_TYPE_SPEAR600); +} + +int board_late_init(void) +{ + /* + * Monitor and env protection on by default + */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + + CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* Init FPGA subsystem */ + x600_init_fpga(); + + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +void board_nand_init(void) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) + fsmc_nand_init(nand); +} + +int designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + /* Extended PHY control 1, select GMII */ + mii_write(dev, phy_addr, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + dw_reset_phy(dev); + + /* Enable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + mii_write(dev, phy_addr, 17, 0x09ff); + mii_write(dev, phy_addr, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + mii_write(dev, phy_addr, 16, 0xe0ea); + + /* Disable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0000); + + /* Enable clock output pin */ + mii_write(dev, phy_addr, 18, 0x0049); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + PHY_INTERFACE_MODE_GMII) >= 0) + ret++; + + return ret; +} diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c index 8c743c0adb0..e750df189dd 100644 --- a/board/st-ericsson/snowball/snowball.c +++ b/board/st-ericsson/snowball/snowball.c @@ -253,6 +253,10 @@ int board_late_init(void) if ((raise_ab8500_gpio16() < 0)) printf("error: cant' raise GPIO16\n"); + /* empty UART RX FIFO */ + while (tstc()) + (void) getc(); + return 0; } diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 7429e934fde..1471559909d 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -67,12 +67,12 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(void) +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata); + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); } -int ehci_hcd_stop(void) +int ehci_hcd_stop(int index) { return omap_ehci_hcd_stop(); } diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index b8ad4471f52..ecb9b6c4136 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -110,12 +110,12 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(void) +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata); + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); } -int ehci_hcd_stop(void) +int ehci_hcd_stop(int index) { return omap_ehci_hcd_stop(); } diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 99f833f0410..6175e1d1ac0 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -488,7 +488,7 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_USB_EHCI +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { @@ -502,12 +502,12 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED }; -int ehci_hcd_init(void) +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - return omap_ehci_hcd_init(&usbhs_bdata); + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); } -int ehci_hcd_stop(void) +int ehci_hcd_stop(int index) { return omap_ehci_hcd_stop(); } diff --git a/board/ti/omap2420h4/sys_info.c b/board/ti/omap2420h4/sys_info.c index a9f72412a79..b12011e04ab 100644 --- a/board/ti/omap2420h4/sys_info.c +++ b/board/ti/omap2420h4/sys_info.c @@ -237,20 +237,20 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) *********************************************************************/ void display_board_info(u32 btype) { - char cpu_2420[] = "2420"; /* cpu type */ - char cpu_2422[] = "2422"; - char cpu_2423[] = "2423"; - char db_men[] = "Menelaus"; /* board type */ - char db_ip[] = "IP"; - char mem_sdr[] = "mSDR"; /* memory type */ - char mem_ddr[] = "mDDR"; - char t_tst[] = "TST"; /* security level */ - char t_emu[] = "EMU"; - char t_hs[] = "HS"; - char t_gp[] = "GP"; - char unk[] = "?"; - - char *cpu_s, *db_s, *mem_s, *sec_s; + static const char cpu_2420 [] = "2420"; /* cpu type */ + static const char cpu_2422 [] = "2422"; + static const char cpu_2423 [] = "2423"; + static const char db_men [] = "Menelaus"; /* board type */ + static const char db_ip [] = "IP"; + static const char mem_sdr [] = "mSDR"; /* memory type */ + static const char mem_ddr [] = "mDDR"; + static const char t_tst [] = "TST"; /* security level */ + static const char t_emu [] = "EMU"; + static const char t_hs [] = "HS"; + static const char t_gp [] = "GP"; + static const char unk [] = "?"; + + const char *cpu_s, *db_s, *mem_s, *sec_s; u32 cpu, rev, sec; rev = get_cpu_rev(); diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index ee82771b08d..4feef78efe4 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -192,7 +192,7 @@ static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; -int ehci_hcd_init(void) +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { int ret; unsigned int utmi_clk; @@ -202,14 +202,14 @@ int ehci_hcd_init(void) utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk); - ret = omap_ehci_hcd_init(&usbhs_bdata); + ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); if (ret < 0) return ret; return 0; } -int ehci_hcd_stop(void) +int ehci_hcd_stop(int index) { return omap_ehci_hcd_stop(); } diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index d72e5d6b5a0..a6e13c8b2c6 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -29,11 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct serial_device *default_serial_console(void) -{ - return &serial_ffuart_device; -} - int board_init(void) { /* We have RAM, disable cache */ diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c deleted file mode 100644 index c596303c5db..00000000000 --- a/board/tqc/tqm85xx/law.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * Standard mapping: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M - * 0xef00_0000 0xefff_ffff PCI express IO 16M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M - * - * Big FLASH mapping: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xa000_ffff CCSR 1M - * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M - * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M - * 0xaf00_0000 0xafff_ffff PCI express IO 16M - * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M - * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#ifdef CONFIG_TQM_BIGFLASH -#define LAW_3_SIZE LAW_SIZE_1G -#define LAW_5_SIZE LAW_SIZE_256M -#else -#define LAW_3_SIZE LAW_SIZE_128M -#define LAW_5_SIZE LAW_SIZE_512M -#endif - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), -#ifndef CONFIG_PCIE1 - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), -#endif /* CONFIG_PCIE1 */ -#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) - SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), -#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ -}; - -int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c deleted file mode 100644 index 4b16c31de28..00000000000 --- a/board/tqc/tqm85xx/nand.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> - * - * (C) Copyright 2006 - * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/fsl_upm.h> -#include <ioports.h> - -#include <nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern uint get_lbc_clock (void); - -/* index of UPM RAM array run pattern for NAND command cycle */ -#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08 - -/* index of UPM RAM array run pattern for NAND address cycle */ -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10 - -/* Structure for table with supported UPM timings */ -struct upm_freq { - ulong freq; - const u32 *upm_patt; - uchar gpl4_disable; - uchar ehtr; - uchar ead; -}; - -/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */ - -/* UPM pattern for bus clock = 25 MHz */ -static const u32 upm_patt_25[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 33.3 MHz */ -static const u32 upm_patt_33[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 41.7 MHz */ -static const u32 upm_patt_42[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 50 MHz */ -static const u32 upm_patt_50[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, - /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 66.7 MHz */ -static const u32 upm_patt_67[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 83.3 MHz */ -static const u32 upm_patt_83[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const u32 upm_patt_100[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const u32 upm_patt_133[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 166.7 MHz */ -static const u32 upm_patt_167[] = { - /* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, - /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write CMD */ - /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> NAND Write ADDR */ - /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data */ - /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05, - /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* Supported UPM timings */ -struct upm_freq upm_freq_table[] = { - /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */ - {25000000, upm_patt_25, 1, 0, 0}, - {33333333, upm_patt_33, 1, 0, 0}, - {41666666, upm_patt_42, 1, 0, 0}, - {50000000, upm_patt_50, 0, 0, 0}, - {66666666, upm_patt_67, 0, 0, 0}, - {83333333, upm_patt_83, 0, 0, 0}, - {100000000, upm_patt_100, 0, 1, 1}, - {133333333, upm_patt_133, 0, 1, 1}, - {166666666, upm_patt_167, 0, 1, 1}, -}; - -#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq)) - -volatile const u32 *nand_upm_patt; - -/* - * write into UPMB ram - */ -static void upmb_write (u_char addr, ulong val) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - out_be32 (&lbc->mdr, val); - - clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK, - MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); - - /* dummy access to perform write */ - out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0); - - clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); -} - -/* - * Initialize UPM for NAND flash access. - */ -static void nand_upm_setup (volatile fsl_lbc_t *lbc) -{ - uint i, j; - uint or3 = CONFIG_SYS_OR3_PRELIM; - uint clock = get_lbc_clock (); - - set_lbc_br(3, 0); /* disable bank and reset all bits */ - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); - - /* - * Search appropriate UPM table for bus clock. - * If the bus clock exceeds a tolerated value, take the UPM timing for - * the next higher supported frequency to ensure that access works - * (even the access may be slower then). - */ - for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++) - ; - - if (i >= UPM_FREQS) - /* no valid entry found */ - /* take last entry with configuration for max. bus clock */ - i--; - - if (upm_freq_table[i].ehtr) { - /* EHTR must be set due to TQM8548 timing specification */ - or3 |= OR_UPM_EHTR; - } - if (upm_freq_table[i].ead) - /* EAD must be set due to TQM8548 timing specification */ - or3 |= OR_UPM_EAD; - - set_lbc_or(3, or3); - - /* Assign address of table */ - nand_upm_patt = upm_freq_table[i].upm_patt; - - for (j = 0; j < 64; j++) { - upmb_write (j, *nand_upm_patt); - nand_upm_patt++; - } - - /* Put UPM back to normal operation mode */ - if (upm_freq_table[i].gpl4_disable) - /* GPL4 must be disabled according to timing specification */ - out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS); - - return; -} - -static struct fsl_upm_nand fun = { - .width = 8, - .upm_cmd_offset = 0x08, - .upm_addr_offset = 0x10, - .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST, - .chip_offset = CONFIG_SYS_NAND_CS_DIST, - .chip_delay = NAND_BIG_DELAY_US, - .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER, -}; - -void board_nand_select_device (struct nand_chip *nand, int chip) -{ -} - -int board_nand_init (struct nand_chip *nand) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - if (!nand_upm_patt) - nand_upm_setup (lbc); - - fun.upm.io_addr = nand->IO_ADDR_R; - fun.upm.mxmr = (void __iomem *)&lbc->mbmr; - fun.upm.mdr = (void __iomem *)&lbc->mdr; - fun.upm.mar = (void __iomem *)&lbc->mar; - - return fsl_upm_nand_init (nand, &fun); -} diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c deleted file mode 100644 index baf073e5489..00000000000 --- a/board/tqc/tqm85xx/sdram.c +++ /dev/null @@ -1,436 +0,0 @@ - -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <asm/mmu.h> - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -#ifdef CONFIG_TQM8548 - unsigned long refresh; -#endif /* CONFIG_TQM8548 */ -}; - -typedef struct sdram_conf_s sdram_conf_t; - -#ifdef CONFIG_TQM8548 -#ifdef CONFIG_TQM8548_AG -sdram_conf_t ddr_cs_conf[] = { - {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */ - { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ - { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ - { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ -}; -#else /* !CONFIG_TQM8548_AG */ -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ - {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ -}; -#endif /* CONFIG_TQM8548_AG */ -#else /* !CONFIG_TQM8548 */ -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ - {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ - {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ -}; -#endif /* CONFIG_TQM8548 */ - -#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) - -int cas_latency (void); -static phys_size_t sdram_setup(int); - -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -phys_size_t fixed_sdram(void) -{ - int casl = 0; - phys_size_t dram_size = 0; - - casl = cas_latency(); - dram_size = sdram_setup(casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - printf("Problem with CAS lantency, using default CL %d/10!\n", - CONFIG_DDR_DEFAULT_CL); - dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); - puts(" "); - } - return dram_size; -} - -static phys_size_t sdram_setup(int casl) -{ - int i; - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); -#ifdef CONFIG_TQM8548 - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); -#endif -#else /* !CONFIG_TQM8548 */ - unsigned long cfg_ddr_timing1; - unsigned long cfg_ddr_mode; -#endif /* CONFIG_TQM8548 */ - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - -#ifdef CONFIG_TQM8548 - /* Timing and refresh settings for DDR2-533 and below */ - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_3 = 0x00020000; - - /* TIMING CFG 1, 533MHz - * PRETOACT: 4 Clocks - * ACTTOPRE: 12 Clocks - * ACTTORW: 4 Clocks - * CASLAT: 4 Clocks - * REFREC: EXT_REFREC:REFREC 53 Clocks - * WRREC: 4 Clocks - * ACTTOACT: 3 Clocks - * WRTORD: 2 Clocks - */ - ddr->timing_cfg_1 = 0x4C47D432; - - /* TIMING CFG 2, 533MHz - * ADD_LAT: 3 Clocks - * CPO: READLAT + 1 - * WR_LAT: 3 Clocks - * RD_TO_PRE: 2 Clocks - * WR_DATA_DELAY: 1/2 Clock - * CKE_PLS: 3 Clock - * FOUR_ACT: 14 Clocks - */ - ddr->timing_cfg_2 = 0x331848CE; - - /* DDR SDRAM Mode, 533MHz - * MRS: Extended Mode Register - * OUT: Outputs enabled - * RDQS: no - * DQS: enabled - * OCD: default state - * RTT: 75 Ohms - * Posted CAS: 3 Clocks - * ODS: reduced strength - * DLL: enabled - * MR: Mode Register - * PD: fast exit - * WR: 4 Clocks - * DLL: no DLL reset - * TM: normal - * CAS latency: 4 Clocks - * BT: sequential - * Burst length: 4 - */ - ddr->sdram_mode = 0x439E0642; - - /* DDR SDRAM Interval, 533MHz - * REFINT: 1040 Clocks - * BSTOPRE: 256 - */ - ddr->sdram_interval = (1040 << 16) | 0x100; - - /* - * Workaround for erratum DDR19 according to MPC8548 Device Errata - * document, Rev. 1: DDR IO receiver must be set to an acceptable - * bias point by modifying a hidden register. - */ - if (SVR_REV (get_svr ()) < 0x21) - gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ - - /* DDR SDRAM CFG 2 - * FRC_SR: normal mode - * SR_IE: no self-refresh interrupt - * DLL_RST_DIS: don't care, leave at reset value - * DQS_CFG: differential DQS signals - * ODT_CFG: assert ODT to internal IOs only during reads to DRAM - * LVWx_CFG: don't care, leave at reset value - * NUM_PR: 1 refresh will be issued at a time - * DM_CFG: don't care, leave at reset value - * D_INIT: no data initialization - */ - ddr->sdram_cfg_2 = 0x04401000; - - /* DDR SDRAM MODE 2 - * MRS: Extended Mode Register 2 - */ - ddr->sdram_mode_2 = 0x8000C000; - - /* DDR SDRAM CLK CNTL - * CLK_ADJUST: 1/2 Clock 0x02000000 - * CLK_ADJUST: 5/8 Clock 0x02800000 - */ - ddr->sdram_clk_cntl = 0x02800000; - - /* wait for clock stabilization */ - asm ("sync;isync;msync"); - udelay (1000); - -#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) - /* - * Workaround for erratum DDR20 according to MPC8548 Device Errata - * document, Rev. 1: "CKE signal may not function correctly after - * assertion of HRESET" - */ - - /* 1. Configure DDR register as is done in normal DDR configuration. - * Do not set DDR_SDRAM_CFG[MEM_EN]. - * - * 2. Set reserved bit EEBACR[3] at offset 0x1000 - */ - ecm->eebacr |= 0x10000000; - - /* - * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT] - * - * DDR_SDRAM_CFG_2: - * FRC_SR: normal mode - * SR_IE: no self-refresh interrupt - * DLL_RST_DIS: don't care, leave at reset value - * DQS_CFG: differential DQS signals - * ODT_CFG: assert ODT to internal IOs only during reads to DRAM - * LVWx_CFG: don't care, leave at reset value - * NUM_PR: 1 refresh will be issued at a time - * DM_CFG: don't care, leave at reset value - * D_INIT: enable data initialization - */ - ddr->sdram_cfg_2 |= 0x00000010; - - /* - * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data - * training - */ - ddr->debug[2] |= 0x00000400; - - /* - * 5. Wait 200 micro-seconds - */ - udelay (200); - - /* - * 6. Set DDR_SDRAM_CFG[MEM_EN] - * - * BTW, initialize DDR_SDRAM_CFG: - * MEM_EN: enabled - * SREN: don't care, leave at reset value - * ECC_EN: no error report - * RD_EN: no registered DIMMs - * SDRAM_TYPE: DDR2 - * DYN_PWR: no power management - * 32_BE: don't care, leave at reset value - * 8_BE: 4 beat burst - * NCAP: don't care, leave at reset value - * 2T_EN: 1T Timing - * BA_INTLV_CTL: no interleaving - * x32_EN: x16 organization - * PCHB8: MA[10] for auto-precharge - * HSE: half strength for single and 2-layer stacks - * (full strength for 3- and 4-layer stacks not - * yet considered) - * MEM_HALT: no halt - * BI: automatic initialization - */ - ddr->sdram_cfg = 0x83000008; - - /* - * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware - */ - asm ("sync;isync;msync"); - while (ddr->sdram_cfg_2 & 0x00000010) - asm ("eieio"); - - /* - * 8. Clear D3[21] to re-enable data training - */ - ddr->debug[2] &= ~0x00000400; - - /* - * 9. Set D2(21) to force data training to run - */ - ddr->debug[1] |= 0x00000400; - - /* - * 10. Poll on D2[21] until it is cleared by hardware - */ - asm ("sync;isync;msync"); - while (ddr->debug[1] & 0x00000400) - asm ("eieio"); - - /* - * 11. Clear reserved bit EEBACR[3] at offset 0x1000 - */ - ecm->eebacr &= ~0x10000000; - -#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */ - - /* DDR SDRAM CLK CNTL - * MEM_EN: enabled - * SREN: don't care, leave at reset value - * ECC_EN: no error report - * RD_EN: no register DIMMs - * SDRAM_TYPE: DDR2 - * DYN_PWR: no power management - * 32_BE: don't care, leave at reset value - * 8_BE: 4 beat burst - * NCAP: don't care, leave at reset value - * 2T_EN: 1T Timing - * BA_INTLV_CTL: no interleaving - * x32_EN: x16 organization - * PCHB8: MA[10] for auto-precharge - * HSE: half strength for single and 2-layer stacks - * (full strength for 3- and 4-layer stacks no yet considered) - * MEM_HALT: no halt - * BI: automatic initialization - */ - ddr->sdram_cfg = 0x83000008; - -#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */ - - asm ("sync; isync; msync"); - udelay (1000); -#else /* !CONFIG_TQM8548 */ - switch (casl) { - case 20: - cfg_ddr_timing1 = 0x47405331 | (3 << 16); - cfg_ddr_mode = 0x40020002 | (2 << 4); - break; - - case 25: - cfg_ddr_timing1 = 0x47405331 | (4 << 16); - cfg_ddr_mode = 0x40020002 | (6 << 4); - break; - - case 30: - default: - cfg_ddr_timing1 = 0x47405331 | (5 << 16); - cfg_ddr_mode = 0x40020002 | (3 << 4); - break; - } - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_1 = cfg_ddr_timing1; - ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ - ddr->sdram_mode = cfg_ddr_mode; - ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ - ddr->err_disable = 0x0000000D; - - asm ("sync; isync; msync"); - udelay (1000); - - ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ - asm ("sync; isync; msync"); - udelay (1000); -#endif /* CONFIG_TQM8548 */ - - /* - * get_ram_size() depends on having tlbs for the DDR, but they are - * not yet setup because we don't know the size. Set up a temp - * mapping and delete it when done. - */ - setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB); - for (i = 0; i < N_DDR_CS_CONF; i++) { - ddr->cs0_config = ddr_cs_conf[i].reg; - - if (get_ram_size (0, ddr_cs_conf[i].size) == - ddr_cs_conf[i].size) { - /* - * size detected -> set Chip Select Bounds Register - */ - ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24; - - break; - } - } - clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB); - -#ifdef CONFIG_TQM8548 - if (i < N_DDR_CS_CONF) { - /* Adjust refresh rate for DDR2 */ - - ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000; - - ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) | - (ddr_cs_conf[i].refresh & 0x0000F000); - - return ddr_cs_conf[i].size; - } -#endif /* CONFIG_TQM8548 */ - - /* return size if detected, else return 0 */ - return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c deleted file mode 100644 index f9f8cc9a01e..00000000000 --- a/board/tqc/tqm85xx/tlb.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - -#ifndef CONFIG_TQM_BIGFLASH - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000, - CONFIG_SYS_FLASH_BASE + 0x4000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - -#ifdef CONFIG_PCIE1 - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M PCI express MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M PCI express MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000, - CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), -#else /* !CONFIG_PCIE */ - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), -#endif /* CONFIG_PCIE */ - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO - * 0xe3000000 16M CAN and NAND Flash - */ - SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), -#ifdef CONFIG_PCIE1 - /* - * TLB 9: 16M Non-cacheable, guarded - * 0xef000000 16M PCI express IO - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 9, BOOKE_PAGESZ_16M, 1), -#endif /* CONFIG_PCIE */ - -#else /* CONFIG_TQM_BIGFLASH */ - - /* - * TLB 0,1,2,3: 1G Non-cacheable, guarded - * 0xc0000000 1G FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000, - CONFIG_SYS_FLASH_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000, - CONFIG_SYS_FLASH_BASE + 0x20000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000, - CONFIG_SYS_FLASH_BASE + 0x30000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 0, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - -#ifdef CONFIG_PCIE1 - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xc0000000 256M PCI express MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), -#else /* !CONFIG_PCIE */ - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xb0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - -#endif /* CONFIG_PCIE */ - - /* - * TLB 7: 64M Non-cacheable, guarded - * 0xa0000000 1M CCSRBAR - * 0xa2000000 16M PCI1 IO - * 0xa3000000 16M CAN and NAND Flash - */ - SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_64M, 1), -#ifdef CONFIG_PCIE1 - /* - * TLB 10: 16M Non-cacheable, guarded - * 0xaf000000 16M PCI express IO - */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif /* CONFIG_PCIE */ - -#endif /* CONFIG_TQM_BIGFLASH */ -}; - -int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c deleted file mode 100644 index 8fb73abde7c..00000000000 --- a/board/tqc/tqm85xx/tqm85xx.c +++ /dev/null @@ -1,626 +0,0 @@ -/* - * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de> - * - * (C) Copyright 2006 - * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <linux/compiler.h> -#include <ioports.h> -#include <flash.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -void local_bus_init (void); -ulong flash_get_size (ulong base, int banknum); - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init (void); -#endif - -#ifdef CONFIG_CPM2 -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A: conf, ppar, psor, pdir, podr, pdat */ - { - {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ - {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ - {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ - {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ - {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ - {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ - {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ - {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ - {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ - {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ - {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ - {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ - {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ - {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ - {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ - {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ - {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ - {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ - {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ - {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ - {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ - {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ - {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ - {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ - {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ - {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ - {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ - {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ - {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ - }, - - /* Port B: conf, ppar, psor, pdir, podr, pdat */ - { - {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ - {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ - {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ - {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ - {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ - {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ - {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ - {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ - {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ - {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ - {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ - {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ - {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ - {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ - {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ - {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ - {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ - {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ - {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ - {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ - {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ - {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ - {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ - {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ - {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ - {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ - {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ - {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ - }, - - /* Port C: conf, ppar, psor, pdir, podr, pdat */ - { - {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ - {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ - {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ - {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ - {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ - {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ - {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ - {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ - {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ - {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ - {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ - {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ - {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ - {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ - {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ - {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ - {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ - {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ - {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ - {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ - {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ - {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ - {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ - {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ - {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ - {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ - {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ - {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ - {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ - {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ - {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ - {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ - }, - - /* Port D: conf, ppar, psor, pdir, podr, pdat */ - { -#ifdef CONFIG_TQM8560 - {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ - {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ - {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ -#else /* !CONFIG_TQM8560 */ - {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ - {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ - {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ -#endif /* CONFIG_TQM8560 */ - {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ - {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ - {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ - {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ - {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ - {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ - {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ - {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ - {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ - {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ - {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ - {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ - {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ - {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ - {0, 0, 0, 1, 0, 0}, /* PD14: LED */ - {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ - {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ - {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ - {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ - {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ - {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ - {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ - {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ - {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ - {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ - {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ - {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ - } -}; -#endif /* CONFIG_CPM2 */ - -#define CASL_STRING1 "casl=xx" -#define CASL_STRING2 "casl=" - -static const int casl_table[] = { 20, 25, 30 }; -#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) - -int cas_latency (void) -{ - char buf[128]; - int casl; - int val; - int i; - - casl = CONFIG_DDR_DEFAULT_CL; - - i = getenv_f("serial#", buf, sizeof(buf)); - - if (i >0) { - if (strncmp(buf + strlen (buf) - strlen (CASL_STRING1), - CASL_STRING2, strlen (CASL_STRING2)) == 0) { - val = simple_strtoul (buf + strlen (buf) - 2, NULL, 10); - - for (i = 0; i < N_CASL; ++i) { - if (val == casl_table[i]) { - return val; - } - } - } - } - - return casl; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: %s", CONFIG_BOARDNAME); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc ('\n'); - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -int misc_init_r (void) -{ - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Recalculate CS configuration if second FLASH bank is available - */ - if (flash_info[0].size > 0) { - set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) | - (CONFIG_SYS_OR1_PRELIM & 0x00007fff)); - set_lbc_br(1, gd->bd->bi_flashstart | - (CONFIG_SYS_BR1_PRELIM & 0x00007fff)); - /* - * Re-check to get correct base address for bank 1 - */ - flash_get_size (gd->bd->bi_flashstart, 0); - } else { - set_lbc_or(1, 0); - set_lbc_br(1, 0); - } - - /* - * If bank 1 is equipped, bank 0 is mapped after bank 1 - */ - set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); - set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); - - /* - * Re-check to get correct base address for bank 0 - */ - flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - -#ifdef CONFIG_ENV_ADDR_REDUND - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); -#endif - - return 0; -} - -#ifdef CONFIG_CAN_DRIVER -/* - * Initialize UPMC RAM - */ -static void upmc_write (u_char addr, uint val) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - out_be32 (&lbc->mdr, val); - - clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK, - MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); - - /* dummy access to perform write */ - out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); - - /* normal operation */ - clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); -} -#endif /* CONFIG_CAN_DRIVER */ - -uint get_lbc_clock (void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; - - get_sys_info (&sys_info); - - if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 - /* - * Yes, the entire PQ38 family use the same - * bit-representation for twice the clock divider value. - */ - clkdiv *= 2; -#endif - return sys_info.freqSystemBus / clkdiv; - } - - puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n"); - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint lbc_mhz = get_lbc_clock () / 1000000; - -#ifdef CONFIG_MPC8548 - uint svr = get_svr (); - uint lcrr; - - /* - * MPC revision < 2.0 - * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: - * Modify engineering use only register at address 0xE_0F20. - * "1. Read register at offset 0xE_0F20 - * 2. And value with 0x0000_FFFF - * 3. OR result with 0x0000_0004 - * 4. Write result back to offset 0xE_0F20." - * - * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: - * Modify engineering use only register at address 0xE_0F20. - * "1. Read register at offset 0xE_0F20 - * 2. And value with 0xFFFF_FFDF - * 3. Write result back to offset 0xE_0F20." - * - * Since it is the same register, we do the modification in one step. - */ - if (SVR_MAJ (svr) < 2) { - uint dummy = gur->lbiuiplldcr1; - dummy &= 0x0000FFDF; - dummy |= 0x00000004; - gur->lbiuiplldcr1 = dummy; - } - - lcrr = CONFIG_SYS_LBC_LCRR; - - /* - * Local Bus Clock > 83.3 MHz. According to timing - * specifications set LCRR[EADC] to 2 delay cycles. - */ - if (lbc_mhz > 83) { - lcrr &= ~LCRR_EADC; - lcrr |= LCRR_EADC_2; - } - - /* - * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 - * disable PLL bypass for Local Bus Clock > 83 MHz. - */ - if (lbc_mhz >= 66) - lcrr &= (~LCRR_DBYP); /* DLL Enabled */ - - else - lcrr |= LCRR_DBYP; /* DLL Bypass */ - - lbc->lcrr = lcrr; - asm ("sync;isync;msync"); - - /* - * According to MPC8548ERMAD Rev.1.3 read back LCRR - * and terminate with isync - */ - lcrr = lbc->lcrr; - asm ("isync;"); - - /* let DLL stabilize */ - udelay (500); - -#else /* !CONFIG_MPC8548 */ - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - if (lbc_mhz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | - LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ - - } else if (lbc_mhz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr (); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - udelay (200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm ("sync;isync;msync"); - } -#endif /* !CONFIG_MPC8548 */ - -#ifdef CONFIG_CAN_DRIVER - /* - * According to timing specifications EAD must be - * set if Local Bus Clock is > 83 MHz. - */ - if (lbc_mhz > 83) - set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); - else - set_lbc_or(2, CONFIG_SYS_OR2_CAN); - set_lbc_br(2, CONFIG_SYS_BR2_CAN); - - /* LGPL4 is UPWAIT */ - out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); - - /* Initialize UPMC for CAN: single read */ - upmc_write (0x00, 0xFFFFED00); - upmc_write (0x01, 0xCCFFCC00); - upmc_write (0x02, 0x00FFCF00); - upmc_write (0x03, 0x00FFCF00); - upmc_write (0x04, 0x00FFDC00); - upmc_write (0x05, 0x00FFCF00); - upmc_write (0x06, 0x00FFED00); - upmc_write (0x07, 0x3FFFCC07); - - /* Initialize UPMC for CAN: single write */ - upmc_write (0x18, 0xFFFFED00); - upmc_write (0x19, 0xCCFFEC00); - upmc_write (0x1A, 0x00FFED80); - upmc_write (0x1B, 0x00FFED80); - upmc_write (0x1C, 0x00FFFC00); - upmc_write (0x1D, 0x0FFFEC00); - upmc_write (0x1E, 0x0FFFEF00); - upmc_write (0x1F, 0x3FFFEC05); -#endif /* CONFIG_CAN_DRIVER */ -} - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI1 */ - -void pci_init_board (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int first_free_busno = 0; -#ifdef CONFIG_PCI1 - struct fsl_pci_info pci_info; - int pcie_ep; - - u32 devdisr = in_be32(&gur->devdisr); - - uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; - uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; - uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ - uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI1: %d bit, %s MHz, %s, %s, %s\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333333) ? "33" : - (pci_speed == 66666666) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pcie_ep ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter"); - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); -#ifdef CONFIG_PCIX_CHECK - if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) { - ushort reg16 = - PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | - PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - uint dev = PCI_BDF(0, 0, 0); - - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - puts ("PCI-X will only work at 66 MHz\n"); - - pci_write_config_word(dev, PCIX_COMMAND, reg16); - } -#endif - } else { - printf("PCI1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); -#endif - - fsl_pcie_init_board(first_free_busno); -} - -#ifdef CONFIG_OF_BOARD_SETUP -void ft_board_setup (void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - - FT_FSL_PCI_SETUP; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ -#ifdef CONFIG_PS2MULT - ps2mult_early_init (); -#endif /* CONFIG_PS2MULT */ - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Intialize TSECs first */ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 4f08be61f1c..e905c26c6f0 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -43,8 +43,6 @@ SECTIONS drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable) drivers/rtc/librtc.o (.text*) drivers/misc/libmisc.o (.text*) - *(.text.print_buffer) - *(.text.print_size) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv*) diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 129119528fe..871e052b04e 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -120,7 +120,6 @@ int board_init (void) int board_late_init(void) { -#if defined(CONFIG_SERIAL_MULTI) char *console=getenv("boot_console"); if ((console == NULL) || (strcmp(console,"serial_btuart") && @@ -131,15 +130,9 @@ int board_late_init(void) setenv("stdout",console); setenv("stdin", console); setenv("stderr",console); -#endif return 0; } -struct serial_device *default_serial_console (void) -{ - return &serial_ffuart_device; -} - int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index dfdab9b6f68..26635341e2b 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -50,11 +50,6 @@ int board_init(void) return 0; } -struct serial_device *default_serial_console(void) -{ - return &serial_ffuart_device; -} - int dram_init(void) { #ifndef CONFIG_ONENAND diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 5c84e65a09d..4392779163d 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -33,13 +33,6 @@ unsigned long get_dram_size (void); void sdram_init(void); -/* - * Macros to transform values - * into environment strings. - */ -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - /* ------------------------------------------------------------------------- */ int board_early_init_f (void) @@ -228,7 +221,7 @@ static void w7o_env_init (VPD * vpd) /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ eth = (char *)(vpd->ethAddrs[0]); if (ethaddr - && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) { + && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) { /* Now setup ethaddr */ sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", eth[0], eth[1], eth[2], eth[3], eth[4], diff --git a/board/amirix/ap1000/Makefile b/board/xilinx/zynq/Makefile index 3a22ce62e33..ef4faa125ed 100644 --- a/board/amirix/ap1000/Makefile +++ b/board/xilinx/zynq/Makefile @@ -22,20 +22,27 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o -SOBJS = init.o +COBJS-y := board.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +COBJS := $(sort $(COBJS-y)) + +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -all: $(LIB) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) -$(LIB): $(OBJS) - $(call cmd_link_o_target, $^) +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### diff --git a/board/gth2/flash.c b/board/xilinx/zynq/board.c index 1b3c43c4316..8ed75c3d383 100644 --- a/board/gth2/flash.c +++ b/board/xilinx/zynq/board.c @@ -1,6 +1,5 @@ /* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> * * See file CREDITS for list of people who contributed to this * project. @@ -12,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -22,22 +21,34 @@ */ #include <common.h> +#include <netdev.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +DECLARE_GLOBAL_DATA_PTR; -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) +int board_init(void) +{ + icache_enable(); + + return 0; +} + + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) { - printf ("Skipping flash_init\n"); - return (0); + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0) + ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0); +#endif + + return ret; } +#endif -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +int dram_init(void) { - printf ("write_buff not implemented\n"); - return (-1); + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; } diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 272e59b63a5..e7b2f4d5124 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -39,7 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; #define REBOOT_DO_POST 0x00000001 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -extern env_t *env_ptr; ulong flash_get_size(ulong base, int banknum); void env_crc_update(void); diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 82dfa82688a..579841d1a9c 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -62,11 +62,6 @@ int board_init (void) return 0; } -struct serial_device *default_serial_console (void) -{ - return &serial_stuart_device; -} - int dram_init(void) { pxa2xx_dram_init(); |