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-rw-r--r--board/CZ.NIC/turris_mox/MAINTAINERS6
-rw-r--r--board/CZ.NIC/turris_mox/Makefile5
-rw-r--r--board/CZ.NIC/turris_mox/turris_mox.c127
-rw-r--r--board/CZ.NIC/turris_omnia/turris_omnia.c38
-rw-r--r--board/Marvell/db-88f6820-amc/db-88f6820-amc.c21
-rw-r--r--board/Marvell/db-88f6820-gp/db-88f6820-gp.c21
-rw-r--r--board/gdsys/a38x/controlcenterdc.c22
-rw-r--r--board/solidrun/clearfog/clearfog.c21
8 files changed, 209 insertions, 52 deletions
diff --git a/board/CZ.NIC/turris_mox/MAINTAINERS b/board/CZ.NIC/turris_mox/MAINTAINERS
new file mode 100644
index 00000000000..2b9c1132f5e
--- /dev/null
+++ b/board/CZ.NIC/turris_mox/MAINTAINERS
@@ -0,0 +1,6 @@
+TURRIS OMNIA BOARD
+M: Marek Behún <marek.behun@nic.cz>
+S: Maintained
+F: board/CZ.NIC/turris_mox/
+F: include/configs/turris_mox.h
+F: configs/turris_mox_defconfig
diff --git a/board/CZ.NIC/turris_mox/Makefile b/board/CZ.NIC/turris_mox/Makefile
new file mode 100644
index 00000000000..619704288b3
--- /dev/null
+++ b/board/CZ.NIC/turris_mox/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+
+obj-y := turris_mox.o
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
new file mode 100644
index 00000000000..130d4c606d3
--- /dev/null
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <spi.h>
+#include <linux/string.h>
+
+#ifdef CONFIG_WDT_ARMADA_3720
+#include <wdt.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_WDT_ARMADA_3720
+static struct udevice *watchdog_dev;
+
+void watchdog_reset(void)
+{
+ static ulong next_reset;
+ ulong now;
+
+ if (!watchdog_dev)
+ return;
+
+ now = timer_get_us();
+
+ /* Do not reset the watchdog too often */
+ if (now > next_reset) {
+ wdt_reset(watchdog_dev);
+ next_reset = now + 100000;
+ }
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_WDT_ARMADA_3720
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ printf("Cannot find Armada 3720 watchdog!\n");
+ } else {
+ printf("Enabling Armada 3720 watchdog (3 minutes timeout).\n");
+ wdt_start(watchdog_dev, 180000, 0);
+ }
+#endif
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ struct spi_slave *slave;
+ struct udevice *dev;
+ u8 din[10], dout[10];
+ int ret, i;
+ size_t len = 0;
+ char module_topology[128];
+
+ ret = spi_get_bus_and_cs(0, 1, 20000000, SPI_CPHA, "spi_generic_drv",
+ "mox-modules@1", &dev, &slave);
+ if (ret)
+ goto fail;
+
+ ret = spi_claim_bus(slave);
+ if (ret)
+ goto fail_free;
+
+ memset(din, 0, 10);
+ memset(dout, 0, 10);
+
+ ret = spi_xfer(slave, 80, dout, din, SPI_XFER_ONCE);
+ if (ret)
+ goto fail_release;
+
+ if (din[0] != 0x00 && din[0] != 0xff)
+ goto fail_release;
+
+ printf("Module Topology:\n");
+ for (i = 1; i < 10 && din[i] != 0xff; ++i) {
+ u8 mid = din[i] & 0xf;
+ size_t mlen;
+ const char *mname = "";
+
+ switch (mid) {
+ case 0x1:
+ mname = "sfp-";
+ printf("% 4i: SFP Module\n", i);
+ break;
+ case 0x2:
+ mname = "pci-";
+ printf("% 4i: Mini-PCIe Module\n", i);
+ break;
+ case 0x3:
+ mname = "topaz-";
+ printf("% 4i: Topaz Switch Module\n", i);
+ break;
+ default:
+ printf("% 4i: unknown (ID %i)\n", i, mid);
+ }
+
+ mlen = strlen(mname);
+ if (len + mlen < sizeof(module_topology)) {
+ strcpy(module_topology + len, mname);
+ len += mlen;
+ }
+ }
+ printf("\n");
+
+ module_topology[len > 0 ? len - 1 : 0] = '\0';
+
+ env_set("module_topology", module_topology);
+
+fail_release:
+ spi_release_bus(slave);
+fail_free:
+ spi_free_slave(slave);
+fail:
+ if (ret)
+ printf("Cannot read module topology!\n");
+ return ret;
+}
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 58d1f5fe353..da663cf1bb0 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -27,7 +27,7 @@
# include <wdt.h>
#endif
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -200,7 +200,8 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
-static struct hws_topology_map board_topology_map_1g = {
+static struct mv_ddr_topology_map board_topology_map_1g = {
+ DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
@@ -209,17 +210,20 @@ static struct hws_topology_map board_topology_map_1g = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
- BUS_WIDTH_16, /* memory_width */
- MEM_4G, /* mem_size */
+ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
+ MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- HWS_TEMP_NORMAL, /* temperature */
- HWS_TIM_2T} }, /* timing (force 2t) */
- 5, /* Num Of Bus Per Interface*/
- BUS_MASK_32BIT /* Busses mask */
+ MV_DDR_TEMP_NORMAL, /* temperature */
+ MV_DDR_TIM_2T} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
};
-static struct hws_topology_map board_topology_map_2g = {
+static struct mv_ddr_topology_map board_topology_map_2g = {
+ DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
@@ -228,17 +232,19 @@ static struct hws_topology_map board_topology_map_2g = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
- BUS_WIDTH_16, /* memory_width */
- MEM_8G, /* mem_size */
+ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
+ MV_DDR_DIE_CAP_8GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- HWS_TEMP_NORMAL, /* temperature */
- HWS_TIM_2T} }, /* timing (force 2t) */
- 5, /* Num Of Bus Per Interface*/
- BUS_MASK_32BIT /* Busses mask */
+ MV_DDR_TEMP_NORMAL, /* temperature */
+ MV_DDR_TIM_2T} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
};
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
static int mem = 0;
struct omnia_eeprom oep;
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index ba9738c0f7e..92d7ae77f07 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -11,7 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -55,7 +55,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
-static struct hws_topology_map board_topology_map = {
+static struct mv_ddr_topology_map board_topology_map = {
+ DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
@@ -64,17 +65,19 @@ static struct hws_topology_map board_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1866L, /* speed_bin */
- BUS_WIDTH_8, /* memory_width */
- MEM_2G, /* mem_size */
+ MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
+ MV_DDR_DIE_CAP_2GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- HWS_TEMP_LOW, /* temperature */
- HWS_TIM_DEFAULT} }, /* timing */
- 5, /* Num Of Bus Per Interface*/
- BUS_MASK_32BIT /* Busses mask */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
};
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &board_topology_map;
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index fc405b939b9..a8cfe8af0a8 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -11,7 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -76,7 +76,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
-static struct hws_topology_map board_topology_map = {
+static struct mv_ddr_topology_map board_topology_map = {
+ DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
@@ -85,17 +86,19 @@ static struct hws_topology_map board_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1866L, /* speed_bin */
- BUS_WIDTH_8, /* memory_width */
- MEM_4G, /* mem_size */
+ MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
+ MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- HWS_TEMP_LOW, /* temperature */
- HWS_TIM_DEFAULT} }, /* timing */
- 5, /* Num Of Bus Per Interface*/
- BUS_MASK_32BIT /* Busses mask */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
};
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &board_topology_map;
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index 5599767dffb..320bc100c9d 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -12,7 +12,7 @@
#include <asm/arch/cpu.h>
#include <asm-generic/gpio.h>
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
#include "keyprogram.h"
@@ -39,7 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
-static struct hws_topology_map ddr_topology_map = {
+static struct mv_ddr_topology_map ddr_topology_map = {
+ DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
@@ -48,14 +49,17 @@ static struct hws_topology_map ddr_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
- BUS_WIDTH_16, /* memory_width */
- MEM_4G, /* mem_size */
+ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
+ MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_533, /* frequency */
0, 0, /* cas_wl cas_l */
- HWS_TEMP_LOW, /* temperature */
- HWS_TIM_DEFAULT} }, /* timing */
- 5, /* Num Of Bus Per Interface*/
- BUS_MASK_32BIT /* Busses mask */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
+
};
static struct serdes_map serdes_topology_map[] = {
@@ -121,7 +125,7 @@ void board_pex_config(void)
#endif
}
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
return &ddr_topology_map;
}
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 61de16d19e0..ede303d4ebf 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -11,7 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -69,7 +69,8 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
* be used by the DDR3 init code in the SPL U-Boot version to configure
* the DDR3 controller.
*/
-static struct hws_topology_map board_topology_map = {
+static struct mv_ddr_topology_map board_topology_map = {
+ DEBUG_LEVEL_ERROR,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
{ { { {0x1, 0, 0, 0},
@@ -78,17 +79,19 @@ static struct hws_topology_map board_topology_map = {
{0x1, 0, 0, 0},
{0x1, 0, 0, 0} },
SPEED_BIN_DDR_1600K, /* speed_bin */
- BUS_WIDTH_16, /* memory_width */
- MEM_4G, /* mem_size */
+ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
+ MV_DDR_DIE_CAP_4GBIT, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_wl cas_l */
- HWS_TEMP_LOW, /* temperature */
- HWS_TIM_DEFAULT} }, /* timing */
- 5, /* Num Of Bus Per Interface*/
- BUS_MASK_32BIT /* Busses mask */
+ MV_DDR_TEMP_LOW, /* temperature */
+ MV_DDR_TIM_DEFAULT} }, /* timing */
+ BUS_MASK_32BIT, /* Busses mask */
+ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ { {0} }, /* raw spd data */
+ {0} /* timing parameters */
};
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
/* Return the board topology as defined in the board code */
return &board_topology_map;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 04:50:52 +0000