diff options
Diffstat (limited to 'board')
138 files changed, 17253 insertions, 926 deletions
diff --git a/board/altera/arria5-socdk/socfpga.c b/board/altera/arria5-socdk/socfpga.c index a1dbc492c98..97fb902f8e6 100644 --- a/board/altera/arria5-socdk/socfpga.c +++ b/board/altera/arria5-socdk/socfpga.c @@ -3,83 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fdb64e..f1e6d2b0bce 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -9,19 +9,19 @@ const u8 sys_mgr_init_table[] = { 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ 0, /* EMACIO14 */ 0, /* EMACIO15 */ 0, /* EMACIO16 */ @@ -55,8 +55,8 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO12 */ 2, /* GENERALIO13 */ 2, /* GENERALIO14 */ - 0, /* GENERALIO15 */ - 0, /* GENERALIO16 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ 2, /* GENERALIO17 */ 2, /* GENERALIO18 */ 0, /* GENERALIO19 */ @@ -72,27 +72,27 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed9c15..4abd2e0aacd 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c index a1dbc492c98..97fb902f8e6 100644 --- a/board/altera/cyclone5-socdk/socfpga.c +++ b/board/altera/cyclone5-socdk/socfpga.c @@ -3,83 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile index a35db401b68..b4391a71249 100644 --- a/board/armltd/vexpress64/Makefile +++ b/board/armltd/vexpress64/Makefile @@ -5,4 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := vexpress64.o pcie.o +obj-y := vexpress64.o +obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 7b999e8ef40..b3fb09ca67c 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -87,7 +87,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH); writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); - printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", + debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr, ((u64)1) << window_size, trsl_param); } @@ -191,7 +191,5 @@ void xr3pci_init(void) void vexpress64_pcie_init(void) { -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO xr3pci_init(); -#endif } diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index f4e80840b2e..6efc8c183a6 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -28,6 +28,13 @@ U_BOOT_DEVICE(vexpress_serials) = { .platdata = &serial_platdata, }; +/* This function gets replaced by platforms supporting PCIe. + * The replacement function, eg. on Juno, initialises the PCIe bus. + */ +__weak void vexpress64_pcie_init(void) +{ +} + int board_init(void) { vexpress64_pcie_init(); @@ -44,8 +51,10 @@ void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#ifdef PHYS_SDRAM_2 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif } /* diff --git a/board/atmel/sama5d2_xplained/Kconfig b/board/atmel/sama5d2_xplained/Kconfig new file mode 100644 index 00000000000..55712e97454 --- /dev/null +++ b/board/atmel/sama5d2_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_XPLAINED + +config SYS_BOARD + default "sama5d2_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_xplained" + +endif diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS new file mode 100644 index 00000000000..ff9c86f5380 --- /dev/null +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 XPLAINED BOARD +M: Wenyou Yang <wenyou.yang@atmel.com> +S: Maintained +F: board/atmel/sama5d2_xplained/ +F: include/configs/sama5d2_xplained.h +F: configs/sama5d2_xplained_mmc_defconfig +F: configs/sama5d2_xplained_spiflash_defconfig diff --git a/board/atmel/sama5d2_xplained/Makefile b/board/atmel/sama5d2_xplained/Makefile new file mode 100644 index 00000000000..420870b561a --- /dev/null +++ b/board/atmel/sama5d2_xplained/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015 Atmel Corporation +# Wenyou Yang <wenyou.yang@atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_xplained.o diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c new file mode 100644 index 00000000000..0b3397fa090 --- /dev/null +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <atmel_hlcdc.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 41, + .vl_left_margin = 2, + .vl_right_margin = 2, + .vl_vsync_len = 11, + .vl_upper_margin = 2, + .vl_lower_margin = 2, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void board_lcd_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ + + /* LCDDAT0 */ + /* LCDDAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ + + /* LCDDAT8 */ + /* LCDDAT9 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ + + /* LCDD16 */ + /* LCDD17 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size; + int i; + char temp[32]; + + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("2015 ATMEL Corp\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + lcd_printf("%ld MB SDRAM\n", dram_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD */ + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_sdhci0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, + GCK_CSS_PLLA_CLK, 1); +} + +static void board_sdhci1_hw_init(void) +{ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC1); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, + GCK_CSS_PLLA_CLK, 1); +} + +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_ATMEL_SDHCI0 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1); +#endif + + return 0; +} + +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart1_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI +#ifdef CONFIG_ATMEL_SDHCI0 + board_sdhci0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + board_sdhci1_hw_init(); +#endif +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_LCD + board_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c index 20eb19142a9..b3a4a4144d6 100644 --- a/board/broadcom/bcm28155_ap/bcm28155_ap.c +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c @@ -13,7 +13,7 @@ #include <asm/arch/sysmap.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <g_dnl.h> #define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 @@ -95,14 +95,14 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_USB_GADGET -static struct s3c_plat_otg_data bcm_otg_data = { +static struct dwc2_plat_otg_data bcm_otg_data = { .regs_otg = HSOTG_BASE_ADDR }; int board_usb_init(int index, enum usb_init_type init) { - debug("%s: performing s3c_udc_probe\n", __func__); - return s3c_udc_probe(&bcm_otg_data); + debug("%s: performing dwc2_udc_probe\n", __func__); + return dwc2_udc_probe(&bcm_otg_data); } int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c index 1c74a0f7d0c..340a009c895 100644 --- a/board/corscience/tricorder/tricorder-eeprom.c +++ b/board/corscience/tricorder/tricorder-eeprom.c @@ -77,17 +77,13 @@ static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) { -#ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif memset(eeprom, 0, TRICORDER_EEPROM_SIZE); i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); -#ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); -#endif if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, @@ -138,9 +134,6 @@ int tricorder_eeprom_write(unsigned devaddr, const char *name, int ret; unsigned char *p; int i; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus; -#endif memset(eeprom, 0, TRICORDER_EEPROM_SIZE); memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); @@ -172,33 +165,23 @@ int tricorder_eeprom_write(unsigned devaddr, const char *name, print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); #endif -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif + eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM); - /* do page write to the eeprom */ - for (i = 0, p = (unsigned char *)&eeprom; - i < sizeof(eeprom); - i += 32, p += 32) { - ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min(sizeof(eeprom) - i, 32)); - if (ret) - break; - udelay(5000); /* 5ms write cycle timing */ - } + ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom, + TRICORDER_EEPROM_SIZE); + if (ret) + printf("Tricorder: Could not write EEPROM content!\n"); - ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, + ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify, TRICORDER_EEPROM_SIZE); + if (ret) + printf("Tricorder: Could not read EEPROM content!\n"); if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { printf("Tricorder: Could not verify EEPROM content!\n"); ret = 1; } -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif return ret; } @@ -206,7 +189,7 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc == 3) { ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - eeprom_init(); + if (strcmp(argv[1], "read") == 0) { int rcode; @@ -220,7 +203,6 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *version = argv[4]; char *serial = argv[5]; char *interface = NULL; - eeprom_init(); if (argc == 7) interface = argv[6]; diff --git a/board/denx/mcvevk/socfpga.c b/board/denx/mcvevk/socfpga.c index 1a23a7d88c8..6be58f047f7 100644 --- a/board/denx/mcvevk/socfpga.c +++ b/board/denx/mcvevk/socfpga.c @@ -3,43 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/ebv/socrates/MAINTAINERS b/board/ebv/socrates/MAINTAINERS new file mode 100644 index 00000000000..e48236fc8fc --- /dev/null +++ b/board/ebv/socrates/MAINTAINERS @@ -0,0 +1,6 @@ +SOCRATES BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/ebv/socrates/ +F: include/configs/socfpga_socrates.h +F: configs/socfpga_socrates_defconfig diff --git a/board/ebv/socrates/Makefile b/board/ebv/socrates/Makefile new file mode 100644 index 00000000000..86f9b78cad7 --- /dev/null +++ b/board/ebv/socrates/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h new file mode 100644 index 00000000000..f1bbe685513 --- /dev/null +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00004824, + 0x01209000, + 0x82400000, + 0x00018004, + 0x00000000, + 0x00004000, + 0x00002412, + 0x00904800, + 0x41200000, + 0x80000002, + 0x00000904, + 0x00002000, + 0x00001209, + 0x00482400, + 0x20900000, + 0x40000001, + 0x00000482, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00009048, + 0x02412000, + 0x048000C0, + 0x00000009, + 0x00002412, + 0x00008000, + 0x00004824, + 0x01209000, + 0x82400000, + 0x00000004, + 0x00001209, + 0x00004000, + 0x00002412, + 0x00904800, + 0x41200000, + 0x80000002, + 0x00000904, + 0x00002000, + 0x06001209, + 0x00482400, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x80001000, + 0x00000904, + 0x00241200, + 0x90480000, + 0x20003000, + 0x00000241, + 0x00000800, + 0x00000000, + 0x00000000, + 0x48240000, + 0x90000000, + 0x00000120, + 0x00000400, + 0x00000000, + 0x00090480, + 0x00000003, + 0x00000000, + 0x00000000, + 0x90000200, + 0x00600120, + 0x00000000, + 0x12090000, + 0x24000600, + 0x00000048, + 0x48000100, + 0x00300090, + 0xC0024120, + 0x09048000, + 0x12000300, + 0x000C0024, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x30009048, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C002412, + 0x00008000, + 0x18004824, + 0x00000000, + 0x82400000, + 0x00018004, + 0x06001209, + 0x00004000, + 0x20002412, + 0x00904800, + 0x00000030, + 0x80000000, + 0x03000904, + 0x00002000, + 0x10001209, + 0x00482400, + 0x20900000, + 0x40010001, + 0x00000482, + 0x80001000, + 0x00000904, + 0x00000000, + 0x90480000, + 0x20008000, + 0x00C00241, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0CC20D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x45034030, + 0x12481A01, + 0x80A280D0, + 0x34030C06, + 0x01A01450, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD00A281A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D5, + 0xF6D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD949247A, + 0x1EF228A3, + 0x88F6D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF3CF23D5, + 0xF4D1451E, + 0x034A9248, + 0x821A038E, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D9, + 0xF4D1451E, + 0x034A9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF228A3, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x08864000, + 0x49247A02, + 0xF3CF23D9, + 0xF4D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4DE79, + 0x000342A2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/pinmux_config.h b/board/ebv/socrates/qts/pinmux_config.h new file mode 100644 index 00000000000..4bb654fe297 --- /dev/null +++ b/board/ebv/socrates/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h new file mode 100644 index 00000000000..c5aea9d3149 --- /dev/null +++ b/board/ebv/socrates/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h new file mode 100644 index 00000000000..cf9d1d3affd --- /dev/null +++ b/board/ebv/socrates/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 375 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 82 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 82 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080221, + 0x10080320, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080241, + 0x100802c0, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c new file mode 100644 index 00000000000..97fb902f8e6 --- /dev/null +++ b/board/ebv/socrates/socfpga.c @@ -0,0 +1,6 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/evb_rk3036/evb_rk3036/Kconfig new file mode 100644 index 00000000000..ae2a9ebe479 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3036 + +config SYS_BOARD + default "evb_rk3036" + +config SYS_VENDOR + default "evb_rk3036" + +config SYS_CONFIG_NAME + default "evb_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/evb_rk3036/evb_rk3036/MAINTAINERS new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/MAINTAINERS diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/evb_rk3036/evb_rk3036/Makefile new file mode 100644 index 00000000000..0403836e131 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3036.o diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/evb_rk3036/evb_rk3036/evb_rk3036.c new file mode 100644 index 00000000000..f5758b1e9a7 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/evb_rk3036.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <asm/arch/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_ddr_config(struct rk3036_ddr_config *config) +{ + /* K4B4G1646Q config */ + config->ddr_type = 3; + config->rank = 2; + config->cs0_row = 15; + config->cs1_row = 15; + + /* 8bank */ + config->bank = 3; + config->col = 10; + + /* 16bit bw */ + config->bw = 1; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 26cf5175c77..b5025ab14e8 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -52,6 +52,8 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, if (!ph) return -FDT_ERR_BADPHANDLE; + ph = cpu_to_fdt32(ph); + offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); if (offset < 0) return offset; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 73b6718db9c..b510c71c409 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -15,7 +15,7 @@ #include <u-boot/rsa-mod-exp.h> #include <hash.h> #include <fsl_secboot_err.h> -#ifndef CONFIG_MPC85xx +#ifdef CONFIG_LS102XA #include <asm/arch/immap_ls102xa.h> #endif @@ -99,7 +99,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN)) + if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, + barker_code, ESBC_BARKER_LEN)) return -1; *csf_addr = csf_hdr_addr; @@ -117,7 +118,7 @@ static int get_ie_info_addr(u32 *ie_addr) if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; - hdr = (struct fsl_secboot_img_hdr *)csf_addr; + hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; /* For SoC's with Trust Architecture v1 with corenet bus * the sg table field in CSF header has absolute address @@ -130,7 +131,7 @@ static int get_ie_info_addr(u32 *ie_addr) (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else - sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + + sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + (u32)hdr->psgtable); #endif @@ -379,8 +380,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { ret = algo->hash_update(algo, ctx, - (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off), - img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); srk = 1; } #endif @@ -438,8 +439,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { ret = algo->hash_update(algo, ctx, - (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off), - img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); key_hash = 1; } #endif @@ -454,8 +455,13 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) return ret; /* Update hash for actual Image */ +#ifdef CONFIG_ESBC_ADDR_64BIT ret = algo->hash_update(algo, ctx, - (u8 *)img->hdr.pimg, img->hdr.img_size, 1); + (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1); +#else + ret = algo->hash_update(algo, ctx, + (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1); +#endif if (ret) return ret; @@ -533,7 +539,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) { char buf[20]; struct fsl_secboot_img_hdr *hdr = &img->hdr; - void *esbc = (u8 *)img->ehdrloc; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; #ifdef CONFIG_KEY_REVOCATION u32 ret; @@ -549,7 +555,11 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; +#ifdef CONFIG_ESBC_ADDR_64BIT + sprintf(buf, "%llx", hdr->pimg64); +#else sprintf(buf, "%x", hdr->pimg); +#endif setenv("img_addr", buf); if (!hdr->img_size) @@ -594,7 +604,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (!key_found && check_ie(img)) { if (get_ie_info_addr(&img->ie_addr)) return ERROR_IE_TABLE_NOT_FOUND; - ie_info = (struct ie_key_info *)img->ie_addr; + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; if (ie_info->num_keys == 0 || ie_info->num_keys > 32) return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; @@ -748,7 +758,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, hdr = &img->hdr; img->ehdrloc = addr; - esbc = (u8 *)img->ehdrloc; + esbc = (u8 *)(uintptr_t)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 6b8af14e7ae..f1bed51d304 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -7,7 +7,12 @@ #include <common.h> #include <command.h> #include <i2c.h> +#include <asm/io.h> +#ifdef CONFIG_LS1043A +#include <asm/arch/immap_lsch2.h> +#else #include <asm/immap_85xx.h> +#endif #include "vid.h" DECLARE_GLOBAL_DATA_PTR; @@ -240,7 +245,11 @@ static int set_voltage_to_IR(int i2caddress, int vdd) * SoC before converting into an IR VID value */ vdd += board_vdd_drop_compensation(); +#ifdef CONFIG_LS1043A + vid = DIV_ROUND_UP(vdd - 265, 5); +#else vid = DIV_ROUND_UP(vdd - 245, 5); +#endif ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, 1, (void *)&vid, sizeof(vid)); @@ -276,8 +285,12 @@ static int set_voltage(int i2caddress, int vdd) int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); +#ifdef CONFIG_LS1043A + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#else ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif u32 fusesr; u8 vid; int vdd_target, vdd_current, vdd_last; @@ -352,12 +365,21 @@ int adjust_vdd(ulong vdd_override) * | T | | | | | * ------------------------------------------------------ */ +#ifdef CONFIG_LS1043A + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; + } +#else vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & FSL_CORENET_DCFG_FUSESR_VID_MASK; } +#endif vdd_target = vdd[vid]; /* check override variable for overriding VDD */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d889ad50fd0..be3358a564a 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> @@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -205,40 +193,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - } + arch_soc_init(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4918c1192e2..8eaff5f0ced 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_sata.h> #include <hwconfig.h> #include <mmc.h> @@ -138,17 +139,6 @@ int checkboard(void) return 0; } -unsigned int get_soc_major_rev(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr, major; - - svr = in_be32(&gur->svr); - major = SVR_MAJ(svr); - - return major; -} - void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -394,8 +384,6 @@ conflict: int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -407,33 +395,7 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif -#ifdef CONFIG_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - -#ifdef CONFIG_FSL_QSPI - out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); -#endif - - /* Configure Little endian for SAI, ASRC and SPDIF */ - out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); - - /* - * Enable snoop requests and DVM message requests for - * Slave insterface S4 (A7 core cluster) - */ - out_le32(&cci->slave[4].snoop_ctrl, - CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override - * Register All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - } + arch_soc_init(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) { diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig new file mode 100644 index 00000000000..7e27f8f5b13 --- /dev/null +++ b/board/freescale/ls1043aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1043AQDS + +config SYS_BOARD + default "ls1043aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1043aqds" + +endif diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS new file mode 100644 index 00000000000..0c7f648b6cb --- /dev/null +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -0,0 +1,9 @@ +LS1043AQDS BOARD +M: Mingkai Hu <Mingkai.Hu@freescale.com> +S: Maintained +F: board/freescale/ls1043aqds/ +F: include/configs/ls1043aqds.h +F: configs/ls1043aqds_defconfig +F: configs/ls1043aqds_nor_ddr3_defconfig +F: configs/ls1043aqds_nand_defconfig +F: configs/ls1043aqds_sdcard_ifc_defconfig diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile new file mode 100644 index 00000000000..f727bfd622e --- /dev/null +++ b/board/freescale/ls1043aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ddr.o +obj-y += eth.o +obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README new file mode 100644 index 00000000000..6261a778aaa --- /dev/null +++ b/board/freescale/ls1043aqds/README @@ -0,0 +1,96 @@ +Overview +-------- +The LS1043A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043AQDS provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. + +LS1043A SoC Overview +-------------------- +The LS1043A integrated multicore processor combines four ARM Cortex-A53 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1043A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A53 CPUs + - 1 MB unified L2 Cache + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Ethernet interfaces by FMan + - Up to 1 x XFI supporting 10G interface + - Up to 1 x QSGMII + - Up to 4 x SGMII supporting 1000Mbps + - Up to 2 x SGMII supporting 2500Mbps + - Up to 2 x RGMII supporting 1000Mbps + - High-speed peripheral interfaces + - Three PCIe 2.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 + + LS1043AQDS board Overview + ----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - XFI + - DDR Controller + - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - PromJet Port + - FPGA connection + - USB 3.0 + - Three high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - The other two USB 3.0 ports configured as OTG with micro-AB connector + - SDHC port connects directly to an adapter card slot, featuring: + - Optional clock feedback paths, and optional high-speed voltage translation assistance + - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC + - eMMC memory devices + - DSPI: Onboard support for three SPI flash memory devices + - 4 I2C controllers + - One SATA onboard connectors + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c new file mode 100644 index 00000000000..42d906824ae --- /dev/null +++ b/board/freescale/ls1043aqds/ddr.c @@ -0,0 +1,140 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#ifdef CONFIG_FSL_DEEP_SLEEP +#include <fsl_sleep.h> +#endif +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + return dram_size; +} + +void dram_init_banksize(void) +{ + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif +} diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h new file mode 100644 index 00000000000..8adb6600125 --- /dev/null +++ b/board/freescale/ls1043aqds/ddr.h @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c new file mode 100644 index 00000000000..b7fc360e2cc --- /dev/null +++ b/board/freescale/ls1043aqds/eth.c @@ -0,0 +1,492 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <fsl_dtsec.h> +#include <malloc.h> +#include <asm/arch/fsl_serdes.h> + +#include "../common/qixis.h" +#include "../common/fman.h" +#include "ls1043aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT4 5 +#define EMI2 6 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "LS1043AQDS_MDIO_RGMII1", + "LS1043AQDS_MDIO_RGMII2", + "LS1043AQDS_MDIO_SLOT1", + "LS1043AQDS_MDIO_SLOT2", + "LS1043AQDS_MDIO_SLOT3", + "LS1043AQDS_MDIO_SLOT4", + "NULL", +}; + +/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +static u8 lane_to_slot[] = {1, 2, 3, 4}; + +static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI2) + return NULL; + + name = ls1043aqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct ls1043aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1043aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, + regnum, value); +} + +static int ls1043aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1043aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1043aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1043aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1043aqds_mdio_read; + bus->write = ls1043aqds_mdio_write; + bus->reset = ls1043aqds_mdio_reset; + sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + if (port == FM1_DTSEC9) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s1_p1"); + } else if (port == FM1_DTSEC2) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s2_p1"); + } else if (port == FM1_DTSEC5) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s3_p1"); + } else if (port == FM1_DTSEC6) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii_riser_s4_p1"); + } + } else if (fm_info_get_enet_if(port) == + PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5G SGMII interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 1000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 2.5G SGMII */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "sgmii-2500"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (mdio_mux[port]) { + case EMI1_SLOT1: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s1_p4"); + break; + default: + break; + } + break; + case EMI1_SLOT2: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii_s2_p4"); + break; + default: + break; + } + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + port == FM1_10GEC1) { + /* XFI interface */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1_slot4"); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_XGMII: + break; + default: + break; + } + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x2555: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + break; + case 0x4555: + case 0x4558: + /* QSGMII on lane A, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S1); + break; + case 0x1355: + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x2355: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x3335: + /* SGMII on lane C, MAC 5 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3355: + case 0x3358: + /* SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3555: + case 0x3558: + /* SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x1455: + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2455: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2255: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* 2.5G SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, 2); + break; + case 0x3333: + /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, + SGMII_CARD_PORT1_PHY_ADDR); + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + } + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c new file mode 100644 index 00000000000..d6696ca8120 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -0,0 +1,333 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/fdt.h> +#include <asm/arch/soc.h> +#include <ahci.h> +#include <hwconfig.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_ifc.h> +#include <spl.h> + +#include "../common/qixis.h" +#include "ls1043aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_GPIO, +}; + +/* LS1043AQDS serdes mux */ +#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ +#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ +#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ +#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ +#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ +#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ +#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ +#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ + +int checkboard(void) +{ + char buf[64]; +#ifndef CONFIG_SD_BOOT + u8 sw; +#endif + + puts("Board: LS1043AQDS, boot from "); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +bool if_board_diff_clk(void) +{ + u8 diff_conf = QIXIS_READ(brdcfg[11]); + + return diff_conf & 0x40; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + gd->ram_size = initdram(0); + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +void board_retimer_init(void) +{ + u8 reg; + + /* Retimer is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); + reg = I2C_MUX_CH5; + i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); + reg |= 0x24; + i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + reg &= 0x8f; + i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + reg &= 0x3f; + reg |= 0x20; + i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); + reg = 0xb2; + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} +#endif + +int config_board_mux(int ctrl_type) +{ + u8 reg14; + + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_GPIO: + reg14 = (reg14 & (~0x30)) | 0x20; + break; + default: + puts("Unsupported mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + return 0; +} + + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + if (hwconfig("gpio")) + config_board_mux(MUX_TYPE_GPIO); + + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + board_retimer_init(); + +#ifdef CONFIG_SYS_FSL_SERDES + config_serdes_mux(); +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg new file mode 100644 index 00000000000..f072274f474 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/board/freescale/ls1043aqds/ls1043aqds_qixis.h new file mode 100644 index 00000000000..8783be89271 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_qixis.h @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg new file mode 100644 index 00000000000..d87058b7efe --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +08100010 0a000000 00000000 00000000 +14550002 80004012 e0106000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg new file mode 100644 index 00000000000..b6b5e0b1018 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable IFC; disable QSPI +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index efca5bf2455..84ffb638d8e 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -7,3 +7,8 @@ F: include/configs/ls1043ardb.h F: configs/ls1043ardb_defconfig F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig + +LS1043A_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal@freescale.com> +S: Maintained +F: configs/ls1043ardb_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index b181579e8e4..11bc0f24d9a 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -186,6 +186,28 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 9032ed36c85..c8f723a1085 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -18,6 +18,8 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <environment.h> +#include <fsl_sec.h> #include "cpld.h" DECLARE_GLOBAL_DATA_PTR; @@ -69,7 +71,23 @@ int dram_init(void) int board_early_init_f(void) { + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + return 0; } @@ -107,13 +125,37 @@ int config_board_mux(void) int misc_init_r(void) { config_board_mux(); - +#ifdef CONFIG_SECURE_BOOT + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif return 0; } #endif int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg index 935ffc01021..d87058b7efe 100644 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # serdes protocol -0810000f 0c000000 00000000 00000000 -14550002 80004012 e0106000 61002000 +08100010 0a000000 00000000 00000000 +14550002 80004012 e0106000 c1002000 00000000 00000000 00000000 00038800 00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg index 28cd95859d2..e2ee34b7dfc 100644 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # RCW -0810000f 0c000000 00000000 00000000 -14550002 80004012 60040000 61002000 +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 00000000 00000000 00000000 00038800 00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2080a/Kconfig index 042f85b3670..0b938ffb541 100644 --- a/board/freescale/ls2085a/Kconfig +++ b/board/freescale/ls2080a/Kconfig @@ -1,7 +1,7 @@ -if TARGET_LS2085A_EMU +if TARGET_LS2080A_EMU config SYS_BOARD - default "ls2085a" + default "ls2080a" config SYS_VENDOR default "freescale" @@ -10,14 +10,14 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085a_emu" + default "ls2080a_emu" endif -if TARGET_LS2085A_SIMU +if TARGET_LS2080A_SIMU config SYS_BOARD - default "ls2085a" + default "ls2080a" config SYS_VENDOR default "freescale" @@ -26,6 +26,6 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085a_simu" + default "ls2080a_simu" endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS new file mode 100644 index 00000000000..03ca168f154 --- /dev/null +++ b/board/freescale/ls2080a/MAINTAINERS @@ -0,0 +1,10 @@ +LS2080A BOARD +M: York Sun <yorksun@freescale.com> +S: Maintained +F: board/freescale/ls2080a/ +F: include/configs/ls2080a_emu.h +F: configs/ls2080a_emu_defconfig +F: include/configs/ls2080a_simu.h +F: configs/ls2080a_simu_defconfig +F: configs/ls2085a_emu_defconfig +F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile new file mode 100644 index 00000000000..47c7c748ea1 --- /dev/null +++ b/board/freescale/ls2080a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014-15 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls2080a.o +obj-y += ddr.o diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2080a/README index bc1d0bb4a70..7e53f1f1e4e 100644 --- a/board/freescale/ls2085a/README +++ b/board/freescale/ls2080a/README @@ -1,4 +1,4 @@ -Freescale ls2085a_emu +Freescale ls2080a_emu This is a emulator target with limited peripherals. diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2080a/ddr.c index 4884fa24d04..56c5d96e99d 100644 --- a/board/freescale/ls2085a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -71,7 +71,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -79,6 +79,7 @@ found: popts->burst_length = DDR_BL8; popts->bstopre = 0; /* enable auto precharge */ } +#endif /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed @@ -174,14 +175,29 @@ void dram_init_banksize(void) phys_size_t dp_ddr_size; #endif + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2080a/ddr.h index 9958a68e3ec..9958a68e3ec 100644 --- a/board/freescale/ls2085a/ddr.h +++ b/board/freescale/ls2080a/ddr.h diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2080a/ls2080a.c index 27481e2ba3a..7bce8b0772a 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -41,11 +41,13 @@ void detail_board_ddr_info(void) puts("\nDDR "); print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } +#endif } int dram_init(void) @@ -66,23 +68,6 @@ int arch_misc_init(void) } #endif -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - int board_eth_init(bd_t *bis) { int error = 0; diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig index 8d6acbac93c..2f997e9de1a 100644 --- a/board/freescale/ls2085aqds/Kconfig +++ b/board/freescale/ls2080aqds/Kconfig @@ -1,8 +1,8 @@ -if TARGET_LS2085AQDS +if TARGET_LS2080AQDS config SYS_BOARD - default "ls2085aqds" + default "ls2080aqds" config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085aqds" + default "ls2080aqds" endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS new file mode 100644 index 00000000000..6f99ad0d912 --- /dev/null +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -0,0 +1,10 @@ +LS2080A BOARD +M: Prabhakar Kushwaha <prabhakar@freescale.com> +S: Maintained +F: board/freescale/ls2080aqds/ +F: board/freescale/ls2080a/ls2080aqds.c +F: include/configs/ls2080aqds.h +F: configs/ls2080aqds_defconfig +F: configs/ls2080aqds_nand_defconfig +F: configs/ls2085aqds_defconfig +F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2080aqds/Makefile index da69a7d22d6..e0da8a5d77a 100644 --- a/board/freescale/ls2085aqds/Makefile +++ b/board/freescale/ls2080aqds/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085aqds.o +obj-y += ls2080aqds.o obj-y += ddr.o obj-y += eth.o diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2080aqds/README index e4a6f69bfcf..375e97c9b03 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2080aqds/README @@ -1,19 +1,19 @@ Overview -------- -The LS2085A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A -Layerscape Architecture processor. The LS2085AQDS provides validation and -SW development platform for the Freescale LS2085A processor series, with +The LS2080A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A +Layerscape Architecture processor. The LS2080AQDS provides validation and +SW development platform for the Freescale LS2080A processor series, with a complete debugging environment. -LS2085A SoC Overview +LS2080A SoC Overview ------------------ -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. -The LS2085A SoC includes the following function and features: +The LS2080A SoC includes the following function and features: - Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC @@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities - LS2085AQDS board Overview + LS2080AQDS board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 @@ -172,7 +172,7 @@ Supported PHY addresses during SGMII: #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -Mapping DPMACx to PHY during QSGMII +Mapping DPMACx to PHY during SGMII DPMAC1 -> PHY1-P0 DPMAC2 -> PHY2-P0 DPMAC3 -> PHY3-P0 diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2080aqds/ddr.c index 8d71ae12646..9fb5e112db0 100644 --- a/board/freescale/ls2085ardb/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; int slot; @@ -79,7 +81,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -114,6 +116,7 @@ found: pdimm[slot].dq_mapping[16] = 0; pdimm[slot].dq_mapping[17] = 0; } +#endif /* To work at higher than 1333MT/s */ popts->half_strength_driver_enable = 0; /* @@ -131,10 +134,18 @@ found: popts->zq_en = 1; if (ddr_freq < 2350) { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } } else { popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); @@ -164,14 +175,29 @@ void dram_init_banksize(void) phys_size_t dp_ddr_size; #endif + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h index b76ea61ba0b..b76ea61ba0b 100644 --- a/board/freescale/ls2085aqds/ddr.h +++ b/board/freescale/ls2080aqds/ddr.h diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2080aqds/eth.c index b8a2bf49e68..0637ecf2a7f 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -18,16 +18,16 @@ #include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2080aqds_qixis.h" #ifdef CONFIG_FSL_MC_ENET - /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks. + /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H * Bank 2 -> Lanes A,B, C, D, E, F, G, H */ - /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here + /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here * means that the mapping must be determined dynamically, or that the lane * maps to something other than a board slot. */ @@ -74,16 +74,16 @@ static int sgmii_riser_phy_addr[] = { #define SFP_TX 0 static const char * const mdio_names[] = { - "LS2085A_QDS_MDIO0", - "LS2085A_QDS_MDIO1", - "LS2085A_QDS_MDIO2", - "LS2085A_QDS_MDIO3", - "LS2085A_QDS_MDIO4", - "LS2085A_QDS_MDIO5", + "LS2080A_QDS_MDIO0", + "LS2080A_QDS_MDIO1", + "LS2080A_QDS_MDIO2", + "LS2080A_QDS_MDIO3", + "LS2080A_QDS_MDIO4", + "LS2080A_QDS_MDIO5", DEFAULT_WRIOP_MDIO2_NAME, }; -struct ls2085a_qds_mdio { +struct ls2080a_qds_mdio { u8 muxval; struct mii_dev *realbus; }; @@ -95,7 +95,7 @@ static void sgmii_configure_repeater(int serdes_port) int i, j, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; - char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"}; + char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60}; uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; @@ -222,7 +222,7 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - const char *dev = "LS2085A_QDS_MDIO0"; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; @@ -318,7 +318,7 @@ error: return; } -static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) +static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; } @@ -326,7 +326,7 @@ static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) struct mii_dev *mii_dev_for_muxval(u8 muxval) { struct mii_dev *bus; - const char *name = ls2085a_qds_mdio_name_for_muxval(muxval); + const char *name = ls2080a_qds_mdio_name_for_muxval(muxval); if (!name) { printf("No bus for muxval %x\n", muxval); @@ -343,7 +343,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } -static void ls2085a_qds_enable_SFP_TX(u8 muxval) +static void ls2080a_qds_enable_SFP_TX(u8 muxval) { u8 brdcfg9; @@ -353,7 +353,7 @@ static void ls2085a_qds_enable_SFP_TX(u8 muxval) QIXIS_WRITE(brdcfg[9], brdcfg9); } -static void ls2085a_qds_mux_mdio(u8 muxval) +static void ls2080a_qds_mux_mdio(u8 muxval) { u8 brdcfg4; @@ -365,54 +365,54 @@ static void ls2085a_qds_mux_mdio(u8 muxval) } } -static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr, +static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr, int devad, int regnum) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; - ls2085a_qds_mux_mdio(priv->muxval); + ls2080a_qds_mux_mdio(priv->muxval); return priv->realbus->read(priv->realbus, addr, devad, regnum); } -static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, +static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, int regnum, u16 value) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; - ls2085a_qds_mux_mdio(priv->muxval); + ls2080a_qds_mux_mdio(priv->muxval); return priv->realbus->write(priv->realbus, addr, devad, regnum, value); } -static int ls2085a_qds_mdio_reset(struct mii_dev *bus) +static int ls2080a_qds_mdio_reset(struct mii_dev *bus) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; return priv->realbus->reset(priv->realbus); } -static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval) +static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) { - struct ls2085a_qds_mdio *pmdio; + struct ls2080a_qds_mdio *pmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { - printf("Failed to allocate ls2085a_qds MDIO bus\n"); + printf("Failed to allocate ls2080a_qds MDIO bus\n"); return -1; } pmdio = malloc(sizeof(*pmdio)); if (!pmdio) { - printf("Failed to allocate ls2085a_qds private data\n"); + printf("Failed to allocate ls2080a_qds private data\n"); free(bus); return -1; } - bus->read = ls2085a_qds_mdio_read; - bus->write = ls2085a_qds_mdio_write; - bus->reset = ls2085a_qds_mdio_reset; - sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval)); + bus->read = ls2080a_qds_mdio_read; + bus->write = ls2080a_qds_mdio_write; + bus->reset = ls2080a_qds_mdio_reset; + sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); @@ -474,8 +474,8 @@ static void initialize_dpmac_to_slot(void) serdes1_prtcl); break; default: - printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + __func__, serdes1_prtcl); break; } @@ -505,13 +505,13 @@ static void initialize_dpmac_to_slot(void) } break; default: - printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); + printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", + __func__ , serdes2_prtcl); break; } } -void ls2085a_handle_phy_interface_sgmii(int dpmac_id) +void ls2080a_handle_phy_interface_sgmii(int dpmac_id) { int lane, slot; struct mii_dev *bus; @@ -580,8 +580,8 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) } break; default: - printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + __func__ , serdes1_prtcl); break; } @@ -626,13 +626,13 @@ serdes2: } break; default: - printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); + printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", + __func__, serdes2_prtcl); break; } } -void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) +void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) { int lane = 0, slot; struct mii_dev *bus; @@ -706,7 +706,7 @@ void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) qsgmii_configure_repeater(dpmac_id); } -void ls2085a_handle_phy_interface_xsgmii(int i) +void ls2080a_handle_phy_interface_xsgmii(int i) { struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -725,7 +725,7 @@ void ls2085a_handle_phy_interface_xsgmii(int i) * error. */ wriop_set_phy_address(i, i + 4); - ls2085a_qds_enable_SFP_TX(SFP_TX); + ls2080a_qds_enable_SFP_TX(SFP_TX); break; default: @@ -778,25 +778,25 @@ int board_eth_init(bd_t *bis) fm_memac_mdio_init(bis, memac_mdio1_info); /* Register the muxing front-ends to the MDIO buses */ - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: - ls2085a_handle_phy_interface_qsgmii(i); + ls2080a_handle_phy_interface_qsgmii(i); break; case PHY_INTERFACE_MODE_SGMII: - ls2085a_handle_phy_interface_sgmii(i); + ls2080a_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_XGMII: - ls2085a_handle_phy_interface_xsgmii(i); + ls2080a_handle_phy_interface_xsgmii(i); break; default: break; diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index b02d6e86b43..aa256a225be 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -21,7 +21,7 @@ #include <hwconfig.h> #include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2080aqds_qixis.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -226,11 +226,13 @@ void detail_board_ddr_info(void) puts("\nDDR "); print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } +#endif } int dram_init(void) @@ -251,23 +253,6 @@ int arch_misc_init(void) } #endif -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { @@ -294,6 +279,7 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + int err; u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -309,7 +295,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); - fsl_mc_ldpaa_exit(bd); + err = fsl_mc_ldpaa_exit(bd); + if (err) + return err; #endif return 0; diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h index e281e5ffe00..e281e5ffe00 100644 --- a/board/freescale/ls2085aqds/ls2085aqds_qixis.h +++ b/board/freescale/ls2080aqds/ls2080aqds_qixis.h diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig index cb40db9b55d..fe02575cf98 100644 --- a/board/freescale/ls2085ardb/Kconfig +++ b/board/freescale/ls2080ardb/Kconfig @@ -1,8 +1,8 @@ -if TARGET_LS2085ARDB +if TARGET_LS2080ARDB config SYS_BOARD - default "ls2085ardb" + default "ls2080ardb" config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-layerscape" config SYS_CONFIG_NAME - default "ls2085ardb" + default "ls2080ardb" endif diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS new file mode 100644 index 00000000000..c9f3459f785 --- /dev/null +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -0,0 +1,10 @@ +LS2080A BOARD +M: Prabhakar Kushwaha <prabhakar@freescale.com> +S: Maintained +F: board/freescale/ls2080ardb/ +F: board/freescale/ls2080a/ls2080ardb.c +F: include/configs/ls2080ardb.h +F: configs/ls2080ardb_defconfig +F: configs/ls2080ardb_nand_defconfig +F: configs/ls2085ardb_defconfig +F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2080ardb/Makefile index de383ccc0fa..6a52167be14 100644 --- a/board/freescale/ls2085ardb/Makefile +++ b/board/freescale/ls2080ardb/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085ardb.o eth_ls2085rdb.o +obj-y += ls2080ardb.o eth_ls2080rdb.o obj-y += ddr.o diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2080ardb/README index 2f18243a8b2..7fc25696481 100644 --- a/board/freescale/ls2085ardb/README +++ b/board/freescale/ls2080ardb/README @@ -1,17 +1,17 @@ Overview -------- -The LS2085A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A +The LS2080A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. -LS2085A SoC Overview +LS2080A SoC Overview ------------------ -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. -The LS2085A SoC includes the following function and features: +The LS2080A SoC includes the following function and features: - Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC @@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities - LS2085ARDB board Overview + LS2080ARDB board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2080ardb/ddr.c index 8d71ae12646..6c191738ec4 100644 --- a/board/freescale/ls2085aqds/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; int slot; @@ -79,7 +81,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -114,6 +116,7 @@ found: pdimm[slot].dq_mapping[16] = 0; pdimm[slot].dq_mapping[17] = 0; } +#endif /* To work at higher than 1333MT/s */ popts->half_strength_driver_enable = 0; /* @@ -131,10 +134,18 @@ found: popts->zq_en = 1; if (ddr_freq < 2350) { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } } else { popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); @@ -164,14 +175,29 @@ void dram_init_banksize(void) phys_size_t dp_ddr_size; #endif + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a40fc..bda9d4a40fc 100644 --- a/board/freescale/ls2085ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index d578757dfde..db50e4efa96 100644 --- a/board/freescale/ls2085ardb/eth_ls2085rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -97,7 +97,7 @@ int board_eth_init(bd_t *bis) break; default: - printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", + printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", srds_s1); break; } diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 18953b8ecbf..c63b6396250 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -20,7 +20,7 @@ #include <asm/arch/soc.h> #include "../common/qixis.h" -#include "ls2085ardb_qixis.h" +#include "ls2080ardb_qixis.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -192,11 +192,13 @@ void detail_board_ddr_info(void) puts("\nDDR "); print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } +#endif } int dram_init(void) @@ -217,23 +219,6 @@ int arch_misc_init(void) } #endif -unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { @@ -260,6 +245,7 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + int err; u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -275,7 +261,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); - fsl_mc_ldpaa_exit(bd); + err = fsl_mc_ldpaa_exit(bd); + if (err) + return err; #endif return 0; diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2080ardb/ls2080ardb_qixis.h index cb60c00c6c1..cb60c00c6c1 100644 --- a/board/freescale/ls2085ardb/ls2085ardb_qixis.h +++ b/board/freescale/ls2080ardb/ls2080ardb_qixis.h diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS deleted file mode 100644 index 90b4e4715d7..00000000000 --- a/board/freescale/ls2085a/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: York Sun <yorksun@freescale.com> -S: Maintained -F: board/freescale/ls2085a/ -F: include/configs/ls2085a_emu.h -F: configs/ls2085a_emu_defconfig -F: include/configs/ls2085a_simu.h -F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile deleted file mode 100644 index 701b35cd59e..00000000000 --- a/board/freescale/ls2085a/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls2085a.o -obj-y += ddr.o diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS deleted file mode 100644 index fbed6726016..00000000000 --- a/board/freescale/ls2085aqds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> -S: Maintained -F: board/freescale/ls2085aqds/ -F: board/freescale/ls2085a/ls2085aqds.c -F: include/configs/ls2085aqds.h -F: configs/ls2085aqds_defconfig -F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS deleted file mode 100644 index d5cce40b212..00000000000 --- a/board/freescale/ls2085ardb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> -S: Maintained -F: board/freescale/ls2085ardb/ -F: board/freescale/ls2085a/ls2085ardb.c -F: include/configs/ls2085ardb.h -F: configs/ls2085ardb_defconfig -F: configs/ls2085ardb_nand_defconfig diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 6c863dae5a2..f8ae9733fc0 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -44,6 +44,9 @@ DECLARE_GLOBAL_DATA_PTR; #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ @@ -455,6 +458,29 @@ int board_phy_config(struct phy_device *phydev) } #endif +#ifdef CONFIG_FSL_QSPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), +}; + +int board_qspi_init(void) +{ + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -481,6 +507,10 @@ int board_init(void) setup_lcd(); #endif +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; } diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index d3644a96550..6b139392b56 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -18,10 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR - select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 config PCIE_ECAM_BASE diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index d56d90378c4..ae96d23d030 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -19,10 +19,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR - select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 config SYS_CAR_ADDR diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 044c6d5e9d6..57b89e0ba64 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -40,7 +40,7 @@ static const struct ns16550_platdata igep_serial = { }; U_BOOT_DEVICE(igep_uart) = { - "serial_omap", + "ns16550_serial", &igep_serial }; diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/kylin/kylin_rk3036/Kconfig new file mode 100644 index 00000000000..5d75c1fc0f6 --- /dev/null +++ b/board/kylin/kylin_rk3036/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KYLIN_RK3036 + +config SYS_BOARD + default "kylin_rk3036" + +config SYS_VENDOR + default "kylin" + +config SYS_CONFIG_NAME + default "kylin_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS new file mode 100644 index 00000000000..e69de29bb2d --- /dev/null +++ b/board/kylin/kylin_rk3036/MAINTAINERS diff --git a/board/kylin/kylin_rk3036/Makefile b/board/kylin/kylin_rk3036/Makefile new file mode 100644 index 00000000000..0663270506c --- /dev/null +++ b/board/kylin/kylin_rk3036/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += kylin_rk3036.o diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/kylin/kylin_rk3036/kylin_rk3036.c new file mode 100644 index 00000000000..40d6b521bc6 --- /dev/null +++ b/board/kylin/kylin_rk3036/kylin_rk3036.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <asm/arch/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_ddr_config(struct rk3036_ddr_config *config) +{ + /* K4B4G1646Q config */ + config->ddr_type = 3; + config->rank = 1; + config->cs0_row = 15; + config->cs1_row = 15; + + /* 8bank */ + config->bank = 3; + config->col = 10; + + /* 16bit bw */ + config->bw = 1; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index 4eff01a255f..c818c9d4ced 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -35,7 +35,7 @@ static const struct ns16550_platdata serial_omap_platdata = { }; U_BOOT_DEVICE(sniper_serial) = { - .name = "serial_omap", + .name = "ns16550_serial", .platdata = &serial_omap_platdata }; diff --git a/board/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig index 7b8c605a070..7f1bb400989 100644 --- a/board/lwmon5/Kconfig +++ b/board/liebherr/lwmon5/Kconfig @@ -3,6 +3,9 @@ if TARGET_LWMON5 config SYS_BOARD default "lwmon5" +config SYS_VENDOR + default "liebherr" + config SYS_CONFIG_NAME default "lwmon5" diff --git a/board/lwmon5/MAINTAINERS b/board/liebherr/lwmon5/MAINTAINERS index 3ea1888cea9..df4573012ca 100644 --- a/board/lwmon5/MAINTAINERS +++ b/board/liebherr/lwmon5/MAINTAINERS @@ -1,6 +1,6 @@ LWMON5 BOARD M: Stefan Roese <sr@denx.de> S: Maintained -F: board/lwmon5/ +F: board/liebherr/lwmon5/ F: include/configs/lwmon5.h F: configs/lwmon5_defconfig diff --git a/board/lwmon5/Makefile b/board/liebherr/lwmon5/Makefile index 02478ca0c85..02478ca0c85 100644 --- a/board/lwmon5/Makefile +++ b/board/liebherr/lwmon5/Makefile diff --git a/board/lwmon5/config.mk b/board/liebherr/lwmon5/config.mk index d0348e8024d..d0348e8024d 100644 --- a/board/lwmon5/config.mk +++ b/board/liebherr/lwmon5/config.mk diff --git a/board/lwmon5/init.S b/board/liebherr/lwmon5/init.S index e5207c2b40b..e5207c2b40b 100644 --- a/board/lwmon5/init.S +++ b/board/liebherr/lwmon5/init.S diff --git a/board/lwmon5/kbd.c b/board/liebherr/lwmon5/kbd.c index d6c0a205a3c..d6c0a205a3c 100644 --- a/board/lwmon5/kbd.c +++ b/board/liebherr/lwmon5/kbd.c diff --git a/board/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c index 8ad67128411..8ad67128411 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/liebherr/lwmon5/lwmon5.c diff --git a/board/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c index bcb344940bd..bcb344940bd 100644 --- a/board/lwmon5/sdram.c +++ b/board/liebherr/lwmon5/sdram.c diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index babb0dc0fe4..fb89921e6b7 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -43,7 +43,7 @@ static const struct ns16550_platdata omap3logic_serial = { }; U_BOOT_DEVICE(omap3logic_uart) = { - "serial_omap", + "ns16550_serial", &omap3logic_serial }; diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 0a3b55b6c12..4040114ce0a 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -50,7 +50,7 @@ static const struct ns16550_platdata zoom1_serial = { }; U_BOOT_DEVICE(zoom1_uart) = { - "serial_omap", + "ns16550_serial", &zoom1_serial }; diff --git a/board/overo/overo.c b/board/overo/overo.c index 20cbec208e8..a38b959cb24 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -74,7 +74,7 @@ static const struct ns16550_platdata overo_serial = { }; U_BOOT_DEVICE(overo_uart) = { - "serial_omap", + "ns16550_serial", &overo_serial }; diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c index b97a09ab151..21793e85c4d 100644 --- a/board/quipos/cairo/cairo.c +++ b/board/quipos/cairo/cairo.c @@ -97,7 +97,7 @@ static const struct ns16550_platdata cairo_serial = { }; U_BOOT_DEVICE(cairo_uart) = { - "serial_omap", + "ns16550_serial", &cairo_serial }; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6451d1d916b..4b80d7b742f 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -74,117 +74,132 @@ struct msg_get_clock_rate { u32 end_tag; }; -/* See comments in mbox.h for data source */ -static const struct { +/* + * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 + * http://git.drogon.net/?p=wiringPi;a=blob;f=wiringPi/wiringPi.c;h=503151f61014418b9c42f4476a6086f75cd4e64b;hb=refs/heads/master#l922 + */ +struct rpi_model { const char *name; const char *fdtfile; bool has_onboard_eth; -} models[] = { - [0] = { - "Unknown model", +}; + +static const struct rpi_model rpi_model_unknown = { + "Unknown model", #ifdef CONFIG_BCM2836 - "bcm2836-rpi-other.dtb", + "bcm2836-rpi-other.dtb", #else - "bcm2835-rpi-other.dtb", + "bcm2835-rpi-other.dtb", #endif - false, - }, -#ifdef CONFIG_BCM2836 - [BCM2836_BOARD_REV_2_B] = { + false, +}; + +static const struct rpi_model rpi_models_new_scheme[] = { + [0x4] = { "2 Model B", "bcm2836-rpi-2-b.dtb", true, }, -#else - [BCM2835_BOARD_REV_B_I2C0_2] = { + [0x9] = { + "Zero", + "bcm2835-rpi-zero.dtb", + false, + }, +}; + +static const struct rpi_model rpi_models_old_scheme[] = { + [0x2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C0_3] = { + [0x3] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_4] = { + [0x4] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_5] = { + [0x5] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_B_I2C1_6] = { + [0x6] = { "Model B", "bcm2835-rpi-b.dtb", true, }, - [BCM2835_BOARD_REV_A_7] = { + [0x7] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_A_8] = { + [0x8] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_A_9] = { + [0x9] = { "Model A", "bcm2835-rpi-a.dtb", false, }, - [BCM2835_BOARD_REV_B_REV2_d] = { + [0xd] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_REV2_e] = { + [0xe] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_REV2_f] = { + [0xf] = { "Model B rev2", "bcm2835-rpi-b-rev2.dtb", true, }, - [BCM2835_BOARD_REV_B_PLUS] = { + [0x10] = { "Model B+", "bcm2835-rpi-b-plus.dtb", true, }, - [BCM2835_BOARD_REV_CM] = { + [0x11] = { "Compute Module", "bcm2835-rpi-cm.dtb", false, }, - [BCM2835_BOARD_REV_A_PLUS] = { + [0x12] = { "Model A+", "bcm2835-rpi-a-plus.dtb", false, }, - [BCM2835_BOARD_REV_B_PLUS_13] = { + [0x13] = { "Model B+", "bcm2835-rpi-b-plus.dtb", true, }, - [BCM2835_BOARD_REV_CM_14] = { + [0x14] = { "Compute Module", "bcm2835-rpi-cm.dtb", false, }, - [BCM2835_BOARD_REV_A_PLUS_15] = { + [0x15] = { "Model A+", "bcm2835-rpi-a-plus.dtb", false, }, -#endif }; -u32 rpi_board_rev = 0; +static uint32_t revision; +static uint32_t rev_scheme; +static uint32_t rev_type; +static const struct rpi_model *model; int dram_init(void) { @@ -212,7 +227,7 @@ static void set_fdtfile(void) if (getenv("fdtfile")) return; - fdtfile = models[rpi_board_rev].fdtfile; + fdtfile = model->fdtfile; setenv("fdtfile", fdtfile); } @@ -221,7 +236,7 @@ static void set_usbethaddr(void) ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1); int ret; - if (!models[rpi_board_rev].has_onboard_eth) + if (!model->has_onboard_eth) return; if (getenv("usbethaddr")) @@ -245,10 +260,16 @@ static void set_usbethaddr(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG static void set_board_info(void) { - char str_rev[11]; - sprintf(str_rev, "0x%X", rpi_board_rev); - setenv("board_rev", str_rev); - setenv("board_name", models[rpi_board_rev].name); + char s[11]; + + snprintf(s, sizeof(s), "0x%X", revision); + setenv("board_revision", s); + snprintf(s, sizeof(s), "%d", rev_scheme); + setenv("board_rev_scheme", s); + /* Can't rename this to board_rev_type since it's an ABI for scripts */ + snprintf(s, sizeof(s), "0x%X", rev_type); + setenv("board_rev", s); + setenv("board_name", model->name); } #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ @@ -290,7 +311,8 @@ static void get_board_rev(void) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1); int ret; - const char *name; + const struct rpi_model *models; + uint32_t models_count; BCM2835_MBOX_INIT_HDR(msg); BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); @@ -313,23 +335,29 @@ static void get_board_rev(void) * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 */ - rpi_board_rev = msg->get_board_rev.body.resp.rev; - if (rpi_board_rev & 0x800000) - rpi_board_rev = (rpi_board_rev >> 4) & 0xff; - else - rpi_board_rev &= 0xff; - if (rpi_board_rev >= ARRAY_SIZE(models)) { - printf("RPI: Board rev %u outside known range\n", - rpi_board_rev); - rpi_board_rev = 0; + revision = msg->get_board_rev.body.resp.rev; + if (revision & 0x800000) { + rev_scheme = 1; + rev_type = (revision >> 4) & 0xff; + models = rpi_models_new_scheme; + models_count = ARRAY_SIZE(rpi_models_new_scheme); + } else { + rev_scheme = 0; + rev_type = revision & 0xff; + models = rpi_models_old_scheme; + models_count = ARRAY_SIZE(rpi_models_old_scheme); } - if (!models[rpi_board_rev].name) { - printf("RPI: Board rev %u unknown\n", rpi_board_rev); - rpi_board_rev = 0; + if (rev_type >= models_count) { + printf("RPI: Board rev 0x%x outside known range\n", rev_type); + model = &rpi_model_unknown; + } else if (!models[rev_type].name) { + printf("RPI: Board rev 0x%x unknown\n", rev_type); + model = &rpi_model_unknown; + } else { + model = &models[rev_type]; } - name = models[rpi_board_rev].name; - printf("RPI %s\n", name); + printf("RPI %s (0x%x)\n", model->name, revision); } int board_init(void) diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index d943d63eca0..1600568193a 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -10,7 +10,7 @@ #include <asm/gpio.h> #include <asm/arch/mmc.h> #include <power/pmic.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <asm/arch/cpu.h> #include <power/max8998_pmic.h> #include <samsung/misc.h> @@ -183,7 +183,7 @@ static int s5pc1xx_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc110_otg_data = { +struct dwc2_plat_otg_data s5pc110_otg_data = { .phy_control = s5pc1xx_phy_control, .regs_phy = S5PC110_PHY_BASE, .regs_otg = S5PC110_OTG_BASE, @@ -193,7 +193,7 @@ struct s3c_plat_otg_data s5pc110_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc110_otg_data); + return dwc2_udc_probe(&s5pc110_otg_data); } #endif diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 36d493d514d..b4cb33240e1 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -19,7 +19,7 @@ #include <errno.h> #include <mmc.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <samsung/misc.h> #include "setup.h" @@ -452,7 +452,7 @@ static int s5pc210_phy_control(int on) return regulator_set_mode(dev, OPMODE_LPM); } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4X12_USBPHY_BASE, .regs_otg = EXYNOS4X12_USBOTG_BASE, @@ -510,6 +510,6 @@ int board_usb_init(int index, enum usb_init_type init) } #endif debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } #endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index e163e45a587..54d01ec439a 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -18,7 +18,7 @@ #include <asm/arch/watchdog.h> #include <asm/arch/power.h> #include <power/pmic.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <power/max8997_pmic.h> #include <power/max8997_muic.h> #include <power/battery.h> @@ -41,7 +41,7 @@ u32 get_board_rev(void) #endif static void check_hw_revision(void); -struct s3c_plat_otg_data s5pc210_otg_data; +struct dwc2_plat_otg_data s5pc210_otg_data; int exynos_init(void) { @@ -419,7 +419,7 @@ static int s5pc210_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4_USBPHY_BASE, .regs_otg = EXYNOS4_USBOTG_BASE, @@ -430,7 +430,7 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } int g_dnl_board_usb_cable_connected(void) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index a7377497e5d..7b28ae8cc72 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -21,7 +21,7 @@ #include <libtizen.h> #include <errno.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <usb_mass_storage.h> DECLARE_GLOBAL_DATA_PTR; @@ -303,7 +303,7 @@ static int s5pc210_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4X12_USBPHY_BASE, .regs_otg = EXYNOS4X12_USBOTG_BASE, @@ -314,7 +314,7 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } int g_dnl_board_usb_cable_connected(void) diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index df4671394f6..c25b486f4a9 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -17,7 +17,7 @@ #include <ld9040.h> #include <power/pmic.h> #include <usb.h> -#include <usb/s3c_udc.h> +#include <usb/dwc2_udc.h> #include <asm/arch/cpu.h> #include <power/max8998_pmic.h> #include <libtizen.h> @@ -179,7 +179,7 @@ static int s5pc210_phy_control(int on) return 0; } -struct s3c_plat_otg_data s5pc210_otg_data = { +struct dwc2_plat_otg_data s5pc210_otg_data = { .phy_control = s5pc210_phy_control, .regs_phy = EXYNOS4_USBPHY_BASE, .regs_otg = EXYNOS4_USBOTG_BASE, @@ -191,7 +191,7 @@ struct s3c_plat_otg_data s5pc210_otg_data = { int board_usb_init(int index, enum usb_init_type init) { debug("USB_udc_probe\n"); - return s3c_udc_probe(&s5pc210_otg_data); + return dwc2_udc_probe(&s5pc210_otg_data); } int exynos_early_init_f(void) diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 48823141daa..988c12ac7c8 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -196,11 +196,6 @@ struct ctrl_ioregs draco_ddr3_ioregs = { config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); - - /* For Samsung 2Gbit RAM we need this delay otherwise config fails after - * soft reset. - */ - udelay(2000); } static void spl_siemens_board_init(void) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index fc0918f91d8..858a9cae76a 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -48,9 +48,6 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_ETH_DESIGNWARE) u32 interface = PHY_INTERFACE_MODE_MII; -#if defined(CONFIG_DW_AUTONEG) - interface = PHY_INTERFACE_MODE_GMII; -#endif if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif diff --git a/board/sr1500/MAINTAINERS b/board/sr1500/MAINTAINERS new file mode 100644 index 00000000000..ed013a85243 --- /dev/null +++ b/board/sr1500/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA SR1500 BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/sr1500/ +F: include/configs/socfpga_sr1500.h +F: configs/socfpga_sr1500_defconfig diff --git a/board/sr1500/Makefile b/board/sr1500/Makefile new file mode 100644 index 00000000000..eae7ad0302a --- /dev/null +++ b/board/sr1500/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h new file mode 100644 index 00000000000..aa1e65c2ae9 --- /dev/null +++ b/board/sr1500/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00100000, + 0x40000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x000E0180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x000700C0, + 0x1C030000, + 0x0C000000, + 0x00000070, + 0x0001C030, + 0x00002000, + 0x00018060, + 0x0E018000, + 0x06000000, + 0x00000038, + 0x0000E018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x001C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x000000E0, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x1C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x000C0300, + 0x700C0000, + 0x0FF00000, + 0x00000000, + 0x000700C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x0C000000, + 0x00000070, + 0x0001C030, + 0x00002000, + 0x10018060, + 0x0E018000, + 0x06000000, + 0x00010018, + 0x0000E018, + 0x00001000, + 0x0001C030, + 0x04000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x180D0000, + 0x71C06806, + 0x01450340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x80E380D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x01450340, + 0xD00A281A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3DD, + 0xF5D5551E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D555, + 0x00035AD3, + 0x00080000, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00808000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3DD, + 0xF5D9651E, + 0x035AB2C8, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D965, + 0x00035AD3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820004, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00808000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010000, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00202000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xCB2CA3D5, + 0xF6D9651E, + 0x035AB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1ECB2CA3, + 0x48F5D965, + 0x00034AD3, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820004, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040000, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00800000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020000, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00001000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xCB2CA3D5, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1ECB2CA3, + 0x48F6D965, + 0x00034A92, + 0x00080000, + 0x00001000, + 0x00080000, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x00000000, + 0x00000010, + 0x0080C000, + 0x41000000, + 0x00000002, + 0x00820004, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00004000, + 0x00010000, + 0x40002080, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000008, + 0x00000020, + 0x00008000, + 0x20001040, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/sr1500/qts/pinmux_config.h b/board/sr1500/qts/pinmux_config.h new file mode 100644 index 00000000000..45e390debb3 --- /dev/null +++ b/board/sr1500/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 0, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 0, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 0, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 0, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 0, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 0, /* GPLMUX40 */ + 0, /* GPLMUX41 */ + 0, /* GPLMUX42 */ + 0, /* GPLMUX43 */ + 0, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 0, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 0, /* GPLMUX53 */ + 0, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 0, /* GPLMUX57 */ + 0, /* GPLMUX58 */ + 0, /* GPLMUX59 */ + 0, /* GPLMUX60 */ + 0, /* GPLMUX61 */ + 0, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h new file mode 100644 index 00000000000..359e7ad734b --- /dev/null +++ b/board/sr1500/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 12500000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h new file mode 100644 index 00000000000..edbaf8929fb --- /dev/null +++ b/board/sr1500/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090044, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0024, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c new file mode 100644 index 00000000000..617dffa136e --- /dev/null +++ b/board/sr1500/socfpga.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/gpio.h> +#include <asm/io.h> + +int board_early_init_f(void) +{ + int ret; + + /* Reset the Marvell PHY 88E1510 */ + ret = gpio_request(63, "PHY reset"); + if (ret) + return ret; + + gpio_direction_output(63, 0); + mdelay(1); + gpio_set_value(63, 1); + mdelay(10); + + return 0; +} diff --git a/board/st/stm32f429-discovery/MAINTAINERS b/board/st/stm32f429-discovery/MAINTAINERS index 641f26a0371..fdb62e98e89 100644 --- a/board/st/stm32f429-discovery/MAINTAINERS +++ b/board/st/stm32f429-discovery/MAINTAINERS @@ -1,5 +1,5 @@ STM32F429-DISCOVERY BOARD -M: Kamil Lulko <rev13@wp.pl> +M: Kamil Lulko <kamil.lulko@gmail.com> S: Maintained F: board/st/stm32f429-discovery/ F: include/configs/stm32f429-discovery.h diff --git a/board/st/stm32f429-discovery/Makefile b/board/st/stm32f429-discovery/Makefile index 7e764e3308b..d94059d0aec 100644 --- a/board/st/stm32f429-discovery/Makefile +++ b/board/st/stm32f429-discovery/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2015 -# Kamil Lulko, <rev13@wp.pl> +# Kamil Lulko, <kamil.lulko@gmail.com> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c index 306e550a7c0..ee22009f314 100644 --- a/board/st/stm32f429-discovery/led.c +++ b/board/st/stm32f429-discovery/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index f418186c1ea..8bc2d9e4c1c 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -6,7 +6,7 @@ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,6 +17,8 @@ #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> #include <asm/arch/fmc.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_stm32.h> DECLARE_GLOBAL_DATA_PTR; @@ -263,6 +265,15 @@ int dram_init(void) return rv; } +static const struct stm32_serial_platdata serial_platdata = { + .base = (struct stm32_usart *)STM32_USART1_BASE, +}; + +U_BOOT_DEVICE(stm32_serials) = { + .name = "serial_stm32", + .platdata = &serial_platdata, +}; + u32 get_board_rev(void) { return 0; diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index f6f2a605eca..9d67847850f 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -68,6 +68,18 @@ config MACH_SUN8I_A33 select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +config MACH_SUN8I_H3 + bool "sun8i (Allwinner H3)" + select CPU_V7 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + +config MACH_SUN8I_A83T + bool "sun8i (Allwinner A83T)" + select CPU_V7 + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7 @@ -78,7 +90,7 @@ endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool - default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 + default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T config DRAM_CLK @@ -367,6 +379,7 @@ config AXP_GPIO config VIDEO boolean "Enable graphical uboot console on HDMI, LCD or VGA" + depends on !MACH_SUN8I_A83T default y ---help--- Say Y here to add support for using a cfb console on the HDMI, LCD diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 96c4f3aa029..131c3415aa3 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -25,6 +25,7 @@ F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T003_defconfig F: configs/Auxtek-T004_defconfig F: configs/CHIP_defconfig +F: configs/Empire_electronix_d709_defconfig F: configs/inet98v_rev2_defconfig F: configs/mk802_a10s_defconfig F: configs/q8_a13_tablet_defconfig @@ -50,6 +51,8 @@ F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig +F: configs/orangepi_pc_defconfig +F: configs/orangepi_plus_defconfig F: configs/q8_a23_tablet_800x480_defconfig F: configs/q8_a33_tablet_800x480_defconfig F: configs/q8_a33_tablet_1024x600_defconfig @@ -99,6 +102,11 @@ M: Priit Laes <plaes@plaes.org> S: Maintained F: configs/sunxi_Gemei_G9_defconfig +H8HOMLET PROTO A83T BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/h8_homlet_v2_defconfig + HUMMINGBIRD-A31 BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained @@ -119,6 +127,11 @@ M: Michal Suchanek <hramrach@gmail.com> S: Maintained F: configs/iNet_86VS_defconfig +LAMOBO-R1 BOARD +M: Jelle de Jong <jelledejong@powercraft.nl> +S: Maintained +F: configs/Lamobo_R1_defconfig + LINKSPRITE-PCDUINO BOARD M: Zoltan Herpai <wigyori@uid0.hu> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 6ac398c2dc1..386e2e04c21 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -430,26 +430,29 @@ void sunxi_board_init(void) int power_failed = 0; unsigned long ramsize; -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ + defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed = axp_init(); -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); -#ifndef CONFIG_AXP209_POWER +#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif #ifdef CONFIG_AXP221_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif +#ifndef CONFIG_AXP818_POWER power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); -#ifndef CONFIG_AXP152_POWER +#endif +#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER) power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); #endif #ifdef CONFIG_AXP209_POWER diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c index 85700b05bef..97fb902f8e6 100644 --- a/board/terasic/de0-nano-soc/socfpga.c +++ b/board/terasic/de0-nano-soc/socfpga.c @@ -3,70 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9031 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x70); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x7777); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0); - if (ret) - return ret; - - ret = ksz9031_phy_extended_write(phydev, 0x2, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - 0x03FC); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif diff --git a/board/terasic/sockit/socfpga.c b/board/terasic/sockit/socfpga.c index a1dbc492c98..97fb902f8e6 100644 --- a/board/terasic/sockit/socfpga.c +++ b/board/terasic/sockit/socfpga.c @@ -3,83 +3,4 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <asm/arch/reset_manager.h> -#include <asm/io.h> - -#include <usb.h> -#include <usb/s3c_udc.h> -#include <usb_mass_storage.h> - -#include <micrel.h> -#include <netdev.h> -#include <phy.h> - -DECLARE_GLOBAL_DATA_PTR; - -void s_init(void) {} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -/* - * PHY configuration - */ -#ifdef CONFIG_PHY_MICREL_KSZ9021 -int board_phy_config(struct phy_device *phydev) -{ - int ret; - /* - * These skew settings for the KSZ9021 ethernet phy is required for ethernet - * to work reliably on most flavors of cyclone5 boards. - */ - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x0); - if (ret) - return ret; - - ret = ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf0f0); - if (ret) - return ret; - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_USB_GADGET -struct s3c_plat_otg_data socfpga_otg_data = { - .regs_otg = CONFIG_USB_DWC2_REG_ADDR, - .usb_gusbcfg = 0x1417, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - return s3c_udc_probe(&socfpga_otg_data); -} - -int g_dnl_board_usb_cable_connected(void) -{ - return 1; -} -#endif diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 23f22a02bec..3c007b76dd5 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -255,10 +255,10 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ - {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ - {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ - {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ - {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */ {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 56e3cfe935a..ff317efc2c7 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -79,7 +79,7 @@ static const struct ns16550_platdata beagle_serial = { }; U_BOOT_DEVICE(beagle_uart) = { - "serial_omap", + "ns16550_serial", &beagle_serial }; diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index bf401443e46..1bfb36243b5 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -372,7 +372,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ - {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ + {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */ }; #ifdef CONFIG_IODELAY_RECALIBRATION diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index a61cc1481b4..1a447c77df2 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -52,7 +52,7 @@ static const struct ns16550_platdata devkit8000_serial = { }; U_BOOT_DEVICE(devkit8000_uart) = { - "serial_omap", + "ns16550_serial", &devkit8000_serial }; diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 0c8bd7d1511..dfa62932222 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -69,6 +69,7 @@ int dram_init(void) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_XILINX_GPIO if (reset_pin != -1) gpio_direction_output(reset_pin, 1); @@ -77,7 +78,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_XILINX_TB_WATCHDOG hw_watchdog_disable(); #endif - +#endif puts ("Reseting board\n"); __asm__ __volatile__ (" mts rmsr, r0;" \ "bra r0"); @@ -122,40 +123,5 @@ int board_eth_init(bd_t *bis) txpp, rxpp); #endif -#ifdef CONFIG_XILINX_LL_TEMAC -# ifdef XILINX_LLTEMAC_BASEADDR -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, - XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, - XILINX_LL_TEMAC_M_SDMA_DCR, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# else - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, - XILINX_LL_TEMAC_M_SDMA_PLB, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); -# endif -# endif -# endif -# ifdef XILINX_LLTEMAC_BASEADDR1 -# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, - XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); -# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 -# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, - XILINX_LL_TEMAC_M_SDMA_DCR, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); -# else - ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, - XILINX_LL_TEMAC_M_SDMA_PLB, - XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); -# endif -# endif -# endif -#endif - return ret; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index d6d0d679e8e..8ba146cb88d 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -56,12 +56,6 @@ /* Ethernet controller is Ethernet_MAC */ #define XILINX_EMACLITE_BASEADDR 0x40C00000 -/* LL_TEMAC Ethernet controller */ -#define XILINX_LLTEMAC_BASEADDR 0x44000000 -#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 -#define XILINX_LLTEMAC_BASEADDR1 0x44200000 -#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 88047ec1de4..eab93038cef 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -12,6 +12,7 @@ hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform +hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform # If you want to use customized ps7_init_gpl.c/h, # enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/. # This line must be placed at the bottom of the list because diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 237f2c2a2bf..414f5302a06 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -119,39 +119,9 @@ int board_eth_init(bd_t *bis) ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, txpp, rxpp); #endif - -#if defined(CONFIG_ZYNQ_GEM) -# if defined(CONFIG_ZYNQ_GEM0) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, - CONFIG_ZYNQ_GEM_EMIO0); -# endif -# if defined(CONFIG_ZYNQ_GEM1) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, - CONFIG_ZYNQ_GEM_EMIO1); -# endif -#endif return ret; } -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bd) -{ - int ret = 0; - -#if defined(CONFIG_ZYNQ_SDHCI) -# if defined(CONFIG_ZYNQ_SDHCI0) - ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); -# endif -# if defined(CONFIG_ZYNQ_SDHCI1) - ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); -# endif -#endif - return ret; -} -#endif - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c new file mode 100644 index 00000000000..2c0fecac43f --- /dev/null +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c @@ -0,0 +1,11948 @@ +/* + * Copyright (c) Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000154[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x3 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ + /* .. .. DIVISOR0 = 0x6 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), + /* .. .. SRCSEL = 0x2 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ + /* .. .. DIVISOR0 = 0x35 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ + /* .. .. DIVISOR1 = 0x2 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ + /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ + /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ + /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_t_cksre = 0x6 */ + /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_t_cksrx = 0x6 */ + /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_t_ckesr = 0x4 */ + /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + /* .. .. reg_ddrc_t_ckpde = 0x2 */ + /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_ckpdx = 0x2 */ + /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ + /* .. .. reg_ddrc_t_ckdpde = 0x2 */ + /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ + /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ + /* .. .. reg_ddrc_t_ckcsx = 0x3 */ + /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B00[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCI_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. reserved_INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE_B = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCI_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. reserved_SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. reserved_DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. reserved_DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. reserved_SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. reserved_SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. reserved_GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. reserved_RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. reserved_VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. reserved_REFIO_TEST = 0x0 */ + /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ + /* .. reserved_REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. reserved_DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. reserved_CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reserved_VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reserved_VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reserved_VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reserved_VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reserved_VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reserved_INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reserved_TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reserved_TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reserved_TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. reserved_TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reserved_INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x3e */ + /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_3_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_LVL_INP_EN_0 = 1 */ + /* .. ==> 0XF8000900[3:3] = 0x00000001U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. USER_LVL_OUT_EN_0 = 1 */ + /* .. ==> 0XF8000900[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. USER_LVL_INP_EN_1 = 1 */ + /* .. ==> 0XF8000900[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. USER_LVL_OUT_EN_1 = 1 */ + /* .. ==> 0XF8000900[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. reserved_FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. reserved_FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. reserved_FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. reserved_FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. reserved_FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. reserved_FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. reserved_FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_3_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_pll_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000154[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x3 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ + /* .. .. DIVISOR0 = 0x6 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), + /* .. .. SRCSEL = 0x2 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ + /* .. .. DIVISOR0 = 0x35 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ + /* .. .. DIVISOR1 = 0x2 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_block = 0x1 */ + /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ + /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ + /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ + /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ + /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_sdram = 0x1 */ + /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_clock_stop_en = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_loopback = 0x0 */ + /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_max_rank_rd = 0xf */ + /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_debug_mode = 0x0 */ + /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_dq0_wait_t = 0x0 */ + /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ + /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ + /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */ + /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */ + /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */ + /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */ + /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_t_cksre = 0x6 */ + /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_t_cksrx = 0x6 */ + /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_t_ckesr = 0x4 */ + /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + /* .. .. reg_ddrc_t_ckpde = 0x2 */ + /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_ckpdx = 0x2 */ + /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */ + /* .. .. reg_ddrc_t_ckdpde = 0x2 */ + /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_ckdpdx = 0x2 */ + /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */ + /* .. .. reg_ddrc_t_ckcsx = 0x3 */ + /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + /* .. .. refresh_timer0_start_value_x32 = 0x0 */ + /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ + /* .. .. refresh_timer1_start_value_x32 = 0x8 */ + /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_2t_delay = 0x0 */ + /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ + /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_loopback = 0x0 */ + /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ + /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_rank0_delays = 0x1 */ + /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_phy_int_lpbk = 0x0 */ + /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ + /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. CLK_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. SRSTN_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. REFIO_TEST = 0x0 */ + /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */ + /* .. REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x3e */ + /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. IRMODE = 0x0 */ + /* .. ==> 0XE0001004[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. UCLKEN = 0x0 */ + /* .. ==> 0XE0001004[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_2_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_INP_ICT_EN_0 = 3 */ + /* .. ==> 0XF8000900[1:0] = 0x00000003U */ + /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ + /* .. USER_INP_ICT_EN_1 = 3 */ + /* .. ==> 0XF8000900[3:2] = 0x00000003U */ + /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_2_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_pll_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: PLL SLCR REGISTERS */ + /* .. .. START: ARM PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x177 */ + /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x1a */ + /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. ARM_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. SRCSEL = 0x0 */ + /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. .. DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */ + /* .. .. .. CPU_6OR4XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. .. CPU_3OR2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */ + /* .. .. .. CPU_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. .. CPU_1XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. .. CPU_PERI_CLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + /* .. .. FINISH: ARM PLL INIT */ + /* .. .. START: DDR PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1db */ + /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x15 */ + /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. DDR_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. .. DDR_3XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. DDR_2XCLKACT = 0x1 */ + /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */ + /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */ + /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */ + /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */ + /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + /* .. .. FINISH: DDR PLL INIT */ + /* .. .. START: IO PLL INIT */ + /* .. .. PLL_RES = 0xc */ + /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */ + /* .. .. PLL_CP = 0x2 */ + /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. LOCK_CNT = 0x1f4 */ + /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + /* .. .. .. START: UPDATE FB_DIV */ + /* .. .. .. PLL_FDIV = 0x14 */ + /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */ + /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + /* .. .. .. FINISH: UPDATE FB_DIV */ + /* .. .. .. START: BY PASS PLL */ + /* .. .. .. PLL_BYPASS_FORCE = 1 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + /* .. .. .. FINISH: BY PASS PLL */ + /* .. .. .. START: ASSERT RESET */ + /* .. .. .. PLL_RESET = 1 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + /* .. .. .. FINISH: ASSERT RESET */ + /* .. .. .. START: DEASSERT RESET */ + /* .. .. .. PLL_RESET = 0 */ + /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + /* .. .. .. FINISH: DEASSERT RESET */ + /* .. .. .. START: CHECK PLL STATUS */ + /* .. .. .. IO_PLL_LOCK = 1 */ + /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */ + /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. .. */ + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + /* .. .. .. FINISH: CHECK PLL STATUS */ + /* .. .. .. START: REMOVE PLL BY PASS */ + /* .. .. .. PLL_BYPASS_FORCE = 0 */ + /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */ + /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. .. */ + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + /* .. .. .. FINISH: REMOVE PLL BY PASS */ + /* .. .. FINISH: IO PLL INIT */ + /* .. FINISH: PLL SLCR REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_clock_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: CLOCK CONTROL SLCR REGISTERS */ + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000128[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. DIVISOR0 = 0x34 */ + /* .. ==> 0XF8000128[13:8] = 0x00000034U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */ + /* .. DIVISOR1 = 0x2 */ + /* .. ==> 0XF8000128[25:20] = 0x00000002U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000138[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000138[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF8000140[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000140[6:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. DIVISOR = 0x8 */ + /* .. ==> 0XF8000140[13:8] = 0x00000008U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */ + /* .. DIVISOR1 = 0x1 */ + /* .. ==> 0XF8000140[25:20] = 0x00000001U */ + /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + /* .. CLKACT = 0x1 */ + /* .. ==> 0XF800014C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF800014C[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x5 */ + /* .. ==> 0XF800014C[13:8] = 0x00000005U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. */ + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + /* .. CLKACT0 = 0x1 */ + /* .. ==> 0XF8000150[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. CLKACT1 = 0x0 */ + /* .. ==> 0XF8000150[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000150[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000150[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + /* .. CLKACT0 = 0x0 */ + /* .. ==> 0XF8000154[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. CLKACT1 = 0x1 */ + /* .. ==> 0XF8000154[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. SRCSEL = 0x0 */ + /* .. ==> 0XF8000154[5:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. DIVISOR = 0x14 */ + /* .. ==> 0XF8000154[13:8] = 0x00000014U */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. */ + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + /* .. .. START: TRACE CLOCK */ + /* .. .. FINISH: TRACE CLOCK */ + /* .. .. CLKACT = 0x1 */ + /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR = 0x5 */ + /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), + /* .. .. SRCSEL = 0x3 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ + /* .. .. DIVISOR0 = 0x6 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), + /* .. .. SRCSEL = 0x2 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ + /* .. .. DIVISOR0 = 0x35 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ + /* .. .. DIVISOR1 = 0x2 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0xa */ + /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + /* .. .. CLK_621_TRUE = 0x1 */ + /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + /* .. .. DMA_CPU_2XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. USB0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. .. USB1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. GEM0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */ + /* .. .. GEM1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. SDI0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */ + /* .. .. SDI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. SPI0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. SPI1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. CAN0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. CAN1_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. I2C0_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */ + /* .. .. I2C1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. UART0_CPU_1XCLKACT = 0x0 */ + /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. UART1_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. GPIO_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */ + /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */ + /* .. .. SMC_CPU_1XCLKACT = 0x1 */ + /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU), + /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */ + /* .. START: THIS SHOULD BE BLANK */ + /* .. FINISH: THIS SHOULD BE BLANK */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + /* START: top */ + /* .. START: DDR INITIALIZATION */ + /* .. .. START: LOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + /* .. .. FINISH: LOCK DDR */ + /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */ + /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */ + /* .. .. reg_ddrc_active_ranks = 0x1 */ + /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */ + /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */ + /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_block = 0x1 */ + /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */ + /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */ + /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */ + /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */ + /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU), + /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */ + /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */ + /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */ + /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */ + /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */ + /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */ + /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */ + /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */ + /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */ + /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */ + /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_w_xact_run_length = 0x8 */ + /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */ + /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */ + /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */ + /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */ + /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + /* .. .. reg_ddrc_t_rc = 0x1a */ + /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */ + /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */ + /* .. .. reg_ddrc_t_rfc_min = 0x54 */ + /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */ + /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */ + /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */ + /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */ + /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU), + /* .. .. reg_ddrc_wr2pre = 0x12 */ + /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */ + /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */ + /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_t_faw = 0x15 */ + /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */ + /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */ + /* .. .. reg_ddrc_t_ras_max = 0x23 */ + /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */ + /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */ + /* .. .. reg_ddrc_t_ras_min = 0x13 */ + /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */ + /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */ + /* .. .. reg_ddrc_t_cke = 0x4 */ + /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U), + /* .. .. reg_ddrc_write_latency = 0x5 */ + /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_rd2wr = 0x7 */ + /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */ + /* .. .. reg_ddrc_wr2rd = 0xe */ + /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */ + /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */ + /* .. .. reg_ddrc_t_xp = 0x4 */ + /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */ + /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */ + /* .. .. reg_ddrc_pad_pd = 0x0 */ + /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd2pre = 0x4 */ + /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */ + /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */ + /* .. .. reg_ddrc_t_rcd = 0x7 */ + /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U), + /* .. .. reg_ddrc_t_ccd = 0x4 */ + /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */ + /* .. .. reg_ddrc_t_rrd = 0x6 */ + /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */ + /* .. .. reg_ddrc_refresh_margin = 0x2 */ + /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */ + /* .. .. reg_ddrc_t_rp = 0x7 */ + /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */ + /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */ + /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */ + /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */ + /* .. .. reg_ddrc_sdram = 0x1 */ + /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_mobile = 0x0 */ + /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_clock_stop_en = 0x0 */ + /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_read_latency = 0x7 */ + /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */ + /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */ + /* .. .. reg_ddrc_dis_pad_pd = 0x0 */ + /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_loopback = 0x0 */ + /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U), + /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */ + /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_prefer_write = 0x0 */ + /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_max_rank_rd = 0xf */ + /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */ + /* .. .. reg_ddrc_mr_wr = 0x0 */ + /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_addr = 0x0 */ + /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_data = 0x0 */ + /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */ + /* .. .. ddrc_reg_mr_wr_busy = 0x0 */ + /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_type = 0x0 */ + /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */ + /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU), + /* .. .. reg_ddrc_final_wait_x32 = 0x7 */ + /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */ + /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */ + /* .. .. reg_ddrc_t_mrd = 0x4 */ + /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + /* .. .. reg_ddrc_emr2 = 0x8 */ + /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */ + /* .. .. reg_ddrc_emr3 = 0x0 */ + /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U), + /* .. .. reg_ddrc_mr = 0x930 */ + /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */ + /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */ + /* .. .. reg_ddrc_emr = 0x4 */ + /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */ + /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U), + /* .. .. reg_ddrc_burst_rdwr = 0x4 */ + /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ + /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ + /* .. .. reg_ddrc_burstchop = 0x0 */ + /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ + /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_dq = 0x0 */ + /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_debug_mode = 0x0 */ + /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_level_start = 0x0 */ + /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_dq0_wait_t = 0x0 */ + /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U), + /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */ + /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */ + /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */ + /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */ + /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */ + /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */ + /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */ + /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */ + /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */ + /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */ + /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */ + /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */ + /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */ + /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */ + /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */ + /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */ + /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */ + /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */ + /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */ + /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */ + /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */ + /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */ + /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */ + /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */ + /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */ + /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */ + /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */ + /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */ + /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */ + /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */ + /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */ + /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */ + /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */ + /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. .. reg_phy_rd_local_odt = 0x0 */ + /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */ + /* .. .. reg_phy_idle_local_odt = 0x3 */ + /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */ + /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */ + /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */ + /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */ + /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */ + /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U), + /* .. .. reg_phy_rd_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_wr_cmd_to_data = 0x0 */ + /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */ + /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */ + /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */ + /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_fixed_re = 0x1 */ + /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */ + /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */ + /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_phy_clk_stall_level = 0x0 */ + /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */ + /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */ + /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */ + /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */ + /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */ + /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */ + /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */ + /* .. .. reg_ddrc_dis_dll_calib = 0x0 */ + /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U), + /* .. .. reg_ddrc_rd_odt_delay = 0x3 */ + /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */ + /* .. .. reg_ddrc_wr_odt_delay = 0x0 */ + /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rd_odt_hold = 0x0 */ + /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */ + /* .. .. reg_ddrc_wr_odt_hold = 0x5 */ + /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + /* .. .. reg_ddrc_pageclose = 0x0 */ + /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_lpr_num_entries = 0x1f */ + /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */ + /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */ + /* .. .. reg_ddrc_auto_pre_en = 0x0 */ + /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. .. reg_ddrc_refresh_update_level = 0x0 */ + /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_wc = 0x0 */ + /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */ + /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_ddrc_selfref_en = 0x0 */ + /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */ + /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */ + /* .. .. reg_arb_go2critical_en = 0x1 */ + /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + /* .. .. reg_ddrc_wrlvl_ww = 0x41 */ + /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */ + /* .. .. reg_ddrc_rdlvl_rr = 0x41 */ + /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */ + /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */ + /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */ + /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U), + /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */ + /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */ + /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */ + /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + /* .. .. refresh_timer0_start_value_x32 = 0x0 */ + /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */ + /* .. .. refresh_timer1_start_value_x32 = 0x8 */ + /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U), + /* .. .. reg_ddrc_dis_auto_zq = 0x0 */ + /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_ddr3 = 0x1 */ + /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. reg_ddrc_t_mod = 0x200 */ + /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */ + /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */ + /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */ + /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */ + /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */ + /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */ + /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + /* .. .. t_zq_short_interval_x1024 = 0xc845 */ + /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */ + /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */ + /* .. .. dram_rstn_x1024 = 0x67 */ + /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */ + /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + /* .. .. deeppowerdown_en = 0x0 */ + /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. deeppowerdown_to_x1024 = 0xff */ + /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */ + /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + /* .. .. dfi_wrlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */ + /* .. .. dfi_rdlvl_max_x1024 = 0xfff */ + /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */ + /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */ + /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */ + /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */ + /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */ + /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */ + /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */ + /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */ + /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + /* .. .. reg_ddrc_2t_delay = 0x0 */ + /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */ + /* .. .. reg_ddrc_skip_ocd = 0x1 */ + /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */ + /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U), + /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */ + /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */ + /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */ + /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */ + /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */ + /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */ + /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U), + /* .. .. START: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U), + /* .. .. FINISH: RESET ECC ERROR */ + /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */ + /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + /* .. .. CORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */ + /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */ + /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + /* .. .. STAT_NUM_CORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */ + /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */ + /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + /* .. .. reg_ddrc_ecc_mode = 0x0 */ + /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_scrub = 0x1 */ + /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + /* .. .. reg_phy_dif_on = 0x0 */ + /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */ + /* .. .. reg_phy_dif_off = 0x0 */ + /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_data_slice_in_use = 0x1 */ + /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */ + /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_tx = 0x0 */ + /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_board_lpbk_rx = 0x0 */ + /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_shift_dq = 0x0 */ + /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_err_clr = 0x0 */ + /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */ + /* .. .. reg_phy_dq_offset = 0x40 */ + /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */ + /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */ + /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */ + /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */ + /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U), + /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */ + /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */ + /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */ + /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */ + /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */ + /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */ + /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */ + /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU), + /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */ + /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */ + /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */ + /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */ + /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */ + /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */ + /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U), + /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */ + /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */ + /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */ + /* .. .. reg_phy_fifo_we_in_force = 0x0 */ + /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. .. reg_phy_fifo_we_in_delay = 0x0 */ + /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */ + /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */ + /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */ + /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU), + /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */ + /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */ + /* .. .. reg_phy_wr_data_slave_force = 0x0 */ + /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. .. reg_phy_wr_data_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */ + /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U), + /* .. .. reg_phy_loopback = 0x0 */ + /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_phy_bl2 = 0x0 */ + /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_phy_at_spd_atpg = 0x0 */ + /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_enable = 0x0 */ + /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_force_err = 0x0 */ + /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. reg_phy_bist_mode = 0x0 */ + /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. .. reg_phy_invert_clkout = 0x1 */ + /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */ + /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. .. reg_phy_sel_logic = 0x0 */ + /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */ + /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */ + /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */ + /* .. .. reg_phy_ctrl_slave_force = 0x0 */ + /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */ + /* .. .. reg_phy_use_rank0_delays = 0x1 */ + /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */ + /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */ + /* .. .. reg_phy_lpddr = 0x0 */ + /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */ + /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. .. reg_phy_cmd_latency = 0x0 */ + /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */ + /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */ + /* .. .. reg_phy_int_lpbk = 0x0 */ + /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */ + /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U), + /* .. .. reg_phy_wr_rl_delay = 0x2 */ + /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */ + /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */ + /* .. .. reg_phy_rd_rl_delay = 0x4 */ + /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */ + /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */ + /* .. .. reg_phy_dll_lock_diff = 0xf */ + /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */ + /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */ + /* .. .. reg_phy_use_wr_level = 0x1 */ + /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */ + /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */ + /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */ + /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */ + /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */ + /* .. .. reg_phy_dis_calib_rst = 0x0 */ + /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_phy_ctrl_slave_delay = 0x0 */ + /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U), + /* .. .. reg_arb_page_addr_mask = 0x0 */ + /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_wr_portn = 0x3ff */ + /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */ + /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_rmw_portn = 0x1 */ + /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_arb_pri_rd_portn = 0x3ff */ + /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */ + /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */ + /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */ + /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */ + /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */ + /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */ + /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + /* .. .. reg_ddrc_lpddr2 = 0x0 */ + /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. reg_ddrc_per_bank_refresh = 0x0 */ + /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_derate_enable = 0x0 */ + /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. reg_ddrc_mr4_margin = 0x0 */ + /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U), + /* .. .. reg_ddrc_mr4_read_interval = 0x0 */ + /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */ + /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */ + /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */ + /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */ + /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */ + /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */ + /* .. .. reg_ddrc_t_mrw = 0x5 */ + /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */ + /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */ + /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */ + /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */ + /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */ + /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */ + /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */ + /* .. .. */ + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + /* .. .. START: POLL ON DCI STATUS */ + /* .. .. DONE = 1 */ + /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */ + /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + /* .. .. FINISH: POLL ON DCI STATUS */ + /* .. .. START: UNLOCK DDR */ + /* .. .. reg_ddrc_soft_rstb = 0x1 */ + /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. reg_ddrc_powerdown_en = 0x0 */ + /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. .. reg_ddrc_data_bus_width = 0x0 */ + /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */ + /* .. .. reg_ddrc_burst8_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */ + /* .. .. reg_ddrc_rdwr_idle_gap = 1 */ + /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */ + /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_act_bypass = 0x0 */ + /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */ + /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */ + /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */ + /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */ + /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + /* .. .. FINISH: UNLOCK DDR */ + /* .. .. START: CHECK DDR STATUS */ + /* .. .. ddrc_reg_operating_mode = 1 */ + /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */ + /* .. .. */ + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + /* .. .. FINISH: CHECK DDR STATUS */ + /* .. FINISH: DDR INITIALIZATION */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_mio_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: OCM REMAPPING */ + /* .. VREF_EN = 0x1 */ + /* .. ==> 0XF8000B00[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. CLK_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. SRSTN_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B00[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U), + /* .. FINISH: OCM REMAPPING */ + /* .. START: DDRIOB SETTINGS */ + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B40[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B40[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B40[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B40[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B40[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B40[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B40[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B44[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B44[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B44[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B44[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B44[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B44[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B44[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B48[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B48[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B48[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B48[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B48[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B48[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B48[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x1 */ + /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B50[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B50[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B50[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B50[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B50[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B50[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B50[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B54[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x2 */ + /* .. ==> 0XF8000B54[2:1] = 0x00000002U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B54[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x1 */ + /* .. ==> 0XF8000B54[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. DCR_TYPE = 0x3 */ + /* .. ==> 0XF8000B54[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. IBUF_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B54[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B54[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + /* .. INP_POWER = 0x0 */ + /* .. ==> 0XF8000B58[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. INP_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. DCI_UPDATE = 0x0 */ + /* .. ==> 0XF8000B58[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. TERM_EN = 0x0 */ + /* .. ==> 0XF8000B58[4:4] = 0x00000000U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. DCR_TYPE = 0x0 */ + /* .. ==> 0XF8000B58[6:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */ + /* .. IBUF_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. TERM_DISABLE_MODE = 0x0 */ + /* .. ==> 0XF8000B58[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. OUTPUT_EN = 0x3 */ + /* .. ==> 0XF8000B58[10:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */ + /* .. PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B58[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x3 */ + /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */ + /* .. SLEW_N = 0x3 */ + /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B60[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B60[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B60[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B64[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B64[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B64[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + /* .. DRIVE_P = 0x1c */ + /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */ + /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */ + /* .. DRIVE_N = 0xc */ + /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */ + /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */ + /* .. SLEW_P = 0x6 */ + /* .. ==> 0XF8000B68[18:14] = 0x00000006U */ + /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */ + /* .. SLEW_N = 0x1f */ + /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */ + /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */ + /* .. GTL = 0x0 */ + /* .. ==> 0XF8000B68[26:24] = 0x00000000U */ + /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */ + /* .. RTERM = 0x0 */ + /* .. ==> 0XF8000B68[31:27] = 0x00000000U */ + /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + /* .. VREF_INT_EN = 0x0 */ + /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. VREF_SEL = 0x0 */ + /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */ + /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */ + /* .. VREF_EXT_EN = 0x3 */ + /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */ + /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */ + /* .. VREF_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */ + /* .. REFIO_EN = 0x1 */ + /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */ + /* .. REFIO_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DRST_B_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. CKE_PULLUP_EN = 0x0 */ + /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */ + /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U), + /* .. .. START: ASSERT RESET */ + /* .. .. RESET = 1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U), + /* .. .. FINISH: ASSERT RESET */ + /* .. .. START: DEASSERT RESET */ + /* .. .. RESET = 0 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + /* .. .. FINISH: DEASSERT RESET */ + /* .. .. RESET = 0x1 */ + /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. .. ENABLE = 0x1 */ + /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. .. VRP_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. .. VRN_TRI = 0x0 */ + /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. .. VRP_OUT = 0x0 */ + /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */ + /* .. .. VRN_OUT = 0x1 */ + /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */ + /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */ + /* .. .. NREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */ + /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. .. NREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */ + /* .. .. NREF_OPT4 = 0x1 */ + /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */ + /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */ + /* .. .. PREF_OPT1 = 0x0 */ + /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */ + /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */ + /* .. .. PREF_OPT2 = 0x0 */ + /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */ + /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */ + /* .. .. UPDATE_CONTROL = 0x0 */ + /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */ + /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. .. INIT_COMPLETE = 0x0 */ + /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */ + /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. .. TST_CLK = 0x0 */ + /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */ + /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. .. TST_HLN = 0x0 */ + /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */ + /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. .. TST_HLP = 0x0 */ + /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */ + /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. .. TST_RST = 0x0 */ + /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */ + /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */ + /* .. .. INT_DCI_EN = 0x0 */ + /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */ + /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U), + /* .. FINISH: DDRIOB SETTINGS */ + /* .. START: MIO PROGRAMMING */ + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000704[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000704[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000704[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000704[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000704[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000704[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000704[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000704[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000704[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000708[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000708[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000708[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000708[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000708[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000708[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000708[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000708[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000708[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800070C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800070C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800070C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800070C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800070C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800070C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800070C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800070C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800070C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000710[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000710[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000710[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000710[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000710[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000710[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000710[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000710[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000710[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000714[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000714[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000714[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000714[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000714[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000714[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000714[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000714[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000714[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000718[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000718[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000718[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000718[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000718[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000718[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000718[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000718[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000718[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000740[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000740[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000740[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000740[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000740[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000740[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000740[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000740[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000740[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000744[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000744[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000744[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000744[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000744[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000744[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000744[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000744[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000744[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000748[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000748[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000748[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000748[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000748[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000748[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000748[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000748[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000748[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800074C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800074C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800074C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800074C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800074C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800074C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800074C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800074C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF800074C[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000750[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000750[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000750[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000750[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000750[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000750[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000750[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000750[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000750[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000754[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000754[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000754[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000754[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000754[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000754[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000754[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000754[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 1 */ + /* .. ==> 0XF8000754[13:13] = 0x00000001U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000758[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000758[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000758[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000758[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000758[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000758[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000758[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000758[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000758[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800075C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800075C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800075C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800075C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800075C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800075C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800075C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800075C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800075C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000760[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000760[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000760[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000760[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000760[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000760[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000760[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000760[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000760[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000764[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000764[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000764[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000764[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000764[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000764[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000764[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000764[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000764[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000768[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000768[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000768[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000768[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000768[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000768[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF8000768[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000768[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000768[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800076C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF800076C[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800076C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800076C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800076C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800076C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 4 */ + /* .. ==> 0XF800076C[11:9] = 0x00000004U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800076C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800076C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000770[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000770[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000770[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000770[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000770[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000770[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000770[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000770[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000770[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000774[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000774[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000774[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000774[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000774[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000774[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000774[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000774[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000774[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000778[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000778[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000778[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000778[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000778[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000778[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000778[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000778[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000778[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF800077C[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800077C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800077C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800077C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800077C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800077C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800077C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800077C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800077C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000780[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000780[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000780[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000780[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000780[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000780[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000780[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000780[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000780[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000784[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000784[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000784[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000784[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000784[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000784[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000784[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000784[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000784[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000788[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000788[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000788[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000788[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000788[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000788[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000788[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000788[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000788[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800078C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800078C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800078C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800078C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800078C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800078C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800078C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800078C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800078C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF8000790[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000790[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000790[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000790[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000790[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000790[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000790[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000790[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000790[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000794[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000794[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000794[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000794[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000794[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000794[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000794[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000794[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000794[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000798[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000798[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF8000798[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000798[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000798[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000798[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF8000798[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000798[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000798[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800079C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800079C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 1 */ + /* .. ==> 0XF800079C[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800079C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800079C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF800079C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF800079C[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800079C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800079C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007A8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007A8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007A8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007A8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007A8[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007A8[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007A8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007A8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007A8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007AC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007AC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007AC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007AC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007AC[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007AC[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007AC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007AC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007AC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B0[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007B4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 1 */ + /* .. ==> 0XF80007B4[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007B4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007BC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007BC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007BC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007BC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C0[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U), + /* .. TRI_ENABLE = 1 */ + /* .. ==> 0XF80007C4[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 7 */ + /* .. ==> 0XF80007C4[7:5] = 0x00000007U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D0[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D0[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D0[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D0[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D0[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D0[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D0[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D0[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007D4[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007D4[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007D4[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007D4[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 4 */ + /* .. ==> 0XF80007D4[7:5] = 0x00000004U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007D4[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007D4[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007D4[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007D4[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + /* .. SDIO0_WP_SEL = 55 */ + /* .. ==> 0XF8000830[5:0] = 0x00000037U */ + /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */ + /* .. SDIO0_CD_SEL = 47 */ + /* .. ==> 0XF8000830[21:16] = 0x0000002FU */ + /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U), + /* .. FINISH: MIO PROGRAMMING */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B48[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B50[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + /* .. IBUF_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[7:7] = 0x00000001U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */ + /* .. TERM_DISABLE_MODE = 0x1 */ + /* .. ==> 0XF8000B54[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. */ + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* .. START: SRAM/NOR SET OPMODE */ + /* .. FINISH: SRAM/NOR SET OPMODE */ + /* .. START: UART REGISTERS */ + /* .. BDIV = 0x6 */ + /* .. ==> 0XE0001034[7:0] = 0x00000006U */ + /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ + /* .. */ + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + /* .. CD = 0x3e */ + /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. */ + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + /* .. STPBRK = 0x0 */ + /* .. ==> 0XE0001000[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. STTBRK = 0x0 */ + /* .. ==> 0XE0001000[7:7] = 0x00000000U */ + /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ + /* .. RSTTO = 0x0 */ + /* .. ==> 0XE0001000[6:6] = 0x00000000U */ + /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ + /* .. TXDIS = 0x0 */ + /* .. ==> 0XE0001000[5:5] = 0x00000000U */ + /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ + /* .. TXEN = 0x1 */ + /* .. ==> 0XE0001000[4:4] = 0x00000001U */ + /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ + /* .. RXDIS = 0x0 */ + /* .. ==> 0XE0001000[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. RXEN = 0x1 */ + /* .. ==> 0XE0001000[2:2] = 0x00000001U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ + /* .. TXRES = 0x1 */ + /* .. ==> 0XE0001000[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. RXRES = 0x1 */ + /* .. ==> 0XE0001000[0:0] = 0x00000001U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ + /* .. */ + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + /* .. IRMODE = 0x0 */ + /* .. ==> 0XE0001004[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. UCLKEN = 0x0 */ + /* .. ==> 0XE0001004[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. CHMODE = 0x0 */ + /* .. ==> 0XE0001004[9:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ + /* .. NBSTOP = 0x0 */ + /* .. ==> 0XE0001004[7:6] = 0x00000000U */ + /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ + /* .. PAR = 0x4 */ + /* .. ==> 0XE0001004[5:3] = 0x00000004U */ + /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ + /* .. CHRL = 0x0 */ + /* .. ==> 0XE0001004[2:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ + /* .. CLKS = 0x0 */ + /* .. ==> 0XE0001004[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), + /* .. FINISH: UART REGISTERS */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: QSPI REGISTERS */ + /* .. Holdb_dr = 1 */ + /* .. ==> 0XE000D000[19:19] = 0x00000001U */ + /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */ + /* .. */ + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + /* .. FINISH: QSPI REGISTERS */ + /* .. START: PL POWER ON RESET REGISTERS */ + /* .. PCFG_POR_CNT_4K = 0 */ + /* .. ==> 0XF8007000[29:29] = 0x00000000U */ + /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + /* .. FINISH: PL POWER ON RESET REGISTERS */ + /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */ + /* .. .. START: NAND SET CYCLE */ + /* .. .. FINISH: NAND SET CYCLE */ + /* .. .. START: OPMODE */ + /* .. .. FINISH: OPMODE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: SRAM/NOR CS0 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS0 BASE ADDRESS */ + /* .. .. FINISH: NOR CS0 BASE ADDRESS */ + /* .. .. START: SRAM/NOR CS1 SET CYCLE */ + /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */ + /* .. .. START: DIRECT COMMAND */ + /* .. .. FINISH: DIRECT COMMAND */ + /* .. .. START: NOR CS1 BASE ADDRESS */ + /* .. .. FINISH: NOR CS1 BASE ADDRESS */ + /* .. .. START: USB RESET */ + /* .. .. .. START: USB0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB0 RESET */ + /* .. .. .. START: USB1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: USB1 RESET */ + /* .. .. FINISH: USB RESET */ + /* .. .. START: ENET RESET */ + /* .. .. .. START: ENET0 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET0 RESET */ + /* .. .. .. START: ENET1 RESET */ + /* .. .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. FINISH: DIR MODE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: ENET1 RESET */ + /* .. .. FINISH: ENET RESET */ + /* .. .. START: I2C RESET */ + /* .. .. .. START: I2C0 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C0 RESET */ + /* .. .. .. START: I2C1 RESET */ + /* .. .. .. .. START: DIR MODE GPIO BANK0 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */ + /* .. .. .. .. START: DIR MODE GPIO BANK1 */ + /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: OUTPUT ENABLE */ + /* .. .. .. .. FINISH: OUTPUT ENABLE */ + /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ + /* .. .. .. .. START: ADD 1 MS DELAY */ + /* .. .. .. .. */ + EMIT_MASKDELAY(0XF8F00200, 1), + /* .. .. .. .. FINISH: ADD 1 MS DELAY */ + /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ + /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ + /* .. .. .. FINISH: I2C1 RESET */ + /* .. .. FINISH: I2C RESET */ + /* .. .. START: NOR CHIP SELECT */ + /* .. .. .. START: DIR MODE BANK 0 */ + /* .. .. .. FINISH: DIR MODE BANK 0 */ + /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ + /* .. .. .. START: OUTPUT ENABLE BANK 0 */ + /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ + /* .. .. FINISH: NOR CHIP SELECT */ + /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_post_config_1_0[] = { + /* START: top */ + /* .. START: SLCR SETTINGS */ + /* .. UNLOCK_KEY = 0XDF0D */ + /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */ + /* .. */ + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), + /* .. FINISH: SLCR SETTINGS */ + /* .. START: ENABLING LEVEL SHIFTER */ + /* .. USER_INP_ICT_EN_0 = 3 */ + /* .. ==> 0XF8000900[1:0] = 0x00000003U */ + /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */ + /* .. USER_INP_ICT_EN_1 = 3 */ + /* .. ==> 0XF8000900[3:2] = 0x00000003U */ + /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */ + /* .. */ + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + /* .. FINISH: ENABLING LEVEL SHIFTER */ + /* .. START: TPIU WIDTH IN CASE OF EMIO */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0XC5ACCE55 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. .. START: TRACE CURRENT PORT SIZE */ + /* .. .. a = 2 */ + /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), + /* .. .. FINISH: TRACE CURRENT PORT SIZE */ + /* .. .. START: TRACE LOCK ACCESS REGISTER */ + /* .. .. a = 0X0 */ + /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), + /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ + /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ + /* .. START: FPGA RESETS TO 0 */ + /* .. reserved_3 = 0 */ + /* .. ==> 0XF8000240[31:25] = 0x00000000U */ + /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */ + /* .. FPGA_ACP_RST = 0 */ + /* .. ==> 0XF8000240[24:24] = 0x00000000U */ + /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */ + /* .. FPGA_AXDS3_RST = 0 */ + /* .. ==> 0XF8000240[23:23] = 0x00000000U */ + /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */ + /* .. FPGA_AXDS2_RST = 0 */ + /* .. ==> 0XF8000240[22:22] = 0x00000000U */ + /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */ + /* .. FPGA_AXDS1_RST = 0 */ + /* .. ==> 0XF8000240[21:21] = 0x00000000U */ + /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */ + /* .. FPGA_AXDS0_RST = 0 */ + /* .. ==> 0XF8000240[20:20] = 0x00000000U */ + /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */ + /* .. reserved_2 = 0 */ + /* .. ==> 0XF8000240[19:18] = 0x00000000U */ + /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */ + /* .. FSSW1_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[17:17] = 0x00000000U */ + /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */ + /* .. FSSW0_FPGA_RST = 0 */ + /* .. ==> 0XF8000240[16:16] = 0x00000000U */ + /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */ + /* .. reserved_1 = 0 */ + /* .. ==> 0XF8000240[15:14] = 0x00000000U */ + /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */ + /* .. FPGA_FMSW1_RST = 0 */ + /* .. ==> 0XF8000240[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. FPGA_FMSW0_RST = 0 */ + /* .. ==> 0XF8000240[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. FPGA_DMA3_RST = 0 */ + /* .. ==> 0XF8000240[11:11] = 0x00000000U */ + /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ + /* .. FPGA_DMA2_RST = 0 */ + /* .. ==> 0XF8000240[10:10] = 0x00000000U */ + /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ + /* .. FPGA_DMA1_RST = 0 */ + /* .. ==> 0XF8000240[9:9] = 0x00000000U */ + /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */ + /* .. FPGA_DMA0_RST = 0 */ + /* .. ==> 0XF8000240[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. reserved = 0 */ + /* .. ==> 0XF8000240[7:4] = 0x00000000U */ + /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */ + /* .. FPGA3_OUT_RST = 0 */ + /* .. ==> 0XF8000240[3:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ + /* .. FPGA2_OUT_RST = 0 */ + /* .. ==> 0XF8000240[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. FPGA1_OUT_RST = 0 */ + /* .. ==> 0XF8000240[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. FPGA0_OUT_RST = 0 */ + /* .. ==> 0XF8000240[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + /* .. FINISH: FPGA RESETS TO 0 */ + /* .. START: AFI REGISTERS */ + /* .. .. START: AFI0 REGISTERS */ + /* .. .. FINISH: AFI0 REGISTERS */ + /* .. .. START: AFI1 REGISTERS */ + /* .. .. FINISH: AFI1 REGISTERS */ + /* .. .. START: AFI2 REGISTERS */ + /* .. .. FINISH: AFI2 REGISTERS */ + /* .. .. START: AFI3 REGISTERS */ + /* .. .. FINISH: AFI3 REGISTERS */ + /* .. FINISH: AFI REGISTERS */ + /* .. START: LOCK IT BACK */ + /* .. LOCK_KEY = 0X767B */ + /* .. ==> 0XF8000004[15:0] = 0x0000767BU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */ + /* .. */ + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), + /* .. FINISH: LOCK IT BACK */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +unsigned long ps7_debug_1_0[] = { + /* START: top */ + /* .. START: CROSS TRIGGER CONFIGURATIONS */ + /* .. .. START: UNLOCKING CTI REGISTERS */ + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. KEY = 0XC5ACCE55 */ + /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ + /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), + /* .. .. FINISH: UNLOCKING CTI REGISTERS */ + /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ + /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ + /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ + /* FINISH: top */ + /* */ + EMIT_EXIT(), + + /* */ +}; + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char *getPS7MessageInfo(unsigned key) +{ + char *err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: + err_msg = "PS7 initialization successful"; + break; + case PS7_INIT_CORRUPT: + err_msg = "PS7 init Data Corrupted"; + break; + case PS7_INIT_TIMEOUT: + err_msg = "PS7 init mask poll timeout"; + break; + case PS7_POLL_FAILED_DDR_INIT: + err_msg = "Mask Poll failed for DDR Init"; + break; + case PS7_POLL_FAILED_DMA: + err_msg = "Mask Poll failed for PLL Init"; + break; + case PS7_POLL_FAILED_PLL: + err_msg = "Mask Poll failed for DMA done bit"; + break; + default: + err_msg = "Undefined error status"; + break; + } + + return err_msg; +} + +unsigned long ps7GetSiliconVersion(void) +{ + /* Read PS version from MCTRL register [31:28] */ + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long *)0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write(unsigned long add, unsigned long mask, unsigned long val) +{ + unsigned long *addr = (unsigned long *)add; + *addr = (val & mask) | (*addr & ~mask); +} + +int mask_poll(unsigned long add, unsigned long mask) +{ + volatile unsigned long *addr = (volatile unsigned long *)add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) + return -1; + i++; + } + return 1; +} + +unsigned long mask_read(unsigned long add, unsigned long mask) +{ + unsigned long *addr = (unsigned long *)add; + unsigned long val = (*addr & mask); + return val; +} + +int ps7_config(unsigned long *ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; /* current instruction .. */ + unsigned long args[16]; /* no opcode has so many args ... */ + int numargs; /* number of arguments of this instruction */ + int j; /* general purpose index */ + + volatile unsigned long *addr; /* some variable to make code readable */ + unsigned long val, mask; /* some variable to make code readable */ + + int finish = -1; /* loop while this is negative ! */ + int i = 0; /* Timeout variable */ + + while (finish < 0) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for (j = 0; j < numargs; j++) + args[j] = ptr[j + 1]; + ptr += numargs + 1; + + switch (opcode) { + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long *)args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long *)args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long *)args[0]; + mask = args[1]; + val = args[2]; + *addr = (val & mask) | (*addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long *)args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long *)args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) + ; + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int ps7_post_config(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config(ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config(ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else { + ret = ps7_config(ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } + return PS7_INIT_SUCCESS; +} + +int ps7_debug(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config(ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config(ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } else { + ret = ps7_config(ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + } + return PS7_INIT_SUCCESS; +} + +int ps7_init(void) +{ + /* Get the PS_VERSION on run time */ + unsigned long si_ver = ps7GetSiliconVersion(); + int ret; + /*int pcw_ver = 0; */ + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + /*pcw_ver = 1; */ + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + /*pcw_ver = 2; */ + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + /*pcw_ver = 3; */ + } + + /* MIO init */ + ret = ps7_config(ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* PLL init */ + ret = ps7_config(ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* Clock init */ + ret = ps7_config(ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* DDR init */ + ret = ps7_config(ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + /* Peripherals init */ + ret = ps7_config(ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} + +/* For delay calculation using global timer */ + +/* start timer */ +void perf_start_clock(void) +{ + *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */ + (1 << 3) | /* Auto-increment */ + (0 << 8) /* Pre-scale */ + ); +} + +/* stop timer and reset timer count regs */ +void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */ + return APU_FREQ * delay / (2 * 1000); +} + +/* stop timer */ +void perf_disable_clock(void) +{ + *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer(void) +{ + perf_reset_clock(); + perf_start_clock(); +} diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h new file mode 100644 index 00000000000..62b8a5846b6 --- /dev/null +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*typedef unsigned int u32; */ + +/** do we need to make this name more unique ? **/ +/*extern u32 ps7_init_data[]; */ +extern unsigned long *ps7_ddr_init_data; +extern unsigned long *ps7_mio_init_data; +extern unsigned long *ps7_pll_init_data; +extern unsigned long *ps7_clock_init_data; +extern unsigned long *ps7_peripherals_init_data; + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) +#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr +#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val +#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val +#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask +#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ +#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ +#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ +#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ +#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ +#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 650000000 +#define DDR_FREQ 525000000 +#define DCI_FREQ 10096154 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 108333336 +#define WDT_FREQ 108333336 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 175000000 +#define FPGA2_FREQ 12264151 +#define FPGA3_FREQ 100000000 + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config(unsigned long *); +int ps7_init(void); +int ps7_post_config(void); +int ps7_debug(void); +char *getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(void); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d105bb4de32..2cf47125d43 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -65,53 +65,6 @@ void scsi_init(void) } #endif -int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#if defined(CONFIG_ZYNQ_GEM) -# if defined(CONFIG_ZYNQ_GEM0) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, - CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM1) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, - CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM2) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, - CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); -# endif -# if defined(CONFIG_ZYNQ_GEM3) - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, - CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); -# endif -#endif - return ret; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bd) -{ - int ret = 0; - - u32 ver = zynqmp_get_silicon_version(); - - if (ver != ZYNQMP_CSU_VERSION_VELOCE) { -#if defined(CONFIG_ZYNQ_SDHCI) -# if defined(CONFIG_ZYNQ_SDHCI0) - ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); -# endif -# if defined(CONFIG_ZYNQ_SDHCI1) - ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); -# endif -#endif - } - - return ret; -} -#endif - int board_late_init(void) { u32 reg = 0; diff --git a/board/zyxel/nsa310s/Kconfig b/board/zyxel/nsa310s/Kconfig new file mode 100644 index 00000000000..77e734d0e21 --- /dev/null +++ b/board/zyxel/nsa310s/Kconfig @@ -0,0 +1,20 @@ +# +# Copyright (C) 2015 +# Gerald Kerma <dreagle@doukki.net> +# Tony Dinh <mibodhi@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if TARGET_NSA310S + +config SYS_BOARD + default "nsa310s" + +config SYS_VENDOR + default "zyxel" + +config SYS_CONFIG_NAME + default "nsa310s" + +endif diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS new file mode 100644 index 00000000000..d153758c218 --- /dev/null +++ b/board/zyxel/nsa310s/MAINTAINERS @@ -0,0 +1,8 @@ +NSA310S BOARD +M: Gerald Kerma <dreagle@doukki.net> +M: Tony Dinh <mibodhi@gmail.com> +M: Luka Perkov <luka.perkov@sartura.hr> +S: Maintained +F: board/zyxel/nsa310s/ +F: include/configs/nsa310s.h +F: configs/nsa310s_defconfig diff --git a/board/zyxel/nsa310s/Makefile b/board/zyxel/nsa310s/Makefile new file mode 100644 index 00000000000..43cdb86c205 --- /dev/null +++ b/board/zyxel/nsa310s/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 +# Gerald Kerma <dreagle@doukki.net> +# Tony Dinh <mibodhi@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nsa310s.o diff --git a/board/zyxel/nsa310s/kwbimage.cfg b/board/zyxel/nsa310s/kwbimage.cfg new file mode 100644 index 00000000000..e8f4b8a69ff --- /dev/null +++ b/board/zyxel/nsa310s/kwbimage.cfg @@ -0,0 +1,43 @@ +# +# Copyright (C) 2015 +# Gerald Kerma <dreagle@doukki.net> +# Tony Dinh <mibodhi@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer to doc/README.kwbimage for more details about how-to +# configure and create kirkwood boot images. +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +DATA 0xFFD01400 0x43010c30 +DATA 0xFFD01404 0x39543000 +DATA 0xFFD01408 0x22125451 +DATA 0xFFD0140C 0x00000833 +DATA 0xFFD01410 0x0000000C +DATA 0xFFD01414 0x00000000 +DATA 0xFFD01418 0x00000000 +DATA 0xFFD0141C 0x00000652 +DATA 0xFFD01420 0x00000004 +DATA 0xFFD01424 0x0000F17F +DATA 0xFFD01428 0x00085520 +DATA 0xFFD0147c 0x00008552 +DATA 0xFFD01504 0x0FFFFFF1 +DATA 0xFFD01508 0x10000000 +DATA 0xFFD0150C 0x00000000 +DATA 0xFFD01514 0x00000000 +DATA 0xFFD0151C 0x00000000 +DATA 0xFFD01494 0x00010000 +DATA 0xFFD01498 0x00000000 +DATA 0xFFD0149C 0x0000E403 +DATA 0xFFD01480 0x00000001 +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0x0 0x0 diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c new file mode 100644 index 00000000000..aab33cfa2a2 --- /dev/null +++ b/board/zyxel/nsa310s/nsa310s.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2015 + * Gerald Kerma <dreagle@doukki.net> + * Tony Dinh <mibodhi@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/io.h> +#include "nsa310s.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH, + NSA310S_OE_LOW, NSA310S_OE_HIGH); + + /* (all LEDs & power off active high) */ + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_GPIO, + MPP14_GPIO, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ + u16 reg; + u16 phyaddr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* read PHY dev address */ + if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) { + printf("could not read PHY dev address\n"); + return; + } + + /* set RGMII delay */ + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); + miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®); + reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL); + miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); + + /* reset PHY */ + if (miiphy_reset(name, phyaddr)) + return; + + /* + * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318) + * and has an MCU attached to the LED[2] via tristate interrupt + */ + + /* switch to LED register page */ + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); + /* read out LED polarity register */ + miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®); + /* clear 4, set 5 - LED2 low, tri-state */ + reg &= ~(MV88E1318_LED2_4); + reg |= (MV88E1318_LED2_5); + /* write back LED polarity register */ + miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg); + /* jump back to page 0, per the PHY chip documenation. */ + miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); + + /* set PHY back to auto-negotiation mode */ + miiphy_write(name, phyaddr, 0x4, 0x1e1); + miiphy_write(name, phyaddr, 0x9, 0x300); + /* downshift */ + miiphy_write(name, phyaddr, 0x10, 0x3860); + miiphy_write(name, phyaddr, 0x0, 0x9140); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/zyxel/nsa310s/nsa310s.h b/board/zyxel/nsa310s/nsa310s.h new file mode 100644 index 00000000000..1ea110560f8 --- /dev/null +++ b/board/zyxel/nsa310s/nsa310s.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2015 + * Gerald Kerma <dreagle@doukki.net> + * Tony Dinh <mibodhi@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __NSA310S_H +#define __NSA310S_H + +/* low GPIO's */ +#define HDD1_GREEN_LED (1 << 16) +#define HDD1_RED_LED (1 << 13) +#define USB_GREEN_LED (1 << 15) +#define USB_POWER (1 << 21) +#define SYS_GREEN_LED (1 << 28) +#define SYS_ORANGE_LED (1 << 29) + +#define COPY_GREEN_LED (1 << 22) +#define COPY_RED_LED (1 << 23) + +#define PIN_USB_GREEN_LED 15 +#define PIN_USB_POWER 21 + +#define NSA310S_OE_LOW (~(0)) +#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER) + +/* high GPIO's */ +#define HDD2_GREEN_LED (1 << 2) +#define HDD2_POWER (1 << 1) + +#define NSA310S_OE_HIGH (~(0)) +#define NSA310S_VAL_HIGH (HDD2_POWER) + +/* PHY related */ +#define MV88E1318_PGADR_REG 22 +#define MV88E1318_MAC_CTRL_PG 2 +#define MV88E1318_MAC_CTRL_REG 21 +#define MV88E1318_RGMII_TX_CTRL (1 << 4) +#define MV88E1318_RGMII_RX_CTRL (1 << 5) +#define MV88E1318_LED_PG 3 +#define MV88E1318_LED_POL_REG 17 +#define MV88E1318_LED2_4 (1 << 4) +#define MV88E1318_LED2_5 (1 << 5) + +#endif /* __NSA310S_H */ |