diff options
Diffstat (limited to 'cpu/arm720t/cpu.c')
| -rw-r--r-- | cpu/arm720t/cpu.c | 171 |
1 files changed, 122 insertions, 49 deletions
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 0ad5481fd22..58eab4e550e 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -33,51 +33,7 @@ #include <common.h> #include <command.h> #include <clps7111.h> - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - /* printf("p15/c1 is = %08lx\n", value); */ - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - /* printf("write %08lx to p15/c1\n", value); */ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_IDC (1<<2) /* icache and/or dcache off/on */ -#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#include <asm/hardware.h> int cpu_init (void) { @@ -103,12 +59,11 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */ +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) unsigned long i; disable_interrupts (); -#ifdef CONFIG_NETARM - return 0; -#endif + /* turn off I-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~0x1000; @@ -116,11 +71,16 @@ int cleanup_before_linux (void) /* flush I-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) + disable_interrupts (); + /* Nothing more needed */ +#else +#error No cleanup_before_linux() defined for this CPU type +#endif return 0; } @@ -134,6 +94,57 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } +/* + * Instruction and Data cache enable and disable functions + * + */ + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1(void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + /* printf("p15/c1 is = %08lx\n", value); */ + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1(unsigned long value) +{ + /* printf("write %08lx to p15/c1\n", value); */ + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1(); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_IDC (1<<2) /* icache and/or dcache off/on */ +#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + void icache_enable (void) { ulong reg; @@ -179,3 +190,65 @@ int dcache_status (void) { return (read_p15_c1 () & C1_IDC) != 0; } + +#elif defined(CONFIG_S3C4510B) + +void icache_enable (void) +{ + s32 i; + + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); + + /* 8KB cache, write enable */ + SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + + /* clear TAG RAM bits */ + for ( i = 0; i < 256; i++) + PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + + /* clear SET0 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + + /* clear SET1 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + + /* enable cache */ + SET_REG( REG_SYSCFG, CACHE_ENABLE); + +} + +void icache_disable (void) +{ + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); +} + +int icache_status (void) +{ + return GET_REG( REG_SYSCFG) & CACHE_ENABLE; +} + +void dcache_enable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_enable(); +} + +void dcache_disable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_disable(); +} + +int dcache_status (void) +{ + /* we don't have seperate instruction/data caches */ + return icache_status(); +} + +#else +#error No icache/dcache enable/disable functions defined for this CPU type +#endif |