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-rw-r--r--cpu/arm926ejs/at91/at91cap9_devices.c128
-rw-r--r--cpu/arm926ejs/at91/at91sam9260_devices.c124
-rw-r--r--cpu/arm926ejs/at91/at91sam9261_devices.c84
-rw-r--r--cpu/arm926ejs/at91/at91sam9263_devices.c137
-rw-r--r--cpu/arm926ejs/at91/at91sam9m10g45_devices.c120
-rw-r--r--cpu/arm926ejs/at91/at91sam9rl_devices.c58
-rw-r--r--cpu/arm926ejs/at91/clock.c60
-rw-r--r--cpu/arm926ejs/at91/cpu.c46
-rw-r--r--cpu/arm926ejs/at91/led.c1
-rw-r--r--cpu/arm926ejs/at91/lowlevel_init.S95
-rw-r--r--cpu/arm926ejs/at91/reset.c8
-rw-r--r--cpu/arm926ejs/at91/timer.c17
-rw-r--r--cpu/arm926ejs/mx25/Makefile46
-rw-r--r--cpu/arm926ejs/mx25/generic.c263
-rw-r--r--cpu/arm926ejs/mx25/reset.c56
-rw-r--r--cpu/arm926ejs/mx25/timer.c187
-rw-r--r--cpu/arm926ejs/mx27/generic.c5
-rw-r--r--cpu/arm926ejs/start.S42
18 files changed, 1098 insertions, 379 deletions
diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c
index 39e405fee13..2d878fdde6d 100644
--- a/cpu/arm926ejs/at91/at91cap9_devices.c
+++ b/cpu/arm926ejs/at91/at91cap9_devices.c
@@ -34,30 +34,38 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
+ writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
+ writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
+ writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -82,71 +90,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
+ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
+ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
+ writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_B_periph(AT91_PIN_PA5, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PA3, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PD0, 1);
+ at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PD1, 1);
+ at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA5, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PD0, 1);
+ at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD1, 1);
+ at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1);
+ writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB15, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_A_periph(AT91_PIN_PB16, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PB17, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PB18, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB15, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB16, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PB17, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PB18, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
}
@@ -155,26 +167,26 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
+ at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
- at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
- at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
+ at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */
+ at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
+ at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
+ at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
+ at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
+ at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
#endif
}
#endif
@@ -182,10 +194,12 @@ void at91_macb_hw_init(void)
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */
- at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN);
+ writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c
index f86cb99da65..77d49ab1c76 100644
--- a/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD0 */
+ writel(1 << AT91SAM9260_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* RXD1 */
+ writel(1 << AT91SAM9260_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* RXD2 */
+ writel(1 << AT91SAM9260_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -78,71 +86,75 @@ void at91_serial_hw_init(void)
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+ writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PA3, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PC11, 1);
+ at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PC16, 1);
+ at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PC17, 1);
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PC11, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PC16, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PC17, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI1_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1);
+ writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB3, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PC5, 1);
+ at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PC4, 1);
+ at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_gpio_output(AT91_PIN_PC3, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB3, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PC5, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PC4, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PC3, 1);
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}
}
#endif
@@ -150,35 +162,35 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
+ at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
+ at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
+ at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
+ at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
+ at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
+ at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
/*
* use PA10, PA11 for ETX2, ETX3.
* PA23 and PA24 are for TWI EEPROM
*/
- at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
+ at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
+ at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
#else
- at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
+ at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
+ at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
#endif
- at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
+ at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
#endif
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c
index 16d411f6532..b4353ef5cb5 100644
--- a/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
+ writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
+ writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
+ writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -78,71 +86,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
+ writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PA3, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_A_periph(AT91_PIN_PA4, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PA5, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PA6, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA4, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PA5, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PA6, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
+ writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB28, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PA24, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PA25, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PA26, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB28, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA24, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PA25, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PA26, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
}
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c
index f72efdfe807..deda3e54d92 100644
--- a/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -27,37 +27,46 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/arch/at91_pio.h>
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
+ writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
+ writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
+ writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -82,71 +91,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
+ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
+ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
+ writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_B_periph(AT91_PIN_PA5, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PA3, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PA4, 1);
+ at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PB11, 1);
+ at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA5, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PA4, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PB11, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1);
+ writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB15, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_A_periph(AT91_PIN_PB16, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PB17, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PB18, 1);
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB15, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB16, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PB17, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PB18, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
}
#endif
@@ -154,26 +167,26 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
- at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
+ at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */
+ at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
- at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
- at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
+ at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */
+ at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
+ at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
+ at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
+ at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
+ at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
#endif
}
#endif
@@ -182,18 +195,20 @@ void at91_macb_hw_init(void)
void at91_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
- at91_set_gpio_output(AT91_PIN_PA21, 0);
- at91_set_gpio_output(AT91_PIN_PA24, 0);
+ at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
+ at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
}
#endif
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */
- at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN);
+ writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
index 98d90f2514b..4ad9b1fcc98 100644
--- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */
+ writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */
+ writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */
+ writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -78,71 +86,75 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
+ writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB3, 0);
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PB18, 0);
+ at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PB19, 0);
+ at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PD27, 0);
+ at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB3, 0);
+ at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB18, 0);
+ at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PB19, 0);
+ at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD27, 0);
+ at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);
+ writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB17, 0);
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PD28, 0);
+ at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PD18, 0);
+ at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PD19, 0);
+ at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB17, 0);
+ at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PD28, 0);
+ at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PD18, 0);
+ at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD19, 0);
+ at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
}
}
@@ -151,25 +163,25 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
+ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
- at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
- at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
+ at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
+ at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
+ at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
+ at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
+ at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
+ at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
+ at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
+ at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
#endif
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c
index ebed193052c..4f570f4fb55 100644
--- a/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -30,30 +30,38 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */
+ writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */
+ writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */
+ writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
@@ -78,36 +86,38 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
+ writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PA28, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PB7, 1);
+ at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PD8, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PD9, 1);
+ at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA28, 1);
+ at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB7, 1);
+ at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PD8, 1);
+ at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD9, 1);
+ at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
}
}
#endif
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
index 574f48824c0..b06d7601b91 100644
--- a/cpu/arm926ejs/at91/clock.c
+++ b/cpu/arm926ejs/at91/clock.c
@@ -13,9 +13,9 @@
#include <config.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
-#include <asm/arch/io.h>
static unsigned long cpu_clk_rate_hz;
static unsigned long main_clk_rate_hz;
@@ -57,14 +57,14 @@ u32 get_pllb_init(void)
static unsigned long at91_css_to_rate(unsigned long css)
{
switch (css) {
- case AT91_PMC_CSS_SLOW:
- return AT91_SLOW_CLOCK;
- case AT91_PMC_CSS_MAIN:
- return main_clk_rate_hz;
- case AT91_PMC_CSS_PLLA:
- return plla_rate_hz;
- case AT91_PMC_CSS_PLLB:
- return pllb_rate_hz;
+ case AT91_PMC_MCKR_CSS_SLOW:
+ return AT91_SLOW_CLOCK;
+ case AT91_PMC_MCKR_CSS_MAIN:
+ return main_clk_rate_hz;
+ case AT91_PMC_MCKR_CSS_PLLA:
+ return plla_rate_hz;
+ case AT91_PMC_MCKR_CSS_PLLB:
+ return pllb_rate_hz;
}
return 0;
@@ -146,7 +146,8 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
int at91_clock_init(unsigned long main_clock)
{
unsigned freq, mckr;
-#ifndef AT91_MAIN_CLOCK
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@@ -156,15 +157,16 @@ int at91_clock_init(unsigned long main_clock)
*/
if (!main_clock) {
do {
- tmp = at91_sys_read(AT91_CKGR_MCFR);
- } while (!(tmp & AT91_PMC_MAINRDY));
- main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+ tmp = readl(&pmc->mcfr);
+ } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+ tmp &= AT91_PMC_MCFR_MAINF_MASK;
+ main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
- plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+ plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
@@ -174,7 +176,7 @@ int at91_clock_init(unsigned long main_clock)
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
- AT91_PMC_USB96M;
+ AT91_PMC_PLLBR_USBDIV_2;
pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
#endif
@@ -182,28 +184,32 @@ int at91_clock_init(unsigned long main_clock)
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
- mckr = at91_sys_read(AT91_PMC_MCKR);
+ mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
- freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
+ mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = mck_rate_hz;
- freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
+ freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
- mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
+ /* mdiv */
+ mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
- mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
- freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- if (mckr & AT91_PMC_PDIV)
- freq /= 2; /* processor clock division */
+ /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+ mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+ freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
+ if (mckr & AT91_PMC_MCKR_MDIV_MASK)
+ freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
- mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
- freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
+ mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
+ ? freq / 3
+ : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
- mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
+ mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
cpu_clk_rate_hz = freq;
- return 0;
+ return 0;
}
diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c
index f2f7b625509..141a7d1ec63 100644
--- a/cpu/arm926ejs/at91/cpu.c
+++ b/cpu/arm926ejs/at91/cpu.c
@@ -22,18 +22,29 @@
*/
#include <common.h>
+#ifdef CONFIG_AT91_LEGACY
+#warning Your board is using legacy SoC access. Please update!
+#endif
+
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
-#ifndef AT91_MAIN_CLOCK
-#define AT91_MAIN_CLOCK 0
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
+/*
+ * The at91sam9260 has 4 GPBR (0-3), we'll use the last one, nr 3,
+ * to keep track of the bootcount.
+ */
+#define AT91_GPBR_BOOTCOUNT_REGISTER 3
+#define AT91_BOOTCOUNT_ADDRESS (AT91_GPBR + 4*AT91_GPBR_BOOTCOUNT_REGISTER)
+
int arch_cpu_init(void)
{
- return at91_clock_init(AT91_MAIN_CLOCK);
+ return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -41,7 +52,7 @@ int print_cpuinfo(void)
{
char buf[32];
- printf("CPU: %s\n", AT91_CPU_NAME);
+ printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
printf("Crystal frequency: %8s MHz\n",
strmhz(buf, get_main_clk_rate()));
printf("CPU clock : %8s MHz\n",
@@ -52,3 +63,30 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+/*
+ * Just as the mpc5xxx, we combine the BOOTCOUNT_MAGIC and boocount
+ * in one 32-bit register. This is done, as the AT91SAM9260 only has
+ * 4 GPBR.
+ */
+void bootcount_store (ulong a)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+
+ *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff);
+}
+
+ulong bootcount_load (void)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(AT91_BASE_SYS + AT91_BOOTCOUNT_ADDRESS);
+
+ if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+ return 0;
+ else
+ return (*save_addr & 0x0000ffff);
+}
+
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c
index be68f5958a0..0a315c49710 100644
--- a/cpu/arm926ejs/at91/led.c
+++ b/cpu/arm926ejs/at91/led.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S
index f11ebc67b37..559c35c9ee7 100644
--- a/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/cpu/arm926ejs/at91/lowlevel_init.S
@@ -27,15 +27,20 @@
*/
#include <config.h>
-#include <version.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_wdt.h>
-#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_rstc.h>
+#ifdef CONFIG_AT91_LEGACY
+#include <asm/arch/at91sam9_matrix.h>
+#endif
+#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
+#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
+#endif
_TEXT_BASE:
.word TEXT_BASE
@@ -75,7 +80,7 @@ POS1:
* - Check if the PLL is already initialized
* ----------------------------------------------------------------------------
*/
- ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
+ ldr r1, =(AT91_ASM_PMC_MCKR)
ldr r0, [r1]
and r0, r0, #3
cmp r0, #0
@@ -85,18 +90,18 @@ POS1:
* - Enable the Main Oscillator
* ---------------------------------------------------------------------------
*/
- ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
- ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
+ ldr r1, =(AT91_ASM_PMC_MOR)
+ ldr r2, =(AT91_ASM_PMC_SR)
/* Main oscillator Enable register PMC_MOR: */
ldr r0, =CONFIG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
- mov r4, #AT91_PMC_MOSCS
+ mov r4, #AT91_PMC_IXR_MOSCS
MOSCS_Loop:
ldr r3, [r2]
and r3, r4, r3
- cmp r3, #AT91_PMC_MOSCS
+ cmp r3, #AT91_PMC_IXR_MOSCS
bne MOSCS_Loop
/* ----------------------------------------------------------------------------
@@ -105,16 +110,16 @@ MOSCS_Loop:
* Setup PLLA
* ----------------------------------------------------------------------------
*/
- ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
+ ldr r1, =(AT91_ASM_PMC_PLLAR)
ldr r0, =CONFIG_SYS_PLLAR_VAL
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
- mov r4, #AT91_PMC_LOCKA
+ mov r4, #AT91_PMC_IXR_LOCKA
MOSCS_Loop1:
ldr r3, [r2]
and r3, r4, r3
- cmp r3, #AT91_PMC_LOCKA
+ cmp r3, #AT91_PMC_IXR_LOCKA
bne MOSCS_Loop1
/* ----------------------------------------------------------------------------
@@ -123,38 +128,37 @@ MOSCS_Loop1:
* - Switch on the Main Oscillator
* ----------------------------------------------------------------------------
*/
- ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
+ ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */
ldr r0, =CONFIG_SYS_MCKR1_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
- mov r4, #AT91_PMC_MCKRDY
+ mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop:
ldr r3, [r2]
and r3, r4, r3
- cmp r3, #AT91_PMC_MCKRDY
+ cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
ldr r0, =CONFIG_SYS_MCKR2_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
- mov r4, #AT91_PMC_MCKRDY
+ mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop1:
ldr r3, [r2]
and r3, r4, r3
- cmp r3, #AT91_PMC_MCKRDY
+ cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop1
-
PLL_setup_end:
/* ----------------------------------------------------------------------------
* - memory control configuration 2
* ----------------------------------------------------------------------------
*/
- ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
+ ldr r0, =(AT91_ASM_SDRAMC_TR)
ldr r1, [r0]
cmp r1, #0
bne SDRAM_setup_end
@@ -166,7 +170,6 @@ PLL_setup_end:
sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
-
2:
/* the address */
ldr r1, [r0], #4
@@ -183,60 +186,53 @@ SDRAM_setup_end:
.ltorg
SMRDATA:
- .word (AT91_BASE_SYS + AT91_WDT_MR)
+ .word AT91_ASM_WDT_MR
.word CONFIG_SYS_WDTC_WDMR_VAL
-
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
- .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
+ .word AT91_ASM_PIOD_PDR
.word CONFIG_SYS_PIOD_PDR_VAL1
- .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
+ .word AT91_ASM_PIOD_PUDR
.word CONFIG_SYS_PIOD_PPUDR_VAL
- .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
+ .word AT91_ASM_PIOD_ASR
.word CONFIG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|| defined(CONFIG_AT91SAM9G20)
- .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
+ .word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL1
- .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
+ .word AT91_ASM_PIOC_PUDR
.word CONFIG_SYS_PIOC_PPUDR_VAL
#endif
-
-#if defined(AT91_MATRIX_EBI0CSA)
- .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
- .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
-#else /* AT91_MATRIX_EBICSA */
- .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
+ .word AT91_ASM_MATRIX_CSA0
.word CONFIG_SYS_MATRIX_EBICSA_VAL
-#endif
/* flash */
- .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
+ .word AT91_ASM_SMC_MODE0
.word CONFIG_SYS_SMC0_MODE0_VAL
- .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
+ .word AT91_ASM_SMC_CYCLE0
.word CONFIG_SYS_SMC0_CYCLE0_VAL
- .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
+ .word AT91_ASM_SMC_PULSE0
.word CONFIG_SYS_SMC0_PULSE0_VAL
- .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
+ .word AT91_ASM_SMC_SETUP0
.word CONFIG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+ .word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
- .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
+ .word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL1
- .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
+ .word AT91_ASM_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
- .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
+ .word AT91_ASM_SDRAMC_MDR
.word CONFIG_SYS_SDRC_MDR_VAL
- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+ .word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL1
- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+ .word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL2
@@ -254,26 +250,25 @@ SMRDATA1:
.word CONFIG_SYS_SDRAM_VAL8
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL9
- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+ .word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL10
- .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+ .word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL11
- .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
+ .word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
.word AT91_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL12
/* User reset enable*/
- .word (AT91_BASE_SYS + AT91_RSTC_MR)
+ .word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
- .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
+ .word AT91_ASM_MATRIX_MCFG
.word 0x1FF
#endif
-
SMRDATA2:
.word 0
diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c
index f963e14eda8..1b67e77887f 100644
--- a/cpu/arm926ejs/at91/reset.c
+++ b/cpu/arm926ejs/at91/reset.c
@@ -32,10 +32,12 @@
*/
void reset_cpu(ulong ignored)
{
+ at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
+
/* this is the way Linux does it */
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
- AT91_RSTC_PROCRST |
- AT91_RSTC_PERRST);
+
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST,
+ &rstc->cr);
while (1);
/* Never reached */
diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c
index 7352b5c3379..d21eebfb4eb 100644
--- a/cpu/arm926ejs/at91/timer.c
+++ b/cpu/arm926ejs/at91/timer.c
@@ -35,8 +35,6 @@
* setting the 20 bit counter period to its maximum (0xfffff).
*/
#define TIMER_LOAD_VAL 0xfffff
-#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
-#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
static ulong timestamp;
static ulong lastinc;
@@ -61,14 +59,16 @@ static inline unsigned long long usec_to_tick(unsigned long long usec)
/* nothing really to do with interrupts, just starts up a counter. */
int timer_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
- at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+ writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
- at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
+ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
reset_timer_masked();
@@ -82,7 +82,9 @@ int timer_init(void)
*/
unsigned long long get_ticks(void)
{
- ulong now = READ_TIMER;
+ at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
+
+ ulong now = readl(&pit->piir);
if (now >= lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
@@ -96,7 +98,10 @@ unsigned long long get_ticks(void)
void reset_timer_masked(void)
{
/* reset time */
- lastinc = READ_TIMER; /* capture current incrementer value time */
+ at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
+
+ /* capture current incrementer value time */
+ lastinc = readl(&pit->piir);
timestamp = 0; /* start "advancing" time stamp from 0 */
}
diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile
new file mode 100644
index 00000000000..55c1e899be7
--- /dev/null
+++ b/cpu/arm926ejs/mx25/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = generic.o timer.o
+MX27OBJS = reset.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/mx25/generic.c b/cpu/arm926ejs/mx25/generic.c
new file mode 100644
index 00000000000..694841dd10e
--- /dev/null
+++ b/cpu/arm926ejs/mx25/generic.c
@@ -0,0 +1,263 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on mx27/generic.c:
+ * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx25-pinmux.h>
+#ifdef CONFIG_MXC_MMC
+#include <asm/arch/mxcmmc.h>
+#endif
+
+/*
+ * get the system pll clock in Hz
+ *
+ * mfi + mfn / (mfd +1)
+ * f = 2 * f_ref * --------------------
+ * pd + 1
+ */
+static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
+{
+ unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
+ & CCM_PLL_MFI_MASK;
+ unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+ & CCM_PLL_MFN_MASK;
+ unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
+ & CCM_PLL_MFD_MASK;
+ unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
+ & CCM_PLL_PD_MASK;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
+ (mfd + 1) * (pd + 1));
+}
+
+static ulong imx_get_mpllclk (void)
+{
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong fref = 24000000;
+
+ return imx_decode_pll (readl (&ccm->mpctl), fref);
+}
+
+ulong imx_get_armclk (void)
+{
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong cctl = readl (&ccm->cctl);
+ ulong fref = imx_get_mpllclk ();
+ ulong div;
+
+ if (cctl & CCM_CCTL_ARM_SRC)
+ fref = lldiv ((fref * 3), 4);
+
+ div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
+ & CCM_CCTL_ARM_DIV_MASK) + 1;
+
+ return lldiv (fref, div);
+}
+
+ulong imx_get_ahbclk (void)
+{
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong cctl = readl (&ccm->cctl);
+ ulong fref = imx_get_armclk ();
+ ulong div;
+
+ div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
+ & CCM_CCTL_AHB_DIV_MASK) + 1;
+
+ return lldiv (fref, div);
+}
+
+ulong imx_get_perclk (int clk)
+{
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong fref = imx_get_ahbclk ();
+ ulong div;
+
+ div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
+ div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
+
+ return lldiv (fref, div);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+ char buf[32];
+
+ printf ("CPU: Freescale i.MX25 at %s MHz\n\n",
+ strmhz (buf, imx_get_mpllclk ()));
+ return 0;
+}
+#endif
+
+int cpu_eth_init (bd_t * bis)
+{
+#if defined(CONFIG_FEC_MXC)
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ ulong val;
+
+ val = readl (&ccm->cgr0);
+ val |= (1 << 23);
+ writel (val, &ccm->cgr0);
+ return fecmxc_initialize (bis);
+#else
+ return 0;
+#endif
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init (bd_t * bis)
+{
+#ifdef CONFIG_MXC_MMC
+ return mxc_mmc_init (bis);
+#else
+ return 0;
+#endif
+}
+
+#ifdef CONFIG_MXC_UART
+void mx25_uart_init_pins (void)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 inpadctl;
+ u32 outpadctl;
+ u32 muxmode0;
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ muxmode0 = MX25_PIN_MUX_MODE (0);
+ /*
+ * set up input pins with hysteresis and 100K pull-ups
+ */
+ inpadctl = MX25_PIN_PAD_CTL_HYS
+ | MX25_PIN_PAD_CTL_PKE
+ | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
+
+ /*
+ * set up output pins with 100K pull-downs
+ * FIXME: need to revisit this
+ * PUE is ignored if PKE is not set
+ * so the right value here is likely
+ * 0x0 for no pull up/down
+ * or
+ * 0xc0 for 100k pull down
+ */
+ outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
+
+ /* UART1 */
+ /* rxd */
+ writel (muxmode0, &muxctl->pad_uart1_rxd);
+ writel (inpadctl, &padctl->pad_uart1_rxd);
+
+ /* txd */
+ writel (muxmode0, &muxctl->pad_uart1_txd);
+ writel (outpadctl, &padctl->pad_uart1_txd);
+
+ /* rts */
+ writel (muxmode0, &muxctl->pad_uart1_rts);
+ writel (outpadctl, &padctl->pad_uart1_rts);
+
+ /* cts */
+ writel (muxmode0, &muxctl->pad_uart1_cts);
+ writel (inpadctl, &padctl->pad_uart1_cts);
+}
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+void mx25_fec_init_pins (void)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 inpadctl_100kpd;
+ u32 inpadctl_22kpu;
+ u32 outpadctl;
+ u32 muxmode0;
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ muxmode0 = MX25_PIN_MUX_MODE (0);
+ inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
+ | MX25_PIN_PAD_CTL_PKE
+ | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
+ inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
+ | MX25_PIN_PAD_CTL_PKE
+ | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
+ /*
+ * set up output pins with 100K pull-downs
+ * FIXME: need to revisit this
+ * PUE is ignored if PKE is not set
+ * so the right value here is likely
+ * 0x0 for no pull
+ * or
+ * 0xc0 for 100k pull down
+ */
+ outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
+
+ /* FEC_TX_CLK */
+ writel (muxmode0, &muxctl->pad_fec_tx_clk);
+ writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
+
+ /* FEC_RX_DV */
+ writel (muxmode0, &muxctl->pad_fec_rx_dv);
+ writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
+
+ /* FEC_RDATA0 */
+ writel (muxmode0, &muxctl->pad_fec_rdata0);
+ writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
+
+ /* FEC_TDATA0 */
+ writel (muxmode0, &muxctl->pad_fec_tdata0);
+ writel (outpadctl, &padctl->pad_fec_tdata0);
+
+ /* FEC_TX_EN */
+ writel (muxmode0, &muxctl->pad_fec_tx_en);
+ writel (outpadctl, &padctl->pad_fec_tx_en);
+
+ /* FEC_MDC */
+ writel (muxmode0, &muxctl->pad_fec_mdc);
+ writel (outpadctl, &padctl->pad_fec_mdc);
+
+ /* FEC_MDIO */
+ writel (muxmode0, &muxctl->pad_fec_mdio);
+ writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
+
+ /* FEC_RDATA1 */
+ writel (muxmode0, &muxctl->pad_fec_rdata1);
+ writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
+
+ /* FEC_TDATA1 */
+ writel (muxmode0, &muxctl->pad_fec_tdata1);
+ writel (outpadctl, &padctl->pad_fec_tdata1);
+
+}
+#endif /* CONFIG_FEC_MXC */
diff --git a/cpu/arm926ejs/mx25/reset.c b/cpu/arm926ejs/mx25/reset.c
new file mode 100644
index 00000000000..1e33150eb9f
--- /dev/null
+++ b/cpu/arm926ejs/mx25/reset.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu (ulong ignored)
+{
+ struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+ /* Disable watchdog and set Time-Out field to 0 */
+ writel (0x00000000, &regs->wcr);
+
+ /* Write Service Sequence */
+ writel (0x00005555, &regs->wsr);
+ writel (0x0000AAAA, &regs->wsr);
+
+ /* Enable watchdog */
+ writel (WCR_WDE, &regs->wcr);
+
+ while (1) ;
+}
diff --git a/cpu/arm926ejs/mx25/timer.c b/cpu/arm926ejs/mx25/timer.c
new file mode 100644
index 00000000000..11d41a8bf9f
--- /dev/null
+++ b/cpu/arm926ejs/mx25/timer.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ * Add support for MX25
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+static ulong timestamp;
+static ulong lastinc;
+
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, CONFIG_MX25_CLK32);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ time *= CONFIG_MX25_CLK32;
+ do_div(time, CONFIG_SYS_HZ);
+ return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us = us * CONFIG_MX25_CLK32 + 999999;
+ do_div(us, 1000000);
+ return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
+ CONFIG_SYS_HZ)
+#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ do_div(tick, TICK_PER_TIME);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us += US_PER_TICK - 1;
+ do_div(us, US_PER_TICK);
+ return us;
+}
+#endif
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32KHz 32-bit timer overruns in 134217 seconds */
+int timer_init(void)
+{
+ int i;
+ struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
+ struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* setup GP Timer 1 */
+ writel(GPT_CTRL_SWR, &gpt->ctrl);
+
+ writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
+
+ for (i = 0; i < 100; i++)
+ writel(0, &gpt->ctrl); /* We have no udelay by now */
+ writel(0, &gpt->pre); /* prescaler = 1 */
+ /* Freerun Mode, 32KHz input */
+ writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
+ &gpt->ctrl);
+ writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
+ /* reset time */
+ /* capture current incrementer value time */
+ lastinc = readl(&gpt->counter);
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+ struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
+ ulong now = readl(&gpt->counter); /* current tick value */
+
+ if (now >= lastinc) {
+ /*
+ * normal mode (non roll)
+ * move stamp forward with absolut diff ticks
+ */
+ timestamp += (now - lastinc);
+ } else {
+ /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ }
+ lastinc = now;
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ /*
+ * get_ticks() returns a long long (64 bit), it wraps in
+ * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+ * 5 * 10^6 days - long enough.
+ */
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay (unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index da05c55fb53..30cf5447121 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -166,6 +166,11 @@ int print_cpuinfo (void)
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FEC_MXC)
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+ /* enable FEC clock */
+ writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+ writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
#else
return 0;
diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
index 4421b6a9901..3b81151f49c 100644
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -53,6 +53,27 @@
.globl _start
_start:
b reset
+#ifdef CONFIG_PRELOADER
+/* No exception handlers in preloader */
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+
+_hang:
+ .word do_hang
+/* pad to 64 byte boundary */
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -76,6 +97,7 @@ _irq:
_fiq:
.word fiq
+#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
@@ -150,7 +172,6 @@ relocate: /* relocate U-Boot to RAM */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
-
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
@@ -166,11 +187,14 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ sub sp, r0, #128 /* leave 32 words for abort-stack */
+#ifndef CONFIG_PRELOADER
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
+#endif /* CONFIG_PRELOADER */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, r0, #7 /* 8-byte align stack for ABI compliance */
@@ -179,6 +203,7 @@ clear_bss:
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
+#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
@@ -186,11 +211,16 @@ clbss_l:str r2, [r0] /* clear loop... */
bl coloured_LED_init
bl red_LED_on
+#endif /* CONFIG_PRELOADER */
ldr pc, _start_armboot
_start_armboot:
+#ifdef CONFIG_NAND_SPL
+ .word nand_boot
+#else
.word start_armboot
+#endif /* CONFIG_NAND_SPL */
/*
@@ -231,6 +261,7 @@ cpu_init_crit:
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+#ifndef CONFIG_PRELOADER
/*
*************************************************************************
*
@@ -332,10 +363,18 @@ cpu_init_crit:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
+#endif /* CONFIG_PRELOADER */
/*
* exception handlers
*/
+#ifdef CONFIG_PRELOADER
+ .align 5
+do_hang:
+ ldr sp, _TEXT_BASE /* switch to abort stack */
+1:
+ bl 1b /* hang and never return */
+#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@@ -398,3 +437,4 @@ fiq:
bl do_fiq
#endif
+#endif /* CONFIG_PRELOADER */
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-15 11:20:22 +0000