diff options
Diffstat (limited to 'cpu/mpc8260/pci.c')
| -rw-r--r-- | cpu/mpc8260/pci.c | 100 |
1 files changed, 50 insertions, 50 deletions
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 82303644b2b..378d6c573a2 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -70,23 +70,23 @@ DECLARE_GLOBAL_DATA_PTR; * This window is set up using the first set of Inbound ATU registers */ -#ifndef CFG_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ #else -#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL #endif -#ifndef CFG_PCI_SLV_MEM_BUS +#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ #else -#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS +#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS #endif -#ifndef CFG_PICMR0_MASK_ATTRIB +#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ PICMR_PREFETCH_EN) #else -#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB +#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB #endif /* @@ -97,29 +97,29 @@ DECLARE_GLOBAL_DATA_PTR; */ /* PCIBR0 */ -#ifndef CFG_PCI_MSTR0_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ #else -#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL +#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL #endif -#ifndef CFG_PCIMSK0_MASK +#ifndef CONFIG_SYS_PCIMSK0_MASK #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ #else -#define PCIMSK0_MASK CFG_PCIMSK0_MASK +#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK #endif /* PCIBR1 */ -#ifndef CFG_PCI_MSTR1_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ #else -#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL +#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL #endif -#ifndef CFG_PCIMSK1_MASK +#ifndef CONFIG_SYS_PCIMSK1_MASK #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ #else -#define PCIMSK1_MASK CFG_PCIMSK1_MASK +#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK #endif /* @@ -128,34 +128,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_MEM_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ #else -#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL #endif -#ifndef CFG_PCI_MSTR_MEM_BUS +#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ #else -#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS +#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS #endif -#ifndef CFG_CPU_PCI_MEM_START +#ifndef CONFIG_SYS_CPU_PCI_MEM_START #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL #else -#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START +#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START #endif -#ifndef CFG_PCI_MSTR_MEM_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ #else -#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE +#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE #endif -#ifndef CFG_POCMR0_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) #else -#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB +#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB #endif /* @@ -164,34 +164,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_MEMIO_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ #else -#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL +#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL #endif -#ifndef CFG_PCI_MSTR_MEMIO_BUS +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ #else -#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS +#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS #endif -#ifndef CFG_CPU_PCI_MEMIO_START +#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL #else -#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START +#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START #endif -#ifndef CFG_PCI_MSTR_MEMIO_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ #else -#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE +#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE #endif -#ifndef CFG_POCMR1_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) #else -#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB +#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB #endif /* @@ -200,34 +200,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_IO_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ #else -#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL +#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL #endif -#ifndef CFG_PCI_MSTR_IO_BUS +#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ #else -#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS +#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS #endif -#ifndef CFG_CPU_PCI_IO_START +#ifndef CONFIG_SYS_CPU_PCI_IO_START #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL #else -#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START +#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START #endif -#ifndef CFG_PCI_MSTR_IO_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ #else -#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE +#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE #endif -#ifndef CFG_POCMR2_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) #else -#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB +#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB #endif /* PCI bus configuration registers. @@ -245,11 +245,11 @@ void pci_mpc8250_init (struct pci_controller *hose) { u16 tempShort; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; pci_dev_t host_devno = PCI_BDF (0, 0, 0); - pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, - CFG_IMMR + PCI_CFG_DATA_REG); + pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, + CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); /* * Setting required to enable local bus for PCI (SIUMCR [LBPC]). @@ -413,8 +413,8 @@ void pci_mpc8250_init (struct pci_controller *hose) gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); #else pci_set_region (hose->regions + 0, - CFG_SDRAM_BASE, - CFG_SDRAM_BASE, + CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); #endif |